TI OpenMP-DSP
Introduction
Devices Supported
Building an OpenMP Application
Build Prerequisites
Building Applications within CCS
Building Applications Using Makefiles
Running applications within CCS
Heap Management API
Heaps in Shared Memory (DDR or MSMC)
Heap Initialization API
Dynamic Memory Management APIs
Heap in Local Memory (L2SRAM)
Heap Initialization API
Dynamic Memory Management APIs
Configuring the Runtime
Configuring Cores
Configuring Memory Regions
Configuring the Heap
Configuring Reset and Startup functions
Platform file
Device Name
CPU Clock Frequency
Memory Regions
OpenMP Acclerator Model
Device Constructs supported
#pragma omp target
#pragma omp declare target
#pragma omp target data
#pragma omp target update
OpenCL Mode
Dispatching OpenMP with OpenCL
Structure of an OpenCL + OpenMP Application
Host Code
Kernel
C Function with OpenMP regions
Makefile
Guidelines for writing OpenCL + OpenMP applications
OpenMP 3.0 Implementation-Defined Behaviors
Resource Usage
Reducing Memory Footprint in L2SRAM
Stacks in MSMCSRAM
Integrating Applications Using QMSS
Migration Guide
Key Differences between OpenMP Runtime 1.x and 2.x
Porting an OpenMP Runtime 1.x Application to 2.x
Defect Fixes
Known Issues
Definitions
Disclaimer
Important Notice
TI OpenMP-DSP
TI OpenMP-DSP Home
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Defect Fixes
Defect Fixes
ΒΆ
Configuring the OpenMP runtime in RTSC mode to use a subset of the cores starting with a non zero master core index (OpenMP.masterCoreIdx) does not work as expected. This is fixed in OpenMP Runtime version 2.01.17.02.
