UDMACC26XX.h

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/*
 * Copyright (c) 2015, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
#ifndef ti_drivers_UDMACC26XX__include
#define ti_drivers_UDMACC26XX__include

#ifdef __cplusplus
extern "C" {
#endif

#include <stdint.h>
#include <stdbool.h>
#include "driverlib/udma.h"
#include "inc/hw_types.h"

#include <ti/sysbios/family/arm/cc26xx/Power.h>
#include <ti/sysbios/family/arm/cc26xx/PowerCC2650.h>

#ifndef UDMACC26XX_CONFIG_BASE
   #define UDMACC26XX_CONFIG_BASE 0x20000400
#endif

#if(UDMACC26XX_CONFIG_BASE & 0x3FF)
    #error "Base address for DMA control table 'UDMACC26XX_CONFIG_BASE' must be 1024 bytes aligned."
#endif

#if defined(__IAR_SYSTEMS_ICC__)
#define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \
__no_init static volatile tDMAControlTable ENTRY_NAME @ UDMACC26XX_CONFIG_BASE + CHANNEL_INDEX * sizeof(tDMAControlTable)
#endif
#if defined(__TI_COMPILER_VERSION__)
#define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \
PRAGMA(LOCATION( ENTRY_NAME , UDMACC26XX_CONFIG_BASE + CHANNEL_INDEX * sizeof(tDMAControlTable) );)\
static volatile tDMAControlTable ENTRY_NAME
#define PRAGMA(x) _Pragma(#x)
#endif

#define UDMACC26XX_SET_TRANSFER_SIZE(SIZE)    (((SIZE - 1) << UDMA_XFER_SIZE_S) & UDMA_XFER_SIZE_M)

#define UDMACC26XX_GET_TRANSFER_SIZE(CONTROL) (((CONTROL & UDMA_XFER_SIZE_M) >> UDMA_XFER_SIZE_S) + 1)

typedef struct UDMACC26XX_Object {
    bool             isOpen;           
    ti_sysbios_family_arm_m3_Hwi_Struct hwi;  
} UDMACC26XX_Object;

typedef struct UDMACC26XX_HWAttrs {
    uint32_t        baseAddr;    
    Power_Resource  powerMngrId; 
    uint8_t         intNum;      
    uint8_t         intPriority;
} UDMACC26XX_HWAttrs;

typedef struct UDMACC26XX_Config {
    void              *object;            
    void const        *hwAttrs;           
} UDMACC26XX_Config;

typedef struct UDMACC26XX_Config      *UDMACC26XX_Handle;

/* Extern'd hwiIntFxn */
extern void UDMACC26XX_hwiIntFxn(UArg callbacks);

__STATIC_INLINE void UDMACC26XX_init(UDMACC26XX_Handle handle)
{
    UDMACC26XX_Object           *object;

    /* Get the pointer to the object */
    object = handle->object;

    /* mark the module as available */
    object->isOpen = FALSE;
}

extern UDMACC26XX_Handle UDMACC26XX_open();

__STATIC_INLINE void UDMACC26XX_channelEnable(UDMACC26XX_Handle handle, uint32_t channelBitMask)
{
    UDMACC26XX_HWAttrs const *hwAttrs;

    /* Get the pointer to the hwAttrs */
    hwAttrs = handle->hwAttrs;

    /* Enable DMA channel */
    HWREG(hwAttrs->baseAddr + UDMA_O_SETCHANNELEN) = channelBitMask;
}

__STATIC_INLINE bool UDMACC26XX_channelDone(UDMACC26XX_Handle handle, uint32_t channelBitMask)
{
    UDMACC26XX_HWAttrs const *hwAttrs;

    /* Get the pointer to the hwAttrs */
    hwAttrs = handle->hwAttrs;

    /* Check if REQDONE is set for a specific channel */
    return (uDMAIntStatus(hwAttrs->baseAddr) & channelBitMask) ? true : false;
}

__STATIC_INLINE void UDMACC26XX_clearInterrupt(UDMACC26XX_Handle handle, uint32_t channelBitMask)
{
    UDMACC26XX_HWAttrs const *hwAttrs;

    /* Get the pointer to the hwAttrs and object */
    hwAttrs = handle->hwAttrs;

    /* Clear UDMA done interrupt */
    uDMAIntClear(hwAttrs->baseAddr, channelBitMask);
}

__STATIC_INLINE void UDMACC26XX_channelDisable(UDMACC26XX_Handle handle, uint32_t channelBitMask)
{
    UDMACC26XX_HWAttrs const *hwAttrs;

    /* Get the pointer to the hwAttrs and object */
    hwAttrs = handle->hwAttrs;

    /* disable DMA channel */
    uDMAChannelDisable(hwAttrs->baseAddr, channelBitMask);
}

extern void UDMACC26XX_close(UDMACC26XX_Handle handle);

#ifdef __cplusplus
}
#endif

#endif /* ti_drivers_UDMACC26XX__include */