IPC API  3.40.00.06
power_rsc_table_vayu_dsp.h
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1 /*
2  * Copyright (c) 2015, Texas Instruments Incorporated
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  *
9  * * Redistributions of source code must retain the above copyright
10  * notice, this list of conditions and the following disclaimer.
11  *
12  * * Redistributions in binary form must reproduce the above copyright
13  * notice, this list of conditions and the following disclaimer in the
14  * documentation and/or other materials provided with the distribution.
15  *
16  * * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 /*
34  * ======== power_rsc_table_vayu_dsp.h ========
35  *
36  * Define the resource table entries for all DSP cores. This adds
37  * an entry on top of the default resource table for L2 internal memory,
38  * in order to accomodate for a silicon bug workaround.
39  *
40  */
41 
42 #ifndef _POWER_RSC_TABLE_VAYU_DSP_H_
43 #define _POWER_RSC_TABLE_VAYU_DSP_H_
44 
45 #include <ti/ipc/remoteproc/rsc_types.h>
46 
47 /* DSP Memory Map */
48 #define L4_DRA7XX_BASE 0x4A000000
49 
50 #define L4_PERIPHERAL_L4CFG (L4_DRA7XX_BASE)
51 #define DSP_PERIPHERAL_L4CFG 0x4A000000
52 
53 #define L4_PERIPHERAL_L4PER1 0x48000000
54 #define DSP_PERIPHERAL_L4PER1 0x48000000
55 
56 #define L4_PERIPHERAL_L4PER2 0x48400000
57 #define DSP_PERIPHERAL_L4PER2 0x48400000
58 
59 #define L4_PERIPHERAL_L4PER3 0x48800000
60 #define DSP_PERIPHERAL_L4PER3 0x48800000
61 
62 #define L4_PERIPHERAL_L4EMU 0x54000000
63 #define DSP_PERIPHERAL_L4EMU 0x54000000
64 
65 #define L3_PERIPHERAL_DMM 0x4E000000
66 #define DSP_PERIPHERAL_DMM 0x4E000000
67 
68 #define L3_TILER_MODE_0_1 0x60000000
69 #define DSP_TILER_MODE_0_1 0x60000000
70 
71 #define L3_TILER_MODE_2 0x70000000
72 #define DSP_TILER_MODE_2 0x70000000
73 
74 #define L3_TILER_MODE_3 0x78000000
75 #define DSP_TILER_MODE_3 0x78000000
76 
77 #define DSP_MEM_TEXT 0x95000000
78 /* Co-locate alongside TILER region for easier flushing */
79 #define DSP_MEM_IOBUFS 0x80000000
80 #define DSP_MEM_DATA 0x95100000
81 #define DSP_MEM_HEAP 0x95200000
82 #define DSP_INTMEM_L2 0x800000
83 #if defined (DSP_1)
84 #define PHYS_MEM_L2_RAM 0x40800000
85 #elif defined (DSP_2)
86 #define PHYS_MEM_L2_RAM 0x41000000
87 #endif
88 #define DSP_MEM_L2_RAM_SIZE 0x00040000
89 
90 #define DSP_MEM_IPC_DATA 0x9F000000
91 #define DSP_MEM_IPC_VRING 0xA0000000
92 #define DSP_MEM_RPMSG_VRING0 0xA0000000
93 #define DSP_MEM_RPMSG_VRING1 0xA0004000
94 #define DSP_MEM_VRING_BUFS0 0xA0040000
95 #define DSP_MEM_VRING_BUFS1 0xA0080000
96 
97 #define DSP_MEM_IPC_VRING_SIZE SZ_1M
98 #define DSP_MEM_IPC_DATA_SIZE SZ_1M
99 #define DSP_MEM_TEXT_SIZE SZ_1M
100 #define DSP_MEM_DATA_SIZE SZ_1M
101 #define DSP_MEM_HEAP_SIZE (SZ_1M * 3)
102 #define DSP_MEM_IOBUFS_SIZE (SZ_1M * 90)
103 
104 /*
105  * Assign fixed RAM addresses to facilitate a fixed MMU table.
106  */
107 /* See CMA BASE addresses in Linux side: arch/arm/mach-omap2/remoteproc.c */
108 #if defined (DSP_1)
109 #define PHYS_MEM_IPC_VRING 0x99000000
110 #elif defined (DSP_2)
111 #define PHYS_MEM_IPC_VRING 0x9F000000
112 #endif
113 
114 /* Need to be identical to that of IPU */
115 #define PHYS_MEM_IOBUFS 0xBA300000
116 
117 /*
118  * Sizes of the virtqueues (expressed in number of buffers supported,
119  * and must be power of 2)
120  */
121 #define DSP_RPMSG_VQ0_SIZE 256
122 #define DSP_RPMSG_VQ1_SIZE 256
123 
124 /* flip up bits whose indices represent features we support */
125 #define RPMSG_DSP_C0_FEATURES 1
126 
127 struct my_resource_table {
128  struct resource_table base;
129 
130  UInt32 offset[18]; /* Should match 'num' in actual definition */
131 
132  /* rpmsg vdev entry */
133  struct fw_rsc_vdev rpmsg_vdev;
134  struct fw_rsc_vdev_vring rpmsg_vring0;
135  struct fw_rsc_vdev_vring rpmsg_vring1;
136 
137  /* text carveout entry */
138  struct fw_rsc_carveout text_cout;
139 
140  /* data carveout entry */
141  struct fw_rsc_carveout data_cout;
142 
143  /* heap carveout entry */
144  struct fw_rsc_carveout heap_cout;
145 
146  /* ipcdata carveout entry */
147  struct fw_rsc_carveout ipcdata_cout;
148 
149  /* trace entry */
150  struct fw_rsc_trace trace;
151 
152  /* devmem entry */
153  struct fw_rsc_devmem devmem0;
154 
155  /* devmem entry */
156  struct fw_rsc_devmem devmem1;
157 
158  /* devmem entry */
159  struct fw_rsc_devmem devmem2;
160 
161  /* devmem entry */
162  struct fw_rsc_devmem devmem3;
163 
164  /* devmem entry */
165  struct fw_rsc_devmem devmem4;
166 
167  /* devmem entry */
168  struct fw_rsc_devmem devmem5;
169 
170  /* devmem entry */
171  struct fw_rsc_devmem devmem6;
172 
173  /* devmem entry */
174  struct fw_rsc_devmem devmem7;
175 
176  /* devmem entry */
177  struct fw_rsc_devmem devmem8;
178 
179  /* devmem entry */
180  struct fw_rsc_devmem devmem9;
181 
182  /* devmem entry */
183  struct fw_rsc_devmem devmem10;
184 
185  /* L2 intmem entry */
186  struct fw_rsc_intmem l2_intmem;
187 };
188 
190 #define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A
191 
192 #pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")
193 #pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)
194 
196  1, /* we're the first version that implements this */
197  18, /* number of entries in the table */
198  0, 0, /* reserved, must be zero */
199  /* offsets to entries */
200  {
201  offsetof(struct my_resource_table, rpmsg_vdev),
202  offsetof(struct my_resource_table, text_cout),
203  offsetof(struct my_resource_table, data_cout),
204  offsetof(struct my_resource_table, heap_cout),
205  offsetof(struct my_resource_table, ipcdata_cout),
206  offsetof(struct my_resource_table, trace),
207  offsetof(struct my_resource_table, devmem0),
208  offsetof(struct my_resource_table, devmem1),
209  offsetof(struct my_resource_table, devmem2),
210  offsetof(struct my_resource_table, devmem3),
211  offsetof(struct my_resource_table, devmem4),
212  offsetof(struct my_resource_table, devmem5),
213  offsetof(struct my_resource_table, devmem6),
214  offsetof(struct my_resource_table, devmem7),
215  offsetof(struct my_resource_table, devmem8),
216  offsetof(struct my_resource_table, devmem9),
217  offsetof(struct my_resource_table, devmem10),
218  offsetof(struct my_resource_table, l2_intmem),
219  },
220 
221  /* rpmsg vdev entry */
222  {
223  TYPE_VDEV, VIRTIO_ID_RPMSG, 0,
224  RPMSG_DSP_C0_FEATURES, 0, 0, 0, 2, { 0, 0 },
225  /* no config data */
226  },
227  /* the two vrings */
228  { DSP_MEM_RPMSG_VRING0, 4096, DSP_RPMSG_VQ0_SIZE, 1, 0 },
229  { DSP_MEM_RPMSG_VRING1, 4096, DSP_RPMSG_VQ1_SIZE, 2, 0 },
230 
231  {
232  TYPE_CARVEOUT,
233  DSP_MEM_TEXT, 0,
234  DSP_MEM_TEXT_SIZE, 0, 0, "DSP_MEM_TEXT",
235  },
236 
237  {
238  TYPE_CARVEOUT,
239  DSP_MEM_DATA, 0,
240  DSP_MEM_DATA_SIZE, 0, 0, "DSP_MEM_DATA",
241  },
242 
243  {
244  TYPE_CARVEOUT,
245  DSP_MEM_HEAP, 0,
246  DSP_MEM_HEAP_SIZE, 0, 0, "DSP_MEM_HEAP",
247  },
248 
249  {
250  TYPE_CARVEOUT,
251  DSP_MEM_IPC_DATA, 0,
252  DSP_MEM_IPC_DATA_SIZE, 0, 0, "DSP_MEM_IPC_DATA",
253  },
254 
255  {
256  TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:dsp",
257  },
258 
259  {
260  TYPE_DEVMEM,
262  DSP_MEM_IPC_VRING_SIZE, 0, 0, "DSP_MEM_IPC_VRING",
263  },
264 
265  {
266  TYPE_DEVMEM,
268  DSP_MEM_IOBUFS_SIZE, 0, 0, "DSP_MEM_IOBUFS",
269  },
270 
271  {
272  TYPE_DEVMEM,
274  SZ_256M, 0, 0, "DSP_TILER_MODE_0_1",
275  },
276 
277  {
278  TYPE_DEVMEM,
280  SZ_128M, 0, 0, "DSP_TILER_MODE_2",
281  },
282 
283  {
284  TYPE_DEVMEM,
286  SZ_128M, 0, 0, "DSP_TILER_MODE_3",
287  },
288 
289  {
290  TYPE_DEVMEM,
292  SZ_16M, 0, 0, "DSP_PERIPHERAL_L4CFG",
293  },
294 
295  {
296  TYPE_DEVMEM,
298  SZ_2M, 0, 0, "DSP_PERIPHERAL_L4PER1",
299  },
300 
301  {
302  TYPE_DEVMEM,
304  SZ_4M, 0, 0, "DSP_PERIPHERAL_L4PER2",
305  },
306 
307  {
308  TYPE_DEVMEM,
310  SZ_8M, 0, 0, "DSP_PERIPHERAL_L4PER3",
311  },
312 
313  {
314  TYPE_DEVMEM,
316  SZ_16M, 0, 0, "DSP_PERIPHERAL_L4EMU",
317  },
318 
319  {
320  TYPE_DEVMEM,
322  SZ_1M, 0, 0, "DSP_PERIPHERAL_DMM",
323  },
324 
325  {
326  TYPE_INTMEM, 1,
327  DSP_INTMEM_L2, PHYS_MEM_L2_RAM,
328  DSP_MEM_L2_RAM_SIZE, 0, "DSP_MEM_L2_RAM",
329  },
330 };
331 
332 #endif /* _POWER_RSC_TABLE_VAYU_DSP_H_ */
#define PHYS_MEM_IOBUFS
Definition: power_rsc_table_vayu_dsp.h:115
#define DSP_TILER_MODE_0_1
Definition: power_rsc_table_vayu_dsp.h:69
struct fw_rsc_carveout data_cout
Definition: gatempapp_rsc_table_vayu_dsp.h:138
Definition: gatempapp_rsc_table_vayu_dsp.h:124
struct my_resource_table ti_ipc_remoteproc_ResourceTable
Definition: power_rsc_table_vayu_dsp.h:195
struct fw_rsc_carveout ipcdata_cout
Definition: gatempapp_rsc_table_vayu_dsp.h:144
#define DSP_MEM_IPC_DATA_SIZE
Definition: power_rsc_table_vayu_dsp.h:98
#define DSP_MEM_IOBUFS_SIZE
Definition: power_rsc_table_vayu_dsp.h:102
struct fw_rsc_carveout text_cout
Definition: gatempapp_rsc_table_vayu_dsp.h:135
#define L4_PERIPHERAL_L4PER1
Definition: power_rsc_table_vayu_dsp.h:53
#define DSP_PERIPHERAL_L4PER2
Definition: power_rsc_table_vayu_dsp.h:57
#define DSP_MEM_HEAP
Definition: power_rsc_table_vayu_dsp.h:81
#define DSP_MEM_IPC_VRING
Definition: power_rsc_table_vayu_dsp.h:91
#define L3_TILER_MODE_0_1
Definition: power_rsc_table_vayu_dsp.h:68
#define DSP_RPMSG_VQ1_SIZE
Definition: power_rsc_table_vayu_dsp.h:122
#define DSP_MEM_RPMSG_VRING1
Definition: power_rsc_table_vayu_dsp.h:93
#define DSP_MEM_RPMSG_VRING0
Definition: power_rsc_table_vayu_dsp.h:92
#define L3_TILER_MODE_3
Definition: power_rsc_table_vayu_dsp.h:74
#define L3_TILER_MODE_2
Definition: power_rsc_table_vayu_dsp.h:71
#define DSP_INTMEM_L2
Definition: power_rsc_table_vayu_dsp.h:82
struct fw_rsc_devmem devmem2
Definition: gatempapp_rsc_table_vayu_dsp.h:156
#define DSP_MEM_TEXT_SIZE
Definition: power_rsc_table_vayu_dsp.h:99
#define RPMSG_DSP_C0_FEATURES
Definition: power_rsc_table_vayu_dsp.h:125
struct fw_rsc_devmem devmem6
Definition: gatempapp_rsc_table_vayu_dsp.h:168
struct fw_rsc_intmem l2_intmem
Definition: power_rsc_table_vayu_dsp.h:186
#define DSP_MEM_DATA
Definition: power_rsc_table_vayu_dsp.h:80
#define DSP_PERIPHERAL_DMM
Definition: power_rsc_table_vayu_dsp.h:66
#define DSP_PERIPHERAL_L4CFG
Definition: power_rsc_table_vayu_dsp.h:51
#define DSP_MEM_IOBUFS
Definition: power_rsc_table_vayu_dsp.h:79
#define DSP_PERIPHERAL_L4PER3
Definition: power_rsc_table_vayu_dsp.h:60
#define L4_PERIPHERAL_L4CFG
Definition: power_rsc_table_vayu_dsp.h:50
#define DSP_MEM_TEXT
Definition: power_rsc_table_vayu_dsp.h:77
#define DSP_PERIPHERAL_L4PER1
Definition: power_rsc_table_vayu_dsp.h:54
struct fw_rsc_devmem devmem10
Definition: gatempapp_rsc_table_vayu_dsp.h:180
#define PHYS_MEM_IPC_VRING
Definition: gatempapp_rsc_table_vayu_dsp.h:109
#define DSP_MEM_IPC_VRING_SIZE
Definition: power_rsc_table_vayu_dsp.h:97
#define DSP_MEM_IPC_DATA
Definition: power_rsc_table_vayu_dsp.h:90
struct fw_rsc_carveout heap_cout
Definition: gatempapp_rsc_table_vayu_dsp.h:141
#define DSP_MEM_L2_RAM_SIZE
Definition: power_rsc_table_vayu_dsp.h:88
#define L4_PERIPHERAL_L4PER2
Definition: power_rsc_table_vayu_dsp.h:56
struct fw_rsc_devmem devmem0
Definition: gatempapp_rsc_table_vayu_dsp.h:150
#define L4_PERIPHERAL_L4EMU
Definition: power_rsc_table_vayu_dsp.h:62
struct fw_rsc_devmem devmem7
Definition: gatempapp_rsc_table_vayu_dsp.h:171
struct fw_rsc_devmem devmem5
Definition: gatempapp_rsc_table_vayu_dsp.h:165
char ti_trace_SysMin_Module_State_0_outbuf__A
#define DSP_RPMSG_VQ0_SIZE
Definition: power_rsc_table_vayu_dsp.h:121
struct fw_rsc_devmem devmem4
Definition: gatempapp_rsc_table_vayu_dsp.h:162
#define TRACEBUFADDR
Definition: power_rsc_table_vayu_dsp.h:190
struct fw_rsc_devmem devmem1
Definition: gatempapp_rsc_table_vayu_dsp.h:153
#define L3_PERIPHERAL_DMM
Definition: power_rsc_table_vayu_dsp.h:65
#define DSP_TILER_MODE_2
Definition: power_rsc_table_vayu_dsp.h:72
#define DSP_MEM_HEAP_SIZE
Definition: power_rsc_table_vayu_dsp.h:101
UInt32 offset[19]
Definition: gatempapp_rsc_table_vayu_dsp.h:127
struct fw_rsc_devmem devmem9
Definition: gatempapp_rsc_table_vayu_dsp.h:177
#define DSP_MEM_DATA_SIZE
Definition: power_rsc_table_vayu_dsp.h:100
struct fw_rsc_trace trace
Definition: gatempapp_rsc_table_vayu_dsp.h:147
struct fw_rsc_devmem devmem3
Definition: gatempapp_rsc_table_vayu_dsp.h:159
#define DSP_TILER_MODE_3
Definition: power_rsc_table_vayu_dsp.h:75
struct fw_rsc_vdev rpmsg_vdev
Definition: gatempapp_rsc_table_vayu_dsp.h:130
#define L4_PERIPHERAL_L4PER3
Definition: power_rsc_table_vayu_dsp.h:59
struct fw_rsc_devmem devmem8
Definition: gatempapp_rsc_table_vayu_dsp.h:174
#define DSP_PERIPHERAL_L4EMU
Definition: power_rsc_table_vayu_dsp.h:63
Copyright 2015, Texas Instruments Incorporated