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This guide also provides detailed information regarding software elements and software infrastructure to allow developers to start creating applications.h]j†ubeubaubj)r”}r•(h\X™`Migration Guide `__: Provides migration information for applications built on top of the Processor SDK for RTOS. h]j\hchdhejhg}r–(hi]hj]hk]hl]ho]uhqNhrhhs]r—h›)r˜}r™(h\X˜`Migration Guide `__: Provides migration information for applications built on top of the Processor SDK for RTOS.h]j”hchdhehŸhg}rš(hi]hj]hk]hl]ho]uhqKBhs]r›(h´)rœ}r(h\X;`Migration Guide `__hg}rž(UnameXMigration Guideh¸X%Release_Specific.html#migration-guidehl]hk]hi]hj]ho]uh]j˜hs]rŸh|XMigration Guider …r¡}r¢(h\Uh]jœubaheh¾ubh|X]: Provides migration information for applications built on top of the Processor SDK for RTOS.r£…r¤}r¥(h\X]: Provides migration information for applications built on top of the Processor SDK for RTOS.h]j˜ubeubaubeubhÐ)r¦}r§(h\Uh]hÛhchdhehÓhg}r¨(hi]hj]hk]hl]ho]uhqKFhrhhs]r©hÖ)rª}r«(h\UhÙKh]j¦hchdhehqhg}r¬(hi]hj]hk]hl]ho]uhqKhrhhs]ubaubeubh_h^)r­}r®(h\Uh]hahchdhehfhg}r¯(hi]hj]hk]hl]r°Udevice-driversr±aho]r²h7auhqM%hrhhs]r³(hu)r´}rµ(h\XDevice Driversr¶h]j­hchdhehyhg}r·(hi]hj]hk]hl]ho]uhqM%hrhhs]r¸h|XDevice Driversr¹…rº}r»(h\j¶h]j´ubaubhê)r¼}r½(h\XHHow do I find out if a driver is supported in the package for my device?r¾h]j­hchdhehîhg}r¿(hl]rÀUGhow-do-i-find-out-if-a-driver-is-supported-in-the-package-for-my-devicerÁahk]hi]hj]ho]rÂh`__ corresponding to your release.h]j­hchdhehŸhg}rÉ(hi]hj]hk]hl]ho]uhqM+hrhhs]rÊ(h|XRFor all SoC and board-specific driver support, we recommend that you refer to the rË…rÌ}rÍ(h\XRFor all SoC and board-specific driver support, we recommend that you refer to the h]jÇubh´)rÎ}rÏ(h\X=`Release Notes `__hg}rÐ(UnameX Release Notesh¸X)Release_Specific.html#supported-platformshl]hk]hi]hj]ho]uh]jÇhs]rÑh|X Release NotesrÒ…rÓ}rÔ(h\Uh]jÎubaheh¾ubh|X corresponding to your release.rÕ…rÖ}r×(h\X corresponding to your release.h]jÇubeubh›)rØ}rÙ(h\X¼If you need further details for driver support on all cores on heterogeneous multi-core devices, please reach out to the engineering team using `E2E forums `__.h]j­hchdhehŸhg}rÚ(hi]hj]hk]hl]ho]uhqM/hrhhs]rÛ(h|XIf you need further details for driver support on all cores on heterogeneous multi-core devices, please reach out to the engineering team using rÜ…rÝ}rÞ(h\XIf you need further details for driver support on all cores on heterogeneous multi-core devices, please reach out to the engineering team using h]jØubh´)rß}rà(h\X+`E2E forums `__hg}rá(UnameX E2E forumsh¸Xhttp://e2e.ti.com/support/hl]hk]hi]hj]ho]uh]jØhs]râh|X E2E forumsrã…rä}rå(h\Uh]jßubaheh¾ubh|X.…ræ}rç(h\X.h]jØubeubhê)rè}ré(h\X5Where can I find example projects for device drivers?rêh]j­hchdhehîhg}rë(hl]rìU4where-can-i-find-example-projects-for-device-driversríahk]hi]hj]ho]rîhJauhqNhrhhs]rïh|X5Where can I find example projects for device drivers?rð…rñ}rò(h\jêh]jèubaubh›)ró}rô(h\X—The PDK package in processor SDK RTOS does not contain pre-canned CCS projects for driver examples. But it does provide scripts to set up the development environment and create the example CCS projects based on that setup. This allows the SDK the flexibility to create CCS projects based on the user-specific host setup. In order to create the example projects, users can follow the sequence provided below:rõh]j­hchdhehŸhg}rö(hi]hj]hk]hl]ho]uhqM6hrhhs]r÷h|X—The PDK package in processor SDK RTOS does not contain pre-canned CCS projects for driver examples. But it does provide scripts to set up the development environment and create the example CCS projects based on that setup. This allows the SDK the flexibility to create CCS projects based on the user-specific host setup. In order to create the example projects, users can follow the sequence provided below:rø…rù}rú(h\jõh]jóubaubcdocutils.nodes enumerated_list rû)rü}rý(h\Uh]j­hchdheUenumerated_listrþhg}rÿ(UsuffixrU.hl]hk]hi]UprefixrUhj]ho]UenumtyperUarabicruhqM=hrhhs]r(j)r}r(h\X~Users are required to setup their development environment using `Processor SDK RTOS Setup `__h]jühchdhejhg}r(hi]hj]hk]hl]ho]uhqNhrhhs]rh›)r }r (h\X~Users are required to setup their development environment using `Processor SDK RTOS Setup `__h]jhchdhehŸhg}r (hi]hj]hk]hl]ho]uhqM=hs]r (h|X@Users are required to setup their development environment using r …r}r(h\X@Users are required to setup their development environment using h]j ubh´)r}r(h\X>`Processor SDK RTOS Setup `__hg}r(UnameXProcessor SDK RTOS Setuph¸XOverview.html#setup-environmenthl]hk]hi]hj]ho]uh]j hs]rh|XProcessor SDK RTOS Setupr…r}r(h\Uh]jubaheh¾ubeubaubj)r}r(h\XsSetup the PDK build environment `PDK Setup `__.h]jühchdhejhg}r(hi]hj]hk]hl]ho]uhqNhrhhs]rh›)r}r(h\XsSetup the PDK build environment `PDK Setup `__.h]jhchdhehŸhg}r(hi]hj]hk]hl]ho]uhqM?hs]r(h|X Setup the PDK build environment r…r }r!(h\X Setup the PDK build environment h]jubh´)r"}r#(h\XR`PDK Setup `__hg}r$(UnameX PDK Setuph¸XBHow_to_Guides.html#building-pdk-using-gmake-in-windows-environmenthl]hk]hi]hj]ho]uh]jhs]r%h|X PDK Setupr&…r'}r((h\Uh]j"ubaheh¾ubh|X.…r)}r*(h\X.h]jubeubaubj)r+}r,(h\XÂExecute the PdkProjectCreate script in ${PDK_INSTALL_PATH}/packages as described on the `PDK Example and Test Project Creation wiki `__ h]jühchdhejhg}r-(hi]hj]hk]hl]ho]uhqNhrhhs]r.h›)r/}r0(h\XÁExecute the PdkProjectCreate script in ${PDK_INSTALL_PATH}/packages as described on the `PDK Example and Test Project Creation wiki `__h]j+hchdhehŸhg}r1(hi]hj]hk]hl]ho]uhqMAhs]r2(h|XXExecute the PdkProjectCreate script in ${PDK_INSTALL_PATH}/packages as described on the r3…r4}r5(h\XXExecute the PdkProjectCreate script in ${PDK_INSTALL_PATH}/packages as described on the h]j/ubh´)r6}r7(h\Xi`PDK Example and Test Project Creation wiki `__hg}r8(UnameX*PDK Example and Test Project Creation wikih¸X8How_to_Guides.html#pdk-example-and-test-project-creationhl]hk]hi]hj]ho]uh]j/hs]r9h|X*PDK Example and Test Project Creation wikir:…r;}r<(h\Uh]j6ubaheh¾ubeubaubeubhê)r=}r>(h\XzWhat is the difference between SOC-specific driver library and the SOC-independent (Generic core-specific) driver library?r?h]j­hchdhehîhg}r@(hl]rAUwwhat-is-the-difference-between-soc-specific-driver-library-and-the-soc-independent-generic-core-specific-driver-libraryrBahk]hi]hj]ho]rChauhqNhrhhs]rDh|XzWhat is the difference between SOC-specific driver library and the SOC-independent (Generic core-specific) driver library?rE…rF}rG(h\j?h]j=ubaubh›)rH}rI(h\X‚Each low level driver (LLD) in the PDK package contains two versions of the driver library. The naming conventions are as follows:rJh]j­hchdhehŸhg}rK(hi]hj]hk]hl]ho]uhqMIhrhhs]rLh|X‚Each low level driver (LLD) in the PDK package contains two versions of the driver library. The naming conventions are as follows:rM…rN}rO(h\jJh]jHubaubj)rP}rQ(h\Uh]j­hchdhejhg}rR(jX-hl]hk]hi]hj]ho]uhqMLhrhhs]rSj)rT}rU(h\XV**Generic Core-specific Driver Library** : ti.drv.. h]jPhchdhejhg}rV(hi]hj]hk]hl]ho]uhqNhrhhs]rWh›)rX}rY(h\XU**Generic Core-specific Driver Library** : ti.drv..h]jThchdhehŸhg}rZ(hi]hj]hk]hl]ho]uhqMLhs]r[(cdocutils.nodes strong r\)r]}r^(h\X(**Generic Core-specific Driver Library**hg}r_(hi]hj]hk]hl]ho]uh]jXhs]r`h|X$Generic Core-specific Driver Libraryra…rb}rc(h\Uh]j]ubaheUstrongrdubh|X- : ti.drv..re…rf}rg(h\X- : ti.drv..h]jXubeubaubaubh›)rh}ri(h\XCExample: ti.drv.gpio.aa15fg (A15 core-specific GPIO driver library)rjh]j­hchdhehŸhg}rk(hi]hj]hk]hl]ho]uhqMOhrhhs]rlh|XCExample: ti.drv.gpio.aa15fg (A15 core-specific GPIO driver library)rm…rn}ro(h\jjh]jhubaubj)rp}rq(h\Uh]j­hchdhejhg}rr(jX-hl]hk]hi]hj]ho]uhqMQhrhhs]rsj)rt}ru(h\XQ**SOC-specific Driver Library**: ti.pdk... h]jphchdhejhg}rv(hi]hj]hk]hl]ho]uhqNhrhhs]rwh›)rx}ry(h\XP**SOC-specific Driver Library**: ti.pdk...h]jthchdhehŸhg}rz(hi]hj]hk]hl]ho]uhqMQhs]r{(j\)r|}r}(h\X**SOC-specific Driver Library**hg}r~(hi]hj]hk]hl]ho]uh]jxhs]rh|XSOC-specific Driver Libraryr€…r}r‚(h\Uh]j|ubahejdubh|X1: ti.pdk...rƒ…r„}r…(h\X1: ti.pdk...h]jxubeubaubaubh›)r†}r‡(h\XGExample: ti.drv.gpio.am572x.aa15fg (A15 GPIO driver library for AM572x)rˆh]j­hchdhehŸhg}r‰(hi]hj]hk]hl]ho]uhqMThrhhs]rŠh|XGExample: ti.drv.gpio.am572x.aa15fg (A15 GPIO driver library for AM572x)r‹…rŒ}r(h\jˆh]j†ubaubh›)rŽ}r(h\XâWhen using the core-specific driver library, users are required to provide SOC-specific driver initialization structures that provide information regarding the module instance used, interrupt numbers, configuration modes, etc.rh]j­hchdhehŸhg}r‘(hi]hj]hk]hl]ho]uhqMVhrhhs]r’h|XâWhen using the core-specific driver library, users are required to provide SOC-specific driver initialization structures that provide information regarding the module instance used, interrupt numbers, configuration modes, etc.r“…r”}r•(h\jh]jŽubaubh›)r–}r—(h\X™The SOC-specific driver library contains a default configuration (provided in _soc.c file) built into the library that gets used to initialize the driver on TI EVMs and to run sample applications provided in driver package. It may need to be modified to suit for a custom board and/or target application. The default configuration includes a specific peripheral instance, interrupt configuration, etc.r˜h]j­hchdhehŸhg}r™(hi]hj]hk]hl]ho]uhqM[hrhhs]ršh|X™The SOC-specific driver library contains a default configuration (provided in _soc.c file) built into the library that gets used to initialize the driver on TI EVMs and to run sample applications provided in driver package. It may need to be modified to suit for a custom board and/or target application. The default configuration includes a specific peripheral instance, interrupt configuration, etc.r›…rœ}r(h\j˜h]j–ubaubhê)rž}rŸ(h\X[How to create ARM baremetal CCS project that link to PDK driver libraries using GNU Linker?r h]j­hchdhehîhg}r¡(hl]r¢UZhow-to-create-arm-baremetal-ccs-project-that-link-to-pdk-driver-libraries-using-gnu-linkerr£ahk]hi]hj]ho]r¤h5auhqNhrhhs]r¥h|X[How to create ARM baremetal CCS project that link to PDK driver libraries using GNU Linker?r¦…r§}r¨(h\j h]jžubaubh›)r©}rª(h\X¦The static libraries in Platform development kit (PDK) drivers use the convention ti.drv..a. For example, the UART driver library for A15 is named "ti.drv.uart.aa15fg". This is different form the convention of naming the libraries with a suffix of "lib" and extension ".a" which is generally the case for ARM compiler libraries (e.g., librdimon.a, libgcc.a, libm.a). This is usually not an issue when building applications using GCC compiler and make/gmake as libraries can be linked using "-l" option. However, when building bare-metal (no-OS) ARM projects in CCS, the IDE expects the libraries to have the name with suffix "lib" and extension ".a". If developers try to link libraries which does not follow this convention, they observe a linking error that mentions that the library doesn`t exist. There are a couple of work around options available to users when working with baremetal PDK driver libraries:r«h]j­hchdhehŸhg}r¬(hi]hj]hk]hl]ho]uhqMfhrhhs]r­h|X¦The static libraries in Platform development kit (PDK) drivers use the convention ti.drv..a. For example, the UART driver library for A15 is named "ti.drv.uart.aa15fg". This is different form the convention of naming the libraries with a suffix of "lib" and extension ".a" which is generally the case for ARM compiler libraries (e.g., librdimon.a, libgcc.a, libm.a). This is usually not an issue when building applications using GCC compiler and make/gmake as libraries can be linked using "-l" option. However, when building bare-metal (no-OS) ARM projects in CCS, the IDE expects the libraries to have the name with suffix "lib" and extension ".a". If developers try to link libraries which does not follow this convention, they observe a linking error that mentions that the library doesn`t exist. There are a couple of work around options available to users when working with baremetal PDK driver libraries:r®…r¯}r°(h\j«h]j©ubaubh›)r±}r²(h\X˜**Option 1:** Add a colon in front of the library name when adding the ARM driver library to "Build Settings"->"GNU Linker"->"Libraries" as shown below:h]j­hchdhehŸhg}r³(hi]hj]hk]hl]ho]uhqMuhrhhs]r´(j\)rµ}r¶(h\X **Option 1:**hg}r·(hi]hj]hk]hl]ho]uh]j±hs]r¸h|X Option 1:r¹…rº}r»(h\Uh]jµubahejdubh|X‹ Add a colon in front of the library name when adding the ARM driver library to "Build Settings"->"GNU Linker"->"Libraries" as shown below:r¼…r½}r¾(h\X‹ Add a colon in front of the library name when adding the ARM driver library to "Build Settings"->"GNU Linker"->"Libraries" as shown below:h]j±ubeubcdocutils.nodes image r¿)rÀ}rÁ(h\X0.. Image:: ../images/Bare-metal_driver_link.png h]j­hchdheUimagerÂhg}rÃ(UuriX)rtos/../images/Bare-metal_driver_link.pngrÄhl]hk]hi]hj]U candidatesrÅ}rÆU*jÄsho]uhqMzhrhhs]ubh›)rÇ}rÈ(h\XS**Option 2:** Add driver libraries using linker command file using the INPUT syntaxh]j­hchdhehŸhg}rÉ(hi]hj]hk]hl]ho]uhqM{hrhhs]rÊ(j\)rË}rÌ(h\X **Option 2:**hg}rÍ(hi]hj]hk]hl]ho]uh]jÇhs]rÎh|X Option 2:rÏ…rÐ}rÑ(h\Uh]jËubahejdubh|XF Add driver libraries using linker command file using the INPUT syntaxrÒ…rÓ}rÔ(h\XF Add driver libraries using linker command file using the INPUT syntaxh]jÇubeubcdocutils.nodes literal_block rÕ)rÖ}r×(h\XWINPUT( "C:\ti\pdk_am335x_1_0_6\packages\ti\drv\gpio\lib\a8\release\ti.drv.gpio.profiling.aa8fg" "C:\ti\pdk_am335x_1_0_6\packages\ti\utils\profiling\lib\a8\release\ti.utils.profiling.aa8fg" "C:\ti\pdk_am335x_1_0_6\packages\ti\board\lib\icev2AM335x\a8\release\ti.board.aa8fg" "C:\ti\pdk_am335x_1_0_6\packages\ti\drv\i2c\lib\a8\release\ti.drv.i2c.aa8fg" "C:\ti\pdk_am335x_1_0_6\packages\ti\drv\uart\lib\a8\release\ti.drv.uart.aa8fg" "C:\ti\pdk_am335x_1_0_6\packages\ti\csl\lib\am335x\a8\release\ti.csl.aa8fg" "C:\ti\pdk_am335x_1_0_6\packages\ti\osal\lib\tirtos\a8\release\ti.osal.aa8fg" )h]j­hchdheU literal_blockrØhg}rÙ(U xml:spacerÚUpreserverÛhl]hk]hi]hj]ho]uhqM€hrhhs]rÜh|XWINPUT( "C:\ti\pdk_am335x_1_0_6\packages\ti\drv\gpio\lib\a8\release\ti.drv.gpio.profiling.aa8fg" "C:\ti\pdk_am335x_1_0_6\packages\ti\utils\profiling\lib\a8\release\ti.utils.profiling.aa8fg" "C:\ti\pdk_am335x_1_0_6\packages\ti\board\lib\icev2AM335x\a8\release\ti.board.aa8fg" "C:\ti\pdk_am335x_1_0_6\packages\ti\drv\i2c\lib\a8\release\ti.drv.i2c.aa8fg" "C:\ti\pdk_am335x_1_0_6\packages\ti\drv\uart\lib\a8\release\ti.drv.uart.aa8fg" "C:\ti\pdk_am335x_1_0_6\packages\ti\csl\lib\am335x\a8\release\ti.csl.aa8fg" "C:\ti\pdk_am335x_1_0_6\packages\ti\osal\lib\tirtos\a8\release\ti.osal.aa8fg" )rÝ…rÞ}rß(h\Uh]jÖubaubhÐ)rà}rá(h\Uh]j­hchdhehÓhg}râ(hi]hj]hk]hl]ho]uhqMŠhrhhs]rãhÖ)rä}rå(h\UhÙKh]jàhchdhehqhg}ræ(hi]hj]hk]hl]ho]uhqKhrhhs]ubaubeubh^)rç}rè(h\Uh]hahchdhehfhg}ré(hi]hj]hk]hl]rêUchip-support-library-cslrëaho]rìh auhqMhrhhs]rí(hu)rî}rï(h\XChip Support Library (CSL)rðh]jçhchdhehyhg}rñ(hi]hj]hk]hl]ho]uhqMhrhhs]ròh|XChip Support Library (CSL)ró…rô}rõ(h\jðh]jîubaubhê)rö}r÷(h\X5Are there any bare-metal examples in the PDK package?røh]jçhchdhehîhg}rù(hl]rúU4are-there-any-bare-metal-examples-in-the-pdk-packagerûahk]hi]hj]ho]rüh(auhqNhrhhs]rýh|X5Are there any bare-metal examples in the PDK package?rþ…rÿ}r(h\jøh]jöubaubh›)r}r(h\XCustomers who are wanting to start bare-metal code development can refer to the diagnostics package which uses the PDK drivers and does not rely on the TI RTOS. There are also CSL examples included in the package under the path ${PDK_INSTALL_PATH}\\packages\\ti\\csl\\test.h]jçhchdhehŸhg}r(hi]hj]hk]hl]ho]uhqM’hrhhs]rh|X Customers who are wanting to start bare-metal code development can refer to the diagnostics package which uses the PDK drivers and does not rely on the TI RTOS. There are also CSL examples included in the package under the path ${PDK_INSTALL_PATH}\packages\ti\csl\test.r…r}r(h\XCustomers who are wanting to start bare-metal code development can refer to the diagnostics package which uses the PDK drivers and does not rely on the TI RTOS. There are also CSL examples included in the package under the path ${PDK_INSTALL_PATH}\\packages\\ti\\csl\\test.h]jubaubh›)r}r (h\X¼In addition to CSL example, the PDK contains bare-metal diagnostic test cases that help in testing EVM functionality. These can be located under pdk_am57xx_x_x_x\\packages\\ti\\board\\diagh]jçhchdhehŸhg}r (hi]hj]hk]hl]ho]uhqM—hrhhs]r h|X¸In addition to CSL example, the PDK contains bare-metal diagnostic test cases that help in testing EVM functionality. These can be located under pdk_am57xx_x_x_x\packages\ti\board\diagr …r }r(h\X¼In addition to CSL example, the PDK contains bare-metal diagnostic test cases that help in testing EVM functionality. These can be located under pdk_am57xx_x_x_x\\packages\\ti\\board\\diagh]jubaubh›)r}r(h\X†Some of the driver examples contain a flag for BARE METAL usage of the driver. Example: GPIO/SPI already have these flags implemented.rh]jçhchdhehŸhg}r(hi]hj]hk]hl]ho]uhqM›hrhhs]rh|X†Some of the driver examples contain a flag for BARE METAL usage of the driver. Example: GPIO/SPI already have these flags implemented.r…r}r(h\jh]jubaubhê)r}r(h\XhCan I read core-specific registers on multi-core devices supported in Processor SDK RTOS using CSL code?rh]jçhchdhehîhg}r(hl]rUgcan-i-read-core-specific-registers-on-multi-core-devices-supported-in-processor-sdk-rtos-using-csl-coderahk]hi]hj]ho]rh.auhqNhrhhs]rh|XhCan I read core-specific registers on multi-core devices supported in Processor SDK RTOS using CSL code?r…r }r!(h\jh]jubaubh›)r"}r#(h\XYes, SDK provides CSL code to read core status and system configurations using the CSL provided for specific core. For CSL code specific to cores and peripherals present on your device, please refer to the header files provided under ${PDK_INSTALL_PATH}\\packages\\ti\\csl\\src\\ip.h]jçhchdhehŸhg}r$(hi]hj]hk]hl]ho]uhqM¢hrhhs]r%h|XYes, SDK provides CSL code to read core status and system configurations using the CSL provided for specific core. For CSL code specific to cores and peripherals present on your device, please refer to the header files provided under ${PDK_INSTALL_PATH}\packages\ti\csl\src\ip.r&…r'}r((h\XYes, SDK provides CSL code to read core status and system configurations using the CSL provided for specific core. For CSL code specific to cores and peripherals present on your device, please refer to the header files provided under ${PDK_INSTALL_PATH}\\packages\\ti\\csl\\src\\ip.h]j"ubaubh›)r)}r*(h\X'A good example of where you may need to access CSL code to read core-specific information is on a multi-core device. You can have code shared between multiple cores and would like to use a different code path or internal buffer based on core ID. The CSL code helps you implement this as follows:r+h]jçhchdhehŸhg}r,(hi]hj]hk]hl]ho]uhqM§hrhhs]r-h|X'A good example of where you may need to access CSL code to read core-specific information is on a multi-core device. You can have code shared between multiple cores and would like to use a different code path or internal buffer based on core ID. The CSL code helps you implement this as follows:r.…r/}r0(h\j+h]j)ubaubh›)r1}r2(h\XHFor example, if you need to read the core ID on a multi-core DSP device:r3h]jçhchdhehŸhg}r4(hi]hj]hk]hl]ho]uhqM­hrhhs]r5h|XHFor example, if you need to read the core ID on a multi-core DSP device:r6…r7}r8(h\j3h]j1ubaubjÕ)r9}r:(h\XVuint32_t coreNum; /* Get the core number. */ coreNum = CSL_chipReadReg(CSL_CHIP_DNUM);h]jçhchdhejØhg}r;(jÚjÛhl]hk]hi]hj]ho]uhqM±hrhhs]r<h|XVuint32_t coreNum; /* Get the core number. */ coreNum = CSL_chipReadReg(CSL_CHIP_DNUM);r=…r>}r?(h\Uh]j9ubaubh›)r@}rA(h\X[To do the same on the multi-core A15 device, you can use the following code in the A15 CSL:rBh]jçhchdhehŸhg}rC(hi]hj]hk]hl]ho]uhqMµhrhhs]rDh|X[To do the same on the multi-core A15 device, you can use the following code in the A15 CSL:rE…rF}rG(h\jBh]j@ubaubjÕ)rH}rI(h\Xeunsigned int armNum; armNum = CSL_a15ReadCoreId(); //This gets the core ID using the MPIDR in the A15h]jçhchdhejØhg}rJ(jÚjÛhl]hk]hi]hj]ho]uhqMºhrhhs]rKh|Xeunsigned int armNum; armNum = CSL_a15ReadCoreId(); //This gets the core ID using the MPIDR in the A15rL…rM}rN(h\Uh]jHubaubhê)rO}rP(h\XGHow do I find out which CSL header and source files apply to my device?rQh]jçhchdhehîhg}rR(hl]rSUFhow-do-i-find-out-which-csl-header-and-source-files-apply-to-my-devicerTahk]hi]hj]ho]rUhFauhqNhrhhs]rVh|XGHow do I find out which CSL header and source files apply to my device?rW…rX}rY(h\jQh]jOubaubh›)rZ}r[(h\X7The CSL package that is part of the SDK is a unified CSL that covers all devices supported by the Processor SDK RTOS. When you link to the CSL library or include the header files for a specific IP, the CSL library requires users to add a MACRO definition (-D SOC_XX####) to your build to indicate which SOC you are using. In order to locate the IP files for your device, always look at the header file at the top of the CSL directory pdk__xx_xx_xx\\packages\\ti\\csl and the files that are found under the SOC_XX#### corresponds to the SOC that you are using.h]jçhchdhehŸhg}r\(hi]hj]hk]hl]ho]uhqMÁhrhhs]r]h|X4The CSL package that is part of the SDK is a unified CSL that covers all devices supported by the Processor SDK RTOS. When you link to the CSL library or include the header files for a specific IP, the CSL library requires users to add a MACRO definition (-D SOC_XX####) to your build to indicate which SOC you are using. In order to locate the IP files for your device, always look at the header file at the top of the CSL directory pdk__xx_xx_xx\packages\ti\csl and the files that are found under the SOC_XX#### corresponds to the SOC that you are using.r^…r_}r`(h\X7The CSL package that is part of the SDK is a unified CSL that covers all devices supported by the Processor SDK RTOS. When you link to the CSL library or include the header files for a specific IP, the CSL library requires users to add a MACRO definition (-D SOC_XX####) to your build to indicate which SOC you are using. In order to locate the IP files for your device, always look at the header file at the top of the CSL directory pdk__xx_xx_xx\\packages\\ti\\csl and the files that are found under the SOC_XX#### corresponds to the SOC that you are using.h]jZubaubh›)ra}rb(h\XkSOC-specific files can also be found under the pdk__xx_xx_xx\\packages\\ti\\csl\\soc\\h]jçhchdhehŸhg}rc(hi]hj]hk]hl]ho]uhqMÊhrhhs]rdh|XfSOC-specific files can also be found under the pdk__xx_xx_xx\packages\ti\csl\soc\re…rf}rg(h\XkSOC-specific files can also be found under the pdk__xx_xx_xx\\packages\\ti\\csl\\soc\\h]jaubaubhê)rh}ri(h\X7What is the system memory map used by the SDK examples?rjh]jçhchdhehîhg}rk(hl]rlU6what-is-the-system-memory-map-used-by-the-sdk-examplesrmahk]hi]hj]ho]rnhauhqNhrhhs]roh|X7What is the system memory map used by the SDK examples?rp…rq}rr(h\jjh]jhubaubh›)rs}rt(h\X The TI RTOS-based examples included in the SDK rely on the platform definitions provided inside bios_6_xx_xx_xx\\packages\\ti\\platforms for partitioning the SOC memory between all the available cores on the SoC. Please take a look at the snapshot below for AM572x:h]jçhchdhehŸhg}ru(hi]hj]hk]hl]ho]uhqMÐhrhhs]rvh|XThe TI RTOS-based examples included in the SDK rely on the platform definitions provided inside bios_6_xx_xx_xx\packages\ti\platforms for partitioning the SOC memory between all the available cores on the SoC. Please take a look at the snapshot below for AM572x:rw…rx}ry(h\X The TI RTOS-based examples included in the SDK rely on the platform definitions provided inside bios_6_xx_xx_xx\\packages\\ti\\platforms for partitioning the SOC memory between all the available cores on the SoC. Please take a look at the snapshot below for AM572x:h]jsubaubjÕ)rz}r{(h\Xu/* Memory Map for ti.platforms.evmAM572X * * Virtual Physical Size Comment * ------------------------------------------------------------------------ * 8000_0000 1000_0000 ( 256 MB) External Memory * * 0000_0000 0 8000_0000 100 ( 256 B) -------- * 8000_0100 FF00 ( ~64 KB) -------- * 0000_0000 8001_0000 100 ( 256 B) -------- * 8001_0100 FF00 ( ~64 KB) -------- * 0000_0000 8002_0000 100 ( 256 B) -------- * 8002_0100 FF00 ( ~64 KB) -------- * 0000_0000 8003_0000 100 ( 256 B) -------- * 8003_0100 FE_FF00 ( ~16 MB) -------- * 1 8100_0000 40_0000 ( 4 MB) -------- * 8140_0000 C0_0000 ( 12 MB) -------- * 2 8200_0000 40_0000 ( 4 MB) -------- * 8240_0000 C0_0000 ( 12 MB) -------- * 3 8300_0000 40_0000 ( 4 MB) -------- * 8340_0000 C0_0000 ( 12 MB) -------- * 4 8400_0000 40_0000 ( 4 MB) -------- * 8440_0000 C0_0000 ( 12 MB) -------- * 5 8500_0000 100_0000 ( 16 MB) -------- * 6 8600_0000 100_0000 ( 16 MB) -------- * 7 8700_0000 100_0000 ( 16 MB) -------- * 8 8800_0000 100_0000 ( 16 MB) -------- * 9 8900_0000 100_0000 ( 16 MB) -------- * A 8A00_0000 80_0000 ( 8 MB) IPU1 (code, data), benelli * 8A80_0000 80_0000 ( 8 MB) IPU2 (code, data), benelli * B 8B00_0000 100_0000 ( 16 MB) HOST (code, data) * C 8C00_0000 100_0000 ( 16 MB) DSP1 (code, data) * D 8D00_0000 100_0000 ( 16 MB) DSP2 (code, data) * E 8E00_0000 100_0000 ( 16 MB) SR_0 (ipc) * F 8F00_0000 100_0000 ( 16 MB) -------- */h]jçhchdhejØhg}r|(jÚjÛhl]hk]hi]hj]ho]uhqM×hrhhs]r}h|Xu/* Memory Map for ti.platforms.evmAM572X * * Virtual Physical Size Comment * ------------------------------------------------------------------------ * 8000_0000 1000_0000 ( 256 MB) External Memory * * 0000_0000 0 8000_0000 100 ( 256 B) -------- * 8000_0100 FF00 ( ~64 KB) -------- * 0000_0000 8001_0000 100 ( 256 B) -------- * 8001_0100 FF00 ( ~64 KB) -------- * 0000_0000 8002_0000 100 ( 256 B) -------- * 8002_0100 FF00 ( ~64 KB) -------- * 0000_0000 8003_0000 100 ( 256 B) -------- * 8003_0100 FE_FF00 ( ~16 MB) -------- * 1 8100_0000 40_0000 ( 4 MB) -------- * 8140_0000 C0_0000 ( 12 MB) -------- * 2 8200_0000 40_0000 ( 4 MB) -------- * 8240_0000 C0_0000 ( 12 MB) -------- * 3 8300_0000 40_0000 ( 4 MB) -------- * 8340_0000 C0_0000 ( 12 MB) -------- * 4 8400_0000 40_0000 ( 4 MB) -------- * 8440_0000 C0_0000 ( 12 MB) -------- * 5 8500_0000 100_0000 ( 16 MB) -------- * 6 8600_0000 100_0000 ( 16 MB) -------- * 7 8700_0000 100_0000 ( 16 MB) -------- * 8 8800_0000 100_0000 ( 16 MB) -------- * 9 8900_0000 100_0000 ( 16 MB) -------- * A 8A00_0000 80_0000 ( 8 MB) IPU1 (code, data), benelli * 8A80_0000 80_0000 ( 8 MB) IPU2 (code, data), benelli * B 8B00_0000 100_0000 ( 16 MB) HOST (code, data) * C 8C00_0000 100_0000 ( 16 MB) DSP1 (code, data) * D 8D00_0000 100_0000 ( 16 MB) DSP2 (code, data) * E 8E00_0000 100_0000 ( 16 MB) SR_0 (ipc) * F 8F00_0000 100_0000 ( 16 MB) -------- */r~…r}r€(h\Uh]jzubaubh›)r}r‚(h\X¾For bare-metal code, users are required to use a linker command file for each of the cores and partition the memory manually so that there is no memory overlap in the applications running on each of the cores. For bare-metal linker command files, you can refer to the CCS templates for `Hello World `__ or the linker command file used in the common folder of the the diagnostics package.h]jçhchdhehŸhg}rƒ(hi]hj]hk]hl]ho]uhqMûhrhhs]r„(h|XFor bare-metal code, users are required to use a linker command file for each of the cores and partition the memory manually so that there is no memory overlap in the applications running on each of the cores. For bare-metal linker command files, you can refer to the CCS templates for r……r†}r‡(h\XFor bare-metal code, users are required to use a linker command file for each of the cores and partition the memory manually so that there is no memory overlap in the applications running on each of the cores. For bare-metal linker command files, you can refer to the CCS templates for h]jubh´)rˆ}r‰(h\XK`Hello World `__hg}rŠ(UnameX Hello Worldh¸X9Examples_and_Demonstrations.html#no-os-bare-metal-examplehl]hk]hi]hj]ho]uh]jhs]r‹h|X Hello WorldrŒ…r}rŽ(h\Uh]jˆubaheh¾ubh|XU or the linker command file used in the common folder of the the diagnostics package.r…r}r‘(h\XU or the linker command file used in the common folder of the the diagnostics package.h]jubeubhÐ)r’}r“(h\Uh]jçhchdhehÓhg}r”(hi]hj]hk]hl]ho]uhqMhrhhs]r•hÖ)r–}r—(h\UhÙKh]j’hchdhehqhg}r˜(hi]hj]hk]hl]ho]uhqKhrhhs]ubaubeubh^)r™}rš(h\Uh]hahchdhehfhg}r›(hi]hj]hk]hl]rœU board-supportraho]ržh$auhqMhrhhs]rŸ(hu)r }r¡(h\X Board Supportr¢h]j™hchdhehyhg}r£(hi]hj]hk]hl]ho]uhqMhrhhs]r¤h|X Board Supportr¥…r¦}r§(h\j¢h]j ubaubhê)r¨}r©(h\XAWhat steps are involved when creating a new custom board library?rªh]j™hchdhehîhg}r«(hl]r¬U@what-steps-are-involved-when-creating-a-new-custom-board-libraryr­ahk]hi]hj]ho]r®hRauhqNhrhhs]r¯h|XAWhat steps are involved when creating a new custom board library?r°…r±}r²(h\jªh]j¨ubaubh›)r³}r´(h\XThe board library consolidates all the board-specific information so that all the modifications made when moving to a new custom platform using the SOC can be made in the source of this library. The following steps are involved in creating custom board library:rµh]j™hchdhehŸhg}r¶(hi]hj]hk]hl]ho]uhqM hrhhs]r·h|XThe board library consolidates all the board-specific information so that all the modifications made when moving to a new custom platform using the SOC can be made in the source of this library. The following steps are involved in creating custom board library:r¸…r¹}rº(h\jµh]j³ubaubj)r»}r¼(h\Uh]j™hchdhejhg}r½(jX-hl]hk]hi]hj]ho]uhqMhrhhs]r¾(j)r¿}rÀ(h\X°**Modify SOC Clock Settings** The core clocks and module clocks used on the custom board library may vary based on the power requirements and external components used on the boards. TI provides `Clock Tree Tools `__ to simulate the device clocks. We recommend that you test the settings in CCS by creating a GEL file with the modified settings before modifying the source in the board library. h]j»hchdhejhg}rÁ(hi]hj]hk]hl]ho]uhqNhrhhs]rÂh›)rÃ}rÄ(h\X¯**Modify SOC Clock Settings** The core clocks and module clocks used on the custom board library may vary based on the power requirements and external components used on the boards. TI provides `Clock Tree Tools `__ to simulate the device clocks. We recommend that you test the settings in CCS by creating a GEL file with the modified settings before modifying the source in the board library.h]j¿hchdhehŸhg}rÅ(hi]hj]hk]hl]ho]uhqMhs]rÆ(j\)rÇ}rÈ(h\X**Modify SOC Clock Settings**hg}rÉ(hi]hj]hk]hl]ho]uh]jÃhs]rÊh|XModify SOC Clock SettingsrË…rÌ}rÍ(h\Uh]jÇubahejdubh|X¥ The core clocks and module clocks used on the custom board library may vary based on the power requirements and external components used on the boards. TI provides rÎ…rÏ}rÐ(h\X¥ The core clocks and module clocks used on the custom board library may vary based on the power requirements and external components used on the boards. TI provides h]jÃubh´)rÑ}rÒ(h\X;`Clock Tree Tools `__hg}rÓ(UnameXClock Tree Toolsh¸X$http://www.ti.com/tool/CLOCKTREETOOLhl]hk]hi]hj]ho]uh]jÃhs]rÔh|XClock Tree ToolsrÕ…rÖ}r×(h\Uh]jÑubaheh¾ubh|X² to simulate the device clocks. We recommend that you test the settings in CCS by creating a GEL file with the modified settings before modifying the source in the board library.rØ…rÙ}rÚ(h\X² to simulate the device clocks. We recommend that you test the settings in CCS by creating a GEL file with the modified settings before modifying the source in the board library.h]jÃubeubaubj)rÛ}rÜ(h\X¶**Modify SOC DDR:** The board library has the correct DDR initialization sequence to initialize the DDR memory on your board. You may need to make changes to the AC timings, hardware leveling, and DDR PHY configuration, some or all of which may be different than the TI supported platforms. We recommend that you test the settings in CCS by creating a GEL file with the modified settings before modifying the source in the board library. h]j»hchdhejhg}rÝ(hi]hj]hk]hl]ho]uhqNhrhhs]rÞh›)rß}rà(h\Xµ**Modify SOC DDR:** The board library has the correct DDR initialization sequence to initialize the DDR memory on your board. You may need to make changes to the AC timings, hardware leveling, and DDR PHY configuration, some or all of which may be different than the TI supported platforms. We recommend that you test the settings in CCS by creating a GEL file with the modified settings before modifying the source in the board library.h]jÛhchdhehŸhg}rá(hi]hj]hk]hl]ho]uhqMhs]râ(j\)rã}rä(h\X**Modify SOC DDR:**hg}rå(hi]hj]hk]hl]ho]uh]jßhs]ræh|XModify SOC DDR:rç…rè}ré(h\Uh]jãubahejdubh|X¢ The board library has the correct DDR initialization sequence to initialize the DDR memory on your board. You may need to make changes to the AC timings, hardware leveling, and DDR PHY configuration, some or all of which may be different than the TI supported platforms. We recommend that you test the settings in CCS by creating a GEL file with the modified settings before modifying the source in the board library.rê…rë}rì(h\X¢ The board library has the correct DDR initialization sequence to initialize the DDR memory on your board. You may need to make changes to the AC timings, hardware leveling, and DDR PHY configuration, some or all of which may be different than the TI supported platforms. We recommend that you test the settings in CCS by creating a GEL file with the modified settings before modifying the source in the board library.h]jßubeubaubeubh^)rí}rî(h\Uh]j™hchdhehfhg}rï(hi]hj]hk]hl]rðU"useful-ddr-configuration-resourcesrñaho]ròhTauhqM"hrhhs]ró(hu)rô}rõ(h\X"Useful DDR Configuration Resourcesröh]jíhchdhehyhg}r÷(hi]hj]hk]hl]ho]uhqM"hrhhs]røh|X"Useful DDR Configuration Resourcesrù…rú}rû(h\jöh]jôubaubcdocutils.nodes table rü)rý}rþ(h\Uh]jíhchdheUtablerÿhg}r(hi]hj]hk]hl]ho]uhqNhrhhs]rcdocutils.nodes tgroup r)r}r(h\Uhg}r(hl]hk]hi]hj]ho]UcolsKuh]jýhs]r(cdocutils.nodes colspec r)r}r (h\Uhg}r (hl]hk]hi]hj]ho]UcolwidthK‚uh]jhs]heUcolspecr ubj)r }r (h\Uhg}r(hl]hk]hi]hj]ho]UcolwidthKFuh]jhs]hej ubcdocutils.nodes thead r)r}r(h\Uhg}r(hi]hj]hk]hl]ho]uh]jhs]rcdocutils.nodes row r)r}r(h\Uhg}r(hi]hj]hk]hl]ho]uh]jhs]r(cdocutils.nodes entry r)r}r(h\Uhg}r(hi]hj]hk]hl]ho]uh]jhs]rh›)r}r(h\XSitara Resources:r h]jhchdhehŸhg}r!(hi]hj]hk]hl]ho]uhqM%hs]r"h|XSitara Resources:r#…r$}r%(h\j h]jubaubaheUentryr&ubj)r'}r((h\Uhg}r)(hi]hj]hk]hl]ho]uh]jhs]r*h›)r+}r,(h\XKeystone Resources:r-h]j'hchdhehŸhg}r.(hi]hj]hk]hl]ho]uhqM%hs]r/h|XKeystone Resources:r0…r1}r2(h\j-h]j+ubaubahej&ubeheUrowr3ubaheUtheadr4ubcdocutils.nodes tbody r5)r6}r7(h\Uhg}r8(hi]hj]hk]hl]ho]uh]jhs]r9(j)r:}r;(h\Uhg}r<(hi]hj]hk]hl]ho]uh]j6hs]r=(j)r>}r?(h\Uhg}r@(hi]hj]hk]hl]ho]uh]j:hs]rAh›)rB}rC(h\X7`AM57x EMIF Tools `_rDh]j>hchdhehŸhg}rE(hi]hj]hk]hl]ho]uhqM'hs]rF(h´)rG}rH(h\jDhg}rI(UnameXAM57x EMIF Toolsh¸X!http://www.ti.com/lit/pdf/sprac36rJhl]hk]hi]hj]ho]uh]jBhs]rKh|XAM57x EMIF ToolsrL…rM}rN(h\Uh]jGubaheh¾ubh¿)rO}rP(h\X$ hÂKh]jBhehÃhg}rQ(UrefurijJhl]rRUam57x-emif-toolsrSahk]hi]hj]ho]rThauhs]ubeubahej&ubj)rU}rV(h\Uhg}rW(hi]hj]hk]hl]ho]uh]j:hs]rXh›)rY}rZ(h\X<`KeyStone II DDR Guide `_r[h]jUhchdhehŸhg}r\(hi]hj]hk]hl]ho]uhqM'hs]r](h´)r^}r_(h\j[hg}r`(UnameXKeyStone II DDR Guideh¸X!http://www.ti.com/lit/pdf/sprabx7rahl]hk]hi]hj]ho]uh]jYhs]rbh|XKeyStone II DDR Guiderc…rd}re(h\Uh]j^ubaheh¾ubh¿)rf}rg(h\X$ hÂKh]jYhehÃhg}rh(Urefurijahl]riUkeystone-ii-ddr-guiderjahk]hi]hj]ho]rkh>auhs]ubeubahej&ubehej3ubj)rl}rm(h\Uhg}rn(hi]hj]hk]hl]ho]uh]j6hs]ro(j)rp}rq(h\Uhg}rr(hi]hj]hk]hl]ho]uh]jlhs]rsh›)rt}ru(h\Xz`AM437x DDR Configuration Guide `_rvh]jphchdhehŸhg}rw(hi]hj]hk]hl]ho]uhqM)hs]rx(h´)ry}rz(h\jvhg}r{(UnameXAM437x DDR Configuration Guideh¸XVhttp://processors.wiki.ti.com/index.php/AM437x_DDR_Configuration_and_Programming_Guider|hl]hk]hi]hj]ho]uh]jths]r}h|XAM437x DDR Configuration Guider~…r}r€(h\Uh]jyubaheh¾ubh¿)r}r‚(h\XY hÂKh]jthehÃhg}rƒ(Urefurij|hl]r„Uam437x-ddr-configuration-guider…ahk]hi]hj]ho]r†hMauhs]ubeubahej&ubj)r‡}rˆ(h\Uhg}r‰(hi]hj]hk]hl]ho]uh]jlhs]rŠh›)r‹}rŒ(h\XB`KeyStone II DDR Debug Guide `_rh]j‡hchdhehŸhg}rŽ(hi]hj]hk]hl]ho]uhqM)hs]r(h´)r}r‘(h\jhg}r’(UnameXKeyStone II DDR Debug Guideh¸X!http://www.ti.com/lit/pdf/sprac04r“hl]hk]hi]hj]ho]uh]j‹hs]r”h|XKeyStone II DDR Debug Guider•…r–}r—(h\Uh]jubaheh¾ubh¿)r˜}r™(h\X$ hÂKh]j‹hehÃhg}rš(Urefurij“hl]r›Ukeystone-ii-ddr-debug-guiderœahk]hi]hj]ho]rhOauhs]ubeubahej&ubehej3ubj)rž}rŸ(h\Uhg}r (hi]hj]hk]hl]ho]uh]j6hs]r¡(j)r¢}r£(h\Uhg}r¤(hi]hj]hk]hl]ho]uh]jžhs]r¥h›)r¦}r§(h\Xp`AM335x/AM11x EMIF ConfigurationTools `_r¨h]j¢hchdhehŸhg}r©(hi]hj]hk]hl]ho]uhqM+hs]rª(h´)r«}r¬(h\j¨hg}r­(UnameX$AM335x/AM11x EMIF ConfigurationToolsh¸XFhttp://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tipsr®hl]hk]hi]hj]ho]uh]j¦hs]r¯h|X$AM335x/AM11x EMIF ConfigurationToolsr°…r±}r²(h\Uh]j«ubaheh¾ubh¿)r³}r´(h\XI hÂKh]j¦hehÃhg}rµ(Urefurij®hl]r¶U$am335x-am11x-emif-configurationtoolsr·ahk]hi]hj]ho]r¸h+auhs]ubeubahej&ubj)r¹}rº(h\Uhg}r»(hi]hj]hk]hl]ho]uh]jžhs]r¼h›)r½}r¾(h\XC`KeyStoneI DDR Initialization `_r¿h]j¹hchdhehŸhg}rÀ(hi]hj]hk]hl]ho]uhqM+hs]rÁ(h´)rÂ}rÃ(h\j¿hg}rÄ(UnameXKeyStoneI DDR Initializationh¸X!http://www.ti.com/lit/pdf/sprabl2rÅhl]hk]hi]hj]ho]uh]j½hs]rÆh|XKeyStoneI DDR InitializationrÇ…rÈ}rÉ(h\Uh]jÂubaheh¾ubh¿)rÊ}rË(h\X$ hÂKh]j½hehÃhg}rÌ(UrefurijÅhl]rÍUkeystonei-ddr-initializationrÎahk]hi]hj]ho]rÏh2auhs]ubeubahej&ubehej3ubeheUtbodyrÐubeheUtgrouprÑubaubj)rÒ}rÓ(h\Uh]jíhchdhejhg}rÔ(jX-hl]hk]hi]hj]ho]uhqM.hrhhs]rÕ(j)rÖ}r×(h\X°**Modify SoC Pin Mux Settings.** The Pin Mux configuration for a particular platform is obtained by creating a .pinmux project for the device using the `TI Pin Mux Tools `__ available on ti.com. The output of the tool can be plugged into the board library to modify the default configuration. The default baseline Pin Mux project (boardname.pinmux) is included in the board library for reference. h]jÒhchdhejhg}rØ(hi]hj]hk]hl]ho]uhqNhrhhs]rÙh›)rÚ}rÛ(h\X¯**Modify SoC Pin Mux Settings.** The Pin Mux configuration for a particular platform is obtained by creating a .pinmux project for the device using the `TI Pin Mux Tools `__ available on ti.com. The output of the tool can be plugged into the board library to modify the default configuration. The default baseline Pin Mux project (boardname.pinmux) is included in the board library for reference.h]jÖhchdhehŸhg}rÜ(hi]hj]hk]hl]ho]uhqM.hs]rÝ(j\)rÞ}rß(h\X **Modify SoC Pin Mux Settings.**hg}rà(hi]hj]hk]hl]ho]uh]jÚhs]ráh|XModify SoC Pin Mux Settings.râ…rã}rä(h\Uh]jÞubahejdubh|Xx The Pin Mux configuration for a particular platform is obtained by creating a .pinmux project for the device using the rå…ræ}rç(h\Xx The Pin Mux configuration for a particular platform is obtained by creating a .pinmux project for the device using the h]jÚubh´)rè}ré(h\X8`TI Pin Mux Tools `__hg}rê(UnameXTI Pin Mux Toolsh¸X!http://www.ti.com/tool/PINMUXTOOLhl]hk]hi]hj]ho]uh]jÚhs]rëh|XTI Pin Mux Toolsrì…rí}rî(h\Uh]jèubaheh¾ubh|Xß available on ti.com. The output of the tool can be plugged into the board library to modify the default configuration. The default baseline Pin Mux project (boardname.pinmux) is included in the board library for reference.rï…rð}rñ(h\Xß available on ti.com. The output of the tool can be plugged into the board library to modify the default configuration. The default baseline Pin Mux project (boardname.pinmux) is included in the board library for reference.h]jÚubeubaubj)rò}ró(h\X"**Modify IO Instance and Configuration to Match Use Case:** If your custom board uses an IO instance different from the TI-supported board, the instance needs to be modified in the Pin Mux setup as well as in the board_cfg.h file in pdk_xx_Xx_xx_xx/packages/ti/board/src// h]jÒhchdhejhg}rô(hi]hj]hk]hl]ho]uhqNhrhhs]rõh›)rö}r÷(h\X!**Modify IO Instance and Configuration to Match Use Case:** If your custom board uses an IO instance different from the TI-supported board, the instance needs to be modified in the Pin Mux setup as well as in the board_cfg.h file in pdk_xx_Xx_xx_xx/packages/ti/board/src//h]jòhchdhehŸhg}rø(hi]hj]hk]hl]ho]uhqM6hs]rù(j\)rú}rû(h\X;**Modify IO Instance and Configuration to Match Use Case:**hg}rü(hi]hj]hk]hl]ho]uh]jöhs]rýh|X7Modify IO Instance and Configuration to Match Use Case:rþ…rÿ}r(h\Uh]júubahejdubh|Xæ If your custom board uses an IO instance different from the TI-supported board, the instance needs to be modified in the Pin Mux setup as well as in the board_cfg.h file in pdk_xx_Xx_xx_xx/packages/ti/board/src//r…r}r(h\Xæ If your custom board uses an IO instance different from the TI-supported board, the instance needs to be modified in the Pin Mux setup as well as in the board_cfg.h file in pdk_xx_Xx_xx_xx/packages/ti/board/src//h]jöubeubaubj)r}r(h\X**Modify Files Corresponding to External Board Components:** The custom board may have external components (flash devices, Ethernet PHY, etc.) that are different from the components populated on the TI-supported EVM. These components and their support files need to be added to the pdk_xx_Xx_xx_xx/packages/ti/board/src//device path and linked as part of the board library build. h]jÒhchdhejhg}r(hi]hj]hk]hl]ho]uhqNhrhhs]rh›)r}r (h\XŒ**Modify Files Corresponding to External Board Components:** The custom board may have external components (flash devices, Ethernet PHY, etc.) that are different from the components populated on the TI-supported EVM. These components and their support files need to be added to the pdk_xx_Xx_xx_xx/packages/ti/board/src//device path and linked as part of the board library build.h]jhchdhehŸhg}r (hi]hj]hk]hl]ho]uhqM<hs]r (j\)r }r (h\X<**Modify Files Corresponding to External Board Components:**hg}r(hi]hj]hk]hl]ho]uh]jhs]rh|X8Modify Files Corresponding to External Board Components:r…r}r(h\Uh]j ubahejdubh|XP The custom board may have external components (flash devices, Ethernet PHY, etc.) that are different from the components populated on the TI-supported EVM. These components and their support files need to be added to the pdk_xx_Xx_xx_xx/packages/ti/board/src//device path and linked as part of the board library build.r…r}r(h\XP The custom board may have external components (flash devices, Ethernet PHY, etc.) that are different from the components populated on the TI-supported EVM. These components and their support files need to be added to the pdk_xx_Xx_xx_xx/packages/ti/board/src//device path and linked as part of the board library build.h]jubeubaubeubh›)r}r(h\X‹The above steps have been explained in detail in **Section 9** of the **`Application Development Using Processor SDK RTOS Training `__**. The slides talk about the different aspects of porting Processor SDK 3.0 to your custom platform, including incorporating custom Pin Mux, clocking, peripheral instance, etc.h]jíhchdhehŸhg}r(hi]hj]hk]hl]ho]uhqMDhrhhs]r(h|X1The above steps have been explained in detail in r…r}r(h\X1The above steps have been explained in detail in h]jubj\)r}r(h\X **Section 9**hg}r(hi]hj]hk]hl]ho]uh]jhs]r h|X Section 9r!…r"}r#(h\Uh]jubahejdubh|X of the r$…r%}r&(h\X of the h]jubj\)r'}r((h\X–**`Application Development Using Processor SDK RTOS Training `__**hg}r)(hi]hj]hk]hl]ho]uh]jhs]r*h|X’`Application Development Using Processor SDK RTOS Training `__r+…r,}r-(h\Uh]j'ubahejdubh|X¯. The slides talk about the different aspects of porting Processor SDK 3.0 to your custom platform, including incorporating custom Pin Mux, clocking, peripheral instance, etc.r.…r/}r0(h\X¯. The slides talk about the different aspects of porting Processor SDK 3.0 to your custom platform, including incorporating custom Pin Mux, clocking, peripheral instance, etc.h]jubeubh›)r1}r2(h\XýAdding custom board to the PDK directory structure and build setup is described in the article `Adding_Custom_Board_Library_Target_to_Processor_SDK_RTOS_makefiles `__h]jíhchdhehŸhg}r3(hi]hj]hk]hl]ho]uhqMKhrhhs]r4(h|X_Adding custom board to the PDK directory structure and build setup is described in the article r5…r6}r7(h\X_Adding custom board to the PDK directory structure and build setup is described in the article h]j1ubh´)r8}r9(h\Xž`Adding_Custom_Board_Library_Target_to_Processor_SDK_RTOS_makefiles `__hg}r:(UnameXBAdding_Custom_Board_Library_Target_to_Processor_SDK_RTOS_makefilesh¸XUHow_to_Guides.html#adding-custom-board-library-target-to-processor-sdk-rtos-makefileshl]hk]hi]hj]ho]uh]j1hs]r;h|XBAdding_Custom_Board_Library_Target_to_Processor_SDK_RTOS_makefilesr<…r=}r>(h\Uh]j8ubaheh¾ubeubcdocutils.nodes note r?)r@}rA(h\XRTI evaluation platforms for Sitara Processors usually have board information stored in an EEPROM which checks for revision number and board name which is used to configure the board. When creating a custom platform if you don`t intend to use an EEPROM then we recommend removing code corresponding to Board_getIDInfo in your board libraryh]jíhchdheUnoterBhg}rC(hi]hj]hk]hl]ho]uhqNhrhhs]rDh›)rE}rF(h\XRTI evaluation platforms for Sitara Processors usually have board information stored in an EEPROM which checks for revision number and board name which is used to configure the board. When creating a custom platform if you don`t intend to use an EEPROM then we recommend removing code corresponding to Board_getIDInfo in your board libraryrGh]j@hchdhehŸhg}rH(hi]hj]hk]hl]ho]uhqMPhs]rIh|XRTI evaluation platforms for Sitara Processors usually have board information stored in an EEPROM which checks for revision number and board name which is used to configure the board. When creating a custom platform if you don`t intend to use an EEPROM then we recommend removing code corresponding to Board_getIDInfo in your board libraryrJ…rK}rL(h\jGh]jEubaubaubhÐ)rM}rN(h\Uh]jíhchdhehÓhg}rO(hi]hj]hk]hl]ho]uhqMUhrhhs]rPhÖ)rQ}rR(h\UhÙKh]jMhchdhehqhg}rS(hi]hj]hk]hl]ho]uhqKhrhhs]ubaubhê)rT}rU(h\XNDo I need to do any post processing on PDK files generated by Pin Mux Utility?rVh]jíhchdhehîhg}rW(hl]rXUMdo-i-need-to-do-any-post-processing-on-pdk-files-generated-by-pin-mux-utilityrYahk]hi]hj]ho]rZhauhqNhrhhs]r[h|XNDo I need to do any post processing on PDK files generated by Pin Mux Utility?r\…r]}r^(h\jVh]jTubaubh›)r_}r`(h\XúThe Pin Mux utility is designed to automate the integration of a custom-designed SOC pin map into the board library software. For AM335x, AM437x, and K2G devices, the PDK files generated by the utility can be integrated into the board library without any manual edits to the files. For AM57x users, there are system design-level considerations that require the user to manually select IO delay modes for specific peripherals, which may require manual intervention before integrating with the board library.rah]jíhchdhehŸhg}rb(hi]hj]hk]hl]ho]uhqM[hrhhs]rch|XúThe Pin Mux utility is designed to automate the integration of a custom-designed SOC pin map into the board library software. For AM335x, AM437x, and K2G devices, the PDK files generated by the utility can be integrated into the board library without any manual edits to the files. For AM57x users, there are system design-level considerations that require the user to manually select IO delay modes for specific peripherals, which may require manual intervention before integrating with the board library.rd…re}rf(h\jah]j_ubaubh›)rg}rh(h\X+An example for modifying the Pin Mux in the board library to modify the UART instance on AM335x is provided in the wiki article `Processor SDK RTOS Customization `__.h]jíhchdhehŸhg}ri(hi]hj]hk]hl]ho]uhqMdhrhhs]rj(h|X€An example for modifying the Pin Mux in the board library to modify the UART instance on AM335x is provided in the wiki article rk…rl}rm(h\X€An example for modifying the Pin Mux in the board library to modify the UART instance on AM335x is provided in the wiki article h]jgubh´)rn}ro(h\Xª`Processor SDK RTOS Customization `__hg}rp(UnameX Processor SDK RTOS Customizationh¸Xƒhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_Customization:_Modifying_Board_library_to_change_UART_instance_on_AM335xhl]hk]hi]hj]ho]uh]jghs]rqh|X Processor SDK RTOS Customizationrr…rs}rt(h\Uh]jnubaheh¾ubh|X.…ru}rv(h\X.h]jgubeubh›)rw}rx(h\X**For More Information:** Refer to `Application Development Using Processor SDK RTOS Training `__ and `Application Notes on AM57xx Pin Multiplexing Utilities `__.h]jíhchdhehŸhg}ry(hi]hj]hk]hl]ho]uhqMihrhhs]rz(j\)r{}r|(h\X**For More Information:**hg}r}(hi]hj]hk]hl]ho]uh]jwhs]r~h|XFor More Information:r…r€}r(h\Uh]j{ubahejdubh|X Refer to r‚…rƒ}r„(h\X Refer to h]jwubh´)r…}r†(h\X’`Application Development Using Processor SDK RTOS Training `__hg}r‡(UnameX9Application Development Using Processor SDK RTOS Trainingh¸XRhttp://training.ti.com/application-development-using-processor-sdk-rtos/index.htmlhl]hk]hi]hj]ho]uh]jwhs]rˆh|X9Application Development Using Processor SDK RTOS Trainingr‰…rŠ}r‹(h\Uh]j…ubaheh¾ubh|X and rŒ…r}rŽ(h\X and h]jwubh´)r}r(h\X^`Application Notes on AM57xx Pin Multiplexing Utilities `__hg}r‘(UnameX6Application Notes on AM57xx Pin Multiplexing Utilitiesh¸X!http://www.ti.com/lit/pdf/sprac44hl]hk]hi]hj]ho]uh]jwhs]r’h|X6Application Notes on AM57xx Pin Multiplexing Utilitiesr“…r”}r•(h\Uh]jubaheh¾ubh|X.…r–}r—(h\X.h]jwubeubhê)r˜}r™(h\X1How can I modify PLL settings in board libraries?ršh]jíhchdhehîhg}r›(hl]rœU0how-can-i-modify-pll-settings-in-board-librariesrahk]hi]hj]ho]ržh auhqNhrhhs]rŸh|X1How can I modify PLL settings in board libraries?r …r¡}r¢(h\jšh]j˜ubaubh›)r£}r¤(h\XÉThe SOC board library in the PDK configures the SOC PLL and module clock settings to the nominal settings required to be used with the TI evaluation platform. If you want to use different clock settings due to power consideration, or if you are using a variant of the device that needs to be clocked differently, you can enter the PLL and clock settings in the board library. All of the PLL and module clock settings are consolidated in the following files:r¥h]jíhchdhehŸhg}r¦(hi]hj]hk]hl]ho]uhqMrhrhhs]r§h|XÉThe SOC board library in the PDK configures the SOC PLL and module clock settings to the nominal settings required to be used with the TI evaluation platform. If you want to use different clock settings due to power consideration, or if you are using a variant of the device that needs to be clocked differently, you can enter the PLL and clock settings in the board library. All of the PLL and module clock settings are consolidated in the following files:r¨…r©}rª(h\j¥h]j£ubaubj)r«}r¬(h\Uh]jíhchdhejhg}r­(jX-hl]hk]hi]hj]ho]uhqMzhrhhs]r®(j)r¯}r°(h\X‡.c: Contains calls related to all board-level initialization. refers to the evaluation platform (For example, evmam335x)h]j«hchdhejhg}r±(hi]hj]hk]hl]ho]uhqNhrhhs]r²h›)r³}r´(h\X‡.c: Contains calls related to all board-level initialization. refers to the evaluation platform (For example, evmam335x)rµh]j¯hchdhehŸhg}r¶(hi]hj]hk]hl]ho]uhqMzhs]r·h|X‡.c: Contains calls related to all board-level initialization. refers to the evaluation platform (For example, evmam335x)r¸…r¹}rº(h\jµh]j³ubaubaubj)r»}r¼(h\Xr_pll.c: Defines the Board_PLLInit() function that configures the dividers and multipliers for the clock tree.h]j«hchdhejhg}r½(hi]hj]hk]hl]ho]uhqNhrhhs]r¾h›)r¿}rÀ(h\Xr_pll.c: Defines the Board_PLLInit() function that configures the dividers and multipliers for the clock tree.rÁh]j»hchdhehŸhg}rÂ(hi]hj]hk]hl]ho]uhqM|hs]rÃh|Xr_pll.c: Defines the Board_PLLInit() function that configures the dividers and multipliers for the clock tree.rÄ…rÅ}rÆ(h\jÁh]j¿ubaubaubj)rÇ}rÈ(h\X‚_clock.c: Defines clock dividers, scalars, and multipliers for individual board modules initialized using the board library. h]j«hchdhejhg}rÉ(hi]hj]hk]hl]ho]uhqNhrhhs]rÊh›)rË}rÌ(h\X_clock.c: Defines clock dividers, scalars, and multipliers for individual board modules initialized using the board library.rÍh]jÇhchdhehŸhg}rÎ(hi]hj]hk]hl]ho]uhqM~hs]rÏh|X_clock.c: Defines clock dividers, scalars, and multipliers for individual board modules initialized using the board library.rÐ…rÑ}rÒ(h\jÍh]jËubaubaubeubhê)rÓ}rÔ(h\X}Can you provide an example of modifying a board library to use a different peripheral instance as compared to the EVM design?rÕh]jíhchdhehîhg}rÖ(hl]r×U|can-you-provide-an-example-of-modifying-a-board-library-to-use-a-different-peripheral-instance-as-compared-to-the-evm-designrØahk]hi]hj]ho]rÙh1auhqNhrhhs]rÚh|X}Can you provide an example of modifying a board library to use a different peripheral instance as compared to the EVM design?rÛ…rÜ}rÝ(h\jÕh]jÓubaubh›)rÞ}rß(h\XÏA good example of the steps involved in modifying a peripheral instance is provided in the application note "`Processor SDK RTOS Customization: Modifying UART Instance `__"h]jíhchdhehŸhg}rà(hi]hj]hk]hl]ho]uhqM…hrhhs]rá(h|XmA good example of the steps involved in modifying a peripheral instance is provided in the application note "râ…rã}rä(h\XmA good example of the steps involved in modifying a peripheral instance is provided in the application note "h]jÞubh´)rå}ræ(h\Xa`Processor SDK RTOS Customization: Modifying UART Instance `__hg}rç(UnameX9Processor SDK RTOS Customization: Modifying UART Instanceh¸X!http://www.ti.com/lit/pdf/sprac32hl]hk]hi]hj]ho]uh]jÞhs]rèh|X9Processor SDK RTOS Customization: Modifying UART Instanceré…rê}rë(h\Uh]jåubaheh¾ubh|X"…rì}rí(h\X"h]jÞubeubhÐ)rî}rï(h\Uh]jíhchdhehÓhg}rð(hi]hj]hk]hl]ho]uhqMŠhrhhs]rñhÖ)rò}ró(h\UhÙKh]jîhchdhehqhg}rô(hi]hj]hk]hl]ho]uhqKhrhhs]ubaubeubeubh^)rõ}rö(h\Uh]hahchdhehfhg}r÷(hi]hj]hk]hl]røUsecondary-bootloaderrùaho]rúhauhqMhrhhs]rû(hu)rü}rý(h\XSecondary Bootloaderrþh]jõhchdhehyhg}rÿ(hi]hj]hk]hl]ho]uhqMhrhhs]rh|XSecondary Bootloaderr…r}r(h\jþh]jüubaubhê)r}r(h\XmWhat board initialization is required in the application after booting using the Secondary Boot Loader (SBL)?rh]jõhchdhehîhg}r(hl]rUjwhat-board-initialization-is-required-in-the-application-after-booting-using-the-secondary-boot-loader-sblr ahk]hi]hj]ho]r h0auhqNhrhhs]r h|XmWhat board initialization is required in the application after booting using the Secondary Boot Loader (SBL)?r …r }r(h\jh]jubaubh›)r}r(h\X›SBL calls the board library to set up the PLL clock, DDR, and Pin Mux, and to power on slave cores and the I/O peripheral from which it will boot the application. Excluding those just mentioned, any other configuration need to be done from the application code. As long as you have added all of the device initialization to the board library, you will not need to add any initialization code in the application.rh]jõhchdhehŸhg}r(hi]hj]hk]hl]ho]uhqM“hrhhs]rh|X›SBL calls the board library to set up the PLL clock, DDR, and Pin Mux, and to power on slave cores and the I/O peripheral from which it will boot the application. Excluding those just mentioned, any other configuration need to be done from the application code. As long as you have added all of the device initialization to the board library, you will not need to add any initialization code in the application.r…r}r(h\jh]jubaubj?)r}r(h\X§For AM57xx devices, the AVS and ABB settings required for all core rails is added to the SBL code, as this initialization is required only in a production environment.h]jõhchdhejBhg}r(hi]hj]hk]hl]ho]uhqNhrhhs]rh›)r}r(h\X§For AM57xx devices, the AVS and ABB settings required for all core rails is added to the SBL code, as this initialization is required only in a production environment.rh]jhchdhehŸhg}r(hi]hj]hk]hl]ho]uhqM›hs]rh|X§For AM57xx devices, the AVS and ABB settings required for all core rails is added to the SBL code, as this initialization is required only in a production environment.r …r!}r"(h\jh]jubaubaubhê)r#}r$(h\X=Where do I locate flashing and boot utilities in the package?r%h]jõhchdhehîhg}r&(hl]r'U`h]jõhchdhehŸhg}r0(hi]hj]hk]hl]ho]uhqM¤hrhhs]r1(h|X|The documentation for the booting and flashing of images to EVMs using Processor SDK RTOS is provided from the wiki article r2…r3}r4(h\X|The documentation for the booting and flashing of images to EVMs using Processor SDK RTOS is provided from the wiki article h]j.ubjh)r5}r6(h\X<:ref:`Processor SDK RTOS Boot Documentation `r7h]j.hchdhejlhg}r8(UreftypeXrefjnˆjoX fc-boot-labelU refdomainXstdr9hl]hk]U refexplicitˆhi]hj]ho]jqhuhqM¤hs]r:js)r;}r<(h\j7hg}r=(hi]hj]r>(jxj9Xstd-refr?ehk]hl]ho]uh]j5hs]r@h|X%Processor SDK RTOS Boot DocumentationrA…rB}rC(h\Uh]j;ubahej~ubaubeubh›)rD}rE(h\X¬The :ref:`Boot and Flashing Utilities ` for all devices is located in the PDK package under the path pdk__x_x_x\\packages\\ti\\boot\\sbl\\tools.h]jõhchdhehŸhg}rF(hi]hj]hk]hl]ho]uhqM¨hrhhs]rG(h|XThe rH…rI}rJ(h\XThe h]jDubjh)rK}rL(h\X2:ref:`Boot and Flashing Utilities `rMh]jDhchdhejlhg}rN(UreftypeXrefjnˆjoX fc-boot-labelU refdomainXstdrOhl]hk]U refexplicitˆhi]hj]ho]jqhuhqM¨hs]rPjs)rQ}rR(h\jMhg}rS(hi]hj]rT(jxjOXstd-refrUehk]hl]ho]uh]jKhs]rVh|XBoot and Flashing UtilitiesrW…rX}rY(h\Uh]jQubahej~ubaubh|Xq for all devices is located in the PDK package under the path pdk__x_x_x\packages\ti\boot\sbl\tools.rZ…r[}r\(h\Xv for all devices is located in the PDK package under the path pdk__x_x_x\\packages\\ti\\boot\\sbl\\tools.h]jDubeubh›)r]}r^(h\XˆThe SDK provides secondary bootloader code for all devices, which is loaded by the ROM bootloader. The SBL is responsible for device initialization, waking up secondary cores, and deployment of the application code on different cores on multi-core devices. On single core devices, the SBL is used to manage the device initialization, as well as loading and running applications on the device.r_h]jõhchdhehŸhg}r`(hi]hj]hk]hl]ho]uhqM¬hrhhs]rah|XˆThe SDK provides secondary bootloader code for all devices, which is loaded by the ROM bootloader. The SBL is responsible for device initialization, waking up secondary cores, and deployment of the application code on different cores on multi-core devices. On single core devices, the SBL is used to manage the device initialization, as well as loading and running applications on the device.rb…rc}rd(h\j_h]j]ubaubh›)re}rf(h\X\Depending on the boot design you need to implement, the boot and flashing tools that are used for formatting and booting the SBL can also be leveraged to format and boot the application image directly. The flash-writing utilities for different EVMs can be located under the path pdk__x_x_x\\packages\\ti\\boot\\sbl\\tools\\flashWriter.h]jõhchdhehŸhg}rg(hi]hj]hk]hl]ho]uhqM³hrhhs]rhh|XVDepending on the boot design you need to implement, the boot and flashing tools that are used for formatting and booting the SBL can also be leveraged to format and boot the application image directly. The flash-writing utilities for different EVMs can be located under the path pdk__x_x_x\packages\ti\boot\sbl\tools\flashWriter.ri…rj}rk(h\X\Depending on the boot design you need to implement, the boot and flashing tools that are used for formatting and booting the SBL can also be leveraged to format and boot the application image directly. The flash-writing utilities for different EVMs can be located under the path pdk__x_x_x\\packages\\ti\\boot\\sbl\\tools\\flashWriter.h]jeubaubh›)rl}rm(h\XIf the intent is to restore the KeyStone II EVM to factory settings, then the `Program EVM Script `__ enables users to program the flash on the EVM using the pre-built firmware images provided by TI/board manufacturer.h]jõhchdhehŸhg}rn(hi]hj]hk]hl]ho]uhqM¹hrhhs]ro(h|XNIf the intent is to restore the KeyStone II EVM to factory settings, then the rp…rq}rr(h\XNIf the intent is to restore the KeyStone II EVM to factory settings, then the h]jlubh´)rs}rt(h\XW`Program EVM Script `__hg}ru(UnameXProgram EVM Scripth¸X>How_to_Guides.html#flash-bootable-images-c66x-k2h-k2e-k2l-onlyhl]hk]hi]hj]ho]uh]jlhs]rvh|XProgram EVM Scriptrw…rx}ry(h\Uh]jsubaheh¾ubh|Xu enables users to program the flash on the EVM using the pre-built firmware images provided by TI/board manufacturer.rz…r{}r|(h\Xu enables users to program the flash on the EVM using the pre-built firmware images provided by TI/board manufacturer.h]jlubeubhÐ)r}}r~(h\Uh]jõhchdhehÓhg}r(hi]hj]hk]hl]ho]uhqM¾hrhhs]r€hÖ)r}r‚(h\UhÙKh]j}hchdhehqhg}rƒ(hi]hj]hk]hl]ho]uhqKhrhhs]ubaubeubh^)r„}r…(h\Uh]hahchdhehfhg}r†(hi]hj]hk]hl]r‡U diagnosticsrˆaho]r‰hPauhqMÁhrhhs]rŠ(hu)r‹}rŒ(h\X Diagnosticsrh]j„hchdhehyhg}rŽ(hi]hj]hk]hl]ho]uhqMÁhrhhs]rh|X Diagnosticsr…r‘}r’(h\jh]j‹ubaubhê)r“}r”(h\XSHow to I test my EVM functionality? Can I use the same tests on my custom platform?r•h]j„hchdhehîhg}r–(hl]r—UQhow-to-i-test-my-evm-functionality-can-i-use-the-same-tests-on-my-custom-platformr˜ahk]hi]hj]ho]r™h/auhqNhrhhs]ršh|XSHow to I test my EVM functionality? Can I use the same tests on my custom platform?r›…rœ}r(h\j•h]j“ubaubh›)rž}rŸ(h\X¡The Processor SDK RTOS provides unit tests to test interfaces on the EVM as part of diagnostics package that can be found in the package in the path pdk__x_x_x\\packages\\ti\\board\\diag. It also provides a framework to run each of these tests through a command line serial interface. Users can either load the tests using an emulator or they can load them over an SD card to test the EVM functionality.h]j„hchdhehŸhg}r (hi]hj]hk]hl]ho]uhqMÇhrhhs]r¡h|XThe Processor SDK RTOS provides unit tests to test interfaces on the EVM as part of diagnostics package that can be found in the package in the path pdk__x_x_x\packages\ti\board\diag. It also provides a framework to run each of these tests through a command line serial interface. Users can either load the tests using an emulator or they can load them over an SD card to test the EVM functionality.r¢…r£}r¤(h\X¡The Processor SDK RTOS provides unit tests to test interfaces on the EVM as part of diagnostics package that can be found in the package in the path pdk__x_x_x\\packages\\ti\\board\\diag. It also provides a framework to run each of these tests through a command line serial interface. Users can either load the tests using an emulator or they can load them over an SD card to test the EVM functionality.h]jžubaubh›)r¥}r¦(h\X·These tests, like all other examples in the SDK, rely on the board library to perform the SOC and board initialization. So if you have modified the board library to account for the components on your custom hardware, then you should be able to re-use the diagnostic tests while bringing up your custom hardware. Users will link to the new board library and rebuild the diagnostics package to leverage these examples on the custom hardware.r§h]j„hchdhehŸhg}r¨(hi]hj]hk]hl]ho]uhqMÎhrhhs]r©h|X·These tests, like all other examples in the SDK, rely on the board library to perform the SOC and board initialization. So if you have modified the board library to account for the components on your custom hardware, then you should be able to re-use the diagnostic tests while bringing up your custom hardware. Users will link to the new board library and rebuild the diagnostics package to leverage these examples on the custom hardware.rª…r«}r¬(h\j§h]j¥ubaubhÐ)r­}r®(h\Uh]j„hchdhehÓhg}r¯(hi]hj]hk]hl]ho]uhqMÖhrhhs]r°hÖ)r±}r²(h\UhÙKh]j­hchdhehqhg}r³(hi]hj]hk]hl]ho]uhqKhrhhs]ubaubeubh^)r´}rµ(h\Uh]hahchdhehfhg}r¶(hi]hj]hk]hl]r·Ufilesystem-supportr¸aho]r¹hauhqMÙhrhhs]rº(hu)r»}r¼(h\XFilesystem Supportr½h]j´hchdhehyhg}r¾(hi]hj]hk]hl]ho]uhqMÙhrhhs]r¿h|XFilesystem SupportrÀ…rÁ}rÂ(h\j½h]j»ubaubhê)rÃ}rÄ(h\X›What filesystem support if provided by Processor SDK RTOS ? Can I use UBIFS, RAMFS, or FATFS with TI RTOS when using external non-volatile memory devices?rÅh]j´hchdhehîhg}rÆ(hl]rÇU•what-filesystem-support-if-provided-by-processor-sdk-rtos-can-i-use-ubifs-ramfs-or-fatfs-with-ti-rtos-when-using-external-non-volatile-memory-devicesrÈahk]hi]hj]ho]rÉhGauhqNhrhhs]rÊh|X›What filesystem support if provided by Processor SDK RTOS ? Can I use UBIFS, RAMFS, or FATFS with TI RTOS when using external non-volatile memory devices?rË…rÌ}rÍ(h\jÅh]jÃubaubh›)rÎ}rÏ(h\XÌProcessor SDK RTOS only supports use of FATFS filesystem for some devices. For availability of support for your devices check the `Release Notes `__ There are numerous examples for using FATFS with USB driver and SD/MMC driver in the SDK that you can use for reference. The FATFS-specific documentation for Processor SDK RTOS is available in the `FATFS wiki section of the Processor SDK RTOS `__.h]j´hchdhehŸhg}rÐ(hi]hj]hk]hl]ho]uhqMàhrhhs]rÑ(h|X‚Processor SDK RTOS only supports use of FATFS filesystem for some devices. For availability of support for your devices check the rÒ…rÓ}rÔ(h\X‚Processor SDK RTOS only supports use of FATFS filesystem for some devices. For availability of support for your devices check the h]jÎubh´)rÕ}rÖ(h\X7`Release Notes `__hg}r×(UnameX Release Notesh¸X#Release_Specific.html#release-noteshl]hk]hi]hj]ho]uh]jÎhs]rØh|X Release NotesrÙ…rÚ}rÛ(h\Uh]jÕubaheh¾ubh|XÆ There are numerous examples for using FATFS with USB driver and SD/MMC driver in the SDK that you can use for reference. The FATFS-specific documentation for Processor SDK RTOS is available in the rÜ…rÝ}rÞ(h\XÆ There are numerous examples for using FATFS with USB driver and SD/MMC driver in the SDK that you can use for reference. The FATFS-specific documentation for Processor SDK RTOS is available in the h]jÎubh´)rß}rà(h\XL`FATFS wiki section of the Processor SDK RTOS `__hg}rá(UnameX,FATFS wiki section of the Processor SDK RTOSh¸XDevice_Drivers.html#fatfshl]hk]hi]hj]ho]uh]jÎhs]râh|X,FATFS wiki section of the Processor SDK RTOSrã…rä}rå(h\Uh]jßubaheh¾ubh|X.…ræ}rç(h\X.h]jÎubeubhÐ)rè}ré(h\Uh]j´hchdhehÓhg}rê(hi]hj]hk]hl]ho]uhqMèhrhhs]rëhÖ)rì}rí(h\UhÙKh]jèhchdhehqhg}rî(hi]hj]hk]hl]ho]uhqKhrhhs]ubaubeubh^)rï}rð(h\Uh]hahchdhehfhg}rñ(hi]hj]hk]hl]ròUti-rtosróaho]rôhauhqMëhrhhs]rõ(hu)rö}r÷(h\XTI RTOSrøh]jïhchdhehyhg}rù(hi]hj]hk]hl]ho]uhqMëhrhhs]rúh|XTI RTOSrû…rü}rý(h\jøh]jöubaubh^)rþ}rÿ(h\Uh]jïhchdhehfhg}r(hi]hj]hk]hl]rUuseful-resourcesraho]rhauhqMîhrhhs]r(hu)r}r(h\XUseful Resourcesrh]jþhchdhehyhg}r(hi]hj]hk]hl]ho]uhqMîhrhhs]r h|XUseful Resourcesr …r }r (h\jh]jubaubj)r }r(h\Uh]jþhchdhejhg}r(jX-hl]hk]hi]hj]ho]uhqMðhrhhs]r(j)r}r(h\XG`SYSBIOS FAQ `__h]j hchdhejhg}r(hi]hj]hk]hl]ho]uhqNhrhhs]rh›)r}r(h\XG`SYSBIOS FAQ `__rh]jhchdhehŸhg}r(hi]hj]hk]hl]ho]uhqMðhs]rh´)r}r(h\jhg}r(UnameX SYSBIOS FAQh¸X5http://processors.wiki.ti.com/index.php/SYS/BIOS_FAQshl]hk]hi]hj]ho]uh]jhs]rh|X SYSBIOS FAQr…r}r (h\Uh]jubaheh¾ubaubaubj)r!}r"(h\X…`Processor_SDK_RTOS:_TI_RTOS_Tips_And_Tricks `__r#h]j hchdhejhg}r$(hi]hj]hk]hl]ho]uhqNhrhhs]r%h›)r&}r'(h\j#h]j!hchdhehŸhg}r((hi]hj]hk]hl]ho]uhqMòhs]r)h´)r*}r+(h\j#hg}r,(UnameX+Processor_SDK_RTOS:_TI_RTOS_Tips_And_Tricksh¸XShttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS:_TI_RTOS_Tips_And_Trickshl]hk]hi]hj]ho]uh]j&hs]r-h|X+Processor_SDK_RTOS:_TI_RTOS_Tips_And_Tricksr.…r/}r0(h\Uh]j*ubaheh¾ubaubaubj)r1}r2(h\XG`TI RTOS Worskshop `__h]j hchdhejhg}r3(hi]hj]hk]hl]ho]uhqNhrhhs]r4h›)r5}r6(h\XG`TI RTOS Worskshop `__r7h]j1hchdhehŸhg}r8(hi]hj]hk]hl]ho]uhqMóhs]r9h´)r:}r;(h\j7hg}r<(UnameXTI RTOS Worskshoph¸X/https://training.ti.com/ti-rtos-workshop-serieshl]hk]hi]hj]ho]uh]j5hs]r=h|XTI RTOS Worskshopr>…r?}r@(h\Uh]j:ubaheh¾ubaubaubj)rA}rB(h\Xf`SYS/BIOS_with_GCC_(CortexA) `__ h]j hchdhejhg}rC(hi]hj]hk]hl]ho]uhqNhrhhs]rDh›)rE}rF(h\Xe`SYS/BIOS_with_GCC_(CortexA) `__rGh]jAhchdhehŸhg}rH(hi]hj]hk]hl]ho]uhqMõhs]rIh´)rJ}rK(h\jGhg}rL(UnameXSYS/BIOS_with_GCC_(CortexA)h¸XChttp://processors.wiki.ti.com/index.php/SYS/BIOS_with_GCC_(CortexA)hl]hk]hi]hj]ho]uh]jEhs]rMh|XSYS/BIOS_with_GCC_(CortexA)rN…rO}rP(h\Uh]jJubaheh¾ubaubaubeubhÐ)rQ}rR(h\Uh]jþhchdhehÓhg}rS(hi]hj]hk]hl]ho]uhqM÷hrhhs]rThÖ)rU}rV(h\UhÙKh]jQhchdhehqhg}rW(hi]hj]hk]hl]ho]uhqKhrhhs]ubaubhê)rX}rY(h\XjHow do I start writing my TI RTOS application code? Is there any documentation that describes the process?rZh]jþhchdhehîhg}r[(hl]r\Uhhow-do-i-start-writing-my-ti-rtos-application-code-is-there-any-documentation-that-describes-the-processr]ahk]hi]hj]ho]r^h3auhqNhrhhs]r_h|XjHow do I start writing my TI RTOS application code? Is there any documentation that describes the process?r`…ra}rb(h\jZh]jXubaubh›)rc}rd(h\X‡The typical recommendation is to start a TI RTOS project using the predefined templates provided as part of CCS installation and then add custom configuration on top of it. CCS allows users to create a TI RTOS project with Minimum, Typical, and a set of generic examples, as you can see from wiki `Processor SDK RTOS TI RTOS Getting Started Examples `__.h]jþhchdhehŸhg}re(hi]hj]hk]hl]ho]uhqMührhhs]rf(h|X)The typical recommendation is to start a TI RTOS project using the predefined templates provided as part of CCS installation and then add custom configuration on top of it. CCS allows users to create a TI RTOS project with Minimum, Typical, and a set of generic examples, as you can see from wiki rg…rh}ri(h\X)The typical recommendation is to start a TI RTOS project using the predefined templates provided as part of CCS installation and then add custom configuration on top of it. CCS allows users to create a TI RTOS project with Minimum, Typical, and a set of generic examples, as you can see from wiki h]jcubh´)rj}rk(h\X]`Processor SDK RTOS TI RTOS Getting Started Examples `__hg}rl(UnameX3Processor SDK RTOS TI RTOS Getting Started Examplesh¸X#Release_Specific.html#release-noteshl]hk]hi]hj]ho]uh]jchs]rmh|X3Processor SDK RTOS TI RTOS Getting Started Examplesrn…ro}rp(h\Uh]jjubaheh¾ubh|X.…rq}rr(h\X.h]jcubeubh›)rs}rt(h\XøOther than that, there is an TI RTOS workshop that addresses different features and use cases of TI RTOS with CCS: `Introduction to the TI-RTOS Kernel Workshop `__h]jþhchdhehŸhg}ru(hi]hj]hk]hl]ho]uhqMhrhhs]rv(h|XsOther than that, there is an TI RTOS workshop that addresses different features and use cases of TI RTOS with CCS: rw…rx}ry(h\XsOther than that, there is an TI RTOS workshop that addresses different features and use cases of TI RTOS with CCS: h]jsubh´)rz}r{(h\X…`Introduction to the TI-RTOS Kernel Workshop `__hg}r|(UnameX+Introduction to the TI-RTOS Kernel Workshoph¸XShttp://processors.wiki.ti.com/index.php/Introduction_to_the_TI-RTOS_Kernel_Workshophl]hk]hi]hj]ho]uh]jshs]r}h|X+Introduction to the TI-RTOS Kernel Workshopr~…r}r€(h\Uh]jzubaheh¾ubeubh›)r}r‚(h\X‡The TI RTOS component also ships with user documentation that provides information on configuring TI RTOS through scripts APIs and also using the graphical XGCONF tool. Full online API and module documentation is available here: `TI RTOS API Documentation `__h]jþhchdhehŸhg}rƒ(hi]hj]hk]hl]ho]uhqMhrhhs]r„(h|XåThe TI RTOS component also ships with user documentation that provides information on configuring TI RTOS through scripts APIs and also using the graphical XGCONF tool. Full online API and module documentation is available here: r……r†}r‡(h\XåThe TI RTOS component also ships with user documentation that provides information on configuring TI RTOS through scripts APIs and also using the graphical XGCONF tool. Full online API and module documentation is available here: h]jubh´)rˆ}r‰(h\X¢`TI RTOS API Documentation `__hg}rŠ(UnameXTI RTOS API Documentationh¸X‚http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/sysbios/6_46_00_23/exports/bios_6_46_00_23/docs/cdoc/index.htmlhl]hk]hi]hj]ho]uh]jhs]r‹h|XTI RTOS API DocumentationrŒ…r}rŽ(h\Uh]jˆubaheh¾ubeubhê)r}r(h\XJWhat interrupt latency, foot print, etc. can I expect while using TI RTOS?r‘h]jþhchdhehîhg}r’(hl]r“UFwhat-interrupt-latency-foot-print-etc-can-i-expect-while-using-ti-rtosr”ahk]hi]hj]ho]r•hEauhqNhrhhs]r–h|XJWhat interrupt latency, foot print, etc. can I expect while using TI RTOS?r—…r˜}r™(h\j‘h]jubaubh›)rš}r›(h\XuPerformance and size benchmarks are available for every released SYS/BIOS kernel in the TI RTOS package and are shipped as part of the standard product documentation. In addition to the benchmark numbers themselves, .pdf files provide a detailed description of how the benchmarks were implemented. For example, whether they were implemented in internal or external memory..rœh]jþhchdhehŸhg}r(hi]hj]hk]hl]ho]uhqMhrhhs]ržh|XuPerformance and size benchmarks are available for every released SYS/BIOS kernel in the TI RTOS package and are shipped as part of the standard product documentation. In addition to the benchmark numbers themselves, .pdf files provide a detailed description of how the benchmarks were implemented. For example, whether they were implemented in internal or external memory..rŸ…r }r¡(h\jœh]jšubaubh›)r¢}r£(h\XÞIf you do not have access to a release, you can access the release notes (and thereby the benchmarks) online by clicking on the following link and going to the download link for the TI RTOS version that is part of the SDK.r¤h]jþhchdhehŸhg}r¥(hi]hj]hk]hl]ho]uhqMhrhhs]r¦h|XÞIf you do not have access to a release, you can access the release notes (and thereby the benchmarks) online by clicking on the following link and going to the download link for the TI RTOS version that is part of the SDK.r§…r¨}r©(h\j¤h]j¢ubaubj)rª}r«(h\Uh]jþhchdhejhg}r¬(jX-hl]hk]hi]hj]ho]uhqMhrhhs]r­j)r®}r¯(h\Xs`SYS/BIOS Releases `__ h]jªhchdhejhg}r°(hi]hj]hk]hl]ho]uhqNhrhhs]r±h›)r²}r³(h\Xr`SYS/BIOS Releases `__r´h]j®hchdhehŸhg}rµ(hi]hj]hk]hl]ho]uhqMhs]r¶h´)r·}r¸(h\j´hg}r¹(UnameXSYS/BIOS Releasesh¸XZhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/bios/sysbios/index.htmlhl]hk]hi]hj]ho]uh]j²hs]rºh|XSYS/BIOS Releasesr»…r¼}r½(h\Uh]j·ubaheh¾ubaubaubaubh›)r¾}r¿(h\XìThis link enables you to access any TI RTOS products and their associated release notes. The release notes may be browsed directly. There is no need to download the whole product. You will need to have a my.ti login to access this site.rÀh]jþhchdhehŸhg}rÁ(hi]hj]hk]hl]ho]uhqM!hrhhs]rÂh|XìThis link enables you to access any TI RTOS products and their associated release notes. The release notes may be browsed directly. There is no need to download the whole product. You will need to have a my.ti login to access this site.rÃ…rÄ}rÅ(h\jÀh]j¾ubaubh›)rÆ}rÇ(h\X™Within the SDK package, TI-RTOS Benchmark Documentation can be found under directory path *bios_6_xx_xx_xx\\packages\\ti\\sysbios\\benchmarks\\doc-files*h]jþhchdhehŸhg}rÈ(hi]hj]hk]hl]ho]uhqM&hrhhs]rÉ(h|XZWithin the SDK package, TI-RTOS Benchmark Documentation can be found under directory path rÊ…rË}rÌ(h\XZWithin the SDK package, TI-RTOS Benchmark Documentation can be found under directory path h]jÆubcdocutils.nodes emphasis rÍ)rÎ}rÏ(h\X?*bios_6_xx_xx_xx\\packages\\ti\\sysbios\\benchmarks\\doc-files*hg}rÐ(hi]hj]hk]hl]ho]uh]jÆhs]rÑh|X8bios_6_xx_xx_xx\packages\ti\sysbios\benchmarks\doc-filesrÒ…rÓ}rÔ(h\Uh]jÎubaheUemphasisrÕubeubhê)rÖ}r×(h\X'How do I debug TI-RTOS and driver code?rØh]jþhchdhehîhg}rÙ(hl]rÚU&how-do-i-debug-ti-rtos-and-driver-coderÛahk]hi]hj]ho]rÜhauhqNhrhhs]rÝh|X'How do I debug TI-RTOS and driver code?rÞ…rß}rà(h\jØh]jÖubaubh›)rá}râ(h\X…In order to single step through code, the driver libraries and the TI RTOS libraries should be built with complete symbol definition.rãh]jþhchdhehŸhg}rä(hi]hj]hk]hl]ho]uhqM-hrhhs]råh|X…In order to single step through code, the driver libraries and the TI RTOS libraries should be built with complete symbol definition.ræ…rç}rè(h\jãh]jáubaubh›)ré}rê(h\XëFor building a debug-able version of TI RTOS, please refer to the following article: `Making_a_debug-able_Custom_SYSBIOS_Library `__h]jþhchdhehŸhg}rë(hi]hj]hk]hl]ho]uhqM0hrhhs]rì(h|XUFor building a debug-able version of TI RTOS, please refer to the following article: rí…rî}rï(h\XUFor building a debug-able version of TI RTOS, please refer to the following article: h]jéubh´)rð}rñ(h\X–`Making_a_debug-able_Custom_SYSBIOS_Library `__hg}rò(UnameX*Making_a_debug-able_Custom_SYSBIOS_Libraryh¸Xehttp://processors.wiki.ti.com/index.php/SYS/BIOS_FAQs#1_Making_a_debug-able_Custom_SYS.2FBIOS_Libraryhl]hk]hi]hj]ho]uh]jéhs]róh|X*Making_a_debug-able_Custom_SYSBIOS_Libraryrô…rõ}rö(h\Uh]jðubaheh¾ubeubh›)r÷}rø(h\XProcessor SDK RTOS drivers are already built with full symbol definition. So you should be able to single step into the drivers in the CCS IDE environment. **Note**: You may need to add the source of the SYS/BIOS and the drivers in the source search path in CCS.h]jþhchdhehŸhg}rù(hi]hj]hk]hl]ho]uhqM4hrhhs]rú(h|XœProcessor SDK RTOS drivers are already built with full symbol definition. So you should be able to single step into the drivers in the CCS IDE environment. rû…rü}rý(h\XœProcessor SDK RTOS drivers are already built with full symbol definition. So you should be able to single step into the drivers in the CCS IDE environment. h]j÷ubj\)rþ}rÿ(h\X**Note**hg}r(hi]hj]hk]hl]ho]uh]j÷hs]rh|XNoter…r}r(h\Uh]jþubahejdubh|Xb: You may need to add the source of the SYS/BIOS and the drivers in the source search path in CCS.r…r}r(h\Xb: You may need to add the source of the SYS/BIOS and the drivers in the source search path in CCS.h]j÷ubeubh›)r}r (h\XàAdvanced debug of TI RTOS applications using system analyzer and ROV object viewer is described in the `TI RTOS SYSTEM Anlayzer wiki `__.h]jþhchdhehŸhg}r (hi]hj]hk]hl]ho]uhqM9hrhhs]r (h|XgAdvanced debug of TI RTOS applications using system analyzer and ROV object viewer is described in the r …r }r(h\XgAdvanced debug of TI RTOS applications using system analyzer and ROV object viewer is described in the h]jubh´)r}r(h\Xx`TI RTOS SYSTEM Anlayzer wiki `__hg}r(UnameXTI RTOS SYSTEM Anlayzer wikih¸XUhttp://processors.wiki.ti.com/index.php/How_is_SYS/BIOS_related_to_System_Analyzer%3Fhl]hk]hi]hj]ho]uh]jhs]rh|XTI RTOS SYSTEM Anlayzer wikir…r}r(h\Uh]jubaheh¾ubh|X.…r}r(h\X.h]jubeubhÐ)r}r(h\Uh]jþhchdhehÓhg}r(hi]hj]hk]hl]ho]uhqM=hrhhs]rhÖ)r}r(h\UhÙKh]jhchdhehqhg}r(hi]hj]hk]hl]ho]uhqKhrhhs]ubaubhê)r}r (h\XFHow can I run TI RTOS on secondary ARM cores on multi-core ARM devicesr!h]jþhchdhehîhg}r"(hl]r#UFhow-can-i-run-ti-rtos-on-secondary-arm-cores-on-multi-core-arm-devicesr$ahk]hi]hj]ho]r%hauhqNhrhhs]r&h|XFHow can I run TI RTOS on secondary ARM cores on multi-core ARM devicesr'…r(}r)(h\j!h]jubaubh›)r*}r+(h\X^Processor SDK RTOS supports multiple device that have multi-core ARM like AM572x and Keystone2 devices. In order to run TI RTOS application on the secondary ARM core in non-SMP mode, application developers need to add correct coreID to the configuration to their BIOS configuration to allow the hardware interrupts to be routed to the secondary core.r,h]jþhchdhehŸhg}r-(hi]hj]hk]hl]ho]uhqMChrhhs]r.h|X^Processor SDK RTOS supports multiple device that have multi-core ARM like AM572x and Keystone2 devices. In order to run TI RTOS application on the secondary ARM core in non-SMP mode, application developers need to add correct coreID to the configuration to their BIOS configuration to allow the hardware interrupts to be routed to the secondary core.r/…r0}r1(h\j,h]j*ubaubh›)r2}r3(h\XFor example on AM572x which has 2 A15 cores, to run the TI RTOS example on secondary ARM core, application users need to add :r4h]jþhchdhehŸhg}r5(hi]hj]hk]hl]ho]uhqMIhrhhs]r6h|XFor example on AM572x which has 2 A15 cores, to run the TI RTOS example on secondary ARM core, application users need to add :r7…r8}r9(h\j4h]j2ubaubjÕ)r:}r;(h\XKvar Core = xdc.useModule('ti.sysbios.family.arm.ducati.Core'); Core.id = 1;h]jþhchdhejØhg}r<(jÚjÛhl]hk]hi]hj]ho]uhqMNhrhhs]r=h|XKvar Core = xdc.useModule('ti.sysbios.family.arm.ducati.Core'); Core.id = 1;r>…r?}r@(h\Uh]j:ubaubhÐ)rA}rB(h\Uh]jþhchdhehÓhg}rC(hi]hj]hk]hl]ho]uhqMQhrhhs]rDhÖ)rE}rF(h\UhÙKh]jAhchdhehqhg}rG(hi]hj]hk]hl]ho]uhqKhrhhs]ubaubhê)rH}rI(h\X…Why do I get a "undefined reference to \`ti_sysbios_rts_gnu_ReentSupport_checkIfCorrectLibrary'" error when compiling my application?h]jþhchdhehîhg}rJ(hl]rKUwhy-do-i-get-a-undefined-reference-to-ti-sysbios-rts-gnu-reentsupport-checkifcorrectlibrary-error-when-compiling-my-applicationrLahk]hi]hj]ho]rMhauhqNhrhhs]rNh|X„Why do I get a "undefined reference to `ti_sysbios_rts_gnu_ReentSupport_checkIfCorrectLibrary'" error when compiling my application?rO…rP}rQ(h\X…Why do I get a "undefined reference to \`ti_sysbios_rts_gnu_ReentSupport_checkIfCorrectLibrary'" error when compiling my application?h]jHubaubh›)rR}rS(h\XJYou may have encountered this error when building an application for ARM using makefile and not using CCS. You will need to link in the proper C runtime library from SYS/BIOS. Double check the makefile(s) and make sure that you are using libc, libgcc, libm, etc. from the SYS/BIOS package and not from your toolchain (GCC Linaro).rTh]jþhchdhehŸhg}rU(hi]hj]hk]hl]ho]uhqMXhrhhs]rVh|XJYou may have encountered this error when building an application for ARM using makefile and not using CCS. You will need to link in the proper C runtime library from SYS/BIOS. Double check the makefile(s) and make sure that you are using libc, libgcc, libm, etc. from the SYS/BIOS package and not from your toolchain (GCC Linaro).rW…rX}rY(h\jTh]jRubaubh›)rZ}r[(h\XpFor additional information, refer to: `What do I need to do to make the C runtime library re-entrant when building SYS/BIOS applications for Cortex-A GNU targets `__h]jþhchdhehŸhg}r\(hi]hj]hk]hl]ho]uhqM^hrhhs]r](h|X&For additional information, refer to: r^…r_}r`(h\X&For additional information, refer to: h]jZubh´)ra}rb(h\XJ`What do I need to do to make the C runtime library re-entrant when building SYS/BIOS applications for Cortex-A GNU targets `__hg}rc(UnameXzWhat do I need to do to make the C runtime library re-entrant when building SYS/BIOS applications for Cortex-A GNU targetsh¸XÉhttp://processors.wiki.ti.com/index.php/SYS/BIOS_with_GCC_(CortexA)#What_do_I_need_to_do_to_make_the_C_runtime_library_re-entrant_when_building_SYS.2FBIOS_applications_for_Cortex-A_GNU_targets.C2.A0.3Fhl]hk]hi]hj]ho]uh]jZhs]rdh|XzWhat do I need to do to make the C runtime library re-entrant when building SYS/BIOS applications for Cortex-A GNU targetsre…rf}rg(h\Uh]jaubaheh¾ubeubhê)rh}ri(h\X-Where do I post questions on generic TI RTOS?rjh]jþhchdhehîhg}rk(hl]rlU,where-do-i-post-questions-on-generic-ti-rtosrmahk]hi]hj]ho]rnh auhqNhrhhs]roh|X-Where do I post questions on generic TI RTOS?rp…rq}rr(h\jjh]jhubaubh›)rs}rt(h\XÎWe recommend that all TI RTOS users review the list of TI RTOS frequently asked questions on the `TI RTOS FAQ `__ page prior to posting the questions on the E2E forum. If the question is not specific to the Processor SDK RTOS drivers, but relates to configuration of a specific module inside TI RTOS, then please post the questions on the `TI RTOS E2E Forum `__.h]jþhchdhehŸhg}ru(hi]hj]hk]hl]ho]uhqMfhrhhs]rv(h|XaWe recommend that all TI RTOS users review the list of TI RTOS frequently asked questions on the rw…rx}ry(h\XaWe recommend that all TI RTOS users review the list of TI RTOS frequently asked questions on the h]jsubh´)rz}r{(h\XG`TI RTOS FAQ `__hg}r|(UnameX TI RTOS FAQh¸X5http://processors.wiki.ti.com/index.php/SYS/BIOS_FAQshl]hk]hi]hj]ho]uh]jshs]r}h|X TI RTOS FAQr~…r}r€(h\Uh]jzubaheh¾ubh|Xâ page prior to posting the questions on the E2E forum. If the question is not specific to the Processor SDK RTOS drivers, but relates to configuration of a specific module inside TI RTOS, then please post the questions on the r…r‚}rƒ(h\Xâ page prior to posting the questions on the E2E forum. If the question is not specific to the Processor SDK RTOS drivers, but relates to configuration of a specific module inside TI RTOS, then please post the questions on the h]jsubh´)r„}r…(h\XC`TI RTOS E2E Forum `__hg}r†(UnameXTI RTOS E2E Forumh¸X+https://e2e.ti.com/support/embedded/tirtos/hl]hk]hi]hj]ho]uh]jshs]r‡h|XTI RTOS E2E Forumrˆ…r‰}rŠ(h\Uh]j„ubaheh¾ubh|X.…r‹}rŒ(h\X.h]jsubeubhê)r}rŽ(h\XjWhen load a RTOS example to DSP2, the code stuck at timer.c before go main(), but the same worked on DSP1?rh]jþhchdhehîhg}r(hl]r‘Uewhen-load-a-rtos-example-to-dsp2-the-code-stuck-at-timer-c-before-go-main-but-the-same-worked-on-dsp1r’ahk]hi]hj]ho]r“hQauhqNhrhhs]r”h|XjWhen load a RTOS example to DSP2, the code stuck at timer.c before go main(), but the same worked on DSP1?r•…r–}r—(h\jh]jubaubh›)r˜}r™(h\XxBy default, BIOS uses GPtimer5 to source the clock ticks in the BIOS clock module. The GEL is created with the assumption that the DSP1 developers will use GPtimer5 and DSP2 users will use GPtimer6 to source clock module. This means that DSP2 developers will need to add configuration script to change the clock source to GPtimer6. Try to add the following in your DSP2.cfg :ršh]jþhchdhehŸhg}r›(hi]hj]hk]hl]ho]uhqMrhrhhs]rœh|XxBy default, BIOS uses GPtimer5 to source the clock ticks in the BIOS clock module. The GEL is created with the assumption that the DSP1 developers will use GPtimer5 and DSP2 users will use GPtimer6 to source clock module. This means that DSP2 developers will need to add configuration script to change the clock source to GPtimer6. Try to add the following in your DSP2.cfg :r…rž}rŸ(h\jšh]j˜ubaubjÕ)r }r¡(h\Xivar Clock = xdc.useModule('ti.sysbios.knl.Clock'); Clock.timerId = 5; /* Change BIOS clock to GPTimer6 */h]jþhchdhejØhg}r¢(jÚjÛhl]hk]hi]hj]ho]uhqM{hrhhs]r£h|Xivar Clock = xdc.useModule('ti.sysbios.knl.Clock'); Clock.timerId = 5; /* Change BIOS clock to GPTimer6 */r¤…r¥}r¦(h\Uh]j ubaubhÐ)r§}r¨(h\Uh]jþhchdhehÓhg}r©(hi]hj]hk]hl]ho]uhqM~hrhhs]rªhÖ)r«}r¬(h\UhÙKh]j§hchdhehqhg}r­(hi]hj]hk]hl]ho]uhqKhrhhs]ubaubeubeubh^)r®}r¯(h\Uh]hahchdhehfhg}r°(hi]hj]hk]hl]r±Unetworking-supportr²aho]r³h@auhqMhrhhs]r´(hu)rµ}r¶(h\XNetworking Supportr·h]j®hchdhehyhg}r¸(hi]hj]hk]hl]ho]uhqMhrhhs]r¹h|XNetworking Supportrº…r»}r¼(h\j·h]jµubaubhê)r½}r¾(h\XLCan I use NDK software stack on all devices supported in Processor SDK RTOS?r¿h]j®hchdhehîhg}rÀ(hl]rÁUKcan-i-use-ndk-software-stack-on-all-devices-supported-in-processor-sdk-rtosrÂahk]hi]hj]ho]rÃh8auhqNhrhhs]rÄh|XLCan I use NDK software stack on all devices supported in Processor SDK RTOS?rÅ…rÆ}rÇ(h\j¿h]j½ubaubh›)rÈ}rÉ(h\XThe NDK software stack provided by TI typically requires a transport layer called Network Interface Management Unit (NIMU) layer to interface the underlying platform software elements and device drivers. Please check the `Processor SDK RTOS Release Notes `__ for support of the NIMU transport driver to determine if NDK software can be utilized on your device.h]j®hchdhehŸhg}rÊ(hi]hj]hk]hl]ho]uhqM‡hrhhs]rË(h|XÝThe NDK software stack provided by TI typically requires a transport layer called Network Interface Management Unit (NIMU) layer to interface the underlying platform software elements and device drivers. Please check the rÌ…rÍ}rÎ(h\XÝThe NDK software stack provided by TI typically requires a transport layer called Network Interface Management Unit (NIMU) layer to interface the underlying platform software elements and device drivers. Please check the h]jÈubh´)rÏ}rÐ(h\XJ`Processor SDK RTOS Release Notes `__hg}rÑ(UnameX Processor SDK RTOS Release Notesh¸X#Release_Specific.html#release-noteshl]hk]hi]hj]ho]uh]jÈhs]rÒh|X Processor SDK RTOS Release NotesrÓ…rÔ}rÕ(h\Uh]jÏubaheh¾ubh|Xf for support of the NIMU transport driver to determine if NDK software can be utilized on your device.rÖ…r×}rØ(h\Xf for support of the NIMU transport driver to determine if NDK software can be utilized on your device.h]jÈubeubhê)rÙ}rÚ(h\X4Where do I find the documentation for the NDK stack?rÛh]j®hchdhehîhg}rÜ(hl]rÝU3where-do-i-find-the-documentation-for-the-ndk-stackrÞahk]hi]hj]ho]rßh auhqNhrhhs]ràh|X4Where do I find the documentation for the NDK stack?rá…râ}rã(h\jÛh]jÙubaubh›)rä}rå(h\XAll the networking-related documentation for Processor SDK RTOS, along with the NDK software stack, is linked from the wiki `NDK Documentation and References `__.h]j®hchdhehŸhg}ræ(hi]hj]hk]hl]ho]uhqM‘hrhhs]rç(h|X|All the networking-related documentation for Processor SDK RTOS, along with the NDK software stack, is linked from the wiki rè…ré}rê(h\X|All the networking-related documentation for Processor SDK RTOS, along with the NDK software stack, is linked from the wiki h]jäubh´)rë}rì(h\X‰`NDK Documentation and References `__hg}rí(UnameX NDK Documentation and Referencesh¸Xbhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_NDK#Additional_Documentation_Referenceshl]hk]hi]hj]ho]uh]jähs]rîh|X NDK Documentation and Referencesrï…rð}rñ(h\Uh]jëubaheh¾ubh|X.…rò}ró(h\X.h]jäubeubhÐ)rô}rõ(h\Uh]j®hchdhehÓhg}rö(hi]hj]hk]hl]ho]uhqM–hrhhs]r÷hÖ)rø}rù(h\UhÙKh]jôhchdhehqhg}rú(hi]hj]hk]hl]ho]uhqKhrhhs]ubaubeubh^)rû}rü(h\Uh]hahchdhehfhg}rý(hi]hj]hk]hl]rþU!inter-processor-communication-ipcrÿaho]r hLauhqM™hrhhs]r (hu)r }r (h\X#Inter-processor Communication (IPC)r h]jûhchdhehyhg}r (hi]hj]hk]hl]ho]uhqM™hrhhs]r h|X#Inter-processor Communication (IPC)r …r }r (h\j h]j ubaubhê)r }r (h\X$How do I build and run IPC examples?r h]jûhchdhehîhg}r (hl]r U#how-do-i-build-and-run-ipc-examplesr ahk]hi]hj]ho]r h=auhqNhrhhs]r h|X$How do I build and run IPC examples?r …r }r (h\j h]j ubaubh›)r }r (h\XGIPC and corresponding examples are designed to be built from the top level `Processor SDK RTOS IPC Make Target `__. Please ensure the `Processor SDK RTOS build `__ environments have been set up before running the "make ipc_bios" or [make ipc_examples] option.h]jûhchdhehŸhg}r (hi]hj]hk]hl]ho]uhqMžhrhhs]r (h|XKIPC and corresponding examples are designed to be built from the top level r …r }r (h\XKIPC and corresponding examples are designed to be built from the top level h]j ubh´)r }r (h\XI`Processor SDK RTOS IPC Make Target `__hg}r (UnameX"Processor SDK RTOS IPC Make Targeth¸X Overview.html#additional-targetshl]hk]hi]hj]ho]uh]j hs]r h|X"Processor SDK RTOS IPC Make Targetr …r! }r" (h\Uh]j ubaheh¾ubh|X. Please ensure the r# …r$ }r% (h\X. Please ensure the h]j ubh´)r& }r' (h\X?`Processor SDK RTOS build `__hg}r( (UnameXProcessor SDK RTOS buildh¸X Overview.html#additional-targetshl]hk]hi]hj]ho]uh]j hs]r) h|XProcessor SDK RTOS buildr* …r+ }r, (h\Uh]j& ubaheh¾ubh|X` environments have been set up before running the "make ipc_bios" or [make ipc_examples] option.r- …r. }r/ (h\X` environments have been set up before running the "make ipc_bios" or [make ipc_examples] option.h]j ubeubh›)r0 }r1 (h\XÜThe documentation to run the IPC examples is provided as part of ReadMe.txt in the IPC examples or on a device-specific wiki article like `How to Run AM57x IPC Examples `__.h]jûhchdhehŸhg}r2 (hi]hj]hk]hl]ho]uhqM¤hrhhs]r3 (h|XŠThe documentation to run the IPC examples is provided as part of ReadMe.txt in the IPC examples or on a device-specific wiki article like r4 …r5 }r6 (h\XŠThe documentation to run the IPC examples is provided as part of ReadMe.txt in the IPC examples or on a device-specific wiki article like h]j0 ubh´)r7 }r8 (h\XQ`How to Run AM57x IPC Examples `__hg}r9 (UnameXHow to Run AM57x IPC Examplesh¸X-How_to_Guides.html#run-ipc-examples-on-am572xhl]hk]hi]hj]ho]uh]j0 hs]r: h|XHow to Run AM57x IPC Examplesr; …r< }r= (h\Uh]j7 ubaheh¾ubh|X.…r> }r? (h\X.h]j0 ubeubhê)r@ }rA (h\X$Where can I locate IPC FAQ document?rB h]jûhchdhehîhg}rC (hl]rD U#where-can-i-locate-ipc-faq-documentrE ahk]hi]hj]ho]rF h auhqNhrhhs]rG h|X$Where can I locate IPC FAQ document?rH …rI }rJ (h\jB h]j@ ubaubh›)rK }rL (h\X¼For IPC-related questions, please refer to the `IPC FAQ wiki article `__ that consolidates the FAQ across all multi-core TI processors.h]jûhchdhehŸhg}rM (hi]hj]hk]hl]ho]uhqM¬hrhhs]rN (h|X/For IPC-related questions, please refer to the rO …rP }rQ (h\X/For IPC-related questions, please refer to the h]jK ubh´)rR }rS (h\XN`IPC FAQ wiki article `__hg}rT (UnameXIPC FAQ wiki articleh¸X3http://processors.wiki.ti.com/index.php/IPC_3.x_FAQhl]hk]hi]hj]ho]uh]jK hs]rU h|XIPC FAQ wiki articlerV …rW }rX (h\Uh]jR ubaheh¾ubh|X? that consolidates the FAQ across all multi-core TI processors.rY …rZ }r[ (h\X? that consolidates the FAQ across all multi-core TI processors.h]jK ubeubhê)r\ }r] (h\X5How can I run TI RTOS IPC examples on AM57xx devices?r^ h]jûhchdhehîhg}r_ (hl]r` U4how-can-i-run-ti-rtos-ipc-examples-on-am57xx-devicesra ahk]hi]hj]ho]rb hAauhqNhrhhs]rc h|X5How can I run TI RTOS IPC examples on AM57xx devices?rd …re }rf (h\j^ h]j\ ubaubh›)rg }rh (h\X¯The instructions to run the IPC examples on AM57xx are provided in the wiki article "`Running IPC Examples on AM57xx/DRA7xx `__"h]jûhchdhehŸhg}ri (hi]hj]hk]hl]ho]uhqM³hrhhs]rj (h|XUThe instructions to run the IPC examples on AM57xx are provided in the wiki article "rk …rl }rm (h\XUThe instructions to run the IPC examples on AM57xx are provided in the wiki article "h]jg ubh´)rn }ro (h\XY`Running IPC Examples on AM57xx/DRA7xx `__hg}rp (UnameX%Running IPC Examples on AM57xx/DRA7xxh¸X-How_to_Guides.html#run-ipc-examples-on-am572xhl]hk]hi]hj]ho]uh]jg hs]rq h|X%Running IPC Examples on AM57xx/DRA7xxrr …rs }rt (h\Uh]jn ubaheh¾ubh|X"…ru }rv (h\X"h]jg ubeubhÐ)rw }rx (h\Uh]jûhchdhehÓhg}ry (hi]hj]hk]hl]ho]uhqM·hrhhs]rz hÖ)r{ }r| (h\UhÙKh]jw hchdhehqhg}r} (hi]hj]hk]hl]ho]uhqKhrhhs]ubaubeubh^)r~ }r (h\Uh]hahchdhehfhg}r€ (hi]hj]hk]hl]r Udsp-optimized-librariesr‚ aho]rƒ hauhqMºhrhhs]r„ (hu)r… }r† (h\XDSP-Optimized Librariesr‡ h]j~ hchdhehyhg}rˆ (hi]hj]hk]hl]ho]uhqMºhrhhs]r‰ h|XDSP-Optimized LibrariesrŠ …r‹ }rŒ (h\j‡ h]j… ubaubhê)r }rŽ (h\XaWhy did I encounter a build issue while rebuilding DSPLIB, IMGLIB, or MATHLIB with C6000 CGT 8.x?r h]j~ hchdhehîhg}r (hl]r‘ U^why-did-i-encounter-a-build-issue-while-rebuilding-dsplib-imglib-or-mathlib-with-c6000-cgt-8-xr’ ahk]hi]hj]ho]r“ hDauhqNhrhhs]r” h|XaWhy did I encounter a build issue while rebuilding DSPLIB, IMGLIB, or MATHLIB with C6000 CGT 8.x?r• …r– }r— (h\j h]j ubaubh›)r˜ }r™ (h\XÅThis is a known issue. Please refer to the note provided on the `Software Libraries wiki `__ to fix the issue.h]j~ hchdhehŸhg}rš (hi]hj]hk]hl]ho]uhqMÀhrhhs]r› (h|X@This is a known issue. Please refer to the note provided on the rœ …r }rž (h\X@This is a known issue. Please refer to the note provided on the h]j˜ ubh´)rŸ }r  (h\Xs`Software Libraries wiki `__hg}r¡ (UnameXSoftware Libraries wikih¸XUhttp://processors.wiki.ti.com/index.php/Software_libraries#Library_Object_File_Formathl]hk]hi]hj]ho]uh]j˜ hs]r¢ h|XSoftware Libraries wikir£ …r¤ }r¥ (h\Uh]jŸ ubaheh¾ubh|X to fix the issue.r¦ …r§ }r¨ (h\X to fix the issue.h]j˜ ubeubhê)r© }rª (h\XbWhy does the performance of the DSP Libraries not match with the performance in the documentation?r« h]j~ hchdhehîhg}r¬ (hl]r­ Uawhy-does-the-performance-of-the-dsp-libraries-not-match-with-the-performance-in-the-documentationr® ahk]hi]hj]ho]r¯ hauhqNhrhhs]r° h|XbWhy does the performance of the DSP Libraries not match with the performance in the documentation?r± …r² }r³ (h\j« h]j© ubaubh›)r´ }rµ (h\X!The performance documented in the optimized DSP libraries that are part of the Processor SDK RTOS has been obtained using a C66x simulator interface which only works with a flat memory model. In order to obtain performance similar to the documentation, the user is expected to perform the SOC-specific optimization. This includes placing the data buffers in internal DSP memory, using optimized compiler settings in the application code, enabling cache if buffers are in DDR memory, enabling EDMA for moving data from external memory to L2, etc.r¶ h]j~ hchdhehŸhg}r· (hi]hj]hk]hl]ho]uhqMÉhrhhs]r¸ h|X!The performance documented in the optimized DSP libraries that are part of the Processor SDK RTOS has been obtained using a C66x simulator interface which only works with a flat memory model. In order to obtain performance similar to the documentation, the user is expected to perform the SOC-specific optimization. This includes placing the data buffers in internal DSP memory, using optimized compiler settings in the application code, enabling cache if buffers are in DDR memory, enabling EDMA for moving data from external memory to L2, etc.r¹ …rº }r» (h\j¶ h]j´ ubaubh›)r¼ }r½ (h\XÌThe CSL libraries for the SOC and TI RTOS provide APIs for cache management of instruction memory as well as data memory. There are some useful documents that enable benchmarking on the DSP and ARM cores.r¾ h]j~ hchdhehŸhg}r¿ (hi]hj]hk]hl]ho]uhqMÒhrhhs]rÀ h|XÌThe CSL libraries for the SOC and TI RTOS provide APIs for cache management of instruction memory as well as data memory. There are some useful documents that enable benchmarking on the DSP and ARM cores.rÁ …r }rà (h\j¾ h]j¼ ubaubj)rÄ }rÅ (h\Uh]j~ hchdhejhg}rÆ (jX-hl]hk]hi]hj]ho]uhqMÖhrhhs]rÇ (j)rÈ }rÉ (h\XH`Introduction to DSP Optimization `__h]jÄ hchdhejhg}rÊ (hi]hj]hk]hl]ho]uhqNhrhhs]rË h›)rÌ }rÍ (h\XH`Introduction to DSP Optimization `__rÎ h]jÈ hchdhehŸhg}rÏ (hi]hj]hk]hl]ho]uhqMÖhs]rÐ h´)rÑ }rÒ (h\jÎ hg}rÓ (UnameX Introduction to DSP Optimizationh¸X!http://www.ti.com/lit/pdf/sprabf2hl]hk]hi]hj]ho]uh]jÌ hs]rÔ h|X Introduction to DSP OptimizationrÕ …rÖ }r× (h\Uh]jÑ ubaheh¾ubaubaubj)rØ }rÙ (h\Xu`TI portal for Core Benchmarking `__h]jÄ hchdhejhg}rÚ (hi]hj]hk]hl]ho]uhqNhrhhs]rÛ h›)rÜ }rÝ (h\Xu`TI portal for Core Benchmarking `__rÞ h]jØ hchdhehŸhg}rß (hi]hj]hk]hl]ho]uhqMØhs]rà h´)rá }râ (h\jÞ hg}rã (UnameXTI portal for Core Benchmarkingh¸XOhttp://www.ti.com/lsds/ti/processors/technology/benchmarks/core-benchmarks.pagehl]hk]hi]hj]ho]uh]jÜ hs]rä h|XTI portal for Core Benchmarkingrå …ræ }rç (h\Uh]já ubaheh¾ubaubaubj)rè }ré (h\XO`TI DSP Benchmarking Application Report `__ h]jÄ hchdhejhg}rê (hi]hj]hk]hl]ho]uhqNhrhhs]rë h›)rì }rí (h\XN`TI DSP Benchmarking Application Report `__rî h]jè hchdhehŸhg}rï (hi]hj]hk]hl]ho]uhqMÚhs]rð h´)rñ }rò (h\jî hg}ró (UnameX&TI DSP Benchmarking Application Reporth¸X!http://www.ti.com/lit/pdf/sprac13hl]hk]hi]hj]ho]uh]jì hs]rô h|X&TI DSP Benchmarking Application Reportrõ …rö }r÷ (h\Uh]jñ ubaheh¾ubaubaubeubhÐ)rø }rù (h\Uh]j~ hchdhehÓhg}rú (hi]hj]hk]hl]ho]uhqMÝhrhhs]rû hÖ)rü }rý (h\UhÙKh]jø hchdhehqhg}rþ (hi]hj]hk]hl]ho]uhqKhrhhs]ubaubeubh^)rÿ }r (h\Uh]hahchdhehfhg}r (hi]hj]hk]hl]r U edma-libraryr aho]r h,auhqMàhrhhs]r (hu)r }r (h\X EDMA Libraryr h]jÿ hchdhehyhg}r (hi]hj]hk]hl]ho]uhqMàhrhhs]r h|X EDMA Libraryr …r }r (h\j h]j ubaubhê)r }r (h\X.How do I resolve EDMA instance usage conflict?r h]jÿ hchdhehîhg}r (hl]r U-how-do-i-resolve-edma-instance-usage-conflictr ahk]hi]hj]ho]r h4auhqNhrhhs]r h|X.How do I resolve EDMA instance usage conflict?r …r }r (h\j h]j ubaubh›)r }r (h\XThere are several RTOS driver example projects using EDMA (e.g., PCIE, SPI, UART, and MMCSD). These projects typically can run on A15, DSP, or M4 cores. As a driver example, these projects use the first EDMA instance (EDMA #0), assuming that no others are using it at the system level.r h]jÿ hchdhehŸhg}r (hi]hj]hk]hl]ho]uhqMåhrhhs]r h|XThere are several RTOS driver example projects using EDMA (e.g., PCIE, SPI, UART, and MMCSD). These projects typically can run on A15, DSP, or M4 cores. As a driver example, these projects use the first EDMA instance (EDMA #0), assuming that no others are using it at the system level.r …r }r (h\j h]j ubaubh›)r! }r" (h\XLThere may be an issue if the EDMA instance #0 is already being used in the system. For example, if the A15 core runs Linux and uses the EDMA #0 already, and a user wants to run a Processor SDK RTOS example on C66x with default EDMA #0. To resolve such an issue, please choose an unused instance. For example, EDMA #1 in the example.r# h]jÿ hchdhehŸhg}r$ (hi]hj]hk]hl]ho]uhqMëhrhhs]r% h|XLThere may be an issue if the EDMA instance #0 is already being used in the system. For example, if the A15 core runs Linux and uses the EDMA #0 already, and a user wants to run a Processor SDK RTOS example on C66x with default EDMA #0. To resolve such an issue, please choose an unused instance. For example, EDMA #1 in the example.r& …r' }r( (h\j# h]j! ubaubhê)r) }r* (h\X*CCS 7.1 platform can't be verified warningr+ h]jÿ hchdhehîhg}r, (hl]r- U)ccs-7-1-platform-cant-be-verified-warningr. ahk]hi]hj]ho]r/ h%auhqNhrhhs]r0 h|X*CCS 7.1 platform can't be verified warningr1 …r2 }r3 (h\j+ h]j) ubaubhê)r4 }r5 (h\X¬When I use CCS 7.1 for Processor SDK RTOS 4.0 projects, I saw a warning "Platform name 'ti.platforms.xxxxxx' could not be verified. Your project may not build as expected."r6 h]jÿ hchdhehîhg}r7 (hl]r8 U¥when-i-use-ccs-7-1-for-processor-sdk-rtos-4-0-projects-i-saw-a-warning-platform-name-ti-platforms-xxxxxx-could-not-be-verified-your-project-may-not-build-as-expectedr9 ahk]hi]hj]ho]r: hHauhqNhrhhs]r; h|X¬When I use CCS 7.1 for Processor SDK RTOS 4.0 projects, I saw a warning "Platform name 'ti.platforms.xxxxxx' could not be verified. Your project may not build as expected."r< …r= }r> (h\j6 h]j4 ubaubh›)r? }r@ (h\X±The warning shows in Properties---->General of a CCS project in CCS 7.1. The warning is due to a change made in CCS 7.1, whereby the User Interface tries to verify the project's target/platform name against a list of known names and if it cannot be verified then it shows the warning. The warning, in itself, does not necessarily mean that the target-name is incorrect. Especially in this case where we are looking at a known good project, it is likely showing up because the known target-names list it is checking against is incomplete. Hence you can treat the warning as harmless and ignore it. This causes some confusion we have decided to remove the warning in the next release of CCS.rA h]jÿ hchdhehŸhg}rB (hi]hj]hk]hl]ho]uhqMùhrhhs]rC h|X±The warning shows in Properties---->General of a CCS project in CCS 7.1. The warning is due to a change made in CCS 7.1, whereby the User Interface tries to verify the project's target/platform name against a list of known names and if it cannot be verified then it shows the warning. The warning, in itself, does not necessarily mean that the target-name is incorrect. Especially in this case where we are looking at a known good project, it is likely showing up because the known target-names list it is checking against is incomplete. Hence you can treat the warning as harmless and ignore it. This causes some confusion we have decided to remove the warning in the next release of CCS.rD …rE }rF (h\jA h]j? ubaubhê)rG }rH (h\X(Keystone I and II devices SGMII/MDIO/PHYrI h]jÿ hchdhehîhg}rJ (hl]rK U&keystone-i-and-ii-devices-sgmiimdiophyrL ahk]hi]hj]ho]rM h auhqNhrhhs]rN h|X(Keystone I and II devices SGMII/MDIO/PHYrO …rP }rQ (h\jI h]jG ubaubhê)rR }rS (h\XSHow to setup SGMII interface to a PHY or to another SGMII port without using a PHY?rT h]jÿ hchdhehîhg}rU (hl]rV URhow-to-setup-sgmii-interface-to-a-phy-or-to-another-sgmii-port-without-using-a-phyrW ahk]hi]hj]ho]rX h6auhqNhrhhs]rY h|XSHow to setup SGMII interface to a PHY or to another SGMII port without using a PHY?rZ …r[ }r\ (h\jT h]jR ubaubh›)r] }r^ (h\X³There are 3 SGMII connectivity modes: • SGMII port with PHY attached and auto-negotiation enabled - for connecting to an external PHY • SGMII master to SGMII slave with auto-negotiation enabled - this is for connecting two SGMII devices, one has to be set as master and the other as slave • SGMII port to SGMII port with forced link configuration – generally this is used when one of the ports does not support auto-negotiationr_ h]jÿ hchdhehŸhg}r` (hi]hj]hk]hl]ho]uhqM hrhhs]ra h|X³There are 3 SGMII connectivity modes: • SGMII port with PHY attached and auto-negotiation enabled - for connecting to an external PHY • SGMII master to SGMII slave with auto-negotiation enabled - this is for connecting two SGMII devices, one has to be set as master and the other as slave • SGMII port to SGMII port with forced link configuration – generally this is used when one of the ports does not support auto-negotiationrb …rc }rd (h\j_ h]j] ubaubh›)re }rf (h\X~When a device having an SGMII MAC port is connected to a PHY device, the SGMII MAC is the slave in this link and the PHY is the master. The link is established using auto-negotiation across the SGMII link that is initiated by the master with an expected response by the slave. If the auto-negotiation is not initiated by the link master (PHY), the link will remain down. In TI Keystone EVMs, the Processor with an SGMII MAC port is connected to a PHY, which provides a copper interface to a Gigabit RJ-45 connector. The Processor’s SGMII MAC port is configured as a slave with auto-negotiation enabled. This is done in the Init_SGMII().rg h]jÿ hchdhehŸhg}rh (hi]hj]hk]hl]ho]uhqMhrhhs]ri h|X~When a device having an SGMII MAC port is connected to a PHY device, the SGMII MAC is the slave in this link and the PHY is the master. The link is established using auto-negotiation across the SGMII link that is initiated by the master with an expected response by the slave. If the auto-negotiation is not initiated by the link master (PHY), the link will remain down. In TI Keystone EVMs, the Processor with an SGMII MAC port is connected to a PHY, which provides a copper interface to a Gigabit RJ-45 connector. The Processor’s SGMII MAC port is configured as a slave with auto-negotiation enabled. This is done in the Init_SGMII().rj …rk }rl (h\jg h]je ubaubh›)rm }rn (h\X&When a SGMII MAC port is connected to another SGMII MAC port and auto-negotiation is enabled, one must be configured to emulate a master while the other is a slave. The master port uses the MR_ADV_ABILITY register to determine speed and duplex setting instead of the MR_LP_ADV_ABILITY register.ro h]jÿ hchdhehŸhg}rp (hi]hj]hk]hl]ho]uhqMhrhhs]rq h|X&When a SGMII MAC port is connected to another SGMII MAC port and auto-negotiation is enabled, one must be configured to emulate a master while the other is a slave. The master port uses the MR_ADV_ABILITY register to determine speed and duplex setting instead of the MR_LP_ADV_ABILITY register.rr …rs }rt (h\jo h]jm ubaubh›)ru }rv (h\XAlternately, when an SGMII MAC port is connected to another SGMII MAC port and auto-negotiation is not enabled, or not available, a “forced link†can be established. Again, the MR_ADV_ABILITY register determines the speed and duplex setting. Please refer to the TI KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide, section 3.3, SGMII_CONTROL, MR_ADV_ABILITY and MR_LP_ADV_ABILITY registers for detail. The corresponding CSL code is implemented in packages\\ti\\csl\\src\\ip\\sgmii\\Vx\\csl_cpsgmiiAux.h.h]jÿ hchdhehŸhg}rw (hi]hj]hk]hl]ho]uhqM#hrhhs]rx h|X Alternately, when an SGMII MAC port is connected to another SGMII MAC port and auto-negotiation is not enabled, or not available, a “forced link†can be established. Again, the MR_ADV_ABILITY register determines the speed and duplex setting. Please refer to the TI KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide, section 3.3, SGMII_CONTROL, MR_ADV_ABILITY and MR_LP_ADV_ABILITY registers for detail. The corresponding CSL code is implemented in packages\ti\csl\src\ip\sgmii\Vx\csl_cpsgmiiAux.h.ry …rz }r{ (h\XAlternately, when an SGMII MAC port is connected to another SGMII MAC port and auto-negotiation is not enabled, or not available, a “forced link†can be established. Again, the MR_ADV_ABILITY register determines the speed and duplex setting. Please refer to the TI KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide, section 3.3, SGMII_CONTROL, MR_ADV_ABILITY and MR_LP_ADV_ABILITY registers for detail. The corresponding CSL code is implemented in packages\\ti\\csl\\src\\ip\\sgmii\\Vx\\csl_cpsgmiiAux.h.h]ju ubaubhê)r| }r} (h\XvIn a TI SGMII to FPGA (PHY port) connection, data corruption is observed on egress direction, what could be the cause?r~ h]jÿ hchdhehîhg}r (hl]r€ Uqin-a-ti-sgmii-to-fpga-phy-port-connection-data-corruption-is-observed-on-egress-direction-what-could-be-the-causer ahk]hi]hj]ho]r‚ h&auhqNhrhhs]rƒ h|XvIn a TI SGMII to FPGA (PHY port) connection, data corruption is observed on egress direction, what could be the cause?r„ …r… }r† (h\j~ h]j| ubaubh›)r‡ }rˆ (h\XßFirst to check if the FPGA side is a PHY port or 1000BASE-X media port. There are many similarities but they are not identical. It is important to recognize that from an electrical point of view, the SGMII interface is very similar to the 1000BASE-X interface. Both use 8B/10B encoding, a serial interface and an embedded clock. Systems can operate with SGMII connected to a media port but they are not guaranteed to operate as they are not consistent with the Ethernet standard.r‰ h]jÿ hchdhehŸhg}rŠ (hi]hj]hk]hl]ho]uhqM0hrhhs]r‹ h|XßFirst to check if the FPGA side is a PHY port or 1000BASE-X media port. There are many similarities but they are not identical. It is important to recognize that from an electrical point of view, the SGMII interface is very similar to the 1000BASE-X interface. Both use 8B/10B encoding, a serial interface and an embedded clock. Systems can operate with SGMII connected to a media port but they are not guaranteed to operate as they are not consistent with the Ethernet standard.rŒ …r }rŽ (h\j‰ h]j‡ ubaubh›)r }r (h\XÒAlso, check Rx equalization. Some FPGA may have different choices of robust mode (dynamic feedback equalization, aka DFE) or more basic mode (linear equalizer). The DFE allows better compensation of transmission channel losses by providing a closer adjustment of filter parameters than when using a linear equalizer. However, a DFE cannot remove the pre-cursor of a transmitted bit; it only compensates for the post cursors. Try to use basic mode to see if it helps.r‘ h]jÿ hchdhehŸhg}r’ (hi]hj]hk]hl]ho]uhqM8hrhhs]r“ h|XÒAlso, check Rx equalization. Some FPGA may have different choices of robust mode (dynamic feedback equalization, aka DFE) or more basic mode (linear equalizer). The DFE allows better compensation of transmission channel losses by providing a closer adjustment of filter parameters than when using a linear equalizer. However, a DFE cannot remove the pre-cursor of a transmitted bit; it only compensates for the post cursors. Try to use basic mode to see if it helps.r” …r• }r– (h\j‘ h]j ubaubhê)r— }r˜ (h\X^How do I program the PHY through MDIO interface? I find that TI Init_MDIO() function is empty?r™ h]jÿ hchdhehîhg}rš (hl]r› UZhow-do-i-program-the-phy-through-mdio-interface-i-find-that-ti-init-mdio-function-is-emptyrœ ahk]hi]hj]ho]r h?auhqNhrhhs]rž h|X^How do I program the PHY through MDIO interface? I find that TI Init_MDIO() function is empty?rŸ …r  }r¡ (h\j™ h]j— ubaubh›)r¢ }r£ (h\X×For some TI EVMs, Init_MDIO() is empty because that PHY is configured using pin strapping and no MDIO control is needed to enable it to operate through auto-negotiation in the optimum configuration. Sample CSL code to access PHY via MDIO can be found under packages\\ti\\csl\\src\\ip\\mdio\\Vx\\csl_mdioAux.h. The MDIO user access register is used to communicate with the physical transceiver connected to the MDIO bus, not to a register of the Keystone SOC MDIO itself. The code must be customized for what you want to get or set within the PHY. To do this you must set the correct PHY address and then identify PHY register that you want to access. Those registers are defined in the PHY datasheet, not TI Keystone documents.h]jÿ hchdhehŸhg}r¤ (hi]hj]hk]hl]ho]uhqMDhrhhs]r¥ h|XÐFor some TI EVMs, Init_MDIO() is empty because that PHY is configured using pin strapping and no MDIO control is needed to enable it to operate through auto-negotiation in the optimum configuration. Sample CSL code to access PHY via MDIO can be found under packages\ti\csl\src\ip\mdio\Vx\csl_mdioAux.h. The MDIO user access register is used to communicate with the physical transceiver connected to the MDIO bus, not to a register of the Keystone SOC MDIO itself. The code must be customized for what you want to get or set within the PHY. To do this you must set the correct PHY address and then identify PHY register that you want to access. Those registers are defined in the PHY datasheet, not TI Keystone documents.r¦ …r§ }r¨ (h\X×For some TI EVMs, Init_MDIO() is empty because that PHY is configured using pin strapping and no MDIO control is needed to enable it to operate through auto-negotiation in the optimum configuration. Sample CSL code to access PHY via MDIO can be found under packages\\ti\\csl\\src\\ip\\mdio\\Vx\\csl_mdioAux.h. The MDIO user access register is used to communicate with the physical transceiver connected to the MDIO bus, not to a register of the Keystone SOC MDIO itself. The code must be customized for what you want to get or set within the PHY. To do this you must set the correct PHY address and then identify PHY register that you want to access. Those registers are defined in the PHY datasheet, not TI Keystone documents.h]j¢ ubaubh›)r© }rª (h\XTAfter PHY is programmed, the MDIO controller will continue polling the PHY periodically for status. The PHY Alive Status Register (ALIVE) and PHY Link Status Register (LINK) can be read to monitor this status of the PHY and link (please refer to the TI KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide, section 3.4).r« h]jÿ hchdhehŸhg}r¬ (hi]hj]hk]hl]ho]uhqMPhrhhs]r­ h|XTAfter PHY is programmed, the MDIO controller will continue polling the PHY periodically for status. The PHY Alive Status Register (ALIVE) and PHY Link Status Register (LINK) can be read to monitor this status of the PHY and link (please refer to the TI KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide, section 3.4).r® …r¯ }r° (h\j« h]j© ubaubeubh^)r± }r² (h\Uh]hahchdhehfhg}r³ (hi]hj]hk]hl]r´ U dmsc-sysfwrµ aho]r¶ h)auhqMWhrhhs]r· (hu)r¸ }r¹ (h\X DMSC/SYSFWrº h]j± hchdhehyhg}r» (hi]hj]hk]hl]ho]uhqMWhrhhs]r¼ h|X DMSC/SYSFWr½ …r¾ }r¿ (h\jº h]j¸ ubaubh›)rÀ }rÁ (h\X·Questions and answers found in this section expand on information found in the `System Firmware Public Documentation `__h]j± hchdhehŸhg}r (hi]hj]hk]hl]ho]uhqMYhrhhs]rà (h|XOQuestions and answers found in this section expand on information found in the rÄ …rÅ }rÆ (h\XOQuestions and answers found in this section expand on information found in the h]jÀ ubh´)rÇ }rÈ (h\Xh`System Firmware Public Documentation `__hg}rÉ (UnameX$System Firmware Public Documentationh¸X=http://software-dl.ti.com/tisci/esd/latest/1_intro/index.htmlhl]hk]hi]hj]ho]uh]jÀ hs]rÊ h|X$System Firmware Public DocumentationrË …rÌ }rÍ (h\Uh]jÇ ubaheh¾ubeubhê)rÎ }rÏ (h\XHow do I configure the AM65x MMU to preemptively restrict write access to memory regions protected by SYSFW controlled firewalls?rÐ h]j± hchdhehîhg}rÑ (hi]hj]hk]hl]ho]uhqM_hrhhs]rÒ h|XHow do I configure the AM65x MMU to preemptively restrict write access to memory regions protected by SYSFW controlled firewalls?rÓ …rÔ }rÕ (h\jÐ h]jÎ ubaubh›)rÖ }r× (h\X Device Management & Security Controller (DMSC) uses device firewalls to prevent applications from directly manipulating non-real-time registers. The MMU can optionally be used to mimic the firewall access restrictions enforced by DMSC. Programming the MMU in such a manner allows applications to be compatible with firewall configurations whether or not DMSC firewall support is enabled. Therefore, it is highly recommended that applications configure the MMU to prevent write accesses to these regions as detailed below.rØ h]j± hchdhehŸhg}rÙ (hi]hj]hk]hl]ho]uhqM`hrhhs]rÚ h|X Device Management & Security Controller (DMSC) uses device firewalls to prevent applications from directly manipulating non-real-time registers. The MMU can optionally be used to mimic the firewall access restrictions enforced by DMSC. Programming the MMU in such a manner allows applications to be compatible with firewall configurations whether or not DMSC firewall support is enabled. Therefore, it is highly recommended that applications configure the MMU to prevent write accesses to these regions as detailed below.rÛ …rÜ }rÝ (h\jØ h]jÖ ubaubh›)rÞ }rß (h\XAThe recommendation to keep MMU configuration as restrictive (or more restrictive) than the firewalls always stands as the MMU will give a precise exception at the time the offending instruction is executed. The firewall will give an imprecise data abort that will happen some time after the offending memory access lands.rà h]j± hchdhehŸhg}rá (hi]hj]hk]hl]ho]uhqMhhrhhs]râ h|XAThe recommendation to keep MMU configuration as restrictive (or more restrictive) than the firewalls always stands as the MMU will give a precise exception at the time the offending instruction is executed. The firewall will give an imprecise data abort that will happen some time after the offending memory access lands.rã …rä }rå (h\jà h]jÞ ubaubh›)ræ }rç (h\XiThe following table describes all AM65x MMR regions which must be configured for read only using the MMU.rè h]j± hchdhehŸhg}ré (hi]hj]hk]hl]ho]uhqMnhrhhs]rê h|XiThe following table describes all AM65x MMR regions which must be configured for read only using the MMU.rë …rì }rí (h\jè h]jæ ubaubjü)rî }rï (h\Uh]j± hchdhejÿhg}rð (hi]hj]hk]hl]ho]uhqNhrhhs]rñ j)rò }ró (h\Uhg}rô (hl]hk]hi]hj]ho]UcolsKuh]jî hs]rõ (j)rö }r÷ (h\Uhg}rø (hl]hk]hi]hj]ho]UcolwidthKuh]jò hs]hej ubj)rù }rú (h\Uhg}rû (hl]hk]hi]hj]ho]UcolwidthK uh]jò hs]hej ubj)rü }rý (h\Uhg}rþ (hl]hk]hi]hj]ho]UcolwidthK uh]jò hs]hej ubj)rÿ }r (h\Uhg}r (hl]hk]hi]hj]ho]UcolwidthK uh]jò hs]hej ubj)r }r (h\Uhg}r (hl]hk]hi]hj]ho]UcolwidthKuh]jò hs]hej ubj)r }r (h\Uhg}r (hl]hk]hi]hj]ho]UcolwidthKuh]jò hs]hej ubj)r }r (h\Uhg}r (hi]hj]hk]hl]ho]uh]jò hs]r j)r }r (h\Uhg}r (hi]hj]hk]hl]ho]uh]j hs]r (j)r }r (h\Uhg}r (hi]hj]hk]hl]ho]uh]j hs]r h›)r }r (h\XIP Blockr h]j hchdhehŸhg}r (hi]hj]hk]hl]ho]uhqMrhs]r h|XIP Blockr …r }r (h\j h]j ubaubahej&ubj)r }r (h\Uhg}r (hi]hj]hk]hl]ho]uh]j hs]r h›)r }r! (h\XMMR Region Namer" h]j hchdhehŸhg}r# (hi]hj]hk]hl]ho]uhqMrhs]r$ h|XMMR Region Namer% …r& }r' (h\j" h]j ubaubahej&ubj)r( }r) (h\Uhg}r* (hi]hj]hk]hl]ho]uh]j hs]r+ h›)r, }r- (h\X Start Addressr. h]j( hchdhehŸhg}r/ (hi]hj]hk]hl]ho]uhqMrhs]r0 h|X Start Addressr1 …r2 }r3 (h\j. h]j, ubaubahej&ubj)r4 }r5 (h\Uhg}r6 (hi]hj]hk]hl]ho]uh]j hs]r7 h›)r8 }r9 (h\X End Addressr: h]j4 hchdhehŸhg}r; (hi]hj]hk]hl]ho]uhqMrhs]r< h|X End Addressr= …r> }r? (h\j: h]j8 ubaubahej&ubj)r@ }rA (h\Uhg}rB (hi]hj]hk]hl]ho]uh]j hs]rC h›)rD }rE (h\XMMU Page Start AddressrF h]j@ hchdhehŸhg}rG (hi]hj]hk]hl]ho]uhqMrhs]rH h|XMMU Page Start AddressrI …rJ }rK (h\jF h]jD ubaubahej&ubj)rL }rM (h\Uhg}rN (hi]hj]hk]hl]ho]uh]j hs]rO h›)rP }rQ (h\XMMU Page End AddressrR h]jL hchdhehŸhg}rS (hi]hj]hk]hl]ho]uhqMrhs]rT h|XMMU Page End AddressrU …rV }rW (h\jR h]jP ubaubahej&ubehej3ubahej4ubj5)rX }rY (h\Uhg}rZ (hi]hj]hk]hl]ho]uh]jò hs]r[ (j)r\ }r] (h\Uhg}r^ (hi]hj]hk]hl]ho]uh]jX hs]r_ (j)r` }ra (h\Uhg}rb (hi]hj]hk]hl]ho]uh]j\ hs]rc h›)rd }re (h\X)MCU Navigator UDMASS Interrupt Aggregatorrf h]j` hchdhehŸhg}rg (hi]hj]hk]hl]ho]uhqMuhs]rh h|X)MCU Navigator UDMASS Interrupt Aggregatorri …rj }rk (h\jf h]jd ubaubahej&ubj)rl }rm (h\Uhg}rn (hi]hj]hk]hl]ho]uh]j\ hs]ro h›)rp }rq (h\Xcfgrr h]jl hchdhehŸhg}rs (hi]hj]hk]hl]ho]uhqMuhs]rt h|Xcfgru …rv }rw (h\jr h]jp ubaubahej&ubj)rx }ry (h\Uhg}rz (hi]hj]hk]hl]ho]uh]j\ hs]r{ h›)r| }r} (h\X 0x283C0000r~ h]jx hchdhehŸhg}r (hi]hj]hk]hl]ho]uhqMuhs]r€ h|X 0x283C0000r …r‚ }rƒ (h\j~ h]j| ubaubahej&ubj)r„ }r… (h\Uhg}r† (hi]hj]hk]hl]ho]uh]j\ hs]r‡ h›)rˆ }r‰ (h\X 0x283C001FrŠ h]j„ hchdhehŸhg}r‹ (hi]hj]hk]hl]ho]uhqMuhs]rŒ h|X 0x283C001Fr …rŽ }r (h\jŠ h]jˆ ubaubahej&ubj)r }r‘ (h\Uhg}r’ (hi]hj]hk]hl]ho]uh]j\ hs]r“ h›)r” }r• (h\X 0x00283C0000r– h]j hchdhehŸhg}r— (hi]hj]hk]hl]ho]uhqMuhs]r˜ h|X 0x00283C0000r™ …rš }r› (h\j– h]j” ubaubahej&ubj)rœ }r (h\Uhg}rž (hi]hj]hk]hl]ho]uh]j\ hs]rŸ h›)r  }r¡ (h\X 0x00283D0000r¢ h]jœ hchdhehŸhg}r£ (hi]hj]hk]hl]ho]uhqMuhs]r¤ h|X 0x00283D0000r¥ …r¦ }r§ (h\j¢ h]j  ubaubahej&ubehej3ubj)r¨ }r© (h\Uhg}rª (hi]hj]hk]hl]ho]uh]jX hs]r« (j)r¬ }r­ (h\Uhg}r® (hi]hj]hk]hl]ho]uh]j¨ hs]r¯ h›)r° }r± (h\XMain Navigator UDMAPr² h]j¬ hchdhehŸhg}r³ (hi]hj]hk]hl]ho]uhqMxhs]r´ h|XMain Navigator UDMAPrµ …r¶ }r· (h\j² h]j° ubaubahej&ubj)r¸ }r¹ (h\Uhg}rº (hi]hj]hk]hl]ho]uh]j¨ hs]r» h›)r¼ }r½ (h\Xrflowr¾ h]j¸ hchdhehŸhg}r¿ (hi]hj]hk]hl]ho]uhqMxhs]rÀ h|XrflowrÁ …r }rà (h\j¾ h]j¼ ubaubahej&ubj)rÄ }rÅ (h\Uhg}rÆ (hi]hj]hk]hl]ho]uh]j¨ hs]rÇ h›)rÈ }rÉ (h\X 0x28400000rÊ h]jÄ hchdhehŸhg}rË (hi]hj]hk]hl]ho]uhqMxhs]rÌ h|X 0x28400000rÍ …rÎ }rÏ (h\jÊ h]jÈ ubaubahej&ubj)rÐ }rÑ (h\Uhg}rÒ (hi]hj]hk]hl]ho]uh]j¨ hs]rÓ h›)rÔ }rÕ (h\X 0x28401FFFrÖ h]jÐ hchdhehŸhg}r× (hi]hj]hk]hl]ho]uhqMxhs]rØ h|X 0x28401FFFrÙ …rÚ }rÛ (h\jÖ h]jÔ ubaubahej&ubj)rÜ }rÝ (h\Uhg}rÞ (hi]hj]hk]hl]ho]uh]j¨ hs]rß h›)rà }rá (h\X 0x0028400000râ h]jÜ hchdhehŸhg}rã (hi]hj]hk]hl]ho]uhqMxhs]rä h|X 0x0028400000rå …ræ }rç (h\jâ h]jà ubaubahej&ubj)rè }ré (h\Uhg}rê (hi]hj]hk]hl]ho]uh]j¨ hs]rë h›)rì }rí (h\X 0x0028410000rî h]jè hchdhehŸhg}rï (hi]hj]hk]hl]ho]uhqMxhs]rð h|X 0x0028410000rñ …rò }ró (h\jî h]jì ubaubahej&ubehej3ubj)rô }rõ (h\Uhg}rö (hi]hj]hk]hl]ho]uh]jX hs]r÷ (j)rø }rù (h\Uhg}rú (hi]hj]hk]hl]ho]uh]jô hs]rû h›)rü }rý (h\XMCU Navigator Ring Acceleratorrþ h]jø hchdhehŸhg}rÿ (hi]hj]hk]hl]ho]uhqMzhs]r h|XMCU Navigator Ring Acceleratorr …r }r (h\jþ h]jü ubaubahej&ubj)r }r (h\Uhg}r (hi]hj]hk]hl]ho]uh]jô hs]r h›)r }r (h\Xcfgr h]j hchdhehŸhg}r (hi]hj]hk]hl]ho]uhqMzhs]r h|Xcfgr …r }r (h\j h]j ubaubahej&ubj)r }r (h\Uhg}r (hi]hj]hk]hl]ho]uh]jô hs]r h›)r }r (h\X 0x28440000r h]j hchdhehŸhg}r (hi]hj]hk]hl]ho]uhqMzhs]r h|X 0x28440000r …r }r (h\j h]j ubaubahej&ubj)r }r (h\Uhg}r (hi]hj]hk]hl]ho]uh]jô hs]r h›)r }r! (h\X 0x2847FFFFr" h]j hchdhehŸhg}r# (hi]hj]hk]hl]ho]uhqMzhs]r$ h|X 0x2847FFFFr% …r& }r' (h\j" h]j ubaubahej&ubj)r( }r) (h\Uhg}r* (hi]hj]hk]hl]ho]uh]jô hs]r+ h›)r, }r- (h\X 0x0028440000r. h]j( hchdhehŸhg}r/ (hi]hj]hk]hl]ho]uhqMzhs]r0 h|X 0x0028440000r1 …r2 }r3 (h\j. h]j, ubaubahej&ubj)r4 }r5 (h\Uhg}r6 (hi]hj]hk]hl]ho]uh]jô hs]r7 h›)r8 }r9 (h\X 0x0028450000r: h]j4 hchdhehŸhg}r; (hi]hj]hk]hl]ho]uhqMzhs]r< h|X 0x0028450000r= …r> }r? (h\j: h]j8 ubaubahej&ubehej3ubj)r@ }rA (h\Uhg}rB (hi]hj]hk]hl]ho]uh]jX hs]rC (j)rD }rE (h\Uhg}rF (hi]hj]hk]hl]ho]uh]j@ hs]rG h›)rH }rI (h\X)MCU Navigator UDMASS Interrupt AggregatorrJ h]jD hchdhehŸhg}rK (hi]hj]hk]hl]ho]uhqM}hs]rL h|X)MCU Navigator UDMASS Interrupt AggregatorrM …rN }rO (h\jJ h]jH ubaubahej&ubj)rP }rQ (h\Uhg}rR (hi]hj]hk]hl]ho]uh]j@ hs]rS h›)rT }rU (h\XgcntcfgrV h]jP hchdhehŸhg}rW (hi]hj]hk]hl]ho]uhqM}hs]rX h|XgcntcfgrY …rZ }r[ (h\jV h]jT ubaubahej&ubj)r\ }r] (h\Uhg}r^ (hi]hj]hk]hl]ho]uh]j@ hs]r_ h›)r` }ra (h\X 0x28480000rb h]j\ hchdhehŸhg}rc (hi]hj]hk]hl]ho]uhqM}hs]rd h|X 0x28480000re …rf }rg (h\jb h]j` ubaubahej&ubj)rh }ri (h\Uhg}rj (hi]hj]hk]hl]ho]uh]j@ hs]rk h›)rl }rm (h\X 0x28481FFFrn h]jh hchdhehŸhg}ro (hi]hj]hk]hl]ho]uhqM}hs]rp h|X 0x28481FFFrq …rr }rs (h\jn h]jl ubaubahej&ubj)rt }ru (h\Uhg}rv (hi]hj]hk]hl]ho]uh]j@ hs]rw h›)rx }ry (h\X 0x0028480000rz h]jt hchdhehŸhg}r{ (hi]hj]hk]hl]ho]uhqM}hs]r| h|X 0x0028480000r} …r~ }r (h\jz h]jx ubaubahej&ubj)r€ }r (h\Uhg}r‚ (hi]hj]hk]hl]ho]uh]j@ hs]rƒ h›)r„ }r… (h\X 0x0028490000r† h]j€ hchdhehŸhg}r‡ (hi]hj]hk]hl]ho]uhqM}hs]rˆ h|X 0x0028490000r‰ …rŠ }r‹ (h\j† h]j„ ubaubahej&ubehej3ubj)rŒ }r (h\Uhg}rŽ (hi]hj]hk]hl]ho]uh]jX hs]r (j)r }r‘ (h\Uhg}r’ (hi]hj]hk]hl]ho]uh]jŒ hs]r“ h›)r” }r• (h\XMain Navigator UDMAPr– h]j hchdhehŸhg}r— (hi]hj]hk]hl]ho]uhqM€hs]r˜ h|XMain Navigator UDMAPr™ …rš }r› (h\j– h]j” ubaubahej&ubj)rœ }r (h\Uhg}rž (hi]hj]hk]hl]ho]uh]jŒ hs]rŸ h›)r  }r¡ (h\Xtchanr¢ h]jœ hchdhehŸhg}r£ (hi]hj]hk]hl]ho]uhqM€hs]r¤ h|Xtchanr¥ …r¦ }r§ (h\j¢ h]j  ubaubahej&ubj)r¨ }r© (h\Uhg}rª (hi]hj]hk]hl]ho]uh]jŒ hs]r« h›)r¬ }r­ (h\X 0x284A0000r® h]j¨ hchdhehŸhg}r¯ (hi]hj]hk]hl]ho]uhqM€hs]r° h|X 0x284A0000r± …r² }r³ (h\j® h]j¬ ubaubahej&ubj)r´ }rµ (h\Uhg}r¶ (hi]hj]hk]hl]ho]uh]jŒ hs]r· h›)r¸ }r¹ (h\X 0x284A3FFFrº h]j´ hchdhehŸhg}r» (hi]hj]hk]hl]ho]uhqM€hs]r¼ h|X 0x284A3FFFr½ …r¾ }r¿ (h\jº h]j¸ ubaubahej&ubj)rÀ }rÁ (h\Uhg}r (hi]hj]hk]hl]ho]uh]jŒ hs]rà h›)rÄ }rÅ (h\X 0x00284A0000rÆ h]jÀ hchdhehŸhg}rÇ (hi]hj]hk]hl]ho]uhqM€hs]rÈ h|X 0x00284A0000rÉ …rÊ }rË (h\jÆ h]jÄ ubaubahej&ubj)rÌ }rÍ (h\Uhg}rÎ (hi]hj]hk]hl]ho]uh]jŒ hs]rÏ h›)rÐ }rÑ (h\X 0x00284B0000rÒ h]jÌ hchdhehŸhg}rÓ (hi]hj]hk]hl]ho]uhqM€hs]rÔ h|X 0x00284B0000rÕ …rÖ }r× (h\jÒ h]jÐ ubaubahej&ubehej3ubj)rØ }rÙ (h\Uhg}rÚ (hi]hj]hk]hl]ho]uh]jX hs]rÛ (j)rÜ }rÝ (h\Uhg}rÞ (hi]hj]hk]hl]ho]uh]jØ hs]rß h›)rà }rá (h\XMain Navigator UDMAPrâ h]jÜ hchdhehŸhg}rã (hi]hj]hk]hl]ho]uhqM‚hs]rä h|XMain Navigator UDMAPrå …ræ }rç (h\jâ h]jà ubaubahej&ubj)rè }ré (h\Uhg}rê (hi]hj]hk]hl]ho]uh]jØ hs]rë h›)rì }rí (h\Xrchanrî h]jè hchdhehŸhg}rï (hi]hj]hk]hl]ho]uhqM‚hs]rð h|Xrchanrñ …rò }ró (h\jî h]jì ubaubahej&ubj)rô }rõ (h\Uhg}rö (hi]hj]hk]hl]ho]uh]jØ hs]r÷ h›)rø }rù (h\X 0x284C0000rú h]jô hchdhehŸhg}rû (hi]hj]hk]hl]ho]uhqM‚hs]rü h|X 0x284C0000rý …rþ }rÿ (h\jú h]jø ubaubahej&ubj)r }r (h\Uhg}r (hi]hj]hk]hl]ho]uh]jØ hs]r h›)r }r (h\X 0x284C3FFFr h]j hchdhehŸhg}r (hi]hj]hk]hl]ho]uhqM‚hs]r h|X 0x284C3FFFr …r }r (h\j h]j ubaubahej&ubj)r }r (h\Uhg}r (hi]hj]hk]hl]ho]uh]jØ hs]r h›)r }r (h\X 0x00284C0000r h]j hchdhehŸhg}r (hi]hj]hk]hl]ho]uhqM‚hs]r h|X 0x00284C0000r …r }r (h\j h]j ubaubahej&ubj)r }r (h\Uhg}r (hi]hj]hk]hl]ho]uh]jØ hs]r h›)r }r (h\X 0x00284D0000r h]j hchdhehŸhg}r (hi]hj]hk]hl]ho]uhqM‚hs]r h|X 0x00284D0000r! …r" }r# (h\j h]j ubaubahej&ubehej3ubj)r$ }r% (h\Uhg}r& (hi]hj]hk]hl]ho]uh]jX hs]r' (j)r( }r) (h\Uhg}r* (hi]hj]hk]hl]ho]uh]j$ hs]r+ h›)r, }r- (h\X)MCU Navigator UDMASS Interrupt Aggregatorr. h]j( hchdhehŸhg}r/ (hi]hj]hk]hl]ho]uhqM„hs]r0 h|X)MCU Navigator UDMASS Interrupt Aggregatorr1 …r2 }r3 (h\j. h]j, ubaubahej&ubj)r4 }r5 (h\Uhg}r6 (hi]hj]hk]hl]ho]uh]j$ hs]r7 h›)r8 }r9 (h\Ximapr: h]j4 hchdhehŸhg}r; (hi]hj]hk]hl]ho]uhqM„hs]r< h|Ximapr= …r> }r? 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Navigator UDMAPré…rê}rë(h\jæh]jäubaubahej&ubj)rì}rí(h\Uhg}rî(hi]hj]hk]hl]ho]uh]jÜhs]rïh›)rð}rñ(h\Xgcfgròh]jìhchdhehŸhg}ró(hi]hj]hk]hl]ho]uhqMÂhs]rôh|Xgcfgrõ…rö}r÷(h\jòh]jðubaubahej&ubj)rø}rù(h\Uhg}rú(hi]hj]hk]hl]ho]uh]jÜhs]rûh›)rü}rý(h\X 0x31150000rþh]jøhchdhehŸhg}rÿ(hi]hj]hk]hl]ho]uhqMÂhs]rh|X 0x31150000r…r}r(h\jþh]jüubaubahej&ubj)r}r(h\Uhg}r(hi]hj]hk]hl]ho]uh]jÜhs]rh›)r}r (h\X 0x311500FFr h]jhchdhehŸhg}r (hi]hj]hk]hl]ho]uhqMÂhs]r h|X 0x311500FFr …r}r(h\j h]jubaubahej&ubj)r}r(h\Uhg}r(hi]hj]hk]hl]ho]uh]jÜhs]rh›)r}r(h\X 0x0031150000rh]jhchdhehŸhg}r(hi]hj]hk]hl]ho]uhqMÂhs]rh|X 0x0031150000r…r}r(h\jh]jubaubahej&ubj)r}r(h\Uhg}r(hi]hj]hk]hl]ho]uh]jÜhs]rh›)r }r!(h\X 0x0031160000r"h]jhchdhehŸhg}r#(hi]hj]hk]hl]ho]uhqMÂhs]r$h|X 0x0031160000r%…r&}r'(h\j"h]j ubaubahej&ubehej3ubj)r(}r)(h\Uhg}r*(hi]hj]hk]hl]ho]uh]jX hs]r+(j)r,}r-(h\Uhg}r.(hi]hj]hk]hl]ho]uh]j(hs]r/h›)r0}r1(h\XMain Navigator Ring Acceleratorr2h]j,hchdhehŸhg}r3(hi]hj]hk]hl]ho]uhqMÄhs]r4h|XMain Navigator Ring Acceleratorr5…r6}r7(h\j2h]j0ubaubahej&ubj)r8}r9(h\Uhg}r:(hi]hj]hk]hl]ho]uh]j(hs]r;h›)r<}r=(h\Xgcfgr>h]j8hchdhehŸhg}r?(hi]hj]hk]hl]ho]uhqMÄhs]r@h|XgcfgrA…rB}rC(h\j>h]j<ubaubahej&ubj)rD}rE(h\Uhg}rF(hi]hj]hk]hl]ho]uh]j(hs]rGh›)rH}rI(h\X 0x31160000rJh]jDhchdhehŸhg}rK(hi]hj]hk]hl]ho]uhqMÄhs]rLh|X 0x31160000rM…rN}rO(h\jJh]jHubaubahej&ubj)rP}rQ(h\Uhg}rR(hi]hj]hk]hl]ho]uh]j(hs]rSh›)rT}rU(h\X 0x311603FFrVh]jPhchdhehŸhg}rW(hi]hj]hk]hl]ho]uhqMÄhs]rXh|X 0x311603FFrY…rZ}r[(h\jVh]jTubaubahej&ubj)r\}r](h\Uhg}r^(hi]hj]hk]hl]ho]uh]j(hs]r_h›)r`}ra(h\X 0x0031160000rbh]j\hchdhehŸhg}rc(hi]hj]hk]hl]ho]uhqMÄhs]rdh|X 0x0031160000re…rf}rg(h\jbh]j`ubaubahej&ubj)rh}ri(h\Uhg}rj(hi]hj]hk]hl]ho]uh]j(hs]rkh›)rl}rm(h\X 0x0031170000rnh]jhhchdhehŸhg}ro(hi]hj]hk]hl]ho]uhqMÄhs]rph|X 0x0031170000rq…rr}rs(h\jnh]jlubaubahej&ubehej3ubehejÐubehejÑubaubhê)rt}ru(h\X5What AM65x memory areas are reserved for use by DMSC?rvh]j± hchdhehîhg}rw(hi]hj]hk]hl]ho]uhqMÉhrhhs]rxh|X5What AM65x memory areas are reserved for use by DMSC?ry…rz}r{(h\jvh]jtubaubh›)r|}r}(h\XÎDMSC reserves a portion of the AM65x MSMC memory for the communication path between itself and the A53. Applications must not use the reserved region of MSMC or communication with DMSC will be compromised.r~h]j± hchdhehŸhg}r(hi]hj]hk]hl]ho]uhqMÊhrhhs]r€h|XÎDMSC reserves a portion of the AM65x MSMC memory for the communication path between itself and the A53. Applications must not use the reserved region of MSMC or communication with DMSC will be compromised.r…r‚}rƒ(h\j~h]j|ubaubh›)r„}r…(h\XMThe size of the MSMC region used by DMSC is both configurable and discoverable. The size of the region can be configured through the DMSC board configuration's `msmc_cache_size parameter `__. The useable MSMC memory after DMSC reservations can be discovered by sending the `TISCI_MSG_QUERY_MSMC message `__ to DMSC. The message response contains the range of MSMC memory useable by the application.h]j± hchdhehŸhg}r†(hi]hj]hk]hl]ho]uhqMÎhrhhs]r‡(h|X The size of the MSMC region used by DMSC is both configurable and discoverable. The size of the region can be configured through the DMSC board configuration's rˆ…r‰}rŠ(h\X The size of the MSMC region used by DMSC is both configurable and discoverable. The size of the region can be configured through the DMSC board configuration's h]j„ubh´)r‹}rŒ(h\X|`msmc_cache_size parameter `__hg}r(UnameXmsmc_cache_size parameterh¸X\http://software-dl.ti.com/tisci/esd/latest/3_boardcfg/BOARDCFG.html#design-for-boardcfg-msmchl]hk]hi]hj]ho]uh]j„hs]rŽh|Xmsmc_cache_size parameterr…r}r‘(h\Uh]j‹ubaheh¾ubh|XS. The useable MSMC memory after DMSC reservations can be discovered by sending the r’…r“}r”(h\XS. The useable MSMC memory after DMSC reservations can be discovered by sending the h]j„ubh´)r•}r–(h\X`TISCI_MSG_QUERY_MSMC message `__hg}r—(UnameXTISCI_MSG_QUERY_MSMC messageh¸X^http://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/general/core.html#tisci-msg-query-msmchl]hk]hi]hj]ho]uh]j„hs]r˜h|XTISCI_MSG_QUERY_MSMC messager™…rš}r›(h\Uh]j•ubaheh¾ubh|X] to DMSC. The message response contains the range of MSMC memory useable by the application.rœ…r}rž(h\X] to DMSC. The message response contains the range of MSMC memory useable by the application.h]j„ubeubhÐ)rŸ}r (h\Uh]j± hchdhehÓhg}r¡(hi]hj]hk]hl]ho]uhqMØhrhhs]r¢hÖ)r£}r¤(h\UhÙKh]jŸhchdhehqhg}r¥(hi]hj]hk]hl]ho]uhqKhrhhs]ubaubeubh^)r¦}r§(h\Uh]hahchdhehfhg}r¨(hi]hj]hk]hl]r©U smp-examplesrªaho]r«h!auhqMÛhrhhs]r¬(hu)r­}r®(h\X SMP Examplesr¯h]j¦hchdhehyhg}r°(hi]hj]hk]hl]ho]uhqMÛhrhhs]r±h|X SMP Examplesr²…r³}r´(h\j¯h]j­ubaubhê)rµ}r¶(h\X;How do I load SMP enabled example into target through CCS ?r·h]j¦hchdhehîhg}r¸(hl]r¹U9how-do-i-load-smp-enabled-example-into-target-through-ccsrºahk]hi]hj]ho]r»hNauhqNhrhhs]r¼h|X;How do I load SMP enabled example into target through CCS ?r½…r¾}r¿(h\j·h]jµubaubh›)rÀ}rÁ(h\XSymmetric Multi Processing requires a different approach to load the application into target board through CCS. The detailed documentation on loading and debugging the SMP enabled example is linked `here `__.h]j¦hchdhehŸhg}rÂ(hi]hj]hk]hl]ho]uhqMàhrhhs]rÃ(h|XÆSymmetric Multi Processing requires a different approach to load the application into target board through CCS. The detailed documentation on loading and debugging the SMP enabled example is linked rÄ…rÅ}rÆ(h\XÆSymmetric Multi Processing requires a different approach to load the application into target board through CCS. The detailed documentation on loading and debugging the SMP enabled example is linked h]jÀubh´)rÇ}rÈ(h\XI`here `__hg}rÉ(UnameXhereh¸X>http://software-dl.ti.com/ccs/esd/documents/ccs_smp-debug.htmlhl]hk]hi]hj]ho]uh]jÀhs]rÊh|XhererË…rÌ}rÍ(h\Uh]jÇubaheh¾ubh|X.…rÎ}rÏ(h\X.h]jÀubeubeubeubhchdhehfhg}rÐ(hi]hj]hk]hl]rÑUhost-and-target-setuprÒaho]rÓh-auhqKIhrhhs]rÔ(hu)rÕ}rÖ(h\XHost and Target Setupr×h]h_hchdhehyhg}rØ(hi]hj]hk]hl]ho]uhqKIhrhhs]rÙh|XHost and Target SetuprÚ…rÛ}rÜ(h\j×h]jÕubaubhê)rÝ}rÞ(h\XsHow do I setup the build environment with custom Processor SDK RTOS and CCS Installation paths on the host machine?rßh]h_hchdhehîhg}rà(hl]ráUrhow-do-i-setup-the-build-environment-with-custom-processor-sdk-rtos-and-ccs-installation-paths-on-the-host-machinerâahk]hi]hj]ho]rãhauhqNhrhhs]räh|XsHow do I setup the build environment with custom Processor SDK RTOS and CCS Installation paths on the host machine?rå…ræ}rç(h\jßh]jÝubaubh›)rè}ré(h\XúThe steps to set up CCS and Processor SDK RTOS when the SDK or the IDE is installed in a location other than the default location are described below: `Processor SDK RTOS Setup with CCS `__h]h_hchdhehŸhg}rê(hi]hj]hk]hl]ho]uhqKOhrhhs]rë(h|X—The steps to set up CCS and Processor SDK RTOS when the SDK or the IDE is installed in a location other than the default location are described below: rì…rí}rî(h\X—The steps to set up CCS and Processor SDK RTOS when the SDK or the IDE is installed in a location other than the default location are described below: h]jèubh´)rï}rð(h\Xc`Processor SDK RTOS Setup with CCS `__hg}rñ(UnameX!Processor SDK RTOS Setup with CCSh¸X;How_to_Guides.html#setup-ccs-for-evm-and-processor-sdk-rtoshl]hk]hi]hj]ho]uh]jèhs]ròh|X!Processor SDK RTOS Setup with CCSró…rô}rõ(h\Uh]jïubaheh¾ubeubh›)rö}r÷(h\XÈ**A common gotcha while setting up the build environment is compatibility with CCS version. Please refer to `Release Notes `__ for the recommended version of CCS**røh]h_hchdhehŸhg}rù(hi]hj]hk]hl]ho]uhqKShrhhs]rúj\)rû}rü(h\jøhg}rý(hi]hj]hk]hl]ho]uh]jöhs]rþh|XÄA common gotcha while setting up the build environment is compatibility with CCS version. Please refer to `Release Notes `__ for the recommended version of CCSrÿ…r}r(h\Uh]jûubahejdubaubhê)r}r(h\XMCan I install multiple versions of the Processor SDK RTOS in the same folder?rh]h_hchdhehîhg}r(hl]rULcan-i-install-multiple-versions-of-the-processor-sdk-rtos-in-the-same-folderrahk]hi]hj]ho]rh;auhqNhrhhs]r h|XMCan I install multiple versions of the Processor SDK RTOS in the same folder?r …r }r (h\jh]jubaubh›)r }r(h\X¡Typically, the version numbers of most components (PDK, Processor SDK, BIOS, XDC, etc.) will be updated in the newer release. However there are components like DSPLIB, IMGLIB, etc. and EDMA drivers that may remain the same. The safe option would be to install the most current Processor SDK in a custom location. You can have multiple versions of the SDK for different devices on your machine and install all of them in custom folders. For example, if you have a project with AM335x and AM437x that requires you to download the Processor SDK RTOS for those device, we recommend that you install them under different directories say C:\\ti\\PRSDK_AM3x and C:\\ti\\PRSDK_AM4xh]h_hchdhehŸhg}r(hi]hj]hk]hl]ho]uhqK\hrhhs]rh|XTypically, the version numbers of most components (PDK, Processor SDK, BIOS, XDC, etc.) will be updated in the newer release. However there are components like DSPLIB, IMGLIB, etc. and EDMA drivers that may remain the same. The safe option would be to install the most current Processor SDK in a custom location. You can have multiple versions of the SDK for different devices on your machine and install all of them in custom folders. For example, if you have a project with AM335x and AM437x that requires you to download the Processor SDK RTOS for those device, we recommend that you install them under different directories say C:\ti\PRSDK_AM3x and C:\ti\PRSDK_AM4xr…r}r(h\X¡Typically, the version numbers of most components (PDK, Processor SDK, BIOS, XDC, etc.) will be updated in the newer release. However there are components like DSPLIB, IMGLIB, etc. and EDMA drivers that may remain the same. The safe option would be to install the most current Processor SDK in a custom location. You can have multiple versions of the SDK for different devices on your machine and install all of them in custom folders. For example, if you have a project with AM335x and AM437x that requires you to download the Processor SDK RTOS for those device, we recommend that you install them under different directories say C:\\ti\\PRSDK_AM3x and C:\\ti\\PRSDK_AM4xh]j ubaubj?)r}r(h\X When you install the SDK in a custom location, there are few additional steps to follow: - CCS auto-detects components only in C:\\ti path. So you will need to add the custom path to discovery as described in `Setup CCS `__. - Assuming CCS is installed in the default path, the process to set the custom SDK path while building the SDK is provided in `Install in Custom Path `h]h_hcNhejBhg}r(hi]hj]hk]hl]ho]uhqNhrhhs]r(h›)r}r(h\XXWhen you install the SDK in a custom location, there are few additional steps to follow:rh]jhchdhehŸhg}r(hi]hj]hk]hl]ho]uhqKhhs]rh|XXWhen you install the SDK in a custom location, there are few additional steps to follow:r…r}r(h\jh]jubaubj)r }r!(h\Uhg}r"(jX-hl]hk]hi]hj]ho]uh]jhs]r#(j)r$}r%(h\XÂCCS auto-detects components only in C:\\ti path. So you will need to add the custom path to discovery as described in `Setup CCS `__.hg}r&(hi]hj]hk]hl]ho]uh]j hs]r'h›)r(}r)(h\XÂCCS auto-detects components only in C:\\ti path. So you will need to add the custom path to discovery as described in `Setup CCS `__.h]j$hchdhehŸhg}r*(hi]hj]hk]hl]ho]uhqKkhs]r+(h|XuCCS auto-detects components only in C:\ti path. So you will need to add the custom path to discovery as described in r,…r-}r.(h\XvCCS auto-detects components only in C:\\ti path. So you will need to add the custom path to discovery as described in h]j(ubh´)r/}r0(h\XK`Setup CCS `__hg}r1(UnameX Setup CCSh¸X;How_to_Guides.html#setup-ccs-for-evm-and-processor-sdk-rtoshl]hk]hi]hj]ho]uh]j(hs]r2h|X Setup CCSr3…r4}r5(h\Uh]j/ubaheh¾ubh|X.…r6}r7(h\X.h]j(ubeubahejubj)r8}r9(h\XÝAssuming CCS is installed in the default path, the process to set the custom SDK path while building the SDK is provided in `Install in Custom Path `hg}r:(hi]hj]hk]hl]ho]uh]j hs]r;h›)r<}r=(h\XÝAssuming CCS is installed in the default path, the process to set the custom SDK path while building the SDK is provided in `Install in Custom Path `h]j8hchdhehŸhg}r>(hi]hj]hk]hl]ho]uhqKnhs]r?(h|X|Assuming CCS is installed in the default path, the process to set the custom SDK path while building the SDK is provided in r@…rA}rB(h\X|Assuming CCS is installed in the default path, the process to set the custom SDK path while building the SDK is provided in h]j<ubcdocutils.nodes title_reference rC)rD}rE(h\Xa`Install in Custom Path `hg}rF(hi]hj]hk]hl]ho]uh]j<hs]rGh|X_Install in Custom Path rH…rI}rJ(h\Uh]jDubaheUtitle_referencerKubeubahejubehejubeubhê)rL}rM(h\XbWhat are the typical flows for a new user to setup the Processor SDK RTOS development environment?rNh]h_hchdhehîhg}rO(hl]rPUawhat-are-the-typical-flows-for-a-new-user-to-setup-the-processor-sdk-rtos-development-environmentrQahk]hi]hj]ho]rRhSauhqNhrhhs]rSh|XbWhat are the typical flows for a new user to setup the Processor SDK RTOS development environment?rT…rU}rV(h\jNh]jLubaubh›)rW}rX(h\XEThe typical Processor SDK RTOS setup steps have been described below:rYh]h_hchdhehŸhg}rZ(hi]hj]hk]hl]ho]uhqKvhrhhs]r[h|XEThe typical Processor SDK RTOS setup steps have been described below:r\…r]}r^(h\jYh]jWubaubhê)r_}r`(h\X*Step 1: Basic Hardware, SDK, and IDE Setuprah]h_hchdhehîhg}rb(hl]rcU'step-1-basic-hardware-sdk-and-ide-setuprdahk]hi]hj]ho]rehIauhqNhrhhs]rfh|X*Step 1: Basic Hardware, SDK, and IDE Setuprg…rh}ri(h\jah]j_ubaubh›)rj}rk(h\XSetup the software and hardware as described in the :ref:`Getting Started Guide ` At this stage, you should have the CCS IDE environment, the Processor SDK RTOS installed and be able to connect to your target using an emulator.h]h_hchdhehŸhg}rl(hi]hj]hk]hl]ho]uhqK{hrhhs]rm(h|X4Setup the software and hardware as described in the rn…ro}rp(h\X4Setup the software and hardware as described in the h]jjubjh)rq}rr(h\XM:ref:`Getting Started Guide `rsh]jjhchdhejlhg}rt(UreftypeXrefjnˆjoX.processor-sdk-rtos-getting-started-guide-labelU refdomainXstdruhl]hk]U refexplicitˆhi]hj]ho]jqhuhqK{hs]rvjs)rw}rx(h\jshg}ry(hi]hj]rz(jxjuXstd-refr{ehk]hl]ho]uh]jqhs]r|h|XGetting Started Guider}…r~}r(h\Uh]jwubahej~ubaubh|X’ At this stage, you should have the CCS IDE environment, the Processor SDK RTOS installed and be able to connect to your target using an emulator.r€…r}r‚(h\X’ At this stage, you should have the CCS IDE environment, the Processor SDK RTOS installed and be able to connect to your target using an emulator.h]jjubeubj?)rƒ}r„(h\X If you have installed CCS and/or the Processor SDK RTOS in a custom location, you need to manually add the SDK install path to CCS as described here `CCS_and_SDK_installed_in_different_directories `__h]h_hchdhejBhg}r…(hi]hj]hk]hl]ho]uhqNhrhhs]r†h›)r‡}rˆ(h\X If you have installed CCS and/or the Processor SDK RTOS in a custom location, you need to manually add the SDK install path to CCS as described here `CCS_and_SDK_installed_in_different_directories `__h]jƒhchdhehŸhg}r‰(hi]hj]hk]hl]ho]uhqK‚hs]rŠ(h|X•If you have installed CCS and/or the Processor SDK RTOS in a custom location, you need to manually add the SDK install path to CCS as described here r‹…rŒ}r(h\X•If you have installed CCS and/or the Processor SDK RTOS in a custom location, you need to manually add the SDK install path to CCS as described here h]j‡ubh´)rŽ}r(h\Xv`CCS_and_SDK_installed_in_different_directories `__hg}r(UnameX.CCS_and_SDK_installed_in_different_directoriesh¸XAHow_to_Guides.html#ccs-and-sdk-installed-in-different-directorieshl]hk]hi]hj]ho]uh]j‡hs]r‘h|X.CCS_and_SDK_installed_in_different_directoriesr’…r“}r”(h\Uh]jŽubaheh¾ubeubaubhê)r•}r–(h\X2Step 2: Run the Out-of-Box Examples or Diagnosticsr—h]h_hchdhehîhg}r˜(hl]r™U1step-2-run-the-out-of-box-examples-or-diagnosticsršahk]hi]hj]ho]r›h:auhqNhrhhs]rœh|X2Step 2: Run the Out-of-Box Examples or Diagnosticsr…rž}rŸ(h\j—h]j•ubaubh›)r }r¡(h\XThe SDK and CCS ships with some pre-built out-of-box demonstrations/examples that can be flashed on to the EVM, copied over to an SD card, or loaded over emulator so that you can bring up and test the EVM hardware. The steps to flash and run the out-of-box examples are described here:r¢h]h_hchdhehŸhg}r£(hi]hj]hk]hl]ho]uhqKŠhrhhs]r¤h|XThe SDK and CCS ships with some pre-built out-of-box demonstrations/examples that can be flashed on to the EVM, copied over to an SD card, or loaded over emulator so that you can bring up and test the EVM hardware. The steps to flash and run the out-of-box examples are described here:r¥…r¦}r§(h\j¢h]j ubaubj)r¨}r©(h\Uh]h_hchdhejhg}rª(jX-hl]hk]hi]hj]ho]uhqKhrhhs]r«j)r¬}r­(h\Xe`Running_examples.2Fdemonstrations `__ h]j¨hchdhejhg}r®(hi]hj]hk]hl]ho]uhqNhrhhs]r¯h›)r°}r±(h\Xd`Running_examples.2Fdemonstrations `__r²h]j¬hchdhehŸhg}r³(hi]hj]hk]hl]ho]uhqKhs]r´h´)rµ}r¶(h\j²hg}r·(UnameX!Running_examples.2Fdemonstrationsh¸X<Examples_and_Demonstrations.html#examples-and-demonstrationshl]hk]hi]hj]ho]uh]j°hs]r¸h|X!Running_examples.2Fdemonstrationsr¹…rº}r»(h\Uh]jµubaheh¾ubaubaubaubhê)r¼}r½(h\XStep 3: Build Environment Setupr¾h]h_hchdhehîhg}r¿(hl]rÀUstep-3-build-environment-setuprÁahk]hi]hj]ho]rÂh*auhqNhrhhs]rÃh|XStep 3: Build Environment SetuprÄ…rÅ}rÆ(h\j¾h]j¼ubaubh›)rÇ}rÈ(h\X!Processor SDK RTOS provides a script to set up the Windows and Linux environment with the component and compiler PATHs. Running the script and rebuilding the Processor SDK from the root directory is described in the wiki article `Setup build Environment `.h]h_hchdhehŸhg}rÉ(hi]hj]hk]hl]ho]uhqK•hrhhs]rÊ(h|XåProcessor SDK RTOS provides a script to set up the Windows and Linux environment with the component and compiler PATHs. Running the script and rebuilding the Processor SDK from the root directory is described in the wiki article rË…rÌ}rÍ(h\XåProcessor SDK RTOS provides a script to set up the Windows and Linux environment with the component and compiler PATHs. Running the script and rebuilding the Processor SDK from the root directory is described in the wiki article h]jÇubjC)rÎ}rÏ(h\X;`Setup build Environment `hg}rÐ(hi]hj]hk]hl]ho]uh]jÇhs]rÑh|X9Setup build Environment rÒ…rÓ}rÔ(h\Uh]jÎubahejKubh|X.…rÕ}rÖ(h\X.h]jÇubeubj?)r×}rØ(h\XV- The script assumes that CCS and Processor SDK RTOS are installed in the default location. If you have installed CCS and/or the Processor SDK RTOS in a custom location, then modify the setup file to the custom path. Please setup the environment using the steps described in the wiki article `Processor SDK RTOS Install in Custom Path `__ - After the script executes, it prints all the PATH macros set for the different variables. Be sure that the compiler and component paths have been setup correctly.h]h_hcNhejBhg}rÙ(hi]hj]hk]hl]ho]uhqNhrhhs]rÚj)rÛ}rÜ(h\Uhg}rÝ(jX-hl]hk]hi]hj]ho]uh]j×hs]rÞ(j)rß}rà(h\X˜The script assumes that CCS and Processor SDK RTOS are installed in the default location. If you have installed CCS and/or the Processor SDK RTOS in a custom location, then modify the setup file to the custom path. Please setup the environment using the steps described in the wiki article `Processor SDK RTOS Install in Custom Path `__hg}rá(hi]hj]hk]hl]ho]uh]jÛhs]râh›)rã}rä(h\X˜The script assumes that CCS and Processor SDK RTOS are installed in the default location. If you have installed CCS and/or the Processor SDK RTOS in a custom location, then modify the setup file to the custom path. Please setup the environment using the steps described in the wiki article `Processor SDK RTOS Install in Custom Path `__h]jßhchdhehŸhg}rå(hi]hj]hk]hl]ho]uhqKœhs]ræ(h|X"The script assumes that CCS and Processor SDK RTOS are installed in the default location. If you have installed CCS and/or the Processor SDK RTOS in a custom location, then modify the setup file to the custom path. Please setup the environment using the steps described in the wiki article rç…rè}ré(h\X"The script assumes that CCS and Processor SDK RTOS are installed in the default location. If you have installed CCS and/or the Processor SDK RTOS in a custom location, then modify the setup file to the custom path. Please setup the environment using the steps described in the wiki article h]jãubh´)rê}rë(h\Xv`Processor SDK RTOS Install in Custom Path `__hg}rì(UnameX)Processor SDK RTOS Install in Custom Pathh¸XFHow_to_Guides.html#update-environment-when-installing-to-a-custom-pathhl]hk]hi]hj]ho]uh]jãhs]ríh|X)Processor SDK RTOS Install in Custom Pathrî…rï}rð(h\Uh]jêubaheh¾ubeubahejubj)rñ}rò(h\X¢After the script executes, it prints all the PATH macros set for the different variables. Be sure that the compiler and component paths have been setup correctly.hg}ró(hi]hj]hk]hl]ho]uh]jÛhs]rôh›)rõ}rö(h\X¢After the script executes, it prints all the PATH macros set for the different variables. Be sure that the compiler and component paths have been setup correctly.r÷h]jñhchdhehŸhg}rø(hi]hj]hk]hl]ho]uhqK¢hs]rùh|X¢After the script executes, it prints all the PATH macros set for the different variables. Be sure that the compiler and component paths have been setup correctly.rú…rû}rü(h\j÷h]jõubaubahejubehejubaubhê)rý}rþ(h\XStep 4: Rebuilding the SDKrÿh]h_hchdhehîhg}r(hl]rUstep-4-rebuilding-the-sdkrahk]hi]hj]ho]rhauhqNhrhhs]rh|XStep 4: Rebuilding the SDKr…r}r(h\jÿh]jýubaubh›)r}r (h\XQThe critical device-specific components of the Processor SDK RTOS can be rebuilt from the top-level make file provided in the root directory processor_sdk_rtos_x_xx_xx_xx. Invoking the build and available options from top-level make files is described in the wiki article `Rebuilding SDK Components `__.h]h_hchdhehŸhg}r (hi]hj]hk]hl]ho]uhqKªhrhhs]r (h|XThe critical device-specific components of the Processor SDK RTOS can be rebuilt from the top-level make file provided in the root directory processor_sdk_rtos_x_xx_xx_xx. Invoking the build and available options from top-level make files is described in the wiki article r …r }r(h\XThe critical device-specific components of the Processor SDK RTOS can be rebuilt from the top-level make file provided in the root directory processor_sdk_rtos_x_xx_xx_xx. Invoking the build and available options from top-level make files is described in the wiki article h]jubh´)r}r(h\X@`Rebuilding SDK Components `__hg}r(UnameXRebuilding SDK Componentsh¸X Overview.html#top-level-makefilehl]hk]hi]hj]ho]uh]jhs]rh|XRebuilding SDK Componentsr…r}r(h\Uh]jubaheh¾ubh|X.…r}r(h\X.h]jubeubj?)r}r(h\X„The SDK offers command line build for all the components. CCS projects are only supported for DSP libraries and PDK driver examples.h]h_hchdhejBhg}r(hi]hj]hk]hl]ho]uhqNhrhhs]rh›)r}r(h\X„The SDK offers command line build for all the components. CCS projects are only supported for DSP libraries and PDK driver examples.rh]jhchdhehŸhg}r(hi]hj]hk]hl]ho]uhqK²hs]r h|X„The SDK offers command line build for all the components. CCS projects are only supported for DSP libraries and PDK driver examples.r!…r"}r#(h\jh]jubaubaubhÐ)r$}r%(h\Uh]h_hchdhehÓhg}r&(hi]hj]hk]hl]ho]uhqK´hrhhs]r'hÖ)r(}r)(h\UhÙKh]j$hchdhehqhg}r*(hi]hj]hk]hl]ho]uhqKhrhhs]ubaubhê)r+}r,(h\X3Step 5: Generate and Run Peripheral Driver Examplesr-h]h_hchdhehîhg}r.(hl]r/U2step-5-generate-and-run-peripheral-driver-examplesr0ahk]hi]hj]ho]r1hauhqNhrhhs]r2h|X3Step 5: Generate and Run Peripheral Driver Examplesr3…r4}r5(h\j-h]j+ubaubh›)r6}r7(h\XThe PDK component in Processor SDK RTOS provides drivers for different IPs on the SOC and provides unit tests and examples for the drivers to test them on a specific board/hardware. These examples do not ship with pre-generated CCS projects and require users to generate a project create script to generate the CCS project for the unit tests. The procedure to generate the CCS projects for a given SOC is described in this article `PDK_Example_and_Test_Project_Creation `__.h]h_hchdhehŸhg}r8(hi]hj]hk]hl]ho]uhqK¹hrhhs]r9(h|X¯The PDK component in Processor SDK RTOS provides drivers for different IPs on the SOC and provides unit tests and examples for the drivers to test them on a specific board/hardware. These examples do not ship with pre-generated CCS projects and require users to generate a project create script to generate the CCS project for the unit tests. The procedure to generate the CCS projects for a given SOC is described in this article r:…r;}r<(h\X¯The PDK component in Processor SDK RTOS provides drivers for different IPs on the SOC and provides unit tests and examples for the drivers to test them on a specific board/hardware. These examples do not ship with pre-generated CCS projects and require users to generate a project create script to generate the CCS project for the unit tests. The procedure to generate the CCS projects for a given SOC is described in this article h]j6ubh´)r=}r>(h\Xd`PDK_Example_and_Test_Project_Creation `__hg}r?(UnameX%PDK_Example_and_Test_Project_Creationh¸X8How_to_Guides.html#pdk-example-and-test-project-creationhl]hk]hi]hj]ho]uh]j6hs]r@h|X%PDK_Example_and_Test_Project_CreationrA…rB}rC(h\Uh]j=ubaheh¾ubh|X.…rD}rE(h\X.h]j6ubeubhê)rF}rG(h\X-Step 6: Exploring Other Components in the SDKrHh]h_hchdhehîhg}rI(hl]rJU,step-6-exploring-other-components-in-the-sdkrKahk]hi]hj]ho]rLh9auhqNhrhhs]rMh|X-Step 6: Exploring Other Components in the SDKrN…rO}rP(h\jHh]jFubaubh›)rQ}rR(h\X+The SDK package includes several other components that allow application developers to develop software for multi-core devices. This includes an inter-processor communication component known as (IPC). For SOCs that contain an C66x DSP, the SDK provides several optimized DSP libraries (DSPLIB, MATHLIB and IMGLIB). These components also ship with pre-built examples that can be built using build steps described in their documentation that is linked at the top level `Software Developer Guide `__.h]h_hchdhehŸhg}rS(hi]hj]hk]hl]ho]uhqKÅhrhhs]rT(h|XÓThe SDK package includes several other components that allow application developers to develop software for multi-core devices. This includes an inter-processor communication component known as (IPC). For SOCs that contain an C66x DSP, the SDK provides several optimized DSP libraries (DSPLIB, MATHLIB and IMGLIB). These components also ship with pre-built examples that can be built using build steps described in their documentation that is linked at the top level rU…rV}rW(h\XÓThe SDK package includes several other components that allow application developers to develop software for multi-core devices. This includes an inter-processor communication component known as (IPC). For SOCs that contain an C66x DSP, the SDK provides several optimized DSP libraries (DSPLIB, MATHLIB and IMGLIB). These components also ship with pre-built examples that can be built using build steps described in their documentation that is linked at the top level h]jQubh´)rX}rY(h\XW`Software Developer Guide `__hg}rZ(UnameXSoftware Developer Guideh¸X8index.html#processor-sdk-rtos-software-developer-s-guidehl]hk]hi]hj]ho]uh]jQhs]r[h|XSoftware Developer Guider\…r]}r^(h\Uh]jXubaheh¾ubh|X.…r_}r`(h\X.h]jQubeubhÐ)ra}rb(h\Uh]h_hchdhehÓhg}rc(hi]hj]hk]hl]ho]uhqKÎhrhhs]rdhÖ)re}rf(h\UhÙKh]jahchdhehqhg}rg(hi]hj]hk]hl]ho]uhqKhrhhs]ubaubhê)rh}ri(h\XKHow can I optimize the build time when rebuilding the Processor SDK RTOS ?rjh]h_hchdhehîhg}rk(hl]rlUHhow-can-i-optimize-the-build-time-when-rebuilding-the-processor-sdk-rtosrmahk]hi]hj]ho]rnhauhqNhrhhs]roh|XKHow can I optimize the build time when rebuilding the Processor SDK RTOS ?rp…rq}rr(h\jjh]jhubaubh›)rs}rt(h\XÅProcessor SDK RTOS top level build will rebuild IPC, all components inside the PDK package for all supported cores and evaluation platforms. Building all components can cause long build times. If you wish to only rebuild a section of the package, the build times can be significantly optimized if you invoke make for specific components in the SDK instead of making all components. Also, for the PDK users can invoke the build using the following syntaxruh]h_hchdhehŸhg}rv(hi]hj]hk]hl]ho]uhqKÔhrhhs]rwh|XÅProcessor SDK RTOS top level build will rebuild IPC, all components inside the PDK package for all supported cores and evaluation platforms. Building all components can cause long build times. If you wish to only rebuild a section of the package, the build times can be significantly optimized if you invoke make for specific components in the SDK instead of making all components. Also, for the PDK users can invoke the build using the following syntaxrx…ry}rz(h\juh]jsubaubjÕ)r{}r|(h\XCmake LIMIT_BOARDS="" LIMIT_SOCS="" LIMIT_CORES=""h]h_hchdhejØhg}r}(jÚjÛhl]hk]hi]hj]ho]uhqKÞhrhhs]r~h|XCmake LIMIT_BOARDS="" LIMIT_SOCS="" LIMIT_CORES=""r…r€}r(h\Uh]j{ubaubh›)r‚}rƒ(h\X@**SOC** can be am335x, am437x, am571x, am572x, k2g,k2h,k2e, etc.r„h]h_hchdhehŸhg}r…(hi]hj]hk]hl]ho]uhqKàhrhhs]r†(j\)r‡}rˆ(h\X**SOC**hg}r‰(hi]hj]hk]hl]ho]uh]j‚hs]rŠh|XSOCr‹…rŒ}r(h\Uh]j‡ubahejdubh|X9 can be am335x, am437x, am571x, am572x, k2g,k2h,k2e, etc.rŽ…r}r(h\X9 can be am335x, am437x, am571x, am572x, k2g,k2h,k2e, etc.h]j‚ubeubh›)r‘}r’(h\XX**CORE** can be “a15_0â€, “c66xâ€, or “ipu1_0â€, for a15, c66, m4 respectively.h]h_hchdhehŸhg}r“(hi]hj]hk]hl]ho]uhqKâhrhhs]r”(j\)r•}r–(h\X**CORE**hg}r—(hi]hj]hk]hl]ho]uh]j‘hs]r˜h|XCOREr™…rš}r›(h\Uh]j•ubahejdubh|XP can be “a15_0â€, “c66xâ€, or “ipu1_0â€, for a15, c66, m4 respectively.rœ…r}rž(h\XP can be “a15_0â€, “c66xâ€, or “ipu1_0â€, for a15, c66, m4 respectively.h]j‘ubeubh›)rŸ}r (h\XI**BOARD** can be any evaluation hardware platform that your SOC supports.h]h_hchdhehŸhg}r¡(hi]hj]hk]hl]ho]uhqKåhrhhs]r¢(j\)r£}r¤(h\X **BOARD**hg}r¥(hi]hj]hk]hl]ho]uh]jŸhs]r¦h|XBOARDr§…r¨}r©(h\Uh]j£ubahejdubh|X@ can be any evaluation hardware platform that your SOC supports.rª…r«}r¬(h\X@ can be any evaluation hardware platform that your SOC supports.h]jŸubeubjÕ)r­}r®(h\XSFor Example: make LIMIT_BOARDS="evmK2G iceK2G" LIMIT_SOCS="k2g" LIMIT_CORES="a15_0"h]h_hchdhejØhg}r¯(jÚjÛhl]hk]hi]hj]ho]uhqKêhrhhs]r°h|XSFor Example: make LIMIT_BOARDS="evmK2G iceK2G" LIMIT_SOCS="k2g" LIMIT_CORES="a15_0"r±…r²}r³(h\Uh]j­ubaubhÐ)r´}rµ(h\Uh]h_hchdhehÓhg}r¶(hi]hj]hk]hl]ho]uhqKìhrhhs]r·hÖ)r¸}r¹(h\UhÙKh]j´hchdhehqhg}rº(hi]hj]hk]hl]ho]uhqKhrhhs]ubaubhê)r»}r¼(h\X`Why am I not able to connect to the DSP core in CCS when Linux is booted on KeyStone II devices?r½h]h_hchdhehîhg}r¾(hl]r¿U_why-am-i-not-able-to-connect-to-the-dsp-core-in-ccs-when-linux-is-booted-on-keystone-ii-devicesrÀahk]hi]hj]ho]rÁhauhqNhrhhs]rÂh|X`Why am I not able to connect to the DSP core in CCS when Linux is booted on KeyStone II devices?rÃ…rÄ}rÅ(h\j½h]j»ubaubh›)rÆ}rÇ(h\XHThe U-boot code that is booted before booting Linux puts the DSP core in reset. In order to connect to the DSP, you need to run a GEL script in CCS as described in this article `Taking_the_C66x_Out_Of_Reset_with_Linux_Running_on_the_ARM_A15 `__.h]h_hchdhehŸhg}rÈ(hi]hj]hk]hl]ho]uhqKòhrhhs]rÉ(h|X±The U-boot code that is booted before booting Linux puts the DSP core in reset. In order to connect to the DSP, you need to run a GEL script in CCS as described in this article rÊ…rË}rÌ(h\X±The U-boot code that is booted before booting Linux puts the DSP core in reset. In order to connect to the DSP, you need to run a GEL script in CCS as described in this article h]jÆubh´)rÍ}rÎ(h\X–`Taking_the_C66x_Out_Of_Reset_with_Linux_Running_on_the_ARM_A15 `__hg}rÏ(UnameX>Taking_the_C66x_Out_Of_Reset_with_Linux_Running_on_the_ARM_A15h¸XQHow_to_Guides.html#taking-the-c66x-out-of-reset-with-linux-running-on-the-arm-a15hl]hk]hi]hj]ho]uh]jÆhs]rÐh|X>Taking_the_C66x_Out_Of_Reset_with_Linux_Running_on_the_ARM_A15rÑ…rÒ}rÓ(h\Uh]jÍubaheh¾ubh|X.…rÔ}rÕ(h\X.h]jÆubeubhê)rÖ}r×(h\X2How can I create a SD card for Processor SDK RTOS?rØh]h_hchdhehîhg}rÙ(hl]rÚU1how-can-i-create-a-sd-card-for-processor-sdk-rtosrÛahk]hi]hj]ho]rÜh'auhqNhrhhs]rÝh|X2How can I create a SD card for Processor SDK RTOS?rÞ…rß}rà(h\jØh]jÖubaubh›)rá}râ(h\X©Many of the TI-supported EVMs ship with an SD card with Linux Booting as part of the EVM out-of-box experience. Users are required to create a separate SD card if they want to boot their EVM with Processor SDK RTOS out-of-box demonstrations or run board diagnostics. The procedure to create an SD differs depending on whether you are doing this on a Windows or Linux host machine, as described in the two articles shown here:rãh]h_hchdhehŸhg}rä(hi]hj]hk]hl]ho]uhqKúhrhhs]råh|X©Many of the TI-supported EVMs ship with an SD card with Linux Booting as part of the EVM out-of-box experience. Users are required to create a separate SD card if they want to boot their EVM with Processor SDK RTOS out-of-box demonstrations or run board diagnostics. The procedure to create an SD differs depending on whether you are doing this on a Windows or Linux host machine, as described in the two articles shown here:ræ…rç}rè(h\jãh]jáubaubj)ré}rê(h\Uh]h_hchdhejhg}rë(jX-hl]hk]hi]hj]ho]uhqMhrhhs]rì(j)rí}rî(h\Xe`Create an SD card on Windows Host (AMx, K2G only) `__ h]jéhchdhejhg}rï(hi]hj]hk]hl]ho]uhqNhrhhs]rðh›)rñ}rò(h\Xd`Create an SD card on Windows Host (AMx, K2G only) `__róh]jíhchdhehŸhg}rô(hi]hj]hk]hl]ho]uhqMhs]rõh´)rö}r÷(h\jóhg}rø(UnameX1Create an SD card on Windows Host (AMx, K2G only)h¸X,Overview.html#windows-sd-card-creation-guidehl]hk]hi]hj]ho]uh]jñhs]rùh|X1Create an SD card on Windows Host (AMx, K2G only)rú…rû}rü(h\Uh]jöubaheh¾ubaubaubj)rý}rþ(h\Xa`Create an SD card on Linux Host (AMx, K2G only) `__ h]jéhchdhejhg}rÿ(hi]hj]hk]hl]ho]uhqNhrhhs]rh›)r}r(h\X``Create an SD card on Linux Host (AMx, K2G only) `__rh]jýhchdhehŸhg}r(hi]hj]hk]hl]ho]uhqMhs]rh´)r}r(h\jhg}r(UnameX/Create an SD card on Linux Host (AMx, K2G only)h¸X*Overview.html#linux-sd-card-creation-guidehl]hk]hi]hj]ho]uh]jhs]r h|X/Create an SD card on Linux Host (AMx, K2G only)r …r }r (h\Uh]jubaheh¾ubaubaubeubhê)r }r(h\X=How can I restore the firmware on my EVM to factory settings?rh]h_hchdhehîhg}r(hl]rU`__ provided in Processor SDK Linux.h]h_hchdhehŸhg}r(hi]hj]hk]hl]ho]uhqM hrhhs]r(h|X¬Most of the Sitara EVMs ship with a bootable SD card that boots Linux. To restore the EVM to factory settings, simply reflash the SD card with the bootable image using the r…r}r(h\X¬Most of the Sitara EVMs ship with a bootable SD card that boots Linux. To restore the EVM to factory settings, simply reflash the SD card with the bootable image using the h]jubh´)r}r (h\Xo`SD Card Creation Script `__hg}r!(UnameXSD Card Creation Scripth¸XQhttp://processors.wiki.ti.com/index.php/Processor_SDK_Linux_create_SD_card_scripthl]hk]hi]hj]ho]uh]jhs]r"h|XSD Card Creation Scriptr#…r$}r%(h\Uh]jubaheh¾ubh|X! provided in Processor SDK Linux.r&…r'}r((h\X! provided in Processor SDK Linux.h]jubeubh›)r)}r*(h\XêFor KeyStone Devices, the Processor SDK RTOS provides a `Program EVM Script `__ with default binaries that reflash images on EEPROM, SPI, and/or NAND (depending on the EVM platform used).h]h_hchdhehŸhg}r+(hi]hj]hk]hl]ho]uhqMhrhhs]r,(h|X8For KeyStone Devices, the Processor SDK RTOS provides a r-…r.}r/(h\X8For KeyStone Devices, the Processor SDK RTOS provides a h]j)ubh´)r0}r1(h\XF`Program EVM Script `__hg}r2(UnameXProgram EVM Scripth¸X-How_to_Guides.html#default-binaries-and-setuphl]hk]hi]hj]ho]uh]j)hs]r3h|XProgram EVM Scriptr4…r5}r6(h\Uh]j0ubaheh¾ubh|Xl with default binaries that reflash images on EEPROM, SPI, and/or NAND (depending on the EVM platform used).r7…r8}r9(h\Xl with default binaries that reflash images on EEPROM, SPI, and/or NAND (depending on the EVM platform used).h]j)ubeubhê)r:}r;(h\X+Can I run Processor SDK RTOS on BeagleBone?r<h]h_hchdhehîhg}r=(hl]r>U*can-i-run-processor-sdk-rtos-on-beagleboner?ahk]hi]hj]ho]r@hKauhqNhrhhs]rAh|X+Can I run Processor SDK RTOS on BeagleBone?rB…rC}rD(h\j<h]j:ubaubh›)rE}rF(h\X„Yes, Processor SDK RTOS software can be used to develop and run code on BeagleBone platform. In order to test Processor SDK RTOS software on BeagleBone, you will need to connect a JTAG to the BeagleBone. With the default configuration of the board, we have observed that connecting a JTAG causes a reset. Users need to follow the procedure provided here to prevent a reset from occurring.rGh]h_hchdhehŸhg}rH(hi]hj]hk]hl]ho]uhqMhrhhs]rIh|X„Yes, Processor SDK RTOS software can be used to develop and run code on BeagleBone platform. In order to test Processor SDK RTOS software on BeagleBone, you will need to connect a JTAG to the BeagleBone. With the default configuration of the board, we have observed that connecting a JTAG causes a reset. Users need to follow the procedure provided here to prevent a reset from occurring.rJ…rK}rL(h\jGh]jEubaubj)rM}rN(h\Uh]h_hchdhejhg}rO(jX-hl]hk]hi]hj]ho]uhqMhrhhs]rPj)rQ}rR(h\X•`Preventing a Reset When Connecting a JTAG on BeagleBone `__ h]jMhchdhejhg}rS(hi]hj]hk]hl]ho]uhqNhrhhs]rTh›)rU}rV(h\X”`Preventing a Reset When Connecting a JTAG on BeagleBone `__rWh]jQhchdhehŸhg}rX(hi]hj]hk]hl]ho]uhqMhs]rYh´)rZ}r[(h\jWhg}r\(UnameX7Preventing a Reset When Connecting a JTAG on BeagleBoneh¸XVhttp://elinux.org/Beagleboard:BeagleBone#Board_Reset_on_JTAG_Connect.28A3.2CA4.2CA5.29hl]hk]hi]hj]ho]uh]jUhs]r]h|X7Preventing a Reset When Connecting a JTAG on BeagleBoner^…r_}r`(h\Uh]jZubaheh¾ubaubaubaubhÐ)ra}rb(h\Uh]h_hchdhehÓhg}rc(hi]hj]hk]hl]ho]uhqM"hrhhs]rdhÖ)re}rf(h\UhÙKh]jahchdhehqhg}rg(hi]hj]hk]hl]ho]uhqKhrhhs]ubaubeubhchdheUsystem_messagerhhg}ri(hi]UlevelKhl]hk]Usourcehdhj]ho]UlineK´UtypeUWARNINGrjuhqK³hrhhs]rkh›)rl}rm(h\X?Explicit markup ends without a blank line; unexpected unindent.hg}rn(hi]hj]hk]hl]ho]uh]hZhs]roh|X?Explicit markup ends without a blank line; unexpected unindent.rp…rq}rr(h\Uh]jlubahehŸubaubhY)rs}rt(h\Uh]h_hchdhejhhg}ru(hi]UlevelKhl]hk]Usourcehdhj]ho]UlineKìUtypejjuhqKëhrhhs]rvh›)rw}rx(h\X=Literal block ends without a blank line; unexpected unindent.hg}ry(hi]hj]hk]hl]ho]uh]jshs]rzh|X=Literal block ends without a blank line; unexpected unindent.r{…r|}r}(h\Uh]jwubahehŸubaubhY)r~}r(h\Uh]jíhchdhejhhg}r€(hi]UlevelKhl]hk]Usourcehdhj]ho]UlineMUUtypejjuhqMThrhhs]rh›)r‚}rƒ(h\X?Explicit markup ends without a blank line; unexpected unindent.hg}r„(hi]hj]hk]hl]ho]uh]j~hs]r…h|X?Explicit markup ends without a blank line; unexpected unindent.r†…r‡}rˆ(h\Uh]j‚ubahehŸubaubhY)r‰}rŠ(h\Uh]jþhchdhejhhg}r‹(hi]UlevelKhl]hk]Usourcehdhj]ho]UlineMøUtypejjuhqM÷hrhhs]rŒh›)r}rŽ(h\X%Line block ends without a blank line.hg}r(hi]hj]hk]hl]ho]uh]j‰hs]rh|X%Line block ends without a blank line.r‘…r’}r“(h\Uh]jubahehŸubaubeUcurrent_sourcer”NU decorationr•NUautofootnote_startr–KUnameidsr—}r˜(hjYhj(hj® h jÞh jE h jëh jh jL hjNhjmhjhj0hjLhjâhj$hjhjóhj¸hjùhjÀhjBhj‚ hjShjmhjhjÛh jmh!jªh"hñh#hßh$jh%j. h&j h'jÛh(jûh)jµ h*jÁh+j·h,j h-jÒh.jh/j˜h0j h1jØh2jÎh3j]h4j h5j£h6jW h7j±h8jÂh9jKh:jšh;jhjjh?jœ h@j²hAja hBhÆhChnhDj’ hEj”hFjThGjÈhHj9 hIjdhJjíhKj?hLjÿhMj…hNjºhOjœhPjˆhQj’hRj­hSjQhTjñuhs]r™haah\UU transformerršNU footnote_refsr›}rœUrefnamesr}ržUsymbol_footnotesrŸ]r Uautofootnote_refsr¡]r¢Usymbol_footnote_refsr£]r¤U citationsr¥]r¦hrhU current_liner§NUtransform_messagesr¨]r©UreporterrªNUid_startr«KU autofootnotesr¬]r­U citation_refsr®}r¯Uindirect_targetsr°]r±Usettingsr²(cdocutils.frontend Values r³or´}rµ(Ufootnote_backlinksr¶KUrecord_dependenciesr·NU rfc_base_urlr¸Uhttps://tools.ietf.org/html/r¹U tracebackrºˆUpep_referencesr»NUstrip_commentsr¼NU toc_backlinksr½j&U language_coder¾Uenr¿U datestamprÀNU report_levelrÁKU _destinationrÂNU halt_levelrÃKU strip_classesrÄNhyNUerror_encoding_error_handlerrÅUbackslashreplacerÆUdebugrÇNUembed_stylesheetrȉUoutput_encoding_error_handlerrÉUstrictrÊU sectnum_xformrËKUdump_transformsrÌNU docinfo_xformrÍKUwarning_streamrÎNUpep_file_url_templaterÏUpep-%04drÐUexit_status_levelrÑKUconfigrÒNUstrict_visitorrÓNUcloak_email_addressesrÔˆUtrim_footnote_reference_spacerÕ‰UenvrÖNUdump_pseudo_xmlr×NUexpose_internalsrØNUsectsubtitle_xformrÙ‰U source_linkrÚNUrfc_referencesrÛNUoutput_encodingrÜUutf-8rÝU source_urlrÞNUinput_encodingrßU utf-8-sigràU_disable_configráNU id_prefixrâUU tab_widthrãKUerror_encodingräUUTF-8råU_sourceræhdUgettext_compactrçˆU generatorrèNUdump_internalsréNU smart_quotesrê‰U pep_base_urlrëU https://www.python.org/dev/peps/rìUsyntax_highlightríUlongrîUinput_encoding_error_handlerrïjÊUauto_id_prefixrðUidrñUdoctitle_xformrò‰Ustrip_elements_with_classesróNU _config_filesrô]Ufile_insertion_enabledrõˆU raw_enabledröKU dump_settingsr÷NubUsymbol_footnote_startrøKUidsrù}rú(j’jjYjTj(j#jójïjÞjÙjÒh_jùjõj jjj˜j¸j´jSjOjNjIjmjhjjýj0j+j”jjâjÝj$jjj jÛjÖjÎjÊjL jG j j jÀj»jBj=j jÿ jñjíj‚ j~ jœ j— jªj¦jmjhjjjfj·j³jE j@ j j| hñhëjmjhjÿjûjÛjÖjûjöjÁj¼hßhÛj® j© jj™jjj˜j“jœj˜jØjÓj’ j j]jXhÆhÀj. j) j£jžjLjHjÂj½jKjFjšj•jjþjjjÁj¼j j j…jj9 j4 jW jR j±j­jTjOj²j®jÈjÃjdj_jíjèj?j:ja j\ jºjµjˆj„j­j¨jµ j± jQjLhnhajëjçuUsubstitution_namesrû}rühehrhg}rý(hi]hl]hk]Usourcehdhj]ho]uU footnotesrþ]rÿUrefidsr}rub.