cdocutils.nodes document q)q}q(U nametypesq}q(Xdsp-access-to-peripheralsqX%timer-suspend-control-options-for-dspqXuwhere can i find memory foot print, interrupt latency and performance numbers of the ti rtos when designing my systemqNX%pdk example and test project creationq X,ipc debugging tools and techniques on am57xxq NX+running-uart-readwrite-pdk-example-from-ccsq Xboot configurationq NX5connect-ethernet-cable-to-enable-network-connectivityq Xattaching after the issueqNXmulti-core-initializationqXverify componentsqNX;debugging tools and techniques with ipc3.x application noteqXadditional notes for gel usersqNX$viewing the state of the remote coreqNX(additional steps for am335x/am437x usersqNX ccs setupqNXVhow to debug common application issues like stack overflow, exception and memory leaksqNXRcreating debug configuration to integrate ccs gel and dmsc firmware initializationqNX0code composer studio (ccs) and emulation supportqNX%connect without an sd card boot imageqNX'ccs and sdk installed in same directoryqNXchanging-the-dsp-memory-mapqX;update-ccs-v6-to-install-keystone-ii-device-support-packageqX related-linksqXsetting up the hardwareqNXrun ipc examples on am572xqNXconnecting to ccsq NX(omap-l137/c6747 evm hardware setup guideq!NXdiscovering sdk productsq"NXconnecting-to-targetq#X2related article for processor sdk linux developersq$NX2connecting the amic110 ice to code composer studioq%NX0xdc.tools.configuro: missing input config scriptq&NXusageq'NX!creating the target configurationq(NXconnect to evmk2h using ccsq)NX%qnx – remote core state informationq*NXhardware setup stepsq+NX?processor sdk rtos porting guide for am571x/am570x speed gradesq,NXipc-ping-exampleq-X2advanced am65x debug setup with dmsc firmware loadq.NX&linux and android - remote core tracesq/NX#debugging mmu faults and exceptionsq0NX/processor-sdk-rtos-install-in-custom-path-labelq1Xrebuilding the sdk rtosq2NX+host driver for on-board mini-usb connectorq3NX'supported jtag debug probes (emulators)q4NXconnecting an emulatorq5NXk2h-set-no-boot-modeq6X>taking the c66x out of reset with linux running on the arm a15q7NX1what sys/bios debugging tools do we have in ccs ?q8NXYwhere does ti rtos application get the platform definition and memory sections on the socq9NX/ccs in default path and sdk rtos in custom pathq:NXconnecting-the-uartq;X66ak2gx gp evm hardware setupqNX unicache-mmuq?Xrebuilding the pdkq@NXpower managementqANX cma-carveoutsqBXam65xx ipc examplesqCNXbootmodeconfigurationqDXhardware setupqENXam335x ice evm hardware setupqFNXYhow to set input frequency in sysbios configuration and change timer used by clock moduleqGNX"open new target configuration fileqHNX crash dumpqINXquick-start-guideqJXcmemqKXreal time analysis(rta) agentqLNX$creating a target configuration fileqMNX(handling-ammu-l1-unicache-mmu-and-l2-mmuqNXdefault binaries and setupqONXpowering up the evmqPNX1minimum hardware setup required to connect to evmqQNX6how do i determine the call stack at the time of crashqRNXlinux quick start guideqSNXipc-hello-exampleqTX"connect with an sd card boot imageqUNXtracesqVNX*example custom board library for referenceqWNXGcreating pdk example/test projects when ccs is installed to custom pathqXNXlaunch target configurationqYNXdsp-physical-addressesqZXcontents-of-the-kitq[Xccs and pdk in custom pathq\NXconnectingemulatorq]X ccs-setupq^Xperform in-field updateq_NX requirementsq`NXiommuqaX1make-ccs-project-out-of-ex02_messageq-ipc-exampleqbXrunning board diagnosticsqcNX am65x evmqdNXccs and sdk rtos in custom pathqeNX:what is relationship between ti rtos and xdctools and rtscqfNX8adding-ipc-to-an-existing-ti-rtos-application-on-the-ipuqgX1attach the serial port cable to the soc uart portqhNXtmdxidk5728 hardware setupqiNX*ccs in custom path and pdk in default pathqjNXdirectory structureqkNXconnecting to a console windowqlNXipc-notify-peer-exampleqmXam65x debug software setupqnNXamic110 ice evm hardware setupqoNX@how to add custom compiler options and build custom bios libraryqpNX%timer suspend control options for dspqqNX)run baremetal applications from ddr on r5qrNXtmdxevm6670l evm hardware setupqsNX"clock and prcm updates to considerqtNXbootmode switchesquNXPxdc.cfg.sourcedir : build of generated source libraries failed: exit status = 2:qvNX<update-xds200-firmware-and-hardware-components-on-the-gp-evmqwX5how get uia logging working with ti rtos application?qxNXadditional referencesqyNXdriver soc module clock changesqzNX run-baremetal-app-from-ddr-on-r5q{Xlogging and traceq|NX(setup ccs for evm and processor-sdk rtosq}NXconnect the jtag interfaceq~NX how-to-guideqX0connecting to target and loading/running programqNXsys/bios – disabling watchdogqNXruntime object viewerqX(create target configuration file for evmqNXhardware-updates-requiredqX^create dsp and ipu firmware using pdk drivers and ipc to load from arm linux on am57xx devicesqNXprocessor sdk release notesqXexception handlingqNXrun-apps-from-ddr-on-r5-coresqXuart connectionqNXschema files not foundqNX>board library changes to consider for using processor sdk rtosqNXti rtos platform configurationqNXhostqNXdownload-the-full-ccs-projectqXrecommended boot modeqNXchanging the bootmodeqNX+connecting the lcdk to code composer studioqNXlinux and android - remoteprocqNXsoftware setupqNX*ccs in default path and pdk in custom pathqNX#cortex-m4-ipu-access-to-peripheralsqXLhow to configure crossbar when setting up interrupts on dra7xx/tda2xx/am57xxqNXsetting-boot-switchesqXpower-supply-specificationsqXconnect the power cableqNXdsp-virtual-addressesqXconnect to am57x slave coresqNX!pmic-auto-off-after-seven-secondsqXusing code composer studioqNX3update environment when installing to a custom pathqNXqnx - remote core tracesqNXucd power management updateqNX/typical-boot-flow-on-am572x-for-arm-linux-usersqXccs host setupqNXtargetqNXdwhat kind of heap should i use in sysbios application and how do i allocate heap in my configurationqNX.ccs and sdk installed in different directoriesqNX?how to take the c66x dsp out of reset with linux running on a15qNXhardware interrupts (hwi)qNXsoftwareqNX#ftdi driver installation on pc hostqNX)jtag-debug-probes-aka-emulators-supportedqX host-driversqX connecting to the cores on am65xqNXchanges to ccs configurationqNX1using sysbios with gnu gcc (for arm devices only)qNX"connect-after-booting-from-sd-cardqXoverviewqNX!changing-cortex-m4-ipu-memory-mapqX$run bios applications from ddr on r5qNXshow to place code and data sections in different memory location than set by default ti rtos platform configurationqNX<adding ipc to an existing ti-rtos application on slave coresqNXevmk2e hardware setup guideqNXconnect targetqNXconnect-power-to-the-evmqX1connecting the am3359 ice to code composer studioqNX application software developmentqNXk2h-spi-le-boot-modeqXtroubleshootingqNX'build-and-run-ex02_messageq-ipc-exampleqXexception dump decodingqNX$software-dependencies-to-get-startedqX0inspecting-the-dsp-iommu-page-tables-at-run-timeqXgo to product preferenceqNX$connect-without-a-sd-card-boot-imageqX(processor sdk rtos getting started guideqˆXBinstall latest emulation package and sitara device support packageqNX/ccs in custom path and sdk rtos in default pathqNXdra7xx/am572xx ipc examplesqNX introductionqNXsupportqNX%tmdsevm6657l evm hardware setup guideqNXbmc in-field updateqNXadditional notes for am57xqNX,ucd power management modules in-field updateqNXboot mode dip switch settingsqNXtarget configurationqNXk2e-set-no-boot-modeqΈX sample outputqNXclocks and timersqNX.flash bootable images (c66x, k2h/k2e/k2l only)qNXipc-message-queue-exampleq҈X debug symbolsqNXbmc version check and updateqNXNcustomizing memory map for creating multicore applications on am57xx using ipcqNXevm k2e how to guidesqNXuseful-resources-and-supportq׈XQhow to create custom platform like ddrless platforms to use with ti rtos projectsqNX?install the latest emulation package and device support packageqNXsuccess!qNXVwhat are the different clock and timer modules in ti rtos that you should be aware of?qNX:how can i get dump of registers when an exception occurs ?qNXportingqNX semihostingqNXunderstanding the memory mapqNX cortex-m4-ipu-physical-addressesqX thread typesqNX%tmdxevm6678l evm hardware setup guideqNXgeneric ti rtos questionsqNX1instructions to add custom board to the pdk buildqNX/comparison of am572x, am571x and am570x devicesqNXadd-ipc-to-the-uart-exampleqXrun ipc examples on am65xxqNXsave target configurationqNX(configuring-target-configuration-files-1qXprepare evm for in-field updateqNXsetupqNXcan you use any sysbios version with any version of xdctools when creating create or migrating to ti rtos based application development environmentqNXlinux and android - iommu infoqNXLrtos customization: using an external input to trigger an interrupt on am57xqNXattaching before the issueqNX8update ccs to install keystone ii device support packageqNX@are there any graphical tools to configure sysbios configurationqNX&dip switch and bootmode configurationsqNX-what is the difference between swis and tasksqNX benchmarksqNXtracingqNXuseful resources and supportqNXevm-layout-and-key-componentsqXpowering-up-the-evmqX)how can you route exception print to uartqNX7why can`t i see output of system_printf on ccs console?qNXoverall-linux-memory-mapqX debuggingqNXti rtos basicsqNXevm hardware setupqNX+update-the-evm-for-improved-usb-performanceqX#ddr configuration (rev 0b evm only)rNX5linux and android - disabling remoteproc auto-suspendrNX add-ipc-to-the-led-blink-examplerX&running-led-blink-pdk-example-from-ccsrXremote core status informationrNX mmu faultsrNX'getting started with ipc linux examplesrNX#omap-l138/c6748 lcdk hardware setuprNXhardwarerNXti rtos tips & tricksr NXsystem integrationr NXOhow do i port existing application developed on sysbios application to smp/biosr NX0rtsc diagnostics: understanding xdc build errorsr NXview target configurationsr NXrun-bios-app-from-ddr-on-r5rXevm layout and key componentsrNXPxdc.tools.configuro: can't locate the package 'package name' along the path: ...rNX8adding-ipc-to-an-existing-ti-rtos-application-on-the-dsprXworkaround-for-this-issuerX6how to get accurate clock ticks from the clock module?rNXquick start guiderNX3how to add house keeping functions in the idle taskrNXpowering the lcdkrNXqnx - adding tracesrNXsettingbootswitchesrXchanging-soc-operating-pointrXam572x gp evm hardware setuprNXIhow to enable printf/system_printf to go to ccs io console on arm devicesrNXexpanding-ipc-ping-examplerXminimal-evm-setuprX"rebuild drivers from pdk directoryrNX66ak2g audio dc addonrNX*connecting-idk-evm-to-code-composer-studior Xattach the ethernet cabler!NXtestr"NXmemory and heapr#NX.prevent beaglebone board reset on jtag connectr$NXconfiguringtargetconfigfiler%XLupdate-linux-kernel-device-tree-to-remove-uart-that-will-be-controlled-by-m4r&Xhardware setup overviewr'NXsetting boot switchesr(NX66ak2g02 ice evm hardware setupr)NX k2h set the boot mode switch sw1r*NX descriptionr+X,linux and android - disabling error recoveryr,NXevmk2h hardware setup guider-NXcortex-m4-ipu-virtual-addressesr.Xenter path to sdkr/NXgel-file-optionsr0X debug toolsr1NX(linux and android – disabling watchdogr2NX qnx – disabling error recoveryr3NXrtos object view(rov)r4NX!building-the-bundled-ipc-examplesr5X'linux and android - enabling ipc tracesr6NX"update-the-bmc-firmware-on-the-evmr7X!connect-with-a-sd-card-boot-imager8X%run applications from ddr on r5 coresr9NXother-how-to-optionsr:Xbasic ccs setupr;NXsoftware-update-requiredr<X#select target configuration optionsr=NXuseful-utilitiesr>X-rev 1.0 evm sw1 switch bootmode configurationr?NXk2e-spi-le-boot-moder@X"processor-sdk-rtos-setup-ccs-labelrAXconfigure ddr interfacesrBNX running-the-bundled-ipc-examplesrCX*create-sd-card-to-boot-linux-on-the-gp-evmrDXqnx – enabling ipc tracesrENXlinux and android - debugfsrFNXconnecting-emulatorrGXpowering the evmrHNXcode composer studiorINXpinmux changes to considerrJNX#connect target and load/run programrKNX restart ccsrLNX&configuring-target-configuration-filesrMXhardware user's guiderNX k2e set the boot mode switch sw1rONXtest target configurationrPNXminimal evm setuprQNuUsubstitution_defsrR}rSUparse_messagesrT]rU(cdocutils.nodes system_message rV)rW}rX(U rawsourcerYUUparentrZcdocutils.nodes section r[)r\}r](jYUjZj[)r^}r_(jYUjZj[)r`}ra(jYUjZhUsourcerbXR/home/gtbldadm/nightlybuilds/processor-sdk-doc/source/rtos/index_how_to_guides.rstrcUtagnamerdUsectionreU attributesrf}rg(Udupnamesrh]Uclassesri]Ubackrefsrj]Uidsrk]rlUtargetrmaUnamesrn]rohauUlinerpKUdocumentrqhUchildrenrr]rs(cdocutils.nodes title rt)ru}rv(jYXTargetrwjZj`jbjcjdUtitlerxjf}ry(jh]ji]jj]jk]jn]ujpKjqhjr]rzcdocutils.nodes Text r{XTargetr|r}}r~(jYjwjZjuubaubj^j[)r}r(jYUjZj`jbjcjdjejf}r(jh]ji]jj]jk]rUrun-ipc-examples-on-am65xxrajn]rhaujpK jqhjr]r(jt)r}r(jYXRun IPC Examples on AM65XXrjZjjbjcjdjxjf}r(jh]ji]jj]jk]jn]ujpK jqhjr]rj{XRun IPC Examples on AM65XXrr}r(jYjjZjubaubj[)r}r(jYUjZjjbcdocutils.nodes reprunicode rXCsource/rtos/How_to_Guides/Target/Run_IPC_Examples_on_AM65xx.rst.incrr}rbjdjejf}r(jh]ji]jj]jk]rUam65xx-ipc-examplesrajn]rhCaujpKjqhjr]r(jt)r}r(jYXAM65xx IPC ExamplesrjZjjbjjdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XAM65xx IPC Examplesrr}r(jYjjZjubaubcdocutils.nodes paragraph r)r}r(jYXaIn the processor SDK release ipc examples can be built from the Processor SDK top level makefile.rjZjjbjjdU paragraphrjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XaIn the processor SDK release ipc examples can be built from the Processor SDK top level makefile.rr}r(jYjjZjubaubj)r}r(jYX"See link for building IPC examplesrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X"See link for building IPC examplesrr}r(jYjjZjubaubj)r}r(jYX:ref:`ipc-rtos-examples`rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK jqhjr]rcsphinx.addnodes pending_xref r)r}r(jYjjZjjbjjdU pending_xrefrjf}r(UreftypeXrefUrefwarnrU reftargetrXipc-rtos-examplesU refdomainXstdrjk]jj]U refexplicitjh]ji]jn]UrefdocrXrtos/index_how_to_guidesrujpK jr]rcdocutils.nodes inline r)r}r(jYjjf}r(jh]ji]r(UxrefrjXstd-refrejj]jk]jn]ujZjjr]rj{Xipc-rtos-examplesrr}r(jYUjZjubajdUinlinerubaubaubj)r}r(jYXOnce the examples are built, they can be run by loading and running the binaries using CCS through JTAG. Please refer to the section "Advanced AM65x Debug Setup with DMSC Firmware Load" of the TMDX654 EVM Hardware Setup Guide for setting up the JTAG.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK jqhjr]rj{XOnce the examples are built, they can be run by loading and running the binaries using CCS through JTAG. Please refer to the section "Advanced AM65x Debug Setup with DMSC Firmware Load" of the TMDX654 EVM Hardware Setup Guide for setting up the JTAG.rr}r(jYjjZjubaubj)r}r(jYX5`Advanced AM65x Debug Setup with DMSC Firmware Load`_rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rcdocutils.nodes reference r)r}r(jYjUresolvedrKjZjjdU referencerjf}r(UnameX2Advanced AM65x Debug Setup with DMSC Firmware Loadjk]jj]jh]ji]jn]UrefidrU2advanced-am65x-debug-setup-with-dmsc-firmware-loadrujr]rj{X2Advanced AM65x Debug Setup with DMSC Firmware Loadrr}r(jYUjZjubaubaubcdocutils.nodes rubric r)r}r(jYXIPC Message Queue Example:rU referencedrKjZjjbjjdUrubricrjf}r(jk]rUid1rajj]jh]rXipc-message-queue-exampleraji]jn]ujpNjqhjr]rj{XIPC Message Queue Example:rr}r(jYjjZjubaubj)r}r(jYX**ex02_messageq**rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rcdocutils.nodes strong r)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X ex02_messageqrr}r(jYUjZjubajdUstrongrubaubj)r}r(jYXMessage queue example sends round-trip message from client to server and back. MessageQ example uses client/server pattern. It is a two processors example: the HOST and R5F-0 processor.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r j{XMessage queue example sends round-trip message from client to server and back. MessageQ example uses client/server pattern. It is a two processors example: the HOST and R5F-0 processor.r r }r (jYjjZjubaubj)r }r(jYXThe R5F-0 processor is configured as server. It creates a named message queue. The server does not open any queues because it extracts the return address from the message header. The server returns all messages to the sender. It does not access the message pool.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XThe R5F-0 processor is configured as server. It creates a named message queue. The server does not open any queues because it extracts the return address from the message header. The server returns all messages to the sender. It does not access the message pool.rr}r(jYjjZj ubaubj)r}r(jYXThe HOST processor is configured as client application. The client creates an anonymous message queue. The client also creates and manages the message pool. The client's return address is set in the message header for each message before sending it to the server.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XThe HOST processor is configured as client application. The client creates an anonymous message queue. The client also creates and manages the message pool. The client's return address is set in the message header for each message before sending it to the server.rr}r(jYjjZjubaubj)r}r(jYX&Here are the steps to run the example.rjZjjbjjdjjf}r (jh]ji]jj]jk]jn]ujpK#jqhjr]r!j{X&Here are the steps to run the example.r"r#}r$(jYjjZjubaubcdocutils.nodes enumerated_list r%)r&}r'(jYUjZjjbjjdUenumerated_listr(jf}r)(Usuffixr*U.jk]jj]jh]Uprefixr+Uji]jn]Uenumtyper,Uarabicr-ujpK%jqhjr]r.cdocutils.nodes list_item r/)r0}r1(jYXFollow instructions above to build the IPC examples. The build will create the R5F-0 and HOST binaries under debug and release sub folders For examplejZj&jbjjdU list_itemr2jf}r3(jh]ji]jj]jk]jn]ujpNjqhjr]r4j)r5}r6(jYXFollow instructions above to build the IPC examples. The build will create the R5F-0 and HOST binaries under debug and release sub folders For exampler7jZj0jbjjdjjf}r8(jh]ji]jj]jk]jn]ujpK%jr]r9j{XFollow instructions above to build the IPC examples. The build will create the R5F-0 and HOST binaries under debug and release sub folders For exampler:r;}r<(jYj7jZj5ubaubaubaubcdocutils.nodes block_quote r=)r>}r?(jYUjZjjbNjdU block_quoter@jf}rA(jh]ji]jj]jk]jn]ujpNjqhjr]rBcdocutils.nodes bullet_list rC)rD}rE(jYUjf}rF(UbulletrGX-jk]jj]jh]ji]jn]ujZj>jr]rH(j/)rI}rJ(jYXSAM65XX_bios_elf\\ex02_messageq\\host\\bin\\debug\\app_host.xa53fg : HOST A15 binaryrKjf}rL(jh]ji]jj]jk]jn]ujZjDjr]rMj)rN}rO(jYjKjZjIjbjjdjjf}rP(jh]ji]jj]jk]jn]ujpK'jr]rQj{XNAM65XX_bios_elf\ex02_messageq\host\bin\debug\app_host.xa53fg : HOST A15 binaryrRrS}rT(jYXSAM65XX_bios_elf\\ex02_messageq\\host\\bin\\debug\\app_host.xa53fg : HOST A15 binaryjZjNubaubajdj2ubj/)rU}rV(jYXQAM65XX_bios_elfex02_messageq\\r5f-0\\bin\\debug\\server_r5f-0.xer5fg : R5 binary jf}rW(jh]ji]jj]jk]jn]ujZjDjr]rXj)rY}rZ(jYXPAM65XX_bios_elfex02_messageq\\r5f-0\\bin\\debug\\server_r5f-0.xer5fg : R5 binaryjZjUjbjjdjjf}r[(jh]ji]jj]jk]jn]ujpK(jr]r\j{XLAM65XX_bios_elfex02_messageq\r5f-0\bin\debug\server_r5f-0.xer5fg : R5 binaryr]r^}r_(jYXPAM65XX_bios_elfex02_messageq\\r5f-0\\bin\\debug\\server_r5f-0.xer5fg : R5 binaryjZjYubaubajdj2ubejdU bullet_listr`ubaubj%)ra}rb(jYUjZjjbjjdj(jf}rc(j*U.UstartrdKjk]jj]jh]j+Uji]jn]j,j-ujpK*jqhjr]re(j/)rf}rg(jYXFollow procedure to initialize platform and launch target configuration through steps outlined in the hardware setup guide referred above. jZjajbjjdj2jf}rh(jh]ji]jj]jk]jn]ujpNjqhjr]rij)rj}rk(jYXFollow procedure to initialize platform and launch target configuration through steps outlined in the hardware setup guide referred above.rljZjfjbjjdjjf}rm(jh]ji]jj]jk]jn]ujpK*jr]rnj{XFollow procedure to initialize platform and launch target configuration through steps outlined in the hardware setup guide referred above.rorp}rq(jYjljZjjubaubaubj/)rr}rs(jYX*Right click R5 core 0 and connect target. jZjajbjjdj2jf}rt(jh]ji]jj]jk]jn]ujpNjqhjr]ruj)rv}rw(jYX)Right click R5 core 0 and connect target.rxjZjrjbjjdjjf}ry(jh]ji]jj]jk]jn]ujpK-jr]rzj{X)Right click R5 core 0 and connect target.r{r|}r}(jYjxjZjvubaubaubj/)r~}r(jYXO**Load R5F-0** messageQ Example out file(server_r5f-0.xer5fg) onto R5F core 0. jZjajbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXN**Load R5F-0** messageQ Example out file(server_r5f-0.xer5fg) onto R5F core 0.jZj~jbjjdjjf}r(jh]ji]jj]jk]jn]ujpK/jr]r(j)r}r(jYX**Load R5F-0**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X Load R5F-0rr}r(jYUjZjubajdjubj{X@ messageQ Example out file(server_r5f-0.xer5fg) onto R5F core 0.rr}r(jYX@ messageQ Example out file(server_r5f-0.xer5fg) onto R5F core 0.jZjubeubaubj/)r}r(jYX,Right click CortexA53_0 and connect target. jZjajbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYX+Right click CortexA53_0 and connect target.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK1jr]rj{X+Right click CortexA53_0 and connect target.rr}r(jYjjZjubaubaubj/)r}r(jYXO**Load HOST** messageQ Example out file(app_host.xa53fg) onto ARM CortexA53_0. jZjajbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXN**Load HOST** messageQ Example out file(app_host.xa53fg) onto ARM CortexA53_0.jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK3jr]r(j)r}r(jYX **Load HOST**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X Load HOSTrr}r(jYUjZjubajdjubj{XA messageQ Example out file(app_host.xa53fg) onto ARM CortexA53_0.rr}r(jYXA messageQ Example out file(app_host.xa53fg) onto ARM CortexA53_0.jZjubeubaubj/)r}r(jYXRun both R5F-0 and HOST. jZjajbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXRun both R5F-0 and HOST.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK5jr]rj{XRun both R5F-0 and HOST.rr}r(jYjjZjubaubaubj/)r}r(jYX-On CCS --> Tools --> RTOS Object view (ROV). jZjajbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYX,On CCS --> Tools --> RTOS Object view (ROV).rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK7jr]rj{X,On CCS --> Tools --> RTOS Object view (ROV).rr}r(jYjjZjubaubaubj/)r}r(jYXXSuspend (halt) ARM Cortex_53 to view test messages on ROV Viewable Modules -->LoggerBuf jZjajbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXWSuspend (halt) ARM Cortex_53 to view test messages on ROV Viewable Modules -->LoggerBufrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK9jr]rj{XWSuspend (halt) ARM Cortex_53 to view test messages on ROV Viewable Modules -->LoggerBufrr}r(jYjjZjubaubaubj/)r}r(jYXASuspend (halt) R5F-0 and click on ROV icon to view log messages. jZjajbXZinternal padding after source/rtos/How_to_Guides/Target/Run_IPC_Examples_on_AM65xx.rst.incrjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYX@Suspend (halt) R5F-0 and click on ROV icon to view log messages.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK;jr]rj{X@Suspend (halt) R5F-0 and click on ROV icon to view log messages.rr}r(jYjjZjubaubaubeubeubeubj[)r}r(jYUjZj`jbjcjdjejf}r(jh]ji]jj]jk]rU>taking-the-c66x-out-of-reset-with-linux-running-on-the-arm-a15rajn]rh7aujpKjqhjr]r(jt)r}r(jYX>Taking the C66x Out Of Reset with Linux Running on the ARM A15rjZjjbjcjdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X>Taking the C66x Out Of Reset with Linux Running on the ARM A15rr}r(jYjjZjubaubcdocutils.nodes comment r)r}r(jYXfhttp://processors.wiki.ti.com/index.php/Taking_the_C66x_Out_Of_Reset_with_Linux_Running_on_the_ARM_A15jZjjbjXJsource/rtos/How_to_Guides/Target/C66x_Reset_from_A15_Running_Linux.rst.incrr}rbjdUcommentrjf}r(U xml:spacerUpreserverjk]jj]jh]ji]jn]ujpKjqhjr]rj{Xfhttp://processors.wiki.ti.com/index.php/Taking_the_C66x_Out_Of_Reset_with_Linux_Running_on_the_ARM_A15rr}r(jYUjZjubaubj[)r}r(jYUjZjjbjjdjejf}r(jh]ji]jj]jk]rU?how-to-take-the-c66x-dsp-out-of-reset-with-linux-running-on-a15rajn]rhaujpKjqhjr]r(jt)r}r(jYX?How to take the C66x DSP out of reset with Linux running on A15rjZjjbjjdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X?How to take the C66x DSP out of reset with Linux running on A15rr }r (jYjjZjubaubj)r }r (jYX This document describes the procedure to bring the C66x core out of reset after booting Linux, or at the u-boot prompt.These steps are necessary in to order to load an application on the C66x core, without interfering with the operation of Linux running on the A15.r jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X This document describes the procedure to bring the C66x core out of reset after booting Linux, or at the u-boot prompt.These steps are necessary in to order to load an application on the C66x core, without interfering with the operation of Linux running on the A15.rr}r(jYj jZj ubaubcdocutils.nodes note r)r}r(jYXPrior to proceeding with the below instructions, please ensure that the latest :ref:`Emulation Package<>` is downloaded/installed through CCS. This will ensure the GEL files in your machine has the reset routines described below.jZjjbjjdUnoterjf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXPrior to proceeding with the below instructions, please ensure that the latest :ref:`Emulation Package<>` is downloaded/installed through CCS. This will ensure the GEL files in your machine has the reset routines described below.jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK jr]r(j{XOPrior to proceeding with the below instructions, please ensure that the latest rr}r(jYXOPrior to proceeding with the below instructions, please ensure that the latest jZjubj)r }r!(jYX:ref:`Emulation Package<>`r"jZjjbjjdjjf}r#(UreftypeXrefjjXU refdomainXstdr$jk]jj]U refexplicitjh]ji]jn]jjujpK jr]r%j)r&}r'(jYj"jf}r((jh]ji]r)(jj$Xstd-refr*ejj]jk]jn]ujZj jr]r+j{XEmulation Packager,r-}r.(jYUjZj&ubajdjubaubj{X| is downloaded/installed through CCS. This will ensure the GEL files in your machine has the reset routines described below.r/r0}r1(jYX| is downloaded/installed through CCS. This will ensure the GEL files in your machine has the reset routines described below.jZjubeubaubj%)r2}r3(jYUjZjjbjjdj(jf}r4(j*U)jk]jj]jh]j+Uji]jn]j,j-ujpKjqhjr]r5j/)r6}r7(jYX8Once Linux has booted, launch the target configuration. jZj2jbjjdj2jf}r8(jh]ji]jj]jk]jn]ujpNjqhjr]r9j)r:}r;(jYX7Once Linux has booted, launch the target configuration.r<jZj6jbjjdjjf}r=(jh]ji]jj]jk]jn]ujpKjr]r>j{X7Once Linux has booted, launch the target configuration.r?r@}rA(jYj<jZj:ubaubaubaubcdocutils.nodes image rB)rC}rD(jYX+.. Image:: ../images/Outofreset_1_lali.JPG jZjjbjjdUimagerEjf}rF(UuriX$rtos/../images/Outofreset_1_lali.JPGrGjk]jj]jh]ji]U candidatesrH}rIU*jGsjn]ujpKjqhjr]ubj%)rJ}rK(jYUjZjjbjjdj(jf}rL(j*U)jdKjk]jj]jh]j+Uji]jn]j,j-ujpKjqhjr]rMj/)rN}rO(jYXaWith the target configuration launched, right click on K2x.ccxml and select “Show all cores” jZjJjbjjdj2jf}rP(jh]ji]jj]jk]jn]ujpNjqhjr]rQj)rR}rS(jYX`With the target configuration launched, right click on K2x.ccxml and select “Show all cores”rTjZjNjbjjdjjf}rU(jh]ji]jj]jk]jn]ujpKjr]rVj{X`With the target configuration launched, right click on K2x.ccxml and select “Show all cores”rWrX}rY(jYjTjZjRubaubaubaubjB)rZ}r[(jYX+.. Image:: ../images/Outofreset_2_lali.JPG jZjjbjjdjEjf}r\(UuriX$rtos/../images/Outofreset_2_lali.JPGr]jk]jj]jh]ji]jH}r^U*j]sjn]ujpKjqhjr]ubj%)r_}r`(jYUjZjjbjjdj(jf}ra(j*U)jdKjk]jj]jh]j+Uji]jn]j,j-ujpKjqhjr]rbj/)rc}rd(jYXiThis will bring up the Non-Debuggable Devices section. Right click and connect the CS_DAP_Debug_SS core. jZj_jbjjdj2jf}re(jh]ji]jj]jk]jn]ujpNjqhjr]rfj)rg}rh(jYXhThis will bring up the Non-Debuggable Devices section. Right click and connect the CS_DAP_Debug_SS core.rijZjcjbjjdjjf}rj(jh]ji]jj]jk]jn]ujpKjr]rkj{XhThis will bring up the Non-Debuggable Devices section. Right click and connect the CS_DAP_Debug_SS core.rlrm}rn(jYjijZjgubaubaubaubjB)ro}rp(jYX+.. Image:: ../images/Outofreset_3_lali.JPG jZjjbjjdjEjf}rq(UuriX$rtos/../images/Outofreset_3_lali.JPGrrjk]jj]jh]ji]jH}rsU*jrsjn]ujpKjqhjr]ubj%)rt}ru(jYUjZjjbjjdj(jf}rv(j*U)jdKjk]jj]jh]j+Uji]jn]j,j-ujpKjqhjr]rwj/)rx}ry(jYXGo to Tools>GEL files and load the evmk2x.gel file by right clicking on the GEL file window. The Gel file would typically be located in the CCS installation under \\ccsv6\\ccs_base\\emulation\\boards\\evmk2x\\gel\\ jZjtjbjjdj2jf}rz(jh]ji]jj]jk]jn]ujpNjqhjr]r{j)r|}r}(jYXGo to Tools>GEL files and load the evmk2x.gel file by right clicking on the GEL file window. The Gel file would typically be located in the CCS installation under \\ccsv6\\ccs_base\\emulation\\boards\\evmk2x\\gel\\jZjxjbjjdjjf}r~(jh]ji]jj]jk]jn]ujpKjr]rj{XGo to Tools>GEL files and load the evmk2x.gel file by right clicking on the GEL file window. The Gel file would typically be located in the CCS installation under \ccsv6\ccs_base\emulation\boards\evmk2x\gel\rr}r(jYXGo to Tools>GEL files and load the evmk2x.gel file by right clicking on the GEL file window. The Gel file would typically be located in the CCS installation under \\ccsv6\\ccs_base\\emulation\\boards\\evmk2x\\gel\\jZj|ubaubaubaubjB)r}r(jYX+.. Image:: ../images/Outofreset_4_lali.png jZjjbjjdjEjf}r(UuriX$rtos/../images/Outofreset_4_lali.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpK#jqhjr]ubj%)r}r(jYUjZjjbjjdj(jf}r(j*U)jdKjk]jj]jh]j+Uji]jn]j,j-ujpK$jqhjr]rj/)r}r(jYXcOnce the GEL has been successfully loaded, go to Scripts>default and select K2x_TakeDSPOutofReset. jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXbOnce the GEL has been successfully loaded, go to Scripts>default and select K2x_TakeDSPOutofReset.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK$jr]rj{XbOnce the GEL has been successfully loaded, go to Scripts>default and select K2x_TakeDSPOutofReset.rr}r(jYjjZjubaubaubaubjB)r}r(jYX+.. Image:: ../images/Outofreset_5_lali.png jZjjbjjdjEjf}r(UuriX$rtos/../images/Outofreset_5_lali.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpK'jqhjr]ubj%)r}r(jYUjZjjbjjdj(jf}r(j*U)jdKjk]jj]jh]j+Uji]jn]j,j-ujpK(jqhjr]rj/)r}r(jYXGAt this point the console would indicate that the DSP is out of reset. jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXFAt this point the console would indicate that the DSP is out of reset.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK(jr]rj{XFAt this point the console would indicate that the DSP is out of reset.rr}r(jYjjZjubaubaubaubjB)r}r(jYX+.. Image:: ../images/Outofreset_6_lali.png jZjjbjjdjEjf}r(UuriX$rtos/../images/Outofreset_6_lali.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpK+jqhjr]ubj%)r}r(jYUjZjjbjjdj(jf}r(j*U)jdKjk]jj]jh]j+Uji]jn]j,j-ujpK,jqhjr]rj/)r}r(jYXCNow the DSP cores can be right-clicked and connected successfully. jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXBNow the DSP cores can be right-clicked and connected successfully.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK,jr]rj{XBNow the DSP cores can be right-clicked and connected successfully.rr}r(jYjjZjubaubaubaubjB)r}r(jYX+.. Image:: ../images/Outofreset_7_lali.png jZjjbjjdjEjf}r(UuriX$rtos/../images/Outofreset_7_lali.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpK/jqhjr]ubeubj[)r}r(jYUjKjZjjbjjdjejf}r(jh]rXtarget configurationraji]jj]jk]rUtarget-configurationrajn]ujpK1jqhjr]r(jt)r}r(jYXTarget ConfigurationrjZjjbjjdjxjf}r(jh]ji]jj]jk]jn]ujpK1jqhjr]rj{XTarget Configurationrr}r(jYjjZjubaubj)r}r(jYX(Once the DSP core is connected following the above out of reset routine, the DDR and PLL settings done by u-boot would be overwritten by what's in the GEL. In order to avoid this, please ensure that the gel is NOT preloaded on the DSP core in the ccxml by leaving the initialization script blank.jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYX(Once the DSP core is connected following the above out of reset routine, the DDR and PLL settings done by u-boot would be overwritten by what's in the GEL. In order to avoid this, please ensure that the gel is NOT preloaded on the DSP core in the ccxml by leaving the initialization script blank.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK4jr]rj{X(Once the DSP core is connected following the above out of reset routine, the DDR and PLL settings done by u-boot would be overwritten by what's in the GEL. In order to avoid this, please ensure that the gel is NOT preloaded on the DSP core in the ccxml by leaving the initialization script blank.rr}r(jYjjZjubaubaubjB)r}r(jYX,.. Image:: ../images/Outofreset_8_lali.JPG jZjjbXainternal padding after source/rtos/How_to_Guides/Target/C66x_Reset_from_A15_Running_Linux.rst.incrjdjEjf}r(UuriX$rtos/../images/Outofreset_8_lali.JPGrjk]jj]jh]ji]jH}rU*jsjn]ujpK;jqhjr]ubeubeubj[)r}r(jYUjZj`jbjcjdjejf}r(jh]ji]jj]jk]rUKrtos-customization-using-an-external-input-to-trigger-an-interrupt-on-am57xrajn]rhaujpKjqhjr]r(jt)r}r(jYXLRTOS Customization: using an external input to trigger an interrupt on AM57xrjZjjbjcjdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XLRTOS Customization: using an external input to trigger an interrupt on AM57xrr}r(jYjjZjubaubj)r}r(jYXThis note explains how to develop an example using a General-Purpose Input/Output (GPIO) pin to capture an external input event and generate an interrupt by modifying an existing RTOS GPIO driver LED blinking example. The hardware setup, software development procedures and testing are done using TI AM572x IDK EVM. The same process can be extended to other TI Sitara devices, TI EVMs or custom platforms as well.rjZjjbjXOsource/rtos/How_to_Guides/Target/External_Input_Trigger_Interrupt_AM57x.rst.incrr}rbjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XThis note explains how to develop an example using a General-Purpose Input/Output (GPIO) pin to capture an external input event and generate an interrupt by modifying an existing RTOS GPIO driver LED blinking example. The hardware setup, software development procedures and testing are done using TI AM572x IDK EVM. The same process can be extended to other TI Sitara devices, TI EVMs or custom platforms as well.rr}r(jYjjZjubaubj[)r}r(jYUjKjZjjbjjdjejf}r(jh]rXhardwareraji]jj]jk]rUhardwarer ajn]ujpKjqhjr]r (jt)r }r (jYXHardwarer jZjjbjjdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XHardwarerr}r(jYj jZj ubaubj)r}r(jYX`The AM572x Industrial Development Kit (IDK) `__ is used here for developing the example. The same expect to work with the `AM574x IDK `__ as well.jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r(j)r}r(jYXT`The AM572x Industrial Development Kit (IDK) `__jf}r(UnameX+The AM572x Industrial Development Kit (IDK)UrefurirX"http://www.ti.com/tool/TMDXIDK5728jk]jj]jh]ji]jn]ujZjjr]rj{X+The AM572x Industrial Development Kit (IDK)rr}r(jYUjZjubajdjubj{XK is used here for developing the example. The same expect to work with the rr }r!(jYXK is used here for developing the example. The same expect to work with the jZjubj)r"}r#(jYX2`AM574x IDK `__jf}r$(UnameX AM574x IDKjX!http://www.ti.com/tool/TMDSIDK574jk]jj]jh]ji]jn]ujZjjr]r%j{X AM574x IDKr&r'}r((jYUjZj"ubajdjubj{X as well.r)r*}r+(jYX as well.jZjubeubj)r,}r-(jYX~From the `AM572x IDK EVM hardware user guide `__, the card has 3 push buttons: SW1, SW2 and SW3, but they all are used for different purposes. However, the card has a 60-pin female expansion connector J21, pins that are not used may be dedicated for GPIO input test purpose. Here J21 pin 4 is selected based on the following analysis:jZjjbjjdjjf}r.(jh]ji]jj]jk]jn]ujpK jqhjr]r/(j{X From the r0r1}r2(jYX From the jZj,ubj)r3}r4(jYXW`AM572x IDK EVM hardware user guide `__jf}r5(UnameX"AM572x IDK EVM hardware user guidejX.http://www.ti.com/lit/ug/sprui64c/sprui64c.pdfjk]jj]jh]ji]jn]ujZj,jr]r6j{X"AM572x IDK EVM hardware user guider7r8}r9(jYUjZj3ubajdjubj{X, the card has 3 push buttons: SW1, SW2 and SW3, but they all are used for different purposes. However, the card has a 60-pin female expansion connector J21, pins that are not used may be dedicated for GPIO input test purpose. Here J21 pin 4 is selected based on the following analysis:r:r;}r<(jYX, the card has 3 push buttons: SW1, SW2 and SW3, but they all are used for different purposes. However, the card has a 60-pin female expansion connector J21, pins that are not used may be dedicated for GPIO input test purpose. Here J21 pin 4 is selected based on the following analysis:jZj,ubeubjC)r=}r>(jYUjZjjbjjdj`jf}r?(jGX•jk]jj]jh]ji]jn]ujpKjqhjr]r@j/)rA}rB(jYXkThe Pin 4 signal is labeled as GPMC_CS0 and is connected to AM572x chip ball T1 as shown in the schematic: jZj=jbjjdj2jf}rC(jh]ji]jj]jk]jn]ujpNjqhjr]rDj)rE}rF(jYXjThe Pin 4 signal is labeled as GPMC_CS0 and is connected to AM572x chip ball T1 as shown in the schematic:rGjZjAjbjjdjjf}rH(jh]ji]jj]jk]jn]ujpKjr]rIj{XjThe Pin 4 signal is labeled as GPMC_CS0 and is connected to AM572x chip ball T1 as shown in the schematic:rJrK}rL(jYjGjZjEubaubaubaubjB)rM}rN(jYX'.. Image:: ../images/J21_gpio_input.pngrOjZjjbjjdjEjf}rP(UuriX!rtos/../images/J21_gpio_input.pngrQjk]jj]jh]ji]jH}rRU*jQsjn]ujpKjqhjr]ubjB)rS}rT(jYX%.. Image:: ../images/gpmc_cs0_t1.png jZjjbjjdjEjf}rU(UuriXrtos/../images/gpmc_cs0_t1.pngrVjk]jj]jh]ji]jH}rWU*jVsjn]ujpKjqhjr]ubjC)rX}rY(jYUjZjjbjjdj`jf}rZ(jGX•jk]jj]jh]ji]jn]ujpKjqhjr]r[j/)r\}r](jYXnFrom the AM5728 datasheet, T1 ball can be configured as GPMC_CS0 or GPIO2_19 based on different PINMUX modes. jZjXjbjjdj2jf}r^(jh]ji]jj]jk]jn]ujpNjqhjr]r_j)r`}ra(jYXmFrom the AM5728 datasheet, T1 ball can be configured as GPMC_CS0 or GPIO2_19 based on different PINMUX modes.rbjZj\jbjjdjjf}rc(jh]ji]jj]jk]jn]ujpKjr]rdj{XmFrom the AM5728 datasheet, T1 ball can be configured as GPMC_CS0 or GPIO2_19 based on different PINMUX modes.rerf}rg(jYjbjZj`ubaubaubaubeubj[)rh}ri(jYUjZjjbjjdjejf}rj(jh]ji]jj]jk]rkUsoftwarerlajn]rmhaujpKjqhjr]rn(jt)ro}rp(jYXSoftwarerqjZjhjbjjdjxjf}rr(jh]ji]jj]jk]jn]ujpKjqhjr]rsj{XSoftwarertru}rv(jYjqjZjoubaubj)rw}rx(jYXThe GPIO LED blink example is served as the reference example and the test is developed on the ARM A15 core, it should work for other cores. This section discusses several typical steps involved in the software development work:ryjZjhjbjjdjjf}rz(jh]ji]jj]jk]jn]ujpKjqhjr]r{j{XThe GPIO LED blink example is served as the reference example and the test is developed on the ARM A15 core, it should work for other cores. This section discusses several typical steps involved in the software development work:r|r}}r~(jYjyjZjwubaubjC)r}r(jYUjZjhjbjjdj`jf}r(jGX•jk]jj]jh]ji]jn]ujpKjqhjr]r(j/)r}r(jYXPinMux configurationrjZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XPinMux configurationrr}r(jYjjZjubaubaubj/)r}r(jYX PRCM setuprjZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X PRCM setuprr}r(jYjjZjubaubaubj/)r}r(jYXRe-build board libraryrjZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XRe-build board libraryrr}r(jYjjZjubaubaubj/)r}r(jYX!Application software development jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYX Application software developmentrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X Application software developmentrr}r(jYjjZjubaubaubeubj)r}r(jYX**PinMux configuration**rjZjhjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XPinMux configurationrr}r(jYUjZjubajdjubaubj)r}r(jYXBThe default PinMux file has to be modified for GPIO2_19 pin usage:rjZjhjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK jqhjr]rj{XBThe default PinMux file has to be modified for GPIO2_19 pin usage:rr}r(jYjjZjubaubjC)r}r(jYUjZjhjbjjdj`jf}r(jGX•jk]jj]jh]ji]jn]ujpK"jqhjr]r(j/)r}r(jYXUse the PinMux Utility to open the default PinMux file pdk_am57xx_1_0_x\\packages\\ti\\board\\src\\idkAM572x\\idkAM572x_SR2.0.pinmux (for the latest Rev 1.3B EVM)rjZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK"jr]rj{XUse the PinMux Utility to open the default PinMux file pdk_am57xx_1_0_x\packages\ti\board\src\idkAM572x\idkAM572x_SR2.0.pinmux (for the latest Rev 1.3B EVM)rr}r(jYXUse the PinMux Utility to open the default PinMux file pdk_am57xx_1_0_x\\packages\\ti\\board\\src\\idkAM572x\\idkAM572x_SR2.0.pinmux (for the latest Rev 1.3B EVM)jZjubaubaubj/)r}r(jYXSelect GPIO, then MyGPIO2: jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXSelect GPIO, then MyGPIO2:rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK#jr]rj{XSelect GPIO, then MyGPIO2:rr}r(jYjjZjubaubaubeubjB)r}r(jYX'.. Image:: ../images/pinmux_gpio_1.png jZjhjbjjdjEjf}r(UuriX rtos/../images/pinmux_gpio_1.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpK&jqhjr]ubjC)r}r(jYUjZjhjbjjdj`jf}r(jGX•jk]jj]jh]ji]jn]ujpK'jqhjr]r(j/)r}r(jYXHThen, scroll down, set gpio2_19 with ball #T1, pull up and Rx direction.rjZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK'jr]rj{XHThen, scroll down, set gpio2_19 with ball #T1, pull up and Rx direction.rr}r(jYjjZjubaubaubj/)r}r(jYXqFinally, select Category filter as “SR2.0 – Platform Development Kit (PDK) and download the generated files. jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXpFinally, select Category filter as “SR2.0 – Platform Development Kit (PDK) and download the generated files.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK(jr]rj{XpFinally, select Category filter as “SR2.0 – Platform Development Kit (PDK) and download the generated files.rr}r(jYjjZjubaubaubeubjB)r}r(jYX'.. Image:: ../images/pinmux_gpio_2.png jZjhjbjjdjEjf}r(UuriX rtos/../images/pinmux_gpio_2.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpK+jqhjr]ubjC)r }r (jYUjZjhjbjjdj`jf}r (jGX•jk]jj]jh]ji]jn]ujpK,jqhjr]r j/)r }r(jYXFour new files should be generated, with the only difference being a new pin configuration added in boardPadDelayInit.c file: jZj jbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYX~Four new files should be generated, with the only difference being a new pin configuration added in boardPadDelayInit.c file:rjZj jbjjdjjf}r(jh]ji]jj]jk]jn]ujpK,jr]rj{X~Four new files should be generated, with the only difference being a new pin configuration added in boardPadDelayInit.c file:rr}r(jYjjZjubaubaubaubcdocutils.nodes literal_block r)r}r(jYXa /* GPIO2 - gpio2_19 on T1 - MyGPIO2 */ {0x14B4, 0x6000E, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},jZjhjbjjdU literal_blockrjf}r(UlinenosrUlanguagerXcjjjk]jj]jh]Uhighlight_argsr }ji]jn]ujpK.jqhjr]r!j{Xa /* GPIO2 - gpio2_19 on T1 - MyGPIO2 */ {0x14B4, 0x6000E, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},r"r#}r$(jYUjZjubaubjC)r%}r&(jYUjZjhjbjjdj`jf}r'(jGX•jk]jj]jh]ji]jn]ujpK3jqhjr]r(j/)r)}r*(jYXfReplace the same files under pdk_am57xx_1_0_x\\packages\\ti\\board\\src\\idkAM572x with the new ones. jZj%jbjjdj2jf}r+(jh]ji]jj]jk]jn]ujpNjqhjr]r,j)r-}r.(jYXeReplace the same files under pdk_am57xx_1_0_x\\packages\\ti\\board\\src\\idkAM572x with the new ones.jZj)jbjjdjjf}r/(jh]ji]jj]jk]jn]ujpK3jr]r0j{X`Replace the same files under pdk_am57xx_1_0_x\packages\ti\board\src\idkAM572x with the new ones.r1r2}r3(jYXeReplace the same files under pdk_am57xx_1_0_x\\packages\\ti\\board\\src\\idkAM572x with the new ones.jZj-ubaubaubaubj)r4}r5(jYX**PRCM setup**r6jZjhjbjjdjjf}r7(jh]ji]jj]jk]jn]ujpK5jqhjr]r8j)r9}r:(jYj6jf}r;(jh]ji]jj]jk]jn]ujZj4jr]r<j{X PRCM setupr=r>}r?(jYUjZj9ubajdjubaubj)r@}rA(jYXSetup of the Power, Reset and Clock Management (PRCM) domain for newly added GPIO2 is required. The application code calls Board_init() API with a BOARD_INIT_MODULE_CLOCK flag to enable the clock domain. It is implemented in the Board_moduleClockInit() function inside pdk_am57xx_1_0_x\\packages\\ti\\board\\source\\idkAM572x\\idkAM572x_clock.c. It is found that GPIO2 is enabled already and no further code needed.rBjZjhjbjjdjjf}rC(jh]ji]jj]jk]jn]ujpK7jqhjr]rDj{XSetup of the Power, Reset and Clock Management (PRCM) domain for newly added GPIO2 is required. The application code calls Board_init() API with a BOARD_INIT_MODULE_CLOCK flag to enable the clock domain. It is implemented in the Board_moduleClockInit() function inside pdk_am57xx_1_0_x\packages\ti\board\source\idkAM572x\idkAM572x_clock.c. It is found that GPIO2 is enabled already and no further code needed.rErF}rG(jYXSetup of the Power, Reset and Clock Management (PRCM) domain for newly added GPIO2 is required. The application code calls Board_init() API with a BOARD_INIT_MODULE_CLOCK flag to enable the clock domain. It is implemented in the Board_moduleClockInit() function inside pdk_am57xx_1_0_x\\packages\\ti\\board\\source\\idkAM572x\\idkAM572x_clock.c. It is found that GPIO2 is enabled already and no further code needed.jZj@ubaubj)rH}rI(jYX**Re-build board library**rJjZjhjbjjdjjf}rK(jh]ji]jj]jk]jn]ujpK9jqhjr]rLj)rM}rN(jYjJjf}rO(jh]ji]jj]jk]jn]ujZjHjr]rPj{XRe-build board libraryrQrR}rS(jYUjZjMubajdjubaubj)rT}rU(jYXbThe board library must be recompiled for the changes to take effect. This has several major steps:rVjZjhjbjjdjjf}rW(jh]ji]jj]jk]jn]ujpK;jqhjr]rXj{XbThe board library must be recompiled for the changes to take effect. This has several major steps:rYrZ}r[(jYjVjZjTubaubjC)r\}r](jYUjZjhjbjjdj`jf}r^(jGX•jk]jj]jh]ji]jn]ujpK=jqhjr]r_(j/)r`}ra(jYX6Setup the build environment by running setupenv scriptrbjZj\jbjjdj2jf}rc(jh]ji]jj]jk]jn]ujpNjqhjr]rdj)re}rf(jYjbjZj`jbjjdjjf}rg(jh]ji]jj]jk]jn]ujpK=jr]rhj{X6Setup the build environment by running setupenv scriptrirj}rk(jYjbjZjeubaubaubj/)rl}rm(jYXBuild the library with make command (e.g. “make board”) and the output will be under pdk_am57xx_1_0_x\\packages\\ti\\board\\lib\\idkAM572x\\a15\\release jZj\jbjjdj2jf}rn(jh]ji]jj]jk]jn]ujpNjqhjr]roj)rp}rq(jYXBuild the library with make command (e.g. “make board”) and the output will be under pdk_am57xx_1_0_x\\packages\\ti\\board\\lib\\idkAM572x\\a15\\releasejZjljbjjdjjf}rr(jh]ji]jj]jk]jn]ujpK>jr]rsj{XBuild the library with make command (e.g. “make board”) and the output will be under pdk_am57xx_1_0_x\packages\ti\board\lib\idkAM572x\a15\releasertru}rv(jYXBuild the library with make command (e.g. “make board”) and the output will be under pdk_am57xx_1_0_x\\packages\\ti\\board\\lib\\idkAM572x\\a15\\releasejZjpubaubaubeubeubj[)rw}rx(jYUjZjjbjjdjejf}ry(jh]ji]jj]jk]rzU application-software-developmentr{ajn]r|haujpKAjqhjr]r}(jt)r~}r(jYX Application software developmentrjZjwjbjjdjxjf}r(jh]ji]jj]jk]jn]ujpKAjqhjr]rj{X Application software developmentrr}r(jYjjZj~ubaubj)r}r(jYXThe GPIO LED blinking example (GPIO_LedBlink_idkAM572x_armTestProject) is used as the reference. The CCS project can be created by using pdkprojectcreate script, such as “pdkprojectcreate AM572x idkAM572x little gpio all arm”. Check `PDK Example and Test Project Creation `_ for details.rjZjwjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKBjqhjr]r(j{XThe GPIO LED blinking example (GPIO_LedBlink_idkAM572x_armTestProject) is used as the reference. The CCS project can be created by using pdkprojectcreate script, such as “pdkprojectcreate AM572x idkAM572x little gpio all arm”. Check rr}r(jYXThe GPIO LED blinking example (GPIO_LedBlink_idkAM572x_armTestProject) is used as the reference. The CCS project can be created by using pdkprojectcreate script, such as “pdkprojectcreate AM572x idkAM572x little gpio all arm”. Check jZjubj)r}r(jYX`PDK Example and Test Project Creation `_jf}r(UnameX%PDK Example and Test Project CreationjXkhttp://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_overview.html#rebuilding-componentsrjk]jj]jh]ji]jn]ujZjjr]rj{X%PDK Example and Test Project Creationrr}r(jYUjZjubajdjubcdocutils.nodes target r)r}r(jYXn jKjZjjdUtargetrjf}r(Urefurijjk]rU%pdk-example-and-test-project-creationrajj]jh]ji]jn]rh aujr]ubj{X for details.rr}r(jYX for details.jZjubeubj)r}r(jYXThis LED blink example uses 2 GPIO pins. The first pin is used to periodically generate an interrupt. The second pin is an output pin connected to an onboard LED, which toggles between low and high inside the interrupt ISR, thus driving the LED. Note the first pin doesn’t accept any external input, but using software to write a register (GPIO_IRQSTATUS_RAW_n) to generate interrupt.rjZjwjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKDjqhjr]rj{XThis LED blink example uses 2 GPIO pins. The first pin is used to periodically generate an interrupt. The second pin is an output pin connected to an onboard LED, which toggles between low and high inside the interrupt ISR, thus driving the LED. Note the first pin doesn’t accept any external input, but using software to write a register (GPIO_IRQSTATUS_RAW_n) to generate interrupt.rr}r(jYjjZjubaubj)r}r(jYX[Also note from GPIO_idkAM572x_board.c, the rising edge is configured to generate interrupt:rjZjwjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKFjqhjr]rj{X[Also note from GPIO_idkAM572x_board.c, the rising edge is configured to generate interrupt:rr}r(jYjjZjubaubj)r}r(jYXGPIO_PinConfig gpioPinConfigs_1p3[] = { /* Input pin with interrupt enabled */ GPIO_DEVICE_CONFIG(GPIO_GRN_LED_PORT_NUM_1P3, GPIO_GRN_LED_PIN_NUM_1P3) | GPIO_CFG_IN_INT_RISING | GPIO_CFG_INPUT, }jZjwjbjjdjjf}r(jjXcjjjk]jj]jh]j }ji]jn]ujpKHjqhjr]rj{XGPIO_PinConfig gpioPinConfigs_1p3[] = { /* Input pin with interrupt enabled */ GPIO_DEVICE_CONFIG(GPIO_GRN_LED_PORT_NUM_1P3, GPIO_GRN_LED_PIN_NUM_1P3) | GPIO_CFG_IN_INT_RISING | GPIO_CFG_INPUT, }rr}r(jYUjZjubaubj)r}r(jYXAfter understanding how the reference example works, the code can be modified to use the first pin to receive external input and trigger the interrupt, then the second pin works the same way to toggle the LED, visualizing the event input.rjZjwjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKPjqhjr]rj{XAfter understanding how the reference example works, the code can be modified to use the first pin to receive external input and trigger the interrupt, then the second pin works the same way to toggle the LED, visualizing the event input.rr}r(jYjjZjubaubj)r}r(jYX{Code modifications: • GPIO_board.h: this file defines the GPIO pins for the test, the first pin needs to be updatedrjZjwjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKRjqhjr]rj{X{Code modifications: • GPIO_board.h: this file defines the GPIO pins for the test, the first pin needs to be updatedrr}r(jYjjZjubaubj)r}r(jYXn#define GPIO_INTR_LED_BASE_ADDR_1P3 (CSL_MPU_GPIO2_REGS) #define GPIO_LED_PIN_NUM_1P3 (0x13U)jZjwjbjjdjjf}r(jjXcjjjk]jj]jh]j }ji]jn]ujpKUjqhjr]rj{Xn#define GPIO_INTR_LED_BASE_ADDR_1P3 (CSL_MPU_GPIO2_REGS) #define GPIO_LED_PIN_NUM_1P3 (0x13U)rr}r(jYUjZjubaubjC)r}r(jYUjZjwjbjjdj`jf}r(jGX•jk]jj]jh]ji]jn]ujpKZjqhjr]rj/)r}r(jYXmGPIO_idkAM572x_board.c: this file also defines the GPIO pins for the test, the first pin needs to be updated jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXlGPIO_idkAM572x_board.c: this file also defines the GPIO pins for the test, the first pin needs to be updatedrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKZjr]rj{XlGPIO_idkAM572x_board.c: this file also defines the GPIO pins for the test, the first pin needs to be updatedrr}r(jYjjZjubaubaubaubj)r}r(jYX/* GPIO Definitions specific Rev1p3 Board */ /* GPIO pin number connected to the green LED */ #define GPIO_GRN_LED_PIN_NUM_1P3 (0x13) /* GPIO port number connected to the green LED */ #define GPIO_GRN_LED_PORT_NUM_1P3 (0x02)jZjwjbjjdjjf}r(jjXcjjjk]jj]jh]j }ji]jn]ujpK\jqhjr]rj{X/* GPIO Definitions specific Rev1p3 Board */ /* GPIO pin number connected to the green LED */ #define GPIO_GRN_LED_PIN_NUM_1P3 (0x13) /* GPIO port number connected to the green LED */ #define GPIO_GRN_LED_PORT_NUM_1P3 (0x02)rr}r(jYUjZjubaubjC)r}r(jYUjZjwjbjjdj`jf}r(jGX•jk]jj]jh]ji]jn]ujpKejqhjr]rj/)r}r(jYXzmain_led_blink.c: this is the main test program. The change is high-lighted in black, while the original code is in grey. jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXymain_led_blink.c: this is the main test program. The change is high-lighted in black, while the original code is in grey.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKejr]rj{Xymain_led_blink.c: this is the main test program. The change is high-lighted in black, while the original code is in grey.rr}r(jYjjZjubaubaubaubj%)r}r(jYUjZjwjbjjdj(jf}r(j*U)jk]jj]jh]j+Uji]jn]j,j-ujpKgjqhjr]rj/)r}r(jYX Inside void gpio_test(UArg arg0, UArg arg1) routine there is a while(1) loop that continuously triggers the interrupt by software write. Since the new example relies on the external input event to trigger it, one can simply add another while(1) in front of it to block the original loop: jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXInside void gpio_test(UArg arg0, UArg arg1) routine there is a while(1) loop that continuously triggers the interrupt by software write. Since the new example relies on the external input event to trigger it, one can simply add another while(1) in front of it to block the original loop:rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKgjr]rj{XInside void gpio_test(UArg arg0, UArg arg1) routine there is a while(1) loop that continuously triggers the interrupt by software write. Since the new example relies on the external input event to trigger it, one can simply add another while(1) in front of it to block the original loop:rr}r(jYjjZjubaubaubaubj)r}r(jYXwhile(1); //New added loop while(1) { if defined(SOC_AM574x) || defined(SOC_AM572x) || defined(SOC_AM571x)|| defined(SOC_AM335x) || defined(SOC_AM437x) #if defined (idkAM572x) || defined (idkAM574x) …. }jZjwjbjjdjjf}r(jjXcjjjk]jj]jh]j }ji]jn]ujpKijqhjr]r j{Xwhile(1); //New added loop while(1) { if defined(SOC_AM574x) || defined(SOC_AM572x) || defined(SOC_AM571x)|| defined(SOC_AM335x) || defined(SOC_AM437x) #if defined (idkAM572x) || defined (idkAM574x) …. }r r }r (jYUjZjubaubj%)r }r(jYUjZjwjbjjdj(jf}r(j*U)jdKjk]jj]jh]j+Uji]jn]j,j-ujpKsjqhjr]rj/)r}r(jYXxAlso inside the same void gpio_test(UArg arg0, UArg arg1) routine, one may add a debounce control before the test loop: jZj jbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXwAlso inside the same void gpio_test(UArg arg0, UArg arg1) routine, one may add a debounce control before the test loop:rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKsjr]rj{XwAlso inside the same void gpio_test(UArg arg0, UArg arg1) routine, one may add a debounce control before the test loop:rr}r(jYjjZjubaubaubaubj)r}r(jYXM/* Write high to gpio pin to control LED1 */ GPIO_write((USER_LED1), GPIO_PIN_VAL_HIGH); /* Add new debounce code here */ GPIOAppUpdateConfig(&gpioBaseAddr, &gpioPin); GPIODebounceFuncControl(gpioBaseAddr, gpioPin, 1); GPIODebounceTimeConfig(gpioBaseAddr, 255); AppDelay(DELAY_VALUE); GPIO_log("\n GPIO Led Blink Application \n");jZjwjbjjdjjf}r(jjXcjjjk]jj]jh]j }ji]jn]ujpKujqhjr]r j{XM/* Write high to gpio pin to control LED1 */ GPIO_write((USER_LED1), GPIO_PIN_VAL_HIGH); /* Add new debounce code here */ GPIOAppUpdateConfig(&gpioBaseAddr, &gpioPin); GPIODebounceFuncControl(gpioBaseAddr, gpioPin, 1); GPIODebounceTimeConfig(gpioBaseAddr, 255); AppDelay(DELAY_VALUE); GPIO_log("\n GPIO Led Blink Application \n");r!r"}r#(jYUjZjubaubj)r$}r%(jYX{After all the code changes, rebuild the test application. A GPIO_LedBlink_idkAM572x_armTestProject.out should be generated.r&jZjwjbjjdjjf}r'(jh]ji]jj]jk]jn]ujpKjqhjr]r(j{X{After all the code changes, rebuild the test application. A GPIO_LedBlink_idkAM572x_armTestProject.out should be generated.r)r*}r+(jYj&jZj$ubaubeubj[)r,}r-(jYUjZjjbjjdjejf}r.(jh]ji]jj]jk]r/Utestr0ajn]r1j"aujpKjqhjr]r2(jt)r3}r4(jYXTestr5jZj,jbjjdjxjf}r6(jh]ji]jj]jk]jn]ujpKjqhjr]r7j{XTestr8r9}r:(jYj5jZj3ubaubj)r;}r<(jYXE**Test Setup** The test setup using AM572x IDK EVM is depicted below:jZj,jbjjdjjf}r=(jh]ji]jj]jk]jn]ujpKjqhjr]r>(j)r?}r@(jYX**Test Setup**jf}rA(jh]ji]jj]jk]jn]ujZj;jr]rBj{X Test SetuprCrD}rE(jYUjZj?ubajdjubj{X7 The test setup using AM572x IDK EVM is depicted below:rFrG}rH(jYX7 The test setup using AM572x IDK EVM is depicted below:jZj;ubeubjB)rI}rJ(jYX#.. Image:: ../images/gpio_test.png jZj,jbjjdjEjf}rK(UuriXrtos/../images/gpio_test.pngrLjk]jj]jh]ji]jH}rMU*jLsjn]ujpKjqhjr]ubjC)rN}rO(jYUjZj,jbjjdj`jf}rP(jGX•jk]jj]jh]ji]jn]ujpKjqhjr]rQ(j/)rR}rS(jYX*The EVM is powered with a +5V power supplyrTjZjNjbjjdj2jf}rU(jh]ji]jj]jk]jn]ujpNjqhjr]rVj)rW}rX(jYjTjZjRjbjjdjjf}rY(jh]ji]jj]jk]jn]ujpKjr]rZj{X*The EVM is powered with a +5V power supplyr[r\}r](jYjTjZjWubaubaubj/)r^}r_(jYXeA micro USB cable is connected to the host PC for on-board XDS100v2 JTAG connection and UART console.r`jZjNjbjjdj2jf}ra(jh]ji]jj]jk]jn]ujpNjqhjr]rbj)rc}rd(jYj`jZj^jbjjdjjf}re(jh]ji]jj]jk]jn]ujpKjr]rfj{XeA micro USB cable is connected to the host PC for on-board XDS100v2 JTAG connection and UART console.rgrh}ri(jYj`jZjcubaubaubj/)rj}rk(jYX,A wire is connected to J21 pin4 as the event input. Another wire is connected to J21 pin 60 as the digital ground. When the two wires touch each other, pin 4 goes low, creating a GPIO falling edge. On the other hand, when the two wires are not touching, pin 4 goes high, creating a GPIO rising edge. jZjNjbjjdj2jf}rl(jh]ji]jj]jk]jn]ujpNjqhjr]rmj)rn}ro(jYX+A wire is connected to J21 pin4 as the event input. Another wire is connected to J21 pin 60 as the digital ground. When the two wires touch each other, pin 4 goes low, creating a GPIO falling edge. On the other hand, when the two wires are not touching, pin 4 goes high, creating a GPIO rising edge.rpjZjjjbjjdjjf}rq(jh]ji]jj]jk]jn]ujpKjr]rrj{X+A wire is connected to J21 pin4 as the event input. Another wire is connected to J21 pin 60 as the digital ground. When the two wires touch each other, pin 4 goes low, creating a GPIO falling edge. On the other hand, when the two wires are not touching, pin 4 goes high, creating a GPIO rising edge.rsrt}ru(jYjpjZjnubaubaubeubj)rv}rw(jYX**Test Procedure**rxjZj,jbjjdjjf}ry(jh]ji]jj]jk]jn]ujpKjqhjr]rzj)r{}r|(jYjxjf}r}(jh]ji]jj]jk]jn]ujZjvjr]r~j{XTest Procedurerr}r(jYUjZj{ubajdjubaubjC)r}r(jYUjZj,jbjjdj`jf}r(jGX•jk]jj]jh]ji]jn]ujpKjqhjr]r(j/)r}r(jYX]Connect to the A15_0 with a JTAG emulator and use the default GEL file to initialize the SOC.rjZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X]Connect to the A15_0 with a JTAG emulator and use the default GEL file to initialize the SOC.rr}r(jYjjZjubaubaubj/)r}r(jYXOLoad the test application (GPIO_LedBlink_idkAM572x_armTestProject.out) and run.rjZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XOLoad the test application (GPIO_LedBlink_idkAM572x_armTestProject.out) and run.rr}r(jYjjZjubaubaubj/)r}r(jYXvTouch the two wires, then un-touch, the LED should flip the status and keep steady until next touch, un-touch cycle. jZjjbXfinternal padding after source/rtos/How_to_Guides/Target/External_Input_Trigger_Interrupt_AM57x.rst.incrjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXtTouch the two wires, then un-touch, the LED should flip the status and keep steady until next touch, un-touch cycle.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XtTouch the two wires, then un-touch, the LED should flip the status and keep steady until next touch, un-touch cycle.rr}r(jYjjZjubaubaubeubeubeubj[)r}r(jYUjZj`jbjcjdjejf}r(jh]ji]jj]jk]rU%run-applications-from-ddr-on-r5-coresrajn]rj9aujpKjqhjr]r(jt)r}r(jYX%Run applications from DDR on R5 coresrjZjjbjcjdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X%Run applications from DDR on R5 coresrr}r(jYjjZjubaubj)r}r(jYX".. _run-apps-from-ddr-on-r5-cores:jZjjbjX<source/rtos/How_to_Guides/Target/Run_apps_from_DDR_on_R5.rstrr}rbjdjjf}r(jk]jj]jh]ji]jn]jUrun-apps-from-ddr-on-r5-coresrujpMjqhjr]ubj)r}r(jYXOnce the R5 core is out of reset, the R5 defaults to no execute permissions for the DDR memory space. The side effect of this is, that all code, from entry point till the code that sets up the MPU (Memory Protection Unit), has to be run from internal memory.rjZjjbjUexpect_referenced_by_namer}rhjsjdjjf}r(jh]ji]jj]jk]rjajn]rhaujpKjqhUexpect_referenced_by_idr}rjjsjr]rj{XOnce the R5 core is out of reset, the R5 defaults to no execute permissions for the DDR memory space. The side effect of this is, that all code, from entry point till the code that sets up the MPU (Memory Protection Unit), has to be run from internal memory.rr}r(jYjjZjubaubj)r}r(jYX .. _run-bios-app-from-ddr-on-r5:jZjjbjjdjjf}r(jk]jj]jh]ji]jn]jUrun-bios-app-from-ddr-on-r5rujpMjqhjr]ubj[)r}r(jYUjZjjbjj}rjjsjdjejf}r(jh]ji]jj]jk]r(U$run-bios-applications-from-ddr-on-r5rjejn]r(hjeujpK jqhj}rjjsjr]r(jt)r}r(jYX$Run BIOS Applications from DDR on R5rjZjjbjjdjxjf}r(jh]ji]jj]jk]jn]ujpK jqhjr]rj{X$Run BIOS Applications from DDR on R5rr}r(jYjjZjubaubj)r}r(jYXIn BIOS, the application sets up the MPU as per the memory configuration specified in the *.xs file (that is referred to in the applications bios config file). Once the MPU is setup by the app, the rest of the code can run from DDR.jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK jqhjr]r(j{XZIn BIOS, the application sets up the MPU as per the memory configuration specified in the rr}r(jYXZIn BIOS, the application sets up the MPU as per the memory configuration specified in the jZjubcdocutils.nodes problematic r)r}r(jYX*jf}r(jk]rUid3rajj]jh]ji]jn]UrefidUid2rujZjjr]rj{X*r}r(jYUjZjubajdU problematicrubj{X.xs file (that is referred to in the applications bios config file). Once the MPU is setup by the app, the rest of the code can run from DDR.rr}r(jYX.xs file (that is referred to in the applications bios config file). Once the MPU is setup by the app, the rest of the code can run from DDR.jZjubeubj)r}r(jYXTo ensure that all code from entry point to MPU setup is run from internal memory, the text sections of the following libs must be placed in internal memory using the application's linker command file.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XTo ensure that all code from entry point to MPU setup is run from internal memory, the text sections of the following libs must be placed in internal memory using the application's linker command file.rr}r(jYjjZjubaubjC)r}r(jYUjZjjbjjdj`jf}r(jGX*jk]jj]jh]ji]jn]ujpKjqhjr]r(j/)r}r(jYX*sysbios.aer5f(.text) jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r }r (jYX*sysbios.aer5f(.text)jZjjbjjdjjf}r (jh]ji]jj]jk]jn]ujpKjr]r (j)r }r(jYX*jf}r(jk]rUid5rajj]jh]ji]jn]UrefidUid4rujZj jr]rj{X*r}r(jYUjZj ubajdjubj{Xsysbios.aer5f(.text)rr}r(jYXsysbios.aer5f(.text)jZj ubeubaubj/)r}r(jYX*boot.aer5f(.text) jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYX*boot.aer5f(.text)jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]r (j)r!}r"(jYX*jf}r#(jk]r$Uid7r%ajj]jh]ji]jn]UrefidUid6r&ujZjjr]r'j{X*r(}r)(jYUjZj!ubajdjubj{Xboot.aer5f(.text)r*r+}r,(jYXboot.aer5f(.text)jZjubeubaubj/)r-}r.(jYX*auto_init.aer5f(.text) jZjjbjjdj2jf}r/(jh]ji]jj]jk]jn]ujpNjqhjr]r0j)r1}r2(jYX*auto_init.aer5f(.text)jZj-jbjjdjjf}r3(jh]ji]jj]jk]jn]ujpKjr]r4(j)r5}r6(jYX*jf}r7(jk]r8Uid9r9ajj]jh]ji]jn]UrefidUid8r:ujZj1jr]r;j{X*r<}r=(jYUjZj5ubajdjubj{Xauto_init.aer5f(.text)r>r?}r@(jYXauto_init.aer5f(.text)jZj1ubeubaubj/)rA}rB(jYX*_per5f.oer5f(.text) jZjjbjjdj2jf}rC(jh]ji]jj]jk]jn]ujpNjqhjr]rDj)rE}rF(jYX*_per5f.oer5f(.text)jZjAjbjjdjjf}rG(jh]ji]jj]jk]jn]ujpKjr]rH(j)rI}rJ(jYX*jf}rK(jk]rLUid11rMajj]jh]ji]jn]UrefidUid10rNujZjEjr]rOj{X*rP}rQ(jYUjZjIubajdjubj{X_per5f.oer5f(.text)rRrS}rT(jYX_per5f.oer5f(.text)jZjEubeubaubeubj)rU}rV(jYXRefer `emac_linker_r5.lds `__ for an example.jZjjbjjdjjf}rW(jh]ji]jj]jk]jn]ujpKjqhjr]rX(j{XRefer rYrZ}r[(jYXRefer jZjUubj)r\}r](jYX`emac_linker_r5.lds `__jf}r^(UnameXemac_linker_r5.ldsjXfhttps://git.ti.com/keystone-rtos/emac-lld/blobs/master/test/EmacLoopbackTest/am65xx/emac_linker_r5.ldsjk]jj]jh]ji]jn]ujZjUjr]r_j{Xemac_linker_r5.ldsr`ra}rb(jYUjZj\ubajdjubj{X for an example.rcrd}re(jYX for an example.jZjUubeubj)rf}rg(jYXPlease note that you need to replace *_per5f.oer5f with the corresponding file for your application. For eg, if the application's .cfg file is emacUnitTest_r5.cfg, then the .oer5f file will be named emacUnitTest_r5_per5f.oer5fjZjjbjjdjjf}rh(jh]ji]jj]jk]jn]ujpNjqhjr]rij)rj}rk(jYXPlease note that you need to replace *_per5f.oer5f with the corresponding file for your application. For eg, if the application's .cfg file is emacUnitTest_r5.cfg, then the .oer5f file will be named emacUnitTest_r5_per5f.oer5fjZjfjbjjdjjf}rl(jh]ji]jj]jk]jn]ujpK jr]rm(j{X%Please note that you need to replace rnro}rp(jYX%Please note that you need to replace jZjjubj)rq}rr(jYX*jf}rs(jk]rtUid13ruajj]jh]ji]jn]UrefidUid12rvujZjjjr]rwj{X*rx}ry(jYUjZjqubajdjubj{X_per5f.oer5f with the corresponding file for your application. For eg, if the application's .cfg file is emacUnitTest_r5.cfg, then the .oer5f file will be named emacUnitTest_r5_per5f.oer5frzr{}r|(jYX_per5f.oer5f with the corresponding file for your application. For eg, if the application's .cfg file is emacUnitTest_r5.cfg, then the .oer5f file will be named emacUnitTest_r5_per5f.oer5fjZjjubeubaubj)r}}r~(jYXYou also need to update the *.xs file referred to by the applications .cfg file to make sure that the DDR has execute privileges. Please refer `r5_mpu.xs `__ for an example memory configuration. You could also make the applications .cfg file refer to the common .xs file, as shown in the example `emacUnitTest_r5.cfg `__.jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK%jqhjr]r(j{XYou also need to update the rr}r(jYXYou also need to update the jZj}ubj)r}r(jYX*jf}r(jk]rUid15rajj]jh]ji]jn]UrefidUid14rujZj}jr]rj{X*r}r(jYUjZjubajdjubj{Xr.xs file referred to by the applications .cfg file to make sure that the DDR has execute privileges. Please refer rr}r(jYXr.xs file referred to by the applications .cfg file to make sure that the DDR has execute privileges. Please refer jZj}ubj)r}r(jYXa`r5_mpu.xs `__jf}r(UnameX r5_mpu.xsjXQhttp://git.ti.com/keystone-rtos/processor-pdk-build/blobs/master/am65xx/r5_mpu.xsjk]jj]jh]ji]jn]ujZj}jr]rj{X r5_mpu.xsrr}r(jYUjZjubajdjubj{X for an example memory configuration. You could also make the applications .cfg file refer to the common .xs file, as shown in the example rr}r(jYX for an example memory configuration. You could also make the applications .cfg file refer to the common .xs file, as shown in the example jZj}ubj)r}r(jYX`emacUnitTest_r5.cfg `__jf}r(UnameXemacUnitTest_r5.cfgjXghttps://git.ti.com/keystone-rtos/emac-lld/blobs/master/test/EmacLoopbackTest/am65xx/emacUnitTest_r5.cfgjk]jj]jh]ji]jn]ujZj}jr]rj{XemacUnitTest_r5.cfgrr}r(jYUjZjubajdjubj{X.r}r(jYX.jZj}ubeubcdocutils.nodes warning r)r}r(jYXOnce you update the .xs file, please note remember to delete *_per5f.oer5f from the applications *configuro directory, so that it is autogenerated again. If you simply do a clean build, *_per5f.oer5f will not be updated to reflect the changes in the *.xs file.jZjjbjjdUwarningrjf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXOnce you update the .xs file, please note remember to delete *_per5f.oer5f from the applications *configuro directory, so that it is autogenerated again. If you simply do a clean build, *_per5f.oer5f will not be updated to reflect the changes in the *.xs file.jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK+jr]r(j{X=Once you update the .xs file, please note remember to delete rr}r(jYX=Once you update the .xs file, please note remember to delete jZjubj)r}r(jYX*jf}r(jk]rUid17rajj]jh]ji]jn]UrefidUid16rujZjjr]rj{X*r}r(jYUjZjubajdjubj{X(_per5f.oer5f from the applications rr}r(jYX(_per5f.oer5f from the applications jZjubj)r}r(jYX*jf}r(jk]rUid19rajj]jh]ji]jn]UrefidUid18rujZjjr]rj{X*r}r(jYUjZjubajdjubj{XXconfiguro directory, so that it is autogenerated again. If you simply do a clean build, rr}r(jYXXconfiguro directory, so that it is autogenerated again. If you simply do a clean build, jZjubj)r}r(jYX*jf}r(jk]rUid21rajj]jh]ji]jn]UrefidUid20rujZjjr]rj{X*r}r(jYUjZjubajdjubj{XD_per5f.oer5f will not be updated to reflect the changes in the rr}r(jYXD_per5f.oer5f will not be updated to reflect the changes in the jZjubj)r}r(jYX*jf}r(jk]rUid23rajj]jh]ji]jn]UrefidUid22rujZjjr]rj{X*r}r(jYUjZjubajdjubj{X .xs file.rr}r(jYX .xs file.jZjubeubaubj)r}r(jYX%.. _run-baremetal-app-from-ddr-on-r5:jZjjbjjdjjf}r(jk]jj]jh]ji]jn]jU run-baremetal-app-from-ddr-on-r5rujpMjqhjr]ubeubj[)r}r(jYUjZjjbjj}rh{jsjdjejf}r(jh]ji]jj]jk]r(U)run-baremetal-applications-from-ddr-on-r5rjejn]r(hrh{eujpK5jqhj}rjjsjr]r(jt)r}r(jYX)Run Baremetal Applications from DDR on R5rjZjjbjjdjxjf}r(jh]ji]jj]jk]jn]ujpK5jqhjr]rj{X)Run Baremetal Applications from DDR on R5rr}r(jYjjZjubaubj)r}r(jYXiBaremetal applications have similar restrictions on running code from internal memory till the MPU is configured, just like BIOS applications. For best comaptibility, however, make sure that the entry point is always the reset vector, and that the code that sets up the DDR access permissions in the MPU resides completely within 0x100 bytes of the entry point.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK7jqhjr]rj{XiBaremetal applications have similar restrictions on running code from internal memory till the MPU is configured, just like BIOS applications. For best comaptibility, however, make sure that the entry point is always the reset vector, and that the code that sets up the DDR access permissions in the MPU resides completely within 0x100 bytes of the entry point.rr}r(jYjjZjubaubj)r}r(jYXFor applications that find the default R5 configuration setup by the CSL sufficient, there is another method that can be used to execute an application from DDR. If the bootloader (SBL) is re-built using the SBL_SKIP_MCU_RESET compile option (by enabling the corresponding line in `sbl_component.mk `__, then SBL will branch to the application entry point without resetting the R5 core.jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK>jqhjr]r(j{XFor applications that find the default R5 configuration setup by the CSL sufficient, there is another method that can be used to execute an application from DDR. If the bootloader (SBL) is re-built using the SBL_SKIP_MCU_RESET compile option (by enabling the corresponding line in rr}r(jYXFor applications that find the default R5 configuration setup by the CSL sufficient, there is another method that can be used to execute an application from DDR. If the bootloader (SBL) is re-built using the SBL_SKIP_MCU_RESET compile option (by enabling the corresponding line in jZjubj)r}r(jYXa`sbl_component.mk `__jf}r(UnameXsbl_component.mkjXJhttps://git.ti.com/keystone-rtos/sbl/blobs/master/sbl_component.mk#line399jk]jj]jh]ji]jn]ujZjjr]rj{Xsbl_component.mkrr }r (jYUjZjubajdjubj{XT, then SBL will branch to the application entry point without resetting the R5 core.r r }r (jYXT, then SBL will branch to the application entry point without resetting the R5 core.jZjubeubj)r}r(jYX)In this scenario, as the R5 core was already setup when the SBL invoked CSL init, the app can execute directly from DDR, right from its entry point. However, the app must take care not to redo the R5 initialization using CSL init, as the CSL initialization code assumes that the R5 registers are at their reset default values. This can be done by simply defining an empty __mpu_init function in the baremetal application. Refer `sbl_smp_r5.asm `__ for an example.jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKEjqhjr]r(j{XIn this scenario, as the R5 core was already setup when the SBL invoked CSL init, the app can execute directly from DDR, right from its entry point. However, the app must take care not to redo the R5 initialization using CSL init, as the CSL initialization code assumes that the R5 registers are at their reset default values. This can be done by simply defining an empty __mpu_init function in the baremetal application. Refer rr}r(jYXIn this scenario, as the R5 core was already setup when the SBL invoked CSL init, the app can execute directly from DDR, right from its entry point. However, the app must take care not to redo the R5 initialization using CSL init, as the CSL initialization code assumes that the R5 registers are at their reset default values. This can be done by simply defining an empty __mpu_init function in the baremetal application. Refer jZjubj)r}r(jYXl`sbl_smp_r5.asm `__jf}r(UnameXsbl_smp_r5.asmjXWhttps://git.ti.com/keystone-rtos/sbl/blobs/master/example/k3MulticoreApp/sbl_smp_r5.asmjk]jj]jh]ji]jn]ujZjjr]rj{Xsbl_smp_r5.asmrr}r(jYUjZjubajdjubj{X for an example.rr}r(jYX for an example.jZjubeubeubeubeubjbjcjdjejf}r(jh]ji]jj]jk]r Urun-ipc-examples-on-am572xr!ajn]r"haujpKjqhjr]r#(jt)r$}r%(jYXRun IPC Examples on AM572xr&jZj^jbjcjdjxjf}r'(jh]ji]jj]jk]jn]ujpKjqhjr]r(j{XRun IPC Examples on AM572xr)r*}r+(jYj&jZj$ubaubj)r,}r-(jYXMhttp://processors.wiki.ti.com/index.php/Running_IPC_Examples_on_DRA7xx/AM572xjZj^jbjXCsource/rtos/How_to_Guides/Target/Run_IPC_Examples_on_AM572x.rst.incr.r/}r0bjdjjf}r1(jjjk]jj]jh]ji]jn]ujpKjqhjr]r2j{XMhttp://processors.wiki.ti.com/index.php/Running_IPC_Examples_on_DRA7xx/AM572xr3r4}r5(jYUjZj,ubaubj\eubjbj/jdjejf}r6(jh]ji]jj]jk]r7Udra7xx-am572xx-ipc-examplesr8ajn]r9haujpKjqhjr]r:(jt)r;}r<(jYXDRA7xx/AM572xx IPC Examplesr=jZj\jbj/jdjxjf}r>(jh]ji]jj]jk]jn]ujpKjqhjr]r?j{XDRA7xx/AM572xx IPC Examplesr@rA}rB(jYj=jZj;ubaubj)rC}rD(jYXIPC Hello Example:rEjZj\jbj/jdjjf}rF(jk]rGUipc-hello-examplerHajj]jh]ji]jn]rIhTaujpNjqhjr]rJj{XIPC Hello Example:rKrL}rM(jYjEjZjCubaubj)rN}rO(jYX**ex01_hello**rPjZj\jbj/jdjjf}rQ(jh]ji]jj]jk]jn]ujpK jqhjr]rRj)rS}rT(jYjPjf}rU(jh]ji]jj]jk]jn]ujZjNjr]rVj{X ex01_hellorWrX}rY(jYUjZjSubajdjubaubcdocutils.nodes line_block rZ)r[}r\(jYUjZj\jbj/jdU line_blockr]jf}r^(jh]ji]jj]jk]jn]ujpK jqhjr]r_cdocutils.nodes line r`)ra}rb(jYUUindentrcKjZj[jbj/jdjpjf}rd(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)re}rf(jYXThe following examples demonstrate some of the rudimentary IPC capabilities. They are mostly two processors examples. These examples may be built for any two processors on your device, but only for two at a time. An IPC Ping example using three processors is also presented at the end.rgjZj\jbj/jdjjf}rh(jh]ji]jj]jk]jn]ujpK jqhjr]rij{XThe following examples demonstrate some of the rudimentary IPC capabilities. They are mostly two processors examples. These examples may be built for any two processors on your device, but only for two at a time. An IPC Ping example using three processors is also presented at the end.rjrk}rl(jYjgjZjeubaubj)rm}rn(jYXHello example uses the reader/writer design pattern. One processor will be the reader and the other will be the writer. The reader creates a message queue and waits on it for messages. The writer opens the reader's message queue and sends messages to it. The writer allocates the message from a shared message pool and the reader returns the message to the pool. Thus, messages are sent in only one direction. Default settings of the Hello world example configures DSP1 as the writer and DSP2 as the reader.rojZj\jbj/jdjjf}rp(jh]ji]jj]jk]jn]ujpKjqhjr]rqj{XHello example uses the reader/writer design pattern. One processor will be the reader and the other will be the writer. The reader creates a message queue and waits on it for messages. The writer opens the reader's message queue and sends messages to it. The writer allocates the message from a shared message pool and the reader returns the message to the pool. Thus, messages are sent in only one direction. Default settings of the Hello world example configures DSP1 as the writer and DSP2 as the reader.rrrs}rt(jYjojZjmubaubj)ru}rv(jYXif Windows 7 machine is used for building these examples, **GnuWin32** make utility needs to be installed to run make which can be downloaded from this link `http://gnuwin32.sourceforge.net/packages/make.htm `__jZj\jbj/jdjjf}rw(jh]ji]jj]jk]jn]ujpNjqhjr]rxj)ry}rz(jYXif Windows 7 machine is used for building these examples, **GnuWin32** make utility needs to be installed to run make which can be downloaded from this link `http://gnuwin32.sourceforge.net/packages/make.htm `__jZjujbj/jdjjf}r{(jh]ji]jj]jk]jn]ujpKjr]r|(j{X:if Windows 7 machine is used for building these examples, r}r~}r(jYX:if Windows 7 machine is used for building these examples, jZjyubj)r}r(jYX **GnuWin32**jf}r(jh]ji]jj]jk]jn]ujZjyjr]rj{XGnuWin32rr}r(jYUjZjubajdjubj{XW make utility needs to be installed to run make which can be downloaded from this link rr}r(jYXW make utility needs to be installed to run make which can be downloaded from this link jZjyubj)r}r(jYXi`http://gnuwin32.sourceforge.net/packages/make.htm `__jf}r(UnameX1http://gnuwin32.sourceforge.net/packages/make.htmjX1http://gnuwin32.sourceforge.net/packages/make.htmjk]jj]jh]ji]jn]ujZjyjr]rj{X1http://gnuwin32.sourceforge.net/packages/make.htmrr}r(jYUjZjubajdjubeubaubj)r}r(jYXSet **GnuWin32\\bin** folder on file path and add a system variable **XDCTOOLS_JAVA_HOME** to point to "**c:\\ti\\ccsv6\\eclipse\\jre**"jZj\jbj/jdjjf}r(jh]ji]jj]jk]jn]ujpK#jqhjr]r(j{XSet rr}r(jYXSet jZjubj)r}r(jYX**GnuWin32\\bin**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X GnuWin32\binrr}r(jYUjZjubajdjubj{X/ folder on file path and add a system variable rr}r(jYX/ folder on file path and add a system variable jZjubj)r}r(jYX**XDCTOOLS_JAVA_HOME**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XXDCTOOLS_JAVA_HOMErr}r(jYUjZjubajdjubj{X to point to "rr}r(jYX to point to "jZjubj)r}r(jYX**c:\\ti\\ccsv6\\eclipse\\jre**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{Xc:\ti\ccsv6\eclipse\jrerr}r(jYUjZjubajdjubj{X"r}r(jYX"jZjubeubj)r}r(jYXbset PATH=\GnuWin32\bin;%PATH% set XDCTOOLS_JAVA_HOME=c:\ti\ccsv6\eclipse\jrejZj\jbj/jdjjf}r(jjjk]jj]jh]ji]jn]ujpK1jqhjr]rj{Xbset PATH=\GnuWin32\bin;%PATH% set XDCTOOLS_JAVA_HOME=c:\ti\ccsv6\eclipse\jrerr}r(jYUjZjubaubj)r}r(jYXn1. Change to the example folder by entering: cd ~/ti/ipc_nn_nn_nn_nn/examples/DRA7xx_bios_elf/\ **ex01_hello**jZj\jbj/jdjjf}r(jh]ji]jj]jk]jn]ujpK+jqhjr]r(j{X^1. Change to the example folder by entering: cd ~/ti/ipc_nn_nn_nn_nn/examples/DRA7xx_bios_elf/rr}r(jYX`1. Change to the example folder by entering: cd ~/ti/ipc_nn_nn_nn_nn/examples/DRA7xx_bios_elf/\ jZjubj)r}r(jYX**ex01_hello**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X ex01_hellorr}r(jYUjZjubajdjubeubj)r}r(jYX2. Open readme.txt file and follow build instructions step-by-step. If build this example on Ubuntu PC, make sure there is no spaces between variable name and its value.rjZj\jbj/jdjjf}r(jh]ji]jj]jk]jn]ujpK.jqhjr]rj{X2. Open readme.txt file and follow build instructions step-by-step. If build this example on Ubuntu PC, make sure there is no spaces between variable name and its value.rr}r(jYjjZjubaubjZ)r}r(jYUjZj\jbj/jdj]jf}r(jh]ji]jj]jk]jn]ujpK2jqhjr]rj`)r}r(jYUjcKjZjjbj/jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r}r(jYXDDEPOT (your depository folder ex: DEPOT=/Your_Ubuntu_home_folder/ti)jZj\jbj/jdjjf}r(jjjk]jj]jh]ji]jn]ujpK?jqhjr]rj{XDDEPOT (your depository folder ex: DEPOT=/Your_Ubuntu_home_folder/ti)rr}r(jYUjZjubaubj)r}r(jYX)BIOS_INSTALL_DIR=$(DEPOT)/bios_n_nn_nn_nnjZj\jbj/jdjjf}r(jjjk]jj]jh]ji]jn]ujpKCjqhjr]rj{X)BIOS_INSTALL_DIR=$(DEPOT)/bios_n_nn_nn_nnrr}r(jYUjZjubaubj)r}r(jYX'IPC_INSTALL_DIR=$(DEPOT)/ipc_n_nn_nn_nnjZj\jbj/jdjjf}r(jjjk]jj]jh]ji]jn]ujpKGjqhjr]rj{X'IPC_INSTALL_DIR=$(DEPOT)/ipc_n_nn_nn_nnrr}r(jYUjZjubaubj)r}r(jYX,XDC_INSTALL_DIR=$(DEPOT)/xdctools_n_nn_nn_nnjZj\jbj/jdjjf}r(jjjk]jj]jh]ji]jn]ujpKKjqhjr]rj{X,XDC_INSTALL_DIR=$(DEPOT)/xdctools_n_nn_nn_nnrr}r(jYUjZjubaubj)r}r(jYXOgnu.targets.arm.A15F=$(DEPOT)/ccsv6/tools/compiler/gcc-arm-none-eabi-4_8-2014q3jZj\jbj/jdjjf}r(jjjk]jj]jh]ji]jn]ujpKOjqhjr]rj{XOgnu.targets.arm.A15F=$(DEPOT)/ccsv6/tools/compiler/gcc-arm-none-eabi-4_8-2014q3rr}r(jYUjZjubaubj)r}r(jYX=ti.targets.elf.C66=$(DEPOT)/ccsv6/tools/compiler/c6000_7.4.14jZj\jbj/jdjjf}r(jjjk]jj]jh]ji]jn]ujpKSjqhjr]rj{X=ti.targets.elf.C66=$(DEPOT)/ccsv6/tools/compiler/c6000_7.4.14r r }r (jYUjZjubaubj)r }r (jYX=ti.targets.arm.elf.M4=$(DEPOT)/ccsv6/tools/compiler/arm_5.2.4jZj\jbj/jdjjf}r (jjjk]jj]jh]ji]jn]ujpKWjqhjr]r j{X=ti.targets.arm.elf.M4=$(DEPOT)/ccsv6/tools/compiler/arm_5.2.4r r }r (jYUjZj ubaubj)r }r (jYXFti.targets.arp32.elf.ARP32_far=$(DEPOT)/ccsv6/tools/compiler/arm_5.2.4jZj\jbj/jdjjf}r (jjjk]jj]jh]ji]jn]ujpK[jqhjr]r j{XFti.targets.arp32.elf.ARP32_far=$(DEPOT)/ccsv6/tools/compiler/arm_5.2.4r r }r (jYUjZj ubaubj)r }r (jYX.See the following example, and ensure you are using the latest version of folder names present in ~/ti folder: DEPOT=/home/Your_Ubuntu_home_folder/ti # Use the following environment assignment (Note you must use 32 bit Java even in Ubuntu 14.04 64 bit OS environment) export XDCTOOLS_JAVA_HOME=/home/Your_Ubuntu_home_folder/ti/ccsv6/eclipse/jre #### BIOS-side dependencies #### BIOS_INSTALL_DIR=$(DEPOT)/bios_6_41_04_54 IPC_INSTALL_DIR=$(DEPOT)/ipc_3_36_01_11 XDC_INSTALL_DIR=$(DEPOT)/xdctools_3_31_02_38 #### BIOS-side toolchains #### gnu.targets.arm.A15F=$(DEPOT)/ccsv6/tools/compiler/gcc-arm-none-eabi-4_8-2014q3 ti.targets.elf.C66=$(DEPOT)/ti-cgt-c6000_8.0.3 ti.targets.arm.elf.M4=$(DEPOT)/ccsv6/tools/compiler/ti-cgt-arm_5.2.4 ti.targets.arp32.elf.ARP32_far=$(DEPOT)/ccsv6/tools/compiler/ti-cgt-arm_5.2.4jZj\jbj/jdjjf}r (jjjk]jj]jh]ji]jn]ujpK_jqhjr]r j{X.See the following example, and ensure you are using the latest version of folder names present in ~/ti folder: DEPOT=/home/Your_Ubuntu_home_folder/ti # Use the following environment assignment (Note you must use 32 bit Java even in Ubuntu 14.04 64 bit OS environment) export XDCTOOLS_JAVA_HOME=/home/Your_Ubuntu_home_folder/ti/ccsv6/eclipse/jre #### BIOS-side dependencies #### BIOS_INSTALL_DIR=$(DEPOT)/bios_6_41_04_54 IPC_INSTALL_DIR=$(DEPOT)/ipc_3_36_01_11 XDC_INSTALL_DIR=$(DEPOT)/xdctools_3_31_02_38 #### BIOS-side toolchains #### gnu.targets.arm.A15F=$(DEPOT)/ccsv6/tools/compiler/gcc-arm-none-eabi-4_8-2014q3 ti.targets.elf.C66=$(DEPOT)/ti-cgt-c6000_8.0.3 ti.targets.arm.elf.M4=$(DEPOT)/ccsv6/tools/compiler/ti-cgt-arm_5.2.4 ti.targets.arp32.elf.ARP32_far=$(DEPOT)/ccsv6/tools/compiler/ti-cgt-arm_5.2.4r r }r (jYUjZj ubaubj%)r }r (jYUjZj\jbj/jdj(jf}r (j*U.jdKjk]jj]jh]j+Uji]jn]j,j-ujpKijqhjr]r j/)r }r (jYX|Run make command in current folder to build DSP1 and DSP2 hello examples. Output files are created under debug sub folders. jZj jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r! (jYX{Run make command in current folder to build DSP1 and DSP2 hello examples. Output files are created under debug sub folders.r" jZj jbj/jdjjf}r# (jh]ji]jj]jk]jn]ujpKijr]r$ j{X{Run make command in current folder to build DSP1 and DSP2 hello examples. Output files are created under debug sub folders.r% r& }r' (jYj" jZj ubaubaubaubj=)r( }r) (jYUjZj\jbNjdj@jf}r* (jh]ji]jj]jk]jn]ujpNjqhjr]r+ jC)r, }r- (jYUjf}r. (jGX-jk]jj]jh]ji]jn]ujZj( jr]r/ (j/)r0 }r1 (jYXex01_hello\\dsp1\\bin\\debugr2 jf}r3 (jh]ji]jj]jk]jn]ujZj, jr]r4 j)r5 }r6 (jYj2 jZj0 jbj/jdjjf}r7 (jh]ji]jj]jk]jn]ujpKkjr]r8 j{Xex01_hello\dsp1\bin\debugr9 r: }r; (jYXex01_hello\\dsp1\\bin\\debugjZj5 ubaubajdj2ubj/)r< }r= (jYXex01_hello\\dsp2\\bin\\debug jf}r> (jh]ji]jj]jk]jn]ujZj, jr]r? j)r@ }rA (jYXex01_hello\\dsp2\\bin\\debugjZj< jbj/jdjjf}rB (jh]ji]jj]jk]jn]ujpKljr]rC j{Xex01_hello\dsp2\bin\debugrD rE }rF (jYXex01_hello\\dsp2\\bin\\debugjZj@ ubaubajdj2ubejdj`ubaubj%)rG }rH (jYUjZj\jbj/jdj(jf}rI (j*U.jdKjk]jj]jh]j+Uji]jn]j,j-ujpKnjqhjr]rJ (j/)rK }rL (jYXLaunch target configurations. jZjG jbj/jdj2jf}rM (jh]ji]jj]jk]jn]ujpNjqhjr]rN j)rO }rP (jYXLaunch target configurations.rQ jZjK jbj/jdjjf}rR (jh]ji]jj]jk]jn]ujpKnjr]rS j{XLaunch target configurations.rT rU }rV (jYjQ jZjO ubaubaubj/)rW }rX (jYX,Right click CortexA15_0 and connect target. jZjG jbj/jdj2jf}rY (jh]ji]jj]jk]jn]ujpNjqhjr]rZ j)r[ }r\ (jYX+Right click CortexA15_0 and connect target.r] jZjW jbj/jdjjf}r^ (jh]ji]jj]jk]jn]ujpKpjr]r_ j{X+Right click CortexA15_0 and connect target.r` ra }rb (jYj] jZj[ ubaubaubj/)rc }rd (jYX]On CCS --> Scripts --> AM572 Multicore Initialization --> Run AM572x Multicore EnableAllCore jZjG jbj/jdj2jf}re (jh]ji]jj]jk]jn]ujpNjqhjr]rf j)rg }rh (jYX\On CCS --> Scripts --> AM572 Multicore Initialization --> Run AM572x Multicore EnableAllCoreri jZjc jbj/jdjjf}rj (jh]ji]jj]jk]jn]ujpKrjr]rk j{X\On CCS --> Scripts --> AM572 Multicore Initialization --> Run AM572x Multicore EnableAllCorerl rm }rn (jYji jZjg ubaubaubj/)ro }rp (jYXeInitialize DDR configuration. On CCS --> Scripts --> DDR configurations --> AM572_DDR3_532MHz_config jZjG jbj/jdj2jf}rq (jh]ji]jj]jk]jn]ujpNjqhjr]rr j)rs }rt (jYXdInitialize DDR configuration. On CCS --> Scripts --> DDR configurations --> AM572_DDR3_532MHz_configru jZjo jbj/jdjjf}rv (jh]ji]jj]jk]jn]ujpKtjr]rw j{XdInitialize DDR configuration. On CCS --> Scripts --> DDR configurations --> AM572_DDR3_532MHz_configrx ry }rz (jYju jZjs ubaubaubj/)r{ }r| (jYX>Load DSP1 Hello Example hello_dsp1.xe66 (writer)file on DSP1. jZjG jbj/jdj2jf}r} (jh]ji]jj]jk]jn]ujpNjqhjr]r~ j)r }r (jYX=Load DSP1 Hello Example hello_dsp1.xe66 (writer)file on DSP1.r jZj{ jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKvjr]r j{X=Load DSP1 Hello Example hello_dsp1.xe66 (writer)file on DSP1.r r }r (jYj jZj ubaubaubj/)r }r (jYX?Load DSP2 Hello Example hello_dsp2.xe66 (reader) file on DSP2. jZjG jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYX>Load DSP2 Hello Example hello_dsp2.xe66 (reader) file on DSP2.r jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKxjr]r j{X>Load DSP2 Hello Example hello_dsp2.xe66 (reader) file on DSP2.r r }r (jYj jZj ubaubaubj/)r }r (jYXRun both DSP1 and DSP2. jZjG jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYXRun both DSP1 and DSP2.r jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKzjr]r j{XRun both DSP1 and DSP2.r r }r (jYj jZj ubaubaubj/)r }r (jYX-On CCS --> Tools --> RTOS Object view (ROV). jZjG jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYX,On CCS --> Tools --> RTOS Object view (ROV).r jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpK|jr]r j{X,On CCS --> Tools --> RTOS Object view (ROV).r r }r (jYj jZj ubaubaubj/)r }r (jYXvSuspend (halt) DSP1 to view test messages on ROV Viewable Modules -->LoggerBuf Refer below image of ROV log messages. jZjG jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYXuSuspend (halt) DSP1 to view test messages on ROV Viewable Modules -->LoggerBuf Refer below image of ROV log messages.r jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpK~jr]r j{XuSuspend (halt) DSP1 to view test messages on ROV Viewable Modules -->LoggerBuf Refer below image of ROV log messages.r r }r (jYj jZj ubaubaubeubjB)r }r (jYX$.. Image:: ../images/Hello_dsp2.png jZj\jbj/jdjEjf}r (UuriXrtos/../images/Hello_dsp2.pngr jk]jj]jh]ji]jH}r U*j sjn]ujpKjqhjr]ubj%)r }r (jYUjZj\jbj/jdj(jf}r (j*U.jdK jk]jj]jh]j+Uji]jn]j,j-ujpKjqhjr]r j/)r }r (jYX@Suspend (halt) DSP2 and click on ROV icon to view log messages. jZj jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYX?Suspend (halt) DSP2 and click on ROV icon to view log messages.r jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjr]r j{X?Suspend (halt) DSP2 and click on ROV icon to view log messages.r r }r (jYj jZj ubaubaubaubjZ)r }r (jYUjZj\jbj/jdj]jf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r j`)r }r (jYUjcKjZj jbj/jdjpjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r }r (jYXIPC Message Queue Example:r jKjZj\jbj/jdjjf}r (jk]r Uipc-message-queue-exampler ajj]jh]r jaji]jn]ujpNjqhjr]r j{XIPC Message Queue Example:r r }r (jYj jZj ubaubj)r }r (jYX**ex02_messageq**r jZj\jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r j)r }r (jYj jf}r (jh]ji]jj]jk]jn]ujZj jr]r j{X ex02_messageqr r }r (jYUjZj ubajdjubaubj)r }r (jYXMessage queue example sends round-trip message from client to server and back. MessageQ example uses client/server pattern. It is a two processors example: the HOST and DSP processors. Either DSP1 or DSP2 can be built for testing.r jZj\jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r j{XMessage queue example sends round-trip message from client to server and back. MessageQ example uses client/server pattern. It is a two processors example: the HOST and DSP processors. Either DSP1 or DSP2 can be built for testing.r r }r (jYj jZj ubaubj)r }r (jYXThe DSP processor is configured as server. It creates a named message queue. The server does not open any queues because it extracts the return address from the message header. The server returns all messages to the sender. It does not access the message pool.r jZj\jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r j{XThe DSP processor is configured as server. It creates a named message queue. The server does not open any queues because it extracts the return address from the message header. The server returns all messages to the sender. It does not access the message pool.r r }r (jYj jZj ubaubj)r }r (jYXThe HOST processor is configured as client application. The client creates an anonymous message queue. The client also creates and manages the message pool. The client's return address is set in the message header for each message before sending it to the server.r jZj\jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r j{XThe HOST processor is configured as client application. The client creates an anonymous message queue. The client also creates and manages the message pool. The client's return address is set in the message header for each message before sending it to the server.r r }r (jYj jZj ubaubj%)r }r (jYUjZj\jbj/jdj(jf}r (j*U.jk]jj]jh]j+Uji]jn]j,j-ujpKjqhjr]r j/)r }r (jYXsChange to messageQ folder example by enter: cd ~/ti/ipc_nn_nn_nn_nn/examples/DRA7xx_bios_elf/\ **ex02_messageQ** jZj jbNjdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r cdocutils.nodes definition_list r )r }r (jYUjf}r (jh]ji]jj]jk]jn]ujZj jr]r cdocutils.nodes definition_list_item r )r }r (jYXrChange to messageQ folder example by enter: cd ~/ti/ipc_nn_nn_nn_nn/examples/DRA7xx_bios_elf/\ **ex02_messageQ** jZj jbj/jdUdefinition_list_itemr jf}r (jh]ji]jj]jk]jn]ujpKjr]r (cdocutils.nodes term r )r }r (jYX+Change to messageQ folder example by enter:r jZj jbj/jdUtermr jf}r (jh]ji]jj]jk]jn]ujpKjr]r j{X+Change to messageQ folder example by enter:r r }r (jYj jZj ubaubcdocutils.nodes definition r )r }r! (jYUjf}r" (jh]ji]jj]jk]jn]ujZj jr]r# j)r$ }r% (jYXEcd ~/ti/ipc_nn_nn_nn_nn/examples/DRA7xx_bios_elf/\ **ex02_messageQ**jZj jbj/jdjjf}r& (jh]ji]jj]jk]jn]ujpKjr]r' (j{X2cd ~/ti/ipc_nn_nn_nn_nn/examples/DRA7xx_bios_elf/r( r) }r* (jYX4cd ~/ti/ipc_nn_nn_nn_nn/examples/DRA7xx_bios_elf/\ jZj$ ubj)r+ }r, (jYX**ex02_messageQ**jf}r- (jh]ji]jj]jk]jn]ujZj$ jr]r. j{X ex02_messageQr/ r0 }r1 (jYUjZj+ ubajdjubeubajdU definitionr2 ubeubajdUdefinition_listr3 ubaubaubj)r4 }r5 (jYX2. Open readme.txt file and follow build instructions step-by-step. Make sure there is no spaces between variable name and its value. See Hello World example environment varaible settings for reference.r6 jZj\jbj/jdjjf}r7 (jh]ji]jj]jk]jn]ujpKjqhjr]r8 j{X2. Open readme.txt file and follow build instructions step-by-step. Make sure there is no spaces between variable name and its value. See Hello World example environment varaible settings for reference.r9 r: }r; (jYj6 jZj4 ubaubj%)r< }r= (jYUjZj\jbj/jdj(jf}r> (j*U.jdKjk]jj]jh]j+Uji]jn]j,j-ujpKjqhjr]r? j/)r@ }rA (jYX{Run make command in current folder to build DSP1 and HOST hello examples. Output files are created under debug sub folders jZj< jbj/jdj2jf}rB (jh]ji]jj]jk]jn]ujpNjqhjr]rC j)rD }rE (jYXzRun make command in current folder to build DSP1 and HOST hello examples. Output files are created under debug sub foldersrF jZj@ jbj/jdjjf}rG (jh]ji]jj]jk]jn]ujpKjr]rH j{XzRun make command in current folder to build DSP1 and HOST hello examples. Output files are created under debug sub foldersrI rJ }rK (jYjF jZjD ubaubaubaubj=)rL }rM (jYUjZj\jbNjdj@jf}rN (jh]ji]jj]jk]jn]ujpNjqhjr]rO jC)rP }rQ (jYUjf}rR (jGX-jk]jj]jh]ji]jn]ujZjL jr]rS (j/)rT }rU (jYX1ex02_messageq\\host\\bin\\debug : HOST A15 binaryrV jf}rW (jh]ji]jj]jk]jn]ujZjP jr]rX j)rY }rZ (jYjV jZjT jbj/jdjjf}r[ (jh]ji]jj]jk]jn]ujpKjr]r\ j{X.ex02_messageq\host\bin\debug : HOST A15 binaryr] r^ }r_ (jYX1ex02_messageq\\host\\bin\\debug : HOST A15 binaryjZjY ubaubajdj2ubj/)r` }ra (jYX.ex02_messageq\\dsp1\\bin\\debug : C66x binary jf}rb (jh]ji]jj]jk]jn]ujZjP jr]rc j)rd }re (jYX-ex02_messageq\\dsp1\\bin\\debug : C66x binaryjZj` jbj/jdjjf}rf (jh]ji]jj]jk]jn]ujpKjr]rg j{X*ex02_messageq\dsp1\bin\debug : C66x binaryrh ri }rj (jYX-ex02_messageq\\dsp1\\bin\\debug : C66x binaryjZjd ubaubajdj2ubejdj`ubaubj%)rk }rl (jYUjZj\jbj/jdj(jf}rm (j*U.jdKjk]jj]jh]j+Uji]jn]j,j-ujpKjqhjr]rn (j/)ro }rp (jYXaLaunch target configurations. Note that BH560USB_M is emulator is used to connect to AM572X EVM. jZjk jbj/jdj2jf}rq (jh]ji]jj]jk]jn]ujpNjqhjr]rr j)rs }rt (jYX`Launch target configurations. Note that BH560USB_M is emulator is used to connect to AM572X EVM.ru jZjo jbj/jdjjf}rv (jh]ji]jj]jk]jn]ujpKjr]rw j{X`Launch target configurations. Note that BH560USB_M is emulator is used to connect to AM572X EVM.rx ry }rz (jYju jZjs ubaubaubj/)r{ }r| (jYX,Right click CortexA15_0 and connect target. jZjk jbj/jdj2jf}r} (jh]ji]jj]jk]jn]ujpNjqhjr]r~ j)r }r (jYX+Right click CortexA15_0 and connect target.r jZj{ jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjr]r j{X+Right click CortexA15_0 and connect target.r r }r (jYj jZj ubaubaubj/)r }r (jYX]On CCS --> Scripts --> AM572 Multicore Initialization --> Run AM572x Multicore EnableAllCore jZjk jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYX\On CCS --> Scripts --> AM572 Multicore Initialization --> Run AM572x Multicore EnableAllCorer jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjr]r j{X\On CCS --> Scripts --> AM572 Multicore Initialization --> Run AM572x Multicore EnableAllCorer r }r (jYj jZj ubaubaubj/)r }r (jYXeInitialize DDR configuration. On CCS --> Scripts --> DDR configurations --> AM572_DDR3_532MHz_config jZjk jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYXdInitialize DDR configuration. On CCS --> Scripts --> DDR configurations --> AM572_DDR3_532MHz_configr jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjr]r j{XdInitialize DDR configuration. On CCS --> Scripts --> DDR configurations --> AM572_DDR3_532MHz_configr r }r (jYj jZj ubaubaubj/)r }r (jYXE**Load DSP1** messageQ Example out file(server_dsp1.xe66) onto DSP1. jZjk jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYXD**Load DSP1** messageQ Example out file(server_dsp1.xe66) onto DSP1.jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjr]r (j)r }r (jYX **Load DSP1**jf}r (jh]ji]jj]jk]jn]ujZj jr]r j{X Load DSP1r r }r (jYUjZj ubajdjubj{X7 messageQ Example out file(server_dsp1.xe66) onto DSP1.r r }r (jYX7 messageQ Example out file(server_dsp1.xe66) onto DSP1.jZj ubeubaubj/)r }r (jYXO**Load HOST** messageQ Example out file(app_host.xa15fg) onto ARM CortexA15_0. jZjk jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYXN**Load HOST** messageQ Example out file(app_host.xa15fg) onto ARM CortexA15_0.jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjr]r (j)r }r (jYX **Load HOST**jf}r (jh]ji]jj]jk]jn]ujZj jr]r j{X Load HOSTr r }r (jYUjZj ubajdjubj{XA messageQ Example out file(app_host.xa15fg) onto ARM CortexA15_0.r r }r (jYXA messageQ Example out file(app_host.xa15fg) onto ARM CortexA15_0.jZj ubeubaubj/)r }r (jYXRun both DSP1 and HOST. jZjk jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYXRun both DSP1 and HOST.r jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjr]r j{XRun both DSP1 and HOST.r r }r (jYj jZj ubaubaubj/)r }r (jYX-On CCS --> Tools --> RTOS Object view (ROV). jZjk jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYX,On CCS --> Tools --> RTOS Object view (ROV).r jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjr]r j{X,On CCS --> Tools --> RTOS Object view (ROV).r r }r (jYj jZj ubaubaubj/)r }r (jYXSuspend (halt) ARM Cortex_A15 to view test messages on ROV Viewable Modules -->LoggerBuf Refer the following ROV message queue screenshot jZjk jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYXSuspend (halt) ARM Cortex_A15 to view test messages on ROV Viewable Modules -->LoggerBuf Refer the following ROV message queue screenshotr jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjr]r j{XSuspend (halt) ARM Cortex_A15 to view test messages on ROV Viewable Modules -->LoggerBuf Refer the following ROV message queue screenshotr r }r (jYj jZj ubaubaubeubjB)r }r (jYX$.. Image:: ../images/MesgQ_arm0.png jZj\jbj/jdjEjf}r (UuriXrtos/../images/MesgQ_arm0.pngr jk]jj]jh]ji]jH}r U*j sjn]ujpKjqhjr]ubj%)r }r (jYUjZj\jbj/jdj(jf}r (j*U.jdK jk]jj]jh]j+Uji]jn]j,j-ujpKjqhjr]r j/)r }r (jYX@Suspend (halt) DSP1 and click on ROV icon to view log messages. jZj jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYX?Suspend (halt) DSP1 and click on ROV icon to view log messages.r jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjr]r j{X?Suspend (halt) DSP1 and click on ROV icon to view log messages.r r }r (jYj jZj ubaubaubaubjZ)r }r (jYUjZj\jbj/jdj]jf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r j`)r }r (jYUjcKjZj jbj/jdjpjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r }r (jYXIPC Notify Peer Example:r jZj\jbj/jdjjf}r (jk]r Uipc-notify-peer-exampler ajj]jh]ji]jn]r hmaujpNjqhjr]r j{XIPC Notify Peer Example:r r }r (jYj jZj ubaubj)r }r (jYX**ex13_notifypeer**r jZj\jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r j)r }r (jYj jf}r (jh]ji]jj]jk]jn]ujZj jr]r j{Xex13_notifypeerr r }r (jYUjZj ubajdjubaubj)r }r (jYXNotify peer example only uses notify to communicate to a peer processor. This is an example of IPC Scalability. It uses the client/server design pattern. Initially, the example builds only for two processors: HOST and DSP1. The client runs on HOST and the server runs on DSP1.r jZj\jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r j{XNotify peer example only uses notify to communicate to a peer processor. This is an example of IPC Scalability. It uses the client/server design pattern. Initially, the example builds only for two processors: HOST and DSP1. The client runs on HOST and the server runs on DSP1.r r }r! (jYj jZj ubaubj)r" }r# (jYXThe client (HOST) creates an anonymous message queue. The client also creates and manages its own message pool. And it opens the server message queue using its name. The client initiates the data flow by allocating a message from the pool, placing its return address in the message header and sending the message to the server. It then waits for the message to be returned. When it receives the return message, the message is returned to the pool. The client repeats this in a loop.r$ jZj\jbj/jdjjf}r% (jh]ji]jj]jk]jn]ujpKjqhjr]r& j{XThe client (HOST) creates an anonymous message queue. The client also creates and manages its own message pool. And it opens the server message queue using its name. The client initiates the data flow by allocating a message from the pool, placing its return address in the message header and sending the message to the server. It then waits for the message to be returned. When it receives the return message, the message is returned to the pool. The client repeats this in a loop.r' r( }r) (jYj$ jZj" ubaubj)r* }r+ (jYX_The server (DSP1) creates a named message queue, then waits on it for messages. When a message arrives, the server performs the requested work. When the work is done, the server extracts the return address from the message header and sends the message back to the client. The server never opens any message queues and does not access the message pool.r, jZj\jbj/jdjjf}r- (jh]ji]jj]jk]jn]ujpKjqhjr]r. j{X_The server (DSP1) creates a named message queue, then waits on it for messages. When a message arrives, the server performs the requested work. When the work is done, the server extracts the return address from the message header and sends the message back to the client. The server never opens any message queues and does not access the message pool.r/ r0 }r1 (jYj, jZj* ubaubj)r2 }r3 (jYXSince DSP1 will need to wait on both the message queue and the notify queue, we introduce events. The SYS/BIOS event object can be used to wait on multiple input sources.r4 jZj\jbj/jdjjf}r5 (jh]ji]jj]jk]jn]ujpKjqhjr]r6 j{XSince DSP1 will need to wait on both the message queue and the notify queue, we introduce events. The SYS/BIOS event object can be used to wait on multiple input sources.r7 r8 }r9 (jYj4 jZj2 ubaubj%)r: }r; (jYUjZj\jbj/jdj(jf}r< (j*U.jk]jj]jh]j+Uji]jn]j,j-ujpKjqhjr]r= (j/)r> }r? (jYXvChange to notify_peer folder example by enter: cd ~/ti/ipc_nn_nn_nn_nn/examples/DRA7xx_bios_elf/\ **ex13_notifypeer** jZj: jbj/jdj2jf}r@ (jh]ji]jj]jk]jn]ujpNjqhjr]rA j)rB }rC (jYXuChange to notify_peer folder example by enter: cd ~/ti/ipc_nn_nn_nn_nn/examples/DRA7xx_bios_elf/\ **ex13_notifypeer**jZj> jbj/jdjjf}rD (jh]ji]jj]jk]jn]ujpKjr]rE (j{X`Change to notify_peer folder example by enter: cd ~/ti/ipc_nn_nn_nn_nn/examples/DRA7xx_bios_elf/rF rG }rH (jYXbChange to notify_peer folder example by enter: cd ~/ti/ipc_nn_nn_nn_nn/examples/DRA7xx_bios_elf/\ jZjB ubj)rI }rJ (jYX**ex13_notifypeer**jf}rK (jh]ji]jj]jk]jn]ujZjB jr]rL j{Xex13_notifypeerrM rN }rO (jYUjZjI ubajdjubeubaubj/)rP }rQ (jYXOpen readme.txt file and follow build instructions step-by-step. Make sure there is no spaces between variable name and its value. jZj: jbj/jdj2jf}rR (jh]ji]jj]jk]jn]ujpNjqhjr]rS j)rT }rU (jYXOpen readme.txt file and follow build instructions step-by-step. Make sure there is no spaces between variable name and its value.rV jZjP jbj/jdjjf}rW (jh]ji]jj]jk]jn]ujpKjr]rX j{XOpen readme.txt file and follow build instructions step-by-step. Make sure there is no spaces between variable name and its value.rY rZ }r[ (jYjV jZjT ubaubaubj/)r\ }r] (jYXRun make command in current folder to build DSP1 and HOST notifypeer examples. Output files are created under debug subfolder. jZj: jbj/jdj2jf}r^ (jh]ji]jj]jk]jn]ujpNjqhjr]r_ j)r` }ra (jYX~Run make command in current folder to build DSP1 and HOST notifypeer examples. Output files are created under debug subfolder.rb jZj\ jbj/jdjjf}rc (jh]ji]jj]jk]jn]ujpKjr]rd j{X~Run make command in current folder to build DSP1 and HOST notifypeer examples. Output files are created under debug subfolder.re rf }rg (jYjb jZj` ubaubaubj/)rh }ri (jYXaLaunch target configurations. Note that BH560USB_M is emulator is used to connect to AM572X EVM. jZj: jbj/jdj2jf}rj (jh]ji]jj]jk]jn]ujpNjqhjr]rk j)rl }rm (jYX`Launch target configurations. Note that BH560USB_M is emulator is used to connect to AM572X EVM.rn jZjh jbj/jdjjf}ro (jh]ji]jj]jk]jn]ujpKjr]rp j{X`Launch target configurations. Note that BH560USB_M is emulator is used to connect to AM572X EVM.rq rr }rs (jYjn jZjl ubaubaubj/)rt }ru (jYX,Right click CortexA15_0 and connect target. jZj: jbj/jdj2jf}rv (jh]ji]jj]jk]jn]ujpNjqhjr]rw j)rx }ry (jYX+Right click CortexA15_0 and connect target.rz jZjt jbj/jdjjf}r{ (jh]ji]jj]jk]jn]ujpKjr]r| j{X+Right click CortexA15_0 and connect target.r} r~ }r (jYjz jZjx ubaubaubj/)r }r (jYX]On CCS --> Scripts --> AM572 Multicore Initialization --> Run AM572x Multicore EnableAllCore jZj: jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYX\On CCS --> Scripts --> AM572 Multicore Initialization --> Run AM572x Multicore EnableAllCorer jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjr]r j{X\On CCS --> Scripts --> AM572 Multicore Initialization --> Run AM572x Multicore EnableAllCorer r }r (jYj jZj ubaubaubj/)r }r (jYXeInitialize DDR configuration. On CCS --> Scripts --> DDR configurations --> AM572_DDR3_532MHz_config jZj: jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYXdInitialize DDR configuration. On CCS --> Scripts --> DDR configurations --> AM572_DDR3_532MHz_configr jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjr]r j{XdInitialize DDR configuration. On CCS --> Scripts --> DDR configurations --> AM572_DDR3_532MHz_configr r }r (jYj jZj ubaubaubj/)r }r (jYX3**Load DSP1** notifypeer Example out file on DSP1. jZj: jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYX2**Load DSP1** notifypeer Example out file on DSP1.jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjr]r (j)r }r (jYX **Load DSP1**jf}r (jh]ji]jj]jk]jn]ujZj jr]r j{X Load DSP1r r }r (jYUjZj ubajdjubj{X% notifypeer Example out file on DSP1.r r }r (jYX% notifypeer Example out file on DSP1.jZj ubeubaubj/)r }r (jYX>**Load HOST** notifypeer Example out file on ARM CortexA15_0. jZj: jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYX=**Load HOST** notifypeer Example out file on ARM CortexA15_0.jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjr]r (j)r }r (jYX **Load HOST**jf}r (jh]ji]jj]jk]jn]ujZj jr]r j{X Load HOSTr r }r (jYUjZj ubajdjubj{X0 notifypeer Example out file on ARM CortexA15_0.r r }r (jYX0 notifypeer Example out file on ARM CortexA15_0.jZj ubeubaubj/)r }r (jYXRun both DSP1 and CortexA15_0. jZj: jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYXRun both DSP1 and CortexA15_0.r jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjr]r j{XRun both DSP1 and CortexA15_0.r r }r (jYj jZj ubaubaubj/)r }r (jYX-On CCS --> Tools --> RTOS Object view (ROV). jZj: jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYX,On CCS --> Tools --> RTOS Object view (ROV).r jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjr]r j{X,On CCS --> Tools --> RTOS Object view (ROV).r r }r (jYj jZj ubaubaubj/)r }r (jYXSuspend (halt) ARM CortexA15_0 to view test messages on ROV Viewable Modules -->LoggerBuf. Refer the following image of ROV log messages jZj: jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYXSuspend (halt) ARM CortexA15_0 to view test messages on ROV Viewable Modules -->LoggerBuf. Refer the following image of ROV log messagesr jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjr]r j{XSuspend (halt) ARM CortexA15_0 to view test messages on ROV Viewable Modules -->LoggerBuf. Refer the following image of ROV log messagesr r }r (jYj jZj ubaubaubeubjB)r }r (jYX*.. Image:: ../images/Notify_peer_arm0.png jZj\jbj/jdjEjf}r (UuriX#rtos/../images/Notify_peer_arm0.pngr jk]jj]jh]ji]jH}r U*j sjn]ujpKjqhjr]ubj%)r }r (jYUjZj\jbj/jdj(jf}r (j*U.jdK jk]jj]jh]j+Uji]jn]j,j-ujpKjqhjr]r j/)r }r (jYX@Suspend (halt) DSP2 and click on ROV icon to view log messages. jZj jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYX?Suspend (halt) DSP2 and click on ROV icon to view log messages.r jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjr]r j{X?Suspend (halt) DSP2 and click on ROV icon to view log messages.r r }r (jYj jZj ubaubaubaubjZ)r }r (jYUjZj\jbj/jdj]jf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r j`)r }r (jYUjcKjZj jbj/jdjpjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r }r (jYXIPC Ping Example:r jZj\jbj/jdjjf}r (jk]r Uipc-ping-exampler ajj]jh]ji]jn]r h-aujpNjqhjr]r j{XIPC Ping Example:r r }r (jYj jZj ubaubj)r }r (jYX **ex11_ping**r jZj\jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r j)r }r (jYj jf}r (jh]ji]jj]jk]jn]ujZj jr]r j{X ex11_pingr r }r (jYUjZj ubajdjubaubj)r }r (jYXOping example sends a message between all cores in the system. This example is used to exercise every communication path between all processors in the system (including local delivery on the current processor). Ping example is also organized in a suitable manner to develop an application with different compute units on each processor.r jZj\jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r j{XOping example sends a message between all cores in the system. This example is used to exercise every communication path between all processors in the system (including local delivery on the current processor). Ping example is also organized in a suitable manner to develop an application with different compute units on each processor.r r }r (jYj jZj ubaubj)r }r (jYX Each executable will create two tasks: 1) the server task, and 2) the application task. The server task creates a message queue and then waits on that queue for incoming messages. When a message is received, the server task simply sends it back to the original sender.r jZj\jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpMjqhjr]r j{X Each executable will create two tasks: 1) the server task, and 2) the application task. The server task creates a message queue and then waits on that queue for incoming messages. When a message is received, the server task simply sends it back to the original sender.r r! }r" (jYj jZj ubaubj)r# }r$ (jYX;The application task creates its own message queue and then opens every server message queue in the system (including the server queue on the local processor). The task sends a message to a server and waits for the message to be returned. This is repeated for each server in the system (including the local server).r% jZj\jbj/jdjjf}r& (jh]ji]jj]jk]jn]ujpM jqhjr]r' j{X;The application task creates its own message queue and then opens every server message queue in the system (including the server queue on the local processor). The task sends a message to a server and waits for the message to be returned. This is repeated for each server in the system (including the local server).r( r) }r* (jYj% jZj# ubaubj)r+ }r, (jYXaNote that presently EVE is not yet supported and therefore, DSP1/DSP2/HOST are built for testing.jZj\jbj/jdjjf}r- (jh]ji]jj]jk]jn]ujpNjqhjr]r. j)r/ }r0 (jYXaNote that presently EVE is not yet supported and therefore, DSP1/DSP2/HOST are built for testing.r1 jZj+ jbj/jdjjf}r2 (jh]ji]jj]jk]jn]ujpMjr]r3 j{XaNote that presently EVE is not yet supported and therefore, DSP1/DSP2/HOST are built for testing.r4 r5 }r6 (jYj1 jZj/ ubaubaubj)r7 }r8 (jYXk1. Change to ping folder example by enter: cd ~/ti/ipc_nn_nn_nn_nn/examples/DRA7xx_bios_elf/\ **ex11_ping**jZj\jbj/jdjjf}r9 (jh]ji]jj]jk]jn]ujpMjqhjr]r: (j{X\1. Change to ping folder example by enter: cd ~/ti/ipc_nn_nn_nn_nn/examples/DRA7xx_bios_elf/r; r< }r= (jYX^1. Change to ping folder example by enter: cd ~/ti/ipc_nn_nn_nn_nn/examples/DRA7xx_bios_elf/\ jZj7 ubj)r> }r? (jYX **ex11_ping**jf}r@ (jh]ji]jj]jk]jn]ujZj7 jr]rA j{X ex11_pingrB rC }rD (jYUjZj> ubajdjubeubj)rE }rF (jYX2. Open readme.txt file and follow build instructions step-by-step. Make sure there is no space between variable name and its value.rG jZj\jbj/jdjjf}rH (jh]ji]jj]jk]jn]ujpMjqhjr]rI j{X2. Open readme.txt file and follow build instructions step-by-step. Make sure there is no space between variable name and its value.rJ rK }rL (jYjG jZjE ubaubj%)rM }rN (jYUjZj\jbj/jdj(jf}rO (j*U.jdKjk]jj]jh]j+Uji]jn]j,j-ujpMjqhjr]rP (j/)rQ }rR (jYX;Open makefile and remove EVE and IPU from PROC build list. jZjM jbj/jdj2jf}rS (jh]ji]jj]jk]jn]ujpNjqhjr]rT j)rU }rV (jYX:Open makefile and remove EVE and IPU from PROC build list.rW jZjQ jbj/jdjjf}rX (jh]ji]jj]jk]jn]ujpMjr]rY j{X:Open makefile and remove EVE and IPU from PROC build list.rZ r[ }r\ (jYjW jZjU ubaubaubj/)r] }r^ (jYXRun make command in current folder to build DSP1, DSP2 and HOST ping examples. Output files are created under debug subfolder. jZjM jbj/jdj2jf}r_ (jh]ji]jj]jk]jn]ujpNjqhjr]r` j)ra }rb (jYX~Run make command in current folder to build DSP1, DSP2 and HOST ping examples. Output files are created under debug subfolder.rc jZj] jbj/jdjjf}rd (jh]ji]jj]jk]jn]ujpMjr]re j{X~Run make command in current folder to build DSP1, DSP2 and HOST ping examples. Output files are created under debug subfolder.rf rg }rh (jYjc jZja ubaubaubj/)ri }rj (jYXaLaunch target configurations. Note that BH560USB_M is emulator is used to connect to AM572X EVM. jZjM jbj/jdj2jf}rk (jh]ji]jj]jk]jn]ujpNjqhjr]rl j)rm }rn (jYX`Launch target configurations. Note that BH560USB_M is emulator is used to connect to AM572X EVM.ro jZji jbj/jdjjf}rp (jh]ji]jj]jk]jn]ujpMjr]rq j{X`Launch target configurations. Note that BH560USB_M is emulator is used to connect to AM572X EVM.rr rs }rt (jYjo jZjm ubaubaubj/)ru }rv (jYX,Right click CortexA15_0 and connect target. jZjM jbj/jdj2jf}rw (jh]ji]jj]jk]jn]ujpNjqhjr]rx j)ry }rz (jYX+Right click CortexA15_0 and connect target.r{ jZju jbj/jdjjf}r| (jh]ji]jj]jk]jn]ujpMjr]r} j{X+Right click CortexA15_0 and connect target.r~ r }r (jYj{ jZjy ubaubaubj/)r }r (jYX]On CCS --> Scripts --> AM572 Multicore Initialization --> Run AM572x Multicore EnableAllCore jZjM jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYX\On CCS --> Scripts --> AM572 Multicore Initialization --> Run AM572x Multicore EnableAllCorer jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpM!jr]r j{X\On CCS --> Scripts --> AM572 Multicore Initialization --> Run AM572x Multicore EnableAllCorer r }r (jYj jZj ubaubaubj/)r }r (jYXeInitialize DDR configuration. On CCS --> Scripts --> DDR configurations --> AM572_DDR3_532MHz_config jZjM jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYXdInitialize DDR configuration. On CCS --> Scripts --> DDR configurations --> AM572_DDR3_532MHz_configr jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpM#jr]r j{XdInitialize DDR configuration. On CCS --> Scripts --> DDR configurations --> AM572_DDR3_532MHz_configr r }r (jYj jZj ubaubaubj/)r }r (jYX-**Load DSP1** Ping Example out file on DSP1. jZjM jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYX,**Load DSP1** Ping Example out file on DSP1.jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpM%jr]r (j)r }r (jYX **Load DSP1**jf}r (jh]ji]jj]jk]jn]ujZj jr]r j{X Load DSP1r r }r (jYUjZj ubajdjubj{X Ping Example out file on DSP1.r r }r (jYX Ping Example out file on DSP1.jZj ubeubaubj/)r }r (jYX-**Load DSP2** Ping Example out file on DSP2. jZjM jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYX,**Load DSP2** Ping Example out file on DSP2.jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpM'jr]r (j)r }r (jYX **Load DSP2**jf}r (jh]ji]jj]jk]jn]ujZj jr]r j{X Load DSP2r r }r (jYUjZj ubajdjubj{X Ping Example out file on DSP2.r r }r (jYX Ping Example out file on DSP2.jZj ubeubaubj/)r }r (jYX0**Load HOST** ping Example onto ARM CortexA15_0 jZjM jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYX/**Load HOST** ping Example onto ARM CortexA15_0jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpM)jr]r (j)r }r (jYX **Load HOST**jf}r (jh]ji]jj]jk]jn]ujZj jr]r j{X Load HOSTr r }r (jYUjZj ubajdjubj{X" ping Example onto ARM CortexA15_0r r }r (jYX" ping Example onto ARM CortexA15_0jZj ubeubaubj/)r }r (jYX!Run DSP1, DSP2, and HOST images. jZjM jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYX Run DSP1, DSP2, and HOST images.r jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpM+jr]r j{X Run DSP1, DSP2, and HOST images.r r }r (jYj jZj ubaubaubj/)r }r (jYX-On CCS --> Tools --> RTOS Object view (ROV). jZjM jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYX,On CCS --> Tools --> RTOS Object view (ROV).r jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpM-jr]r j{X,On CCS --> Tools --> RTOS Object view (ROV).r r }r (jYj jZj ubaubaubj/)r }r (jYXkHalt DSP1 to view test messages on ROV Viewable Modules -->LoggerBuf Refer below image of ROV log messages jZjM jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYXjHalt DSP1 to view test messages on ROV Viewable Modules -->LoggerBuf Refer below image of ROV log messagesr jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpM/jr]r j{XjHalt DSP1 to view test messages on ROV Viewable Modules -->LoggerBuf Refer below image of ROV log messagesr r }r (jYj jZj ubaubaubeubjB)r }r (jYX#.. Image:: ../images/Ping_dsp1.png jZj\jbj/jdjEjf}r (UuriXrtos/../images/Ping_dsp1.pngr jk]jj]jh]ji]jH}r U*j sjn]ujpM2jqhjr]ubj%)r }r (jYUjZj\jbj/jdj(jf}r (j*U.jdKjk]jj]jh]j+Uji]jn]j,j-ujpM3jqhjr]r (j/)r }r (jYX@Suspend (halt) DSP2 and click on ROV icon to view log messages. jZj jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYX?Suspend (halt) DSP2 and click on ROV icon to view log messages.r jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpM3jr]r j{X?Suspend (halt) DSP2 and click on ROV icon to view log messages.r r }r (jYj jZj ubaubaubj/)r }r (jYXKSuspend (halt) ARM CortexA15_0 and click on ROV icon to view log messages. jZj jbj/jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYXJSuspend (halt) ARM CortexA15_0 and click on ROV icon to view log messages.r jZj jbj/jdjjf}r (jh]ji]jj]jk]jn]ujpM5jr]r j{XJSuspend (halt) ARM CortexA15_0 and click on ROV icon to view log messages.r r }r (jYj jZj ubaubaubeubjZ)r }r (jYUjZj\jbj/jdj]jf}r (jh]ji]jj]jk]jn]ujpM7jqhjr]r j`)r }r (jYUjcKjZj jbj/jdjpjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r }r (jYXExpanding IPC Ping Example:r jZj\jbj/jdjjf}r (jk]r Uexpanding-ipc-ping-exampler ajj]jh]ji]jn]r! jaujpNjqhjr]r" j{XExpanding IPC Ping Example:r# r$ }r% (jYj jZj ubaubj)r& }r' (jYXaTo demonstrate the flexibility of IPC architecture, you may include additional cores to the above example by modifying the make file. For example, you may add IPU1 in the list of processor in the make file as: DSP1, DSP2, **IPU1,** HOST. After a clean build, the appropriate configuration and output executable files will be generated that allow passing messages between DSP1, DSP2, IPU1 and Host. Procedures are the same as described in the previous example with the exception of additional steps to load the IPU1 core with the corresponding executable and running it in conjunction with DSP1, DSP2 and HOST.jZj\jbj/jdjjf}r( (jh]ji]jj]jk]jn]ujpM<jqhjr]r) (j{XTo demonstrate the flexibility of IPC architecture, you may include additional cores to the above example by modifying the make file. For example, you may add IPU1 in the list of processor in the make file as: DSP1, DSP2, r* r+ }r, (jYXTo demonstrate the flexibility of IPC architecture, you may include additional cores to the above example by modifying the make file. For example, you may add IPU1 in the list of processor in the make file as: DSP1, DSP2, jZj& ubj)r- }r. (jYX **IPU1,**jf}r/ (jh]ji]jj]jk]jn]ujZj& jr]r0 j{XIPU1,r1 r2 }r3 (jYUjZj- ubajdjubj{Xz HOST. After a clean build, the appropriate configuration and output executable files will be generated that allow passing messages between DSP1, DSP2, IPU1 and Host. Procedures are the same as described in the previous example with the exception of additional steps to load the IPU1 core with the corresponding executable and running it in conjunction with DSP1, DSP2 and HOST.r4 r5 }r6 (jYXz HOST. After a clean build, the appropriate configuration and output executable files will be generated that allow passing messages between DSP1, DSP2, IPU1 and Host. Procedures are the same as described in the previous example with the exception of additional steps to load the IPU1 core with the corresponding executable and running it in conjunction with DSP1, DSP2 and HOST.jZj& ubeubj)r7 }r8 (jYXDuring build process using IPU1, you may encounter a message indicating **rtsv7M4_T_le_eabi.lib** library is missing. This is a know issue and is being tracked by **SDCOM00118417** IR. However, you may create this missing library by going to the compiler installation's **lib** directory and execute the following command to regenerate all required libraries: :: ./mklib --alljZj\jbj/jdjjf}r9 (jh]ji]jj]jk]jn]ujpNjqhjr]r: (j)r; }r< (jYXgDuring build process using IPU1, you may encounter a message indicating **rtsv7M4_T_le_eabi.lib** library is missing. This is a know issue and is being tracked by **SDCOM00118417** IR. However, you may create this missing library by going to the compiler installation's **lib** directory and execute the following command to regenerate all required libraries:jZj7 jbj/jdjjf}r= (jh]ji]jj]jk]jn]ujpMGjr]r> (j{XHDuring build process using IPU1, you may encounter a message indicating r? r@ }rA (jYXHDuring build process using IPU1, you may encounter a message indicating jZj; ubj)rB }rC (jYX**rtsv7M4_T_le_eabi.lib**jf}rD (jh]ji]jj]jk]jn]ujZj; jr]rE j{Xrtsv7M4_T_le_eabi.librF rG }rH (jYUjZjB ubajdjubj{XB library is missing. This is a know issue and is being tracked by rI rJ }rK (jYXB library is missing. This is a know issue and is being tracked by jZj; ubj)rL }rM (jYX**SDCOM00118417**jf}rN (jh]ji]jj]jk]jn]ujZj; jr]rO j{X SDCOM00118417rP rQ }rR (jYUjZjL ubajdjubj{XZ IR. However, you may create this missing library by going to the compiler installation's rS rT }rU (jYXZ IR. However, you may create this missing library by going to the compiler installation's jZj; ubj)rV }rW (jYX**lib**jf}rX (jh]ji]jj]jk]jn]ujZj; jr]rY j{XlibrZ r[ }r\ (jYUjZjV ubajdjubj{XR directory and execute the following command to regenerate all required libraries:r] r^ }r_ (jYXR directory and execute the following command to regenerate all required libraries:jZj; ubeubj)r` }ra (jYX ./mklib --alljZj7 jdjjf}rb (jjjk]jj]jh]ji]jn]ujpMYjr]rc j{X ./mklib --allrd re }rf (jYUjZj` ubaubeubj)rg }rh (jYXaThe following example depicts a typical host communications protocol with other IPC apps (dsp1, dsp2, ipu1) **Note that the following HOST communications list has been rearranged to further clarify the type of communications between various cores**. Typically these messages arrive at different intervals depending on each core processes execution time.jZj\jbj/jdjjf}ri (jh]ji]jj]jk]jn]ujpMRjqhjr]rj (j{XlThe following example depicts a typical host communications protocol with other IPC apps (dsp1, dsp2, ipu1) rk rl }rm (jYXlThe following example depicts a typical host communications protocol with other IPC apps (dsp1, dsp2, ipu1) jZjg ubj)rn }ro (jYX**Note that the following HOST communications list has been rearranged to further clarify the type of communications between various cores**jf}rp (jh]ji]jj]jk]jn]ujZjg jr]rq j{XNote that the following HOST communications list has been rearranged to further clarify the type of communications between various coresrr rs }rt (jYUjZjn ubajdjubj{Xi. Typically these messages arrive at different intervals depending on each core processes execution time.ru rv }rw (jYXi. Typically these messages arrive at different intervals depending on each core processes execution time.jZjg ubeubj)rx }ry (jYX>1 xdc.runtime.Main --> main: 2 xdc.runtime.Main main: ipc ready 3 xdc.runtime.Main MainHost_svrTskFxn: 4 SvrHost --> SvrHost_setup: 5 SvrHost SvrHost_setup: slave is ready 6 SvrHost <-- SvrHost_setup: 7 SvrHost --> SvrHost_run: 8 xdc.runtime.Main --> MainHost_appTskFxn: 9 AppHost --> AppHost_setup: 10 AppHost AppHost_setup: procId=0 opened server queue 11 AppHost AppHost_setup: procId=1 opened server queue 12 AppHost AppHost_setup: procId=2 opened server queue 28 AppHost AppHost_setup: procId=3 opened server queue 32 AppHost AppHost_run: ping procId=0 34 AppHost AppHost_run: ping procId=0 36 AppHost AppHost_run: ping procId=0 38 AppHost AppHost_run: ping procId=0 40 AppHost AppHost_run: ping procId=0 33 AppHost AppHost_run: ack received procId=0 35 AppHost AppHost_run: ack received procId=0 37 AppHost AppHost_run: ack received procId=0 39 AppHost AppHost_run: ack received procId=0 41 AppHost AppHost_run: ack received procId=0 13 SvrHost SvrHost_run: message received procId=0 14 SvrHost SvrHost_run: message received procId=0 15 SvrHost SvrHost_run: message received procId=0 16 SvrHost SvrHost_run: message received procId=0 17 SvrHost SvrHost_run: message received procId=0 42 AppHost AppHost_run: ping procId=1 44 AppHost AppHost_run: ping procId=1 46 AppHost AppHost_run: ping procId=1 48 AppHost AppHost_run: ping procId=1 50 AppHost AppHost_run: ping procId=1 43 AppHost AppHost_run: ack received procId=1 45 AppHost AppHost_run: ack received procId=1 47 AppHost AppHost_run: ack received procId=1 49 AppHost AppHost_run: ack received procId=1 51 AppHost AppHost_run: ack received procId=1 18 SvrHost SvrHost_run: message received procId=1 19 SvrHost SvrHost_run: message received procId=1 20 SvrHost SvrHost_run: message received procId=1 21 SvrHost SvrHost_run: message received procId=1 22 SvrHost SvrHost_run: message received procId=1 52 AppHost AppHost_run: ping procId=2 55 AppHost AppHost_run: ping procId=2 58 AppHost AppHost_run: ping procId=2 61 AppHost AppHost_run: ping procId=2 64 AppHost AppHost_run: ping procId=2 54 AppHost AppHost_run: ack received procId=2 57 AppHost AppHost_run: ack received procId=2 60 AppHost AppHost_run: ack received procId=2 63 AppHost AppHost_run: ack received procId=2 66 AppHost AppHost_run: ack received procId=2 53 SvrHost SvrHost_run: message received procId=2 56 SvrHost SvrHost_run: message received procId=2 59 SvrHost SvrHost_run: message received procId=2 62 SvrHost SvrHost_run: message received procId=2 65 SvrHost SvrHost_run: message received procId=2 67 AppHost AppHost_run: ping procId=3 69 AppHost AppHost_run: ping procId=3 71 AppHost AppHost_run: ping procId=3 73 AppHost AppHost_run: ping procId=3 75 AppHost AppHost_run: ping procId=3 68 AppHost AppHost_run: ack received procId=3 70 AppHost AppHost_run: ack received procId=3 72 AppHost AppHost_run: ack received procId=3 74 AppHost AppHost_run: ack received procId=3 76 AppHost AppHost_run: ack received procId=3 23 SvrHost SvrHost_run: message received procId=3 24 SvrHost SvrHost_run: message received procId=3 25 SvrHost SvrHost_run: message received procId=3 26 SvrHost SvrHost_run: message received procId=3 27 SvrHost SvrHost_run: message received procId=3 29 AppHost AppHost_setup: slave is ready 30 AppHost <-- AppHost_setup: 31 AppHost --> AppHost_run: 77 AppHost <-- AppHost_run: 0 78 AppHost --> AppHost_destroy: 79 AppHost <-- AppHost_destroy: status=0 80 xdc.runtime.Main <-- MainHost_appTskFxn: 0 81 xdc.runtime.Main MainHost_done:jZj\jbj/jdjjf}rz (jjjk]jj]jh]ji]jn]ujpMcjqhjr]r{ j{X>1 xdc.runtime.Main --> main: 2 xdc.runtime.Main main: ipc ready 3 xdc.runtime.Main MainHost_svrTskFxn: 4 SvrHost --> SvrHost_setup: 5 SvrHost SvrHost_setup: slave is ready 6 SvrHost <-- SvrHost_setup: 7 SvrHost --> SvrHost_run: 8 xdc.runtime.Main --> MainHost_appTskFxn: 9 AppHost --> AppHost_setup: 10 AppHost AppHost_setup: procId=0 opened server queue 11 AppHost AppHost_setup: procId=1 opened server queue 12 AppHost AppHost_setup: procId=2 opened server queue 28 AppHost AppHost_setup: procId=3 opened server queue 32 AppHost AppHost_run: ping procId=0 34 AppHost AppHost_run: ping procId=0 36 AppHost AppHost_run: ping procId=0 38 AppHost AppHost_run: ping procId=0 40 AppHost AppHost_run: ping procId=0 33 AppHost AppHost_run: ack received procId=0 35 AppHost AppHost_run: ack received procId=0 37 AppHost AppHost_run: ack received procId=0 39 AppHost AppHost_run: ack received procId=0 41 AppHost AppHost_run: ack received procId=0 13 SvrHost SvrHost_run: message received procId=0 14 SvrHost SvrHost_run: message received procId=0 15 SvrHost SvrHost_run: message received procId=0 16 SvrHost SvrHost_run: message received procId=0 17 SvrHost SvrHost_run: message received procId=0 42 AppHost AppHost_run: ping procId=1 44 AppHost AppHost_run: ping procId=1 46 AppHost AppHost_run: ping procId=1 48 AppHost AppHost_run: ping procId=1 50 AppHost AppHost_run: ping procId=1 43 AppHost AppHost_run: ack received procId=1 45 AppHost AppHost_run: ack received procId=1 47 AppHost AppHost_run: ack received procId=1 49 AppHost AppHost_run: ack received procId=1 51 AppHost AppHost_run: ack received procId=1 18 SvrHost SvrHost_run: message received procId=1 19 SvrHost SvrHost_run: message received procId=1 20 SvrHost SvrHost_run: message received procId=1 21 SvrHost SvrHost_run: message received procId=1 22 SvrHost SvrHost_run: message received procId=1 52 AppHost AppHost_run: ping procId=2 55 AppHost AppHost_run: ping procId=2 58 AppHost AppHost_run: ping procId=2 61 AppHost AppHost_run: ping procId=2 64 AppHost AppHost_run: ping procId=2 54 AppHost AppHost_run: ack received procId=2 57 AppHost AppHost_run: ack received procId=2 60 AppHost AppHost_run: ack received procId=2 63 AppHost AppHost_run: ack received procId=2 66 AppHost AppHost_run: ack received procId=2 53 SvrHost SvrHost_run: message received procId=2 56 SvrHost SvrHost_run: message received procId=2 59 SvrHost SvrHost_run: message received procId=2 62 SvrHost SvrHost_run: message received procId=2 65 SvrHost SvrHost_run: message received procId=2 67 AppHost AppHost_run: ping procId=3 69 AppHost AppHost_run: ping procId=3 71 AppHost AppHost_run: ping procId=3 73 AppHost AppHost_run: ping procId=3 75 AppHost AppHost_run: ping procId=3 68 AppHost AppHost_run: ack received procId=3 70 AppHost AppHost_run: ack received procId=3 72 AppHost AppHost_run: ack received procId=3 74 AppHost AppHost_run: ack received procId=3 76 AppHost AppHost_run: ack received procId=3 23 SvrHost SvrHost_run: message received procId=3 24 SvrHost SvrHost_run: message received procId=3 25 SvrHost SvrHost_run: message received procId=3 26 SvrHost SvrHost_run: message received procId=3 27 SvrHost SvrHost_run: message received procId=3 29 AppHost AppHost_setup: slave is ready 30 AppHost <-- AppHost_setup: 31 AppHost --> AppHost_run: 77 AppHost <-- AppHost_run: 0 78 AppHost --> AppHost_destroy: 79 AppHost <-- AppHost_destroy: status=0 80 xdc.runtime.Main <-- MainHost_appTskFxn: 0 81 xdc.runtime.Main MainHost_done:r| r} }r~ (jYUjZjx ubaubeubjbj/jdUsystem_messager jf}r (jh]UlevelKjk]jj]Usourcejcji]jn]UlineKUtypeUINFOr ujpKijqhjr]r j)r }r (jYX:Enumerated list start value not ordinal-1: "3" (ordinal 3)jf}r (jh]ji]jj]jk]jn]ujZjWjr]r j{X:Enumerated list start value not ordinal-1: "3" (ordinal 3)r r }r (jYUjZj ubajdjubaubjV)r }r (jYUjZj\jbj/jdj jf}r (jh]UlevelKjk]jj]Usourcejcji]jn]UlineKUtypej ujpKnjqhjr]r j)r }r (jYX:Enumerated list start value not ordinal-1: "4" (ordinal 4)jf}r (jh]ji]jj]jk]jn]ujZj jr]r j{X:Enumerated list start value not ordinal-1: "4" (ordinal 4)r r }r (jYUjZj ubajdjubaubjV)r }r (jYUjZj\jbj/jdj jf}r (jh]UlevelKjk]jj]Usourcejcji]jn]UlineKUtypej ujpKjqhjr]r j)r }r (jYX<Enumerated list start value not ordinal-1: "13" (ordinal 13)jf}r (jh]ji]jj]jk]jn]ujZj jr]r j{X<Enumerated list start value not ordinal-1: "13" (ordinal 13)r r }r (jYUjZj ubajdjubaubjV)r }r (jYUjZj\jbj/jdj jf}r (jh]UlevelKjk]jj]Usourcejcji]jn]UlineKUtypej ujpKjqhjr]r j)r }r (jYX:Enumerated list start value not ordinal-1: "3" (ordinal 3)jf}r (jh]ji]jj]jk]jn]ujZj jr]r j{X:Enumerated list start value not ordinal-1: "3" (ordinal 3)r r }r (jYUjZj ubajdjubaubjV)r }r (jYUjZj\jbj/jdj jf}r (jh]UlevelKjk]jj]Usourcejcji]jn]UlineKUtypej ujpKjqhjr]r j)r }r (jYX:Enumerated list start value not ordinal-1: "4" (ordinal 4)jf}r (jh]ji]jj]jk]jn]ujZj jr]r j{X:Enumerated list start value not ordinal-1: "4" (ordinal 4)r r }r (jYUjZj ubajdjubaubjV)r }r (jYUjZj\jbj/jdj jf}r (jh]UlevelKjk]jj]Usourcejcji]jn]UlineKUtypej ujpKjqhjr]r j)r }r (jYX<Enumerated list start value not ordinal-1: "13" (ordinal 13)jf}r (jh]ji]jj]jk]jn]ujZj jr]r j{X<Enumerated list start value not ordinal-1: "13" (ordinal 13)r r }r (jYUjZj ubajdjubaubjV)r }r (jYUjZj\jbj/jdj jf}r (jh]UlevelKjk]jj]Usourcejcji]jn]UlineKUtypej ujpKjqhjr]r j)r }r (jYX<Enumerated list start value not ordinal-1: "13" (ordinal 13)jf}r (jh]ji]jj]jk]jn]ujZj jr]r j{X<Enumerated list start value not ordinal-1: "13" (ordinal 13)r r }r (jYUjZj ubajdjubaubjV)r }r (jYUjZj\jbj/jdj jf}r (jh]UlevelKjk]jj]Usourcejcji]jn]UlineKUtypej ujpMjqhjr]r j)r }r (jYX:Enumerated list start value not ordinal-1: "3" (ordinal 3)jf}r (jh]ji]jj]jk]jn]ujZj jr]r j{X:Enumerated list start value not ordinal-1: "3" (ordinal 3)r r }r (jYUjZj ubajdjubaubjV)r }r (jYUjZj\jbj/jdj jf}r (jh]UlevelKjk]jj]Usourcejcji]jn]UlineKUtypej ujpM3jqhjr]r j)r }r (jYX<Enumerated list start value not ordinal-1: "15" (ordinal 15)jf}r (jh]ji]jj]jk]jn]ujZj jr]r j{X<Enumerated list start value not ordinal-1: "15" (ordinal 15)r r }r (jYUjZj ubajdjubaubjV)r }r (jYUjZj\jbXZinternal padding after source/rtos/How_to_Guides/Target/Run_IPC_Examples_on_AM572x.rst.incr jdj jf}r (jh]UlevelKjk]jj]Usourcej/ji]jn]UlineMUtypeUERRORr ujpMjqhjr]r (j)r }r (jYX;Content block expected for the "raw" directive; none found.jf}r (jh]ji]jj]jk]jn]ujZj jr]r j{X;Content block expected for the "raw" directive; none found.r r }r (jYUjZj ubajdjubj)r }r (jYX.. raw:: html jf}r (jjjk]jj]jh]ji]jn]ujZj jr]r j{X.. raw:: html r r }r (jYUjZj ubajdjubeubjV)r }r (jYUjf}r (jh]UlevelKjk]jj]r jaUsourcejcji]jn]UlineKUtypeUWARNINGr ujZjjr]r j)r }r (jYX<Duplicate explicit target name: "ipc-message-queue-example".jf}r (jh]ji]jj]jk]jn]ujZj jr]r j{X<Duplicate explicit target name: "ipc-message-queue-example".rr}r(jYUjZj ubajdjubajdj ubjV)r}r(jYUjZjjbjjdj jf}r(jh]UlevelKjk]jj]Usourcejji]jn]UlineK'Utypej ujpK&jqhjr]rj)r}r(jYX?Enumerated list ends without a blank line; unexpected unindent.jf}r (jh]ji]jj]jk]jn]ujZjjr]r j{X?Enumerated list ends without a blank line; unexpected unindent.r r }r (jYUjZjubajdjubaubjV)r}r(jYUjZjjbjjdj jf}r(jh]UlevelKjk]jj]Usourcejcji]jn]UlineKUtypej ujpK*jqhjr]rj)r}r(jYX:Enumerated list start value not ordinal-1: "2" (ordinal 2)jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X:Enumerated list start value not ordinal-1: "2" (ordinal 2)rr}r(jYUjZjubajdjubaubjV)r}r(jYUjZjjbjjdj jf}r(jh]UlevelKjk]jj]Usourcejcji]jn]UlineKUtypej ujpKjqhjr]rj)r}r(jYX:Enumerated list start value not ordinal-1: "2" (ordinal 2)jf}r(jh]ji]jj]jk]jn]ujZjjr]r j{X:Enumerated list start value not ordinal-1: "2" (ordinal 2)r!r"}r#(jYUjZjubajdjubaubjV)r$}r%(jYUjZjjbjjdj jf}r&(jh]UlevelKjk]jj]Usourcejcji]jn]UlineKUtypej ujpKjqhjr]r'j)r(}r)(jYX:Enumerated list start value not ordinal-1: "3" (ordinal 3)jf}r*(jh]ji]jj]jk]jn]ujZj$jr]r+j{X:Enumerated list start value not ordinal-1: "3" (ordinal 3)r,r-}r.(jYUjZj(ubajdjubaubjV)r/}r0(jYUjZjjbjjdj jf}r1(jh]UlevelKjk]jj]Usourcejcji]jn]UlineKUtypej ujpKjqhjr]r2j)r3}r4(jYX:Enumerated list start value not ordinal-1: "4" (ordinal 4)jf}r5(jh]ji]jj]jk]jn]ujZj/jr]r6j{X:Enumerated list start value not ordinal-1: "4" (ordinal 4)r7r8}r9(jYUjZj3ubajdjubaubjV)r:}r;(jYUjZjjbjjdj jf}r<(jh]UlevelKjk]jj]Usourcejcji]jn]UlineKUtypej ujpK$jqhjr]r=j)r>}r?(jYX:Enumerated list start value not ordinal-1: "5" (ordinal 5)jf}r@(jh]ji]jj]jk]jn]ujZj:jr]rAj{X:Enumerated list start value not ordinal-1: "5" (ordinal 5)rBrC}rD(jYUjZj>ubajdjubaubjV)rE}rF(jYUjZjjbjjdj jf}rG(jh]UlevelKjk]jj]Usourcejcji]jn]UlineKUtypej ujpK(jqhjr]rHj)rI}rJ(jYX:Enumerated list start value not ordinal-1: "6" (ordinal 6)jf}rK(jh]ji]jj]jk]jn]ujZjEjr]rLj{X:Enumerated list start value not ordinal-1: "6" (ordinal 6)rMrN}rO(jYUjZjIubajdjubaubjV)rP}rQ(jYUjZjjbjjdj jf}rR(jh]UlevelKjk]jj]Usourcejcji]jn]UlineKUtypej ujpK,jqhjr]rSj)rT}rU(jYX:Enumerated list start value not ordinal-1: "7" (ordinal 7)jf}rV(jh]ji]jj]jk]jn]ujZjPjr]rWj{X:Enumerated list start value not ordinal-1: "7" (ordinal 7)rXrY}rZ(jYUjZjTubajdjubaubjV)r[}r\(jYUjZjwjbjjdj jf}r](jh]UlevelKjk]jj]Usourcejcji]jn]UlineKUtypej ujpKsjqhjr]r^j)r_}r`(jYX:Enumerated list start value not ordinal-1: "2" (ordinal 2)jf}ra(jh]ji]jj]jk]jn]ujZj[jr]rbj{X:Enumerated list start value not ordinal-1: "2" (ordinal 2)rcrd}re(jYUjZj_ubajdjubaubjV)rf}rg(jYUjZjjbjjdj jf}rh(jh]UlevelKjk]rijajj]rjjaUsourcejji]jn]UlineK Utypej ujpKjqhjr]rkj)rl}rm(jYX0Inline emphasis start-string without end-string.jf}rn(jh]ji]jj]jk]jn]ujZjfjr]roj{X0Inline emphasis start-string without end-string.rprq}rr(jYUjZjlubajdjubaubjV)rs}rt(jYUjf}ru(jh]UlevelKjk]rvjajj]rwjaUsourcejji]jn]UlineKUtypej ujZjjr]rxj)ry}rz(jYX0Inline emphasis start-string without end-string.jf}r{(jh]ji]jj]jk]jn]ujZjsjr]r|j{X0Inline emphasis start-string without end-string.r}r~}r(jYUjZjyubajdjubajdj ubjV)r}r(jYUjf}r(jh]UlevelKjk]rj&ajj]rj%aUsourcejji]jn]UlineKUtypej ujZjjr]rj)r}r(jYX0Inline emphasis start-string without end-string.jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X0Inline emphasis start-string without end-string.rr}r(jYUjZjubajdjubajdj ubjV)r}r(jYUjf}r(jh]UlevelKjk]rj:ajj]rj9aUsourcejji]jn]UlineKUtypej ujZj-jr]rj)r}r(jYX0Inline emphasis start-string without end-string.jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X0Inline emphasis start-string without end-string.rr}r(jYUjZjubajdjubajdj ubjV)r}r(jYUjf}r(jh]UlevelKjk]rjNajj]rjMaUsourcejji]jn]UlineKUtypej ujZjAjr]rj)r}r(jYX0Inline emphasis start-string without end-string.jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X0Inline emphasis start-string without end-string.rr}r(jYUjZjubajdjubajdj ubjV)r}r(jYUjf}r(jh]UlevelKjk]rjvajj]rjuaUsourcejji]jn]UlineK Utypej ujZjfjr]rj)r}r(jYX0Inline emphasis start-string without end-string.jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X0Inline emphasis start-string without end-string.rr}r(jYUjZjubajdjubajdj ubjV)r}r(jYUjZjjbjjdj jf}r(jh]UlevelKjk]rjajj]rjaUsourcejji]jn]UlineK%Utypej ujpK)jqhjr]rj)r}r(jYX0Inline emphasis start-string without end-string.jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X0Inline emphasis start-string without end-string.rr}r(jYUjZjubajdjubaubjV)r}r(jYUjf}r(jh]UlevelKjk]rjajj]rjaUsourcejji]jn]UlineK+Utypej ujZjjr]rj)r}r(jYX0Inline emphasis start-string without end-string.jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X0Inline emphasis start-string without end-string.rr}r(jYUjZjubajdjubajdj ubjV)r}r(jYUjf}r(jh]UlevelKjk]rjajj]rjaUsourcejji]jn]UlineK+Utypej ujZjjr]rj)r}r(jYX0Inline emphasis start-string without end-string.jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X0Inline emphasis start-string without end-string.rr}r(jYUjZjubajdjubajdj ubjV)r}r(jYUjf}r(jh]UlevelKjk]rjajj]rjaUsourcejji]jn]UlineK+Utypej ujZjjr]rj)r}r(jYX0Inline emphasis start-string without end-string.jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X0Inline emphasis start-string without end-string.rr}r(jYUjZjubajdjubajdj ubjV)r}r(jYUjf}r(jh]UlevelKjk]rjajj]rjaUsourcejji]jn]UlineK+Utypej ujZjjr]rj)r}r(jYX0Inline emphasis start-string without end-string.jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X0Inline emphasis start-string without end-string.rr}r(jYUjZjubajdjubajdj ubjV)r}r(jYUjZj[)r}r(jYUjZj[)r}r(jYUjZj[)r}r(jYUjZj[)r}r(jYUjZj[)r}r(jYUjZhjbjcjdjejf}r(jh]ji]jj]jk]rUhostrajn]rhaujpKjqhjr]r(jt)r}r(jYXHostrjZjjbjcjdjxjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r j{XHostr r }r (jYjjZjubaubjj[)r}r(jYUjZjjbjcjdjejf}r(jh]ji]jj]jk]rUti-rtos-basicsrajn]rhaujpK7jqhjr]r(jt)r}r(jYXTI RTOS BasicsrjZjjbjcjdjxjf}r(jh]ji]jj]jk]jn]ujpK7jqhjr]rj{XTI RTOS Basicsrr}r(jYjjZjubaubj[)r}r(jYUjZjjbjXDsource/rtos/How_to_Guides/Host/Setup/TI_RTOS_Tips_and_Tricks.rst.incrr }r!bjdjejf}r"(jh]ji]jj]jk]r#Uti-rtos-tips-tricksr$ajn]r%j aujpKjqhjr]r&(jt)r'}r((jYXTI RTOS Tips & Tricksr)jZjjbj jdjxjf}r*(jh]ji]jj]jk]jn]ujpKjqhjr]r+j{XTI RTOS Tips & Tricksr,r-}r.(jYj)jZj'ubaubj)r/}r0(jYXShttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS:_TI_RTOS_Tips_And_TricksjZjjbj jdjjf}r1(jjjk]jj]jh]ji]jn]ujpKjqhjr]r2j{XShttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS:_TI_RTOS_Tips_And_Tricksr3r4}r5(jYUjZj/ubaubj[)r6}r7(jYUjKjZjjbj jdjejf}r8(jh]r9X descriptionr:aji]jj]jk]r;U descriptionr<ajn]ujpKjqhjr]r=(jt)r>}r?(jYX Descriptionr@jZj6jbj jdjxjf}rA(jh]ji]jj]jk]jn]ujpKjqhjr]rBj{X DescriptionrCrD}rE(jYj@jZj>ubaubj)rF}rG(jYX6The intent of this article is to address common issues that TI RTOS users may run into while configuring SYSBIOS, XDCTools or working with RTSC packages in general on DSP and ARM devices. This is meant to provide insight into build and configuration issue nd must be used as an addendum document by Processor SDK USer to the `SYSBIOS FAQs `__ and `XDCtools/RTSC documentation `__ and `TI RTOS Training `__rHjZj6jbj jdjjf}rI(jh]ji]jj]jk]jn]ujpK jqhjr]rJ(j{XFThe intent of this article is to address common issues that TI RTOS users may run into while configuring SYSBIOS, XDCTools or working with RTSC packages in general on DSP and ARM devices. This is meant to provide insight into build and configuration issue nd must be used as an addendum document by Processor SDK USer to the rKrL}rM(jYXFThe intent of this article is to address common issues that TI RTOS users may run into while configuring SYSBIOS, XDCTools or working with RTSC packages in general on DSP and ARM devices. This is meant to provide insight into build and configuration issue nd must be used as an addendum document by Processor SDK USer to the jZjFubj)rN}rO(jYXH`SYSBIOS FAQs `__jf}rP(UnameX SYSBIOS FAQsjX5http://processors.wiki.ti.com/index.php/SYS/BIOS_FAQsjk]jj]jh]ji]jn]ujZjFjr]rQj{X SYSBIOS FAQsrRrS}rT(jYUjZjNubajdjubj{X and rUrV}rW(jYX and jZjFubj)rX}rY(jYXX`XDCtools/RTSC documentation `__jf}rZ(UnameXXDCtools/RTSC documentationjX6http://rtsc.eclipse.org/docs-tip/XDCtools_User's_Guidejk]jj]jh]ji]jn]ujZjFjr]r[j{XXDCtools/RTSC documentationr\r]}r^(jYUjZjXubajdjubj{X and r_r`}ra(jYX and jZjFubj)rb}rc(jYXF`TI RTOS Training `__jf}rd(UnameXTI RTOS TrainingjX/https://training.ti.com/ti-rtos-workshop-seriesjk]jj]jh]ji]jn]ujZjFjr]rej{XTI RTOS Trainingrfrg}rh(jYUjZjbubajdjubeubeubj[)ri}rj(jYUjZjjbj jdjejf}rk(jh]ji]jj]jk]rlU/rtsc-diagnostics-understanding-xdc-build-errorsrmajn]rnj aujpK jqhjr]ro(jt)rp}rq(jYX0RTSC Diagnostics: Understanding XDC build errorsrrjZjijbj jdjxjf}rs(jh]ji]jj]jk]jn]ujpK jqhjr]rtj{X0RTSC Diagnostics: Understanding XDC build errorsrurv}rw(jYjrjZjpubaubj)rx}ry(jYXSome of the commonly observed XDC errors have been shown below. We try to explain how to understand and take corrective action.rzjZjijbj jdjjf}r{(jh]ji]jj]jk]jn]ujpK jqhjr]r|j{XSome of the commonly observed XDC errors have been shown below. We try to explain how to understand and take corrective action.r}r~}r(jYjzjZjxubaubj[)r}r(jYUjZjijbj jdjejf}r(jh]ji]jj]jk]rUHxdc-tools-configuro-can-t-locate-the-package-package-name-along-the-pathrajn]rjaujpKjqhjr]r(jt)r}r(jYXQxdc.tools.configuro: can't locate the package 'Package Name' along the path: ...rjZjjbj jdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XQxdc.tools.configuro: can't locate the package 'Package Name' along the path: ...rr}r(jYjjZjubaubj)r}r(jYX^This indicates that one of the packages that you linked in your BIOS configuration, can`t be located under XDCPATH. The XDC tools uses XDC paths like library search path, so if you run into this issue check that all the component packages have been added to XDCPATH and there is no typo or non-existent paths that you have added to this variable. TI RTSC packages usually have the name ti.. The packages are named to also sometimes helps locate the package inside the component. For example '''ti.platforms.evmAM335x''' is located under BIOS_INSTALL_PATH/packages/'''ti/platforms/evmAM335x'''rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X^This indicates that one of the packages that you linked in your BIOS configuration, can`t be located under XDCPATH. The XDC tools uses XDC paths like library search path, so if you run into this issue check that all the component packages have been added to XDCPATH and there is no typo or non-existent paths that you have added to this variable. TI RTSC packages usually have the name ti.. The packages are named to also sometimes helps locate the package inside the component. For example '''ti.platforms.evmAM335x''' is located under BIOS_INSTALL_PATH/packages/'''ti/platforms/evmAM335x'''rr}r(jYjjZjubaubj)r}r(jYXFor example if you are using packages from PDK (SOC driver packages)and BIOS (TI RTOS kernel), IPC (Interprocessor Communication) and NDK (Network development kit) then your XDCPATH needs to have following:rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XFor example if you are using packages from PDK (SOC driver packages)and BIOS (TI RTOS kernel), IPC (Interprocessor Communication) and NDK (Network development kit) then your XDCPATH needs to have following:rr}r(jYjjZjubaubjC)r}r(jYUjZjjbj jdj`jf}r(jGX*jk]jj]jh]ji]jn]ujpKjqhjr]r(j/)r}r(jYXBIOS_INSTALL_PATH/packages jZjjbj jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXBIOS_INSTALL_PATH/packagesrjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XBIOS_INSTALL_PATH/packagesrr}r(jYjjZjubaubaubj/)r}r(jYXPDK_INSTALL_PATH/packages jZjjbj jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXPDK_INSTALL_PATH/packagesrjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XPDK_INSTALL_PATH/packagesrr}r(jYjjZjubaubaubj/)r}r(jYXIPC_INSTALL_PATH/packages jZjjbj jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXIPC_INSTALL_PATH/packagesrjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XIPC_INSTALL_PATH/packagesrr}r(jYjjZjubaubaubj/)r}r(jYXNDK_INSTALL_PATH/packages jZjjbj jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXNDK_INSTALL_PATH/packagesrjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XNDK_INSTALL_PATH/packagesrr}r(jYjjZjubaubaubeubeubj[)r}r(jYUjZjijbj jdjejf}r(jh]ji]jj]jk]rUJxdc-cfg-sourcedir-build-of-generated-source-libraries-failed-exit-status-2rajn]rhvaujpK jqhjr]r(jt)r}r(jYXPxdc.cfg.SourceDir : Build of generated source libraries failed: exit status = 2:rjZjjbj jdjxjf}r(jh]ji]jj]jk]jn]ujpK jqhjr]rj{XPxdc.cfg.SourceDir : Build of generated source libraries failed: exit status = 2:rr}r(jYjjZjubaubj)r}r(jYX>A couple of different reasons could trigger this type of errorrjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpK"jqhjr]rj{X>A couple of different reasons could trigger this type of errorrr}r(jYjjZjubaubjC)r}r(jYUjZjjbj jdj`jf}r(jGX*jk]jj]jh]ji]jn]ujpK$jqhjr]r(j/)r}r(jYXuMake sure there are no whitespaces or non-ASCII characters in any paths referenced by the build tools. In other words, make sure all software packages are installed in paths without spaces, and workspace and project names also do not have spaces or non-ASCII characters. We use gmake to build makefiles, and gmake doesn't deal well with spaces in directory and file names. jZjjbj jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXtMake sure there are no whitespaces or non-ASCII characters in any paths referenced by the build tools. In other words, make sure all software packages are installed in paths without spaces, and workspace and project names also do not have spaces or non-ASCII characters. We use gmake to build makefiles, and gmake doesn't deal well with spaces in directory and file names.rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpK$jr]rj{XtMake sure there are no whitespaces or non-ASCII characters in any paths referenced by the build tools. In other words, make sure all software packages are installed in paths without spaces, and workspace and project names also do not have spaces or non-ASCII characters. We use gmake to build makefiles, and gmake doesn't deal well with spaces in directory and file names.rr}r(jYjjZjubaubaubj/)r}r(jYXqTake a close look at the CCS build console and ensure that the sh.exe used for the build is the one from the CCS directory. Also check your system PATH variable and see if there is another sh.exe (or gmake.exe) in your system PATH earlier than the one from the CCS installation. If there is one, then that will be used for the build and could cause build errors such as this. Some toolchains that are known to include sh.exe and could cause a conflict are Cygwin, WinAVR, Yagarto. In this case, remove those conflicting tools from the system PATH or modify the PATH so that the sh.exe and gmake.exe from CCS are seen first. jZjjbj jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXpTake a close look at the CCS build console and ensure that the sh.exe used for the build is the one from the CCS directory. Also check your system PATH variable and see if there is another sh.exe (or gmake.exe) in your system PATH earlier than the one from the CCS installation. If there is one, then that will be used for the build and could cause build errors such as this. Some toolchains that are known to include sh.exe and could cause a conflict are Cygwin, WinAVR, Yagarto. In this case, remove those conflicting tools from the system PATH or modify the PATH so that the sh.exe and gmake.exe from CCS are seen first.rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpK&jr]rj{XpTake a close look at the CCS build console and ensure that the sh.exe used for the build is the one from the CCS directory. Also check your system PATH variable and see if there is another sh.exe (or gmake.exe) in your system PATH earlier than the one from the CCS installation. If there is one, then that will be used for the build and could cause build errors such as this. Some toolchains that are known to include sh.exe and could cause a conflict are Cygwin, WinAVR, Yagarto. In this case, remove those conflicting tools from the system PATH or modify the PATH so that the sh.exe and gmake.exe from CCS are seen first.rr}r(jYjjZjubaubaubj/)r}r(jYXAnother source of problems related to sh.exe runnig Windows 10 may be Windows Defender. In "Windows Defender Security Centre", "App and browser control", "Exploit protection settings" one can add exceptions under "Program settings". Adding a rule for "sh.exe" to disable/override "Force randomisation for images (Mandatory ASLR)", "Randomise memory allocations (Bottom-up ASLR)", "Validate stack integrity (StackPivot)". jZjjbj jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYXAnother source of problems related to sh.exe runnig Windows 10 may be Windows Defender. In "Windows Defender Security Centre", "App and browser control", "Exploit protection settings" one can add exceptions under "Program settings". Adding a rule for "sh.exe" to disable/override "Force randomisation for images (Mandatory ASLR)", "Randomise memory allocations (Bottom-up ASLR)", "Validate stack integrity (StackPivot)".r jZjjbj jdjjf}r (jh]ji]jj]jk]jn]ujpK(jr]rj{XAnother source of problems related to sh.exe runnig Windows 10 may be Windows Defender. In "Windows Defender Security Centre", "App and browser control", "Exploit protection settings" one can add exceptions under "Program settings". Adding a rule for "sh.exe" to disable/override "Force randomisation for images (Mandatory ASLR)", "Randomise memory allocations (Bottom-up ASLR)", "Validate stack integrity (StackPivot)".rr}r(jYj jZj ubaubaubeubeubj[)r}r(jYUjZjijbj jdjejf}r(jh]ji]jj]jk]rU/xdc-tools-configuro-missing-input-config-scriptrajn]rh&aujpK-jqhjr]r(jt)r}r(jYX0xdc.tools.configuro: missing input config scriptrjZjjbj jdjxjf}r(jh]ji]jj]jk]jn]ujpK-jqhjr]rj{X0xdc.tools.configuro: missing input config scriptrr}r (jYjjZjubaubj)r!}r"(jYX+The XDCtools build command should normally have the configuration script (.cfg file) passed at the end of the command. If the .cfg is not getting passed correctly, then this message will appear in the CCS build console. This error will then result in other compiler errors further down in the build.r#jZjjbj jdjjf}r$(jh]ji]jj]jk]jn]ujpK/jqhjr]r%j{X+The XDCtools build command should normally have the configuration script (.cfg file) passed at the end of the command. If the .cfg is not getting passed correctly, then this message will appear in the CCS build console. This error will then result in other compiler errors further down in the build.r&r'}r((jYj#jZj!ubaubj)r)}r*(jYXYou can confirm if the root cause is the .cfg file not getting passed correctly by looking at the subdir_rules.mk file in the directory Debug (or Release) in your project. The command line that runs configuro usually looks like this:
::jZjjbj jdjjf}r+(jh]ji]jj]jk]jn]ujpK1jqhjr]r,j{XYou can confirm if the root cause is the .cfg file not getting passed correctly by looking at the subdir_rules.mk file in the directory Debug (or Release) in your project. The command line that runs configuro usually looks like this:
r-r.}r/(jYXYou can confirm if the root cause is the .cfg file not getting passed correctly by looking at the subdir_rules.mk file in the directory Debug (or Release) in your project. The command line that runs configuro usually looks like this:
jZj)ubaubj)r0}r1(jYX"C:/ti/xdctools_3_xx_xx_xx/xs" --xdcpath="..." xdc.tools.configuro -o configPkg -t ti.targets.elf.C674 -p ti.platforms.evm6747 -r release -c "C:/ti/ccsv5/tools/compiler/c6000_x.x.x" --compileOptions "-g --optimize_with_debug" "$<"jZjjbj jdjjf}r2(jjjk]jj]jh]ji]jn]ujpMjqhjr]r3j{X"C:/ti/xdctools_3_xx_xx_xx/xs" --xdcpath="..." xdc.tools.configuro -o configPkg -t ti.targets.elf.C674 -p ti.platforms.evm6747 -r release -c "C:/ti/ccsv5/tools/compiler/c6000_x.x.x" --compileOptions "-g --optimize_with_debug" "$<"r4r5}r6(jYUjZj0ubaubjZ)r7}r8(jYUjZjjbj jdj]jf}r9(jh]ji]jj]jk]jn]ujpK7jqhjr]r:j`)r;}r<(jYUjcKjZj7jbj jdjpjf}r=(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubj[)r>}r?(jYUjZjijbj jdjejf}r@(jh]ji]jj]jk]rAUschema-files-not-foundrBajn]rChaujpK:jqhjr]rD(jt)rE}rF(jYXSchema files not foundrGjZj>jbj jdjxjf}rH(jh]ji]jj]jk]jn]ujpK:jqhjr]rIj{XSchema files not foundrJrK}rL(jYjGjZjEubaubj)rM}rN(jYXUsually after creating a RTSC package, developers are supposed to run xdc release to generate the package that contains the .sch files but if you accidentally delete the package or the developers requires xdc release to be run in user environment, you can run into this issue. This issue can be resolved by adding XDCtools to your environment PATH variable and running the command xdc releaserOjZj>jbj jdjjf}rP(jh]ji]jj]jk]jn]ujpK xdc releasejZj>jbj jdjjf}rW(jjjk]jj]jh]ji]jn]ujpMjqhjr]rXj{X-set PATH=$PATH; xdc releaserYrZ}r[(jYUjZjUubaubjZ)r\}r](jYUjZj>jbj jdj]jf}r^(jh]ji]jj]jk]jn]ujpKCjqhjr]r_j`)r`}ra(jYUjcKjZj\jbj jdjpjf}rb(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)rc}rd(jYXJDetailed list of '''XDC Error codes''' and Troubleshoot can be found here:rejZj>jbj jdjjf}rf(jh]ji]jj]jk]jn]ujpKEjqhjr]rgj{XJDetailed list of '''XDC Error codes''' and Troubleshoot can be found here:rhri}rj(jYjejZjcubaubjC)rk}rl(jYUjZj>jbj jdj`jf}rm(jGX*jk]jj]jh]ji]jn]ujpKGjqhjr]rn(j/)ro}rp(jYXP`XDCtools Error Codes `__rqjZjkjbj jdj2jf}rr(jh]ji]jj]jk]jn]ujpNjqhjr]rsj)rt}ru(jYjqjZjojbj jdjjf}rv(jh]ji]jj]jk]jn]ujpKGjr]rwj)rx}ry(jYjqjf}rz(UnameXXDCtools Error CodesjX5http://rtsc.eclipse.org/docs-tip/XDCtools_Error_Codesjk]jj]jh]ji]jn]ujZjtjr]r{j{XXDCtools Error Codesr|r}}r~(jYUjZjxubajdjubaubaubj/)r}r(jYXJ`Trouble Shooting `__ jZjkjbj jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXH`Trouble Shooting `__rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKHjr]rj)r}r(jYjjf}r(UnameXTrouble ShootingjX1http://rtsc.eclipse.org/docs-tip/Trouble_Shootingjk]jj]jh]ji]jn]ujZjjr]rj{XTrouble Shootingrr}r(jYUjZjubajdjubaubaubeubeubeubj[)r}r(jYUjZjjbj jdjejf}r(jh]ji]jj]jk]rUti-rtos-platform-configurationrajn]rhaujpKLjqhjr]r(jt)r}r(jYXTI RTOS Platform configurationrjZjjbj jdjxjf}r(jh]ji]jj]jk]jn]ujpKLjqhjr]rj{XTI RTOS Platform configurationrr}r(jYjjZjubaubj[)r}r(jYUjZjjbj jdjejf}r(jh]ji]jj]jk]rUYwhere-does-ti-rtos-application-get-the-platform-definition-and-memory-sections-on-the-socrajn]rh9aujpKOjqhjr]r(jt)r}r(jYXYWhere does TI RTOS application get the Platform definition and memory sections on the SOCrjZjjbj jdjxjf}r(jh]ji]jj]jk]jn]ujpKOjqhjr]rj{XYWhere does TI RTOS application get the Platform definition and memory sections on the SOCrr}r(jYjjZjubaubj)r}r(jYXWhen creating a TI RTOS project, the user is required to specify the Platform and target core as part of their RTSC setup as shown below. This shows an example that is created for evmAM335x platform.rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKQjqhjr]rj{XWhen creating a TI RTOS project, the user is required to specify the Platform and target core as part of their RTSC setup as shown below. This shows an example that is created for evmAM335x platform.rr}r(jYjjZjubaubjB)r}r(jYXE.. Image:: ../images/Platfrom_configuration.png :scale: 50 % jZjjbj jdjEjf}r(UscaleK2UuriX)rtos/../images/Platfrom_configuration.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpNjqhjr]ubj)r}r(jYXSelection of the platform essentially tell the build tools that the platform defintion should be picked up from the platform for evmAM335x from the directory path bios_x_xx_xx_xx\packages\ti\platforms\evmAM3359. If you open the Platform.xdc file under the folder path, you can see the default settings provided for this platform. This file combines the baseline AM335x SOC definition under bios_x_xx_xx_xx\packages\ti\catalog\arm\cortexa with the board specific setting like clockrate, DDR memory range.rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKVjqhjr]rj{XSelection of the platform essentially tell the build tools that the platform defintion should be picked up from the platform for evmAM335x from the directory path bios_x_xx_xx_xxpackagestiplatformsevmAM3359. If you open the Platform.xdc file under the folder path, you can see the default settings provided for this platform. This file combines the baseline AM335x SOC definition under bios_x_xx_xx_xxpackagesticatalogarmcortexa with the board specific setting like clockrate, DDR memory range.rr}r(jYXSelection of the platform essentially tell the build tools that the platform defintion should be picked up from the platform for evmAM335x from the directory path bios_x_xx_xx_xx\packages\ti\platforms\evmAM3359. If you open the Platform.xdc file under the folder path, you can see the default settings provided for this platform. This file combines the baseline AM335x SOC definition under bios_x_xx_xx_xx\packages\ti\catalog\arm\cortexa with the board specific setting like clockrate, DDR memory range.jZjubaubeubj[)r}r(jYUjZjjbj jdjejf}r(jh]ji]jj]jk]rUQhow-to-create-custom-platform-like-ddrless-platforms-to-use-with-ti-rtos-projectsrajn]rhaujpKYjqhjr]r(jt)r}r(jYXQHow to create custom platform like DDRless platforms to use with TI RTOS projectsrjZjjbj jdjxjf}r(jh]ji]jj]jk]jn]ujpKYjqhjr]rj{XQHow to create custom platform like DDRless platforms to use with TI RTOS projectsrr}r(jYjjZjubaubj)r}r(jYXAt some point in the application development process, most customers build their own boards, choosing a TI device and adding custom external memory. You will also need to create your own platform if any of the following items are true: * You want to customize cache sizes. * You want to manually override the default section placement. * You want application to run from on chip device memory.rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpK[jqhjr]rj{XAt some point in the application development process, most customers build their own boards, choosing a TI device and adding custom external memory. You will also need to create your own platform if any of the following items are true: * You want to customize cache sizes. * You want to manually override the default section placement. * You want application to run from on chip device memory.rr}r(jYjjZjubaubj)r}r(jYXFor such custom boards you will need to create a platform using the platform wizard. The platform wizard is a GUI tool that allows you to easily create a custom platform. Creating a custom platform gives you a lot of flexibility in terms of defining the memory map and selecting default memory segments for section placement. This has been described in detail in following User guides and training links:rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKajqhjr]rj{XFor such custom boards you will need to create a platform using the platform wizard. The platform wizard is a GUI tool that allows you to easily create a custom platform. Creating a custom platform gives you a lot of flexibility in terms of defining the memory map and selecting default memory segments for section placement. This has been described in detail in following User guides and training links:rr}r(jYjjZjubaubjC)r}r(jYUjZjjbj jdj`jf}r(jGX*jk]jj]jh]ji]jn]ujpKcjqhjr]r(j/)r}r(jYX\`Section 7.2.2 in the TI RTOS User guide `__rjZjjbj jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKcjr]rj)r}r(jYjjf}r(UnameX'Section 7.2.2 in the TI RTOS User guidejX.http://www.ti.com/lit/ug/spruex3q/spruex3q.pdfjk]jj]jh]ji]jn]ujZjjr]rj{X'Section 7.2.2 in the TI RTOS User guiderr}r(jYUjZjubajdjubaubaubj/)r}r(jYX`Section 10.9 of Application development with Processor SDK RTOS `__ jZjjbj jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYX`Section 10.9 of Application development with Processor SDK RTOS `__rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKdjr]rj)r}r(jYjjf}r(UnameX?Section 10.9 of Application development with Processor SDK RTOSjXNhttp://software-dl.ti.com/public/hpmp/software/app_dev_procsdk_rtos/index.htmljk]jj]jh]ji]jn]ujZjjr]rj{X@Section 10.9 of Application development with Processor SDK RTOSrr}r(jYUjZjubajdjubaubaubeubeubj[)r}r(jYUjZjjbj jdjejf}r(jh]ji]jj]jk]rUshow-to-place-code-and-data-sections-in-different-memory-location-than-set-by-default-ti-rtos-platform-configurationr ajn]r haujpKgjqhjr]r (jt)r }r (jYXsHow to place code and data sections in different memory location than set by default TI RTOS platform configurationrjZjjbj jdjxjf}r(jh]ji]jj]jk]jn]ujpKgjqhjr]rj{XsHow to place code and data sections in different memory location than set by default TI RTOS platform configurationrr}r(jYjjZj ubaubj)r}r(jYXUser can place specific code and data sections in desired location by using the following syntax in the configuration (.cfg) ::jZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKijqhjr]rj{X|User can place specific code and data sections in desired location by using the following syntax in the configuration (.cfg)rr}r(jYX|User can place specific code and data sections in desired location by using the following syntax in the configuration (.cfg)jZjubaubj)r}r(jYXProgram.sectMap[".data"] = new Program.SectionSpec(); /* Set the load address for .data section */ Program.sectMap[".data"].loadAddress = 0x82000000; /* Set the run address for .data section */ Program.sectMap[".data"].runAddress = 0x82010000;jZjjbj jdjjf}r(jjjk]jj]jh]ji]jn]ujpMjqhjr]rj{XProgram.sectMap[".data"] = new Program.SectionSpec(); /* Set the load address for .data section */ Program.sectMap[".data"].loadAddress = 0x82000000; /* Set the run address for .data section */ Program.sectMap[".data"].runAddress = 0x82010000;rr }r!(jYUjZjubaubjZ)r"}r#(jYUjZjjbj jdj]jf}r$(jh]ji]jj]jk]jn]ujpKrjqhjr]r%j`)r&}r'(jYUjcKjZj"jbj jdjpjf}r((jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubeubj[)r)}r*(jYUjZjjbj jdjejf}r+(jh]ji]jj]jk]r,Ugeneric-ti-rtos-questionsr-ajn]r.haujpKujqhjr]r/(jt)r0}r1(jYXGeneric TI RTOS questionsr2jZj)jbj jdjxjf}r3(jh]ji]jj]jk]jn]ujpKujqhjr]r4j{XGeneric TI RTOS questionsr5r6}r7(jYj2jZj0ubaubj[)r8}r9(jYUjZj)jbj jdjejf}r:(jh]ji]jj]jk]r;U:what-is-relationship-between-ti-rtos-and-xdctools-and-rtscr<ajn]r=hfaujpKxjqhjr]r>(jt)r?}r@(jYX:What is relationship between TI RTOS and XDCtools and RTSCrAjZj8jbj jdjxjf}rB(jh]ji]jj]jk]jn]ujpKxjqhjr]rCj{X:What is relationship between TI RTOS and XDCtools and RTSCrDrE}rF(jYjAjZj?ubaubj)rG}rH(jYX`SYSBIOS `__ uses underlying technology provided by Real Time Software Components (RTSC). * RTSC is an open-source specification within the Eclipse.org ecosystem for providing reusable software components (called "packages") for use in embedded systems. * XDCtools is the actual product that contains all the tools necessary for you to use the SYS/BIOS components and configure your application. XDCtools is installed as part of Code Composer Studio (CCS). XDCtools is a separate software component provided by Texas Instruments that provides the underlying tooling needed for configuring and building SYS/BIOS, NDK, and UIA.jZj8jbj jdjjf}rI(jh]ji]jj]jk]jn]ujpKzjqhjr]rJ(j)rK}rL(jYXL`SYSBIOS `__jf}rM(UnameXSYSBIOSjX>http://processors.wiki.ti.com/index.php?title=Category:SYSBIOSjk]jj]jh]ji]jn]ujZjGjr]rNj{XSYSBIOSrOrP}rQ(jYUjZjKubajdjubj{Xe uses underlying technology provided by Real Time Software Components (RTSC). * RTSC is an open-source specification within the Eclipse.org ecosystem for providing reusable software components (called "packages") for use in embedded systems. * XDCtools is the actual product that contains all the tools necessary for you to use the SYS/BIOS components and configure your application. XDCtools is installed as part of Code Composer Studio (CCS). XDCtools is a separate software component provided by Texas Instruments that provides the underlying tooling needed for configuring and building SYS/BIOS, NDK, and UIA.rRrS}rT(jYXe uses underlying technology provided by Real Time Software Components (RTSC). * RTSC is an open-source specification within the Eclipse.org ecosystem for providing reusable software components (called "packages") for use in embedded systems. * XDCtools is the actual product that contains all the tools necessary for you to use the SYS/BIOS components and configure your application. XDCtools is installed as part of Code Composer Studio (CCS). XDCtools is a separate software component provided by Texas Instruments that provides the underlying tooling needed for configuring and building SYS/BIOS, NDK, and UIA.jZjGubeubj)rU}rV(jYX:RTSC and XDCtools are important to SYS/BIOS users because:rWjZj8jbj jdjjf}rX(jh]ji]jj]jk]jn]ujpKjqhjr]rYj{X:RTSC and XDCtools are important to SYS/BIOS users because:rZr[}r\(jYjWjZjUubaubjC)r]}r^(jYUjZj8jbj jdj`jf}r_(jGX*jk]jj]jh]ji]jn]ujpKjqhjr]r`(j/)ra}rb(jYX`SYS/BIOS_as_a_set_of_RTSC_packages `__ containing the modules that make up the RTOS. jZj]jbj jdj2jf}rc(jh]ji]jj]jk]jn]ujpNjqhjr]rdj)re}rf(jYX`SYS/BIOS_as_a_set_of_RTSC_packages `__ containing the modules that make up the RTOS.jZjajbj jdjjf}rg(jh]ji]jj]jk]jn]ujpKjr]rh(j)ri}rj(jYX`SYS/BIOS_as_a_set_of_RTSC_packages `__jf}rk(UnameX"SYS/BIOS_as_a_set_of_RTSC_packagesjXxhttp://dev.ti.com/tirex/content/simplelink_cc2640r2_sdk_2_40_00_32/docs/tirtos/sysbios/docs/cdoc/ti/sysbios/package.htmljk]jj]jh]ji]jn]ujZjejr]rlj{X"SYS/BIOS_as_a_set_of_RTSC_packagesrmrn}ro(jYUjZjiubajdjubj{X. containing the modules that make up the RTOS.rprq}rr(jYX. containing the modules that make up the RTOS.jZjeubeubaubj/)rs}rt(jYX`XDCtools provides configuration tools `__ you use to create and build a static configuration as part of your application. This *.cfg configuration file specifies: * Which modules from XDCtools, SYS/BIOS, and other components to include in the run-time image. * What static instances of RTOS objects to create. For example, these include tasks and semaphores. * Settings for parameter values for modules and objects. jZj]jbj jdj2jf}ru(jh]ji]jj]jk]jn]ujpNjqhjr]rv(j)rw}rx(jYX`XDCtools provides configuration tools `__ you use to create and build a static configuration as part of your application. This *.cfg configuration file specifies:jZjsjbj jdjjf}ry(jh]ji]jj]jk]jn]ujpKjr]rz(j)r{}r|(jYXb`XDCtools provides configuration tools `__jf}r}(UnameX%XDCtools provides configuration toolsjX6http://rtsc.eclipse.org/docs-tip/XDCtools_User's_Guidejk]jj]jh]ji]jn]ujZjwjr]r~j{X%XDCtools provides configuration toolsrr}r(jYUjZj{ubajdjubj{XV you use to create and build a static configuration as part of your application. This rr}r(jYXV you use to create and build a static configuration as part of your application. This jZjwubj)r}r(jYX*jf}r(jk]rUid26rajj]jh]ji]jn]UrefidUid25rujZjwjr]rj{X*r}r(jYUjZjubajdjubj{X".cfg configuration file specifies:rr}r(jYX".cfg configuration file specifies:jZjwubeubj=)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjsjr]rjC)r}r(jYUjf}r(jGX*jk]jj]jh]ji]jn]ujZjjr]r(j/)r}r(jYX]Which modules from XDCtools, SYS/BIOS, and other components to include in the run-time image.rjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYjjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X]Which modules from XDCtools, SYS/BIOS, and other components to include in the run-time image.rr}r(jYjjZjubaubajdj2ubj/)r}r(jYXaWhat static instances of RTOS objects to create. For example, these include tasks and semaphores.rjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYjjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XaWhat static instances of RTOS objects to create. For example, these include tasks and semaphores.rr}r(jYjjZjubaubajdj2ubj/)r}r(jYX7Settings for parameter values for modules and objects. jf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX6Settings for parameter values for modules and objects.rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X6Settings for parameter values for modules and objects.rr}r(jYjjZjubaubajdj2ubejdj`ubajdj@ubeubj/)r}r(jYX`XDCtools provides critical APIs `__ that are used by SYS/BIOS and other related software components. These include memory allocation, logging, and system control. jZj]jbj jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYX`XDCtools provides critical APIs `__ that are used by SYS/BIOS and other related software components. These include memory allocation, logging, and system control.jZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]r(j)r}r(jYXq`XDCtools provides critical APIs `__jf}r(UnameXXDCtools provides critical APIsjXKhttp://rtsc.eclipse.org/docs-tip/Overview_of_xdc.runtime#Using_This_Packagejk]jj]jh]ji]jn]ujZjjr]rj{XXDCtools provides critical APIsrr}r(jYUjZjubajdjubj{X that are used by SYS/BIOS and other related software components. These include memory allocation, logging, and system control.rr}r(jYX that are used by SYS/BIOS and other related software components. These include memory allocation, logging, and system control.jZjubeubaubeubj)r}r(jYX_The `RTSC-pedia web site `__ describes RTSC and XDCtools in more detail. In particular, it provides information for developers planning to create RTSC packages. It is also useful if you plan to edit configuration scripts with a text editor rather than using the XGCONF graphical editor provided withing CCS.rjZj8jbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r(j{XThe rr}r(jYXThe jZjubj)r}r(jYXD`RTSC-pedia web site `__jf}r(UnameXRTSC-pedia web sitejX*http://rtsc.eclipse.org/docs-tip/Main_Pagejk]jj]jh]ji]jn]ujZjjr]rj{XRTSC-pedia web siterr}r(jYUjZjubajdjubj{X describes RTSC and XDCtools in more detail. In particular, it provides information for developers planning to create RTSC packages. It is also useful if you plan to edit configuration scripts with a text editor rather than using the XGCONF graphical editor provided withing CCS.rr}r(jYX describes RTSC and XDCtools in more detail. In particular, it provides information for developers planning to create RTSC packages. It is also useful if you plan to edit configuration scripts with a text editor rather than using the XGCONF graphical editor provided withing CCS.jZjubeubeubj[)r}r(jYUjZj)jbj jdjejf}r(jh]ji]jj]jk]rUcan-you-use-any-sysbios-version-with-any-version-of-xdctools-when-creating-create-or-migrating-to-ti-rtos-based-application-development-environmentrajn]rhaujpKjqhjr]r(jt)r}r(jYXCan you use any SYSBIOS version with any version of XDCTools when creating create or migrating to TI RTOS based application development environmentrjZjjbj jdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XCan you use any SYSBIOS version with any version of XDCTools when creating create or migrating to TI RTOS based application development environmentrr}r(jYjjZjubaubj)r}r(jYXThis is a frequent issue for new user of TI RTOS. SYSBIOS releases are usually validated with a specific version of XDCTools that is described in the Release notes. It is generally not recommended to mix and match SYSBIOS versions with older or newer than the versions described as you may run into incompatibility issues. TI simplifies this build environments by packaging the TI RTOS package with XDCtools or by providing SDKs with the compatible versions of SYSBIOS kernel and XDCtools.rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XThis is a frequent issue for new user of TI RTOS. SYSBIOS releases are usually validated with a specific version of XDCTools that is described in the Release notes. It is generally not recommended to mix and match SYSBIOS versions with older or newer than the versions described as you may run into incompatibility issues. TI simplifies this build environments by packaging the TI RTOS package with XDCtools or by providing SDKs with the compatible versions of SYSBIOS kernel and XDCtools.rr}r(jYjjZjubaubj)r}r(jYX_For customers using TI DSP and ARM Processors, it is recommended to use Processor SDK RTOS for TI RTOS development and to setup the CCS environment such its Preferences are set to use the versions included in the SDK. This process has been described: `Processor_SDK_RTOS_Setup_CCS `__jZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r(j{XFor customers using TI DSP and ARM Processors, it is recommended to use Processor SDK RTOS for TI RTOS development and to setup the CCS environment such its Preferences are set to use the versions included in the SDK. This process has been described: rr}r(jYXFor customers using TI DSP and ARM Processors, it is recommended to use Processor SDK RTOS for TI RTOS development and to setup the CCS environment such its Preferences are set to use the versions included in the SDK. This process has been described: jZjubj)r}r(jYXd`Processor_SDK_RTOS_Setup_CCS `__jf}r(UnameXProcessor_SDK_RTOS_Setup_CCSjXAindex_how_to_guides.html#setup-ccs-for-evm-and-processor-sdk-rtosjk]jj]jh]ji]jn]ujZjjr]rj{XProcessor_SDK_RTOS_Setup_CCSrr}r(jYUjZjubajdjubeubeubj[)r}r(jYUjZj)jbj jdjejf}r(jh]ji]jj]jk]r U/using-sysbios-with-gnu-gcc-for-arm-devices-onlyr ajn]r haujpKjqhjr]r (jt)r }r(jYX1Using SYSBIOS with GNU GCC (for ARM devices only)rjZjjbj jdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X1Using SYSBIOS with GNU GCC (for ARM devices only)rr}r(jYjjZj ubaubj)r}r(jYXThe key care about of using SYSBIOS kernel on ARM based devices with GNU GCC compiler have been described in the article `SYS/BIOS_with_GCC_(CortexA) `__rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r(j{XyThe key care about of using SYSBIOS kernel on ARM based devices with GNU GCC compiler have been described in the article rr}r(jYXyThe key care about of using SYSBIOS kernel on ARM based devices with GNU GCC compiler have been described in the article jZjubj)r}r(jYXe`SYS/BIOS_with_GCC_(CortexA) `__jf}r(UnameXSYS/BIOS_with_GCC_(CortexA)jXChttp://processors.wiki.ti.com/index.php/SYS/BIOS_with_GCC_(CortexA)jk]jj]jh]ji]jn]ujZjjr]r j{XSYS/BIOS_with_GCC_(CortexA)r!r"}r#(jYUjZjubajdjubeubj)r$}r%(jYX)This wiki answers important questions about using SYSBIOS kernel with GNU GCC compiler like: * `Changing entry point to an application `__jZjjbj jdjjf}r&(jh]ji]jj]jk]jn]ujpKjqhjr]r'(j{X_This wiki answers important questions about using SYSBIOS kernel with GNU GCC compiler like: * r(r)}r*(jYX_This wiki answers important questions about using SYSBIOS kernel with GNU GCC compiler like: * jZj$ubj)r+}r,(jYX`Changing entry point to an application `__jf}r-(UnameX&Changing entry point to an applicationjXhttp://processors.wiki.ti.com/index.php/SYS/BIOS_with_GCC_(CortexA)#How_do_I_change_the_address_where_the_entry_point_function_.28_c_int00.29_gets_placed_.3Fjk]jj]jh]ji]jn]ujZj$jr]r.j{X&Changing entry point to an applicationr/r0}r1(jYUjZj+ubajdjubeubjC)r2}r3(jYUjZjjbj jdj`jf}r4(jGX*jk]jj]jh]ji]jn]ujpKjqhjr]r5(j/)r6}r7(jYX`Recommended compiler and linker settings `__ jZj2jbj jdj2jf}r8(jh]ji]jj]jk]jn]ujpNjqhjr]r9j)r:}r;(jYX`Recommended compiler and linker settings `__r<jZj6jbj jdjjf}r=(jh]ji]jj]jk]jn]ujpKjr]r>j)r?}r@(jYj<jf}rA(UnameX(Recommended compiler and linker settingsjXXhttp://processors.wiki.ti.com/index.php/SYS/BIOS_with_GCC_(CortexA)#Configure_SYS.2FBIOSjk]jj]jh]ji]jn]ujZj:jr]rBj{X(Recommended compiler and linker settingsrCrD}rE(jYUjZj?ubajdjubaubaubj/)rF}rG(jYX`Getting System_printf/printf (adding Semihosting support) `__ jZj2jbj jdj2jf}rH(jh]ji]jj]jk]jn]ujpNjqhjr]rIj)rJ}rK(jYX`Getting System_printf/printf (adding Semihosting support) `__rLjZjFjbj jdjjf}rM(jh]ji]jj]jk]jn]ujpKjr]rNj)rO}rP(jYjLjf}rQ(UnameX9Getting System_printf/printf (adding Semihosting support)jX}http://processors.wiki.ti.com/index.php/SYS/BIOS_with_GCC_(CortexA)#Why_is_System_printf.28.29.2Fprintf.28.29_not_working_.3Fjk]jj]jh]ji]jn]ujZjJjr]rRj{X9Getting System_printf/printf (adding Semihosting support)rSrT}rU(jYUjZjOubajdjubaubaubj/)rV}rW(jYX`Creating make based TI RTOS application build using GNU GCC compiler and XDCtools `__ jZj2jbj jdj2jf}rX(jh]ji]jj]jk]jn]ujpNjqhjr]rYj)rZ}r[(jYX`Creating make based TI RTOS application build using GNU GCC compiler and XDCtools `__r\jZjVjbj jdjjf}r](jh]ji]jj]jk]jn]ujpKjr]r^j)r_}r`(jYj\jf}ra(UnameXQCreating make based TI RTOS application build using GNU GCC compiler and XDCtoolsjXhhttp://processors.wiki.ti.com/index.php/SYS/BIOS_with_GCC_(CortexA)#Build_Application_with_Configurationjk]jj]jh]ji]jn]ujZjZjr]rbj{XQCreating make based TI RTOS application build using GNU GCC compiler and XDCtoolsrcrd}re(jYUjZj_ubajdjubaubaubj/)rf}rg(jYX`Configuring ARM MMU and cache settings `__ jZj2jbj jdj2jf}rh(jh]ji]jj]jk]jn]ujpNjqhjr]rij)rj}rk(jYX`Configuring ARM MMU and cache settings `__rljZjfjbj jdjjf}rm(jh]ji]jj]jk]jn]ujpKjr]rnj)ro}rp(jYjljf}rq(UnameX&Configuring ARM MMU and cache settingsjXhttp://processors.wiki.ti.com/index.php/SYS/BIOS_with_GCC_(CortexA)#How_do_I_add_a_4KB_granularity_MMU_pages_on_Cortex-A8.2C_Cortex-A9_and_Cortex-A15_devices_.3Fjk]jj]jh]ji]jn]ujZjjjr]rrj{X&Configuring ARM MMU and cache settingsrsrt}ru(jYUjZjoubajdjubaubaubeubeubj[)rv}rw(jYUjZj)jbj jdjejf}rx(jh]ji]jj]jk]ryUOhow-do-i-port-existing-application-developed-on-sysbios-application-to-smp-biosrzajn]r{j aujpKjqhjr]r|(jt)r}}r~(jYXOHow do I port existing application developed on SYSBIOS application to SMP/BIOSrjZjvjbj jdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XOHow do I port existing application developed on SYSBIOS application to SMP/BIOSrr}r(jYjjZj}ubaubj)r}r(jYXSYSBIOS supports SMP mode of operation on multi-core ARM and few dual core M3/M4 (IPU) subsytem present in Keystone and Sitara processors.rjZjvjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XSYSBIOS supports SMP mode of operation on multi-core ARM and few dual core M3/M4 (IPU) subsytem present in Keystone and Sitara processors.rr}r(jYjjZjubaubj)r}r(jYX**Training Slides**: `SMP SYSBIOS Overview presentation `__.rjZjvjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r(j)r}r(jYX**Training Slides**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XTraining Slidesrr}r(jYUjZjubajdjubj{X: rr}r(jYX: jZjubj)r}r(jYXm`SMP SYSBIOS Overview presentation `__jf}r(UnameX!SMP SYSBIOS Overview presentationjXEhttp://processors.wiki.ti.com/index.php/File:Public_SmpBiosSlides.pdfjk]jj]jh]ji]jn]ujZjjr]rj{X!SMP SYSBIOS Overview presentationrr}r(jYUjZjubajdjubj{X.r}r(jYX.jZjubeubj)r}r(jYXTo Porting existing SYS/BIOS applications to SMP/BIOS, you can use the follow steps described below: * Merge existing separate applications into a single application. * Merge separate platform memory definitions as necessary. * Add this to your existing application’s config script: ::jZjvjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XTo Porting existing SYS/BIOS applications to SMP/BIOS, you can use the follow steps described below: * Merge existing separate applications into a single application. * Merge separate platform memory definitions as necessary. * Add this to your existing application’s config script:rr}r(jYXTo Porting existing SYS/BIOS applications to SMP/BIOS, you can use the follow steps described below: * Merge existing separate applications into a single application. * Merge separate platform memory definitions as necessary. * Add this to your existing application’s config script:jZjubaubj)r}r(jYXBIOS.smpEnabled = true;jZjvjbj jdjjf}r(jjjk]jj]jh]ji]jn]ujpM^jqhjr]rj{XBIOS.smpEnabled = true;rr}r(jYUjZjubaubjZ)r}r(jYUjZjvjbj jdj]jf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj`)r}r(jYUjcKjZjjbj jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjC)r}r(jYUjZjvjbj jdj`jf}r(jGX*jk]jj]jh]ji]jn]ujpKjqhjr]rj/)r}r(jYXUse these SMP-aware clone modules in place of their xdc.runtime equivalents for SysMin, SysStd, LoggerBuf (in ti.sybios.smp package)rjZjjbj jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XUse these SMP-aware clone modules in place of their xdc.runtime equivalents for SysMin, SysStd, LoggerBuf (in ti.sybios.smp package)rr}r(jYjjZjubaubaubaubj)r}r(jYX'''Note:''' The existing Load module has been tweaked to provide minimal support for SMP. * For initial sanity testing, force all tasks to run on core 0: ::jZjvjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X'''Note:''' The existing Load module has been tweaked to provide minimal support for SMP. * For initial sanity testing, force all tasks to run on core 0:rr}r(jYX'''Note:''' The existing Load module has been tweaked to provide minimal support for SMP. * For initial sanity testing, force all tasks to run on core 0:jZjubaubj)r}r(jYXTask.defaultAffinity = 0;jZjvjbj jdjjf}r(jjjk]jj]jh]ji]jn]ujpMdjqhjr]rj{XTask.defaultAffinity = 0;rr}r(jYUjZjubaubjZ)r}r(jYUjZjvjbj jdj]jf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj`)r}r(jYUjcKjZjjbj jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjC)r}r(jYUjZjvjbj jdj`jf}r(jGX*jk]jj]jh]ji]jn]ujpKjqhjr]rj/)r}r(jYXOnce basic functionality of the merged applications has been demonstrated, either remove Task.defaultAffinity setting or replace it with jZjjbj jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXOnce basic functionality of the merged applications has been demonstrated, either remove Task.defaultAffinity setting or replace it withrjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XOnce basic functionality of the merged applications has been demonstrated, either remove Task.defaultAffinity setting or replace it withrr}r(jYjjZjubaubaubaubj)r}r(jYX*Task.defaultAffinity = Task.AFFINITY_NONE;rjZjvjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X*Task.defaultAffinity = Task.AFFINITY_NONE;rr}r(jYjjZjubaubj)r}r(jYXThe above statement will guide RTOS kernel to deploy tasks based on availability in the cluster of compute cores processing in SMP mode.rjZjvjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XThe above statement will guide RTOS kernel to deploy tasks based on availability in the cluster of compute cores processing in SMP mode.rr}r(jYjjZjubaubeubj[)r}r(jYUjZj)jbj jdjejf}r(jh]ji]jj]jk]rU@are-there-any-graphical-tools-to-configure-sysbios-configurationrajn]rhaujpKjqhjr]r(jt)r}r(jYX@Are there any Graphical tools to configure SYSBIOS configurationrjZjjbj jdjxjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r j{X@Are there any Graphical tools to configure SYSBIOS configurationr r }r (jYjjZjubaubj)r}r(jYXThe easiest way for new users to add/configure new modules in the TI RTOS BIOS configuration is to use `XGCONF based graphical tool `__rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r(j{XgThe easiest way for new users to add/configure new modules in the TI RTOS BIOS configuration is to use rr}r(jYXgThe easiest way for new users to add/configure new modules in the TI RTOS BIOS configuration is to use jZjubj)r}r(jYX``XGCONF based graphical tool `__jf}r(UnameXXGCONF based graphical tooljX>http://rtsc.eclipse.org/docs-tip/RTSC%2BCCStudio_v4_QuickStartjk]jj]jh]ji]jn]ujZjjr]rj{XXGCONF based graphical toolrr}r(jYUjZjubajdjubeubeubeubj[)r}r(jYUjZjjbj jdjejf}r(jh]ji]jj]jk]r U thread-typesr!ajn]r"haujpKjqhjr]r#(jt)r$}r%(jYX Thread Typesr&jZjjbj jdjxjf}r'(jh]ji]jj]jk]jn]ujpKjqhjr]r(j{X Thread Typesr)r*}r+(jYj&jZj$ubaubj[)r,}r-(jYUjZjjbj jdjejf}r.(jh]ji]jj]jk]r/U-what-is-the-difference-between-swis-and-tasksr0ajn]r1haujpKjqhjr]r2(jt)r3}r4(jYX-What is the difference between SWIs and Tasksr5jZj,jbj jdjxjf}r6(jh]ji]jj]jk]jn]ujpKjqhjr]r7j{X-What is the difference between SWIs and Tasksr8r9}r:(jYj5jZj3ubaubjC)r;}r<(jYUjZj,jbj jdj`jf}r=(jGX*jk]jj]jh]ji]jn]ujpKjqhjr]r>(j/)r?}r@(jYXA Swi is a non-blocking thread that runs to completion and can only be pre-empted by a higher priority Swi or a Hwi (interrupt). Swi's can pre-empt a Task thread when posted and run on the ISR (system) stack (i.e. they do not have their own stack). jZj;jbj jdj2jf}rA(jh]ji]jj]jk]jn]ujpNjqhjr]rBj)rC}rD(jYXA Swi is a non-blocking thread that runs to completion and can only be pre-empted by a higher priority Swi or a Hwi (interrupt). Swi's can pre-empt a Task thread when posted and run on the ISR (system) stack (i.e. they do not have their own stack).rEjZj?jbj jdjjf}rF(jh]ji]jj]jk]jn]ujpKjr]rGj{XA Swi is a non-blocking thread that runs to completion and can only be pre-empted by a higher priority Swi or a Hwi (interrupt). Swi's can pre-empt a Task thread when posted and run on the ISR (system) stack (i.e. they do not have their own stack).rHrI}rJ(jYjEjZjCubaubaubj/)rK}rL(jYX+A Task thread on the other hand is a blocking thread and can be pre-empted by a higher priority Task or by Swi/Hwi. A task usually has a while loop that keeps the task executing continuously in the system as long as it is required in the application. Also, Tasks run on their own independent stack. jZj;jbj jdj2jf}rM(jh]ji]jj]jk]jn]ujpNjqhjr]rNj)rO}rP(jYX*A Task thread on the other hand is a blocking thread and can be pre-empted by a higher priority Task or by Swi/Hwi. A task usually has a while loop that keeps the task executing continuously in the system as long as it is required in the application. Also, Tasks run on their own independent stack.rQjZjKjbj jdjjf}rR(jh]ji]jj]jk]jn]ujpKjr]rSj{X*A Task thread on the other hand is a blocking thread and can be pre-empted by a higher priority Task or by Swi/Hwi. A task usually has a while loop that keeps the task executing continuously in the system as long as it is required in the application. Also, Tasks run on their own independent stack.rTrU}rV(jYjQjZjOubaubaubeubeubj[)rW}rX(jYUjZjjbj jdjejf}rY(jh]ji]jj]jk]rZU3how-to-add-house-keeping-functions-in-the-idle-taskr[ajn]r\jaujpKjqhjr]r](jt)r^}r_(jYX3How to add house keeping functions in the idle Taskr`jZjWjbj jdjxjf}ra(jh]ji]jj]jk]jn]ujpKjqhjr]rbj{X3How to add house keeping functions in the idle Taskrcrd}re(jYj`jZj^ubaubj)rf}rg(jYXfIf you want to use the idle time of the system to do some "housekeeping" jobs in the background, when the system is not active on interrupts or tasks, TI RTOS provides option to provide a task list or point to a housekeeping function which will run when no other thread is active in the system. The simplest syntax to add this to your code is shown below: ::jZjWjbj jdjjf}rh(jh]ji]jj]jk]jn]ujpKjqhjr]rij{XcIf you want to use the idle time of the system to do some "housekeeping" jobs in the background, when the system is not active on interrupts or tasks, TI RTOS provides option to provide a task list or point to a housekeeping function which will run when no other thread is active in the system. The simplest syntax to add this to your code is shown below:rjrk}rl(jYXcIf you want to use the idle time of the system to do some "housekeeping" jobs in the background, when the system is not active on interrupts or tasks, TI RTOS provides option to provide a task list or point to a housekeeping function which will run when no other thread is active in the system. The simplest syntax to add this to your code is shown below:jZjfubaubj)rm}rn(jYXmTask.enableIdleTask = true; var Idle = xdc.useModule('ti.sysbios.knl.Idle'); Idle.addFunc('&osTaskIdleFunc');jZjWjbj jdjjf}ro(jjjk]jj]jh]ji]jn]ujpMjqhjr]rpj{XmTask.enableIdleTask = true; var Idle = xdc.useModule('ti.sysbios.knl.Idle'); Idle.addFunc('&osTaskIdleFunc');rqrr}rs(jYUjZjmubaubjZ)rt}ru(jYUjZjWjbj jdj]jf}rv(jh]ji]jj]jk]jn]ujpKjqhjr]rwj`)rx}ry(jYUjcKjZjtjbj jdjpjf}rz(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r{}r|(jYXIf you open the BIOS configuration in XGCONF, you will notice that user are allowed to enter upto 8 function in the function list.r}jZjWjbj jdjjf}r~(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XIf you open the BIOS configuration in XGCONF, you will notice that user are allowed to enter upto 8 function in the function list.rr}r(jYj}jZj{ubaubj)r}r(jYX1Syntax to add idle functions is provided below ::jZjWjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X.Syntax to add idle functions is provided belowrr}r(jYX.Syntax to add idle functions is provided belowjZjubaubj)r}r(jYXOvar Idle = xdc.useModule('ti.sysbios.knl.Idle'); Idle.idleFxns[0] = "&myIdle1";jZjWjbj jdjjf}r(jjjk]jj]jh]ji]jn]ujpMjqhjr]rj{XOvar Idle = xdc.useModule('ti.sysbios.knl.Idle'); Idle.idleFxns[0] = "&myIdle1";rr}r(jYUjZjubaubjZ)r}r(jYUjZjWjbj jdj]jf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj`)r}r(jYUjcKjZjjbj jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubeubj[)r}r(jYUjZjjbj jdjejf}r(jh]ji]jj]jk]rUhardware-interrupts-hwirajn]rhaujpKjqhjr]r(jt)r}r(jYXHardware Interrupts (HWI)rjZjjbj jdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XHardware Interrupts (HWI)rr}r(jYjjZjubaubj[)r}r(jYUjZjjbj jdjejf}r(jh]ji]jj]jk]rULhow-to-configure-crossbar-when-setting-up-interrupts-on-dra7xx-tda2xx-am57xxrajn]rhaujpKjqhjr]r(jt)r}r(jYXLHow to configure Crossbar when setting up interrupts on DRA7xx/TDA2xx/AM57xxrjZjjbj jdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XLHow to configure Crossbar when setting up interrupts on DRA7xx/TDA2xx/AM57xxrr}r(jYjjZjubaubj)r}r(jYXSome socs like AM571x and AM572x have a large number of interrupts requests to service the needs of its many peripherals and subsystems. All of the interrupt lines from the subsystems are not needed at the same time, so they have to be muxed to the irq-controller appropriately. In such places a interrupt controllers are preceded by an CROSSBAR that provides flexibility in muxing the device requests to the controller inputs.rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XSome socs like AM571x and AM572x have a large number of interrupts requests to service the needs of its many peripherals and subsystems. All of the interrupt lines from the subsystems are not needed at the same time, so they have to be muxed to the irq-controller appropriately. In such places a interrupt controllers are preceded by an CROSSBAR that provides flexibility in muxing the device requests to the controller inputs.rr}r(jYjjZjubaubj)r}r(jYXVApplication developers have two options to setup interrupts on AM57xx/TDA2xx/DRA7xx devices which provide a crossbar mechanism to connect a given IRQ source to an IRQ line on the target cpu's interrupt controller. The device level chip support library provides functional APIs to map interrupt events to target core interrupt controller line.rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XVApplication developers have two options to setup interrupts on AM57xx/TDA2xx/DRA7xx devices which provide a crossbar mechanism to connect a given IRQ source to an IRQ line on the target cpu's interrupt controller. The device level chip support library provides functional APIs to map interrupt events to target core interrupt controller line.rr}r(jYjjZjubaubj)r}r(jYXTFor example SPI3_IRQ to the CROSSBAR input on DSP and M4, you can use the following:rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XTFor example SPI3_IRQ to the CROSSBAR input on DSP and M4, you can use the following:rr}r(jYjjZjubaubj)r}r(jYX<DSP Core1 configuration of SPI3_IRQ to crossbar input 60: ::jZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X9DSP Core1 configuration of SPI3_IRQ to crossbar input 60:rr}r(jYX9DSP Core1 configuration of SPI3_IRQ to crossbar input 60:jZjubaubj)r}r(jYXF/* Configure xbar connect for MCSPI3: DSP_IRQ_43 (reserved) mapped to MCSPI3 intr */ CSL_xbarIrqConfigure (CSL_XBAR_IRQ_CPU_ID_DSP1, CSL_XBAR_INST_DSP1_IRQ_43, /* should match with C66 intc eventId used for event combiner that maps to DSP interrupts*/ CSL_XBAR_MCSPI3_IRQ);jZjjbj jdjjf}r(jjjk]jj]jh]ji]jn]ujpMjqhjr]rj{XF/* Configure xbar connect for MCSPI3: DSP_IRQ_43 (reserved) mapped to MCSPI3 intr */ CSL_xbarIrqConfigure (CSL_XBAR_IRQ_CPU_ID_DSP1, CSL_XBAR_INST_DSP1_IRQ_43, /* should match with C66 intc eventId used for event combiner that maps to DSP interrupts*/ CSL_XBAR_MCSPI3_IRQ);rr}r(jYUjZjubaubjZ)r}r(jYUjZjjbj jdj]jf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj`)r}r(jYUjcKjZjjbj jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r}r(jYX<IPU core1 configuration of SPI3_IRQ to crossbar input 43: ::jZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X9IPU core1 configuration of SPI3_IRQ to crossbar input 43:rr}r(jYX9IPU core1 configuration of SPI3_IRQ to crossbar input 43:jZjubaubj)r}r(jYX!/* Configure xbar connect for MCSPI3: IPU1_IRQ_60 (reserved) mapped to MCSPI3 intr */ CSL_xbarIrqConfigure (CSL_XBAR_IRQ_CPU_ID_IPU1, CSL_XBAR_INST_IPU1_IRQ_60, /* should match with M4 intNum used for HWI_create */ CSL_XBAR_MCSPI3_IRQ);jZjjbj jdjjf}r(jjjk]jj]jh]ji]jn]ujpMjqhjr]rj{X!/* Configure xbar connect for MCSPI3: IPU1_IRQ_60 (reserved) mapped to MCSPI3 intr */ CSL_xbarIrqConfigure (CSL_XBAR_IRQ_CPU_ID_IPU1, CSL_XBAR_INST_IPU1_IRQ_60, /* should match with M4 intNum used for HWI_create */ CSL_XBAR_MCSPI3_IRQ);rr}r(jYUjZjubaubjZ)r}r(jYUjZjjbj jdj]jf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj`)r}r(jYUjcKjZjjbj jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r}r(jYXhHere is how you would define the same interrupt handler for IPU statically in a configuration script: ::jZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XeHere is how you would define the same interrupt handler for IPU statically in a configuration script:rr}r(jYXeHere is how you would define the same interrupt handler for IPU statically in a configuration script:jZjubaubj)r}r(jYXvar Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi'); var IntXbar = xdc.useModule('ti.sysbios.family.shared.vayu.IntXbar'); // Connect IRQ 23 to Interrupt source index 86 (SPI3_IRQ) IntXbar.connectIRQMeta(60, 86); // Alternately, the connectIRQMeta API can be used. This // API expects XBAR instance number as an argument. // // Connect Xbar Instance 1 (IRQ 60) to Interrupt // source index 86 (MCSPI3_IRQ) // // IntXbar.connectMeta(1, 60); var hwiParams = new Hwi.Params(); hwiParams.arg = 60;jZjjbj jdjjf}r(jjjk]jj]jh]ji]jn]ujpMjqhjr]rj{Xvar Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi'); var IntXbar = xdc.useModule('ti.sysbios.family.shared.vayu.IntXbar'); // Connect IRQ 23 to Interrupt source index 86 (SPI3_IRQ) IntXbar.connectIRQMeta(60, 86); // Alternately, the connectIRQMeta API can be used. This // API expects XBAR instance number as an argument. // // Connect Xbar Instance 1 (IRQ 60) to Interrupt // source index 86 (MCSPI3_IRQ) // // IntXbar.connectMeta(1, 60); var hwiParams = new Hwi.Params(); hwiParams.arg = 60;rr}r(jYUjZjubaubjZ)r}r(jYUjZjjbj jdj]jf}r(jh]ji]jj]jk]jn]ujpM jqhjr]r j`)r }r (jYUjcKjZjjbj jdjpjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubeubj[)r }r(jYUjZjjbj jdjejf}r(jh]ji]jj]jk]rUclocks-and-timersrajn]rhaujpM jqhjr]r(jt)r}r(jYXClocks and TimersrjZj jbj jdjxjf}r(jh]ji]jj]jk]jn]ujpM jqhjr]rj{XClocks and Timersrr}r(jYjjZjubaubj[)r}r(jYUjZj jbj jdjejf}r(jh]ji]jj]jk]rUUwhat-are-the-different-clock-and-timer-modules-in-ti-rtos-that-you-should-be-aware-ofr ajn]r!haujpMjqhjr]r"(jt)r#}r$(jYXVWhat are the different clock and timer modules in TI RTOS that you should be aware of?r%jZjjbj jdjxjf}r&(jh]ji]jj]jk]jn]ujpMjqhjr]r'j{XVWhat are the different clock and timer modules in TI RTOS that you should be aware of?r(r)}r*(jYj%jZj#ubaubjC)r+}r,(jYUjZjjbj jdj`jf}r-(jGX*jk]jj]jh]ji]jn]ujpMjqhjr]r.(j/)r/}r0(jYXZTimer Module * Manages timer peripherals * Provides target/device abstraction jZj+jbNjdj2jf}r1(jh]ji]jj]jk]jn]ujpNjqhjr]r2j )r3}r4(jYUjf}r5(jh]ji]jj]jk]jn]ujZj/jr]r6j )r7}r8(jYXNTimer Module * Manages timer peripherals * Provides target/device abstraction jZj3jbj jdj jf}r9(jh]ji]jj]jk]jn]ujpMjr]r:(j )r;}r<(jYX Timer Moduler=jZj7jbj jdj jf}r>(jh]ji]jj]jk]jn]ujpMjr]r?j{X Timer Moduler@rA}rB(jYj=jZj;ubaubj )rC}rD(jYUjf}rE(jh]ji]jj]jk]jn]ujZj7jr]rFjC)rG}rH(jYUjf}rI(jGX*jk]jj]jh]ji]jn]ujZjCjr]rJ(j/)rK}rL(jYXManages timer peripheralsrMjf}rN(jh]ji]jj]jk]jn]ujZjGjr]rOj)rP}rQ(jYjMjZjKjbj jdjjf}rR(jh]ji]jj]jk]jn]ujpMjr]rSj{XManages timer peripheralsrTrU}rV(jYjMjZjPubaubajdj2ubj/)rW}rX(jYX#Provides target/device abstraction jf}rY(jh]ji]jj]jk]jn]ujZjGjr]rZj)r[}r\(jYX"Provides target/device abstractionr]jZjWjbj jdjjf}r^(jh]ji]jj]jk]jn]ujpMjr]r_j{X"Provides target/device abstractionr`ra}rb(jYj]jZj[ubaubajdj2ubejdj`ubajdj2 ubeubajdj3 ubaubj/)rc}rd(jYXClock Module * Manages BIOS “heartbeat” * Can schedule functions to fire in the future (one-shot or periodically) * Input can be configured to use Timer module “tick” or application “tick” jZj+jbNjdj2jf}re(jh]ji]jj]jk]jn]ujpNjqhjr]rfj )rg}rh(jYUjf}ri(jh]ji]jj]jk]jn]ujZjcjr]rjj )rk}rl(jYXClock Module * Manages BIOS “heartbeat” * Can schedule functions to fire in the future (one-shot or periodically) * Input can be configured to use Timer module “tick” or application “tick” jZjgjbj jdj jf}rm(jh]ji]jj]jk]jn]ujpMjr]rn(j )ro}rp(jYX Clock ModulerqjZjkjbj jdj jf}rr(jh]ji]jj]jk]jn]ujpMjr]rsj{X Clock Modulertru}rv(jYjqjZjoubaubj )rw}rx(jYUjf}ry(jh]ji]jj]jk]jn]ujZjkjr]rzjC)r{}r|(jYUjf}r}(jGX*jk]jj]jh]ji]jn]ujZjwjr]r~(j/)r}r(jYXManages BIOS “heartbeat”rjf}r(jh]ji]jj]jk]jn]ujZj{jr]rj)r}r(jYjjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XManages BIOS “heartbeat”rr}r(jYjjZjubaubajdj2ubj/)r}r(jYXGCan schedule functions to fire in the future (one-shot or periodically)rjf}r(jh]ji]jj]jk]jn]ujZj{jr]rj)r}r(jYjjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XGCan schedule functions to fire in the future (one-shot or periodically)rr}r(jYjjZjubaubajdj2ubj/)r}r(jYXQInput can be configured to use Timer module “tick” or application “tick” jf}r(jh]ji]jj]jk]jn]ujZj{jr]rj)r}r(jYXPInput can be configured to use Timer module “tick” or application “tick”rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XPInput can be configured to use Timer module “tick” or application “tick”rr}r(jYjjZjubaubajdj2ubejdj`ubajdj2 ubeubajdj3 ubaubj/)r}r(jYX|Timestamp Module * Provides simple time stamping services for benchmarking code * Allows time stamping RTA logs jZj+jbNjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj )r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj )r}r(jYXpTimestamp Module * Provides simple time stamping services for benchmarking code * Allows time stamping RTA logs jZjjbj jdj jf}r(jh]ji]jj]jk]jn]ujpMjr]r(j )r}r(jYXTimestamp ModulerjZjjbj jdj jf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XTimestamp Modulerr}r(jYjjZjubaubj )r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rjC)r}r(jYUjf}r(jGX*jk]jj]jh]ji]jn]ujZjjr]r(j/)r}r(jYX<Provides simple time stamping services for benchmarking coderjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYjjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{X<Provides simple time stamping services for benchmarking coderr}r(jYjjZjubaubajdj2ubj/)r}r(jYXAllows time stamping RTA logs jf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXAllows time stamping RTA logsrjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XAllows time stamping RTA logsrr}r(jYjjZjubaubajdj2ubejdj`ubajdj2 ubeubajdj3 ubaubeubj)r}r(jYX**BIOS Timer Architecture**rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpM jqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XBIOS Timer Architecturerr}r(jYUjZjubajdjubaubjB)r}r(jYXA.. Image:: ../images/BIOS_Timer_Architecture.png :scale: 50 % jZjjbj jdjEjf}r(UscaleK2UuriX*rtos/../images/BIOS_Timer_Architecture.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpNjqhjr]ubj)r}r(jYX**BIOS Clock Architecture**rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpM%jqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XBIOS Clock Architecturerr}r(jYUjZjubajdjubaubjB)r}r(jYXG.. Image:: ../images/BIOS_Clock_Architecture.png :scale: 50 % jZjjbj jdjEjf}r(UscaleK2UuriX*rtos/../images/BIOS_Clock_Architecture.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpNjqhjr]ubeubj[)r}r(jYUjZj jbj jdjejf}r(jh]ji]jj]jk]rU5how-to-get-accurate-clock-ticks-from-the-clock-modulerajn]rjaujpM,jqhjr]r(jt)r}r(jYX6How to get accurate clock ticks from the clock module?rjZjjbj jdjxjf}r(jh]ji]jj]jk]jn]ujpM,jqhjr]rj{X6How to get accurate clock ticks from the clock module?rr}r(jYjjZjubaubj)r}r (jYXThe clock module uses the CPU clock setting that is provided by the default platform setting. For example, if the platform is set to AM335x, then the clock is assumed to be 550 MHz, so the clock ticks will be generated with period of 1.8 nanoseconds. '''TI RTOS doesn`t setup the device clocks, the device clock initiation is the responsibility of the initialization code''' (GEL file in debug environment and bootloader in production environment)r jZjjbj jdjjf}r (jh]ji]jj]jk]jn]ujpM.jqhjr]r j{XThe clock module uses the CPU clock setting that is provided by the default platform setting. For example, if the platform is set to AM335x, then the clock is assumed to be 550 MHz, so the clock ticks will be generated with period of 1.8 nanoseconds. '''TI RTOS doesn`t setup the device clocks, the device clock initiation is the responsibility of the initialization code''' (GEL file in debug environment and bootloader in production environment)r r}r(jYj jZjubaubj)r}r(jYXAfter, the clocks are configured, it is the responsibility of the application developer to inform BIOS of the CPU frequency so that accurate system ticks can be generated.rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpM0jqhjr]rj{XAfter, the clocks are configured, it is the responsibility of the application developer to inform BIOS of the CPU frequency so that accurate system ticks can be generated.rr}r(jYjjZjubaubj)r}r(jYX**Note:** For example if the core clock on AM335x is set to 720 MHz instead of default 550 Mhz, then users are required to add the following like the .cfg to inform BIOS kernel of the actual CPU setting. ::jZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpM2jqhjr]r(j)r}r(jYX **Note:**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XNote:r r!}r"(jYUjZjubajdjubj{X For example if the core clock on AM335x is set to 720 MHz instead of default 550 Mhz, then users are required to add the following like the .cfg to inform BIOS kernel of the actual CPU setting.r#r$}r%(jYX For example if the core clock on AM335x is set to 720 MHz instead of default 550 Mhz, then users are required to add the following like the .cfg to inform BIOS kernel of the actual CPU setting.jZjubeubj)r&}r'(jYXBIOS.cpuFreq.lo = 720000000;jZjjbj jdjjf}r((jjjk]jj]jh]ji]jn]ujpMjqhjr]r)j{XBIOS.cpuFreq.lo = 720000000;r*r+}r,(jYUjZj&ubaubjZ)r-}r.(jYUjZjjbj jdj]jf}r/(jh]ji]jj]jk]jn]ujpM5jqhjr]r0j`)r1}r2(jYUjcKjZj-jbj jdjpjf}r3(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r4}r5(jYXWe reiterate that this doesn`t change the actual frequency but only informs the OS of the change from default CPU freq setting.r6jZjjbj jdjjf}r7(jh]ji]jj]jk]jn]ujpM6jqhjr]r8j{XWe reiterate that this doesn`t change the actual frequency but only informs the OS of the change from default CPU freq setting.r9r:}r;(jYj6jZj4ubaubeubj[)r<}r=(jYUjZj jbj jdjejf}r>(jh]ji]jj]jk]r?UYhow-to-set-input-frequency-in-sysbios-configuration-and-change-timer-used-by-clock-moduler@ajn]rAhGaujpM9jqhjr]rB(jt)rC}rD(jYXYHow to set input frequency in SYSBIOS configuration and change timer used by clock modulerEjZj<jbj jdjxjf}rF(jh]ji]jj]jk]jn]ujpM9jqhjr]rGj{XYHow to set input frequency in SYSBIOS configuration and change timer used by clock modulerHrI}rJ(jYjEjZjCubaubj)rK}rL(jYXTimer.intFreq[index] determines the input clock that drivers the timer. In most cases the input clock is assumed to be the input clock used in TI EVM (Example: 24 Mhz used on AM335x EVM). If you have a different input on your custom board users are required to change the input Freqency setting in their configuration. To change the dmtimer frequency in SYS/BIOS you need to add the following to your config file: ::jZj<jbj jdjjf}rM(jh]ji]jj]jk]jn]ujpM;jqhjr]rNj{XTimer.intFreq[index] determines the input clock that drivers the timer. In most cases the input clock is assumed to be the input clock used in TI EVM (Example: 24 Mhz used on AM335x EVM). If you have a different input on your custom board users are required to change the input Freqency setting in their configuration. To change the dmtimer frequency in SYS/BIOS you need to add the following to your config file:rOrP}rQ(jYXTimer.intFreq[index] determines the input clock that drivers the timer. In most cases the input clock is assumed to be the input clock used in TI EVM (Example: 24 Mhz used on AM335x EVM). If you have a different input on your custom board users are required to change the input Freqency setting in their configuration. To change the dmtimer frequency in SYS/BIOS you need to add the following to your config file:jZjKubaubj)rR}rS(jYXlvar Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer'); Timer.intFreqs[index] = {hi: 0, lo: 19200000};jZj<jbj jdjjf}rT(jjjk]jj]jh]ji]jn]ujpMjqhjr]rUj{Xlvar Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer'); Timer.intFreqs[index] = {hi: 0, lo: 19200000};rVrW}rX(jYUjZjRubaubjZ)rY}rZ(jYUjZj<jbj jdj]jf}r[(jh]ji]jj]jk]jn]ujpM?jqhjr]r\j`)r]}r^(jYUjcKjZjYjbj jdjpjf}r_(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r`}ra(jYXWhere index is the SYS/BIOS timer ID. Please remember that timer IDs do not necessarily match the number in the peripheral name. For example on AM335x SYS/BIOS Timer 0 actually corresponds to DMTimer2 on the device. Use the `Timer Mapping Table `__ to determine which timer corresponds to each Timer ID.rbjZj<jbj jdjjf}rc(jh]ji]jj]jk]jn]ujpM@jqhjr]rd(j{XWhere index is the SYS/BIOS timer ID. Please remember that timer IDs do not necessarily match the number in the peripheral name. For example on AM335x SYS/BIOS Timer 0 actually corresponds to DMTimer2 on the device. Use the rerf}rg(jYXWhere index is the SYS/BIOS timer ID. Please remember that timer IDs do not necessarily match the number in the peripheral name. For example on AM335x SYS/BIOS Timer 0 actually corresponds to DMTimer2 on the device. Use the jZj`ubj)rh}ri(jYX`Timer Mapping Table `__jf}rj(UnameXTimer Mapping TablejXhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/bios/sysbios/6_40_01_15/exports/bios_6_40_01_15/docs/cdoc/ti/sysbios/timers/dmtimer/doc-files/TimerTables.htmljk]jj]jh]ji]jn]ujZj`jr]rkj{XTimer Mapping Tablerlrm}rn(jYUjZjhubajdjubj{X7 to determine which timer corresponds to each Timer ID.rorp}rq(jYX7 to determine which timer corresponds to each Timer ID.jZj`ubeubj)rr}rs(jYXThe Clock module uses a Timer internally. By default, the Clock module calls Timer_create() with "ANY" which will return one of the available timers. You can specify the exact timer using the following (the default value for Clock.timerId is ANY).rtjZj<jbj jdjjf}ru(jh]ji]jj]jk]jn]ujpMBjqhjr]rvj{XThe Clock module uses a Timer internally. By default, the Clock module calls Timer_create() with "ANY" which will return one of the available timers. You can specify the exact timer using the following (the default value for Clock.timerId is ANY).rwrx}ry(jYjtjZjrubaubj)rz}r{(jYXDTo set it to a specic timer Id, you can use the following syntax. ::jZj<jbj jdjjf}r|(jh]ji]jj]jk]jn]ujpMEjqhjr]r}j{XATo set it to a specic timer Id, you can use the following syntax.r~r}r(jYXATo set it to a specic timer Id, you can use the following syntax.jZjzubaubj)r}r(jYX@Clock= xdc.useModule('ti.sysbios.knl.Clock'); Clock.timerId = 3;jZj<jbj jdjjf}r(jjjk]jj]jh]ji]jn]ujpMjqhjr]rj{X@Clock= xdc.useModule('ti.sysbios.knl.Clock'); Clock.timerId = 3;rr}r(jYUjZjubaubjZ)r}r(jYUjZj<jbj jdj]jf}r(jh]ji]jj]jk]jn]ujpMIjqhjr]rj`)r}r(jYUjcKjZjjbj jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubeubj[)r}r(jYUjZjjbj jdjejf}r(jh]ji]jj]jk]rU semihostingrajn]rhaujpMMjqhjr]r(jt)r}r(jYX SemiHostingrjZjjbj jdjxjf}r(jh]ji]jj]jk]jn]ujpMMjqhjr]rj{X SemiHostingrr}r(jYjjZjubaubj[)r}r(jYUjZjjbj jdjejf}r(jh]ji]jj]jk]rU6why-can-t-i-see-output-of-system-printf-on-ccs-consolerajn]rhaujpMPjqhjr]r(jt)r}r(jYX7Why can`t I see output of System_printf on CCS console?rjZjjbj jdjxjf}r(jh]ji]jj]jk]jn]ujpMPjqhjr]rj{X7Why can`t I see output of System_printf on CCS console?rr}r(jYjjZjubaubj)r}r(jYXWhen getting started with TI RTOS, you may notice that the printf from your code goes to CCS console but using non-intrusive System_printf doesn`t. If you want to have System_printf output go to the same place as printf, add the following three lines to your .cfg file and re-build: ::jZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMRjqhjr]rj{XWhen getting started with TI RTOS, you may notice that the printf from your code goes to CCS console but using non-intrusive System_printf doesn`t. If you want to have System_printf output go to the same place as printf, add the following three lines to your .cfg file and re-build:rr}r(jYXWhen getting started with TI RTOS, you may notice that the printf from your code goes to CCS console but using non-intrusive System_printf doesn`t. If you want to have System_printf output go to the same place as printf, add the following three lines to your .cfg file and re-build:jZjubaubj)r}r(jYXvar System = xdc.useModule('xdc.runtime.System'); var SysStd = xdc.useModule('xdc.runtime.SysStd'); System.SupportProxy = SysStd;jZjjbj jdjjf}r(jjjk]jj]jh]ji]jn]ujpMjqhjr]rj{Xvar System = xdc.useModule('xdc.runtime.System'); var SysStd = xdc.useModule('xdc.runtime.SysStd'); System.SupportProxy = SysStd;rr}r(jYUjZjubaubjZ)r}r(jYUjZjjbj jdj]jf}r(jh]ji]jj]jk]jn]ujpMWjqhjr]rj`)r}r(jYUjcKjZjjbj jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r}r(jYXIf you don't do this, the output will go to a circular buffer in memory. You can examine that buffer using the ROV tool (use the menu: Tools->ROV while in the debugger).rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMXjqhjr]rj{XIf you don't do this, the output will go to a circular buffer in memory. You can examine that buffer using the ROV tool (use the menu: Tools->ROV while in the debugger).rr}r(jYjjZjubaubeubj[)r}r(jYUjZjjbj jdjejf}r(jh]ji]jj]jk]rUIhow-to-enable-printf-system-printf-to-go-to-ccs-io-console-on-arm-devicesrajn]rjaujpM[jqhjr]r(jt)r}r(jYXIHow to enable printf/System_printf to go to CCS IO console on ARM devicesrjZjjbj jdjxjf}r(jh]ji]jj]jk]jn]ujpM[jqhjr]rj{XIHow to enable printf/System_printf to go to CCS IO console on ARM devicesrr}r(jYjjZjubaubj)r}r(jYXApplication developers need to add the SemiHosting module to the .cfg manually by editing the config script. Add the following line: ::jZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpM\jqhjr]rj{XApplication developers need to add the SemiHosting module to the .cfg manually by editing the config script. Add the following line:rr}r(jYXApplication developers need to add the SemiHosting module to the .cfg manually by editing the config script. Add the following line:jZjubaubj)r}r(jYXJvar SemiHostSupport = xdc.useModule('ti.sysbios.rts.gnu.SemiHostSupport');jZjjbj jdjjf}r(jjjk]jj]jh]ji]jn]ujpM jqhjr]rj{XJvar SemiHostSupport = xdc.useModule('ti.sysbios.rts.gnu.SemiHostSupport');rr}r(jYUjZjubaubjZ)r}r(jYUjZjjbj jdj]jf}r(jh]ji]jj]jk]jn]ujpM_jqhjr]rj`)r}r(jYUjcKjZjjbj jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r}r(jYXvThis module does the required setup (install SVC_Handler and do the required file handle init) to support SemiHosting.rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpM`jqhjr]rj{XvThis module does the required setup (install SVC_Handler and do the required file handle init) to support SemiHosting.rr}r(jYjjZjubaubj)r}r(jYX7GNU GCC users on ARM platforms need to link to "rdimon" library to the "GNU Linker" -> "Libraries" view. If the "nosys" library is already listed in the "Libraries" view then replace it with "rdimon". This will cause the application to link with librdimon.a library which is a Semi-Hosting enabled BSP library.rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMbjqhjr]rj{X7GNU GCC users on ARM platforms need to link to "rdimon" library to the "GNU Linker" -> "Libraries" view. If the "nosys" library is already listed in the "Libraries" view then replace it with "rdimon". This will cause the application to link with librdimon.a library which is a Semi-Hosting enabled BSP library.rr}r(jYjjZjubaubeubeubj[)r}r(jYUjZjjbj jdjejf}r(jh]ji]jj]jk]rUexception-handlingrajn]rhaujpMfjqhjr]r(jt)r}r(jYXException HandlingrjZjjbj jdjxjf}r(jh]ji]jj]jk]jn]ujpMfjqhjr]r j{XException Handlingr r }r (jYjjZjubaubj[)r }r(jYUjZjjbj jdjejf}r(jh]ji]jj]jk]rU8how-can-i-get-dump-of-registers-when-an-exception-occursrajn]rhaujpMijqhjr]r(jt)r}r(jYX:How can I get dump of registers when an exception occurs ?rjZj jbj jdjxjf}r(jh]ji]jj]jk]jn]ujpMijqhjr]rj{X:How can I get dump of registers when an exception occurs ?rr}r(jYjjZjubaubj)r}r(jYX%If you add this to your .cfg file: ::jZj jbj jdjjf}r(jh]ji]jj]jk]jn]ujpMkjqhjr]rj{X"If you add this to your .cfg file:r r!}r"(jYX"If you add this to your .cfg file:jZjubaubj)r#}r$(jYX`var Exception = xdc.useModule('ti.sysbios.family.c64p.Exception'); Exception.enablePrint = true;jZj jbj jdjjf}r%(jjjk]jj]jh]ji]jn]ujpMjqhjr]r&j{X`var Exception = xdc.useModule('ti.sysbios.family.c64p.Exception'); Exception.enablePrint = true;r'r(}r)(jYUjZj#ubaubjZ)r*}r+(jYUjZj jbj jdj]jf}r,(jh]ji]jj]jk]jn]ujpMojqhjr]r-j`)r.}r/(jYUjcKjZj*jbj jdjpjf}r0(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r1}r2(jYXSYS/BIOS provides several target unique exception handlers: * ti.sysbios.family.arm.exc.Exception - used by all Arm9 and A8 targets * ti.sysbios.family.arm.m3.Hwi - used by all cortex-M3 targets * ti.sysbios.family.c64p.Exception - used by all C6x targetsr3jZj jbj jdjjf}r4(jh]ji]jj]jk]jn]ujpMqjqhjr]r5j{XSYS/BIOS provides several target unique exception handlers: * ti.sysbios.family.arm.exc.Exception - used by all Arm9 and A8 targets * ti.sysbios.family.arm.m3.Hwi - used by all cortex-M3 targets * ti.sysbios.family.c64p.Exception - used by all C6x targetsr6r7}r8(jYj3jZj1ubaubj)r9}r:(jYXa complete exception register context should be dumped to the console in addition to the Error raised by the exception handler when an exception occurs.r;jZj jbj jdjjf}r<(jh]ji]jj]jk]jn]ujpMvjqhjr]r=j{Xa complete exception register context should be dumped to the console in addition to the Error raised by the exception handler when an exception occurs.r>r?}r@(jYj;jZj9ubaubj)rA}rB(jYXGIf you set a breakpoint at "ti_sysbios_family_c64p_Hwi_int1", this is the function vectored to on all exceptions. No exception processing will have been performed at this point. Using CCS' register dump, you can see the complete state of the processor. The NRP register should contain the PC at the time the exception occurred.rCjZj jbj jdjjf}rD(jh]ji]jj]jk]jn]ujpMxjqhjr]rEj{XGIf you set a breakpoint at "ti_sysbios_family_c64p_Hwi_int1", this is the function vectored to on all exceptions. No exception processing will have been performed at this point. Using CCS' register dump, you can see the complete state of the processor. The NRP register should contain the PC at the time the exception occurred.rFrG}rH(jYjCjZjAubaubeubj[)rI}rJ(jYUjZjjbj jdjejf}rK(jh]ji]jj]jk]rLU6how-do-i-determine-the-call-stack-at-the-time-of-crashrMajn]rNhRaujpM|jqhjr]rO(jt)rP}rQ(jYX6How do I determine the call stack at the time of crashrRjZjIjbj jdjxjf}rS(jh]ji]jj]jk]jn]ujpM|jqhjr]rTj{X6How do I determine the call stack at the time of crashrUrV}rW(jYjRjZjPubaubj)rX}rY(jYXA detailed view of analyzing the call stack using CCS tools when your TI RTOS application throws an exception has been described in the article:rZjZjIjbj jdjjf}r[(jh]ji]jj]jk]jn]ujpM~jqhjr]r\j{XA detailed view of analyzing the call stack using CCS tools when your TI RTOS application throws an exception has been described in the article:r]r^}r_(jYjZjZjXubaubjC)r`}ra(jYUjZjIjbj jdj`jf}rb(jGX*jk]jj]jh]ji]jn]ujpMjqhjr]rcj/)rd}re(jYX`Exception_Dump_Decoding_Using_the_CCS_Register_View `__ jZj`jbj jdj2jf}rf(jh]ji]jj]jk]jn]ujpNjqhjr]rgj)rh}ri(jYX`Exception_Dump_Decoding_Using_the_CCS_Register_View `__rjjZjdjbj jdjjf}rk(jh]ji]jj]jk]jn]ujpMjr]rlj)rm}rn(jYjjjf}ro(UnameX3Exception_Dump_Decoding_Using_the_CCS_Register_ViewjXihttp://processors.wiki.ti.com/index.php/SYS/BIOS_FAQs#Exception_Dump_Decoding_Using_the_CCS_Register_Viewjk]jj]jh]ji]jn]ujZjhjr]rpj{X3Exception_Dump_Decoding_Using_the_CCS_Register_Viewrqrr}rs(jYUjZjmubajdjubaubaubaubeubj[)rt}ru(jYUjZjjbj jdjejf}rv(jh]ji]jj]jk]rwU)how-can-you-route-exception-print-to-uartrxajn]ryhaujpMjqhjr]rz(jt)r{}r|(jYX)How can you route exception print to UARTr}jZjtjbj jdjxjf}r~(jh]ji]jj]jk]jn]ujpMjqhjr]rj{X)How can you route exception print to UARTrr}r(jYj}jZj{ubaubj)r}r(jYX6The console I/O prints from TI-RTOS can be re-routed to UART. The console I/O messages are printed using the System module which can configured to call callback functions. These callback functions should be configured to write to UART. For example, in your .cfg add a configuration similar to the one below: ::jZjtjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{X3The console I/O prints from TI-RTOS can be re-routed to UART. The console I/O messages are printed using the System module which can configured to call callback functions. These callback functions should be configured to write to UART. For example, in your .cfg add a configuration similar to the one below:rr}r(jYX3The console I/O prints from TI-RTOS can be re-routed to UART. The console I/O messages are printed using the System module which can configured to call callback functions. These callback functions should be configured to write to UART. For example, in your .cfg add a configuration similar to the one below:jZjubaubj)r}r(jYXB/* ================ System configuration ================ */ var System = xdc.useModule('xdc.runtime.System'); var SysCallback = xdc.useModule('xdc.runtime.SysCallback'); SysCallback.abortFxn = "&myUARTAbort"; SysCallback.putchFxn = "&myUARTPutch"; SysCallback.readyFxn = "&myUARTReady"; System.SupportProxy = SysCallback;jZjtjbj jdjjf}r(jjjk]jj]jh]ji]jn]ujpM6jqhjr]rj{XB/* ================ System configuration ================ */ var System = xdc.useModule('xdc.runtime.System'); var SysCallback = xdc.useModule('xdc.runtime.SysCallback'); SysCallback.abortFxn = "&myUARTAbort"; SysCallback.putchFxn = "&myUARTPutch"; SysCallback.readyFxn = "&myUARTReady"; System.SupportProxy = SysCallback;rr}r(jYUjZjubaubjZ)r}r(jYUjZjtjbj jdj]jf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj`)r}r(jYUjcKjZjjbj jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r}r(jYXAnd define the functions myUARTAbort, myUARTPutch and myUARTReady in your application. For details about the SysCallback module's callback function signature, please see this link.rjZjtjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{XAnd define the functions myUARTAbort, myUARTPutch and myUARTReady in your application. For details about the SysCallback module's callback function signature, please see this link.rr}r(jYjjZjubaubj)r}r(jYXFor more details refer to the E2E discussion here: `Redirecting Exception logs to UART `__rjZjtjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]r(j{X3For more details refer to the E2E discussion here: rr}r(jYX3For more details refer to the E2E discussion here: jZjubj)r}r(jYXb`Redirecting Exception logs to UART `__jf}r(UnameX"Redirecting Exception logs to UARTjX9https://e2e.ti.com/support/embedded/tirtos/f/355/t/459864jk]jj]jh]ji]jn]ujZjjr]rj{X"Redirecting Exception logs to UARTrr}r(jYUjZjubajdjubeubeubeubj[)r}r(jYUjZjjbj jdjejf}r(jh]ji]jj]jk]rUlogging-and-tracerajn]rh|aujpMjqhjr]r(jt)r}r(jYXLogging and TracerjZjjbj jdjxjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{XLogging and Tracerr}r(jYjjZjubaubj[)r}r(jYUjZjjbj jdjejf}r(jh]ji]jj]jk]rU4how-get-uia-logging-working-with-ti-rtos-applicationrajn]rhxaujpMjqhjr]r(jt)r}r(jYX5How get UIA logging working with TI RTOS application?rjZjjbj jdjxjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{X5How get UIA logging working with TI RTOS application?rr}r(jYjjZjubaubj)r}r(jYXIn order to get the UIA loggging enabled, you need to include the UIA module and indicate the modules on which you would like obtain the logging information in your application. For example the following configuration will enable Load, Task, Swi and Hwi logging and will enable Task profiler so that you gain visual insight into the execution of the TI RTOS application using System analyzer tools in CCS: ::jZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{XIn order to get the UIA loggging enabled, you need to include the UIA module and indicate the modules on which you would like obtain the logging information in your application. For example the following configuration will enable Load, Task, Swi and Hwi logging and will enable Task profiler so that you gain visual insight into the execution of the TI RTOS application using System analyzer tools in CCS:rr}r(jYXIn order to get the UIA loggging enabled, you need to include the UIA module and indicate the modules on which you would like obtain the logging information in your application. For example the following configuration will enable Load, Task, Swi and Hwi logging and will enable Task profiler so that you gain visual insight into the execution of the TI RTOS application using System analyzer tools in CCS:jZjubaubj)r}r(jYXvar LoggingSetup = xdc.useModule('ti.uia.sysbios.LoggingSetup'); LoggingSetup.loadLogging = true; LoggingSetup.loadLoggerSize = 1024; LoggingSetup.mainLoggerSize = 32768; LoggingSetup.sysbiosLoggerSize = 32768; LoggingSetup.sysbiosSwiLogging = true; LoggingSetup.sysbiosHwiLogging = true; LoggingSetup.sysbiosSemaphoreLogging = true; LoggingSetup.loadTaskLogging = true; LoggingSetup.loadSwiLogging = true; LoggingSetup.loadHwiLogging = true; LoggingSetup.enableTaskProfiler = true; LoggingSetup.sysbiosHwiLoggingRuntimeControl = true; LoggingSetup.sysbiosSwiLoggingRuntimeControl = true; LoggingSetup.eventUploadMode = LoggingSetup.UploadMode_JTAGSTOPMODE;jZjjbj jdjjf}r(jjjk]jj]jh]ji]jn]ujpMJjqhjr]rj{Xvar LoggingSetup = xdc.useModule('ti.uia.sysbios.LoggingSetup'); LoggingSetup.loadLogging = true; LoggingSetup.loadLoggerSize = 1024; LoggingSetup.mainLoggerSize = 32768; LoggingSetup.sysbiosLoggerSize = 32768; LoggingSetup.sysbiosSwiLogging = true; LoggingSetup.sysbiosHwiLogging = true; LoggingSetup.sysbiosSemaphoreLogging = true; LoggingSetup.loadTaskLogging = true; LoggingSetup.loadSwiLogging = true; LoggingSetup.loadHwiLogging = true; LoggingSetup.enableTaskProfiler = true; LoggingSetup.sysbiosHwiLoggingRuntimeControl = true; LoggingSetup.sysbiosSwiLoggingRuntimeControl = true; LoggingSetup.eventUploadMode = LoggingSetup.UploadMode_JTAGSTOPMODE;rr}r(jYUjZjubaubjZ)r}r(jYUjZjjbj jdj]jf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj`)r}r(jYUjcKjZjjbj jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r}r(jYX**System analyzer view :**rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XSystem analyzer view :rr}r(jYUjZjubajdjubaubjB)r}r(jYX7.. Image:: ../images/System_Analyzer_Execution_log.png jZjjbj jdjEjf}r(UuriX0rtos/../images/System_Analyzer_Execution_log.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpMjqhjr]ubj)r}r(jYX**For more information refer to :** `System Analyzer wiki `__jZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]r(j)r}r(jYX#**For more information refer to :**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XFor more information refer to :rr}r(jYUjZjubajdjubj{X r}r(jYX jZjubj)r}r(jYX\`System Analyzer wiki `__jf}r(UnameXSystem Analyzer wikijXAhttp://processors.wiki.ti.com/index.php/Multicore_System_Analyzerjk]jj]jh]ji]jn]ujZjjr]rj{XSystem Analyzer wikirr}r(jYUjZjubajdjubeubj)r}r(jYXTo see how XGCONF graphical tool can be used to add Logging setup, refer to `TI RTOS User Section 2.2 `__r jZjjbj jdjjf}r (jh]ji]jj]jk]jn]ujpMjqhjr]r (j{XLTo see how XGCONF graphical tool can be used to add Logging setup, refer to r r }r(jYXLTo see how XGCONF graphical tool can be used to add Logging setup, refer to jZjubj)r}r(jYXM`TI RTOS User Section 2.2 `__jf}r(UnameXTI RTOS User Section 2.2jX.http://www.ti.com/lit/ug/spruhd4m/spruhd4m.pdfjk]jj]jh]ji]jn]ujZjjr]rj{XTI RTOS User Section 2.2rr}r(jYUjZjubajdjubeubeubj[)r}r(jYUjZjjbj jdjejf}r(jh]ji]jj]jk]rU/what-sys-bios-debugging-tools-do-we-have-in-ccsrajn]rh8aujpMjqhjr]r(jt)r}r(jYX1What SYS/BIOS Debugging Tools do we have in CCS ?rjZjjbj jdjxjf}r (jh]ji]jj]jk]jn]ujpMjqhjr]r!j{X1What SYS/BIOS Debugging Tools do we have in CCS ?r"r#}r$(jYjjZjubaubjC)r%}r&(jYUjZjjbj jdj`jf}r'(jGX*jk]jj]jh]ji]jn]ujpMjqhjr]r((j/)r)}r*(jYXReal Time analysis(RTA) agent jZj%jbj jdj2jf}r+(jh]ji]jj]jk]jn]ujpNjqhjr]r,j)r-}r.(jYXReal Time analysis(RTA) agentr/jZj)jbj jdjjf}r0(jh]ji]jj]jk]jn]ujpMjr]r1j{XReal Time analysis(RTA) agentr2r3}r4(jYj/jZj-ubaubaubj/)r5}r6(jYXRTOS Object View(ROV) jZj%jbj jdj2jf}r7(jh]ji]jj]jk]jn]ujpNjqhjr]r8j)r9}r:(jYXRTOS Object View(ROV)r;jZj5jbj jdjjf}r<(jh]ji]jj]jk]jn]ujpMjr]r=j{XRTOS Object View(ROV)r>r?}r@(jYj;jZj9ubaubaubeubeubj[)rA}rB(jYUjZjjbj jdjejf}rC(jh]ji]jj]jk]rDUreal-time-analysis-rta-agentrEajn]rFhLaujpMjqhjr]rG(jt)rH}rI(jYXReal Time analysis(RTA) agentrJjZjAjbj jdjxjf}rK(jh]ji]jj]jk]jn]ujpMjqhjr]rLj{XReal Time analysis(RTA) agentrMrN}rO(jYjJjZjHubaubj)rP}rQ(jYX"**Note:** Before Debugging the SYSBIOS Debugging options. It is recommended to set the Preferences under the Windows Tab in CCS to select the version of SYSBIOS, XDCTOOLS in Windows->Preferences->General->RTSC Options. Additionally set IPC and XDAIS if your application uses the components.rRjZjAjbj jdjjf}rS(jh]ji]jj]jk]jn]ujpMjqhjr]rT(j)rU}rV(jYX **Note:**jf}rW(jh]ji]jj]jk]jn]ujZjPjr]rXj{XNote:rYrZ}r[(jYUjZjUubajdjubj{X Before Debugging the SYSBIOS Debugging options. It is recommended to set the Preferences under the Windows Tab in CCS to select the version of SYSBIOS, XDCTOOLS in Windows->Preferences->General->RTSC Options. Additionally set IPC and XDAIS if your application uses the components.r\r]}r^(jYX Before Debugging the SYSBIOS Debugging options. It is recommended to set the Preferences under the Windows Tab in CCS to select the version of SYSBIOS, XDCTOOLS in Windows->Preferences->General->RTSC Options. Additionally set IPC and XDAIS if your application uses the components.jZjPubeubj%)r_}r`(jYUjZjAjbj jdj(jf}ra(j*U.jk]jj]jh]j+Uji]jn]j,j-ujpMjqhjr]rb(j/)rc}rd(jYXMReal time analysis can easily be turned on in a SYSBIOS based CCS project using the Grace tools. Select the configuration file (.cfg) in your project this will open an available Resources view inside SYSBIOS. Under diagnostics, select the RTA agent and enable it and save the configuration. Rebuild the project with the new settings.rejZj_jbj jdj2jf}rf(jh]ji]jj]jk]jn]ujpNjqhjr]rgj)rh}ri(jYjejZjcjbj jdjjf}rj(jh]ji]jj]jk]jn]ujpMjr]rkj{XMReal time analysis can easily be turned on in a SYSBIOS based CCS project using the Grace tools. Select the configuration file (.cfg) in your project this will open an available Resources view inside SYSBIOS. Under diagnostics, select the RTA agent and enable it and save the configuration. Rebuild the project with the new settings.rlrm}rn(jYjejZjhubaubaubj/)ro}rp(jYXTo run your project, choose **Target Debug Active Project** from the CCS menus. If this is the first time you are debugging a project for your target, you may need to set up a CCS Target Configuration. See the CCS help for details.rqjZj_jbj jdj2jf}rr(jh]ji]jj]jk]jn]ujpNjqhjr]rsj)rt}ru(jYjqjZjojbj jdjjf}rv(jh]ji]jj]jk]jn]ujpMjr]rw(j{XTo run your project, choose rxry}rz(jYXTo run your project, choose jZjtubj)r{}r|(jYX**Target Debug Active Project**jf}r}(jh]ji]jj]jk]jn]ujZjtjr]r~j{XTarget Debug Active Projectrr}r(jYUjZj{ubajdjubj{X from the CCS menus. If this is the first time you are debugging a project for your target, you may need to set up a CCS Target Configuration. See the CCS help for details.rr}r(jYX from the CCS menus. If this is the first time you are debugging a project for your target, you may need to set up a CCS Target Configuration. See the CCS help for details.jZjtubeubaubj/)r}r(jYXIn the Debug perspective, open the Runtime Object Viewer (ROV) tool by choosing **Tools ROV**. Also open the Raw Logs view by choosing **Tools RTA Raw Logs**. These tools allow you to see the activity of RTSC and SYS/BIOS modules.rjZj_jbj jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]r(j{XPIn the Debug perspective, open the Runtime Object Viewer (ROV) tool by choosing rr}r(jYXPIn the Debug perspective, open the Runtime Object Viewer (ROV) tool by choosing jZjubj)r}r(jYX **Tools ROV**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X Tools ROVrr}r(jYUjZjubajdjubj{X*. Also open the Raw Logs view by choosing rr}r(jYX*. Also open the Raw Logs view by choosing jZjubj)r}r(jYX**Tools RTA Raw Logs**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XTools RTA Raw Logsrr}r(jYUjZjubajdjubj{XI. These tools allow you to see the activity of RTSC and SYS/BIOS modules.rr}r(jYXI. These tools allow you to see the activity of RTSC and SYS/BIOS modules.jZjubeubaubj/)r}r(jYXSet some breakpoints in the log.c source file. (You can do this by right-clicking on a line and choosing **New Breakpoint > Breakpoint**.) For example, set a breakpoint on the last line of each function in log.c.rjZj_jbj jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]r(j{XiSet some breakpoints in the log.c source file. (You can do this by right-clicking on a line and choosing rr}r(jYXiSet some breakpoints in the log.c source file. (You can do this by right-clicking on a line and choosing jZjubj)r}r(jYX"**New Breakpoint > Breakpoint**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XNew Breakpoint > Breakpointrr}r(jYUjZjubajdjubj{XL.) For example, set a breakpoint on the last line of each function in log.c.rr}r(jYXL.) For example, set a breakpoint on the last line of each function in log.c.jZjubeubaubj/)r}r(jYXRun the application.rjZj_jbj jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XRun the application.rr}r(jYjjZjubaubaubj/)r}r(jYXIn the Raw Logs window, you can see the informational, warning, and error messages sent by the calls to Log module APIs in log.c. The messages that begin with **LM** are diagnostics provided by XDCtools. Messages that begin with “WARNING” come from calls to Log_warning2. Messages that begin with “ERROR” come from calls to Log_error2. Messages that begin with “../log.c” come from calls to Log_info0 and Log_info2 (depending on the number of arguments). jZj_jbj jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXIn the Raw Logs window, you can see the informational, warning, and error messages sent by the calls to Log module APIs in log.c. The messages that begin with **LM** are diagnostics provided by XDCtools. Messages that begin with “WARNING” come from calls to Log_warning2. Messages that begin with “ERROR” come from calls to Log_error2. Messages that begin with “../log.c” come from calls to Log_info0 and Log_info2 (depending on the number of arguments).jZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]r(j{XIn the Raw Logs window, you can see the informational, warning, and error messages sent by the calls to Log module APIs in log.c. The messages that begin with rr}r(jYXIn the Raw Logs window, you can see the informational, warning, and error messages sent by the calls to Log module APIs in log.c. The messages that begin with jZjubj)r}r(jYX**LM**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XLMrr}r(jYUjZjubajdjubj{X2 are diagnostics provided by XDCtools. Messages that begin with “WARNING” come from calls to Log_warning2. Messages that begin with “ERROR” come from calls to Log_error2. Messages that begin with “../log.c” come from calls to Log_info0 and Log_info2 (depending on the number of arguments).rr}r(jYX2 are diagnostics provided by XDCtools. Messages that begin with “WARNING” come from calls to Log_warning2. Messages that begin with “ERROR” come from calls to Log_error2. Messages that begin with “../log.c” come from calls to Log_info0 and Log_info2 (depending on the number of arguments).jZjubeubaubeubjB)r}r(jYX:.. Image:: ../images/SYSBIOS_Diag.jpg :scale: 50 %jZjAjbj jdjEjf}r(UscaleK2UuriXrtos/../images/SYSBIOS_Diag.jpgrjk]jj]jh]ji]jH}rU*jsjn]ujpNjqhjr]ubjB)r}r(jYX<.. Image:: ../images/SYSBIOS_Rawlog.jpg :scale: 50 %jZjAjbj jdjEjf}r(UscaleK2UuriX!rtos/../images/SYSBIOS_Rawlog.jpgrjk]jj]jh]ji]jH}rU*jsjn]ujpNjqhjr]ubjB)r}r(jYX".. Image:: ../images/Rta_exec2.pngrjZjAjbj jdjEjf}r(UuriXrtos/../images/Rta_exec2.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpMjqhjr]ubjB)r}r(jYX>.. Image:: ../images/SYSBIOS_CPUload.jpg :scale: 50 % jZjAjbj jdjEjf}r(UscaleK2UuriX"rtos/../images/SYSBIOS_CPUload.jpgrjk]jj]jh]ji]jH}rU*jsjn]ujpNjqhjr]ubj)r}r(jYXFor advanced debugging options we recommend following the instructions on the `BIOS_6_Real-Time_Analysis_(RTA)_in_CCSv4 `__ wikirjZjAjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]r(j{XNFor advanced debugging options we recommend following the instructions on the rr}r(jYXNFor advanced debugging options we recommend following the instructions on the jZjubj)r}r(jYX`BIOS_6_Real-Time_Analysis_(RTA)_in_CCSv4 `__jf}r(UnameX(BIOS_6_Real-Time_Analysis_(RTA)_in_CCSv4jXPhttp://processors.wiki.ti.com/index.php/BIOS_6_Real-Time_Analysis_(RTA)_in_CCSv4jk]jj]jh]ji]jn]ujZjjr]rj{X(BIOS_6_Real-Time_Analysis_(RTA)_in_CCSv4rr}r(jYUjZjubajdjubj{X wikirr}r(jYX wikijZjubeubeubj[)r}r(jYUjZjjbj jdjejf}r(jh]ji]jj]jk]rUrtos-object-view-rovrajn]rj4aujpMjqhjr]r (jt)r }r (jYXRTOS Object View(ROV)r jZjjbj jdjxjf}r (jh]ji]jj]jk]jn]ujpMjqhjr]rj{XRTOS Object View(ROV)rr}r(jYj jZj ubaubj%)r}r(jYUjZjjbj jdj(jf}r(j*U.jk]jj]jh]j+Uji]jn]j,j-ujpMjqhjr]r(j/)r}r(jYX\Load your application for debugging. Select the device you want to debug before opening ROV.rjZjjbj jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{X\Load your application for debugging. Select the device you want to debug before opening ROV.rr }r!(jYjjZjubaubaubj/)r"}r#(jYXIn the ROV window, expand the tree to see the ti.sysbios.knl.Task module. The right pane shows a list of the Task threads in the application. As you advance from breakpoint to breakpoint, you see the run mode of the threads change. jZjjbj jdj2jf}r$(jh]ji]jj]jk]jn]ujpNjqhjr]r%j)r&}r'(jYXIn the ROV window, expand the tree to see the ti.sysbios.knl.Task module. The right pane shows a list of the Task threads in the application. As you advance from breakpoint to breakpoint, you see the run mode of the threads change.r(jZj"jbj jdjjf}r)(jh]ji]jj]jk]jn]ujpMjr]r*j{XIn the ROV window, expand the tree to see the ti.sysbios.knl.Task module. The right pane shows a list of the Task threads in the application. As you advance from breakpoint to breakpoint, you see the run mode of the threads change.r+r,}r-(jYj(jZj&ubaubaubeubjB)r.}r/(jYX$.. Image:: ../images/1.7.6_Image.pngr0jZjjbj jdjEjf}r1(UuriXrtos/../images/1.7.6_Image.pngr2jk]jj]jh]ji]jH}r3U*j2sjn]ujpMjqhjr]ubcdocutils.nodes field_list r4)r5}r6(jYUjZjjbj jdU field_listr7jf}r8(jh]ji]jj]jk]jn]ujpMjqhjr]r9cdocutils.nodes field r:)r;}r<(jYUjZj5jbj jdUfieldr=jf}r>(jh]ji]jj]jk]jn]ujpMjqhjr]r?(cdocutils.nodes field_name r@)rA}rB(jYXscalerCjf}rD(jh]ji]jj]jk]jn]ujZj;jr]rEj{XscalerFrG}rH(jYjCjZjAubajdU field_namerIubcdocutils.nodes field_body rJ)rK}rL(jYX50 % jf}rM(jh]ji]jj]jk]jn]ujZj;jr]rNj)rO}rP(jYX50 %rQjZjKjbj jdjjf}rR(jh]ji]jj]jk]jn]ujpMjr]rSj{X50 %rTrU}rV(jYjQjZjOubaubajdU field_bodyrWubeubaubj)rX}rY(jYXFor more details on ROV tools, refer to the `Runtime Object Viewer(ROV) `__ article on RTSC website.rZjZjjbj jdjjf}r[(jh]ji]jj]jk]jn]ujpMjqhjr]r\(j{X,For more details on ROV tools, refer to the r]r^}r_(jYX,For more details on ROV tools, refer to the jZjXubj)r`}ra(jYXW`Runtime Object Viewer(ROV) `__jf}rb(UnameXRuntime Object Viewer(ROV)jX6http://rtsc.eclipse.org/docs-tip/Runtime_Object_Viewerjk]jj]jh]ji]jn]ujZjXjr]rcj{XRuntime Object Viewer(ROV)rdre}rf(jYUjZj`ubajdjubj{X article on RTSC website.rgrh}ri(jYX article on RTSC website.jZjXubeubeubeubj[)rj}rk(jYUjZjjbj jdjejf}rl(jh]ji]jj]jk]rmUmemory-and-heaprnajn]roj#aujpMjqhjr]rp(jt)rq}rr(jYXMemory and HeaprsjZjjjbj jdjxjf}rt(jh]ji]jj]jk]jn]ujpMjqhjr]ruj{XMemory and Heaprvrw}rx(jYjsjZjqubaubj[)ry}rz(jYUjZjjjbj jdjejf}r{(jh]ji]jj]jk]r|Udwhat-kind-of-heap-should-i-use-in-sysbios-application-and-how-do-i-allocate-heap-in-my-configurationr}ajn]r~haujpMjqhjr]r(jt)r}r(jYXdWhat kind of heap should I use in SYSBIOS application and how do I allocate Heap in my configurationrjZjyjbj jdjxjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{XdWhat kind of heap should I use in SYSBIOS application and how do I allocate Heap in my configurationrr}r(jYjjZjubaubj)r}r(jYX<SYSBIOS Supports five different type of Heap implementation:rjZjyjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{X<SYSBIOS Supports five different type of Heap implementation:rr}r(jYjjZjubaubjC)r}r(jYUjZjyjbj jdj`jf}r(jGX*jk]jj]jh]ji]jn]ujpMjqhjr]r(j/)r}r(jYXHeapMin. Very small code footprint implementation. Supports non blocking memory allocation, but does not support freeing memory.rjZjjbj jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XHeapMin. Very small code footprint implementation. Supports non blocking memory allocation, but does not support freeing memory.rr}r(jYjjZjubaubaubj/)r}r(jYXHeapMem. Allocate variable-size blocks and uses Gate module to protect allocation and freeing of memory. typically Slower and non-deterministicrjZjjbj jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XHeapMem. Allocate variable-size blocks and uses Gate module to protect allocation and freeing of memory. typically Slower and non-deterministicrr}r(jYjjZjubaubaubj/)r}r(jYXfHeapBuf. Allocate fixed-size blocks. Fast deterministic and non-blocking as allocation uses same size.rjZjjbj jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XfHeapBuf. Allocate fixed-size blocks. Fast deterministic and non-blocking as allocation uses same size.rr}r(jYjjZjubaubaubj/)r}r(jYXHeapMultiBuf. Specify variable-size allocation, but internally allocate from a variety of fixed-size blocks. Good tradeoff for HeapMem and HeapBufrjZjjbj jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XHeapMultiBuf. Specify variable-size allocation, but internally allocate from a variety of fixed-size blocks. Good tradeoff for HeapMem and HeapBufrr}r(jYjjZjubaubaubj/)r}r(jYXHeapTrack. Used to detect memory allocation and deallocation problems. Good for debugging as it detects memory leaks and buffer overflows. jZjjbj jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXHeapTrack. Used to detect memory allocation and deallocation problems. Good for debugging as it detects memory leaks and buffer overflows.rjZjjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XHeapTrack. Used to detect memory allocation and deallocation problems. Good for debugging as it detects memory leaks and buffer overflows.rr}r(jYjjZjubaubaubeubj)r}r(jYXRTypical allocation of static heap within the SYSBIOS *.cfg file is shown below: ::jZjyjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]r(j{X5Typical allocation of static heap within the SYSBIOS rr}r(jYX5Typical allocation of static heap within the SYSBIOS jZjubj)r}r(jYX*jf}r(jk]rUid28rajj]jh]ji]jn]UrefidUid27rujZjjr]rj{X*r}r(jYUjZjubajdjubj{X.cfg file is shown below:rr}r(jYX.cfg file is shown below:jZjubeubj)r}r(jYXvar HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem'); /* Create a Heap. */ var heapMemParams = new HeapMem.Params(); heapMemParams.size = 0x8000000; // <-- edit this value to tune the size of the heap heapMemParams.sectionName = "systemHeapMaster"; Program.global.heap0 = HeapMem.create(heapMemParams); Memory.defaultHeapInstance = Program.global.heap0;jZjyjbj jdjjf}r(jjjk]jj]jh]ji]jn]ujpMjqhjr]rj{Xvar HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem'); /* Create a Heap. */ var heapMemParams = new HeapMem.Params(); heapMemParams.size = 0x8000000; // <-- edit this value to tune the size of the heap heapMemParams.sectionName = "systemHeapMaster"; Program.global.heap0 = HeapMem.create(heapMemParams); Memory.defaultHeapInstance = Program.global.heap0;rr}r(jYUjZjubaubjZ)r}r(jYUjZjyjbj jdj]jf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj`)r}r(jYUjcKjZjjbj jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubeubj[)r}r(jYUjZjjbj jdjejf}r(jh]ji]jj]jk]rU benchmarksrajn]rhaujpMjqhjr]r(jt)r}r(jYX BenchmarksrjZjjbj jdjxjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{X Benchmarksrr}r(jYjjZjubaubj[)r}r(jYUjZjjbj jdjejf}r(jh]ji]jj]jk]rUtwhere-can-i-find-memory-foot-print-interrupt-latency-and-performance-numbers-of-the-ti-rtos-when-designing-my-systemrajn]rhaujpMjqhjr]r(jt)r}r(jYXuWhere can I find Memory foot print, Interrupt latency and performance numbers of the TI RTOS when designing my systemr jZjjbj jdjxjf}r (jh]ji]jj]jk]jn]ujpMjqhjr]r j{XuWhere can I find Memory foot print, Interrupt latency and performance numbers of the TI RTOS when designing my systemr r }r(jYj jZjubaubj )r}r(jYUjZjjbj jdj3 jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj )r}r(jYXThe Memory footprint and Interrupt latency for different processor architectures is provided in the SYSBIOS package. It can be located at bios_6_xx_xx_xx/packages/ti/sysbios/benchmarks/doc-files jZjjbj jdj jf}r(jh]ji]jj]jk]jn]ujpMjr]r(j )r}r(jYXThe Memory footprint and Interrupt latency for different processor architectures is provided in the SYSBIOS package. It can be located atrjZjjbj jdj jf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XThe Memory footprint and Interrupt latency for different processor architectures is provided in the SYSBIOS package. It can be located atrr}r(jYjjZjubaubj )r}r (jYUjf}r!(jh]ji]jj]jk]jn]ujZjjr]r"j)r#}r$(jYX8bios_6_xx_xx_xx/packages/ti/sysbios/benchmarks/doc-filesr%jZjjbj jdjjf}r&(jh]ji]jj]jk]jn]ujpMjr]r'j{X8bios_6_xx_xx_xx/packages/ti/sysbios/benchmarks/doc-filesr(r)}r*(jYj%jZj#ubaubajdj2 ubeubaubj)r+}r,(jYX7The Foot print of the OS depends on number of BIOS kernel modules used by the application but an estimate of the foot print can be computed by adding up the module footprint numbers to the base kernel footprint. The interrupt latency is mostly deterministic in the system but OS response may depend on priority of the interrupt setup. If the 2 or more interrupts occur simultaneously, the premptive BIOS scheduler will let the higher HWI to run before letting the one with lower priority so it may seem as the the lower priority interrupt response is slightly slower.r-jZjjbj jdjjf}r.(jh]ji]jj]jk]jn]ujpMjqhjr]r/j{X7The Foot print of the OS depends on number of BIOS kernel modules used by the application but an estimate of the foot print can be computed by adding up the module footprint numbers to the base kernel footprint. The interrupt latency is mostly deterministic in the system but OS response may depend on priority of the interrupt setup. If the 2 or more interrupts occur simultaneously, the premptive BIOS scheduler will let the higher HWI to run before letting the one with lower priority so it may seem as the the lower priority interrupt response is slightly slower.r0r1}r2(jYj-jZj+ubaubeubeubj[)r3}r4(jYUjZjjbj jdjejf}r5(jh]ji]jj]jk]r6U debuggingr7ajn]r8haujpMjqhjr]r9(jt)r:}r;(jYX Debuggingr<jZj3jbj jdjxjf}r=(jh]ji]jj]jk]jn]ujpMjqhjr]r>j{X Debuggingr?r@}rA(jYj<jZj:ubaubj[)rB}rC(jYUjZj3jbj jdjejf}rD(jh]ji]jj]jk]rEUUhow-to-debug-common-application-issues-like-stack-overflow-exception-and-memory-leaksrFajn]rGhaujpMjqhjr]rH(jt)rI}rJ(jYXVHow to debug common application issues like stack overflow, exception and memory leaksrKjZjBjbj jdjxjf}rL(jh]ji]jj]jk]jn]ujpMjqhjr]rMj{XVHow to debug common application issues like stack overflow, exception and memory leaksrNrO}rP(jYjKjZjIubaubj)rQ}rR(jYXCommon Application debug scenarios like exception management, memory leak and stack issues have been described in the following training video: `Debugging Common Application Issues TI RTOS `__jZjBjbj jdjjf}rS(jh]ji]jj]jk]jn]ujpM jqhjr]rT(j{XCommon Application debug scenarios like exception management, memory leak and stack issues have been described in the following training video: rUrV}rW(jYXCommon Application debug scenarios like exception management, memory leak and stack issues have been described in the following training video: jZjQubj)rX}rY(jYXu`Debugging Common Application Issues TI RTOS `__jf}rZ(UnameX+Debugging Common Application Issues TI RTOSjXChttps://training.ti.com/debugging-common-application-issues-ti-rtosjk]jj]jh]ji]jn]ujZjQjr]r[j{X+Debugging Common Application Issues TI RTOSr\r]}r^(jYUjZjXubajdjubeubj)r_}r`(jYXThe training covers stack over flow, exception handling and memory management issues in detail with a Lab for TI MCU devices but the same concepts and features also apply for TI ARM and DSP processors.rajZjBjbj jdjjf}rb(jh]ji]jj]jk]jn]ujpM jqhjr]rcj{XThe training covers stack over flow, exception handling and memory management issues in detail with a Lab for TI MCU devices but the same concepts and features also apply for TI ARM and DSP processors.rdre}rf(jYjajZj_ubaubeubj[)rg}rh(jYUjZj3jbj jdjejf}ri(jh]ji]jj]jk]rjU@how-to-add-custom-compiler-options-and-build-custom-bios-libraryrkajn]rlhpaujpMjqhjr]rm(jt)rn}ro(jYXAHow to add Custom compiler options and build custom BIOS libraryrpjZjgjbj jdjxjf}rq(jh]ji]jj]jk]jn]ujpMjqhjr]rrj{XAHow to add Custom compiler options and build custom BIOS libraryrsrt}ru(jYjpjZjnubaubj)rv}rw(jYX}Users are allowed to change the libType and specify the compiler options from their BIOS configuration using the following ::jZjgjbj jdjjf}rx(jh]ji]jj]jk]jn]ujpMjqhjr]ryj{XzUsers are allowed to change the libType and specify the compiler options from their BIOS configuration using the followingrzr{}r|(jYXzUsers are allowed to change the libType and specify the compiler options from their BIOS configuration using the followingjZjvubaubj)r}}r~(jYXBIOS.libType = BIOS.LibType_Custom; // For Cortex A8 device like AM335x BIOS.customCCOpts = "--endian=little -mv7A8 --abi=eabi --neon --float_support=vfpv3 -q -ms --program_level_compile -o3 --opt_for_speed=3" // For Cortex A9 device like AM437x BIOS.customCCOpts ="-mcpu=cortex-a9 -mfpu=neon -mfloat-abi=hard -mabi=aapcs -O3 -Wunused -Wunknown-pragmas -ffunction-sections -fdata-sections -g "jZjgjbj jdjjf}r(jjjk]jj]jh]ji]jn]ujpMjqhjr]rj{XBIOS.libType = BIOS.LibType_Custom; // For Cortex A8 device like AM335x BIOS.customCCOpts = "--endian=little -mv7A8 --abi=eabi --neon --float_support=vfpv3 -q -ms --program_level_compile -o3 --opt_for_speed=3" // For Cortex A9 device like AM437x BIOS.customCCOpts ="-mcpu=cortex-a9 -mfpu=neon -mfloat-abi=hard -mabi=aapcs -O3 -Wunused -Wunknown-pragmas -ffunction-sections -fdata-sections -g "rr}r(jYUjZj}ubaubjZ)r}r(jYUjZjgjbj jdj]jf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj`)r}r(jYUjcKjZjjbj jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r}r(jYX3To remove a given compiler setting, you can use: ::jZjgjbj jdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{X0To remove a given compiler setting, you can use:rr}r(jYX0To remove a given compiler setting, you can use:jZjubaubj)r}r(jYX9BIOS.customCCOpts = BIOS.customCCOpts.replace(" -g ","");jZjgjbj jdjjf}r(jjjk]jj]jh]ji]jn]ujpMjqhjr]rj{X9BIOS.customCCOpts = BIOS.customCCOpts.replace(" -g ","");rr}r(jYUjZjubaubjZ)r}r(jYUjZjgjbj jdj]jf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj`)r}r(jYUjcKjZjjbj jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubeubeubeubj[)r}r(jYUjZjjbjcjdjejf}r(jh]ji]jj]jk]rUflashing-and-bootrajn]rh=aujpK[SDK Install Path]/processor_sdk_rtos__/binjZjjbjjdjjf}r(jjjk]jj]jh]ji]jn]ujpMjqhjr]rj{X>[SDK Install Path]/processor_sdk_rtos__/binrr}r(jYUjZjubaubj)r}r(jYXmnamed **program_evm.js**. The purpose of this script is to automatically flash bootable images onto your EVM.jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK jqhjr]r(j{Xnamed rr}r(jYXnamed jZjubj)r}r(jYX**program_evm.js**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{Xprogram_evm.jsrr}r(jYUjZjubajdjubj{XU. The purpose of this script is to automatically flash bootable images onto your EVM.rr}r(jYXU. The purpose of this script is to automatically flash bootable images onto your EVM.jZjubeubj)r}r(jYXyThe following sections will describe how to use this script and the default flashable binaries in the Processor SDK RTOS.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XyThe following sections will describe how to use this script and the default flashable binaries in the Processor SDK RTOS.rr}r(jYjjZjubaubeubj[)r}r(jYUjZjjbjjdjejf}r(jh]ji]jj]jk]rU requirementsrajn]rh`aujpKjqhjr]r(jt)r}r(jYX Requirementsr jZjjbjjdjxjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r j{X Requirementsr r }r(jYj jZjubaubjC)r}r(jYUjZjjbjjdj`jf}r(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]r(j/)r}r(jYXA Windows or Linux PCrjZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XA Windows or Linux PCrr}r(jYjjZjubaubaubj/)r}r (jYXbProcessor SDK RTOS installed on your PC. The version to install must match the SOC you plan to usejZjjbjjdj2jf}r!(jh]ji]jj]jk]jn]ujpNjqhjr]r"j)r#}r$(jYXbProcessor SDK RTOS installed on your PC. The version to install must match the SOC you plan to user%jZjjbjjdjjf}r&(jh]ji]jj]jk]jn]ujpKjr]r'j{XbProcessor SDK RTOS installed on your PC. The version to install must match the SOC you plan to user(r)}r*(jYj%jZj#ubaubaubj/)r+}r,(jYX)Code Composer Studio installed on your PCr-jZjjbjjdj2jf}r.(jh]ji]jj]jk]jn]ujpNjqhjr]r/j)r0}r1(jYj-jZj+jbjjdjjf}r2(jh]ji]jj]jk]jn]ujpKjr]r3j{X)Code Composer Studio installed on your PCr4r5}r6(jYj-jZj0ubaubaubj/)r7}r8(jYX'An USB connection to your EVM emulator jZjjbjjdj2jf}r9(jh]ji]jj]jk]jn]ujpNjqhjr]r:j)r;}r<(jYX&An USB connection to your EVM emulatorr=jZj7jbjjdjjf}r>(jh]ji]jj]jk]jn]ujpKjr]r?j{X&An USB connection to your EVM emulatorr@rA}rB(jYj=jZj;ubaubaubeubj)rC}rD(jYXYour board should be set to NO-BOOT mode. Please refer to the boot mode dip switch settings for different boot modes on your EVM Hardware User Guide. See `this page `__ for a link to all supported EVM information.jZjjbjjdjjf}rE(jh]ji]jj]jk]jn]ujpNjqhjr]rFj)rG}rH(jYXYour board should be set to NO-BOOT mode. Please refer to the boot mode dip switch settings for different boot modes on your EVM Hardware User Guide. See `this page `__ for a link to all supported EVM information.jZjCjbjjdjjf}rI(jh]ji]jj]jk]jn]ujpKjr]rJ(j{XYour board should be set to NO-BOOT mode. Please refer to the boot mode dip switch settings for different boot modes on your EVM Hardware User Guide. See rKrL}rM(jYXYour board should be set to NO-BOOT mode. Please refer to the boot mode dip switch settings for different boot modes on your EVM Hardware User Guide. See jZjGubj)rN}rO(jYXL`this page `__jf}rP(UnameX this pagejX<index_release_specific.html#supported-platforms-and-versionsjk]jj]jh]ji]jn]ujZjGjr]rQj{X this pagerRrS}rT(jYUjZjNubajdjubj{X- for a link to all supported EVM information.rUrV}rW(jYX- for a link to all supported EVM information.jZjGubeubaubeubj[)rX}rY(jYUjZjjbjjdjejf}rZ(jh]ji]jj]jk]r[Udirectory-structurer\ajn]r]hkaujpK#jqhjr]r^(jt)r_}r`(jYXDirectory StructurerajZjXjbjjdjxjf}rb(jh]ji]jj]jk]jn]ujpK#jqhjr]rcj{XDirectory Structurerdre}rf(jYjajZj_ubaubj)rg}rh(jYXThe files used are in the Processor SDK RTOS directory. Expanded below are the relevant files and directories for flashing the bootable images for C667x, but a similar structure is used for C665x.rijZjXjbjjdjjf}rj(jh]ji]jj]jk]jn]ujpK%jqhjr]rkj{XThe files used are in the Processor SDK RTOS directory. Expanded below are the relevant files and directories for flashing the bootable images for C667x, but a similar structure is used for C665x.rlrm}rn(jYjijZjgubaubj)ro}rp(jYX├── bin │ ├── configs │ │ └── evm6678l │ │ ├── evm6678l.ccxml │ │ ├── evm6678le.ccxml │ │ ├── evm6678le-linuxhost.ccxml │ │ └── evm6678l-linuxhost.ccxml │ ├── logs │ └── program_evm.js └── prebuilt-images ├── eeprom50.bin ├── eeprom51.bin ├── eepromwriter_evm6678l.out ├── eepromwriter_input50.txt ├── eepromwriter_input51.txt ├── eepromwriter_input.txt ├── nandwriter_evm6678l.out ├── nand_writer_input.txt ├── norwriter_evm6678l.out └── nor_writer_input.txtjZjXjbjjdjjf}rq(jjjk]jj]jh]ji]jn]ujpMjqhjr]rrj{X├── bin │ ├── configs │ │ └── evm6678l │ │ ├── evm6678l.ccxml │ │ ├── evm6678le.ccxml │ │ ├── evm6678le-linuxhost.ccxml │ │ └── evm6678l-linuxhost.ccxml │ ├── logs │ └── program_evm.js └── prebuilt-images ├── eeprom50.bin ├── eeprom51.bin ├── eepromwriter_evm6678l.out ├── eepromwriter_input50.txt ├── eepromwriter_input51.txt ├── eepromwriter_input.txt ├── nandwriter_evm6678l.out ├── nand_writer_input.txt ├── norwriter_evm6678l.out └── nor_writer_input.txtrsrt}ru(jYUjZjoubaubj)rv}rw(jYXUBelow is the expanded tree for K2H. Similarly, this also applies to K2E and K2L EVMs.rxjZjXjbjjdjjf}ry(jh]ji]jj]jk]jn]ujpK@jqhjr]rzj{XUBelow is the expanded tree for K2H. Similarly, this also applies to K2E and K2L EVMs.r{r|}r}(jYjxjZjvubaubj)r~}r(jYXq├── bin │ ├── configs │ │ └── evmk2h │ │ ├── evmk2h.ccxml │ │ ├── evmk2h-linuxhost.ccxml │ │ └── program_evm_config │ ├── logs │ └── program_evm.js └── prebuilt-images ├── app ├── config ├── MLO └── spi_flash_writer.outjZjXjbjjdjjf}r(jjjk]jj]jh]ji]jn]ujpM jqhjr]rj{Xq├── bin │ ├── configs │ │ └── evmk2h │ │ ├── evmk2h.ccxml │ │ ├── evmk2h-linuxhost.ccxml │ │ └── program_evm_config │ ├── logs │ └── program_evm.js └── prebuilt-images ├── app ├── config ├── MLO └── spi_flash_writer.outrr}r(jYUjZj~ubaubeubj[)r}r(jYUjZjjbjjdjejf}r(jh]ji]jj]jk]rUdefault-binaries-and-setuprajn]rhOaujpKTjqhjr]r(jt)r}r(jYXDefault Binaries and SetuprjZjjbjjdjxjf}r(jh]ji]jj]jk]jn]ujpKTjqhjr]rj{XDefault Binaries and Setuprr}r(jYjjZjubaubj)r}r(jYXProcessor SDK RTOS provides the basic CCXML files to connect to your SOC. There is a separate CCXML file for each SOC, emulator, and host OS combination. These CCXML files are located in:rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKVjqhjr]rj{XProcessor SDK RTOS provides the basic CCXML files to connect to your SOC. There is a separate CCXML file for each SOC, emulator, and host OS combination. These CCXML files are located in:rr}r(jYjjZjubaubj)r}r(jYXK[SDK Install Path]/processor_sdk_rtos__/bin/config/jZjjbjjdjjf}r(jjjk]jj]jh]ji]jn]ujpM0 jqhjr]rj{XK[SDK Install Path]/processor_sdk_rtos__/bin/config/rr}r(jYUjZjubaubj)r}r(jYXUsers can choose to use their own CCXML file by setting the environment variable, **PROGRAM_EVM_TARGET_CONFIG_FILE**, to point to their CCXML file in their terminal or command prompt.jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK^jqhjr]r(j{XRUsers can choose to use their own CCXML file by setting the environment variable, rr}r(jYXRUsers can choose to use their own CCXML file by setting the environment variable, jZjubj)r}r(jYX"**PROGRAM_EVM_TARGET_CONFIG_FILE**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XPROGRAM_EVM_TARGET_CONFIG_FILErr}r(jYUjZjubajdjubj{XC, to point to their CCXML file in their terminal or command prompt.rr}r(jYXC, to point to their CCXML file in their terminal or command prompt.jZjubeubj)r}r(jYXsYou can create your own CCXML file by opening CCSv6 --> View --> Target Configurations, and right-clicking on the Target Configuration pane to select New Target Configuration. After selecting your SOC and emulator, remember to set the appropriate GEL file in the advance options for Core 0. The GEL file is used to do basic SOC initialization upon connecting to the core.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKbjqhjr]rj{XsYou can create your own CCXML file by opening CCSv6 --> View --> Target Configurations, and right-clicking on the Target Configuration pane to select New Target Configuration. After selecting your SOC and emulator, remember to set the appropriate GEL file in the advance options for Core 0. The GEL file is used to do basic SOC initialization upon connecting to the core.rr}r(jYjjZjubaubj)r}r(jYXProcessor SDK RTOS also provides the basic binaries needed to perform flashing. These are separated into two categories - flashwriters and flash images.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKijqhjr]rj{XProcessor SDK RTOS also provides the basic binaries needed to perform flashing. These are separated into two categories - flashwriters and flash images.rr}r(jYjjZjubaubj)r}r(jYX FlashwritersrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKmjqhjr]rj{X Flashwritersrr}r(jYjjZjubaubjC)r}r(jYUjZjjbjjdj`jf}r(jGX-jk]jj]jh]ji]jn]ujpKojqhjr]r(j/)r}r(jYXN[C66x] eepromwriter_.out - writes content to your EVM EEPROM flash memoryjZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXN[C66x] eepromwriter_.out - writes content to your EVM EEPROM flash memoryrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKojr]rj{XN[C66x] eepromwriter_.out - writes content to your EVM EEPROM flash memoryrr}r(jYjjZjubaubaubj/)r}r(jYXH[C66x] norwriter_.out - writes content to your EVM NOR flash memoryjZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXH[C66x] norwriter_.out - writes content to your EVM NOR flash memoryrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKqjr]rj{XH[C66x] norwriter_.out - writes content to your EVM NOR flash memoryrr}r(jYjjZjubaubaubj/)r}r(jYXJ[C66x] nandwriter_.out - writes content to your EVM NAND flash memoryjZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXJ[C66x] nandwriter_.out - writes content to your EVM NAND flash memoryrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKsjr]rj{XJ[C66x] nandwriter_.out - writes content to your EVM NAND flash memoryrr}r(jYjjZjubaubaubj/)r}r(jYXQ[K2H/E/L] spi_flash_writer.out - writes multiple images to your NOR flash memory jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXP[K2H/E/L] spi_flash_writer.out - writes multiple images to your NOR flash memoryrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKujr]rj{XP[K2H/E/L] spi_flash_writer.out - writes multiple images to your NOR flash memoryrr}r(jYjjZjubaubaubeubj)r}r(jYX Flash imagesrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKxjqhjr]rj{X Flash imagesrr}r(jYjjZjubaubjC)r}r (jYUjZjjbjjdj`jf}r (jGX-jk]jj]jh]ji]jn]ujpKzjqhjr]r (j/)r }r (jYXc[C66x] eeprom50.bin - eeprom binary for address 0x50. The default for C66x is the POST application.jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXc[C66x] eeprom50.bin - eeprom binary for address 0x50. The default for C66x is the POST application.rjZj jbjjdjjf}r(jh]ji]jj]jk]jn]ujpKzjr]rj{Xc[C66x] eeprom50.bin - eeprom binary for address 0x50. The default for C66x is the POST application.rr}r(jYjjZjubaubaubj/)r}r(jYXq[C66x] eeprom51.bin - eeprom binary for address 0x51. The default for C66x is the Intermediate Boot Loader (IBL).jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXq[C66x] eeprom51.bin - eeprom binary for address 0x51. The default for C66x is the Intermediate Boot Loader (IBL).rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK|jr]r j{Xq[C66x] eeprom51.bin - eeprom binary for address 0x51. The default for C66x is the Intermediate Boot Loader (IBL).r!r"}r#(jYjjZjubaubaubj/)r$}r%(jYXj[C66x] nor.bin - nor binary to be used for NOR boot. May not be provided for every EVM or release version.jZjjbjjdj2jf}r&(jh]ji]jj]jk]jn]ujpNjqhjr]r'j)r(}r)(jYXj[C66x] nor.bin - nor binary to be used for NOR boot. May not be provided for every EVM or release version.r*jZj$jbjjdjjf}r+(jh]ji]jj]jk]jn]ujpK~jr]r,j{Xj[C66x] nor.bin - nor binary to be used for NOR boot. May not be provided for every EVM or release version.r-r.}r/(jYj*jZj(ubaubaubj/)r0}r1(jYXm[C66x] nand.bin - nand binary to be used for NAND boot. May not be provided for every EVM or release version.jZjjbjjdj2jf}r2(jh]ji]jj]jk]jn]ujpNjqhjr]r3j)r4}r5(jYXm[C66x] nand.bin - nand binary to be used for NAND boot. May not be provided for every EVM or release version.r6jZj0jbjjdjjf}r7(jh]ji]jj]jk]jn]ujpKjr]r8j{Xm[C66x] nand.bin - nand binary to be used for NAND boot. May not be provided for every EVM or release version.r9r:}r;(jYj6jZj4ubaubaubj/)r<}r=(jYXw[K2H/K2E/K2L] app - NOR binary to be booted by Secondary Bootloader. The default for Keystone 2 is the POST applicationjZjjbjjdj2jf}r>(jh]ji]jj]jk]jn]ujpNjqhjr]r?j)r@}rA(jYXw[K2H/K2E/K2L] app - NOR binary to be booted by Secondary Bootloader. The default for Keystone 2 is the POST applicationrBjZj<jbjjdjjf}rC(jh]ji]jj]jk]jn]ujpKjr]rDj{Xw[K2H/K2E/K2L] app - NOR binary to be booted by Secondary Bootloader. The default for Keystone 2 is the POST applicationrErF}rG(jYjBjZj@ubaubaubj/)rH}rI(jYXm[K2H/K2E/K2L] MLO - Secondary Bootloader. The default flash location is in SPI NOR flash memory at offset 0. jZjjbjjdj2jf}rJ(jh]ji]jj]jk]jn]ujpNjqhjr]rKj)rL}rM(jYXl[K2H/K2E/K2L] MLO - Secondary Bootloader. The default flash location is in SPI NOR flash memory at offset 0.rNjZjHjbjjdjjf}rO(jh]ji]jj]jk]jn]ujpKjr]rPj{Xl[K2H/K2E/K2L] MLO - Secondary Bootloader. The default flash location is in SPI NOR flash memory at offset 0.rQrR}rS(jYjNjZjLubaubaubeubeubj[)rT}rU(jYUjZjjbjjdjejf}rV(jh]ji]jj]jk]rWUusagerXajn]rYh'aujpKjqhjr]rZ(jt)r[}r\(jYXUsager]jZjTjbjjdjxjf}r^(jh]ji]jj]jk]jn]ujpKjqhjr]r_j{XUsager`ra}rb(jYj]jZj[ubaubj)rc}rd(jYXFor Windows users:rejZjTjbjjdjjf}rf(jh]ji]jj]jk]jn]ujpKjqhjr]rgj{XFor Windows users:rhri}rj(jYjejZjcubaubj)rk}rl(jYX> cd [SDK Install Path]\processor_sdk_rtos__\bin > set DSS_SCRIPT_DIR=[CCS Install Path]\ccsv6\ccs_base\scripting\bin > %DSS_SCRIPT_DIR%\dss.bat program_evm.js [tmdx|tmds]evm(6678|6657|k2h|k2e|k2l)[l|le|ls][-le|-be]jZjTjbjjdjjf}rm(jjjk]jj]jh]ji]jn]ujpMb jqhjr]rnj{X> cd [SDK Install Path]\processor_sdk_rtos__\bin > set DSS_SCRIPT_DIR=[CCS Install Path]\ccsv6\ccs_base\scripting\bin > %DSS_SCRIPT_DIR%\dss.bat program_evm.js [tmdx|tmds]evm(6678|6657|k2h|k2e|k2l)[l|le|ls][-le|-be]rorp}rq(jYUjZjkubaubj)rr}rs(jYXFor Linux users:rtjZjTjbjjdjjf}ru(jh]ji]jj]jk]jn]ujpKjqhjr]rvj{XFor Linux users:rwrx}ry(jYjtjZjrubaubj)rz}r{(jYX> cd [SDK Install Path]/processor_sdk_rtos__/bin > export DSS_SCRIPT_DIR=[CCS Install Path]/ccsv6/ccs_base/scripting/bin > $DSS_SCRIPT_DIR/dss.sh program_evm.js [tmdx|tmds]evm(6678|6657|k2h|k2e|k2l)[l|le|ls][-le|-be]jZjTjbjjdjjf}r|(jjjk]jj]jh]ji]jn]ujpMj jqhjr]r}j{X> cd [SDK Install Path]/processor_sdk_rtos__/bin > export DSS_SCRIPT_DIR=[CCS Install Path]/ccsv6/ccs_base/scripting/bin > $DSS_SCRIPT_DIR/dss.sh program_evm.js [tmdx|tmds]evm(6678|6657|k2h|k2e|k2l)[l|le|ls][-le|-be]r~r}r(jYUjZjzubaubj)r}r(jYXtThe last argument depends on the SOC that you have, concatenated with the options to select emulator and endianness:rjZjTjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XtThe last argument depends on the SOC that you have, concatenated with the options to select emulator and endianness:rr}r(jYjjZjubaubjC)r}r(jYUjZjTjbjjdj`jf}r(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]r(j/)r}r(jYX$l: EVM uses XDS100 on-board EmulatorrjZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X$l: EVM uses XDS100 on-board Emulatorrr}r(jYjjZjubaubaubj/)r}r(jYX1le: EVM uses 560 Mezzanine Emulator daughter cardrjZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X1le: EVM uses 560 Mezzanine Emulator daughter cardrr}r(jYjjZjubaubaubj/)r}r(jYX!ls: EVM uses XDS200 Emulator cardrjZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X!ls: EVM uses XDS200 Emulator cardrr}r(jYjjZjubaubaubj/)r}r(jYX-le: Little EndianrjZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X-le: Little Endianrr}r(jYjjZjubaubaubj/)r}r(jYX-be: Big Endian jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYX-be: Big EndianrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X-be: Big Endianrr}r(jYjjZjubaubaubeubj)r}r(jYX- By default, the images provided are little endian. - Also by default, Keystone 2 EVMs are expected to only use the XDS2xx Emulator. You do not have to supply the emulator in the parameter for K2H/K2E/K2L.jZjTjbNjdjjf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rjC)r}r(jYUjf}r(jGX-jk]jj]jh]ji]jn]ujZjjr]r(j/)r}r(jYX2By default, the images provided are little endian.rjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X2By default, the images provided are little endian.rr}r(jYjjZjubaubajdj2ubj/)r}r(jYXAlso by default, Keystone 2 EVMs are expected to only use the XDS2xx Emulator. You do not have to supply the emulator in the parameter for K2H/K2E/K2L.jf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXAlso by default, Keystone 2 EVMs are expected to only use the XDS2xx Emulator. You do not have to supply the emulator in the parameter for K2H/K2E/K2L.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XAlso by default, Keystone 2 EVMs are expected to only use the XDS2xx Emulator. You do not have to supply the emulator in the parameter for K2H/K2E/K2L.rr}r(jYjjZjubaubajdj2ubejdj`ubaubj)r}r(jYXSome examples are:rjZjTjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XSome examples are:rr}r(jYjjZjubaubj)r}r(jYXTMDXEVM6678LE little endianrjZjTjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XTMDXEVM6678LE little endianrr}r(jYjjZjubaubj)r}r(jYX8> $DSS_SCRIPT_DIR/dss.sh program_evm.js tmdxevm6678le-lejZjTjbjjdjjf}r(jjjk]jj]jh]ji]jn]ujpM jqhjr]rj{X8> $DSS_SCRIPT_DIR/dss.sh program_evm.js tmdxevm6678le-lerr}r(jYUjZjubaubj)r}r(jYXTMDSEVM6657LS little endianrjZjTjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XTMDSEVM6657LS little endianrr}r(jYjjZjubaubj)r}r (jYX8> $DSS_SCRIPT_DIR/dss.sh program_evm.js tmdxevm6657ls-lejZjTjbjjdjjf}r (jjjk]jj]jh]ji]jn]ujpM jqhjr]r j{X8> $DSS_SCRIPT_DIR/dss.sh program_evm.js tmdxevm6657ls-ler r }r(jYUjZjubaubj)r}r(jYXEVMK2H little endianrjZjTjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XEVMK2H little endianrr}r(jYjjZjubaubj)r}r(jYX2> $DSS_SCRIPT_DIR/dss.sh program_evm.js tmdsevmk2hjZjTjbjjdjjf}r(jjjk]jj]jh]ji]jn]ujpM jqhjr]rj{X2> $DSS_SCRIPT_DIR/dss.sh program_evm.js tmdsevmk2hrr}r(jYUjZjubaubj)r}r(jYXEVMK2E little endianr jZjTjbjjdjjf}r!(jh]ji]jj]jk]jn]ujpKjqhjr]r"j{XEVMK2E little endianr#r$}r%(jYj jZjubaubj)r&}r'(jYX2> $DSS_SCRIPT_DIR/dss.sh program_evm.js tmdsevmk2ejZjTjbjjdjjf}r((jjjk]jj]jh]ji]jn]ujpM jqhjr]r)j{X2> $DSS_SCRIPT_DIR/dss.sh program_evm.js tmdsevmk2er*r+}r,(jYUjZj&ubaubeubj[)r-}r.(jYUjZjjbjjdjejf}r/(jh]ji]jj]jk]r0U sample-outputr1ajn]r2haujpKjqhjr]r3(jt)r4}r5(jYX Sample Outputr6jZj-jbjjdjxjf}r7(jh]ji]jj]jk]jn]ujpKjqhjr]r8j{X Sample Outputr9r:}r;(jYj6jZj4ubaubj)r<}r=(jYXC:\ti\processor_sdk_rtos_c665x_2_00_01_07\bin>%DSS_SCRIPT_DIR%\dss.bat program_evm.js tmdxevm6657ls-le board: evm6657l endian: Little emulation: XDS200 emulator binaries: ../prebuilt-images/ ccxml: C:\ti\processor_sdk_rtos_c665x_2_00_01_07\bin/configs/evm6657l/evm6657ls.ccxml C66xx_0: GEL Output: Connecting Target... C66xx_0: GEL Output: DSP core #0 C66xx_0: GEL Output: C6657L GEL file Ver is 1.006 C66xx_0: GEL Output: Global Default Setup... C66xx_0: GEL Output: Setup Cache... C66xx_0: GEL Output: L1P = 32K C66xx_0: GEL Output: L1D = 32K C66xx_0: GEL Output: L2 = ALL SRAM C66xx_0: GEL Output: Setup Cache... Done. C66xx_0: GEL Output: Main PLL (PLL1) Setup ... C66xx_0: GEL Output: PLL in Bypass ... C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz. C66xx_0: GEL Output: SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz. C66xx_0: GEL Output: SYSCLK8 = 15.625 MHz. C66xx_0: GEL Output: PLL1 Setup... Done. C66xx_0: GEL Output: Power on all PSC modules and DSP domains... C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=12, md=4! C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done. C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ... C66xx_0: GEL Output: DDR3 PLL Setup... Done. C66xx_0: GEL Output: DDR3 Init begin (1333 auto) C66xx_0: GEL Output: XMC Setup ... Done C66xx_0: GEL Output: IFRDY bit is SET: DDR3 Interface Ready C66xx_0: GEL Output: DDR3 initialization is complete. C66xx_0: GEL Output: DDR3 Init done C66xx_0: GEL Output: DDR3 memory test... Started C66xx_0: GEL Output: DDR3 memory test... Passed C66xx_0: GEL Output: PLL and DDR3 Initialization completed(0) ... C66xx_0: GEL Output: configSGMIISerdes Setup... Begin C66xx_0: GEL Output: SGMII SERDES has been configured. C66xx_0: GEL Output: Enabling EDC ... C66xx_0: GEL Output: L1P error detection logic is enabled. C66xx_0: GEL Output: L2 error detection/correction logic is enabled. C66xx_0: GEL Output: MSMC error detection/correction logic is enabled. C66xx_0: GEL Output: Enabling EDC ...Done C66xx_0: GEL Output: Global Default Setup... Done. Start writing eeprom50 Writer:../prebuilt-images/eepromwriter_evm6657l.out Image:../prebuilt-images/eeprom50.bin C66xx_0: GEL Output: Invalidate All Cache... C66xx_0: GEL Output: Invalidate All Cache... Done. C66xx_0: GEL Output: GEL Reset... C66xx_0: GEL Output: GEL Reset... Done. C66xx_0: GEL Output: Disable all EDMA3 interrupts and events. EEPROM Writer Utility Version 01.00.00.05 Writing 57432 bytes from DSP memory address 0x0c000000 to EEPROM bus address 0x0050 starting from device address 0x0000 ... Reading 57432 bytes from EEPROM bus address 0x0050 to DSP memory address 0x0c010000 starting from device address 0x0000 ... Verifying data read ... EEPROM programming completed successfully Start writing eeprom51 Writer:../prebuilt-images/eepromwriter_evm6657l.out Image:../prebuilt-images/eeprom51.bin C66xx_0: GEL Output: Invalidate All Cache... C66xx_0: GEL Output: Invalidate All Cache... Done. C66xx_0: GEL Output: GEL Reset... C66xx_0: GEL Output: GEL Reset... Done. C66xx_0: GEL Output: Disable all EDMA3 interrupts and events. EEPROM Writer Utility Version 01.00.00.05 Writing 47888 bytes from DSP memory address 0x0c000000 to EEPROM bus address 0x0051 starting from device address 0x0000 ... Reading 47888 bytes from EEPROM bus address 0x0051 to DSP memory address 0x0c010000 starting from device address 0x0000 ... Verifying data read ... EEPROM programming completed successfully Writer:../prebuilt-images/nandwriter_evm6657l.out NAND:../prebuilt-images/nand.bin Required NAND files does not exist in ../prebuilt-images/ Writer:../prebuilt-images/norwriter_evm6657l.out NOR:../prebuilt-images/nor.bin Required NOR files does not exist in ../prebuilt-images/jZj-jbjjdjjf}r>(jjjk]jj]jh]ji]jn]ujpM jqhjr]r?j{XC:\ti\processor_sdk_rtos_c665x_2_00_01_07\bin>%DSS_SCRIPT_DIR%\dss.bat program_evm.js tmdxevm6657ls-le board: evm6657l endian: Little emulation: XDS200 emulator binaries: ../prebuilt-images/ ccxml: C:\ti\processor_sdk_rtos_c665x_2_00_01_07\bin/configs/evm6657l/evm6657ls.ccxml C66xx_0: GEL Output: Connecting Target... C66xx_0: GEL Output: DSP core #0 C66xx_0: GEL Output: C6657L GEL file Ver is 1.006 C66xx_0: GEL Output: Global Default Setup... C66xx_0: GEL Output: Setup Cache... C66xx_0: GEL Output: L1P = 32K C66xx_0: GEL Output: L1D = 32K C66xx_0: GEL Output: L2 = ALL SRAM C66xx_0: GEL Output: Setup Cache... Done. C66xx_0: GEL Output: Main PLL (PLL1) Setup ... C66xx_0: GEL Output: PLL in Bypass ... C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz. C66xx_0: GEL Output: SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz. C66xx_0: GEL Output: SYSCLK8 = 15.625 MHz. C66xx_0: GEL Output: PLL1 Setup... Done. C66xx_0: GEL Output: Power on all PSC modules and DSP domains... C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=12, md=4! C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done. C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ... C66xx_0: GEL Output: DDR3 PLL Setup... Done. C66xx_0: GEL Output: DDR3 Init begin (1333 auto) C66xx_0: GEL Output: XMC Setup ... Done C66xx_0: GEL Output: IFRDY bit is SET: DDR3 Interface Ready C66xx_0: GEL Output: DDR3 initialization is complete. C66xx_0: GEL Output: DDR3 Init done C66xx_0: GEL Output: DDR3 memory test... Started C66xx_0: GEL Output: DDR3 memory test... Passed C66xx_0: GEL Output: PLL and DDR3 Initialization completed(0) ... C66xx_0: GEL Output: configSGMIISerdes Setup... Begin C66xx_0: GEL Output: SGMII SERDES has been configured. C66xx_0: GEL Output: Enabling EDC ... C66xx_0: GEL Output: L1P error detection logic is enabled. C66xx_0: GEL Output: L2 error detection/correction logic is enabled. C66xx_0: GEL Output: MSMC error detection/correction logic is enabled. C66xx_0: GEL Output: Enabling EDC ...Done C66xx_0: GEL Output: Global Default Setup... Done. Start writing eeprom50 Writer:../prebuilt-images/eepromwriter_evm6657l.out Image:../prebuilt-images/eeprom50.bin C66xx_0: GEL Output: Invalidate All Cache... C66xx_0: GEL Output: Invalidate All Cache... Done. C66xx_0: GEL Output: GEL Reset... C66xx_0: GEL Output: GEL Reset... Done. C66xx_0: GEL Output: Disable all EDMA3 interrupts and events. EEPROM Writer Utility Version 01.00.00.05 Writing 57432 bytes from DSP memory address 0x0c000000 to EEPROM bus address 0x0050 starting from device address 0x0000 ... Reading 57432 bytes from EEPROM bus address 0x0050 to DSP memory address 0x0c010000 starting from device address 0x0000 ... Verifying data read ... EEPROM programming completed successfully Start writing eeprom51 Writer:../prebuilt-images/eepromwriter_evm6657l.out Image:../prebuilt-images/eeprom51.bin C66xx_0: GEL Output: Invalidate All Cache... C66xx_0: GEL Output: Invalidate All Cache... Done. C66xx_0: GEL Output: GEL Reset... C66xx_0: GEL Output: GEL Reset... Done. C66xx_0: GEL Output: Disable all EDMA3 interrupts and events. EEPROM Writer Utility Version 01.00.00.05 Writing 47888 bytes from DSP memory address 0x0c000000 to EEPROM bus address 0x0051 starting from device address 0x0000 ... Reading 47888 bytes from EEPROM bus address 0x0051 to DSP memory address 0x0c010000 starting from device address 0x0000 ... Verifying data read ... EEPROM programming completed successfully Writer:../prebuilt-images/nandwriter_evm6657l.out NAND:../prebuilt-images/nand.bin Required NAND files does not exist in ../prebuilt-images/ Writer:../prebuilt-images/norwriter_evm6657l.out NOR:../prebuilt-images/nor.bin Required NOR files does not exist in ../prebuilt-images/r@rA}rB(jYUjZj<ubaubj)rC}rD(jYXsIn the above example, nothing was flashed to NAND or NOR since there were no nand.bin or nor.bin binaries to flash.rEjZj-jbjjdjjf}rF(jh]ji]jj]jk]jn]ujpMRjqhjr]rGj{XsIn the above example, nothing was flashed to NAND or NOR since there were no nand.bin or nor.bin binaries to flash.rHrI}rJ(jYjEjZjCubaubeubeubeubj[)rK}rL(jYUjZjjbjcjdjejf}rM(jh]ji]jj]jk]rNUportingrOajn]rPhaujpKDjqhjr]rQ(jt)rR}rS(jYXPortingrTjZjKjbjcjdjxjf}rU(jh]ji]jj]jk]jn]ujpKDjqhjr]rVj{XPortingrWrX}rY(jYjTjZjRubaubj[)rZ}r[(jYUjZjKjbjcjdjejf}r\(jh]ji]jj]jk]r]UBadding-custom-board-library-target-to-processor-sdk-rtos-makefilesr^ajn]r_h>aujpKGjqhjr]r`(jt)ra}rb(jYXBAdding Custom Board_Library Target to Processor SDK RTOS makefilesrcjZjZjbjcjdjxjf}rd(jh]ji]jj]jk]jn]ujpKGjqhjr]rej{XBAdding Custom Board_Library Target to Processor SDK RTOS makefilesrfrg}rh(jYjcjZjaubaubj)ri}rj(jYXjhttp://processors.wiki.ti.com/index.php/Adding_Custom_Board_Library_Target_to_Processor_SDK_RTOS_makefilesjZjZjbjXhsource/rtos/How_to_Guides/Host/Porting/Adding_Custom_Board_Library_Target_to_PSDK_RTOS_makefiles.rst.incrkrl}rmbjdjjf}rn(jjjk]jj]jh]ji]jn]ujpKjqhjr]roj{Xjhttp://processors.wiki.ti.com/index.php/Adding_Custom_Board_Library_Target_to_Processor_SDK_RTOS_makefilesrprq}rr(jYUjZjiubaubj[)rs}rt(jYUjKjZjZjbjljdjejf}ru(jh]rvX introductionrwaji]jj]jk]rxU introductionryajn]ujpKjqhjr]rz(jt)r{}r|(jYX Introductionr}jZjsjbjljdjxjf}r~(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X Introductionrr}r(jYj}jZj{ubaubj)r}r(jYXiThe following article describes how a custom Board can be added to the Processor SDK RTOS. The scope of this article is to only describe how to modify the build files in the PDK to add build steps for your custom board library. The article does not describe modification of source files to reflect changes to clocking, DDR and pinmux setup for the custom board.rjZjsjbjljdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XiThe following article describes how a custom Board can be added to the Processor SDK RTOS. The scope of this article is to only describe how to modify the build files in the PDK to add build steps for your custom board library. The article does not describe modification of source files to reflect changes to clocking, DDR and pinmux setup for the custom board.rr}r(jYjjZjubaubj)r}r(jYX1The instructions provided in this article uses example of AM572x custom board but the instructions apply to all the processors supported in Processor SDK RTOS. Note that the instructions on this wiki were created using Processor SDK RTOS v3.2 and PDK_AM57xx_1_0_5 and are subject to change. Also the wiki was created specifically for the newer board variants like evmAM572x, idkAM572x and evmK2G. For AM335x and AM437x variant board library has several dependencies on legacy starterware package, hence additional steps are required and not covered in the wiki.rjZjsjbjljdjjf}r(jh]ji]jj]jk]jn]ujpK jqhjr]rj{X1The instructions provided in this article uses example of AM572x custom board but the instructions apply to all the processors supported in Processor SDK RTOS. Note that the instructions on this wiki were created using Processor SDK RTOS v3.2 and PDK_AM57xx_1_0_5 and are subject to change. Also the wiki was created specifically for the newer board variants like evmAM572x, idkAM572x and evmK2G. For AM335x and AM437x variant board library has several dependencies on legacy starterware package, hence additional steps are required and not covered in the wiki.rr}r(jYjjZjubaubeubj[)r}r(jYUjZjZjbjljdjejf}r(jh]ji]jj]jk]rU1instructions-to-add-custom-board-to-the-pdk-buildrajn]rhaujpKjqhjr]r(jt)r}r(jYX1Instructions to add custom Board to the PDK buildrjZjjbjljdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X1Instructions to add custom Board to the PDK buildrr}r(jYjjZjubaubj)r}r(jYX;**Step 1: Creating new directory for custom board library**rjZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X7Step 1: Creating new directory for custom board libraryrr}r(jYUjZjubajdjubaubj)r}r(jYX|In pdk_am57xx_x_x_x/packages/ti/board/src, Create new directory myCustomBoard and copy files from existing board library package. We recommend that you copy files from the board which closely matches your custom board design. In this case, we assume that the custom board is based on the design of evmAM572x so we copy over the files from that directory into myCustomBoard folder.rjZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X|In pdk_am57xx_x_x_x/packages/ti/board/src, Create new directory myCustomBoard and copy files from existing board library package. We recommend that you copy files from the board which closely matches your custom board design. In this case, we assume that the custom board is based on the design of evmAM572x so we copy over the files from that directory into myCustomBoard folder.rr}r(jYjjZjubaubj)r}r(jYXF**Step 2: Updating names and makefile inside the customBoard package**rjZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpK#jqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XBStep 2: Updating names and makefile inside the customBoard packagerr}r(jYUjZjubajdjubaubj)r}r(jYX#In pdk_am57xx_x_x_x/packages/ti/board/src/myCustomBoard, Rename file src_files_evmAM572x.mk to src_files_myCustomBoard.mk. This file will need a bit of work depending on what elements of board you need for your platform. We have left all the files evmAM572x_*.c but you can modify as needed.rjZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpK%jqhjr]rj{X#In pdk_am57xx_x_x_x/packages/ti/board/src/myCustomBoard, Rename file src_files_evmAM572x.mk to src_files_myCustomBoard.mk. This file will need a bit of work depending on what elements of board you need for your platform. We have left all the files evmAM572x_*.c but you can modify as needed.rr}r(jYjjZjubaubj)r}r(jYX]**Step 3: Adding MACRO based inclusion of updated board_cfg.h corresponding to custom Board**rjZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpK+jqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XYStep 3: Adding MACRO based inclusion of updated board_cfg.h corresponding to custom Boardrr}r(jYUjZjubajdjubaubj)r}r(jYXIn packages/ti/board/board_cfg.h, add the lines pointing to board_cfg.h file in your customBoard package so that updated peripheral instances and board specific defines can be picked uprjZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpK.jqhjr]rj{XIn packages/ti/board/board_cfg.h, add the lines pointing to board_cfg.h file in your customBoard package so that updated peripheral instances and board specific defines can be picked uprr}r(jYjjZjubaubj)r}r(jYX\#if defined (myCustomBoard) #include #endifjZjjbjljdjjf}r(jjjk]jj]jh]ji]jn]ujpMh jqhjr]rj{X\#if defined (myCustomBoard) #include #endifrr}r(jYUjZjubaubj)r}r(jYX**Step 4: Update top level board package makefile to include build for customBoard Library** The makefile is used to include all relevant make files for including Low level driver(LLD), source files relevant to board and the common board.c filejZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpK8jqhjr]r(j)r}r(jYX\**Step 4: Update top level board package makefile to include build for customBoard Library**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XXStep 4: Update top level board package makefile to include build for customBoard Libraryrr}r(jYUjZjubajdjubj{X The makefile is used to include all relevant make files for including Low level driver(LLD), source files relevant to board and the common board.c filerr}r(jYX The makefile is used to include all relevant make files for including Low level driver(LLD), source files relevant to board and the common board.c filejZjubeubjC)r}r(jYUjZjjbjljdj`jf}r(jGX-jk]jj]jh]ji]jn]ujpK=jqhjr]rj/)r}r(jYXPIn packages/ti/board/build/makefile.mk, add board.c to the customBoard build : jZjjbjljdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXOIn packages/ti/board/build/makefile.mk, add board.c to the customBoard build :rjZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpK=jr]rj{XOIn packages/ti/board/build/makefile.mk, add board.c to the customBoard build :rr}r(jYjjZjubaubaubaubj)r}r(jYX"ifeq ($(BOARD),$(filter $(BOARD),evmAM335x icev2AM335x skAM335x bbbAM335x evmAM437x idkAM437x skAM437x myCustomBoard evmAM572x idkAM571x idkAM572x evmK2H evmK2K evmK2E evmK2L evmK2G iceK2G evmC6678 evmC6657)) # Common source files across all platforms and cores SRCS_COMMON += board.c endifjZjjbjljdjjf}r(jjjk]jj]jh]ji]jn]ujpMv jqhjr]rj{X"ifeq ($(BOARD),$(filter $(BOARD),evmAM335x icev2AM335x skAM335x bbbAM335x evmAM437x idkAM437x skAM437x myCustomBoard evmAM572x idkAM571x idkAM572x evmK2H evmK2K evmK2E evmK2L evmK2G iceK2G evmC6678 evmC6657)) # Common source files across all platforms and cores SRCS_COMMON += board.c endifrr}r (jYUjZjubaubjC)r }r (jYUjZjjbjljdj`jf}r (jGX-jk]jj]jh]ji]jn]ujpKGjqhjr]r j/)r}r(jYXFAdd board library source files and LLD files to the customBoard build jZj jbjljdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXEAdd board library source files and LLD files to the customBoard buildrjZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpKGjr]rj{XEAdd board library source files and LLD files to the customBoard buildrr}r(jYjjZjubaubaubaubj)r}r(jYX.In packages/ti/board/build/makefile.mk, changerjZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpKIjqhjr]rj{X.In packages/ti/board/build/makefile.mk, changerr }r!(jYjjZjubaubj)r"}r#(jYXifeq ($(BOARD),$(filter $(BOARD), evmAM572x idkAM571x idkAM572x)) include $(PDK_BOARD_COMP_PATH)/src/$(BOARD)/src_files_$(BOARD).mk include $(PDK_BOARD_COMP_PATH)/src/src_files_lld.mk CFLAGS_LOCAL_$(BOARD) += -D$(BOARD) endifjZjjbjljdjjf}r$(jjjk]jj]jh]ji]jn]ujpM jqhjr]r%j{Xifeq ($(BOARD),$(filter $(BOARD), evmAM572x idkAM571x idkAM572x)) include $(PDK_BOARD_COMP_PATH)/src/$(BOARD)/src_files_$(BOARD).mk include $(PDK_BOARD_COMP_PATH)/src/src_files_lld.mk CFLAGS_LOCAL_$(BOARD) += -D$(BOARD) endifr&r'}r((jYUjZj"ubaubj)r)}r*(jYXtor+jZjjbjljdjjf}r,(jh]ji]jj]jk]jn]ujpKSjqhjr]r-j{Xtor.r/}r0(jYj+jZj)ubaubj)r1}r2(jYXifeq ($(BOARD),$(filter $(BOARD), myCustomBoard evmAM572x idkAM571x idkAM572x)) include $(PDK_BOARD_COMP_PATH)/src/$(BOARD)/src_files_$(BOARD).mk include $(PDK_BOARD_COMP_PATH)/src/src_files_lld.mk CFLAGS_LOCAL_$(BOARD) += -D$(BOARD) endifjZjjbjljdjjf}r3(jjjk]jj]jh]ji]jn]ujpM jqhjr]r4j{Xifeq ($(BOARD),$(filter $(BOARD), myCustomBoard evmAM572x idkAM571x idkAM572x)) include $(PDK_BOARD_COMP_PATH)/src/$(BOARD)/src_files_$(BOARD).mk include $(PDK_BOARD_COMP_PATH)/src/src_files_lld.mk CFLAGS_LOCAL_$(BOARD) += -D$(BOARD) endifr5r6}r7(jYUjZj1ubaubj)r8}r9(jYX#**Step 5: Update Global makerules**r:jZjjbjljdjjf}r;(jh]ji]jj]jk]jn]ujpK]jqhjr]r<j)r=}r>(jYj:jf}r?(jh]ji]jj]jk]jn]ujZj8jr]r@j{XStep 5: Update Global makerulesrArB}rC(jYUjZj=ubajdjubaubj)rD}rE(jYXbuild_config.mk defines the global CFLAGS used to compile different PDK components. Add the following line in the BOARD Specific configurations.rFjZjjbjljdjjf}rG(jh]ji]jj]jk]jn]ujpK_jqhjr]rHj{Xbuild_config.mk defines the global CFLAGS used to compile different PDK components. Add the following line in the BOARD Specific configurations.rIrJ}rK(jYjFjZjDubaubj)rL}rM(jYX6CFLAGS_GLOBAL_customAM572x = -DSOC_AM572x -DevmAM572xjZjjbjljdjjf}rN(jjjk]jj]jh]ji]jn]ujpM jqhjr]rOj{X6CFLAGS_GLOBAL_customAM572x = -DSOC_AM572x -DevmAM572xrPrQ}rR(jYUjZjLubaubj)rS}rT(jYXThe SOC_AM572x macro ensures that the CSL aplicable to this SOC will be included in the build and evmAM572x define will ensure all evmAM572x specific includes that apply to the customAM572x are part of the build.rUjZjjbjljdjjf}rV(jh]ji]jj]jk]jn]ujpKfjqhjr]rWj{XThe SOC_AM572x macro ensures that the CSL aplicable to this SOC will be included in the build and evmAM572x define will ensure all evmAM572x specific includes that apply to the customAM572x are part of the build.rXrY}rZ(jYjUjZjSubaubj)r[}r\(jYX.**Optional step to update RTSC platform definition** If you have a custom RTSC platform definition for your custom board that updates the memory and platform configuration using RTSC Tool then you need to update the platform.mk file that associates the RTSC platfom with the corresponding board libraryjZjjbjljdjjf}r](jh]ji]jj]jk]jn]ujpKkjqhjr]r^(j)r_}r`(jYX4**Optional step to update RTSC platform definition**jf}ra(jh]ji]jj]jk]jn]ujZj[jr]rbj{X0Optional step to update RTSC platform definitionrcrd}re(jYUjZj_ubajdjubj{X If you have a custom RTSC platform definition for your custom board that updates the memory and platform configuration using RTSC Tool then you need to update the platform.mk file that associates the RTSC platfom with the corresponding board libraryrfrg}rh(jYX If you have a custom RTSC platform definition for your custom board that updates the memory and platform configuration using RTSC Tool then you need to update the platform.mk file that associates the RTSC platfom with the corresponding board libraryjZj[ubeubj)ri}rj(jYXCIn packages/ti/buildmakerules/platform.mk, add the following lines:rkjZjjbjljdjjf}rl(jh]ji]jj]jk]jn]ujpKqjqhjr]rmj{XCIn packages/ti/buildmakerules/platform.mk, add the following lines:rnro}rp(jYjkjZjiubaubj)rq}rr(jYX]ifeq ($(BOARD),$(filter $(BOARD), evmAM572x)) PLATFORM_XDC = "ti.platforms.evmAM572X" endifjZjjbjljdjjf}rs(jjjk]jj]jh]ji]jn]ujpM jqhjr]rtj{X]ifeq ($(BOARD),$(filter $(BOARD), evmAM572x)) PLATFORM_XDC = "ti.platforms.evmAM572X" endifrurv}rw(jYUjZjqubaubj)rx}ry(jYXZifeq ($(BOARD),$(filter $(BOARD), myCustomBoard)) PLATFORM_XDC = "evmAM572XCustom" endifjZjjbjljdjjf}rz(jjjk]jj]jh]ji]jn]ujpM jqhjr]r{j{XZifeq ($(BOARD),$(filter $(BOARD), myCustomBoard)) PLATFORM_XDC = "evmAM572XCustom" endifr|r}}r~(jYUjZjxubaubj)r}r(jYXThe SYSBIOS platforms follow the convention to consolidate all platform definitions under SYSBIOS_INSTALL_PATH/packages/ti/platforms/\* hence the convention ti.platorms. but for custom platform, users are not required to follow this convention.jZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXThe SYSBIOS platforms follow the convention to consolidate all platform definitions under SYSBIOS_INSTALL_PATH/packages/ti/platforms/\* hence the convention ti.platorms. but for custom platform, users are not required to follow this convention.jZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XThe SYSBIOS platforms follow the convention to consolidate all platform definitions under SYSBIOS_INSTALL_PATH/packages/ti/platforms/* hence the convention ti.platorms. but for custom platform, users are not required to follow this convention.rr}r(jYXThe SYSBIOS platforms follow the convention to consolidate all platform definitions under SYSBIOS_INSTALL_PATH/packages/ti/platforms/\* hence the convention ti.platorms. but for custom platform, users are not required to follow this convention.jZjubaubaubj)r}r(jYXv**Step 6: Update source files corresponding to drivers used in board library**. src_files_lld.mk file adds source files corresponding to LLD drivers used in the board library. Usually most boards utilitize control driver like I2C (for programming the PMIC or reading EEPROM), UART drivers (for IO) and boot media drivers like (SPI/QSPI, MMC or NAND). In the example below, we assume that the custom Board library has dependency on I2C, SPI and UART LLD drivers. Since the LLD drivers will be linked to the application along with board library, board library only needs _soc.c corresponding to SOC used on the custom Board.jZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r(j)r}r(jYXN**Step 6: Update source files corresponding to drivers used in board library**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XJStep 6: Update source files corresponding to drivers used in board libraryrr}r(jYUjZjubajdjubj{X(. src_files_lld.mk file adds source files corresponding to LLD drivers used in the board library. Usually most boards utilitize control driver like I2C (for programming the PMIC or reading EEPROM), UART drivers (for IO) and boot media drivers like (SPI/QSPI, MMC or NAND). In the example below, we assume that the custom Board library has dependency on I2C, SPI and UART LLD drivers. Since the LLD drivers will be linked to the application along with board library, board library only needs _soc.c corresponding to SOC used on the custom Board.rr}r(jYX(. src_files_lld.mk file adds source files corresponding to LLD drivers used in the board library. Usually most boards utilitize control driver like I2C (for programming the PMIC or reading EEPROM), UART drivers (for IO) and boot media drivers like (SPI/QSPI, MMC or NAND). In the example below, we assume that the custom Board library has dependency on I2C, SPI and UART LLD drivers. Since the LLD drivers will be linked to the application along with board library, board library only needs _soc.c corresponding to SOC used on the custom Board.jZjubeubj)r}r(jYXCIn packages/ti/board/src/src_files_lld.mk, add the following lines:rjZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XCIn packages/ti/board/src/src_files_lld.mk, add the following lines:rr}r(jYjjZjubaubj)r}r(jYXifeq ($(BOARD),$(filter $(BOARD), myCustomBoard)) SRCDIR += $(PDK_INSTALL_PATH)/ti/drv/i2c/soc/am572x \ $(PDK_INSTALL_PATH)/ti/drv/uart/soc/am572x \ $(PDK_INSTALL_PATH)/ti/drv/spi/soc/am572xjZjjbjljdjjf}r(jjjk]jj]jh]ji]jn]ujpM jqhjr]rj{Xifeq ($(BOARD),$(filter $(BOARD), myCustomBoard)) SRCDIR += $(PDK_INSTALL_PATH)/ti/drv/i2c/soc/am572x \ $(PDK_INSTALL_PATH)/ti/drv/uart/soc/am572x \ $(PDK_INSTALL_PATH)/ti/drv/spi/soc/am572xrr}r(jYUjZjubaubj)r}r(jYXINCDIR += $(PDK_INSTALL_PATH)/ti/drv/i2c/soc/am572x \ $(PDK_INSTALL_PATH)/ti/drv/uart/soc/am572x \ $(PDK_INSTALL_PATH)/ti/drv/spi/soc/am572xjZjjbjljdjjf}r(jjjk]jj]jh]ji]jn]ujpM jqhjr]rj{XINCDIR += $(PDK_INSTALL_PATH)/ti/drv/i2c/soc/am572x \ $(PDK_INSTALL_PATH)/ti/drv/uart/soc/am572x \ $(PDK_INSTALL_PATH)/ti/drv/spi/soc/am572xrr}r(jYUjZjubaubj)r}r(jYXh# Common source files across all platforms and cores SRCS_COMMON += I2C_soc.c UART_soc.c SPI_soc.c endifjZjjbjljdjjf}r(jjjk]jj]jh]ji]jn]ujpM jqhjr]rj{Xh# Common source files across all platforms and cores SRCS_COMMON += I2C_soc.c UART_soc.c SPI_soc.c endifrr}r(jYUjZjubaubj)r}r(jYXFor all LLD drivers linked to the board library you need to include corresponding _soc.c file. For example if you include GPIO driver for setting board mux then GPIO_soc.c needs to be added to LLD source files.jZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXFor all LLD drivers linked to the board library you need to include corresponding _soc.c file. For example if you include GPIO driver for setting board mux then GPIO_soc.c needs to be added to LLD source files.rjZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XFor all LLD drivers linked to the board library you need to include corresponding _soc.c file. For example if you include GPIO driver for setting board mux then GPIO_soc.c needs to be added to LLD source files.rr}r(jYjjZjubaubaubj)r}r(jYX=**Step 7: Add custom Board to BOARDLIST and update CORELIST**rjZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X9Step 7: Add custom Board to BOARDLIST and update CORELISTrr}r(jYUjZjubajdjubaubj)r}r(jYXIn packages/ti/board/board_component.mk, modify the build to add your custom board and specify the cores for which you want to build the board library. Example to build board library for only A15 and C66x cores, limit the build by specify only a15_0 and C66x in the CORELISTrjZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XIn packages/ti/board/board_component.mk, modify the build to add your custom board and specify the cores for which you want to build the board library. Example to build board library for only A15 and C66x cores, limit the build by specify only a15_0 and C66x in the CORELISTrr}r(jYjjZjubaubj)r}r(jYXboard_lib_BOARDLIST = myCustomBoard evmAM335x icev2AM335x skAM335x bbbAM335x evmAM437x idkAM437x skAM437x evmAM572x idkAM571x idkAM572x evmK2H evmK2K evmK2E evmK2L evmK2G iceK2G \jZjjbjljdjjf}r(jjjk]jj]jh]ji]jn]ujpM jqhjr]rj{Xboard_lib_BOARDLIST = myCustomBoard evmAM335x icev2AM335x skAM335x bbbAM335x evmAM437x idkAM437x skAM437x evmAM572x idkAM571x idkAM572x evmK2H evmK2K evmK2E evmK2L evmK2G iceK2G \rr}r(jYUjZjubaubj)r}r(jYXU#board_lib_am572x_CORELIST = c66x a15_0 ipu1_0 board_lib_am572x_CORELIST = a15_0 c66xjZjjbjljdjjf}r(jjjk]jj]jh]ji]jn]ujpM jqhjr]rj{XU#board_lib_am572x_CORELIST = c66x a15_0 ipu1_0 board_lib_am572x_CORELIST = a15_0 c66xrr}r(jYUjZjubaubj)r}r(jYX<**Step 8: Update .bld files for XDCTOOL based build steps.**rjZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X8Step 8: Update .bld files for XDCTOOL based build steps.rr}r(jYUjZjubajdjubaubj)r}r(jYXZMake corresponding changes in packages/ti/board/config.bld, by adding the following lines:rjZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XZMake corresponding changes in packages/ti/board/config.bld, by adding the following lines:rr}r(jYjjZjubaubj)r}r(jYX?var myCustomBoard = { name: "myCustomBoard", ccOpts: "-DevmAM572x -DSOC_AM572x", targets: [C66LE,A15LE ] lldFiles: [ "$(PDK_INSTALL_PATH)/ti/drv/i2c/soc/am572x/I2C_soc.c", "$(PDK_INSTALL_PATH)/ti/drv/uart/soc/am572x/UART_soc.c", "$(PDK_INSTALL_PATH)/ti/drv/spi/soc/am572x/SPI_soc.c"] }jZjjbjljdjjf}r(jjjk]jj]jh]ji]jn]ujpM jqhjr]rj{X?var myCustomBoard = { name: "myCustomBoard", ccOpts: "-DevmAM572x -DSOC_AM572x", targets: [C66LE,A15LE ] lldFiles: [ "$(PDK_INSTALL_PATH)/ti/drv/i2c/soc/am572x/I2C_soc.c", "$(PDK_INSTALL_PATH)/ti/drv/uart/soc/am572x/UART_soc.c", "$(PDK_INSTALL_PATH)/ti/drv/spi/soc/am572x/SPI_soc.c"] }rr}r(jYUjZjubaubj)r}r(jYXvar boards = [ evmAM335x, icev2AM335x, skAM335x, bbbAM335x, evmAM437x, idkAM437x, skAM437x, myCustomBoard, evmAM572x, idkAM571x, idkAM572x, evmK2H, evmK2K, evmK2E, evmK2L, evmK2G, evmC6678, evmC6657 ];jZjjbjljdjjf}r(jjjk]jj]jh]ji]jn]ujpM jqhjr]rj{Xvar boards = [ evmAM335x, icev2AM335x, skAM335x, bbbAM335x, evmAM437x, idkAM437x, skAM437x, myCustomBoard, evmAM572x, idkAM571x, idkAM572x, evmK2H, evmK2K, evmK2E, evmK2L, evmK2G, evmC6678, evmC6657 ];rr}r(jYUjZjubaubj)r}r(jYXCAlso, in packages/ti/board/package.bld, I added the following line:rjZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r j{XCAlso, in packages/ti/board/package.bld, I added the following line:r r }r (jYjjZjubaubj)r }r(jYXYPkg.otherFiles[Pkg.otherFiles.length++] = "src/myCustomBoard/src_files_myCustomBoard.mk";jZjjbjljdjjf}r(jjjk]jj]jh]ji]jn]ujpM jqhjr]rj{XYPkg.otherFiles[Pkg.otherFiles.length++] = "src/myCustomBoard/src_files_myCustomBoard.mk";rr}r(jYUjZj ubaubj)r}r(jYXY**Step 9: Setup Top level PDK build files to add the Custom board to setup environment.**rjZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XUStep 9: Setup Top level PDK build files to add the Custom board to setup environment.rr}r(jYUjZjubajdjubaubj)r }r!(jYXFinal setup involves updating the top level setup file for PDK package to update to setup the build environment to include the custom Board in setup. This can be done by commenting out the top line and adding in the bottom line in pdksetupenv.bat:r"jZjjbjljdjjf}r#(jh]ji]jj]jk]jn]ujpKjqhjr]r$j{XFinal setup involves updating the top level setup file for PDK package to update to setup the build environment to include the custom Board in setup. This can be done by commenting out the top line and adding in the bottom line in pdksetupenv.bat:r%r&}r'(jYj"jZj ubaubj)r(}r)(jYX@REM if not defined LIMIT_BOARDS set LIMIT_BOARDS=evmAM572x idkAM571x idkAM572x if not defined LIMIT_BOARDS set LIMIT_BOARDS=myCustomBoardjZjjbjljdjjf}r*(jjjk]jj]jh]ji]jn]ujpM jqhjr]r+j{X@REM if not defined LIMIT_BOARDS set LIMIT_BOARDS=evmAM572x idkAM571x idkAM572x if not defined LIMIT_BOARDS set LIMIT_BOARDS=myCustomBoardr,r-}r.(jYUjZj(ubaubj)r/}r0(jYX**Alternative:** Invoke the build using command line options to limit the build to specific board, specific SOC and specific CORE. For example, if you want to build the A15 version of board library for AM572x EVM, you can invoke the build using:jZjjbjljdjjf}r1(jh]ji]jj]jk]jn]ujpKjqhjr]r2(j)r3}r4(jYX**Alternative:**jf}r5(jh]ji]jj]jk]jn]ujZj/jr]r6j{X Alternative:r7r8}r9(jYUjZj3ubajdjubj{X Invoke the build using command line options to limit the build to specific board, specific SOC and specific CORE. For example, if you want to build the A15 version of board library for AM572x EVM, you can invoke the build using:r:r;}r<(jYX Invoke the build using command line options to limit the build to specific board, specific SOC and specific CORE. For example, if you want to build the A15 version of board library for AM572x EVM, you can invoke the build using:jZj/ubeubj)r=}r>(jYXMgmake board_lib LIMIT_SOCS=am572x LIMIT_BOARDS=customAM572x LIMIT_CORES=a15_0jZjjbjljdjjf}r?(jjjk]jj]jh]ji]jn]ujpM! jqhjr]r@j{XMgmake board_lib LIMIT_SOCS=am572x LIMIT_BOARDS=customAM572x LIMIT_CORES=a15_0rArB}rC(jYUjZj=ubaubj)rD}rE(jYXB**Step 10 : Building the custom board with the updated settings**rFjZjjbjljdjjf}rG(jh]ji]jj]jk]jn]ujpKjqhjr]rHj)rI}rJ(jYjFjf}rK(jh]ji]jj]jk]jn]ujZjDjr]rLj{X>Step 10 : Building the custom board with the updated settingsrMrN}rO(jYUjZjIubajdjubaubj)rP}rQ(jYXlTo build package change directory to /pdk_am57xx_x_x_x/packages, first run pdksetupenv.batrRjZjjbjljdjjf}rS(jh]ji]jj]jk]jn]ujpKjqhjr]rTj{XlTo build package change directory to /pdk_am57xx_x_x_x/packages, first run pdksetupenv.batrUrV}rW(jYjRjZjPubaubj)rX}rY(jYX/To make just the board library: gmake board_librZjZjjbjljdjjf}r[(jh]ji]jj]jk]jn]ujpKjqhjr]r\j{X/To make just the board library: gmake board_libr]r^}r_(jYjZjZjXubaubeubj[)r`}ra(jYUjZjZjbjljdjejf}rb(jh]ji]jj]jk]rcU*example-custom-board-library-for-referencerdajn]rehWaujpKjqhjr]rf(jt)rg}rh(jYX*Example custom Board library for referencerijZj`jbjljdjxjf}rj(jh]ji]jj]jk]jn]ujpKjqhjr]rkj{X*Example custom Board library for referencerlrm}rn(jYjijZjgubaubj)ro}rp(jYXThe package provided below provides updated files for building customBoard "customAM572x" following all steps described above. Please compare the files to the evmAM57xx board library files to follow the steps to add your own board library.rqjZj`jbjljdjjf}rr(jh]ji]jj]jk]jn]ujpKjqhjr]rsj{XThe package provided below provides updated files for building customBoard "customAM572x" following all steps described above. Please compare the files to the evmAM57xx board library files to follow the steps to add your own board library.rtru}rv(jYjqjZjoubaubj)rw}rx(jYX`File:Pdk packages ti board customAM572x.zip `__ryjZj`jbjljdjjf}rz(jh]ji]jj]jk]jn]ujpMjqhjr]r{j)r|}r}(jYjyjf}r~(UnameX+File:Pdk packages ti board customAM572x.zipjXQ/index.php?title=Special:Upload&wpDestFile=Pdk_packages_ti_board_customAM572x.zipjk]jj]jh]ji]jn]ujZjwjr]rj{X+File:Pdk packages ti board customAM572x.ziprr}r(jYUjZj|ubajdjubaubj)r}r(jYXDue to software distribution policy on the wiki, we have removed the file linked here. Users can refer to the discussion and zipped package linked from E2E post provided below:jZj`jbjljdjjf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXDue to software distribution policy on the wiki, we have removed the file linked here. Users can refer to the discussion and zipped package linked from E2E post provided below:rjZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XDue to software distribution policy on the wiki, we have removed the file linked here. Users can refer to the discussion and zipped package linked from E2E post provided below:rr}r(jYjjZjubaubaubjC)r}r(jYUjZj`jbjljdj`jf}r(jGX-jk]jj]jh]ji]jn]ujpM jqhjr]rj/)r}r(jYX`E2E post on creation of custom board library `__ jZjjbjljdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYX~`E2E post on creation of custom board library `__rjZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpM jr]rj)r}r(jYjjf}r(UnameX,E2E post on creation of custom board libraryjXKhttps://e2e.ti.com/support/arm/sitara_arm/f/791/p/555022/2040948#pi316653=2jk]jj]jh]ji]jn]ujZjjr]rj{X,E2E post on creation of custom board libraryrr}r(jYUjZjubajdjubaubaubaubeubj[)r}r(jYUjZjZjbjljdjejf}r(jh]ji]jj]jk]rU(additional-steps-for-am335x-am437x-usersrajn]rhaujpM jqhjr]r(jt)r}r(jYX(Additional steps for AM335x/AM437x usersrjZjjbjljdjxjf}r(jh]ji]jj]jk]jn]ujpM jqhjr]rj{X(Additional steps for AM335x/AM437x usersrr}r(jYjjZjubaubj)r}r(jYXNCurrently the AM335x and AM437x board libraries re-use the board support that was used in legacy starterware software. AM335x and AM437x users will need to additionally modify build files in starterware to build their custom board library. Additional steps required for AM335x/AM437x will be added to this article soon in this sectionjZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXNCurrently the AM335x and AM437x board libraries re-use the board support that was used in legacy starterware software. AM335x and AM437x users will need to additionally modify build files in starterware to build their custom board library. Additional steps required for AM335x/AM437x will be added to this article soon in this sectionrjZjjbjljdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XNCurrently the AM335x and AM437x board libraries re-use the board support that was used in legacy starterware software. AM335x and AM437x users will need to additionally modify build files in starterware to build their custom board library. Additional steps required for AM335x/AM437x will be added to this article soon in this sectionrr}r(jYjjZjubaubaubeubeubj[)r}r(jYUjZjKjbjcjdjejf}r(jh]ji]jj]jk]rU?processor-sdk-rtos-porting-guide-for-am571x-am570x-speed-gradesrajn]rh,aujpKLjqhjr]r(jt)r}r(jYX?Processor SDK RTOS Porting Guide for AM571x/AM570x Speed GradesrjZjjbjcjdjxjf}r(jh]ji]jj]jk]jn]ujpKLjqhjr]rj{X?Processor SDK RTOS Porting Guide for AM571x/AM570x Speed Gradesrr}r(jYjjZjubaubj)r}r(jYXghttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_Porting_Guide_for_AM571x/AM570x_Speed_GradesjZjjbjX^source/rtos/How_to_Guides/Host/Porting/PSDK_RTOS_Porting_Guide_for_AM57xx_Speed_Grades.rst.incrr}rbjdjjf}r(jjjk]jj]jh]ji]jn]ujpKjqhjr]rj{Xghttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_Porting_Guide_for_AM571x/AM570x_Speed_Gradesrr}r(jYUjZjubaubj[)r}r(jYUjKjZjjbjjdjejf}r(jh]rj:aji]jj]jk]rUid30rajn]ujpKjqhjr]r(jt)r}r(jYX DescriptionrjZjjbjjdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X Descriptionrr}r(jYjjZjubaubj)r}r(jYXThe AM57x Family of Processors includes a wide range of operating performance to meet the needs of a number of broad applications. Among these options are a variety of speed grades to meet different performance points. These devices have a number of specialized cores to provide applications specific computation capabilities. These cores can be run at different speeds to fine tune the processor to the needs of the application, power budget, thermal characteristics, etc.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XThe AM57x Family of Processors includes a wide range of operating performance to meet the needs of a number of broad applications. Among these options are a variety of speed grades to meet different performance points. These devices have a number of specialized cores to provide applications specific computation capabilities. These cores can be run at different speeds to fine tune the processor to the needs of the application, power budget, thermal characteristics, etc.rr}r(jYjjZjubaubj)r}r(jYXKThe Processor SDK for RTOS is a software development package provided to speed development by providing a software reference. This package now includes support for then entire AM57x family of processors which can be broken down into the AM572x, AM571x, and AM570x sets of devices or sub-familes. Most of the devices in this family are supported by the Processor SDK for RTOS right out of the box. This support is tested and validated on TI designed EVMs. These EVMs use the highest performance devices in the family in order to allow users to evaluate the entire spectrum of performance.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XKThe Processor SDK for RTOS is a software development package provided to speed development by providing a software reference. This package now includes support for then entire AM57x family of processors which can be broken down into the AM572x, AM571x, and AM570x sets of devices or sub-familes. Most of the devices in this family are supported by the Processor SDK for RTOS right out of the box. This support is tested and validated on TI designed EVMs. These EVMs use the highest performance devices in the family in order to allow users to evaluate the entire spectrum of performance.rr}r(jYjjZjubaubj)r}r(jYX?The AM571X and AM570x supports several lower power speed grades. If one of these devices is being used on the custom board, the GEL file and the board library needs to be changed to account for this difference. If this change is not made, the device could be running out of specification. These changes may reach across other cores and clocks on the device as well, depending on what speeds they need to operate at. This document is not an exhaustive list of all the changes needed for a proper board port as it focused on the changes needed to enable different speed grades.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X?The AM571X and AM570x supports several lower power speed grades. If one of these devices is being used on the custom board, the GEL file and the board library needs to be changed to account for this difference. If this change is not made, the device could be running out of specification. These changes may reach across other cores and clocks on the device as well, depending on what speeds they need to operate at. This document is not an exhaustive list of all the changes needed for a proper board port as it focused on the changes needed to enable different speed grades.rr}r(jYjjZjubaubeubj[)r}r(jYUjZjjbjjdjejf}r(jh]ji]jj]jk]rU.comparison-of-am572x-am571x-and-am570x-devicesrajn]rhaujpK#jqhjr]r(jt)r}r(jYX/Comparison of AM572x, AM571x and AM570x devicesrjZjjbjjdjxjf}r(jh]ji]jj]jk]jn]ujpK#jqhjr]r j{X/Comparison of AM572x, AM571x and AM570x devicesr r }r (jYjjZjubaubj)r }r(jYXK**Quick Feature Set comparison between devices in Sitara AM57xx family :**rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK%jqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZj jr]rj{XGQuick Feature Set comparison between devices in Sitara AM57xx family :rr}r(jYUjZjubajdjubaubjB)r}r(jYX9.. Image:: ../images/AM572x_AM571X_AM570x_Comparison.png jZjjbjjdjEjf}r(UuriX2rtos/../images/AM572x_AM571X_AM570x_Comparison.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpK)jqhjr]ubjZ)r}r(jYUjZjjbjjdj]jf}r (jh]ji]jj]jk]jn]ujpK*jqhjr]r!(j`)r"}r#(jYUjcKjZjjbjjdjpjf}r$(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)r%}r&(jYX$**Supported OPP on AM57xx devices:**r'jcKjZjjbjjdjpjf}r((jh]ji]jj]jk]jn]ujpK+jqhjr]r)j)r*}r+(jYj'jf}r,(jh]ji]jj]jk]jn]ujZj%jr]r-j{X Supported OPP on AM57xx devices:r.r/}r0(jYUjZj*ubajdjubaubeubjB)r1}r2(jYX$.. Image:: ../images/AM57xx_OPP.png jZjjbjjdjEjf}r3(UuriXrtos/../images/AM57xx_OPP.pngr4jk]jj]jh]ji]jH}r5U*j4sjn]ujpK.jqhjr]ubeubj[)r6}r7(jYUjZjjbjjdjejf}r8(jh]ji]jj]jk]r9U.code-composer-studio-ccs-and-emulation-supportr:ajn]r;haujpK0jqhjr]r<(jt)r=}r>(jYX0Code Composer Studio (CCS) and Emulation supportr?jZj6jbjjdjxjf}r@(jh]ji]jj]jk]jn]ujpK0jqhjr]rAj{X0Code Composer Studio (CCS) and Emulation supportrBrC}rD(jYj?jZj=ubaubj)rE}rF(jYXFTI Supports following evaluation platform for AM57xx class of devices:rGjZj6jbjjdjjf}rH(jh]ji]jj]jk]jn]ujpK2jqhjr]rIj{XFTI Supports following evaluation platform for AM57xx class of devices:rJrK}rL(jYjGjZjEubaubjC)rM}rN(jYUjZj6jbjjdj`jf}rO(jGX-jk]jj]jh]ji]jn]ujpK4jqhjr]rP(j/)rQ}rR(jYXP`AM572x GP EVM `__rSjZjMjbjjdj2jf}rT(jh]ji]jj]jk]jn]ujpNjqhjr]rUj)rV}rW(jYjSjZjQjbjjdjjf}rX(jh]ji]jj]jk]jn]ujpK4jr]rYj)rZ}r[(jYjSjf}r\(UnameX AM572x GP EVMjX<index_release_specific.html#supported-platforms-and-versionsjk]jj]jh]ji]jn]ujZjVjr]r]j{X AM572x GP EVMr^r_}r`(jYUjZjZubajdjubaubaubj/)ra}rb(jYXM`AM571x IDK `__rcjZjMjbjjdj2jf}rd(jh]ji]jj]jk]jn]ujpNjqhjr]rej)rf}rg(jYjcjZjajbjjdjjf}rh(jh]ji]jj]jk]jn]ujpK5jr]rij)rj}rk(jYjcjf}rl(UnameX AM571x IDKjX<index_release_specific.html#supported-platforms-and-versionsjk]jj]jh]ji]jn]ujZjfjr]rmj{X AM571x IDKrnro}rp(jYUjZjjubajdjubaubaubj/)rq}rr(jYXN`AM572x IDK `__ jZjMjbjjdj2jf}rs(jh]ji]jj]jk]jn]ujpNjqhjr]rtj)ru}rv(jYXM`AM572x IDK `__rwjZjqjbjjdjjf}rx(jh]ji]jj]jk]jn]ujpK6jr]ryj)rz}r{(jYjwjf}r|(UnameX AM572x IDKjX<index_release_specific.html#supported-platforms-and-versionsjk]jj]jh]ji]jn]ujZjujr]r}j{X AM572x IDKr~r}r(jYUjZjzubajdjubaubaubeubj)r}r(jYXWhen developer selects any of the above platforms in Code composer Studio, the target configuration automatically brings in the required initialization files and GEL files to configure the clocks, slave cores, external memory.rjZj6jbjjdjjf}r(jh]ji]jj]jk]jn]ujpK8jqhjr]rj{XWhen developer selects any of the above platforms in Code composer Studio, the target configuration automatically brings in the required initialization files and GEL files to configure the clocks, slave cores, external memory.rr}r(jYjjZjubaubj)r}r(jYXIf you are using a custom platform or AM5708 device that is not available on a TI Evaluation platform, you can follow the steps provided below to connect to the SOC by reusing the GEL files that are provided for TI evaluation platforms. For example, here we demonstrate how you can create a target configuration for AM570x and connect to the device if your board design is based of one of TI evalauation platforms listed below. The assumption here is that the custom board is based off AM571X IDK platformrjZj6jbjjdjjf}r(jh]ji]jj]jk]jn]ujpK=jqhjr]rj{XIf you are using a custom platform or AM5708 device that is not available on a TI Evaluation platform, you can follow the steps provided below to connect to the SOC by reusing the GEL files that are provided for TI evaluation platforms. For example, here we demonstrate how you can create a target configuration for AM570x and connect to the device if your board design is based of one of TI evalauation platforms listed below. The assumption here is that the custom board is based off AM571X IDK platformrr}r(jYjjZjubaubj)r}r(jYX-Support for AM5708 was added to Sitara Chip Support Package 1.3.4 in Code composer Studio. If you don`t see the device definition in CCS, then you can update the Sitara Chip Support package by going to `Help->Check Updates `__jZj6jbjjdjjf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYX-Support for AM5708 was added to Sitara Chip Support Package 1.3.4 in Code composer Studio. If you don`t see the device definition in CCS, then you can update the Sitara Chip Support package by going to `Help->Check Updates `__jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKGjr]r(j{XSupport for AM5708 was added to Sitara Chip Support Package 1.3.4 in Code composer Studio. If you don`t see the device definition in CCS, then you can update the Sitara Chip Support package by going to rr}r(jYXSupport for AM5708 was added to Sitara Chip Support Package 1.3.4 in Code composer Studio. If you don`t see the device definition in CCS, then you can update the Sitara Chip Support package by going to jZjubj)r}r(jYXc`Help->Check Updates `__jf}r(UnameXHelp->Check UpdatesjXIhttp://ap-fpdsp-swapps.dal.design.ti.com/index.php/File:Check_Updates.pngjk]jj]jh]ji]jn]ujZjjr]rj{XHelp->Check Updatesrr}r(jYUjZjubajdjubeubaubj)r}r(jYXT**Step 1: Select the AM570x part number that is populated on your custom platform:**rjZj6jbjjdjjf}r(jh]ji]jj]jk]jn]ujpKNjqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XPStep 1: Select the AM570x part number that is populated on your custom platform:rr}r(jYUjZjubajdjubaubjB)r}r(jYX:.. Image:: ../images/AM5708_EVM_target_configurations.png jZj6jbjjdjEjf}r(UuriX3rtos/../images/AM5708_EVM_target_configurations.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpKRjqhjr]ubj)r}r(jYX**Step 2: Setup the GEL files for the SOC** Go to the Advanced Tab as shown in the previous screenshot and update startup GEL file in the A15 Core as shown in the screenshot belowjZj6jbjjdjjf}r(jh]ji]jj]jk]jn]ujpKSjqhjr]r(j)r}r(jYX+**Step 2: Setup the GEL files for the SOC**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X'Step 2: Setup the GEL files for the SOCrr}r(jYUjZjubajdjubj{X Go to the Advanced Tab as shown in the previous screenshot and update startup GEL file in the A15 Core as shown in the screenshot belowrr}r(jYX Go to the Advanced Tab as shown in the previous screenshot and update startup GEL file in the A15 Core as shown in the screenshot belowjZjubeubjB)r}r(jYX5.. Image:: ../images/Advanced_settings_GEL_setup.png jZj6jbjjdjEjf}r(UuriX.rtos/../images/Advanced_settings_GEL_setup.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpKXjqhjr]ubeubj[)r}r(jYUjZjjbjjdjejf}r(jh]ji]jj]jk]rU>board-library-changes-to-consider-for-using-processor-sdk-rtosrajn]rhaujpKZjqhjr]r(jt)r}r(jYX>Board Library Changes to Consider for Using Processor SDK RTOSrjZjjbjjdjxjf}r(jh]ji]jj]jk]jn]ujpKZjqhjr]rj{X>Board Library Changes to Consider for Using Processor SDK RTOSrr}r(jYjjZjubaubj[)r}r(jYUjZjjbjjdjejf}r(jh]ji]jj]jk]rU"clock-and-prcm-updates-to-considerrajn]rhtaujpK]jqhjr]r(jt)r}r(jYX"Clock and PRCM Updates to considerrjZjjbjjdjxjf}r(jh]ji]jj]jk]jn]ujpK]jqhjr]rj{X"Clock and PRCM Updates to considerrr}r(jYjjZjubaubj)r}r(jYXkThe board library provides setting for OPP_NOM, OPP_OD and OPP_HIGH in the PLL settings using 20 MHz input clock that has been used on the AM572x GP EVM as well as the AM571x IDK platform. This allows customers to setup the MPU to 1.5, 1.176 and 1GHz. For AM570x devices, we support the "J" and the "D" variant which support the following max speeds on the DPLLs:rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK_jqhjr]rj{XkThe board library provides setting for OPP_NOM, OPP_OD and OPP_HIGH in the PLL settings using 20 MHz input clock that has been used on the AM572x GP EVM as well as the AM571x IDK platform. This allows customers to setup the MPU to 1.5, 1.176 and 1GHz. For AM570x devices, we support the "J" and the "D" variant which support the following max speeds on the DPLLs:rr}r(jYjjZjubaubjB)r}r(jYX-.. Image:: ../images/AM5706_Speed_Grades.png jZjjbjjdjEjf}r(UuriX&rtos/../images/AM5706_Speed_Grades.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpKgjqhjr]ubj)r}r(jYXzWhen using the "J" speed grade, ensure that the DPLLs in the board set the DPLL to OPP_NOM and not for OPP_OD or OPP_HIGH.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKhjqhjr]rj{XzWhen using the "J" speed grade, ensure that the DPLLs in the board set the DPLL to OPP_NOM and not for OPP_OD or OPP_HIGH.rr}r(jYjjZjubaubj)r}r(jYXLTo do this, you can invoke the Board_Init from your application using eitherrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKkjqhjr]rj{XLTo do this, you can invoke the Board_Init from your application using eitherrr }r (jYjjZjubaubj)r }r (jYX/Board_initCfg boardCfg; boardCfg = BOARD_INIT_PLL_OPP_NOM; boardCfg |= BOARD_INIT_UNLOCK_MMR | BOARD_INIT_MODULE_CLOCK | BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_DDR | BOARD_INIT_UART_STDIO | BOARD_INIT_WATCHDOG_DISABLE; /* Board Library Init. */ Board_init(boardCfg);jZjjbjjdjjf}r (jjXcjjjk]jj]jh]j }ji]jn]ujpKnjqhjr]r j{X/Board_initCfg boardCfg; boardCfg = BOARD_INIT_PLL_OPP_NOM; boardCfg |= BOARD_INIT_UNLOCK_MMR | BOARD_INIT_MODULE_CLOCK | BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_DDR | BOARD_INIT_UART_STDIO | BOARD_INIT_WATCHDOG_DISABLE; /* Board Library Init. */ Board_init(boardCfg);r r }r (jYUjZj ubaubj)r }r (jYXZWhen bootloading direct from flash media, this change may also be required in the SBL codejZjjbjjdjjf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYXZWhen bootloading direct from flash media, this change may also be required in the SBL coder jZj jbjjdjjf}r (jh]ji]jj]jk]jn]ujpK|jr]r j{XZWhen bootloading direct from flash media, this change may also be required in the SBL coder r }r (jYj jZj ubaubaubj)r }r (jYXWhen using "D" rated parts that run at 500 MHz, in addition to the above configuration, you will also need to modify OPP_NOM settings in the board library by updating the DPLL setting for MPU and DSP in the file _pll.c as shown below:r jZjjbjjdjjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r j{XWhen using "D" rated parts that run at 500 MHz, in addition to the above configuration, you will also need to modify OPP_NOM settings in the board library by updating the DPLL setting for MPU and DSP in the file _pll.c as shown below:r r }r (jYj jZj ubaubj)r }r (jYX6**Step1 : Update MPU, DSP, IVA and GPU DPLL setting**r jZjjbjjdjjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r! j)r" }r# (jYj jf}r$ (jh]ji]jj]jk]jn]ujZj jr]r% j{X2Step1 : Update MPU, DSP, IVA and GPU DPLL settingr& r' }r( (jYUjZj" ubajdjubaubjC)r) }r* (jYUjZjjbjjdj`jf}r+ (jGX-jk]jj]jh]ji]jn]ujpKjqhjr]r, j/)r- }r. (jYX**MPU DPLL Changes:** jZj) jbjjdj2jf}r/ (jh]ji]jj]jk]jn]ujpNjqhjr]r0 j)r1 }r2 (jYX**MPU DPLL Changes:**r3 jZj- jbjjdjjf}r4 (jh]ji]jj]jk]jn]ujpKjr]r5 j)r6 }r7 (jYj3 jf}r8 (jh]ji]jj]jk]jn]ujZj1 jr]r9 j{XMPU DPLL Changes:r: r; }r< (jYUjZj6 ubajdjubaubaubaubj)r= }r> (jYX/* Default to OPP_NOM */ /* 500MHz at 20MHz sys_clk */ mpuPllcParam.mult = 250U; mpuPllcParam.div = 9U; mpuPllcParam.dccEnable = 0U; mpuPllcParam.divM2 = 1U;jZjjbjjdjjf}r? (jjXcjjjk]jj]jh]j }ji]jn]ujpKjqhjr]r@ j{X/* Default to OPP_NOM */ /* 500MHz at 20MHz sys_clk */ mpuPllcParam.mult = 250U; mpuPllcParam.div = 9U; mpuPllcParam.dccEnable = 0U; mpuPllcParam.divM2 = 1U;rA rB }rC (jYUjZj= ubaubjC)rD }rE (jYUjZjjbjjdj`jf}rF (jGX-jk]jj]jh]ji]jn]ujpKjqhjr]rG j/)rH }rI (jYX**DSP DPLL Changes:** jZjD jbjjdj2jf}rJ (jh]ji]jj]jk]jn]ujpNjqhjr]rK j)rL }rM (jYX**DSP DPLL Changes:**rN jZjH jbjjdjjf}rO (jh]ji]jj]jk]jn]ujpKjr]rP j)rQ }rR (jYjN jf}rS (jh]ji]jj]jk]jn]ujZjL jr]rT j{XDSP DPLL Changes:rU rV }rW (jYUjZjQ ubajdjubaubaubaubj)rX }rY (jYX/* 500MHz at 20MHz sys_clk */ dspPllcParam.mult = 130U; dspPllcParam.div = 3U; dspPllcParam.divM2 = 1U; dspPllcParam.divM3 = 3U;jZjjbjjdjjf}rZ (jjXcjjjk]jj]jh]j }ji]jn]ujpKjqhjr]r[ j{X/* 500MHz at 20MHz sys_clk */ dspPllcParam.mult = 130U; dspPllcParam.div = 3U; dspPllcParam.divM2 = 1U; dspPllcParam.divM3 = 3U;r\ r] }r^ (jYUjZjX ubaubjC)r_ }r` (jYUjZjjbjjdj`jf}ra (jGX-jk]jj]jh]ji]jn]ujpKjqhjr]rb j/)rc }rd (jYX$**Remove IVA and GPU PLL settings** jZj_ jbjjdj2jf}re (jh]ji]jj]jk]jn]ujpNjqhjr]rf j)rg }rh (jYX#**Remove IVA and GPU PLL settings**ri jZjc jbjjdjjf}rj (jh]ji]jj]jk]jn]ujpKjr]rk j)rl }rm (jYji jf}rn (jh]ji]jj]jk]jn]ujZjg jr]ro j{XRemove IVA and GPU PLL settingsrp rq }rr (jYUjZjl ubajdjubaubaubaubj)rs }rt (jYXySince IVA and GPU modules are not available on the device, we recommend removing the ivaPLL and gpuPLL settings in board.ru jZjjbjjdjjf}rv (jh]ji]jj]jk]jn]ujpKjqhjr]rw j{XySince IVA and GPU modules are not available on the device, we recommend removing the ivaPLL and gpuPLL settings in board.rx ry }rz (jYju jZjs ubaubj)r{ }r| (jYX /* Default to OPP_NOM */ /* 388.3MHz at 20MHz sys_clk */ - ivaPllcParam.mult = 233U; - ivaPllcParam.div = 3U; - ivaPllcParam.divM2 = 3U; /* Default to OPP_NOM */ /* 425MHz at 20MHz sys_clk */ - gpuPllcParam.mult = 170U; - gpuPllcParam.div = 3U; - gpuPllcParam.divM2 = 2U;jZjjbjjdjjf}r} (jjXcjjjk]jj]jh]j }ji]jn]ujpKjqhjr]r~ j{X /* Default to OPP_NOM */ /* 388.3MHz at 20MHz sys_clk */ - ivaPllcParam.mult = 233U; - ivaPllcParam.div = 3U; - ivaPllcParam.divM2 = 3U; /* Default to OPP_NOM */ /* 425MHz at 20MHz sys_clk */ - gpuPllcParam.mult = 170U; - gpuPllcParam.div = 3U; - gpuPllcParam.divM2 = 2U;r r }r (jYUjZj{ ubaubj)r }r (jYXE**Step 2 : Disable clocks configuration and wakeup for IVA in PRCM**r jZjjbjjdjjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r j)r }r (jYj jf}r (jh]ji]jj]jk]jn]ujZj jr]r j{XAStep 2 : Disable clocks configuration and wakeup for IVA in PRCMr r }r (jYUjZj ubajdjubaubjC)r }r (jYUjZjjbjjdj`jf}r (jGX-jk]jj]jh]ji]jn]ujpKjqhjr]r j/)r }r (jYX/**Remove IVA wakeup and Module configuration** jZj jbjjdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYX.**Remove IVA wakeup and Module configuration**r jZj jbjjdjjf}r (jh]ji]jj]jk]jn]ujpKjr]r j)r }r (jYj jf}r (jh]ji]jj]jk]jn]ujZj jr]r j{X*Remove IVA wakeup and Module configurationr r }r (jYUjZj ubajdjubaubaubaubj)r }r (jYXrThe following updates need to be made in the file _clock.c to remove IVA wakeup and clock configurationr jZjjbjjdjjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r j{XrThe following updates need to be made in the file _clock.c to remove IVA wakeup and clock configurationr r }r (jYj jZj ubaubj)r }r (jYX- CSL_FINST(ivaCmReg->CM_IVA_CLKSTCTRL_REG, - IVA_CM_CORE_CM_IVA_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP); /* PRCM Specialized module mode setting functions */ - CSL_FINST(ivaCmReg->CM_IVA_SL2_CLKCTRL_REG, - IVA_CM_CORE_CM_IVA_SL2_CLKCTRL_REG_MODULEMODE, AUTO); - while(CSL_IVA_CM_CORE_CM_IVA_SL2_CLKCTRL_REG_IDLEST_DISABLE == - CSL_FEXT(ivaCmReg->CM_IVA_SL2_CLKCTRL_REG, - IVA_CM_CORE_CM_IVA_SL2_CLKCTRL_REG_IDLEST)); - CSL_FINST(ivaCmReg->CM_IVA_IVA_CLKCTRL_REG, - IVA_CM_CORE_CM_IVA_IVA_CLKCTRL_REG_MODULEMODE, AUTO); - while(CSL_IVA_CM_CORE_CM_IVA_IVA_CLKCTRL_REG_IDLEST_DISABLE == - CSL_FEXT(ivaCmReg->CM_IVA_IVA_CLKCTRL_REG, - IVA_CM_CORE_CM_IVA_IVA_CLKCTRL_REG_IDLEST));jZjjbjjdjjf}r (jjXcjjjk]jj]jh]j }ji]jn]ujpKjqhjr]r j{X- CSL_FINST(ivaCmReg->CM_IVA_CLKSTCTRL_REG, - IVA_CM_CORE_CM_IVA_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP); /* PRCM Specialized module mode setting functions */ - CSL_FINST(ivaCmReg->CM_IVA_SL2_CLKCTRL_REG, - IVA_CM_CORE_CM_IVA_SL2_CLKCTRL_REG_MODULEMODE, AUTO); - while(CSL_IVA_CM_CORE_CM_IVA_SL2_CLKCTRL_REG_IDLEST_DISABLE == - CSL_FEXT(ivaCmReg->CM_IVA_SL2_CLKCTRL_REG, - IVA_CM_CORE_CM_IVA_SL2_CLKCTRL_REG_IDLEST)); - CSL_FINST(ivaCmReg->CM_IVA_IVA_CLKCTRL_REG, - IVA_CM_CORE_CM_IVA_IVA_CLKCTRL_REG_MODULEMODE, AUTO); - while(CSL_IVA_CM_CORE_CM_IVA_IVA_CLKCTRL_REG_IDLEST_DISABLE == - CSL_FEXT(ivaCmReg->CM_IVA_IVA_CLKCTRL_REG, - IVA_CM_CORE_CM_IVA_IVA_CLKCTRL_REG_IDLEST));r r }r (jYUjZj ubaubeubeubj[)r }r (jYUjZjjbjjdjejf}r (jh]ji]jj]jk]r Uconfigure-ddr-interfacesr ajn]r jBaujpKjqhjr]r (jt)r }r (jYXConfigure DDR Interfacesr jZj jbjjdjxjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r j{XConfigure DDR Interfacesr r }r (jYj jZj ubaubj)r }r (jYXVAn important one to consider is the speed of the DDR memory. The clock for the DDR is selected using the same dplls structure. Some higher speed grade parts support a 667 MHz DDR clock, but some of the lower speed grade parts only support a 533 MHz DDR3 clock. Make sure to choose the appropriate DDR clock for the device on the custom board.r jZj jbjjdjjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r j{XVAn important one to consider is the speed of the DDR memory. The clock for the DDR is selected using the same dplls structure. Some higher speed grade parts support a 667 MHz DDR clock, but some of the lower speed grade parts only support a 533 MHz DDR3 clock. Make sure to choose the appropriate DDR clock for the device on the custom board.r r }r (jYj jZj ubaubj)r }r (jYX#Over in the board/src//.c file, make sure that the EMIF is being configured correctly for the appropriate speed, and that the appropriate number of EMIFs is being selected to match the part being used. AM572x part has 2 DDR interfaces running at 533 MHz and the AM571x (and AM570x) only have one running at 667 MHz. This code can be kept or removed by the board port. As changes are made, the code must make sure to configure the new board correctly, with the appropriate number of DDR interfaces and speed configuration.r jZj jbjjdjjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r j{X#Over in the board/src//.c file, make sure that the EMIF is being configured correctly for the appropriate speed, and that the appropriate number of EMIFs is being selected to match the part being used. AM572x part has 2 DDR interfaces running at 533 MHz and the AM571x (and AM570x) only have one running at 667 MHz. This code can be kept or removed by the board port. As changes are made, the code must make sure to configure the new board correctly, with the appropriate number of DDR interfaces and speed configuration.r r }r (jYj jZj ubaubj)r }r (jYXFor AM571x and AM570x, make sure to use the code for the AM571x IDK in board/src//.c to select 1 EMIF:r jZj jbjjdjjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r j{XFor AM571x and AM570x, make sure to use the code for the AM571x IDK in board/src//.c to select 1 EMIF:r r }r (jYj jZj ubaubj)r }r (jYXm/* MA_LISA_MAP_i */ hMampuLsm->MAP_0 = 0x80600100U; /* DMM_LISA_MAP_i */ hDmmCfg->LISA_MAP[0U] = 0x80600100U;jZj jbjjdjjf}r (jjXcjjjk]jj]jh]j }ji]jn]ujpKjqhjr]r j{Xm/* MA_LISA_MAP_i */ hMampuLsm->MAP_0 = 0x80600100U; /* DMM_LISA_MAP_i */ hDmmCfg->LISA_MAP[0U] = 0x80600100U;r r }r (jYUjZj ubaubj)r }r (jYX'For AM572x, this is mapped as followingr jZj jbjjdjjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r j{X'For AM572x, this is mapped as followingr r }r (jYj jZj ubaubj)r }r (jYX/* MA_LISA_MAP_i */ hMampuLsm->MAP_0 = 0x80740300; hMampuLsm->MAP_1 = 0x80740300; /* DMM_LISA_MAP_i */ hDmmCfg->LISA_MAP[0U] = 0x80740300; hDmmCfg->LISA_MAP[1U] = 0x80740300;jZj jbjjdjjf}r (jjXcjjjk]jj]jh]j }ji]jn]ujpKjqhjr]r j{X/* MA_LISA_MAP_i */ hMampuLsm->MAP_0 = 0x80740300; hMampuLsm->MAP_1 = 0x80740300; /* DMM_LISA_MAP_i */ hDmmCfg->LISA_MAP[0U] = 0x80740300; hDmmCfg->LISA_MAP[1U] = 0x80740300;r r }r (jYUjZj ubaubj)r }r (jYX~Processor SDK RTOS provides am570x_ddr.c file in the idkAM571x board library for reference for configuring DDR on AM570x partsjZj jbjjdjjf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYX~Processor SDK RTOS provides am570x_ddr.c file in the idkAM571x board library for reference for configuring DDR on AM570x partsr jZj jbjjdjjf}r (jh]ji]jj]jk]jn]ujpKjr]r j{X~Processor SDK RTOS provides am570x_ddr.c file in the idkAM571x board library for reference for configuring DDR on AM570x partsr r }r (jYj jZj ubaubaubeubj[)r }r (jYUjZjjbjjdjejf}r (jh]ji]jj]jk]r Upinmux-changes-to-considerr ajn]r jJaujpKjqhjr]r!(jt)r!}r!(jYXPinmux Changes to Considerr!jZj jbjjdjxjf}r!(jh]ji]jj]jk]jn]ujpKjqhjr]r!j{XPinmux Changes to Considerr!r!}r!(jYj!jZj!ubaubjC)r !}r !(jYUjZj jbjjdj`jf}r !(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]r !(j/)r !}r!(jYXFor part number where the Display subsystem or SATA is not available, the pins can be configured to any other pin functionality that may be required in the system. If you don`t need to use these pins, we recommend that you leave these pins in default MUXMODE and terminate the pinmux as recommended in the `Schematics Checklist `__.jZj !jbjjdj2jf}r!(jh]ji]jj]jk]jn]ujpNjqhjr]r!j)r!}r!(jYXFor part number where the Display subsystem or SATA is not available, the pins can be configured to any other pin functionality that may be required in the system. If you don`t need to use these pins, we recommend that you leave these pins in default MUXMODE and terminate the pinmux as recommended in the `Schematics Checklist `__.jZj !jbjjdjjf}r!(jh]ji]jj]jk]jn]ujpKjr]r!(j{X2For part number where the Display subsystem or SATA is not available, the pins can be configured to any other pin functionality that may be required in the system. If you don`t need to use these pins, we recommend that you leave these pins in default MUXMODE and terminate the pinmux as recommended in the r!r!}r!(jYX2For part number where the Display subsystem or SATA is not available, the pins can be configured to any other pin functionality that may be required in the system. If you don`t need to use these pins, we recommend that you leave these pins in default MUXMODE and terminate the pinmux as recommended in the jZj!ubj)r!}r!(jYX]`Schematics Checklist `__jf}r!(UnameXSchematics ChecklistjXBhttp://processors.wiki.ti.com/index.php/AM57xx_Schematic_Checklistjk]jj]jh]ji]jn]ujZj!jr]r!j{XSchematics Checklistr!r!}r!(jYUjZj!ubajdjubj{X.r!}r !(jYX.jZj!ubeubaubj/)r!!}r"!(jYXThere is no pinmux setting for CSI2 module so you can leave the MUXMODE=0 on those pins if there is no instance of the peripheral jZj !jbjjdj2jf}r#!(jh]ji]jj]jk]jn]ujpNjqhjr]r$!j)r%!}r&!(jYXThere is no pinmux setting for CSI2 module so you can leave the MUXMODE=0 on those pins if there is no instance of the peripheralr'!jZj!!jbjjdjjf}r(!(jh]ji]jj]jk]jn]ujpKjr]r)!j{XThere is no pinmux setting for CSI2 module so you can leave the MUXMODE=0 on those pins if there is no instance of the peripheralr*!r+!}r,!(jYj'!jZj%!ubaubaubeubj)r-!}r.!(jYXProcessor SDK RTOS provides board/src/idkAM571x/include/am570x_pinmux.h file in the idkAM571x board library for reference for configuring pinmux on AM570x based hardware platformjZj jbjjdjjf}r/!(jh]ji]jj]jk]jn]ujpNjqhjr]r0!j)r1!}r2!(jYXProcessor SDK RTOS provides board/src/idkAM571x/include/am570x_pinmux.h file in the idkAM571x board library for reference for configuring pinmux on AM570x based hardware platformr3!jZj-!jbjjdjjf}r4!(jh]ji]jj]jk]jn]ujpMjr]r5!j{XProcessor SDK RTOS provides board/src/idkAM571x/include/am570x_pinmux.h file in the idkAM571x board library for reference for configuring pinmux on AM570x based hardware platformr6!r7!}r8!(jYj3!jZj1!ubaubaubeubj[)r9!}r:!(jYUjZjjbjjdjejf}r;!(jh]ji]jj]jk]r!hzaujpMjqhjr]r?!(jt)r@!}rA!(jYXDriver SOC Module clock changesrB!jZj9!jbjjdjxjf}rC!(jh]ji]jj]jk]jn]ujpMjqhjr]rD!j{XDriver SOC Module clock changesrE!rF!}rG!(jYjB!jZj@!ubaubj)rH!}rI!(jYX3Some control drivers use default Module input clock frequency settings in _soc.c file that gets used by the Low level drivers to configure the peripheral clocks. The default module input clock frequency is set to the OPP_NOM values that are available on the superset variant of the device so if you are using lower speed grades. Ensure you change the default to match the module clock on the 500 MHz settings or you can use the following sequence to update the settings. Code below describes how the SPI driver module input clock frequency can be modifiedrJ!jZj9!jbjjdjjf}rK!(jh]ji]jj]jk]jn]ujpMjqhjr]rL!j{X3Some control drivers use default Module input clock frequency settings in _soc.c file that gets used by the Low level drivers to configure the peripheral clocks. The default module input clock frequency is set to the OPP_NOM values that are available on the superset variant of the device so if you are using lower speed grades. Ensure you change the default to match the module clock on the 500 MHz settings or you can use the following sequence to update the settings. Code below describes how the SPI driver module input clock frequency can be modifiedrM!rN!}rO!(jYjJ!jZjH!ubaubj)rP!}rQ!(jYX%SPI_v1_HWAttrs spi_cfg; /* Get the default SPI init configurations */ SPI_socGetInitCfg(TEST_SPI_PORT, &spi_cfg); /* Modify the default SPI configurations if necessary */ spi_cfg.inputClkFreq = 24000000; /* Set the default SPI init configurations */ SPI_socSetInitCfg(TEST_SPI_PORT, &spi_cfg);jZj9!jbjjdjjf}rR!(jjXcjjjk]jj]jh]j }ji]jn]ujpMjqhjr]rS!j{X%SPI_v1_HWAttrs spi_cfg; /* Get the default SPI init configurations */ SPI_socGetInitCfg(TEST_SPI_PORT, &spi_cfg); /* Modify the default SPI configurations if necessary */ spi_cfg.inputClkFreq = 24000000; /* Set the default SPI init configurations */ SPI_socSetInitCfg(TEST_SPI_PORT, &spi_cfg);rT!rU!}rV!(jYUjZjP!ubaubeubj[)rW!}rX!(jYUjZjjbjjdjejf}rY!(jh]ji]jj]jk]rZ!U2related-article-for-processor-sdk-linux-developersr[!ajn]r\!h$aujpMjqhjr]r]!(jt)r^!}r_!(jYX2Related Article for Processor SDK Linux developersr`!jZjW!jbjjdjxjf}ra!(jh]ji]jj]jk]jn]ujpMjqhjr]rb!j{X2Related Article for Processor SDK Linux developersrc!rd!}re!(jYj`!jZj^!ubaubjC)rf!}rg!(jYUjZjW!jbjjdj`jf}rh!(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]ri!j/)rj!}rk!(jYX`Linux_Porting_Guide_for_AM571x/AM570x_Speed_Grades `__ jZjf!jbjjdj2jf}rl!(jh]ji]jj]jk]jn]ujpNjqhjr]rm!j)rn!}ro!(jYX`Linux_Porting_Guide_for_AM571x/AM570x_Speed_Grades `__rp!jZjj!jbjjdjjf}rq!(jh]ji]jj]jk]jn]ujpMjr]rr!j)rs!}rt!(jYjp!jf}ru!(UnameX2Linux_Porting_Guide_for_AM571x/AM570x_Speed_GradesjXZhttp://processors.wiki.ti.com/index.php/Linux_Porting_Guide_for_AM571x/AM570x_Speed_Gradesjk]jj]jh]ji]jn]ujZjn!jr]rv!j{X2Linux_Porting_Guide_for_AM571x/AM570x_Speed_Gradesrw!rx!}ry!(jYUjZjs!ubajdjubaubaubaubj)rz!}r{!(jYXUseful Utilitiesr|!jZjW!jbjjdjjf}r}!(jk]r~!Uuseful-utilitiesr!ajj]jh]ji]jn]r!j>aujpNjqhjr]r!j{XUseful Utilitiesr!r!}r!(jYj|!jZjz!ubaubjC)r!}r!(jYUjZjW!jbjjdj`jf}r!(jGX-jk]jj]jh]ji]jn]ujpM$jqhjr]r!(j/)r!}r!(jYX:`Clock Tree Tool `__r!jZj!jbjjdj2jf}r!(jh]ji]jj]jk]jn]ujpNjqhjr]r!j)r!}r!(jYj!jZj!jbjjdjjf}r!(jh]ji]jj]jk]jn]ujpM$jr]r!j)r!}r!(jYj!jf}r!(UnameXClock Tree TooljX$http://www.ti.com/tool/clockTreeTooljk]jj]jh]ji]jn]ujZj!jr]r!j{XClock Tree Toolr!r!}r!(jYUjZj!ubajdjubaubaubj/)r!}r!(jYX5`Pin Mux tool `__ jZj!jbjjdj2jf}r!(jh]ji]jj]jk]jn]ujpNjqhjr]r!j)r!}r!(jYX4`Pin Mux tool `__r!jZj!jbjjdjjf}r!(jh]ji]jj]jk]jn]ujpM%jr]r!j)r!}r!(jYj!jf}r!(UnameX Pin Mux tooljX!http://www.ti.com/tool/PinMuxTooljk]jj]jh]ji]jn]ujZj!jr]r!j{X Pin Mux toolr!r!}r!(jYUjZj!ubajdjubaubaubeubeubj[)r!}r!(jYUjZjjbjjdjejf}r!(jh]ji]jj]jk]r!Usupportr!ajn]r!haujpM(jqhjr]r!(jt)r!}r!(jYXSupportr!jZj!jbjjdjxjf}r!(jh]ji]jj]jk]jn]ujpM(jqhjr]r!j{XSupportr!r!}r!(jYj!jZj!ubaubj)r!}r!(jYXpFor any questions related Usage of AM572x, AM571x and AM570x devices, please post your question on TI E2E Forumsr!jZj!jbjjdjjf}r!(jh]ji]jj]jk]jn]ujpM*jqhjr]r!j{XpFor any questions related Usage of AM572x, AM571x and AM570x devices, please post your question on TI E2E Forumsr!r!}r!(jYj!jZj!ubaubjC)r!}r!(jYUjZj!jbjjdj`jf}r!(jGX-jk]jj]jh]ji]jn]ujpM-jqhjr]r!j/)r!}r!(jYXU`TI E2E Forums for Sitara Processors `__ jZj!jbjjdj2jf}r!(jh]ji]jj]jk]jn]ujpNjqhjr]r!j)r!}r!(jYXT`TI E2E Forums for Sitara Processors `__r!jZj!jbjjdjjf}r!(jh]ji]jj]jk]jn]ujpM-jr]r!j)r!}r!(jYj!jf}r!(UnameX#TI E2E Forums for Sitara ProcessorsjX*https://e2e.ti.com/support/arm/sitara_arm/jk]jj]jh]ji]jn]ujZj!jr]r!j{X#TI E2E Forums for Sitara Processorsr!r!}r!(jYUjZj!ubajdjubaubaubaubeubeubeubj[)r!}r!(jYUjZjjbjcjdjejf}r!(jh]ji]jj]jk]r!Usystem-integrationr!ajn]r!j aujpKQjqhjr]r!(jt)r!}r!(jYXSystem Integrationr!jZj!jbjcjdjxjf}r!(jh]ji]jj]jk]jn]ujpKQjqhjr]r!j{XSystem Integrationr!r!}r!(jYj!jZj!ubaubj[)r!}r!(jYUjZj!jbjcjdjejf}r!(jh]ji]jj]jk]r!U^create-dsp-and-ipu-firmware-using-pdk-drivers-and-ipc-to-load-from-arm-linux-on-am57xx-devicesr!ajn]r!haujpKTjqhjr]r!(jt)r!}r!(jYX^Create DSP and IPU firmware using PDK drivers and IPC to load from ARM Linux on AM57xx devicesr!jZj!jbjcjdjxjf}r!(jh]ji]jj]jk]jn]ujpKTjqhjr]r!j{X^Create DSP and IPU firmware using PDK drivers and IPC to load from ARM Linux on AM57xx devicesr!r!}r!(jYj!jZj!ubaubj)r!}r!(jYXihttp://processors.wiki.ti.com/index.php/Linux_IPC_on_AM57xx#Adding_IPC_to_an_Existing_TI-RTOS_ApplicationjZj!jbjXysource/rtos/How_to_Guides/Host/System_Integration/Create_DSP_and_IPU_FW_using_PDK_and_IPC_to_load_from_ARM_AM57xx.rst.incr!r!}r!bjdjjf}r!(jjjk]jj]jh]ji]jn]ujpKjqhjr]r!j{Xihttp://processors.wiki.ti.com/index.php/Linux_IPC_on_AM57xx#Adding_IPC_to_an_Existing_TI-RTOS_Applicationr!r!}r!(jYUjZj!ubaubj[)r!}r!(jYUjKjZj!jbj!jdjejf}r!(jh]r!jwaji]jj]jk]r"Uid31r"ajn]ujpKjqhjr]r"(jt)r"}r"(jYX Introductionr"jZj!jbj!jdjxjf}r"(jh]ji]jj]jk]jn]ujpKjqhjr]r"j{X Introductionr"r "}r "(jYj"jZj"ubaubj)r "}r "(jYXThis article is geared toward AM57xx users that are running Linux on the Cortex A15. The goal is to help users understand how to gain entitlement to the DSP (c66x) and IPU (Cortex M4) subsystems of the AM57xx.r "jZj!jbj!jdjjf}r"(jh]ji]jj]jk]jn]ujpKjqhjr]r"j{XThis article is geared toward AM57xx users that are running Linux on the Cortex A15. The goal is to help users understand how to gain entitlement to the DSP (c66x) and IPU (Cortex M4) subsystems of the AM57xx.r"r"}r"(jYj "jZj "ubaubj)r"}r"(jYX1AM572x device has two IPU subsystems (IPUSS), each of which has 2 cores. IPU2 is used as a controller in multi-media applications, so if you have Processor SDK Linux running, chances are that IPU2 already has firmware loaded. However, IPU1 is open for general purpose programming to offload the ARM tasks.r"jZj!jbj!jdjjf}r"(jh]ji]jj]jk]jn]ujpK jqhjr]r"j{X1AM572x device has two IPU subsystems (IPUSS), each of which has 2 cores. IPU2 is used as a controller in multi-media applications, so if you have Processor SDK Linux running, chances are that IPU2 already has firmware loaded. However, IPU1 is open for general purpose programming to offload the ARM tasks.r"r"}r"(jYj"jZj"ubaubj)r"}r"(jYXThere are many facets to this task: building, loading, debugging, MMUs, memory sharing, etc. This article intends to take incremental steps toward understanding all of those pieces.r"jZj!jbj!jdjjf}r"(jh]ji]jj]jk]jn]ujpKjqhjr]r"j{XThere are many facets to this task: building, loading, debugging, MMUs, memory sharing, etc. This article intends to take incremental steps toward understanding all of those pieces.r "r!"}r""(jYj"jZj"ubaubj)r#"}r$"(jYX$Software Dependencies to Get Startedr%"jZj!jbj!jdjjf}r&"(jk]r'"U$software-dependencies-to-get-startedr("ajj]jh]ji]jn]r)"haujpNjqhjr]r*"j{X$Software Dependencies to Get Startedr+"r,"}r-"(jYj%"jZj#"ubaubj)r."}r/"(jYX Prerequisitesr0"jZj!jbj!jdjjf}r1"(jh]ji]jj]jk]jn]ujpKjqhjr]r2"j{X Prerequisitesr3"r4"}r5"(jYj0"jZj."ubaubjC)r6"}r7"(jYUjZj!jbj!jdj`jf}r8"(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]r9"(j/)r:"}r;"(jYX`Processor SDK Linux for AM57xx `__ (Version 3.01 or newer needed)jZj6"jbj!jdj2jf}r<"(jh]ji]jj]jk]jn]ujpNjqhjr]r="j)r>"}r?"(jYX`Processor SDK Linux for AM57xx `__ (Version 3.01 or newer needed)jZj:"jbj!jdjjf}r@"(jh]ji]jj]jk]jn]ujpKjr]rA"(j)rB"}rC"(jYXr`Processor SDK Linux for AM57xx `__jf}rD"(UnameXProcessor SDK Linux for AM57xxjXMhttp://software-dl.ti.com/processor-sdk-linux/esd/AM57X/latest/index_FDS.htmljk]jj]jh]ji]jn]ujZj>"jr]rE"j{XProcessor SDK Linux for AM57xxrF"rG"}rH"(jYUjZjB"ubajdjubj{X (Version 3.01 or newer needed)rI"rJ"}rK"(jYX (Version 3.01 or newer needed)jZj>"ubeubaubj/)rL"}rM"(jYXp`Processor SDK RTOS for AM57xx `__jZj6"jbj!jdj2jf}rN"(jh]ji]jj]jk]jn]ujpNjqhjr]rO"j)rP"}rQ"(jYXp`Processor SDK RTOS for AM57xx `__rR"jZjL"jbj!jdjjf}rS"(jh]ji]jj]jk]jn]ujpKjr]rT"j)rU"}rV"(jYjR"jf}rW"(UnameXProcessor SDK RTOS for AM57xxjXLhttp://software-dl.ti.com/processor-sdk-rtos/esd/AM57X/latest/index_FDS.htmljk]jj]jh]ji]jn]ujZjP"jr]rX"j{XProcessor SDK RTOS for AM57xxrY"rZ"}r["(jYUjZjU"ubajdjubaubaubj/)r\"}r]"(jYX`Code Composer Studio `__ (choose version as specified on Proc SDK download page) jZj6"jbj!jdj2jf}r^"(jh]ji]jj]jk]jn]ujpNjqhjr]r_"j)r`"}ra"(jYX`Code Composer Studio `__ (choose version as specified on Proc SDK download page)jZj\"jbj!jdjjf}rb"(jh]ji]jj]jk]jn]ujpKjr]rc"(j)rd"}re"(jYXO`Code Composer Studio `__jf}rf"(UnameXCode Composer StudiojX4http://processors.wiki.ti.com/index.php/Download_CCSjk]jj]jh]ji]jn]ujZj`"jr]rg"j{XCode Composer Studiorh"ri"}rj"(jYUjZjd"ubajdjubj{X8 (choose version as specified on Proc SDK download page)rk"rl"}rm"(jYX8 (choose version as specified on Proc SDK download page)jZj`"ubeubaubeubj)rn"}ro"(jYX[Please be sure that you have the same version number for both Processor SDK RTOS and Linux.jZj!jbj!jdjjf}rp"(jh]ji]jj]jk]jn]ujpNjqhjr]rq"j)rr"}rs"(jYX[Please be sure that you have the same version number for both Processor SDK RTOS and Linux.rt"jZjn"jbj!jdjjf}ru"(jh]ji]jj]jk]jn]ujpK#jr]rv"j{X[Please be sure that you have the same version number for both Processor SDK RTOS and Linux.rw"rx"}ry"(jYjt"jZjr"ubaubaubj)rz"}r{"(jYXiFor reference within the context of this wiki page, the Linux SDK is installed at the following location:r|"jZj!jbj!jdjjf}r}"(jh]ji]jj]jk]jn]ujpK&jqhjr]r~"j{XiFor reference within the context of this wiki page, the Linux SDK is installed at the following location:r"r"}r"(jYj|"jZjz"ubaubj)r"}r"(jYX/mnt/data/user/ti-processor-sdk-linux-am57xx-evm-xx.xx.xx.xx ├── bin ├── board-support ├── docs ├── example-applications ├── filesystem ├── ipc-build.txt ├── linux-devkit ├── Makefile ├── Rules.make └── setup.shjZj!jbj!jdjjf}r"(jjjk]jj]jh]ji]jn]ujpM jqhjr]r"j{X/mnt/data/user/ti-processor-sdk-linux-am57xx-evm-xx.xx.xx.xx ├── bin ├── board-support ├── docs ├── example-applications ├── filesystem ├── ipc-build.txt ├── linux-devkit ├── Makefile ├── Rules.make └── setup.shr"r"}r"(jYUjZj"ubaubj)r"}r"(jYXThe RTOS SDK is installed at:r"jZj!jbj!jdjjf}r"(jh]ji]jj]jk]jn]ujpK7jqhjr]r"j{XThe RTOS SDK is installed at:r"r"}r"(jYj"jZj"ubaubj)r"}r"(jYX!/mnt/data/user/my_custom_install_sdk_rtos_am57xx_xx.xx ├── bios_6_xx_xx_xx ├── cg_xml ├── ctoolslib_x_x_x_x ├── dsplib_c66x_x_x_x_x ├── edma3_lld_2_xx_xx_xx ├── framework_components_x_xx_xx_xx ├── imglib_c66x_x_x_x_x ├── ipc_3_xx_xx_xx ├── mathlib_c66x_3_x_x_x ├── ndk_2_xx_xx_xx ├── opencl_rtos_am57xx_01_01_xx_xx ├── openmp_dsp_am57xx_2_04_xx_xx ├── pdk_am57xx_x_x_x ├── processor_sdk_rtos_am57xx_x_xx_xx_xx ├── uia_2_xx_xx_xx ├── xdais_7_xx_xx_xxjZj!jbj!jdjjf}r"(jjjk]jj]jh]ji]jn]ujpM jqhjr]r"j{X!/mnt/data/user/my_custom_install_sdk_rtos_am57xx_xx.xx ├── bios_6_xx_xx_xx ├── cg_xml ├── ctoolslib_x_x_x_x ├── dsplib_c66x_x_x_x_x ├── edma3_lld_2_xx_xx_xx ├── framework_components_x_xx_xx_xx ├── imglib_c66x_x_x_x_x ├── ipc_3_xx_xx_xx ├── mathlib_c66x_3_x_x_x ├── ndk_2_xx_xx_xx ├── opencl_rtos_am57xx_01_01_xx_xx ├── openmp_dsp_am57xx_2_04_xx_xx ├── pdk_am57xx_x_x_x ├── processor_sdk_rtos_am57xx_x_xx_xx_xx ├── uia_2_xx_xx_xx ├── xdais_7_xx_xx_xxr"r"}r"(jYUjZj"ubaubj)r"}r"(jYXCCS is installed at:r"jZj!jbj!jdjjf}r"(jh]ji]jj]jk]jn]ujpKMjqhjr]r"j{XCCS is installed at:r"r"}r"(jYj"jZj"ubaubj)r"}r"(jYX[/mnt/data/user/ti/my_custom_ccs_x.x.x_install ├── ccsvX │   ├── ccs_base │   ├── doc │   ├── eclipse │   ├── install_info │   ├── install_logs │   ├── install_scripts │   ├── tools │   ├── uninstall_ccs │   ├── uninstall_ccs.dat │   ├── uninstallers │   └── utils ├── Code Composer Studio x.x.x.desktop └── xdctools_x_xx_xx_xx_core ├── bin ├── config.jar ├── docs ├── eclipse ├── etc ├── gmake ├── include ├── package ├── packages ├── package.xdc ├── tconfini.tcf ├── xdc ├── xdctools_3_xx_xx_xx_manifest.html ├── xdctools_3_xx_xx_xx_release_notes.html ├── xs └── xs.x86UjZj!jbj!jdjjf}r"(jjjk]jj]jh]ji]jn]ujpM jqhjr]r"j{X[/mnt/data/user/ti/my_custom_ccs_x.x.x_install ├── ccsvX │   ├── ccs_base │   ├── doc │   ├── eclipse │   ├── install_info │   ├── install_logs │   ├── install_scripts │   ├── tools │   ├── uninstall_ccs │   ├── uninstall_ccs.dat │   ├── uninstallers │   └── utils ├── Code Composer Studio x.x.x.desktop └── xdctools_x_xx_xx_xx_core ├── bin ├── config.jar ├── docs ├── eclipse ├── etc ├── gmake ├── include ├── package ├── packages ├── package.xdc ├── tconfini.tcf ├── xdc ├── xdctools_3_xx_xx_xx_manifest.html ├── xdctools_3_xx_xx_xx_release_notes.html ├── xs └── xs.x86Ur"r"}r"(jYUjZj"ubaubjZ)r"}r"(jYUjZj!jbj!jdj]jf}r"(jh]ji]jj]jk]jn]ujpKqjqhjr]r"j`)r"}r"(jYUjcKjZj"jbj!jdjpjf}r"(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r"}r"(jYX/Typical Boot Flow on AM572x for ARM Linux usersr"jZj!jbj!jdjjf}r"(jk]r"U/typical-boot-flow-on-am572x-for-arm-linux-usersr"ajj]jh]ji]jn]r"haujpNjqhjr]r"j{X/Typical Boot Flow on AM572x for ARM Linux usersr"r"}r"(jYj"jZj"ubaubj)r"}r"(jYX:AM57xx SOC's have multiple processor cores - Cortex A15, C66x DSP's and ARM M4 cores. The A15 typically runs a HLOS like Linux/QNX/Android and the remotecores(DSP's and M4's) run a RTOS. In the normal operation, boot loader(U-Boot/SPL) boots and loads the A15 with the HLOS. The A15 boots the DSP and the M4 cores.r"jZj!jbj!jdjjf}r"(jh]ji]jj]jk]jn]ujpKvjqhjr]r"j{X:AM57xx SOC's have multiple processor cores - Cortex A15, C66x DSP's and ARM M4 cores. The A15 typically runs a HLOS like Linux/QNX/Android and the remotecores(DSP's and M4's) run a RTOS. In the normal operation, boot loader(U-Boot/SPL) boots and loads the A15 with the HLOS. The A15 boots the DSP and the M4 cores.r"r"}r"(jYj"jZj"ubaubjB)r"}r"(jYX%.. Image:: ../images/Normal-boot.png jZj!jbj!jdjEjf}r"(UuriXrtos/../images/Normal-boot.pngr"jk]jj]jh]ji]jH}r"U*j"sjn]ujpK}jqhjr]ubj)r"}r"(jYXIn this sequence, the interval between the Power on Reset and the remotecores (i.e. the DSP's and the M4's) executing is dependent on the HLOS initialization time.r"jZj!jbj!jdjjf}r"(jh]ji]jj]jk]jn]ujpK~jqhjr]r"j{XIn this sequence, the interval between the Power on Reset and the remotecores (i.e. the DSP's and the M4's) executing is dependent on the HLOS initialization time.r"r"}r"(jYj"jZj"ubaubjZ)r"}r"(jYUjZj!jbj!jdj]jf}r"(jh]ji]jj]jk]jn]ujpKjqhjr]r"j`)r"}r"(jYUjcKjZj"jbj!jdjpjf}r"(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubj[)r"}r"(jYUjZj!jbj!jdjejf}r"(jh]ji]jj]jk]r"U'getting-started-with-ipc-linux-examplesr"ajn]r"jaujpKjqhjr]r"(jt)r"}r"(jYX'Getting Started with IPC Linux Examplesr"jZj"jbj!jdjxjf}r"(jh]ji]jj]jk]jn]ujpKjqhjr]r"j{X'Getting Started with IPC Linux Examplesr"r"}r"(jYj"jZj"ubaubj)r"}r"(jYXThe figure below illustrates how remoteproc/rpmsg driver from ARM Linux kernel communicates with IPC driver on slave processor (e.g. DSP, IPU, etc) running RTOS.r"jZj"jbj!jdjjf}r"(jh]ji]jj]jk]jn]ujpKjqhjr]r"j{XThe figure below illustrates how remoteproc/rpmsg driver from ARM Linux kernel communicates with IPC driver on slave processor (e.g. DSP, IPU, etc) running RTOS.r"r"}r"(jYj"jZj"ubaubjB)r"}r"(jYX2.. Image:: ../images/LinuxIPC_with_RTOS_Slave.png jZj"jbj!jdjEjf}r"(UuriX+rtos/../images/LinuxIPC_with_RTOS_Slave.pngr"jk]jj]jh]ji]jH}r"U*j"sjn]ujpKjqhjr]ubj)r"}r"(jYXIn order to setup IPC on slave cores, we provide some pre-built examples in IPC package that can be run from ARM Linux. The subsequent sections describe how to build and run this examples and use that as a starting point for this effort.r"jZj"jbj!jdjjf}r"(jh]ji]jj]jk]jn]ujpKjqhjr]r"j{XIn order to setup IPC on slave cores, we provide some pre-built examples in IPC package that can be run from ARM Linux. The subsequent sections describe how to build and run this examples and use that as a starting point for this effort.r"r"}r"(jYj"jZj"ubaubj)r"}r"(jYX!Building the Bundled IPC Examplesr"jZj"jbj!jdjjf}r"(jk]r"U!building-the-bundled-ipc-examplesr"ajj]jh]ji]jn]r"j5aujpNjqhjr]r#j{X!Building the Bundled IPC Examplesr#r#}r#(jYj"jZj"ubaubj)r#}r#(jYX The instructions to build IPC examples found under ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf have been provided in the **`Processor_SDK IPC Quick Start Guide `__.**jZj"jbj!jdjjf}r#(jh]ji]jj]jk]jn]ujpKjqhjr]r#(j{XvThe instructions to build IPC examples found under ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf have been provided in the r#r #}r #(jYXvThe instructions to build IPC examples found under ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf have been provided in the jZj#ubj)r #}r #(jYX**`Processor_SDK IPC Quick Start Guide `__.**jf}r #(jh]ji]jj]jk]jn]ujZj#jr]r#j{X`Processor_SDK IPC Quick Start Guide `__.r#r#}r#(jYUjZj #ubajdjubeubj)r#}r#(jYXLet's focus on one example in particular, ex02_messageq, which is located at **/ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf/ex02_messageq**. Here are the key files that you should see after a successful build:jZj"jbj!jdjjf}r#(jh]ji]jj]jk]jn]ujpKjqhjr]r#(j{XMLet's focus on one example in particular, ex02_messageq, which is located at r#r#}r#(jYXMLet's focus on one example in particular, ex02_messageq, which is located at jZj#ubj)r#}r#(jYXQ**/ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf/ex02_messageq**jf}r#(jh]ji]jj]jk]jn]ujZj#jr]r#j{XM/ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf/ex02_messageqr#r#}r#(jYUjZj#ubajdjubj{XF. Here are the key files that you should see after a successful build:r #r!#}r"#(jYXF. Here are the key files that you should see after a successful build:jZj#ubeubj)r##}r$#(jYX├── dsp1 │   └── bin │      ├── debug │      │   └── server_dsp1.xe66 │      └── release │      └── server_dsp1.xe66 ├── dsp2 │   └── bin │      ├── debug │      │   └── server_dsp2.xe66 │      └── release │      └── server_dsp2.xe66 ├── host │      ├── debug │      │   └── app_host │      └── release │      └── app_host ├── ipu1 │   └── bin │      ├── debug │      │   └── server_ipu1.xem4 │      └── release │      └── server_ipu1.xem4 └── ipu2    └── bin       ├── debug       │   └── server_ipu2.xem4       └── release       └── server_ipu2.xem4jZj"jbj!jdjjf}r%#(jjjk]jj]jh]ji]jn]ujpM. jqhjr]r&#j{X├── dsp1 │   └── bin │      ├── debug │      │   └── server_dsp1.xe66 │      └── release │      └── server_dsp1.xe66 ├── dsp2 │   └── bin │      ├── debug │      │   └── server_dsp2.xe66 │      └── release │      └── server_dsp2.xe66 ├── host │      ├── debug │      │   └── app_host │      └── release │      └── app_host ├── ipu1 │   └── bin │      ├── debug │      │   └── server_ipu1.xem4 │      └── release │      └── server_ipu1.xem4 └── ipu2    └── bin       ├── debug       │   └── server_ipu2.xem4       └── release       └── server_ipu2.xem4r'#r(#}r)#(jYUjZj##ubaubjZ)r*#}r+#(jYUjZj"jbj!jdj]jf}r,#(jh]ji]jj]jk]jn]ujpKjqhjr]r-#j`)r.#}r/#(jYUjcKjZj*#jbj!jdjpjf}r0#(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjZ)r1#}r2#(jYUjZj"jbj!jdj]jf}r3#(jh]ji]jj]jk]jn]ujpKjqhjr]r4#j`)r5#}r6#(jYUjcKjZj1#jbj!jdjpjf}r7#(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r8#}r9#(jYX Running the Bundled IPC Examplesr:#jZj"jbj!jdjjf}r;#(jk]r<#U running-the-bundled-ipc-examplesr=#ajj]jh]ji]jn]r>#jCaujpNjqhjr]r?#j{X Running the Bundled IPC Examplesr@#rA#}rB#(jYj:#jZj8#ubaubj)rC#}rD#(jYX;On the target, let's create a directory called ipc-starter:rE#jZj"jbj!jdjjf}rF#(jh]ji]jj]jk]jn]ujpKjqhjr]rG#j{X;On the target, let's create a directory called ipc-starter:rH#rI#}rJ#(jYjE#jZjC#ubaubj)rK#}rL#(jYX`root@am57xx-evm:~# mkdir -p /home/root/ipc-starter root@am57xx-evm:~# cd /home/root/ipc-starter/jZj"jbj!jdjjf}rM#(jjjk]jj]jh]ji]jn]ujpMW jqhjr]rN#j{X`root@am57xx-evm:~# mkdir -p /home/root/ipc-starter root@am57xx-evm:~# cd /home/root/ipc-starter/rO#rP#}rQ#(jYUjZjK#ubaubj)rR#}rS#(jYXYou will need to copy the ex02_messageq directory of your host PC to that directory on the target (through SD card, NFS export, SCP, etc.). You can copy the entire directory, though we're primarily interested in these files:rT#jZj"jbj!jdjjf}rU#(jh]ji]jj]jk]jn]ujpKjqhjr]rV#j{XYou will need to copy the ex02_messageq directory of your host PC to that directory on the target (through SD card, NFS export, SCP, etc.). You can copy the entire directory, though we're primarily interested in these files:rW#rX#}rY#(jYjT#jZjR#ubaubjC)rZ#}r[#(jYUjZj"jbj!jdj`jf}r\#(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]r]#(j/)r^#}r_#(jYXdsp1/bin/debug/server_dsp1.xe66r`#jZjZ#jbj!jdj2jf}ra#(jh]ji]jj]jk]jn]ujpNjqhjr]rb#j)rc#}rd#(jYj`#jZj^#jbj!jdjjf}re#(jh]ji]jj]jk]jn]ujpKjr]rf#j{Xdsp1/bin/debug/server_dsp1.xe66rg#rh#}ri#(jYj`#jZjc#ubaubaubj/)rj#}rk#(jYXdsp2/bin/debug/server_dsp2.xe66rl#jZjZ#jbj!jdj2jf}rm#(jh]ji]jj]jk]jn]ujpNjqhjr]rn#j)ro#}rp#(jYjl#jZjj#jbj!jdjjf}rq#(jh]ji]jj]jk]jn]ujpKjr]rr#j{Xdsp2/bin/debug/server_dsp2.xe66rs#rt#}ru#(jYjl#jZjo#ubaubaubj/)rv#}rw#(jYXhost/bin/debug/app_hostrx#jZjZ#jbj!jdj2jf}ry#(jh]ji]jj]jk]jn]ujpNjqhjr]rz#j)r{#}r|#(jYjx#jZjv#jbj!jdjjf}r}#(jh]ji]jj]jk]jn]ujpKjr]r~#j{Xhost/bin/debug/app_hostr#r#}r#(jYjx#jZj{#ubaubaubj/)r#}r#(jYXipu1/bin/debug/server_ipu1.xem4r#jZjZ#jbj!jdj2jf}r#(jh]ji]jj]jk]jn]ujpNjqhjr]r#j)r#}r#(jYj#jZj#jbj!jdjjf}r#(jh]ji]jj]jk]jn]ujpKjr]r#j{Xipu1/bin/debug/server_ipu1.xem4r#r#}r#(jYj#jZj#ubaubaubj/)r#}r#(jYX ipu2/bin/debug/server_ipu2.xem4 jZjZ#jbj!jdj2jf}r#(jh]ji]jj]jk]jn]ujpNjqhjr]r#j)r#}r#(jYXipu2/bin/debug/server_ipu2.xem4r#jZj#jbj!jdjjf}r#(jh]ji]jj]jk]jn]ujpKjr]r#j{Xipu2/bin/debug/server_ipu2.xem4r#r#}r#(jYj#jZj#ubaubaubeubj)r#}r#(jYXxThe remoteproc driver is hard-coded to look for specific files when loading the DSP/M4. Here are the files it looks for:r#jZj"jbj!jdjjf}r#(jh]ji]jj]jk]jn]ujpKjqhjr]r#j{XxThe remoteproc driver is hard-coded to look for specific files when loading the DSP/M4. Here are the files it looks for:r#r#}r#(jYj#jZj#ubaubjC)r#}r#(jYUjZj"jbj!jdj`jf}r#(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]r#(j/)r#}r#(jYX/lib/firmware/dra7-dsp1-fw.xe66r#jZj#jbj!jdj2jf}r#(jh]ji]jj]jk]jn]ujpNjqhjr]r#j)r#}r#(jYj#jZj#jbj!jdjjf}r#(jh]ji]jj]jk]jn]ujpKjr]r#j{X/lib/firmware/dra7-dsp1-fw.xe66r#r#}r#(jYj#jZj#ubaubaubj/)r#}r#(jYX/lib/firmware/dra7-dsp2-fw.xe66r#jZj#jbj!jdj2jf}r#(jh]ji]jj]jk]jn]ujpNjqhjr]r#j)r#}r#(jYj#jZj#jbj!jdjjf}r#(jh]ji]jj]jk]jn]ujpKjr]r#j{X/lib/firmware/dra7-dsp2-fw.xe66r#r#}r#(jYj#jZj#ubaubaubj/)r#}r#(jYX/lib/firmware/dra7-ipu1-fw.xem4r#jZj#jbj!jdj2jf}r#(jh]ji]jj]jk]jn]ujpNjqhjr]r#j)r#}r#(jYj#jZj#jbj!jdjjf}r#(jh]ji]jj]jk]jn]ujpKjr]r#j{X/lib/firmware/dra7-ipu1-fw.xem4r#r#}r#(jYj#jZj#ubaubaubj/)r#}r#(jYX /lib/firmware/dra7-ipu2-fw.xem4 jZj#jbj!jdj2jf}r#(jh]ji]jj]jk]jn]ujpNjqhjr]r#j)r#}r#(jYX/lib/firmware/dra7-ipu2-fw.xem4r#jZj#jbj!jdjjf}r#(jh]ji]jj]jk]jn]ujpKjr]r#j{X/lib/firmware/dra7-ipu2-fw.xem4r#r#}r#(jYj#jZj#ubaubaubeubj)r#}r#(jYX{These are generally a soft link to the intended executable. So for example, let's update the DSP1 executable on the target:r#jZj"jbj!jdjjf}r#(jh]ji]jj]jk]jn]ujpKjqhjr]r#j{X{These are generally a soft link to the intended executable. So for example, let's update the DSP1 executable on the target:r#r#}r#(jYj#jZj#ubaubj)r#}r#(jYXroot@am57xx-evm:~# cd /lib/firmware/ root@am57xx-evm:/lib/firmware# rm dra7-dsp1-fw.xe66 root@am57xx-evm:/lib/firmware# ln -s /home/root/ipc-starter/ex02_messageq/dsp1/bin/debug/server_dsp1.xe66 dra7-dsp1-fw.xe66jZj"jbj!jdjjf}r#(jjjk]jj]jh]ji]jn]ujpMr jqhjr]r#j{Xroot@am57xx-evm:~# cd /lib/firmware/ root@am57xx-evm:/lib/firmware# rm dra7-dsp1-fw.xe66 root@am57xx-evm:/lib/firmware# ln -s /home/root/ipc-starter/ex02_messageq/dsp1/bin/debug/server_dsp1.xe66 dra7-dsp1-fw.xe66r#r#}r#(jYUjZj#ubaubj)r#}r#(jYXHTo reload DSP1 with this new executable, we perform the following steps:r#jZj"jbj!jdjjf}r#(jh]ji]jj]jk]jn]ujpKjqhjr]r#j{XHTo reload DSP1 with this new executable, we perform the following steps:r#r#}r#(jYj#jZj#ubaubj)r#}r#(jYXroot@am57xx-evm:/lib/firmware# cd /sys/bus/platform/drivers/omap-rproc/ root@am57xx-evm:/sys/bus/platform/drivers/omap-rproc# echo 40800000.dsp > unbind [27639.985631] omap_hwmod: mmu0_dsp1: _wait_target_disable failed [27639.991534] omap-iommu 40d01000.mmu: 40d01000.mmu: version 3.0 [27639.997610] omap-iommu 40d02000.mmu: 40d02000.mmu: version 3.0 [27640.017557] omap_hwmod: mmu1_dsp1: _wait_target_disable failed [27640.030571] omap_hwmod: mmu0_dsp1: _wait_target_disable failed [27640.036605] remoteproc2: stopped remote processor 40800000.dsp [27640.042805] remoteproc2: releasing 40800000.dsp root@am57xx-evm:/sys/bus/platform/drivers/omap-rproc# echo 40800000.dsp > bind [27645.958613] omap-rproc 40800000.dsp: assigned reserved memory node dsp1_cma@99000000 [27645.966452] remoteproc2: 40800000.dsp is available [27645.971410] remoteproc2: Note: remoteproc is still under development and considered experimental. [27645.980536] remoteproc2: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed. root@am57xx-evm:/sys/bus/platform/drivers/omap-rproc# [27646.008171] remoteproc2: powering up 40800000.dsp [27646.013038] remoteproc2: Booting fw image dra7-dsp1-fw.xe66, size 4706800 [27646.028920] omap_hwmod: mmu0_dsp1: _wait_target_disable failed [27646.034819] omap-iommu 40d01000.mmu: 40d01000.mmu: version 3.0 [27646.040772] omap-iommu 40d02000.mmu: 40d02000.mmu: version 3.0 [27646.058323] remoteproc2: remote processor 40800000.dsp is now up [27646.064772] virtio_rpmsg_bus virtio2: rpmsg host is online [27646.072271] remoteproc2: registered virtio2 (type 7) [27646.078026] virtio_rpmsg_bus virtio2: creating channel rpmsg-proto addr 0x3djZj"jbj!jdjjf}r#(jjjk]jj]jh]ji]jn]ujpMz jqhjr]r#j{Xroot@am57xx-evm:/lib/firmware# cd /sys/bus/platform/drivers/omap-rproc/ root@am57xx-evm:/sys/bus/platform/drivers/omap-rproc# echo 40800000.dsp > unbind [27639.985631] omap_hwmod: mmu0_dsp1: _wait_target_disable failed [27639.991534] omap-iommu 40d01000.mmu: 40d01000.mmu: version 3.0 [27639.997610] omap-iommu 40d02000.mmu: 40d02000.mmu: version 3.0 [27640.017557] omap_hwmod: mmu1_dsp1: _wait_target_disable failed [27640.030571] omap_hwmod: mmu0_dsp1: _wait_target_disable failed [27640.036605] remoteproc2: stopped remote processor 40800000.dsp [27640.042805] remoteproc2: releasing 40800000.dsp root@am57xx-evm:/sys/bus/platform/drivers/omap-rproc# echo 40800000.dsp > bind [27645.958613] omap-rproc 40800000.dsp: assigned reserved memory node dsp1_cma@99000000 [27645.966452] remoteproc2: 40800000.dsp is available [27645.971410] remoteproc2: Note: remoteproc is still under development and considered experimental. [27645.980536] remoteproc2: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed. root@am57xx-evm:/sys/bus/platform/drivers/omap-rproc# [27646.008171] remoteproc2: powering up 40800000.dsp [27646.013038] remoteproc2: Booting fw image dra7-dsp1-fw.xe66, size 4706800 [27646.028920] omap_hwmod: mmu0_dsp1: _wait_target_disable failed [27646.034819] omap-iommu 40d01000.mmu: 40d01000.mmu: version 3.0 [27646.040772] omap-iommu 40d02000.mmu: 40d02000.mmu: version 3.0 [27646.058323] remoteproc2: remote processor 40800000.dsp is now up [27646.064772] virtio_rpmsg_bus virtio2: rpmsg host is online [27646.072271] remoteproc2: registered virtio2 (type 7) [27646.078026] virtio_rpmsg_bus virtio2: creating channel rpmsg-proto addr 0x3dr#r#}r#(jYUjZj#ubaubj)r#}r#(jYXMore info related to loading firmware to the various cores can be found `here `__.jZj"jbj!jdjjf}r#(jh]ji]jj]jk]jn]ujpMjqhjr]r#(j{XHMore info related to loading firmware to the various cores can be found r#r#}r#(jYXHMore info related to loading firmware to the various cores can be found jZj#ubj)r#}r#(jYXS`here `__jf}r#(UnameXherejXH/index.php/Processor_Training:_Multimedia#Firmware_Loading_and_Unloadingjk]jj]jh]ji]jn]ujZj#jr]r#j{Xherer#r$}r$(jYUjZj#ubajdjubj{X.r$}r$(jYX.jZj#ubeubj)r$}r$(jYX(Finally, we can run the example on DSP1:r$jZj"jbj!jdjjf}r$(jh]ji]jj]jk]jn]ujpMjqhjr]r$j{X(Finally, we can run the example on DSP1:r $r $}r $(jYj$jZj$ubaubj)r $}r $(jYXroot@am57xx-evm:/sys/bus/platform/drivers/omap-rproc# cd /home/root/ipc-starter/ex02_messageq/host/bin/debug root@am57xx-evm:~/ipc-starter/ex02_messageq/host/bin/debug# ./app_host DSP1 --> main: [33590.700700] omap_hwmod: mmu0_dsp2: _wait_target_disable failed [33590.706609] omap-iommu 41501000.mmu: 41501000.mmu: version 3.0 [33590.718798] omap-iommu 41502000.mmu: 41502000.mmu: version 3.0 --> Main_main: --> App_create: App_create: Host is ready <-- App_create: --> App_exec: App_exec: sending message 1 App_exec: sending message 2 App_exec: sending message 3 App_exec: message received, sending message 4 App_exec: message received, sending message 5 App_exec: message received, sending message 6 App_exec: message received, sending message 7 App_exec: message received, sending message 8 App_exec: message received, sending message 9 App_exec: message received, sending message 10 App_exec: message received, sending message 11 App_exec: message received, sending message 12 App_exec: message received, sending message 13 App_exec: message received, sending message 14 App_exec: message received, sending message 15 App_exec: message received App_exec: message received App_exec: message received <-- App_exec: 0 --> App_delete: <-- App_delete: <-- Main_main: <-- main:jZj"jbj!jdjjf}r$(jjjk]jj]jh]ji]jn]ujpM jqhjr]r$j{Xroot@am57xx-evm:/sys/bus/platform/drivers/omap-rproc# cd /home/root/ipc-starter/ex02_messageq/host/bin/debug root@am57xx-evm:~/ipc-starter/ex02_messageq/host/bin/debug# ./app_host DSP1 --> main: [33590.700700] omap_hwmod: mmu0_dsp2: _wait_target_disable failed [33590.706609] omap-iommu 41501000.mmu: 41501000.mmu: version 3.0 [33590.718798] omap-iommu 41502000.mmu: 41502000.mmu: version 3.0 --> Main_main: --> App_create: App_create: Host is ready <-- App_create: --> App_exec: App_exec: sending message 1 App_exec: sending message 2 App_exec: sending message 3 App_exec: message received, sending message 4 App_exec: message received, sending message 5 App_exec: message received, sending message 6 App_exec: message received, sending message 7 App_exec: message received, sending message 8 App_exec: message received, sending message 9 App_exec: message received, sending message 10 App_exec: message received, sending message 11 App_exec: message received, sending message 12 App_exec: message received, sending message 13 App_exec: message received, sending message 14 App_exec: message received, sending message 15 App_exec: message received App_exec: message received App_exec: message received <-- App_exec: 0 --> App_delete: <-- App_delete: <-- Main_main: <-- main:r$r$}r$(jYUjZj $ubaubjZ)r$}r$(jYUjZj"jbj!jdj]jf}r$(jh]ji]jj]jk]jn]ujpM/jqhjr]r$j`)r$}r$(jYUjcKjZj$jbj!jdjpjf}r$(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r$}r$(jYXThe similar procedure can be used for DSP2/IPU1/IPU2 also to update the soft link of the firmware, reload the firmware at run-time, and run the host binary from A15.r$jZj"jbj!jdjjf}r$(jh]ji]jj]jk]jn]ujpM0jqhjr]r$j{XThe similar procedure can be used for DSP2/IPU1/IPU2 also to update the soft link of the firmware, reload the firmware at run-time, and run the host binary from A15.r$r $}r!$(jYj$jZj$ubaubeubj[)r"$}r#$(jYUjZj!jbj!jdjejf}r$$(jh]ji]jj]jk]r%$Uunderstanding-the-memory-mapr&$ajn]r'$haujpM5jqhjr]r($(jt)r)$}r*$(jYXUnderstanding the Memory Mapr+$jZj"$jbj!jdjxjf}r,$(jh]ji]jj]jk]jn]ujpM5jqhjr]r-$j{XUnderstanding the Memory Mapr.$r/$}r0$(jYj+$jZj)$ubaubj)r1$}r2$(jYXOverall Linux Memory Mapr3$jZj"$jbj!jdjjf}r4$(jk]r5$Uoverall-linux-memory-mapr6$ajj]jh]ji]jn]r7$haujpNjqhjr]r8$j{XOverall Linux Memory Mapr9$r:$}r;$(jYj3$jZj1$ubaubj)r<$}r=$(jYX$root@am57xx-evm:~# cat /proc/iomem [snip...] 58060000-58078fff : core 58820000-5882ffff : l2ram 58882000-588820ff : /ocp/mmu@58882000 80000000-9fffffff : System RAM 80008000-808d204b : Kernel code 80926000-809c96bf : Kernel data a0000000-abffffff : CMEM ac000000-ffcfffff : System RAMjZj"$jbj!jdjjf}r>$(jjjk]jj]jh]ji]jn]ujpM jqhjr]r?$j{X$root@am57xx-evm:~# cat /proc/iomem [snip...] 58060000-58078fff : core 58820000-5882ffff : l2ram 58882000-588820ff : /ocp/mmu@58882000 80000000-9fffffff : System RAM 80008000-808d204b : Kernel code 80926000-809c96bf : Kernel data a0000000-abffffff : CMEM ac000000-ffcfffff : System RAMr@$rA$}rB$(jYUjZj<$ubaubjZ)rC$}rD$(jYUjZj"$jbj!jdj]jf}rE$(jh]ji]jj]jk]jn]ujpMGjqhjr]rF$j`)rG$}rH$(jYUjcKjZjC$jbj!jdjpjf}rI$(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)rJ$}rK$(jYX CMA CarveoutsrL$jZj"$jbj!jdjjf}rM$(jk]rN$U cma-carveoutsrO$ajj]jh]ji]jn]rP$hBaujpNjqhjr]rQ$j{X CMA CarveoutsrR$rS$}rT$(jYjL$jZjJ$ubaubj)rU$}rV$(jYXdroot@am57xx-evm:~# dmesg | grep -i cma [ 0.000000] Reserved memory: created CMA memory pool at 0x0000000095800000, size 56 MiB [ 0.000000] Reserved memory: initialized node ipu2_cma@95800000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created CMA memory pool at 0x0000000099000000, size 64 MiB [ 0.000000] Reserved memory: initialized node dsp1_cma@99000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created CMA memory pool at 0x000000009d000000, size 32 MiB [ 0.000000] Reserved memory: initialized node ipu1_cma@9d000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created CMA memory pool at 0x000000009f000000, size 8 MiB [ 0.000000] Reserved memory: initialized node dsp2_cma@9f000000, compatible id shared-dma-pool [ 0.000000] cma: Reserved 24 MiB at 0x00000000fe400000 [ 0.000000] Memory: 1713468K/1897472K available (6535K kernel code, 358K rwdata, 2464K rodata, 332K init, 289K bss, 28356K reserved, 155648K cma-reserved, 1283072K highmem) [ 5.492945] omap-rproc 58820000.ipu: assigned reserved memory node ipu1_cma@9d000000 [ 5.603289] omap-rproc 55020000.ipu: assigned reserved memory node ipu2_cma@95800000 [ 5.713411] omap-rproc 40800000.dsp: assigned reserved memory node dsp1_cma@9b000000 [ 5.771990] omap-rproc 41000000.dsp: assigned reserved memory node dsp2_cma@9f000000jZj"$jbj!jdjjf}rW$(jjjk]jj]jh]ji]jn]ujpM jqhjr]rX$j{Xdroot@am57xx-evm:~# dmesg | grep -i cma [ 0.000000] Reserved memory: created CMA memory pool at 0x0000000095800000, size 56 MiB [ 0.000000] Reserved memory: initialized node ipu2_cma@95800000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created CMA memory pool at 0x0000000099000000, size 64 MiB [ 0.000000] Reserved memory: initialized node dsp1_cma@99000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created CMA memory pool at 0x000000009d000000, size 32 MiB [ 0.000000] Reserved memory: initialized node ipu1_cma@9d000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created CMA memory pool at 0x000000009f000000, size 8 MiB [ 0.000000] Reserved memory: initialized node dsp2_cma@9f000000, compatible id shared-dma-pool [ 0.000000] cma: Reserved 24 MiB at 0x00000000fe400000 [ 0.000000] Memory: 1713468K/1897472K available (6535K kernel code, 358K rwdata, 2464K rodata, 332K init, 289K bss, 28356K reserved, 155648K cma-reserved, 1283072K highmem) [ 5.492945] omap-rproc 58820000.ipu: assigned reserved memory node ipu1_cma@9d000000 [ 5.603289] omap-rproc 55020000.ipu: assigned reserved memory node ipu2_cma@95800000 [ 5.713411] omap-rproc 40800000.dsp: assigned reserved memory node dsp1_cma@9b000000 [ 5.771990] omap-rproc 41000000.dsp: assigned reserved memory node dsp2_cma@9f000000rY$rZ$}r[$(jYUjZjU$ubaubj)r\$}r]$(jYXPFrom the output above, we can derive the location and size of each CMA carveout:r^$jZj"$jbj!jdjjf}r_$(jh]ji]jj]jk]jn]ujpM^jqhjr]r`$j{XPFrom the output above, we can derive the location and size of each CMA carveout:ra$rb$}rc$(jYj^$jZj\$ubaubcdocutils.nodes table rd$)re$}rf$(jYUjZj"$jbj!jdUtablerg$jf}rh$(jh]ji]jj]jk]jn]ujpNjqhjr]ri$cdocutils.nodes tgroup rj$)rk$}rl$(jYUjf}rm$(jk]jj]jh]ji]jn]UcolsKujZje$jr]rn$(cdocutils.nodes colspec ro$)rp$}rq$(jYUjf}rr$(jk]jj]jh]ji]jn]UcolwidthKujZjk$jr]jdUcolspecrs$ubjo$)rt$}ru$(jYUjf}rv$(jk]jj]jh]ji]jn]UcolwidthKujZjk$jr]jdjs$ubjo$)rw$}rx$(jYUjf}ry$(jk]jj]jh]ji]jn]UcolwidthKujZjk$jr]jdjs$ubcdocutils.nodes thead rz$)r{$}r|$(jYUjf}r}$(jh]ji]jj]jk]jn]ujZjk$jr]r~$cdocutils.nodes row r$)r$}r$(jYUjf}r$(jh]ji]jj]jk]jn]ujZj{$jr]r$(cdocutils.nodes entry r$)r$}r$(jYUjf}r$(jh]ji]jj]jk]jn]ujZj$jr]r$j)r$}r$(jYXMemory Sectionr$jZj$jbj!jdjjf}r$(jh]ji]jj]jk]jn]ujpMbjr]r$j{XMemory Sectionr$r$}r$(jYj$jZj$ubaubajdUentryr$ubj$)r$}r$(jYUjf}r$(jh]ji]jj]jk]jn]ujZj$jr]r$j)r$}r$(jYXPhysical Addressr$jZj$jbj!jdjjf}r$(jh]ji]jj]jk]jn]ujpMbjr]r$j{XPhysical Addressr$r$}r$(jYj$jZj$ubaubajdj$ubj$)r$}r$(jYUjf}r$(jh]ji]jj]jk]jn]ujZj$jr]r$j)r$}r$(jYXSizer$jZj$jbj!jdjjf}r$(jh]ji]jj]jk]jn]ujpMbjr]r$j{XSizer$r$}r$(jYj$jZj$ubaubajdj$ubejdUrowr$ubajdUtheadr$ubcdocutils.nodes tbody r$)r$}r$(jYUjf}r$(jh]ji]jj]jk]jn]ujZjk$jr]r$(j$)r$}r$(jYUjf}r$(jh]ji]jj]jk]jn]ujZj$jr]r$(j$)r$}r$(jYUjf}r$(jh]ji]jj]jk]jn]ujZj$jr]r$j)r$}r$(jYXIPU2 CMAr$jZj$jbj!jdjjf}r$(jh]ji]jj]jk]jn]ujpMdjr]r$j{XIPU2 CMAr$r$}r$(jYj$jZj$ubaubajdj$ubj$)r$}r$(jYUjf}r$(jh]ji]jj]jk]jn]ujZj$jr]r$j)r$}r$(jYX 0x95800000r$jZj$jbj!jdjjf}r$(jh]ji]jj]jk]jn]ujpMdjr]r$j{X 0x95800000r$r$}r$(jYj$jZj$ubaubajdj$ubj$)r$}r$(jYUjf}r$(jh]ji]jj]jk]jn]ujZj$jr]r$j)r$}r$(jYX56 MBr$jZj$jbj!jdjjf}r$(jh]ji]jj]jk]jn]ujpMdjr]r$j{X56 MBr$r$}r$(jYj$jZj$ubaubajdj$ubejdj$ubj$)r$}r$(jYUjf}r$(jh]ji]jj]jk]jn]ujZj$jr]r$(j$)r$}r$(jYUjf}r$(jh]ji]jj]jk]jn]ujZj$jr]r$j)r$}r$(jYXDSP1 CMAr$jZj$jbj!jdjjf}r$(jh]ji]jj]jk]jn]ujpMfjr]r$j{XDSP1 CMAr$r$}r$(jYj$jZj$ubaubajdj$ubj$)r$}r$(jYUjf}r$(jh]ji]jj]jk]jn]ujZj$jr]r$j)r$}r$(jYX 0x99000000r$jZj$jbj!jdjjf}r$(jh]ji]jj]jk]jn]ujpMfjr]r$j{X 0x99000000r$r$}r$(jYj$jZj$ubaubajdj$ubj$)r$}r$(jYUjf}r$(jh]ji]jj]jk]jn]ujZj$jr]r$j)r$}r$(jYX64 MBr$jZj$jbj!jdjjf}r$(jh]ji]jj]jk]jn]ujpMfjr]r$j{X64 MBr$r$}r%(jYj$jZj$ubaubajdj$ubejdj$ubj$)r%}r%(jYUjf}r%(jh]ji]jj]jk]jn]ujZj$jr]r%(j$)r%}r%(jYUjf}r%(jh]ji]jj]jk]jn]ujZj%jr]r%j)r %}r %(jYXIPU1 CMAr %jZj%jbj!jdjjf}r %(jh]ji]jj]jk]jn]ujpMhjr]r %j{XIPU1 CMAr%r%}r%(jYj %jZj %ubaubajdj$ubj$)r%}r%(jYUjf}r%(jh]ji]jj]jk]jn]ujZj%jr]r%j)r%}r%(jYX 0x9d000000r%jZj%jbj!jdjjf}r%(jh]ji]jj]jk]jn]ujpMhjr]r%j{X 0x9d000000r%r%}r%(jYj%jZj%ubaubajdj$ubj$)r%}r%(jYUjf}r%(jh]ji]jj]jk]jn]ujZj%jr]r %j)r!%}r"%(jYX32 MBr#%jZj%jbj!jdjjf}r$%(jh]ji]jj]jk]jn]ujpMhjr]r%%j{X32 MBr&%r'%}r(%(jYj#%jZj!%ubaubajdj$ubejdj$ubj$)r)%}r*%(jYUjf}r+%(jh]ji]jj]jk]jn]ujZj$jr]r,%(j$)r-%}r.%(jYUjf}r/%(jh]ji]jj]jk]jn]ujZj)%jr]r0%j)r1%}r2%(jYXDSP2 CMAr3%jZj-%jbj!jdjjf}r4%(jh]ji]jj]jk]jn]ujpMjjr]r5%j{XDSP2 CMAr6%r7%}r8%(jYj3%jZj1%ubaubajdj$ubj$)r9%}r:%(jYUjf}r;%(jh]ji]jj]jk]jn]ujZj)%jr]r<%j)r=%}r>%(jYX 0x9f000000r?%jZj9%jbj!jdjjf}r@%(jh]ji]jj]jk]jn]ujpMjjr]rA%j{X 0x9f000000rB%rC%}rD%(jYj?%jZj=%ubaubajdj$ubj$)rE%}rF%(jYUjf}rG%(jh]ji]jj]jk]jn]ujZj)%jr]rH%j)rI%}rJ%(jYX8 MBrK%jZjE%jbj!jdjjf}rL%(jh]ji]jj]jk]jn]ujpMjjr]rM%j{X8 MBrN%rO%}rP%(jYjK%jZjI%ubaubajdj$ubejdj$ubj$)rQ%}rR%(jYUjf}rS%(jh]ji]jj]jk]jn]ujZj$jr]rT%(j$)rU%}rV%(jYUjf}rW%(jh]ji]jj]jk]jn]ujZjQ%jr]rX%j)rY%}rZ%(jYX Default CMAr[%jZjU%jbj!jdjjf}r\%(jh]ji]jj]jk]jn]ujpMljr]r]%j{X Default CMAr^%r_%}r`%(jYj[%jZjY%ubaubajdj$ubj$)ra%}rb%(jYUjf}rc%(jh]ji]jj]jk]jn]ujZjQ%jr]rd%j)re%}rf%(jYX 0xfe400000rg%jZja%jbj!jdjjf}rh%(jh]ji]jj]jk]jn]ujpMljr]ri%j{X 0xfe400000rj%rk%}rl%(jYjg%jZje%ubaubajdj$ubj$)rm%}rn%(jYUjf}ro%(jh]ji]jj]jk]jn]ujZjQ%jr]rp%j)rq%}rr%(jYX24 MBrs%jZjm%jbj!jdjjf}rt%(jh]ji]jj]jk]jn]ujpMljr]ru%j{X24 MBrv%rw%}rx%(jYjs%jZjq%ubaubajdj$ubejdj$ubejdUtbodyry%ubejdUtgrouprz%ubaubj)r{%}r|%(jYXFor details on how to adjust the sizes and locations of the DSP/IPU CMA carveouts, please see the corresponding section for changing the DSP or IPU memory map.r}%jZj"$jbj!jdjjf}r~%(jh]ji]jj]jk]jn]ujpMojqhjr]r%j{XFor details on how to adjust the sizes and locations of the DSP/IPU CMA carveouts, please see the corresponding section for changing the DSP or IPU memory map.r%r%}r%(jYj}%jZj{%ubaubj)r%}r%(jYXZTo adjust the size of the "Default CMA" section, this is done as part of the Linux config:r%jZj"$jbj!jdjjf}r%(jh]ji]jj]jk]jn]ujpMsjqhjr]r%j{XZTo adjust the size of the "Default CMA" section, this is done as part of the Linux config:r%r%}r%(jYj%jZj%ubaubj)r%}r%(jYX1linux/arch/arm/configs/tisdk_am57xx-evm_defconfigr%jZj"$jbj!jdjjf}r%(jh]ji]jj]jk]jn]ujpMvjqhjr]r%j{X1linux/arch/arm/configs/tisdk_am57xx-evm_defconfigr%r%}r%(jYj%jZj%ubaubj)r%}r%(jYXa# # Default contiguous memory area size: # CONFIG_CMA_SIZE_MBYTES=24 CONFIG_CMA_SIZE_SEL_MBYTES=yjZj"$jbj!jdjjf}r%(jjjk]jj]jh]ji]jn]ujpMjqhjr]r%j{Xa# # Default contiguous memory area size: # CONFIG_CMA_SIZE_MBYTES=24 CONFIG_CMA_SIZE_SEL_MBYTES=yr%r%}r%(jYUjZj%ubaubjZ)r%}r%(jYUjZj"$jbj!jdj]jf}r%(jh]ji]jj]jk]jn]ujpMjqhjr]r%j`)r%}r%(jYUjcKjZj%jbj!jdjpjf}r%(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r%}r%(jYXCMEMr%jZj"$jbj!jdjjf}r%(jk]r%Ucmemr%ajj]jh]ji]jn]r%hKaujpNjqhjr]r%j{XCMEMr%r%}r%(jYj%jZj%ubaubj)r%}r%(jYX#To view the allocation at run-time:r%jZj"$jbj!jdjjf}r%(jh]ji]jj]jk]jn]ujpMjqhjr]r%j{X#To view the allocation at run-time:r%r%}r%(jYj%jZj%ubaubj)r%}r%(jYXroot@am57xx-evm:~# cat /proc/cmem Block 0: Pool 0: 1 bufs size 0xc000000 (0xc000000 requested) Pool 0 busy bufs: Pool 0 free bufs: id 0: phys addr 0xa0000000jZj"$jbj!jdjjf}r%(jjjk]jj]jh]ji]jn]ujpMjqhjr]r%j{Xroot@am57xx-evm:~# cat /proc/cmem Block 0: Pool 0: 1 bufs size 0xc000000 (0xc000000 requested) Pool 0 busy bufs: Pool 0 free bufs: id 0: phys addr 0xa0000000r%r%}r%(jYUjZj%ubaubj)r%}r%(jYXThis shows that we have defined a CMEM block at physical base address of 0xA0000000 with total size 0xc000000 (192 MB). This block contains a buffer pool consisting of 1 buffer. Each buffer in the pool (only one in this case) is defined to have a size of 0xc000000 (192 MB).r%jZj"$jbj!jdjjf}r%(jh]ji]jj]jk]jn]ujpMjqhjr]r%j{XThis shows that we have defined a CMEM block at physical base address of 0xA0000000 with total size 0xc000000 (192 MB). This block contains a buffer pool consisting of 1 buffer. Each buffer in the pool (only one in this case) is defined to have a size of 0xc000000 (192 MB).r%r%}r%(jYj%jZj%ubaubj)r%}r%(jYXDHere is where those sizes/addresses were defined for the AM57xx EVM:r%jZj"$jbj!jdjjf}r%(jh]ji]jj]jk]jn]ujpMjqhjr]r%j{XDHere is where those sizes/addresses were defined for the AM57xx EVM:r%r%}r%(jYj%jZj%ubaubj)r%}r%(jYX,linux/arch/arm/boot/dts/am57xx-evm-cmem.dtsir%jZj"$jbj!jdjjf}r%(jh]ji]jj]jk]jn]ujpMjqhjr]r%j{X,linux/arch/arm/boot/dts/am57xx-evm-cmem.dtsir%r%}r%(jYj%jZj%ubaubj)r%}r%(jYX{{ reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; cmem_block_mem_0: cmem_block_mem@a0000000 { reg = <0x0 0xa0000000 0x0 0x0c000000>; no-map; status = "okay"; }; cmem_block_mem_1_ocmc3: cmem_block_mem@40500000 { reg = <0x0 0x40500000 0x0 0x100000>; no-map; status = "okay"; }; }; cmem { compatible = "ti,cmem"; #address-cells = <1>; #size-cells = <0>; #pool-size-cells = <2>; status = "okay"; cmem_block_0: cmem_block@0 { reg = <0>; memory-region = <&cmem_block_mem_0>; cmem-buf-pools = <1 0x0 0x0c000000>; }; cmem_block_1: cmem_block@1 { reg = <1>; memory-region = <&cmem_block_mem_1_ocmc3>; }; }; };jZj"$jbj!jdjjf}r%(jjjk]jj]jh]ji]jn]ujpM*jqhjr]r%j{X{{ reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; cmem_block_mem_0: cmem_block_mem@a0000000 { reg = <0x0 0xa0000000 0x0 0x0c000000>; no-map; status = "okay"; }; cmem_block_mem_1_ocmc3: cmem_block_mem@40500000 { reg = <0x0 0x40500000 0x0 0x100000>; no-map; status = "okay"; }; }; cmem { compatible = "ti,cmem"; #address-cells = <1>; #size-cells = <0>; #pool-size-cells = <2>; status = "okay"; cmem_block_0: cmem_block@0 { reg = <0>; memory-region = <&cmem_block_mem_0>; cmem-buf-pools = <1 0x0 0x0c000000>; }; cmem_block_1: cmem_block@1 { reg = <1>; memory-region = <&cmem_block_mem_1_ocmc3>; }; }; };r%r%}r%(jYUjZj%ubaubjZ)r%}r%(jYUjZj"$jbj!jdj]jf}r%(jh]ji]jj]jk]jn]ujpMjqhjr]r%j`)r%}r%(jYUjcKjZj%jbj!jdjpjf}r%(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r%}r%(jYXChanging the DSP Memory Mapr%jZj"$jbj!jdjjf}r%(jk]r%Uchanging-the-dsp-memory-mapr%ajj]jh]ji]jn]r%haujpNjqhjr]r%j{XChanging the DSP Memory Mapr%r%}r%(jYj%jZj%ubaubj)r%}r%(jYXFirst, it is important to understand that there are a pair of Memory Management Units (MMUs) that sit between the DSP subsystems and the L3 interconnect. One of these MMUs is for the DSP core and the other is for its local EDMA. They both serve the same purpose of translating virtual addresses (i.e. the addresses as viewed by the DSP subsystem) into physical addresses (i.e. addresses as viewed from the L3 interconnect).r%jZj"$jbj!jdjjf}r%(jh]ji]jj]jk]jn]ujpMjqhjr]r%j{XFirst, it is important to understand that there are a pair of Memory Management Units (MMUs) that sit between the DSP subsystems and the L3 interconnect. One of these MMUs is for the DSP core and the other is for its local EDMA. They both serve the same purpose of translating virtual addresses (i.e. the addresses as viewed by the DSP subsystem) into physical addresses (i.e. addresses as viewed from the L3 interconnect).r%r%}r%(jYj%jZj%ubaubjB)r%}r%(jYX(.. Image:: ../images/LinuxIpcDspMmu.png jZj"$jbj!jdjEjf}r%(UuriX!rtos/../images/LinuxIpcDspMmu.pngr%jk]jj]jh]ji]jH}r%U*j%sjn]ujpMjqhjr]ubj)r%}r%(jYXDSP Physical Addressesr%jZj"$jbj!jdjjf}r%(jk]r%Udsp-physical-addressesr%ajj]jh]ji]jn]r%hZaujpNjqhjr]r&j{XDSP Physical Addressesr&r&}r&(jYj%jZj%ubaubj)r&}r&(jYXThe physical location where the DSP code/data will actually reside is defined by the CMA carveout. To change this location, you must change the definition of the carveout. **The DSP carveouts are defined in the Linux dts file.** For example for the AM57xx EVM:jZj"$jbj!jdjjf}r&(jh]ji]jj]jk]jn]ujpMjqhjr]r&(j{XThe physical location where the DSP code/data will actually reside is defined by the CMA carveout. To change this location, you must change the definition of the carveout. r&r &}r &(jYXThe physical location where the DSP code/data will actually reside is defined by the CMA carveout. To change this location, you must change the definition of the carveout. jZj&ubj)r &}r &(jYX8**The DSP carveouts are defined in the Linux dts file.**jf}r &(jh]ji]jj]jk]jn]ujZj&jr]r&j{X4The DSP carveouts are defined in the Linux dts file.r&r&}r&(jYUjZj &ubajdjubj{X For example for the AM57xx EVM:r&r&}r&(jYX For example for the AM57xx EVM:jZj&ubeubjZ)r&}r&(jYUjZj"$jbj!jdj]jf}r&(jh]ji]jj]jk]jn]ujpMjqhjr]r&j`)r&}r&(jYUjcKjZj&jbj!jdjpjf}r&(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r&}r&(jYX5linux/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsir&jZj"$jbj!jdjjf}r&(jh]ji]jj]jk]jn]ujpMjqhjr]r &j{X5linux/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsir!&r"&}r#&(jYj&jZj&ubaubj)r$&}r%&(jYX{ dsp1_cma_pool: dsp1_cma@99000000 { compatible = "shared-dma-pool"; reg = <0x0 0x99000000 0x0 0x4000000>; reusable; status = "okay"; }; dsp2_cma_pool: dsp2_cma@9f000000 { compatible = "shared-dma-pool"; reg = <0x0 0x9f000000 0x0 0x800000>; reusable; status = "okay"; }; };jZj"$jbj!jdjjf}r&&(jjjk]jj]jh]ji]jn]ujpMnjqhjr]r'&j{X{ dsp1_cma_pool: dsp1_cma@99000000 { compatible = "shared-dma-pool"; reg = <0x0 0x99000000 0x0 0x4000000>; reusable; status = "okay"; }; dsp2_cma_pool: dsp2_cma@9f000000 { compatible = "shared-dma-pool"; reg = <0x0 0x9f000000 0x0 0x800000>; reusable; status = "okay"; }; };r(&r)&}r*&(jYUjZj$&ubaubjZ)r+&}r,&(jYUjZj"$jbj!jdj]jf}r-&(jh]ji]jj]jk]jn]ujpMjqhjr]r.&j`)r/&}r0&(jYUjcKjZj+&jbj!jdjpjf}r1&(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r2&}r3&(jYXeYou are able to change both the size and location. **Be careful not to overlap any other carveouts!**jZj"$jbj!jdjjf}r4&(jh]ji]jj]jk]jn]ujpMjqhjr]r5&(j{X3You are able to change both the size and location. r6&r7&}r8&(jYX3You are able to change both the size and location. jZj2&ubj)r9&}r:&(jYX2**Be careful not to overlap any other carveouts!**jf}r;&(jh]ji]jj]jk]jn]ujZj2&jr]r<&j{X.Be careful not to overlap any other carveouts!r=&r>&}r?&(jYUjZj9&ubajdjubeubj)r@&}rA&(jYX?The **two** location entries for a given DSP must be identical!jZj"$jbj!jdjjf}rB&(jh]ji]jj]jk]jn]ujpNjqhjr]rC&j)rD&}rE&(jYX?The **two** location entries for a given DSP must be identical!jZj@&jbj!jdjjf}rF&(jh]ji]jj]jk]jn]ujpMjr]rG&(j{XThe rH&rI&}rJ&(jYXThe jZjD&ubj)rK&}rL&(jYX**two**jf}rM&(jh]ji]jj]jk]jn]ujZjD&jr]rN&j{XtworO&rP&}rQ&(jYUjZjK&ubajdjubj{X4 location entries for a given DSP must be identical!rR&rS&}rT&(jYX4 location entries for a given DSP must be identical!jZjD&ubeubaubjZ)rU&}rV&(jYUjZj"$jbj!jdj]jf}rW&(jh]ji]jj]jk]jn]ujpMjqhjr]rX&j`)rY&}rZ&(jYUjcKjZjU&jbj!jdjpjf}r[&(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r\&}r]&(jYX,Additionally, when you change the carveout location, there is a corresponding change that must be made to the resource table. For starters, if you're making a memory change you will need a **custom** resource table. The resource table is a large structure that is the "bridge" between physical memory and virtual memory. This structure is utilized for configuring the MMUs that sit in front of the DSP subsystem. There is detailed information available in the article `IPC Resource customTable `__.jZj"$jbj!jdjjf}r^&(jh]ji]jj]jk]jn]ujpMjqhjr]r_&(j{XAdditionally, when you change the carveout location, there is a corresponding change that must be made to the resource table. For starters, if you're making a memory change you will need a r`&ra&}rb&(jYXAdditionally, when you change the carveout location, there is a corresponding change that must be made to the resource table. For starters, if you're making a memory change you will need a jZj\&ubj)rc&}rd&(jYX **custom**jf}re&(jh]ji]jj]jk]jn]ujZj\&jr]rf&j{Xcustomrg&rh&}ri&(jYUjZjc&ubajdjubj{X  resource table. The resource table is a large structure that is the "bridge" between physical memory and virtual memory. This structure is utilized for configuring the MMUs that sit in front of the DSP subsystem. There is detailed information available in the article rj&rk&}rl&(jYX  resource table. The resource table is a large structure that is the "bridge" between physical memory and virtual memory. This structure is utilized for configuring the MMUs that sit in front of the DSP subsystem. There is detailed information available in the article jZj\&ubj)rm&}rn&(jYXW`IPC Resource customTable `__jf}ro&(UnameXIPC Resource customTablejX8index_Foundational_Components.html#resource-custom-tablejk]jj]jh]ji]jn]ujZj\&jr]rp&j{XIPC Resource customTablerq&rr&}rs&(jYUjZjm&ubajdjubj{X.rt&}ru&(jYX.jZj\&ubeubj)rv&}rw&(jYXOnce you've created your custom resource table, you must update the address of PHYS_MEM_IPC_VRING to be the same base address as your corresponding CMA.rx&jZj"$jbj!jdjjf}ry&(jh]ji]jj]jk]jn]ujpMjqhjr]rz&j{XOnce you've created your custom resource table, you must update the address of PHYS_MEM_IPC_VRING to be the same base address as your corresponding CMA.r{&r|&}r}&(jYjx&jZjv&ubaubj)r~&}r&(jYX#if defined (VAYU_DSP_1) #define PHYS_MEM_IPC_VRING 0x99000000 #elif defined (VAYU_DSP_2) #define PHYS_MEM_IPC_VRING 0x9F000000 #endifjZj"$jbj!jdjjf}r&(jjXcjjjk]jj]jh]j }ji]jn]ujpMjqhjr]r&j{X#if defined (VAYU_DSP_1) #define PHYS_MEM_IPC_VRING 0x99000000 #elif defined (VAYU_DSP_2) #define PHYS_MEM_IPC_VRING 0x9F000000 #endifr&r&}r&(jYUjZj~&ubaubjZ)r&}r&(jYUjZj"$jbj!jdj]jf}r&(jh]ji]jj]jk]jn]ujpMjqhjr]r&j`)r&}r&(jYUjcKjZj&jbj!jdjpjf}r&(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r&}r&(jYXpThe PHYS_MEM_IPC_VRING definition from the resource table must match the address of the associated CMA carveout!jZj"$jbj!jdjjf}r&(jh]ji]jj]jk]jn]ujpNjqhjr]r&j)r&}r&(jYXpThe PHYS_MEM_IPC_VRING definition from the resource table must match the address of the associated CMA carveout!r&jZj&jbj!jdjjf}r&(jh]ji]jj]jk]jn]ujpMjr]r&j{XpThe PHYS_MEM_IPC_VRING definition from the resource table must match the address of the associated CMA carveout!r&r&}r&(jYj&jZj&ubaubaubj)r&}r&(jYXDSP Virtual Addressesr&jZj"$jbj!jdjjf}r&(jk]r&Udsp-virtual-addressesr&ajj]jh]ji]jn]r&haujpNjqhjr]r&j{XDSP Virtual Addressesr&r&}r&(jYj&jZj&ubaubj)r&}r&(jYX{These addresses are the ones seen by the DSP subsystem, i.e. these will be the addresses in your linker command files, etc.r&jZj"$jbj!jdjjf}r&(jh]ji]jj]jk]jn]ujpMjqhjr]r&j{X{These addresses are the ones seen by the DSP subsystem, i.e. these will be the addresses in your linker command files, etc.r&r&}r&(jYj&jZj&ubaubj)r&}r&(jYXwYou must ensure that the sizes of your sections are consistent with the corresponding definitions in the resource table. You should create your own resource table in order to modify the memory map. This is describe in the wiki page `IPC Resource customTable `__. You can look at an existing resource table inside IPC:jZj"$jbj!jdjjf}r&(jh]ji]jj]jk]jn]ujpMjqhjr]r&(j{XYou must ensure that the sizes of your sections are consistent with the corresponding definitions in the resource table. You should create your own resource table in order to modify the memory map. This is describe in the wiki page r&r&}r&(jYXYou must ensure that the sizes of your sections are consistent with the corresponding definitions in the resource table. You should create your own resource table in order to modify the memory map. This is describe in the wiki page jZj&ubj)r&}r&(jYXW`IPC Resource customTable `__jf}r&(UnameXIPC Resource customTablejX8index_Foundational_Components.html#resource-custom-tablejk]jj]jh]ji]jn]ujZj&jr]r&j{XIPC Resource customTabler&r&}r&(jYUjZj&ubajdjubj{X8. You can look at an existing resource table inside IPC:r&r&}r&(jYX8. You can look at an existing resource table inside IPC:jZj&ubeubj)r&}r&(jYX3ipc/packages/ti/ipc/remoteproc/rsc_table_vayu_dsp.hr&jZj"$jbj!jdjjf}r&(jh]ji]jj]jk]jn]ujpM"jqhjr]r&j{X3ipc/packages/ti/ipc/remoteproc/rsc_table_vayu_dsp.hr&r&}r&(jYj&jZj&ubaubj)r&}r&(jYX,{ TYPE_CARVEOUT, DSP_MEM_TEXT, 0, DSP_MEM_TEXT_SIZE, 0, 0, "DSP_MEM_TEXT", }, { TYPE_CARVEOUT, DSP_MEM_DATA, 0, DSP_MEM_DATA_SIZE, 0, 0, "DSP_MEM_DATA", }, { TYPE_CARVEOUT, DSP_MEM_HEAP, 0, DSP_MEM_HEAP_SIZE, 0, 0, "DSP_MEM_HEAP", }, { TYPE_CARVEOUT, DSP_MEM_IPC_DATA, 0, DSP_MEM_IPC_DATA_SIZE, 0, 0, "DSP_MEM_IPC_DATA", }, { TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:dsp", }, { TYPE_DEVMEM, DSP_MEM_IPC_VRING, PHYS_MEM_IPC_VRING, DSP_MEM_IPC_VRING_SIZE, 0, 0, "DSP_MEM_IPC_VRING", },jZj"$jbj!jdjjf}r&(jjXcjjjk]jj]jh]j }ji]jn]ujpM$jqhjr]r&j{X,{ TYPE_CARVEOUT, DSP_MEM_TEXT, 0, DSP_MEM_TEXT_SIZE, 0, 0, "DSP_MEM_TEXT", }, { TYPE_CARVEOUT, DSP_MEM_DATA, 0, DSP_MEM_DATA_SIZE, 0, 0, "DSP_MEM_DATA", }, { TYPE_CARVEOUT, DSP_MEM_HEAP, 0, DSP_MEM_HEAP_SIZE, 0, 0, "DSP_MEM_HEAP", }, { TYPE_CARVEOUT, DSP_MEM_IPC_DATA, 0, DSP_MEM_IPC_DATA_SIZE, 0, 0, "DSP_MEM_IPC_DATA", }, { TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:dsp", }, { TYPE_DEVMEM, DSP_MEM_IPC_VRING, PHYS_MEM_IPC_VRING, DSP_MEM_IPC_VRING_SIZE, 0, 0, "DSP_MEM_IPC_VRING", },r&r&}r&(jYUjZj&ubaubjZ)r&}r&(jYUjZj"$jbj!jdj]jf}r&(jh]ji]jj]jk]jn]ujpMIjqhjr]r&j`)r&}r&(jYUjcKjZj&jbj!jdjpjf}r&(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r&}r&(jYXJLet's have a look at some of these to understand them better. For example:r&jZj"$jbj!jdjjf}r&(jh]ji]jj]jk]jn]ujpMKjqhjr]r&j{XJLet's have a look at some of these to understand them better. For example:r&r&}r&(jYj&jZj&ubaubj)r&}r&(jYXY{ TYPE_CARVEOUT, DSP_MEM_TEXT, 0, DSP_MEM_TEXT_SIZE, 0, 0, "DSP_MEM_TEXT", },jZj"$jbj!jdjjf}r&(jjXcjjjk]jj]jh]j }ji]jn]ujpMNjqhjr]r&j{XY{ TYPE_CARVEOUT, DSP_MEM_TEXT, 0, DSP_MEM_TEXT_SIZE, 0, 0, "DSP_MEM_TEXT", },r&r&}r&(jYUjZj&ubaubjZ)r&}r&(jYUjZj"$jbj!jdj]jf}r&(jh]ji]jj]jk]jn]ujpMVjqhjr]r&j`)r&}r&(jYUjcKjZj&jbj!jdjpjf}r&(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r&}r&(jYXKey points to note are:r&jZj"$jbj!jdjjf}r&(jh]ji]jj]jk]jn]ujpMXjqhjr]r&j{XKey points to note are:r&r&}r&(jYj&jZj&ubaubj%)r&}r&(jYUjZj"$jbj!jdj(jf}r&(j*U.jk]jj]jh]j+Uji]jn]j,j-ujpMZjqhjr]r&(j/)r&}r&(jYXqThe "TYPE_CARVEOUT" indicates that the physical memory backing this entry will come from the associated CMA pool.jZj&jbj!jdj2jf}r&(jh]ji]jj]jk]jn]ujpNjqhjr]r&j)r&}r&(jYXqThe "TYPE_CARVEOUT" indicates that the physical memory backing this entry will come from the associated CMA pool.r&jZj&jbj!jdjjf}r&(jh]ji]jj]jk]jn]ujpMZjr]r&j{XqThe "TYPE_CARVEOUT" indicates that the physical memory backing this entry will come from the associated CMA pool.r&r&}r&(jYj&jZj&ubaubaubj/)r'}r'(jYXDSP_MEM_TEXT is a #define earlier in the code providing the address for the code section. It is 0x95000000 by default. **This must correspond to a section from your DSP linker command file, i.e. EXT_CODE (or whatever name you choose to give it) must be linked to the same address.**jZj&jbj!jdj2jf}r'(jh]ji]jj]jk]jn]ujpNjqhjr]r'j)r'}r'(jYXDSP_MEM_TEXT is a #define earlier in the code providing the address for the code section. It is 0x95000000 by default. **This must correspond to a section from your DSP linker command file, i.e. EXT_CODE (or whatever name you choose to give it) must be linked to the same address.**jZj'jbj!jdjjf}r'(jh]ji]jj]jk]jn]ujpM\jr]r'(j{XwDSP_MEM_TEXT is a #define earlier in the code providing the address for the code section. It is 0x95000000 by default. r'r '}r '(jYXwDSP_MEM_TEXT is a #define earlier in the code providing the address for the code section. It is 0x95000000 by default. jZj'ubj)r '}r '(jYX**This must correspond to a section from your DSP linker command file, i.e. EXT_CODE (or whatever name you choose to give it) must be linked to the same address.**jf}r '(jh]ji]jj]jk]jn]ujZj'jr]r'j{XThis must correspond to a section from your DSP linker command file, i.e. EXT_CODE (or whatever name you choose to give it) must be linked to the same address.r'r'}r'(jYUjZj 'ubajdjubeubaubj/)r'}r'(jYXDSP_MEM_TEXT_SIZE is the size of the MMU pagetable entry being created (1MB in this particular instance). **The actual amount of linked code in the corresponding section of your executable must be less than or equal to this size.** jZj&jbj!jdj2jf}r'(jh]ji]jj]jk]jn]ujpNjqhjr]r'j)r'}r'(jYXDSP_MEM_TEXT_SIZE is the size of the MMU pagetable entry being created (1MB in this particular instance). **The actual amount of linked code in the corresponding section of your executable must be less than or equal to this size.**jZj'jbj!jdjjf}r'(jh]ji]jj]jk]jn]ujpMajr]r'(j{XjDSP_MEM_TEXT_SIZE is the size of the MMU pagetable entry being created (1MB in this particular instance). r'r'}r'(jYXjDSP_MEM_TEXT_SIZE is the size of the MMU pagetable entry being created (1MB in this particular instance). jZj'ubj)r'}r'(jYX}**The actual amount of linked code in the corresponding section of your executable must be less than or equal to this size.**jf}r'(jh]ji]jj]jk]jn]ujZj'jr]r 'j{XyThe actual amount of linked code in the corresponding section of your executable must be less than or equal to this size.r!'r"'}r#'(jYUjZj'ubajdjubeubaubeubj)r$'}r%'(jYXLet's take another:r&'jZj"$jbj!jdjjf}r''(jh]ji]jj]jk]jn]ujpMfjqhjr]r('j{XLet's take another:r)'r*'}r+'(jYj&'jZj$'ubaubj)r,'}r-'(jYX:{ TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:dsp", },jZj"$jbj!jdjjf}r.'(jjXcjjjk]jj]jh]j }ji]jn]ujpMhjqhjr]r/'j{X:{ TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:dsp", },r0'r1'}r2'(jYUjZj,'ubaubjZ)r3'}r4'(jYUjZj"$jbj!jdj]jf}r5'(jh]ji]jj]jk]jn]ujpMnjqhjr]r6'j`)r7'}r8'(jYUjcKjZj3'jbj!jdjpjf}r9'(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r:'}r;'(jYXKey points are:r<'jZj"$jbj!jdjjf}r='(jh]ji]jj]jk]jn]ujpMpjqhjr]r>'j{XKey points are:r?'r@'}rA'(jYj<'jZj:'ubaubj%)rB'}rC'(jYUjZj"$jbj!jdj(jf}rD'(j*U.jk]jj]jh]j+Uji]jn]j,j-ujpMrjqhjr]rE'(j/)rF'}rG'(jYX2The "TYPE_TRACE" indicates this is for trace info.rH'jZjB'jbj!jdj2jf}rI'(jh]ji]jj]jk]jn]ujpNjqhjr]rJ'j)rK'}rL'(jYjH'jZjF'jbj!jdjjf}rM'(jh]ji]jj]jk]jn]ujpMrjr]rN'j{X2The "TYPE_TRACE" indicates this is for trace info.rO'rP'}rQ'(jYjH'jZjK'ubaubaubj/)rR'}rS'(jYXThe TRACEBUFADDR is defined earlier in the file as &ti_trace_SysMin_Module_State_0_outbuf__A. That corresponds to the symbol used in TI-RTOS for the trace buffer.jZjB'jbj!jdj2jf}rT'(jh]ji]jj]jk]jn]ujpNjqhjr]rU'j)rV'}rW'(jYXThe TRACEBUFADDR is defined earlier in the file as &ti_trace_SysMin_Module_State_0_outbuf__A. That corresponds to the symbol used in TI-RTOS for the trace buffer.rX'jZjR'jbj!jdjjf}rY'(jh]ji]jj]jk]jn]ujpMsjr]rZ'j{XThe TRACEBUFADDR is defined earlier in the file as &ti_trace_SysMin_Module_State_0_outbuf__A. That corresponds to the symbol used in TI-RTOS for the trace buffer.r['r\'}r]'(jYjX'jZjV'ubaubaubj/)r^'}r_'(jYXThe "0x8000" is the size of the MMU mapping. The corresponding size in the cfg file should be the same (or less). It looks like this: ``SysMin.bufSize = 0x8000;`` jZjB'jbj!jdj2jf}r`'(jh]ji]jj]jk]jn]ujpNjqhjr]ra'j)rb'}rc'(jYXThe "0x8000" is the size of the MMU mapping. The corresponding size in the cfg file should be the same (or less). It looks like this: ``SysMin.bufSize = 0x8000;``jZj^'jbj!jdjjf}rd'(jh]ji]jj]jk]jn]ujpMvjr]re'(j{XThe "0x8000" is the size of the MMU mapping. The corresponding size in the cfg file should be the same (or less). It looks like this: rf'rg'}rh'(jYXThe "0x8000" is the size of the MMU mapping. The corresponding size in the cfg file should be the same (or less). It looks like this: jZjb'ubcdocutils.nodes literal ri')rj'}rk'(jYX``SysMin.bufSize = 0x8000;``jf}rl'(jh]ji]jj]jk]jn]ujZjb'jr]rm'j{XSysMin.bufSize = 0x8000;rn'ro'}rp'(jYUjZjj'ubajdUliteralrq'ubeubaubeubj)rr'}rs'(jYX-Finally, let's look at a TYPE_DEVMEM example:rt'jZj"$jbj!jdjjf}ru'(jh]ji]jj]jk]jn]ujpMzjqhjr]rv'j{X-Finally, let's look at a TYPE_DEVMEM example:rw'rx'}ry'(jYjt'jZjr'ubaubj)rz'}r{'(jYXn{ TYPE_DEVMEM, DSP_PERIPHERAL_L4CFG, L4_PERIPHERAL_L4CFG, SZ_16M, 0, 0, "DSP_PERIPHERAL_L4CFG", },jZj"$jbj!jdjjf}r|'(jjXcjjjk]jj]jh]j }ji]jn]ujpM|jqhjr]r}'j{Xn{ TYPE_DEVMEM, DSP_PERIPHERAL_L4CFG, L4_PERIPHERAL_L4CFG, SZ_16M, 0, 0, "DSP_PERIPHERAL_L4CFG", },r~'r'}r'(jYUjZjz'ubaubjZ)r'}r'(jYUjZj"$jbj!jdj]jf}r'(jh]ji]jj]jk]jn]ujpMjqhjr]r'j`)r'}r'(jYUjcKjZj'jbj!jdjpjf}r'(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r'}r'(jYX Key points:r'jZj"$jbj!jdjjf}r'(jh]ji]jj]jk]jn]ujpMjqhjr]r'j{X Key points:r'r'}r'(jYj'jZj'ubaubj%)r'}r'(jYUjZj"$jbj!jdj(jf}r'(j*U.jk]jj]jh]j+Uji]jn]j,j-ujpMjqhjr]r'(j/)r'}r'(jYXThe "TYPE_DEVMEM" indicates that we are making an MMU mapping, but this *does not come from the CMA pool*. This is intended for mapping peripherals, etc. that already exist in the device memory map.jZj'jbj!jdj2jf}r'(jh]ji]jj]jk]jn]ujpNjqhjr]r'j)r'}r'(jYXThe "TYPE_DEVMEM" indicates that we are making an MMU mapping, but this *does not come from the CMA pool*. This is intended for mapping peripherals, etc. that already exist in the device memory map.jZj'jbj!jdjjf}r'(jh]ji]jj]jk]jn]ujpMjr]r'(j{XHThe "TYPE_DEVMEM" indicates that we are making an MMU mapping, but this r'r'}r'(jYXHThe "TYPE_DEVMEM" indicates that we are making an MMU mapping, but this jZj'ubcdocutils.nodes emphasis r')r'}r'(jYX!*does not come from the CMA pool*jf}r'(jh]ji]jj]jk]jn]ujZj'jr]r'j{Xdoes not come from the CMA poolr'r'}r'(jYUjZj'ubajdUemphasisr'ubj{X]. This is intended for mapping peripherals, etc. that already exist in the device memory map.r'r'}r'(jYX]. This is intended for mapping peripherals, etc. that already exist in the device memory map.jZj'ubeubaubj/)r'}r'(jYXDSP_PERIPHERAL_L4CFG (0x4A000000) is the virtual address while L4_PERIPHERAL_L4CFG (0x4A000000) is the physical address. **This is an identity mapping, meaning that peripherals can be referenced by the DSP using their physical address.** jZj'jbj!jdj2jf}r'(jh]ji]jj]jk]jn]ujpNjqhjr]r'j)r'}r'(jYXDSP_PERIPHERAL_L4CFG (0x4A000000) is the virtual address while L4_PERIPHERAL_L4CFG (0x4A000000) is the physical address. **This is an identity mapping, meaning that peripherals can be referenced by the DSP using their physical address.**jZj'jbj!jdjjf}r'(jh]ji]jj]jk]jn]ujpMjr]r'(j{XyDSP_PERIPHERAL_L4CFG (0x4A000000) is the virtual address while L4_PERIPHERAL_L4CFG (0x4A000000) is the physical address. r'r'}r'(jYXyDSP_PERIPHERAL_L4CFG (0x4A000000) is the virtual address while L4_PERIPHERAL_L4CFG (0x4A000000) is the physical address. jZj'ubj)r'}r'(jYXt**This is an identity mapping, meaning that peripherals can be referenced by the DSP using their physical address.**jf}r'(jh]ji]jj]jk]jn]ujZj'jr]r'j{XpThis is an identity mapping, meaning that peripherals can be referenced by the DSP using their physical address.r'r'}r'(jYUjZj'ubajdjubeubaubeubj)r'}r'(jYXDSP Access to Peripheralsr'jZj"$jbj!jdjjf}r'(jk]r'Udsp-access-to-peripheralsr'ajj]jh]ji]jn]r'haujpNjqhjr]r'j{XDSP Access to Peripheralsr'r'}r'(jYj'jZj'ubaubj)r'}r'(jYX:The default resource table creates the following mappings:r'jZj"$jbj!jdjjf}r'(jh]ji]jj]jk]jn]ujpMjqhjr]r'j{X:The default resource table creates the following mappings:r'r'}r'(jYj'jZj'ubaubjd$)r'}r'(jYUjZj"$jbj!jdjg$jf}r'(jh]ji]jj]jk]jn]ujpNjqhjr]r'jj$)r'}r'(jYUjf}r'(jk]jj]jh]ji]jn]UcolsKujZj'jr]r'(jo$)r'}r'(jYUjf}r'(jk]jj]jh]ji]jn]UcolwidthKujZj'jr]jdjs$ubjo$)r'}r'(jYUjf}r'(jk]jj]jh]ji]jn]UcolwidthKujZj'jr]jdjs$ubjo$)r'}r'(jYUjf}r'(jk]jj]jh]ji]jn]UcolwidthKujZj'jr]jdjs$ubjo$)r'}r'(jYUjf}r'(jk]jj]jh]ji]jn]UcolwidthKujZj'jr]jdjs$ubjz$)r'}r'(jYUjf}r'(jh]ji]jj]jk]jn]ujZj'jr]r'j$)r'}r'(jYUjf}r'(jh]ji]jj]jk]jn]ujZj'jr]r'(j$)r'}r'(jYUjf}r'(jh]ji]jj]jk]jn]ujZj'jr]r'j)r'}r'(jYXVirtual Addressr'jZj'jbj!jdjjf}r'(jh]ji]jj]jk]jn]ujpMjr]r'j{XVirtual Addressr'r'}r'(jYj'jZj'ubaubajdj$ubj$)r'}r'(jYUjf}r'(jh]ji]jj]jk]jn]ujZj'jr]r'j)r'}r'(jYXPhysical Addressr'jZj'jbj!jdjjf}r'(jh]ji]jj]jk]jn]ujpMjr]r(j{XPhysical Addressr(r(}r((jYj'jZj'ubaubajdj$ubj$)r(}r((jYUjf}r((jh]ji]jj]jk]jn]ujZj'jr]r(j)r(}r ((jYXSizer (jZj(jbj!jdjjf}r ((jh]ji]jj]jk]jn]ujpMjr]r (j{XSizer (r(}r((jYj (jZj(ubaubajdj$ubj$)r(}r((jYUjf}r((jh]ji]jj]jk]jn]ujZj'jr]r(j)r(}r((jYXCommentr(jZj(jbj!jdjjf}r((jh]ji]jj]jk]jn]ujpMjr]r(j{XCommentr(r(}r((jYj(jZj(ubaubajdj$ubejdj$ubajdj$ubj$)r(}r((jYUjf}r((jh]ji]jj]jk]jn]ujZj'jr]r((j$)r (}r!((jYUjf}r"((jh]ji]jj]jk]jn]ujZj(jr]r#((j$)r$(}r%((jYUjf}r&((jh]ji]jj]jk]jn]ujZj (jr]r'(j)r((}r)((jYX 0x4A000000r*(jZj$(jbj!jdjjf}r+((jh]ji]jj]jk]jn]ujpMjr]r,(j{X 0x4A000000r-(r.(}r/((jYj*(jZj((ubaubajdj$ubj$)r0(}r1((jYUjf}r2((jh]ji]jj]jk]jn]ujZj (jr]r3(j)r4(}r5((jYX 0x4A000000r6(jZj0(jbj!jdjjf}r7((jh]ji]jj]jk]jn]ujpMjr]r8(j{X 0x4A000000r9(r:(}r;((jYj6(jZj4(ubaubajdj$ubj$)r<(}r=((jYUjf}r>((jh]ji]jj]jk]jn]ujZj (jr]r?(j)r@(}rA((jYX16 MBrB(jZj<(jbj!jdjjf}rC((jh]ji]jj]jk]jn]ujpMjr]rD(j{X16 MBrE(rF(}rG((jYjB(jZj@(ubaubajdj$ubj$)rH(}rI((jYUjf}rJ((jh]ji]jj]jk]jn]ujZj (jr]rK(j)rL(}rM((jYXL4CFG + L4WKUPrN(jZjH(jbj!jdjjf}rO((jh]ji]jj]jk]jn]ujpMjr]rP(j{XL4CFG + L4WKUPrQ(rR(}rS((jYjN(jZjL(ubaubajdj$ubejdj$ubj$)rT(}rU((jYUjf}rV((jh]ji]jj]jk]jn]ujZj(jr]rW((j$)rX(}rY((jYUjf}rZ((jh]ji]jj]jk]jn]ujZjT(jr]r[(j)r\(}r]((jYX 0x48000000r^(jZjX(jbj!jdjjf}r_((jh]ji]jj]jk]jn]ujpMjr]r`(j{X 0x48000000ra(rb(}rc((jYj^(jZj\(ubaubajdj$ubj$)rd(}re((jYUjf}rf((jh]ji]jj]jk]jn]ujZjT(jr]rg(j)rh(}ri((jYX 0x48000000rj(jZjd(jbj!jdjjf}rk((jh]ji]jj]jk]jn]ujpMjr]rl(j{X 0x48000000rm(rn(}ro((jYjj(jZjh(ubaubajdj$ubj$)rp(}rq((jYUjf}rr((jh]ji]jj]jk]jn]ujZjT(jr]rs(j)rt(}ru((jYX2 MBrv(jZjp(jbj!jdjjf}rw((jh]ji]jj]jk]jn]ujpMjr]rx(j{X2 MBry(rz(}r{((jYjv(jZjt(ubaubajdj$ubj$)r|(}r}((jYUjf}r~((jh]ji]jj]jk]jn]ujZjT(jr]r(j)r(}r((jYXL4PER1r(jZj|(jbj!jdjjf}r((jh]ji]jj]jk]jn]ujpMjr]r(j{XL4PER1r(r(}r((jYj(jZj(ubaubajdj$ubejdj$ubj$)r(}r((jYUjf}r((jh]ji]jj]jk]jn]ujZj(jr]r((j$)r(}r((jYUjf}r((jh]ji]jj]jk]jn]ujZj(jr]r(j)r(}r((jYX 0x48400000r(jZj(jbj!jdjjf}r((jh]ji]jj]jk]jn]ujpMjr]r(j{X 0x48400000r(r(}r((jYj(jZj(ubaubajdj$ubj$)r(}r((jYUjf}r((jh]ji]jj]jk]jn]ujZj(jr]r(j)r(}r((jYX 0x48400000r(jZj(jbj!jdjjf}r((jh]ji]jj]jk]jn]ujpMjr]r(j{X 0x48400000r(r(}r((jYj(jZj(ubaubajdj$ubj$)r(}r((jYUjf}r((jh]ji]jj]jk]jn]ujZj(jr]r(j)r(}r((jYX4 MBr(jZj(jbj!jdjjf}r((jh]ji]jj]jk]jn]ujpMjr]r(j{X4 MBr(r(}r((jYj(jZj(ubaubajdj$ubj$)r(}r((jYUjf}r((jh]ji]jj]jk]jn]ujZj(jr]r(j)r(}r((jYXL4PER2r(jZj(jbj!jdjjf}r((jh]ji]jj]jk]jn]ujpMjr]r(j{XL4PER2r(r(}r((jYj(jZj(ubaubajdj$ubejdj$ubj$)r(}r((jYUjf}r((jh]ji]jj]jk]jn]ujZj(jr]r((j$)r(}r((jYUjf}r((jh]ji]jj]jk]jn]ujZj(jr]r(j)r(}r((jYX 0x48800000r(jZj(jbj!jdjjf}r((jh]ji]jj]jk]jn]ujpMjr]r(j{X 0x48800000r(r(}r((jYj(jZj(ubaubajdj$ubj$)r(}r((jYUjf}r((jh]ji]jj]jk]jn]ujZj(jr]r(j)r(}r((jYX 0x48800000r(jZj(jbj!jdjjf}r((jh]ji]jj]jk]jn]ujpMjr]r(j{X 0x48800000r(r(}r((jYj(jZj(ubaubajdj$ubj$)r(}r((jYUjf}r((jh]ji]jj]jk]jn]ujZj(jr]r(j)r(}r((jYX8 MBr(jZj(jbj!jdjjf}r((jh]ji]jj]jk]jn]ujpMjr]r(j{X8 MBr(r(}r((jYj(jZj(ubaubajdj$ubj$)r(}r((jYUjf}r((jh]ji]jj]jk]jn]ujZj(jr]r(j)r(}r((jYXL4PER3r(jZj(jbj!jdjjf}r((jh]ji]jj]jk]jn]ujpMjr]r(j{XL4PER3r(r(}r((jYj(jZj(ubaubajdj$ubejdj$ubj$)r(}r((jYUjf}r((jh]ji]jj]jk]jn]ujZj(jr]r((j$)r(}r((jYUjf}r((jh]ji]jj]jk]jn]ujZj(jr]r(j)r(}r((jYX 0x54000000r(jZj(jbj!jdjjf}r((jh]ji]jj]jk]jn]ujpMjr]r(j{X 0x54000000r(r(}r((jYj(jZj(ubaubajdj$ubj$)r)}r)(jYUjf}r)(jh]ji]jj]jk]jn]ujZj(jr]r)j)r)}r)(jYX 0x54000000r)jZj)jbj!jdjjf}r)(jh]ji]jj]jk]jn]ujpMjr]r)j{X 0x54000000r )r )}r )(jYj)jZj)ubaubajdj$ubj$)r )}r )(jYUjf}r)(jh]ji]jj]jk]jn]ujZj(jr]r)j)r)}r)(jYX16 MBr)jZj )jbj!jdjjf}r)(jh]ji]jj]jk]jn]ujpMjr]r)j{X16 MBr)r)}r)(jYj)jZj)ubaubajdj$ubj$)r)}r)(jYUjf}r)(jh]ji]jj]jk]jn]ujZj(jr]r)j)r)}r)(jYXL3_INSTR + CT_TBRr)jZj)jbj!jdjjf}r)(jh]ji]jj]jk]jn]ujpMjr]r )j{XL3_INSTR + CT_TBRr!)r")}r#)(jYj)jZj)ubaubajdj$ubejdj$ubj$)r$)}r%)(jYUjf}r&)(jh]ji]jj]jk]jn]ujZj(jr]r')(j$)r()}r))(jYUjf}r*)(jh]ji]jj]jk]jn]ujZj$)jr]r+)j)r,)}r-)(jYX 0x4E000000r.)jZj()jbj!jdjjf}r/)(jh]ji]jj]jk]jn]ujpMjr]r0)j{X 0x4E000000r1)r2)}r3)(jYj.)jZj,)ubaubajdj$ubj$)r4)}r5)(jYUjf}r6)(jh]ji]jj]jk]jn]ujZj$)jr]r7)j)r8)}r9)(jYX 0x4E000000r:)jZj4)jbj!jdjjf}r;)(jh]ji]jj]jk]jn]ujpMjr]r<)j{X 0x4E000000r=)r>)}r?)(jYj:)jZj8)ubaubajdj$ubj$)r@)}rA)(jYUjf}rB)(jh]ji]jj]jk]jn]ujZj$)jr]rC)j)rD)}rE)(jYX1 MBrF)jZj@)jbj!jdjjf}rG)(jh]ji]jj]jk]jn]ujpMjr]rH)j{X1 MBrI)rJ)}rK)(jYjF)jZjD)ubaubajdj$ubj$)rL)}rM)(jYUjf}rN)(jh]ji]jj]jk]jn]ujZj$)jr]rO)j)rP)}rQ)(jYX DMM configrR)jZjL)jbj!jdjjf}rS)(jh]ji]jj]jk]jn]ujpMjr]rT)j{X DMM configrU)rV)}rW)(jYjR)jZjP)ubaubajdj$ubejdj$ubejdjy%ubejdjz%ubaubj)rX)}rY)(jYXmIn other words, the peripherals can be accessed at their physical addresses since we use an identity mapping.rZ)jZj"$jbj!jdjjf}r[)(jh]ji]jj]jk]jn]ujpMjqhjr]r\)j{XmIn other words, the peripherals can be accessed at their physical addresses since we use an identity mapping.r])r^)}r_)(jYjZ)jZjX)ubaubj)r`)}ra)(jYX0Inspecting the DSP IOMMU Page Tables at Run-Timerb)jZj"$jbj!jdjjf}rc)(jk]rd)U0inspecting-the-dsp-iommu-page-tables-at-run-timere)ajj]jh]ji]jn]rf)haujpNjqhjr]rg)j{X0Inspecting the DSP IOMMU Page Tables at Run-Timerh)ri)}rj)(jYjb)jZj`)ubaubj)rk)}rl)(jYXCYou can dump the DSP IOMMU page tables with the following commands:rm)jZj"$jbj!jdjjf}rn)(jh]ji]jj]jk]jn]ujpMjqhjr]ro)j{XCYou can dump the DSP IOMMU page tables with the following commands:rp)rq)}rr)(jYjm)jZjk)ubaubjd$)rs)}rt)(jYUjZj"$jbj!jdjg$jf}ru)(jh]ji]jj]jk]jn]ujpNjqhjr]rv)jj$)rw)}rx)(jYUjf}ry)(jk]jj]jh]ji]jn]UcolsKujZjs)jr]rz)(jo$)r{)}r|)(jYUjf}r})(jk]jj]jh]ji]jn]UcolwidthKujZjw)jr]jdjs$ubjo$)r~)}r)(jYUjf}r)(jk]jj]jh]ji]jn]UcolwidthKujZjw)jr]jdjs$ubjo$)r)}r)(jYUjf}r)(jk]jj]jh]ji]jn]UcolwidthK9ujZjw)jr]jdjs$ubjz$)r)}r)(jYUjf}r)(jh]ji]jj]jk]jn]ujZjw)jr]r)j$)r)}r)(jYUjf}r)(jh]ji]jj]jk]jn]ujZj)jr]r)(j$)r)}r)(jYUjf}r)(jh]ji]jj]jk]jn]ujZj)jr]r)j)r)}r)(jYXDSPr)jZj)jbj!jdjjf}r)(jh]ji]jj]jk]jn]ujpMjr]r)j{XDSPr)r)}r)(jYj)jZj)ubaubajdj$ubj$)r)}r)(jYUjf}r)(jh]ji]jj]jk]jn]ujZj)jr]r)j)r)}r)(jYXMMUr)jZj)jbj!jdjjf}r)(jh]ji]jj]jk]jn]ujpMjr]r)j{XMMUr)r)}r)(jYj)jZj)ubaubajdj$ubj$)r)}r)(jYUjf}r)(jh]ji]jj]jk]jn]ujZj)jr]r)j)r)}r)(jYXCommandr)jZj)jbj!jdjjf}r)(jh]ji]jj]jk]jn]ujpMjr]r)j{XCommandr)r)}r)(jYj)jZj)ubaubajdj$ubejdj$ubajdj$ubj$)r)}r)(jYUjf}r)(jh]ji]jj]jk]jn]ujZjw)jr]r)(j$)r)}r)(jYUjf}r)(jh]ji]jj]jk]jn]ujZj)jr]r)(j$)r)}r)(jYUjf}r)(jh]ji]jj]jk]jn]ujZj)jr]r)j)r)}r)(jYXDSP1r)jZj)jbj!jdjjf}r)(jh]ji]jj]jk]jn]ujpMjr]r)j{XDSP1r)r)}r)(jYj)jZj)ubaubajdj$ubj$)r)}r)(jYUjf}r)(jh]ji]jj]jk]jn]ujZj)jr]r)j)r)}r)(jYXMMU0r)jZj)jbj!jdjjf}r)(jh]ji]jj]jk]jn]ujpMjr]r)j{XMMU0r)r)}r)(jYj)jZj)ubaubajdj$ubj$)r)}r)(jYUjf}r)(jh]ji]jj]jk]jn]ujZj)jr]r)j)r)}r)(jYX7cat /sys/kernel/debug/omap_iommu/40d01000.mmu/pagetabler)jZj)jbj!jdjjf}r)(jh]ji]jj]jk]jn]ujpMjr]r)j{X7cat /sys/kernel/debug/omap_iommu/40d01000.mmu/pagetabler)r)}r)(jYj)jZj)ubaubajdj$ubejdj$ubj$)r)}r)(jYUjf}r)(jh]ji]jj]jk]jn]ujZj)jr]r)(j$)r)}r)(jYUjf}r)(jh]ji]jj]jk]jn]ujZj)jr]r)j)r)}r)(jYXDSP1r)jZj)jbj!jdjjf}r)(jh]ji]jj]jk]jn]ujpMjr]r)j{XDSP1r)r)}r)(jYj)jZj)ubaubajdj$ubj$)r)}r)(jYUjf}r)(jh]ji]jj]jk]jn]ujZj)jr]r)j)r)}r)(jYXMMU1r)jZj)jbj!jdjjf}r)(jh]ji]jj]jk]jn]ujpMjr]r)j{XMMU1r)r)}r)(jYj)jZj)ubaubajdj$ubj$)r)}r)(jYUjf}r)(jh]ji]jj]jk]jn]ujZj)jr]r)j)r)}r)(jYX7cat /sys/kernel/debug/omap_iommu/40d02000.mmu/pagetabler)jZj)jbj!jdjjf}r)(jh]ji]jj]jk]jn]ujpMjr]r*j{X7cat /sys/kernel/debug/omap_iommu/40d02000.mmu/pagetabler*r*}r*(jYj)jZj)ubaubajdj$ubejdj$ubj$)r*}r*(jYUjf}r*(jh]ji]jj]jk]jn]ujZj)jr]r*(j$)r*}r *(jYUjf}r *(jh]ji]jj]jk]jn]ujZj*jr]r *j)r *}r *(jYXDSP2r*jZj*jbj!jdjjf}r*(jh]ji]jj]jk]jn]ujpMjr]r*j{XDSP2r*r*}r*(jYj*jZj *ubaubajdj$ubj$)r*}r*(jYUjf}r*(jh]ji]jj]jk]jn]ujZj*jr]r*j)r*}r*(jYXMMU0r*jZj*jbj!jdjjf}r*(jh]ji]jj]jk]jn]ujpMjr]r*j{XMMU0r*r*}r*(jYj*jZj*ubaubajdj$ubj$)r *}r!*(jYUjf}r"*(jh]ji]jj]jk]jn]ujZj*jr]r#*j)r$*}r%*(jYX7cat /sys/kernel/debug/omap_iommu/41501000.mmu/pagetabler&*jZj *jbj!jdjjf}r'*(jh]ji]jj]jk]jn]ujpMjr]r(*j{X7cat /sys/kernel/debug/omap_iommu/41501000.mmu/pagetabler)*r**}r+*(jYj&*jZj$*ubaubajdj$ubejdj$ubj$)r,*}r-*(jYUjf}r.*(jh]ji]jj]jk]jn]ujZj)jr]r/*(j$)r0*}r1*(jYUjf}r2*(jh]ji]jj]jk]jn]ujZj,*jr]r3*j)r4*}r5*(jYXDSP2r6*jZj0*jbj!jdjjf}r7*(jh]ji]jj]jk]jn]ujpMjr]r8*j{XDSP2r9*r:*}r;*(jYj6*jZj4*ubaubajdj$ubj$)r<*}r=*(jYUjf}r>*(jh]ji]jj]jk]jn]ujZj,*jr]r?*j)r@*}rA*(jYXMMU1rB*jZj<*jbj!jdjjf}rC*(jh]ji]jj]jk]jn]ujpMjr]rD*j{XMMU1rE*rF*}rG*(jYjB*jZj@*ubaubajdj$ubj$)rH*}rI*(jYUjf}rJ*(jh]ji]jj]jk]jn]ujZj,*jr]rK*j)rL*}rM*(jYX7cat /sys/kernel/debug/omap_iommu/41502000.mmu/pagetablerN*jZjH*jbj!jdjjf}rO*(jh]ji]jj]jk]jn]ujpMjr]rP*j{X7cat /sys/kernel/debug/omap_iommu/41502000.mmu/pagetablerQ*rR*}rS*(jYjN*jZjL*ubaubajdj$ubejdj$ubejdjy%ubejdjz%ubaubj)rT*}rU*(jYXIn general, MMU0 and MMU1 are being programmed identically so you really only need to take a look at one or the other to understand the mapping for a given DSP.rV*jZj"$jbj!jdjjf}rW*(jh]ji]jj]jk]jn]ujpMjqhjr]rX*j{XIn general, MMU0 and MMU1 are being programmed identically so you really only need to take a look at one or the other to understand the mapping for a given DSP.rY*rZ*}r[*(jYjV*jZjT*ubaubj)r\*}r]*(jYX For example:r^*jZj"$jbj!jdjjf}r_*(jh]ji]jj]jk]jn]ujpMjqhjr]r`*j{X For example:ra*rb*}rc*(jYj^*jZj\*ubaubj)rd*}re*(jYXhroot@am57xx-evm:~# cat /sys/kernel/debug/omap_iommu/40d01000.mmu/pagetable L: da: pte: -------------------------- 1: 0x48000000 0x48000002 1: 0x48100000 0x48100002 1: 0x48400000 0x48400002 1: 0x48500000 0x48500002 1: 0x48600000 0x48600002 1: 0x48700000 0x48700002 1: 0x48800000 0x48800002 1: 0x48900000 0x48900002 1: 0x48a00000 0x48a00002 1: 0x48b00000 0x48b00002 1: 0x48c00000 0x48c00002 1: 0x48d00000 0x48d00002 1: 0x48e00000 0x48e00002 1: 0x48f00000 0x48f00002 1: 0x4a000000 0x4a040002 1: 0x4a100000 0x4a040002 1: 0x4a200000 0x4a040002 1: 0x4a300000 0x4a040002 1: 0x4a400000 0x4a040002 1: 0x4a500000 0x4a040002 1: 0x4a600000 0x4a040002 1: 0x4a700000 0x4a040002 1: 0x4a800000 0x4a040002 1: 0x4a900000 0x4a040002 1: 0x4aa00000 0x4a040002 1: 0x4ab00000 0x4a040002 1: 0x4ac00000 0x4a040002 1: 0x4ad00000 0x4a040002 1: 0x4ae00000 0x4a040002 1: 0x4af00000 0x4a040002jZj"$jbj!jdjjf}rf*(jjjk]jj]jh]ji]jn]ujpMNjqhjr]rg*j{Xhroot@am57xx-evm:~# cat /sys/kernel/debug/omap_iommu/40d01000.mmu/pagetable L: da: pte: -------------------------- 1: 0x48000000 0x48000002 1: 0x48100000 0x48100002 1: 0x48400000 0x48400002 1: 0x48500000 0x48500002 1: 0x48600000 0x48600002 1: 0x48700000 0x48700002 1: 0x48800000 0x48800002 1: 0x48900000 0x48900002 1: 0x48a00000 0x48a00002 1: 0x48b00000 0x48b00002 1: 0x48c00000 0x48c00002 1: 0x48d00000 0x48d00002 1: 0x48e00000 0x48e00002 1: 0x48f00000 0x48f00002 1: 0x4a000000 0x4a040002 1: 0x4a100000 0x4a040002 1: 0x4a200000 0x4a040002 1: 0x4a300000 0x4a040002 1: 0x4a400000 0x4a040002 1: 0x4a500000 0x4a040002 1: 0x4a600000 0x4a040002 1: 0x4a700000 0x4a040002 1: 0x4a800000 0x4a040002 1: 0x4a900000 0x4a040002 1: 0x4aa00000 0x4a040002 1: 0x4ab00000 0x4a040002 1: 0x4ac00000 0x4a040002 1: 0x4ad00000 0x4a040002 1: 0x4ae00000 0x4a040002 1: 0x4af00000 0x4a040002rh*ri*}rj*(jYUjZjd*ubaubj)rk*}rl*(jYXThe first column tells us whether the mapping is a Level 1 or Level 2 descriptor. All the lines above are a first level descriptor, so we look at the associated format from the TRM:rm*jZj"$jbj!jdjjf}rn*(jh]ji]jj]jk]jn]ujpMjqhjr]ro*j{XThe first column tells us whether the mapping is a Level 1 or Level 2 descriptor. All the lines above are a first level descriptor, so we look at the associated format from the TRM:rp*rq*}rr*(jYjm*jZjk*ubaubjB)rs*}rt*(jYX6.. Image:: ../images/LinuxIpcPageTableDescriptor1.png jZj"$jbj!jdjEjf}ru*(UuriX/rtos/../images/LinuxIpcPageTableDescriptor1.pngrv*jk]jj]jh]ji]jH}rw*U*jv*sjn]ujpMjqhjr]ubj)rx*}ry*(jYXGThe "da" ("device address") column reflects the virtual address. It is *derived* from the index into the table, i.e. there does not exist a "da" register or field in the page table. Each MB of the address space maps to an entry in the table. The "da" column is displayed to make it easy to find the virtual address of interest.jZj"$jbj!jdjjf}rz*(jh]ji]jj]jk]jn]ujpMjqhjr]r{*(j{XGThe "da" ("device address") column reflects the virtual address. It is r|*r}*}r~*(jYXGThe "da" ("device address") column reflects the virtual address. It is jZjx*ubj')r*}r*(jYX *derived*jf}r*(jh]ji]jj]jk]jn]ujZjx*jr]r*j{Xderivedr*r*}r*(jYUjZj*ubajdj'ubj{X from the index into the table, i.e. there does not exist a "da" register or field in the page table. Each MB of the address space maps to an entry in the table. The "da" column is displayed to make it easy to find the virtual address of interest.r*r*}r*(jYX from the index into the table, i.e. there does not exist a "da" register or field in the page table. Each MB of the address space maps to an entry in the table. The "da" column is displayed to make it easy to find the virtual address of interest.jZjx*ubeubj)r*}r*(jYXfThe "pte" ("page table entry") column can be decoded according to Table 20-4 shown above. For example:r*jZj"$jbj!jdjjf}r*(jh]ji]jj]jk]jn]ujpMjqhjr]r*j{XfThe "pte" ("page table entry") column can be decoded according to Table 20-4 shown above. For example:r*r*}r*(jYj*jZj*ubaubj)r*}r*(jYX1: 0x4a000000 0x4a040002jZj"$jbj!jdjjf}r*(jjjk]jj]jh]ji]jn]ujpMjqhjr]r*j{X1: 0x4a000000 0x4a040002r*r*}r*(jYUjZj*ubaubj)r*}r*(jYXThe 0x4a040002 shows us that it is a Supersection with base address 0x4A000000. This gives us a 16 MB memory page. Note the repeated entries afterward. That's a requirement of the MMU. Here's an excerpt from the TRM:r*jZj"$jbj!jdjjf}r*(jh]ji]jj]jk]jn]ujpMjqhjr]r*j{XThe 0x4a040002 shows us that it is a Supersection with base address 0x4A000000. This gives us a 16 MB memory page. Note the repeated entries afterward. That's a requirement of the MMU. Here's an excerpt from the TRM:r*r*}r*(jYj*jZj*ubaubj)r*}r*(jYXSupersection descriptors must be repeated 16 times, because each descriptor in the first level translation table describes 1 MiB of memory. If an access points to a descriptor that is not initialized, the MMU will behave in an unpredictable way.jZj"$jbj!jdjjf}r*(jh]ji]jj]jk]jn]ujpNjqhjr]r*j)r*}r*(jYXSupersection descriptors must be repeated 16 times, because each descriptor in the first level translation table describes 1 MiB of memory. If an access points to a descriptor that is not initialized, the MMU will behave in an unpredictable way.r*jZj*jbj!jdjjf}r*(jh]ji]jj]jk]jn]ujpMjr]r*j{XSupersection descriptors must be repeated 16 times, because each descriptor in the first level translation table describes 1 MiB of memory. If an access points to a descriptor that is not initialized, the MMU will behave in an unpredictable way.r*r*}r*(jYj*jZj*ubaubaubjZ)r*}r*(jYUjZj"$jbj!jdj]jf}r*(jh]ji]jj]jk]jn]ujpMjqhjr]r*j`)r*}r*(jYUjcKjZj*jbj!jdjpjf}r*(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r*}r*(jYX!Changing Cortex M4 IPU Memory Mapr*jZj"$jbj!jdjjf}r*(jk]r*U!changing-cortex-m4-ipu-memory-mapr*ajj]jh]ji]jn]r*haujpNjqhjr]r*j{X!Changing Cortex M4 IPU Memory Mapr*r*}r*(jYj*jZj*ubaubj)r*}r*(jYXIn order to fully understand the memory mapping of the Cortex M4 IPU Subsystems, it's helpful to recognize that there are two distinct/independent levels of memory translation. Here's a snippet from the TRM to illustrate:r*jZj"$jbj!jdjjf}r*(jh]ji]jj]jk]jn]ujpMjqhjr]r*j{XIn order to fully understand the memory mapping of the Cortex M4 IPU Subsystems, it's helpful to recognize that there are two distinct/independent levels of memory translation. Here's a snippet from the TRM to illustrate:r*r*}r*(jYj*jZj*ubaubjB)r*}r*(jYX(.. Image:: ../images/LinuxIpcIpuMmu.png jZj"$jbj!jdjEjf}r*(UuriX!rtos/../images/LinuxIpcIpuMmu.pngr*jk]jj]jh]ji]jH}r*U*j*sjn]ujpM jqhjr]ubj)r*}r*(jYX Cortex M4 IPU Physical Addressesr*jZj"$jbj!jdjjf}r*(jk]r*U cortex-m4-ipu-physical-addressesr*ajj]jh]ji]jn]r*haujpNjqhjr]r*j{X Cortex M4 IPU Physical Addressesr*r*}r*(jYj*jZj*ubaubj)r*}r*(jYXThe physical location where the M4 code/data will actually reside is defined by the CMA carveout. To change this location, you must change the definition of the carveout. **The M4 carveouts are defined in the Linux dts file.** For example for the AM57xx EVM:jZj"$jbj!jdjjf}r*(jh]ji]jj]jk]jn]ujpMjqhjr]r*(j{XThe physical location where the M4 code/data will actually reside is defined by the CMA carveout. To change this location, you must change the definition of the carveout. r*r*}r*(jYXThe physical location where the M4 code/data will actually reside is defined by the CMA carveout. To change this location, you must change the definition of the carveout. jZj*ubj)r*}r*(jYX7**The M4 carveouts are defined in the Linux dts file.**jf}r*(jh]ji]jj]jk]jn]ujZj*jr]r*j{X3The M4 carveouts are defined in the Linux dts file.r*r*}r*(jYUjZj*ubajdjubj{X For example for the AM57xx EVM:r*r*}r*(jYX For example for the AM57xx EVM:jZj*ubeubjZ)r*}r*(jYUjZj"$jbj!jdj]jf}r*(jh]ji]jj]jk]jn]ujpMjqhjr]r*(j`)r*}r*(jYUjcKjZj*jbj!jdjpjf}r*(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)r*}r*(jYUjcKjZj*jbj!jdjpjf}r*(jh]ji]jj]jk]jn]ujpKjqhjr]ubeubj)r*}r*(jYX5linux/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsir*jZj"$jbj!jdjjf}r*(jh]ji]jj]jk]jn]ujpMjqhjr]r*j{X5linux/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsir*r*}r*(jYj*jZj*ubaubj)r*}r*(jYX{ ipu2_cma_pool: ipu2_cma@95800000 { compatible = "shared-dma-pool"; reg = <0x0 95800000 0x0 0x3800000>; reusable; status = "okay"; }; ipu1_cma_pool: ipu1_cma@9d000000 { compatible = "shared-dma-pool"; reg = <0x0 9d000000 0x0 0x2000000>; reusable; status = "okay"; }; };jZj"$jbj!jdjjf}r*(jjjk]jj]jh]ji]jn]ujpMjqhjr]r*j{X{ ipu2_cma_pool: ipu2_cma@95800000 { compatible = "shared-dma-pool"; reg = <0x0 95800000 0x0 0x3800000>; reusable; status = "okay"; }; ipu1_cma_pool: ipu1_cma@9d000000 { compatible = "shared-dma-pool"; reg = <0x0 9d000000 0x0 0x2000000>; reusable; status = "okay"; }; };r*r*}r*(jYUjZj*ubaubjZ)r+}r+(jYUjZj"$jbj!jdj]jf}r+(jh]ji]jj]jk]jn]ujpM*jqhjr]r+j`)r+}r+(jYUjcKjZj+jbj!jdjpjf}r+(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r+}r+(jYXeYou are able to change both the size and location. **Be careful not to overlap any other carveouts!**jZj"$jbj!jdjjf}r +(jh]ji]jj]jk]jn]ujpM+jqhjr]r +(j{X3You are able to change both the size and location. r +r +}r +(jYX3You are able to change both the size and location. jZj+ubj)r+}r+(jYX2**Be careful not to overlap any other carveouts!**jf}r+(jh]ji]jj]jk]jn]ujZj+jr]r+j{X.Be careful not to overlap any other carveouts!r+r+}r+(jYUjZj+ubajdjubeubj)r+}r+(jYXDThe **two** location entries for a given carveout must be identical!jZj"$jbj!jdjjf}r+(jh]ji]jj]jk]jn]ujpNjqhjr]r+j)r+}r+(jYXDThe **two** location entries for a given carveout must be identical!jZj+jbj!jdjjf}r+(jh]ji]jj]jk]jn]ujpM/jr]r+(j{XThe r+r+}r+(jYXThe jZj+ubj)r +}r!+(jYX**two**jf}r"+(jh]ji]jj]jk]jn]ujZj+jr]r#+j{Xtwor$+r%+}r&+(jYUjZj +ubajdjubj{X9 location entries for a given carveout must be identical!r'+r(+}r)+(jYX9 location entries for a given carveout must be identical!jZj+ubeubaubjZ)r*+}r++(jYUjZj"$jbj!jdj]jf}r,+(jh]ji]jj]jk]jn]ujpM1jqhjr]r-+j`)r.+}r/+(jYUjcKjZj*+jbj!jdjpjf}r0+(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r1+}r2+(jYX Additionally, when you change the carveout location, there is a corresponding change that must be made to the resource table. For starters, if you're making a memory change you will need a **custom** resource table. The resource table is a large structure that is the "bridge" between physical memory and virtual memory. This structure is utilized for configuring the IPUx_MMU (not the Unicache MMU). There is detailed information available in the article `IPC Resource customTable `__.jZj"$jbj!jdjjf}r3+(jh]ji]jj]jk]jn]ujpM2jqhjr]r4+(j{XAdditionally, when you change the carveout location, there is a corresponding change that must be made to the resource table. For starters, if you're making a memory change you will need a r5+r6+}r7+(jYXAdditionally, when you change the carveout location, there is a corresponding change that must be made to the resource table. For starters, if you're making a memory change you will need a jZj1+ubj)r8+}r9+(jYX **custom**jf}r:+(jh]ji]jj]jk]jn]ujZj1+jr]r;+j{Xcustomr<+r=+}r>+(jYUjZj8+ubajdjubj{X resource table. The resource table is a large structure that is the "bridge" between physical memory and virtual memory. This structure is utilized for configuring the IPUx_MMU (not the Unicache MMU). There is detailed information available in the article r?+r@+}rA+(jYX resource table. The resource table is a large structure that is the "bridge" between physical memory and virtual memory. This structure is utilized for configuring the IPUx_MMU (not the Unicache MMU). There is detailed information available in the article jZj1+ubj)rB+}rC+(jYXW`IPC Resource customTable `__jf}rD+(UnameXIPC Resource customTablejX8index_Foundational_Components.html#resource-custom-tablejk]jj]jh]ji]jn]ujZj1+jr]rE+j{XIPC Resource customTablerF+rG+}rH+(jYUjZjB+ubajdjubj{X.rI+}rJ+(jYX.jZj1+ubeubj)rK+}rL+(jYXOnce you've created your custom resource table, you must update the address of PHYS_MEM_IPC_VRING to be the same base address as your corresponding CMA.rM+jZj"$jbj!jdjjf}rN+(jh]ji]jj]jk]jn]ujpM;jqhjr]rO+j{XOnce you've created your custom resource table, you must update the address of PHYS_MEM_IPC_VRING to be the same base address as your corresponding CMA.rP+rQ+}rR+(jYjM+jZjK+ubaubj)rS+}rT+(jYX#if defined(VAYU_IPU_1) #define PHYS_MEM_IPC_VRING 0x9D000000 #elif defined (VAYU_IPU_2) #define PHYS_MEM_IPC_VRING 0x95800000 #endifjZj"$jbj!jdjjf}rU+(jjjk]jj]jh]ji]jn]ujpMjqhjr]rV+j{X#if defined(VAYU_IPU_1) #define PHYS_MEM_IPC_VRING 0x9D000000 #elif defined (VAYU_IPU_2) #define PHYS_MEM_IPC_VRING 0x95800000 #endifrW+rX+}rY+(jYUjZjS+ubaubjZ)rZ+}r[+(jYUjZj"$jbj!jdj]jf}r\+(jh]ji]jj]jk]jn]ujpMGjqhjr]r]+j`)r^+}r_+(jYUjcKjZjZ+jbj!jdjpjf}r`+(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)ra+}rb+(jYXpThe PHYS_MEM_IPC_VRING definition from the resource table must match the address of the associated CMA carveout!jZj"$jbj!jdjjf}rc+(jh]ji]jj]jk]jn]ujpNjqhjr]rd+j)re+}rf+(jYXpThe PHYS_MEM_IPC_VRING definition from the resource table must match the address of the associated CMA carveout!rg+jZja+jbj!jdjjf}rh+(jh]ji]jj]jk]jn]ujpMJjr]ri+j{XpThe PHYS_MEM_IPC_VRING definition from the resource table must match the address of the associated CMA carveout!rj+rk+}rl+(jYjg+jZje+ubaubaubj)rm+}rn+(jYXCortex M4 IPU Virtual Addressesro+jZj"$jbj!jdjjf}rp+(jk]rq+Ucortex-m4-ipu-virtual-addressesrr+ajj]jh]ji]jn]rs+j.aujpNjqhjr]rt+j{XCortex M4 IPU Virtual Addressesru+rv+}rw+(jYjo+jZjm+ubaubj)rx+}ry+(jYX Unicache MMUrz+jZj"$jbj!jdjjf}r{+(jk]r|+U unicache-mmur}+ajj]jh]ji]jn]r~+h?aujpNjqhjr]r+j{X Unicache MMUr+r+}r+(jYjz+jZjx+ubaubj)r+}r+(jYXTThe Unicache MMU sits closest to the Cortex M4. It provides the first level of address translation. The Unicache MMU is actually "self programmed" by the Cortex M4. The Unicache MMU is also referred to as the Attribute MMU (AMMU). There are a fixed number of small, medium and large pages. Here's a snippet showing some of the key mappings:r+jZj"$jbj!jdjjf}r+(jh]ji]jj]jk]jn]ujpMSjqhjr]r+j{XTThe Unicache MMU sits closest to the Cortex M4. It provides the first level of address translation. The Unicache MMU is actually "self programmed" by the Cortex M4. The Unicache MMU is also referred to as the Attribute MMU (AMMU). There are a fixed number of small, medium and large pages. Here's a snippet showing some of the key mappings:r+r+}r+(jYj+jZj+ubaubj)r+}r+(jYXGipc_3_43_02_04/examples/DRA7XX_linux_elf/ex02_messageq/ipu1/IpuAmmu.cfgr+jZj"$jbj!jdjjf}r+(jh]ji]jj]jk]jn]ujpMYjqhjr]r+j{XGipc_3_43_02_04/examples/DRA7XX_linux_elf/ex02_messageq/ipu1/IpuAmmu.cfgr+r+}r+(jYj+jZj+ubaubj)r+}r+(jYXs/*********************** Large Pages *************************/ /* Instruction Code: Large page (512M); cacheable */ /* config large page[0] to map 512MB VA 0x0 to L3 0x0 */ AMMU.largePages[0].pageEnabled = AMMU.Enable_YES; AMMU.largePages[0].logicalAddress = 0x0; AMMU.largePages[0].translationEnabled = AMMU.Enable_NO; AMMU.largePages[0].size = AMMU.Large_512M; AMMU.largePages[0].L1_cacheable = AMMU.CachePolicy_CACHEABLE; AMMU.largePages[0].L1_posted = AMMU.PostedPolicy_POSTED; /* Peripheral regions: Large Page (512M); non-cacheable */ /* config large page[1] to map 512MB VA 0x60000000 to L3 0x60000000 */ AMMU.largePages[1].pageEnabled = AMMU.Enable_YES; AMMU.largePages[1].logicalAddress = 0x60000000; AMMU.largePages[1].translationEnabled = AMMU.Enable_NO; AMMU.largePages[1].size = AMMU.Large_512M; AMMU.largePages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE; AMMU.largePages[1].L1_posted = AMMU.PostedPolicy_POSTED; /* Private, Shared and IPC Data regions: Large page (512M); cacheable */ /* config large page[2] to map 512MB VA 0x80000000 to L3 0x80000000 */ AMMU.largePages[2].pageEnabled = AMMU.Enable_YES; AMMU.largePages[2].logicalAddress = 0x80000000; AMMU.largePages[2].translationEnabled = AMMU.Enable_NO; AMMU.largePages[2].size = AMMU.Large_512M; AMMU.largePages[2].L1_cacheable = AMMU.CachePolicy_CACHEABLE; AMMU.largePages[2].L1_posted = AMMU.PostedPolicy_POSTED;jZj"$jbj!jdjjf}r+(jjjk]jj]jh]ji]jn]ujpMjqhjr]r+j{Xs/*********************** Large Pages *************************/ /* Instruction Code: Large page (512M); cacheable */ /* config large page[0] to map 512MB VA 0x0 to L3 0x0 */ AMMU.largePages[0].pageEnabled = AMMU.Enable_YES; AMMU.largePages[0].logicalAddress = 0x0; AMMU.largePages[0].translationEnabled = AMMU.Enable_NO; AMMU.largePages[0].size = AMMU.Large_512M; AMMU.largePages[0].L1_cacheable = AMMU.CachePolicy_CACHEABLE; AMMU.largePages[0].L1_posted = AMMU.PostedPolicy_POSTED; /* Peripheral regions: Large Page (512M); non-cacheable */ /* config large page[1] to map 512MB VA 0x60000000 to L3 0x60000000 */ AMMU.largePages[1].pageEnabled = AMMU.Enable_YES; AMMU.largePages[1].logicalAddress = 0x60000000; AMMU.largePages[1].translationEnabled = AMMU.Enable_NO; AMMU.largePages[1].size = AMMU.Large_512M; AMMU.largePages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE; AMMU.largePages[1].L1_posted = AMMU.PostedPolicy_POSTED; /* Private, Shared and IPC Data regions: Large page (512M); cacheable */ /* config large page[2] to map 512MB VA 0x80000000 to L3 0x80000000 */ AMMU.largePages[2].pageEnabled = AMMU.Enable_YES; AMMU.largePages[2].logicalAddress = 0x80000000; AMMU.largePages[2].translationEnabled = AMMU.Enable_NO; AMMU.largePages[2].size = AMMU.Large_512M; AMMU.largePages[2].L1_cacheable = AMMU.CachePolicy_CACHEABLE; AMMU.largePages[2].L1_posted = AMMU.PostedPolicy_POSTED;r+r+}r+(jYUjZj+ubaubjZ)r+}r+(jYUjZj"$jbj!jdj]jf}r+(jh]ji]jj]jk]jn]ujpMyjqhjr]r+j`)r+}r+(jYUjcKjZj+jbj!jdjpjf}r+(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubcdocutils.nodes transition r+)r+}r+(jYX````r+jZj"$jbj!jdU transitionr+jf}r+(jh]ji]jj]jk]jn]ujpM{jqhjr]ubjd$)r+}r+(jYUjZj"$jbj!jdjg$jf}r+(jh]ji]jj]jk]jn]ujpNjqhjr]r+jj$)r+}r+(jYUjf}r+(jk]jj]jh]ji]jn]UcolsKujZj+jr]r+(jo$)r+}r+(jYUjf}r+(jk]jj]jh]ji]jn]UcolwidthKujZj+jr]jdjs$ubjo$)r+}r+(jYUjf}r+(jk]jj]jh]ji]jn]UcolwidthKujZj+jr]jdjs$ubjo$)r+}r+(jYUjf}r+(jk]jj]jh]ji]jn]UcolwidthKujZj+jr]jdjs$ubjo$)r+}r+(jYUjf}r+(jk]jj]jh]ji]jn]UcolwidthKujZj+jr]jdjs$ubjo$)r+}r+(jYUjf}r+(jk]jj]jh]ji]jn]UcolwidthK ujZj+jr]jdjs$ubjz$)r+}r+(jYUjf}r+(jh]ji]jj]jk]jn]ujZj+jr]r+j$)r+}r+(jYUjf}r+(jh]ji]jj]jk]jn]ujZj+jr]r+(j$)r+}r+(jYUjf}r+(jh]ji]jj]jk]jn]ujZj+jr]r+j)r+}r+(jYXPager+jZj+jbj!jdjjf}r+(jh]ji]jj]jk]jn]ujpM~jr]r+j{XPager+r+}r+(jYj+jZj+ubaubajdj$ubj$)r+}r+(jYUjf}r+(jh]ji]jj]jk]jn]ujZj+jr]r+j)r+}r+(jYXCortex M4 Addressr+jZj+jbj!jdjjf}r+(jh]ji]jj]jk]jn]ujpM~jr]r+j{XCortex M4 Addressr+r+}r+(jYj+jZj+ubaubajdj$ubj$)r+}r+(jYUjf}r+(jh]ji]jj]jk]jn]ujZj+jr]r+j)r+}r+(jYXIntermediate Addressr+jZj+jbj!jdjjf}r+(jh]ji]jj]jk]jn]ujpM~jr]r+j{XIntermediate Addressr+r+}r+(jYj+jZj+ubaubajdj$ubj$)r+}r+(jYUjf}r+(jh]ji]jj]jk]jn]ujZj+jr]r+j)r+}r+(jYXSizer+jZj+jbj!jdjjf}r+(jh]ji]jj]jk]jn]ujpM~jr]r+j{XSizer+r+}r+(jYj+jZj+ubaubajdj$ubj$)r+}r+(jYUjf}r+(jh]ji]jj]jk]jn]ujZj+jr]r+j)r+}r+(jYXCommentr+jZj+jbj!jdjjf}r+(jh]ji]jj]jk]jn]ujpM~jr]r+j{XCommentr+r,}r,(jYj+jZj+ubaubajdj$ubejdj$ubajdj$ubj$)r,}r,(jYUjf}r,(jh]ji]jj]jk]jn]ujZj+jr]r,(j$)r,}r,(jYUjf}r,(jh]ji]jj]jk]jn]ujZj,jr]r ,(j$)r ,}r ,(jYUjf}r ,(jh]ji]jj]jk]jn]ujZj,jr]r ,j)r,}r,(jYX Large Page 0r,jZj ,jbj!jdjjf}r,(jh]ji]jj]jk]jn]ujpMjr]r,j{X Large Page 0r,r,}r,(jYj,jZj,ubaubajdj$ubj$)r,}r,(jYUjf}r,(jh]ji]jj]jk]jn]ujZj,jr]r,j)r,}r,(jYX0x00000000-0x1fffffffr,jZj,jbj!jdjjf}r,(jh]ji]jj]jk]jn]ujpMjr]r,j{X0x00000000-0x1fffffffr,r ,}r!,(jYj,jZj,ubaubajdj$ubj$)r",}r#,(jYUjf}r$,(jh]ji]jj]jk]jn]ujZj,jr]r%,j)r&,}r',(jYX0x00000000-0x1fffffffr(,jZj",jbj!jdjjf}r),(jh]ji]jj]jk]jn]ujpMjr]r*,j{X0x00000000-0x1fffffffr+,r,,}r-,(jYj(,jZj&,ubaubajdj$ubj$)r.,}r/,(jYUjf}r0,(jh]ji]jj]jk]jn]ujZj,jr]r1,j)r2,}r3,(jYX512 MBr4,jZj.,jbj!jdjjf}r5,(jh]ji]jj]jk]jn]ujpMjr]r6,j{X512 MBr7,r8,}r9,(jYj4,jZj2,ubaubajdj$ubj$)r:,}r;,(jYUjf}r<,(jh]ji]jj]jk]jn]ujZj,jr]r=,j)r>,}r?,(jYXCoder@,jZj:,jbj!jdjjf}rA,(jh]ji]jj]jk]jn]ujpMjr]rB,j{XCoderC,rD,}rE,(jYj@,jZj>,ubaubajdj$ubejdj$ubj$)rF,}rG,(jYUjf}rH,(jh]ji]jj]jk]jn]ujZj,jr]rI,(j$)rJ,}rK,(jYUjf}rL,(jh]ji]jj]jk]jn]ujZjF,jr]rM,j)rN,}rO,(jYX Large Page 1rP,jZjJ,jbj!jdjjf}rQ,(jh]ji]jj]jk]jn]ujpMjr]rR,j{X Large Page 1rS,rT,}rU,(jYjP,jZjN,ubaubajdj$ubj$)rV,}rW,(jYUjf}rX,(jh]ji]jj]jk]jn]ujZjF,jr]rY,j)rZ,}r[,(jYX0x60000000-0x7fffffffr\,jZjV,jbj!jdjjf}r],(jh]ji]jj]jk]jn]ujpMjr]r^,j{X0x60000000-0x7fffffffr_,r`,}ra,(jYj\,jZjZ,ubaubajdj$ubj$)rb,}rc,(jYUjf}rd,(jh]ji]jj]jk]jn]ujZjF,jr]re,j)rf,}rg,(jYX0x60000000-0x7fffffffrh,jZjb,jbj!jdjjf}ri,(jh]ji]jj]jk]jn]ujpMjr]rj,j{X0x60000000-0x7fffffffrk,rl,}rm,(jYjh,jZjf,ubaubajdj$ubj$)rn,}ro,(jYUjf}rp,(jh]ji]jj]jk]jn]ujZjF,jr]rq,j)rr,}rs,(jYX512 MBrt,jZjn,jbj!jdjjf}ru,(jh]ji]jj]jk]jn]ujpMjr]rv,j{X512 MBrw,rx,}ry,(jYjt,jZjr,ubaubajdj$ubj$)rz,}r{,(jYUjf}r|,(jh]ji]jj]jk]jn]ujZjF,jr]r},j)r~,}r,(jYX Peripheralsr,jZjz,jbj!jdjjf}r,(jh]ji]jj]jk]jn]ujpMjr]r,j{X Peripheralsr,r,}r,(jYj,jZj~,ubaubajdj$ubejdj$ubj$)r,}r,(jYUjf}r,(jh]ji]jj]jk]jn]ujZj,jr]r,(j$)r,}r,(jYUjf}r,(jh]ji]jj]jk]jn]ujZj,jr]r,j)r,}r,(jYX Large Page 2r,jZj,jbj!jdjjf}r,(jh]ji]jj]jk]jn]ujpMjr]r,j{X Large Page 2r,r,}r,(jYj,jZj,ubaubajdj$ubj$)r,}r,(jYUjf}r,(jh]ji]jj]jk]jn]ujZj,jr]r,j)r,}r,(jYX0x80000000-0x9fffffffr,jZj,jbj!jdjjf}r,(jh]ji]jj]jk]jn]ujpMjr]r,j{X0x80000000-0x9fffffffr,r,}r,(jYj,jZj,ubaubajdj$ubj$)r,}r,(jYUjf}r,(jh]ji]jj]jk]jn]ujZj,jr]r,j)r,}r,(jYX0x80000000-0x9fffffffr,jZj,jbj!jdjjf}r,(jh]ji]jj]jk]jn]ujpMjr]r,j{X0x80000000-0x9fffffffr,r,}r,(jYj,jZj,ubaubajdj$ubj$)r,}r,(jYUjf}r,(jh]ji]jj]jk]jn]ujZj,jr]r,j)r,}r,(jYX512 MBr,jZj,jbj!jdjjf}r,(jh]ji]jj]jk]jn]ujpMjr]r,j{X512 MBr,r,}r,(jYj,jZj,ubaubajdj$ubj$)r,}r,(jYUjf}r,(jh]ji]jj]jk]jn]ujZj,jr]r,j)r,}r,(jYXDatar,jZj,jbj!jdjjf}r,(jh]ji]jj]jk]jn]ujpMjr]r,j{XDatar,r,}r,(jYj,jZj,ubaubajdj$ubejdj$ubejdjy%ubejdjz%ubaubj)r,}r,(jYXThese 3 pages are "identity" mappings, performing a passthrough of requests to the associated address ranges. These intermediate addresses get mapped to their physical addresses in the next level of translation (IOMMU).r,jZj"$jbj!jdjjf}r,(jh]ji]jj]jk]jn]ujpMjqhjr]r,j{XThese 3 pages are "identity" mappings, performing a passthrough of requests to the associated address ranges. These intermediate addresses get mapped to their physical addresses in the next level of translation (IOMMU).r,r,}r,(jYj,jZj,ubaubj)r,}r,(jYXThe AMMU ranges for code and data *need* to be identity mappings because otherwise the remoteproc loader wouldn't be able to match up the sections from the ELF file with the associated IOMMU mapping. These mappings should suffice for any application, i.e. no need to adjust these. The more likely area for modification is the resource table in the next section. The AMMU mappings are needed mainly to understand the full picture with respect to the Cortex M4 memory map.jZj"$jbj!jdjjf}r,(jh]ji]jj]jk]jn]ujpMjqhjr]r,(j{X"The AMMU ranges for code and data r,r,}r,(jYX"The AMMU ranges for code and data jZj,ubj')r,}r,(jYX*need*jf}r,(jh]ji]jj]jk]jn]ujZj,jr]r,j{Xneedr,r,}r,(jYUjZj,ubajdj'ubj{X to be identity mappings because otherwise the remoteproc loader wouldn't be able to match up the sections from the ELF file with the associated IOMMU mapping. These mappings should suffice for any application, i.e. no need to adjust these. The more likely area for modification is the resource table in the next section. The AMMU mappings are needed mainly to understand the full picture with respect to the Cortex M4 memory map.r,r,}r,(jYX to be identity mappings because otherwise the remoteproc loader wouldn't be able to match up the sections from the ELF file with the associated IOMMU mapping. These mappings should suffice for any application, i.e. no need to adjust these. The more likely area for modification is the resource table in the next section. The AMMU mappings are needed mainly to understand the full picture with respect to the Cortex M4 memory map.jZj,ubeubjZ)r,}r,(jYUjZj"$jbj!jdj]jf}r,(jh]ji]jj]jk]jn]ujpMjqhjr]r,j`)r,}r,(jYUjcKjZj,jbj!jdjpjf}r,(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r,}r,(jYXIOMMUr,jZj"$jbj!jdjjf}r,(jk]r,Uiommur,ajj]jh]ji]jn]r,haaujpNjqhjr]r,j{XIOMMUr,r,}r,(jYj,jZj,ubaubj)r,}r,(jYXThe IOMMU sits closest to the L3 interconnect. It takes the intermediate address output from the AMMU and translates it to the physical address used by the L3 interconnect. The IOMMU is programmed by the ARM based on the associated resource table. If you're planning any memory changes then you'll want to make a custom resource table as described in the wiki page `IPC Resource customTable `__.jZj"$jbj!jdjjf}r,(jh]ji]jj]jk]jn]ujpMjqhjr]r,(j{XmThe IOMMU sits closest to the L3 interconnect. It takes the intermediate address output from the AMMU and translates it to the physical address used by the L3 interconnect. The IOMMU is programmed by the ARM based on the associated resource table. If you're planning any memory changes then you'll want to make a custom resource table as described in the wiki page r,r,}r,(jYXmThe IOMMU sits closest to the L3 interconnect. It takes the intermediate address output from the AMMU and translates it to the physical address used by the L3 interconnect. The IOMMU is programmed by the ARM based on the associated resource table. If you're planning any memory changes then you'll want to make a custom resource table as described in the wiki page jZj,ubj)r,}r,(jYXW`IPC Resource customTable `__jf}r,(UnameXIPC Resource customTablejX8index_Foundational_Components.html#resource-custom-tablejk]jj]jh]ji]jn]ujZj,jr]r,j{XIPC Resource customTabler,r,}r,(jYUjZj,ubajdjubj{X.r,}r-(jYX.jZj,ubeubj)r-}r-(jYXgThe default resource table (which can be adapted to make a custom table) can be found at this location:r-jZj"$jbj!jdjjf}r-(jh]ji]jj]jk]jn]ujpMjqhjr]r-j{XgThe default resource table (which can be adapted to make a custom table) can be found at this location:r-r-}r-(jYj-jZj-ubaubj)r -}r -(jYX3ipc/packages/ti/ipc/remoteproc/rsc_table_vayu_ipu.hr -jZj"$jbj!jdjjf}r -(jh]ji]jj]jk]jn]ujpMjqhjr]r -j{X3ipc/packages/ti/ipc/remoteproc/rsc_table_vayu_ipu.hr-r-}r-(jYj -jZj -ubaubj)r-}r-(jYX#define IPU_MEM_TEXT 0x0 #define IPU_MEM_DATA 0x80000000 #define IPU_MEM_IOBUFS 0x90000000 #define IPU_MEM_IPC_DATA 0x9F000000 #define IPU_MEM_IPC_VRING 0x60000000 #define IPU_MEM_RPMSG_VRING0 0x60000000 #define IPU_MEM_RPMSG_VRING1 0x60004000 #define IPU_MEM_VRING_BUFS0 0x60040000 #define IPU_MEM_VRING_BUFS1 0x60080000 #define IPU_MEM_IPC_VRING_SIZE SZ_1M #define IPU_MEM_IPC_DATA_SIZE SZ_1M #if defined(VAYU_IPU_1) #define IPU_MEM_TEXT_SIZE (SZ_1M) #elif defined(VAYU_IPU_2) #define IPU_MEM_TEXT_SIZE (SZ_1M * 6) #endif #if defined(VAYU_IPU_1) #define IPU_MEM_DATA_SIZE (SZ_1M * 5) #elif defined(VAYU_IPU_2) #define IPU_MEM_DATA_SIZE (SZ_1M * 48) #endifjZj"$jbj!jdjjf}r-(jjXcjjjk]jj]jh]j }ji]jn]ujpMjqhjr]r-j{X#define IPU_MEM_TEXT 0x0 #define IPU_MEM_DATA 0x80000000 #define IPU_MEM_IOBUFS 0x90000000 #define IPU_MEM_IPC_DATA 0x9F000000 #define IPU_MEM_IPC_VRING 0x60000000 #define IPU_MEM_RPMSG_VRING0 0x60000000 #define IPU_MEM_RPMSG_VRING1 0x60004000 #define IPU_MEM_VRING_BUFS0 0x60040000 #define IPU_MEM_VRING_BUFS1 0x60080000 #define IPU_MEM_IPC_VRING_SIZE SZ_1M #define IPU_MEM_IPC_DATA_SIZE SZ_1M #if defined(VAYU_IPU_1) #define IPU_MEM_TEXT_SIZE (SZ_1M) #elif defined(VAYU_IPU_2) #define IPU_MEM_TEXT_SIZE (SZ_1M * 6) #endif #if defined(VAYU_IPU_1) #define IPU_MEM_DATA_SIZE (SZ_1M * 5) #elif defined(VAYU_IPU_2) #define IPU_MEM_DATA_SIZE (SZ_1M * 48) #endifr-r-}r-(jYUjZj-ubaubjZ)r-}r-(jYUjZj"$jbj!jdj]jf}r-(jh]ji]jj]jk]jn]ujpMjqhjr]r-j`)r-}r-(jYUjcKjZj-jbj!jdjpjf}r-(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r-}r -(jYX r!-jZj"$jbj!jdjjf}r"-(jh]ji]jj]jk]jn]ujpMjqhjr]r#-j{X r$-r%-}r&-(jYj!-jZj-ubaubj)r'-}r(-(jYX{ TYPE_CARVEOUT, IPU_MEM_TEXT, 0, IPU_MEM_TEXT_SIZE, 0, 0, "IPU_MEM_TEXT", }, { TYPE_CARVEOUT, IPU_MEM_DATA, 0, IPU_MEM_DATA_SIZE, 0, 0, "IPU_MEM_DATA", }, { TYPE_CARVEOUT, IPU_MEM_IPC_DATA, 0, IPU_MEM_IPC_DATA_SIZE, 0, 0, "IPU_MEM_IPC_DATA", },jZj"$jbj!jdjjf}r)-(jjXcjjjk]jj]jh]j }ji]jn]ujpMjqhjr]r*-j{X{ TYPE_CARVEOUT, IPU_MEM_TEXT, 0, IPU_MEM_TEXT_SIZE, 0, 0, "IPU_MEM_TEXT", }, { TYPE_CARVEOUT, IPU_MEM_DATA, 0, IPU_MEM_DATA_SIZE, 0, 0, "IPU_MEM_DATA", }, { TYPE_CARVEOUT, IPU_MEM_IPC_DATA, 0, IPU_MEM_IPC_DATA_SIZE, 0, 0, "IPU_MEM_IPC_DATA", },r+-r,-}r--(jYUjZj'-ubaubjZ)r.-}r/-(jYUjZj"$jbj!jdj]jf}r0-(jh]ji]jj]jk]jn]ujpMjqhjr]r1-j`)r2-}r3-(jYUjcKjZj.-jbj!jdjpjf}r4-(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r5-}r6-(jYXThe 3 entries above from the resource table all come from the associated IPU CMA pool (i.e. as dictated by the TYPE_CARVEOUT). The second parameter represents the virtual address (i.e. input address to the IOMMU). **These addresses must be consistent with both the AMMU mapping as well as the linker command file.** The ex02_messageq example from ipc defines these memory sections in the file examples/DRA7XX_linux_elf/ex02_messageq/shared/config.bld.jZj"$jbj!jdjjf}r7-(jh]ji]jj]jk]jn]ujpMjqhjr]r8-(j{XThe 3 entries above from the resource table all come from the associated IPU CMA pool (i.e. as dictated by the TYPE_CARVEOUT). The second parameter represents the virtual address (i.e. input address to the IOMMU). r9-r:-}r;-(jYXThe 3 entries above from the resource table all come from the associated IPU CMA pool (i.e. as dictated by the TYPE_CARVEOUT). The second parameter represents the virtual address (i.e. input address to the IOMMU). jZj5-ubj)r<-}r=-(jYXe**These addresses must be consistent with both the AMMU mapping as well as the linker command file.**jf}r>-(jh]ji]jj]jk]jn]ujZj5-jr]r?-j{XaThese addresses must be consistent with both the AMMU mapping as well as the linker command file.r@-rA-}rB-(jYUjZj<-ubajdjubj{X The ex02_messageq example from ipc defines these memory sections in the file examples/DRA7XX_linux_elf/ex02_messageq/shared/config.bld.rC-rD-}rE-(jYX The ex02_messageq example from ipc defines these memory sections in the file examples/DRA7XX_linux_elf/ex02_messageq/shared/config.bld.jZj5-ubeubj)rF-}rG-(jYXCYou can dump the IPU IOMMU page tables with the following commands:rH-jZj"$jbj!jdjjf}rI-(jh]ji]jj]jk]jn]ujpMjqhjr]rJ-j{XCYou can dump the IPU IOMMU page tables with the following commands:rK-rL-}rM-(jYjH-jZjF-ubaubjd$)rN-}rO-(jYUjZj"$jbj!jdjg$jf}rP-(jh]ji]jj]jk]jn]ujpNjqhjr]rQ-jj$)rR-}rS-(jYUjf}rT-(jk]jj]jh]ji]jn]UcolsKujZjN-jr]rU-(jo$)rV-}rW-(jYUjf}rX-(jk]jj]jh]ji]jn]UcolwidthKujZjR-jr]jdjs$ubjo$)rY-}rZ-(jYUjf}r[-(jk]jj]jh]ji]jn]UcolwidthK9ujZjR-jr]jdjs$ubjz$)r\-}r]-(jYUjf}r^-(jh]ji]jj]jk]jn]ujZjR-jr]r_-j$)r`-}ra-(jYUjf}rb-(jh]ji]jj]jk]jn]ujZj\-jr]rc-(j$)rd-}re-(jYUjf}rf-(jh]ji]jj]jk]jn]ujZj`-jr]rg-j)rh-}ri-(jYXIPUrj-jZjd-jbj!jdjjf}rk-(jh]ji]jj]jk]jn]ujpMjr]rl-j{XIPUrm-rn-}ro-(jYjj-jZjh-ubaubajdj$ubj$)rp-}rq-(jYUjf}rr-(jh]ji]jj]jk]jn]ujZj`-jr]rs-j)rt-}ru-(jYXCommandrv-jZjp-jbj!jdjjf}rw-(jh]ji]jj]jk]jn]ujpMjr]rx-j{XCommandry-rz-}r{-(jYjv-jZjt-ubaubajdj$ubejdj$ubajdj$ubj$)r|-}r}-(jYUjf}r~-(jh]ji]jj]jk]jn]ujZjR-jr]r-(j$)r-}r-(jYUjf}r-(jh]ji]jj]jk]jn]ujZj|-jr]r-(j$)r-}r-(jYUjf}r-(jh]ji]jj]jk]jn]ujZj-jr]r-j)r-}r-(jYXIPU1r-jZj-jbj!jdjjf}r-(jh]ji]jj]jk]jn]ujpMjr]r-j{XIPU1r-r-}r-(jYj-jZj-ubaubajdj$ubj$)r-}r-(jYUjf}r-(jh]ji]jj]jk]jn]ujZj-jr]r-j)r-}r-(jYX7cat /sys/kernel/debug/omap_iommu/58882000.mmu/pagetabler-jZj-jbj!jdjjf}r-(jh]ji]jj]jk]jn]ujpMjr]r-j{X7cat /sys/kernel/debug/omap_iommu/58882000.mmu/pagetabler-r-}r-(jYj-jZj-ubaubajdj$ubejdj$ubj$)r-}r-(jYUjf}r-(jh]ji]jj]jk]jn]ujZj|-jr]r-(j$)r-}r-(jYUjf}r-(jh]ji]jj]jk]jn]ujZj-jr]r-j)r-}r-(jYXIPU2r-jZj-jbj!jdjjf}r-(jh]ji]jj]jk]jn]ujpMjr]r-j{XIPU2r-r-}r-(jYj-jZj-ubaubajdj$ubj$)r-}r-(jYUjf}r-(jh]ji]jj]jk]jn]ujZj-jr]r-j)r-}r-(jYX7cat /sys/kernel/debug/omap_iommu/55082000.mmu/pagetabler-jZj-jbj!jdjjf}r-(jh]ji]jj]jk]jn]ujpMjr]r-j{X7cat /sys/kernel/debug/omap_iommu/55082000.mmu/pagetabler-r-}r-(jYj-jZj-ubaubajdj$ubejdj$ubejdjy%ubejdjz%ubaubj)r-}r-(jYXPlease see the `corresponding DSP documentation `__ for more details on interpreting the output.jZj"$jbj!jdjjf}r-(jh]ji]jj]jk]jn]ujpMjqhjr]r-(j{XPlease see the r-r-}r-(jYXPlease see the jZj-ubj)r-}r-(jYXu`corresponding DSP documentation `__jf}r-(UnameXcorresponding DSP documentationjXO/index.php/Linux_IPC_on_AM57xx#Inspecting_the_DSP_IOMMU_Page_Tables_at_Run-Timejk]jj]jh]ji]jn]ujZj-jr]r-j{Xcorresponding DSP documentationr-r-}r-(jYUjZj-ubajdjubj{X- for more details on interpreting the output.r-r-}r-(jYX- for more details on interpreting the output.jZj-ubeubjZ)r-}r-(jYUjZj"$jbj!jdj]jf}r-(jh]ji]jj]jk]jn]ujpMjqhjr]r-j`)r-}r-(jYUjcKjZj-jbj!jdjpjf}r-(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r-}r-(jYX#Cortex M4 IPU Access to Peripheralsr-jZj"$jbj!jdjjf}r-(jk]r-U#cortex-m4-ipu-access-to-peripheralsr-ajj]jh]ji]jn]r-haujpNjqhjr]r-j{X#Cortex M4 IPU Access to Peripheralsr-r-}r-(jYj-jZj-ubaubj)r-}r-(jYX:The default resource table creates the following mappings:r-jZj"$jbj!jdjjf}r-(jh]ji]jj]jk]jn]ujpMjqhjr]r-j{X:The default resource table creates the following mappings:r-r-}r-(jYj-jZj-ubaubjd$)r-}r-(jYUjZj"$jbj!jdjg$jf}r-(jh]ji]jj]jk]jn]ujpNjqhjr]r-jj$)r-}r-(jYUjf}r-(jk]jj]jh]ji]jn]UcolsKujZj-jr]r-(jo$)r-}r-(jYUjf}r-(jk]jj]jh]ji]jn]UcolwidthK ujZj-jr]jdjs$ubjo$)r-}r-(jYUjf}r-(jk]jj]jh]ji]jn]UcolwidthK ujZj-jr]jdjs$ubjo$)r-}r-(jYUjf}r-(jk]jj]jh]ji]jn]UcolwidthK ujZj-jr]jdjs$ubjo$)r-}r-(jYUjf}r-(jk]jj]jh]ji]jn]UcolwidthK ujZj-jr]jdjs$ubjo$)r-}r-(jYUjf}r-(jk]jj]jh]ji]jn]UcolwidthK ujZj-jr]jdjs$ubjz$)r-}r-(jYUjf}r-(jh]ji]jj]jk]jn]ujZj-jr]r-j$)r-}r-(jYUjf}r.(jh]ji]jj]jk]jn]ujZj-jr]r.(j$)r.}r.(jYUjf}r.(jh]ji]jj]jk]jn]ujZj-jr]r.j)r.}r.(jYX!Virtual Address used by Cortex M4r.jZj.jbj!jdjjf}r .(jh]ji]jj]jk]jn]ujpMjr]r .j{X!Virtual Address used by Cortex M4r .r .}r .(jYj.jZj.ubaubajdj$ubj$)r.}r.(jYUjf}r.(jh]ji]jj]jk]jn]ujZj-jr]r.j)r.}r.(jYX!Address at output of Unicache MMUr.jZj.jbj!jdjjf}r.(jh]ji]jj]jk]jn]ujpMjr]r.j{X!Address at output of Unicache MMUr.r.}r.(jYj.jZj.ubaubajdj$ubj$)r.}r.(jYUjf}r.(jh]ji]jj]jk]jn]ujZj-jr]r.j)r.}r.(jYXAddress at output of IOMMUr .jZj.jbj!jdjjf}r!.(jh]ji]jj]jk]jn]ujpMjr]r".j{XAddress at output of IOMMUr#.r$.}r%.(jYj .jZj.ubaubajdj$ubj$)r&.}r'.(jYUjf}r(.(jh]ji]jj]jk]jn]ujZj-jr]r).j)r*.}r+.(jYXSizer,.jZj&.jbj!jdjjf}r-.(jh]ji]jj]jk]jn]ujpMjr]r..j{XSizer/.r0.}r1.(jYj,.jZj*.ubaubajdj$ubj$)r2.}r3.(jYUjf}r4.(jh]ji]jj]jk]jn]ujZj-jr]r5.j)r6.}r7.(jYXCommentr8.jZj2.jbj!jdjjf}r9.(jh]ji]jj]jk]jn]ujpMjr]r:.j{XCommentr;.r<.}r=.(jYj8.jZj6.ubaubajdj$ubejdj$ubajdj$ubj$)r>.}r?.(jYUjf}r@.(jh]ji]jj]jk]jn]ujZj-jr]rA.(j$)rB.}rC.(jYUjf}rD.(jh]ji]jj]jk]jn]ujZj>.jr]rE.(j$)rF.}rG.(jYUjf}rH.(jh]ji]jj]jk]jn]ujZjB.jr]rI.j)rJ.}rK.(jYX 0x6A000000rL.jZjF.jbj!jdjjf}rM.(jh]ji]jj]jk]jn]ujpMjr]rN.j{X 0x6A000000rO.rP.}rQ.(jYjL.jZjJ.ubaubajdj$ubj$)rR.}rS.(jYUjf}rT.(jh]ji]jj]jk]jn]ujZjB.jr]rU.j)rV.}rW.(jYX 0x6A000000rX.jZjR.jbj!jdjjf}rY.(jh]ji]jj]jk]jn]ujpMjr]rZ.j{X 0x6A000000r[.r\.}r].(jYjX.jZjV.ubaubajdj$ubj$)r^.}r_.(jYUjf}r`.(jh]ji]jj]jk]jn]ujZjB.jr]ra.j)rb.}rc.(jYX 0x4A000000rd.jZj^.jbj!jdjjf}re.(jh]ji]jj]jk]jn]ujpMjr]rf.j{X 0x4A000000rg.rh.}ri.(jYjd.jZjb.ubaubajdj$ubj$)rj.}rk.(jYUjf}rl.(jh]ji]jj]jk]jn]ujZjB.jr]rm.j)rn.}ro.(jYX16 MBrp.jZjj.jbj!jdjjf}rq.(jh]ji]jj]jk]jn]ujpMjr]rr.j{X16 MBrs.rt.}ru.(jYjp.jZjn.ubaubajdj$ubj$)rv.}rw.(jYUjf}rx.(jh]ji]jj]jk]jn]ujZjB.jr]ry.j)rz.}r{.(jYXL4CFG + L4WKUPr|.jZjv.jbj!jdjjf}r}.(jh]ji]jj]jk]jn]ujpMjr]r~.j{XL4CFG + L4WKUPr.r.}r.(jYj|.jZjz.ubaubajdj$ubejdj$ubj$)r.}r.(jYUjf}r.(jh]ji]jj]jk]jn]ujZj>.jr]r.(j$)r.}r.(jYUjf}r.(jh]ji]jj]jk]jn]ujZj.jr]r.j)r.}r.(jYX 0x68000000r.jZj.jbj!jdjjf}r.(jh]ji]jj]jk]jn]ujpMjr]r.j{X 0x68000000r.r.}r.(jYj.jZj.ubaubajdj$ubj$)r.}r.(jYUjf}r.(jh]ji]jj]jk]jn]ujZj.jr]r.j)r.}r.(jYX 0x68000000r.jZj.jbj!jdjjf}r.(jh]ji]jj]jk]jn]ujpMjr]r.j{X 0x68000000r.r.}r.(jYj.jZj.ubaubajdj$ubj$)r.}r.(jYUjf}r.(jh]ji]jj]jk]jn]ujZj.jr]r.j)r.}r.(jYX 0x48000000r.jZj.jbj!jdjjf}r.(jh]ji]jj]jk]jn]ujpMjr]r.j{X 0x48000000r.r.}r.(jYj.jZj.ubaubajdj$ubj$)r.}r.(jYUjf}r.(jh]ji]jj]jk]jn]ujZj.jr]r.j)r.}r.(jYX2 MBr.jZj.jbj!jdjjf}r.(jh]ji]jj]jk]jn]ujpMjr]r.j{X2 MBr.r.}r.(jYj.jZj.ubaubajdj$ubj$)r.}r.(jYUjf}r.(jh]ji]jj]jk]jn]ujZj.jr]r.j)r.}r.(jYXL4PER1r.jZj.jbj!jdjjf}r.(jh]ji]jj]jk]jn]ujpMjr]r.j{XL4PER1r.r.}r.(jYj.jZj.ubaubajdj$ubejdj$ubj$)r.}r.(jYUjf}r.(jh]ji]jj]jk]jn]ujZj>.jr]r.(j$)r.}r.(jYUjf}r.(jh]ji]jj]jk]jn]ujZj.jr]r.j)r.}r.(jYX 0x68400000r.jZj.jbj!jdjjf}r.(jh]ji]jj]jk]jn]ujpMjr]r.j{X 0x68400000r.r.}r.(jYj.jZj.ubaubajdj$ubj$)r.}r.(jYUjf}r.(jh]ji]jj]jk]jn]ujZj.jr]r.j)r.}r.(jYX 0x68400000r.jZj.jbj!jdjjf}r.(jh]ji]jj]jk]jn]ujpMjr]r.j{X 0x68400000r.r.}r.(jYj.jZj.ubaubajdj$ubj$)r.}r.(jYUjf}r.(jh]ji]jj]jk]jn]ujZj.jr]r.j)r.}r.(jYX 0x48400000r.jZj.jbj!jdjjf}r.(jh]ji]jj]jk]jn]ujpMjr]r.j{X 0x48400000r.r.}r.(jYj.jZj.ubaubajdj$ubj$)r.}r.(jYUjf}r.(jh]ji]jj]jk]jn]ujZj.jr]r.j)r.}r.(jYX4 MBr.jZj.jbj!jdjjf}r.(jh]ji]jj]jk]jn]ujpMjr]r.j{X4 MBr.r.}r.(jYj.jZj.ubaubajdj$ubj$)r.}r.(jYUjf}r.(jh]ji]jj]jk]jn]ujZj.jr]r.j)r.}r.(jYXL4PER2r.jZj.jbj!jdjjf}r.(jh]ji]jj]jk]jn]ujpMjr]r.j{XL4PER2r.r/}r/(jYj.jZj.ubaubajdj$ubejdj$ubj$)r/}r/(jYUjf}r/(jh]ji]jj]jk]jn]ujZj>.jr]r/(j$)r/}r/(jYUjf}r/(jh]ji]jj]jk]jn]ujZj/jr]r /j)r /}r /(jYX 0x68800000r /jZj/jbj!jdjjf}r /(jh]ji]jj]jk]jn]ujpMjr]r/j{X 0x68800000r/r/}r/(jYj /jZj /ubaubajdj$ubj$)r/}r/(jYUjf}r/(jh]ji]jj]jk]jn]ujZj/jr]r/j)r/}r/(jYX 0x68800000r/jZj/jbj!jdjjf}r/(jh]ji]jj]jk]jn]ujpMjr]r/j{X 0x68800000r/r/}r/(jYj/jZj/ubaubajdj$ubj$)r/}r/(jYUjf}r /(jh]ji]jj]jk]jn]ujZj/jr]r!/j)r"/}r#/(jYX 0x48800000r$/jZj/jbj!jdjjf}r%/(jh]ji]jj]jk]jn]ujpMjr]r&/j{X 0x48800000r'/r(/}r)/(jYj$/jZj"/ubaubajdj$ubj$)r*/}r+/(jYUjf}r,/(jh]ji]jj]jk]jn]ujZj/jr]r-/j)r./}r//(jYX8 MBr0/jZj*/jbj!jdjjf}r1/(jh]ji]jj]jk]jn]ujpMjr]r2/j{X8 MBr3/r4/}r5/(jYj0/jZj./ubaubajdj$ubj$)r6/}r7/(jYUjf}r8/(jh]ji]jj]jk]jn]ujZj/jr]r9/j)r:/}r;/(jYXL4PER3r/j{XL4PER3r?/r@/}rA/(jYj.jr]rE/(j$)rF/}rG/(jYUjf}rH/(jh]ji]jj]jk]jn]ujZjB/jr]rI/j)rJ/}rK/(jYX 0x74000000rL/jZjF/jbj!jdjjf}rM/(jh]ji]jj]jk]jn]ujpMjr]rN/j{X 0x74000000rO/rP/}rQ/(jYjL/jZjJ/ubaubajdj$ubj$)rR/}rS/(jYUjf}rT/(jh]ji]jj]jk]jn]ujZjB/jr]rU/j)rV/}rW/(jYX 0x74000000rX/jZjR/jbj!jdjjf}rY/(jh]ji]jj]jk]jn]ujpMjr]rZ/j{X 0x74000000r[/r\/}r]/(jYjX/jZjV/ubaubajdj$ubj$)r^/}r_/(jYUjf}r`/(jh]ji]jj]jk]jn]ujZjB/jr]ra/j)rb/}rc/(jYX 0x54000000rd/jZj^/jbj!jdjjf}re/(jh]ji]jj]jk]jn]ujpMjr]rf/j{X 0x54000000rg/rh/}ri/(jYjd/jZjb/ubaubajdj$ubj$)rj/}rk/(jYUjf}rl/(jh]ji]jj]jk]jn]ujZjB/jr]rm/j)rn/}ro/(jYX16 MBrp/jZjj/jbj!jdjjf}rq/(jh]ji]jj]jk]jn]ujpMjr]rr/j{X16 MBrs/rt/}ru/(jYjp/jZjn/ubaubajdj$ubj$)rv/}rw/(jYUjf}rx/(jh]ji]jj]jk]jn]ujZjB/jr]ry/j)rz/}r{/(jYXL3_INSTR + CT_TBRr|/jZjv/jbj!jdjjf}r}/(jh]ji]jj]jk]jn]ujpMjr]r~/j{XL3_INSTR + CT_TBRr/r/}r/(jYj|/jZjz/ubaubajdj$ubejdj$ubejdjy%ubejdjz%ubaubj)r/}r/(jYX!Example: Accessing UART5 from IPUr/jZj"$jbj!jdjjf}r/(jh]ji]jj]jk]jn]ujpM jqhjr]r/j{X!Example: Accessing UART5 from IPUr/r/}r/(jYj/jZj/ubaubj%)r/}r/(jYUjZj"$jbj!jdj(jf}r/(j*U.jk]jj]jh]j+Uji]jn]j,j-ujpMjqhjr]r/(j/)r/}r/(jYXFor this example, it's assumed the pin-muxing was already setup in the bootloader. If that's not the case, you would need to do that here.jZj/jbj!jdj2jf}r/(jh]ji]jj]jk]jn]ujpNjqhjr]r/j)r/}r/(jYXFor this example, it's assumed the pin-muxing was already setup in the bootloader. If that's not the case, you would need to do that here.r/jZj/jbj!jdjjf}r/(jh]ji]jj]jk]jn]ujpMjr]r/j{XFor this example, it's assumed the pin-muxing was already setup in the bootloader. If that's not the case, you would need to do that here.r/r/}r/(jYj/jZj/ubaubaubj/)r/}r/(jYX The UART5 module needs to be enabled via the CM_L4PER_UART5_CLKCTRL register. This is located at physical address 0x4A009870. So from the M4 we would program this register at virtual address 0x6A009870. Writing a value of 2 to this register will enable the peripheral.jZj/jbj!jdj2jf}r/(jh]ji]jj]jk]jn]ujpNjqhjr]r/j)r/}r/(jYX The UART5 module needs to be enabled via the CM_L4PER_UART5_CLKCTRL register. This is located at physical address 0x4A009870. So from the M4 we would program this register at virtual address 0x6A009870. Writing a value of 2 to this register will enable the peripheral.r/jZj/jbj!jdjjf}r/(jh]ji]jj]jk]jn]ujpMjr]r/j{X The UART5 module needs to be enabled via the CM_L4PER_UART5_CLKCTRL register. This is located at physical address 0x4A009870. So from the M4 we would program this register at virtual address 0x6A009870. Writing a value of 2 to this register will enable the peripheral.r/r/}r/(jYj/jZj/ubaubaubj/)r/}r/(jYXAfter completing the previous step, the UART5 registers will become accessible. Normally UART5 is accessible at physical base address 0x48066000. This would correspondingly be accessed from the IPU at 0x68066000. jZj/jbj!jdj2jf}r/(jh]ji]jj]jk]jn]ujpNjqhjr]r/j)r/}r/(jYXAfter completing the previous step, the UART5 registers will become accessible. Normally UART5 is accessible at physical base address 0x48066000. This would correspondingly be accessed from the IPU at 0x68066000.r/jZj/jbj!jdjjf}r/(jh]ji]jj]jk]jn]ujpMjr]r/j{XAfter completing the previous step, the UART5 registers will become accessible. Normally UART5 is accessible at physical base address 0x48066000. This would correspondingly be accessed from the IPU at 0x68066000.r/r/}r/(jYj/jZj/ubaubaubeubeubj[)r/}r/(jYUjZj!jbj!jdjejf}r/(jh]ji]jj]jk]r/Upower-managementr/ajn]r/hAaujpMjqhjr]r/(jt)r/}r/(jYXPower Managementr/jZj/jbj!jdjxjf}r/(jh]ji]jj]jk]jn]ujpMjqhjr]r/j{XPower Managementr/r/}r/(jYj/jZj/ubaubj)r/}r/(jYX@The IPUs and DSPs auto-idle by default. This can prevent you from being able to connect to the device using JTAG or from accessing local memory via devmem2. There are some options sprinkled throughout sysfs that are needed in order to force these subsystems on, as is sometimes needed for development and debug purposes.r/jZj/jbj!jdjjf}r/(jh]ji]jj]jk]jn]ujpMjqhjr]r/j{X@The IPUs and DSPs auto-idle by default. This can prevent you from being able to connect to the device using JTAG or from accessing local memory via devmem2. There are some options sprinkled throughout sysfs that are needed in order to force these subsystems on, as is sometimes needed for development and debug purposes.r/r/}r/(jYj/jZj/ubaubj)r/}r/(jYXzThere are some hard-coded device names that originate in the device tree (dra7.dtsi) that are needed for these operations:r/jZj/jbj!jdjjf}r/(jh]ji]jj]jk]jn]ujpM#jqhjr]r/j{XzThere are some hard-coded device names that originate in the device tree (dra7.dtsi) that are needed for these operations:r/r/}r/(jYj/jZj/ubaubjd$)r/}r/(jYUjZj/jbj!jdjg$jf}r/(jh]ji]jj]jk]jn]ujpNjqhjr]r/jj$)r/}r/(jYUjf}r/(jk]jj]jh]ji]jn]UcolsKujZj/jr]r/(jo$)r/}r/(jYUjf}r/(jk]jj]jh]ji]jn]UcolwidthK ujZj/jr]jdjs$ubjo$)r/}r/(jYUjf}r/(jk]jj]jh]ji]jn]UcolwidthKujZj/jr]jdjs$ubjo$)r/}r/(jYUjf}r/(jk]jj]jh]ji]jn]UcolwidthKujZj/jr]jdjs$ubjz$)r/}r/(jYUjf}r/(jh]ji]jj]jk]jn]ujZj/jr]r/j$)r/}r/(jYUjf}r/(jh]ji]jj]jk]jn]ujZj/jr]r/(j$)r/}r/(jYUjf}r/(jh]ji]jj]jk]jn]ujZj/jr]r/j)r/}r/(jYX Remote Corer/jZj/jbj!jdjjf}r/(jh]ji]jj]jk]jn]ujpM'jr]r/j{X Remote Corer/r/}r/(jYj/jZj/ubaubajdj$ubj$)r/}r/(jYUjf}r/(jh]ji]jj]jk]jn]ujZj/jr]r/j)r/}r/(jYXDefinition in dra7.dtsir/jZj/jbj!jdjjf}r/(jh]ji]jj]jk]jn]ujpM'jr]r/j{XDefinition in dra7.dtsir/r0}r0(jYj/jZj/ubaubajdj$ubj$)r0}r0(jYUjf}r0(jh]ji]jj]jk]jn]ujZj/jr]r0j)r0}r0(jYXSystem FS Namer0jZj0jbj!jdjjf}r 0(jh]ji]jj]jk]jn]ujpM'jr]r 0j{XSystem FS Namer 0r 0}r 0(jYj0jZj0ubaubajdj$ubejdj$ubajdj$ubj$)r0}r0(jYUjf}r0(jh]ji]jj]jk]jn]ujZj/jr]r0(j$)r0}r0(jYUjf}r0(jh]ji]jj]jk]jn]ujZj0jr]r0(j$)r0}r0(jYUjf}r0(jh]ji]jj]jk]jn]ujZj0jr]r0j)r0}r0(jYXIPU1r0jZj0jbj!jdjjf}r0(jh]ji]jj]jk]jn]ujpM)jr]r0j{XIPU1r0r 0}r!0(jYj0jZj0ubaubajdj$ubj$)r"0}r#0(jYUjf}r$0(jh]ji]jj]jk]jn]ujZj0jr]r%0j)r&0}r'0(jYX ipu@58820000r(0jZj"0jbj!jdjjf}r)0(jh]ji]jj]jk]jn]ujpM)jr]r*0j)r+0}r,0(jYj(0jf}r-0(UrefuriXmailto:ipu@58820000jk]jj]jh]ji]jn]ujZj&0jr]r.0j{X ipu@58820000r/0r00}r10(jYUjZj+0ubajdjubaubajdj$ubj$)r20}r30(jYUjf}r40(jh]ji]jj]jk]jn]ujZj0jr]r50j)r60}r70(jYX 58820000.ipur80jZj20jbj!jdjjf}r90(jh]ji]jj]jk]jn]ujpM)jr]r:0j{X 58820000.ipur;0r<0}r=0(jYj80jZj60ubaubajdj$ubejdj$ubj$)r>0}r?0(jYUjf}r@0(jh]ji]jj]jk]jn]ujZj0jr]rA0(j$)rB0}rC0(jYUjf}rD0(jh]ji]jj]jk]jn]ujZj>0jr]rE0j)rF0}rG0(jYXIPU2rH0jZjB0jbj!jdjjf}rI0(jh]ji]jj]jk]jn]ujpM+jr]rJ0j{XIPU2rK0rL0}rM0(jYjH0jZjF0ubaubajdj$ubj$)rN0}rO0(jYUjf}rP0(jh]ji]jj]jk]jn]ujZj>0jr]rQ0j)rR0}rS0(jYX ipu@55020000rT0jZjN0jbj!jdjjf}rU0(jh]ji]jj]jk]jn]ujpM+jr]rV0j)rW0}rX0(jYjT0jf}rY0(UrefuriXmailto:ipu@55020000jk]jj]jh]ji]jn]ujZjR0jr]rZ0j{X ipu@55020000r[0r\0}r]0(jYUjZjW0ubajdjubaubajdj$ubj$)r^0}r_0(jYUjf}r`0(jh]ji]jj]jk]jn]ujZj>0jr]ra0j)rb0}rc0(jYX 55020000.ipurd0jZj^0jbj!jdjjf}re0(jh]ji]jj]jk]jn]ujpM+jr]rf0j{X 55020000.ipurg0rh0}ri0(jYjd0jZjb0ubaubajdj$ubejdj$ubj$)rj0}rk0(jYUjf}rl0(jh]ji]jj]jk]jn]ujZj0jr]rm0(j$)rn0}ro0(jYUjf}rp0(jh]ji]jj]jk]jn]ujZjj0jr]rq0j)rr0}rs0(jYXDSP1rt0jZjn0jbj!jdjjf}ru0(jh]ji]jj]jk]jn]ujpM-jr]rv0j{XDSP1rw0rx0}ry0(jYjt0jZjr0ubaubajdj$ubj$)rz0}r{0(jYUjf}r|0(jh]ji]jj]jk]jn]ujZjj0jr]r}0j)r~0}r0(jYX dsp@40800000r0jZjz0jbj!jdjjf}r0(jh]ji]jj]jk]jn]ujpM-jr]r0j)r0}r0(jYj0jf}r0(UrefuriXmailto:dsp@40800000jk]jj]jh]ji]jn]ujZj~0jr]r0j{X dsp@40800000r0r0}r0(jYUjZj0ubajdjubaubajdj$ubj$)r0}r0(jYUjf}r0(jh]ji]jj]jk]jn]ujZjj0jr]r0j)r0}r0(jYX 40800000.dspr0jZj0jbj!jdjjf}r0(jh]ji]jj]jk]jn]ujpM-jr]r0j{X 40800000.dspr0r0}r0(jYj0jZj0ubaubajdj$ubejdj$ubj$)r0}r0(jYUjf}r0(jh]ji]jj]jk]jn]ujZj0jr]r0(j$)r0}r0(jYUjf}r0(jh]ji]jj]jk]jn]ujZj0jr]r0j)r0}r0(jYXDSP2r0jZj0jbj!jdjjf}r0(jh]ji]jj]jk]jn]ujpM/jr]r0j{XDSP2r0r0}r0(jYj0jZj0ubaubajdj$ubj$)r0}r0(jYUjf}r0(jh]ji]jj]jk]jn]ujZj0jr]r0j)r0}r0(jYX dsp@41000000r0jZj0jbj!jdjjf}r0(jh]ji]jj]jk]jn]ujpM/jr]r0j)r0}r0(jYj0jf}r0(UrefuriXmailto:dsp@41000000jk]jj]jh]ji]jn]ujZj0jr]r0j{X dsp@41000000r0r0}r0(jYUjZj0ubajdjubaubajdj$ubj$)r0}r0(jYUjf}r0(jh]ji]jj]jk]jn]ujZj0jr]r0j)r0}r0(jYX 41000000.dspr0jZj0jbj!jdjjf}r0(jh]ji]jj]jk]jn]ujpM/jr]r0j{X 41000000.dspr0r0}r0(jYj0jZj0ubaubajdj$ubejdj$ubj$)r0}r0(jYUjf}r0(jh]ji]jj]jk]jn]ujZj0jr]r0(j$)r0}r0(jYUjf}r0(jh]ji]jj]jk]jn]ujZj0jr]r0j)r0}r0(jYX ICSS1-PRU0r0jZj0jbj!jdjjf}r0(jh]ji]jj]jk]jn]ujpM1jr]r0j{X ICSS1-PRU0r0r0}r0(jYj0jZj0ubaubajdj$ubj$)r0}r0(jYUjf}r0(jh]ji]jj]jk]jn]ujZj0jr]r0j)r0}r0(jYX pru@4b234000r0jZj0jbj!jdjjf}r0(jh]ji]jj]jk]jn]ujpM1jr]r0j)r0}r0(jYj0jf}r0(UrefuriXmailto:pru@4b234000jk]jj]jh]ji]jn]ujZj0jr]r0j{X pru@4b234000r0r0}r0(jYUjZj0ubajdjubaubajdj$ubj$)r0}r0(jYUjf}r0(jh]ji]jj]jk]jn]ujZj0jr]r0j)r0}r0(jYX 4b234000.pru0r0jZj0jbj!jdjjf}r0(jh]ji]jj]jk]jn]ujpM1jr]r0j{X 4b234000.pru0r0r0}r0(jYj0jZj0ubaubajdj$ubejdj$ubj$)r0}r0(jYUjf}r0(jh]ji]jj]jk]jn]ujZj0jr]r0(j$)r0}r0(jYUjf}r0(jh]ji]jj]jk]jn]ujZj0jr]r0j)r0}r0(jYX ICSS1-PRU1r0jZj0jbj!jdjjf}r0(jh]ji]jj]jk]jn]ujpM3jr]r0j{X ICSS1-PRU1r0r0}r0(jYj0jZj0ubaubajdj$ubj$)r0}r0(jYUjf}r1(jh]ji]jj]jk]jn]ujZj0jr]r1j)r1}r1(jYX pru@4b238000r1jZj0jbj!jdjjf}r1(jh]ji]jj]jk]jn]ujpM3jr]r1j)r1}r1(jYj1jf}r 1(UrefuriXmailto:pru@4b238000jk]jj]jh]ji]jn]ujZj1jr]r 1j{X pru@4b238000r 1r 1}r 1(jYUjZj1ubajdjubaubajdj$ubj$)r1}r1(jYUjf}r1(jh]ji]jj]jk]jn]ujZj0jr]r1j)r1}r1(jYX 4b238000.pru1r1jZj1jbj!jdjjf}r1(jh]ji]jj]jk]jn]ujpM3jr]r1j{X 4b238000.pru1r1r1}r1(jYj1jZj1ubaubajdj$ubejdj$ubj$)r1}r1(jYUjf}r1(jh]ji]jj]jk]jn]ujZj0jr]r1(j$)r1}r1(jYUjf}r 1(jh]ji]jj]jk]jn]ujZj1jr]r!1j)r"1}r#1(jYX ICSS2-PRU0r$1jZj1jbj!jdjjf}r%1(jh]ji]jj]jk]jn]ujpM5jr]r&1j{X ICSS2-PRU0r'1r(1}r)1(jYj$1jZj"1ubaubajdj$ubj$)r*1}r+1(jYUjf}r,1(jh]ji]jj]jk]jn]ujZj1jr]r-1j)r.1}r/1(jYX pru@4b2b4000r01jZj*1jbj!jdjjf}r11(jh]ji]jj]jk]jn]ujpM5jr]r21j)r31}r41(jYj01jf}r51(UrefuriXmailto:pru@4b2b4000jk]jj]jh]ji]jn]ujZj.1jr]r61j{X pru@4b2b4000r71r81}r91(jYUjZj31ubajdjubaubajdj$ubj$)r:1}r;1(jYUjf}r<1(jh]ji]jj]jk]jn]ujZj1jr]r=1j)r>1}r?1(jYX 4b2b4000.pru0r@1jZj:1jbj!jdjjf}rA1(jh]ji]jj]jk]jn]ujpM5jr]rB1j{X 4b2b4000.pru0rC1rD1}rE1(jYj@1jZj>1ubaubajdj$ubejdj$ubj$)rF1}rG1(jYUjf}rH1(jh]ji]jj]jk]jn]ujZj0jr]rI1(j$)rJ1}rK1(jYUjf}rL1(jh]ji]jj]jk]jn]ujZjF1jr]rM1j)rN1}rO1(jYX ICSS2-PRU1rP1jZjJ1jbj!jdjjf}rQ1(jh]ji]jj]jk]jn]ujpM7jr]rR1j{X ICSS2-PRU1rS1rT1}rU1(jYjP1jZjN1ubaubajdj$ubj$)rV1}rW1(jYUjf}rX1(jh]ji]jj]jk]jn]ujZjF1jr]rY1j)rZ1}r[1(jYX pru@4b2b8000r\1jZjV1jbj!jdjjf}r]1(jh]ji]jj]jk]jn]ujpM7jr]r^1j)r_1}r`1(jYj\1jf}ra1(UrefuriXmailto:pru@4b2b8000jk]jj]jh]ji]jn]ujZjZ1jr]rb1j{X pru@4b2b8000rc1rd1}re1(jYUjZj_1ubajdjubaubajdj$ubj$)rf1}rg1(jYUjf}rh1(jh]ji]jj]jk]jn]ujZjF1jr]ri1j)rj1}rk1(jYX 4b2b8000.pru1rl1jZjf1jbj!jdjjf}rm1(jh]ji]jj]jk]jn]ujpM7jr]rn1j{X 4b2b8000.pru1ro1rp1}rq1(jYjl1jZjj1ubaubajdj$ubejdj$ubejdjy%ubejdjz%ubaubj)rr1}rs1(jYXdTo map these System FS names to the associated remoteproc entry, you can run the following commands:rt1jZj/jbj!jdjjf}ru1(jh]ji]jj]jk]jn]ujpM:jqhjr]rv1j{XdTo map these System FS names to the associated remoteproc entry, you can run the following commands:rw1rx1}ry1(jYjt1jZjr1ubaubj)rz1}r{1(jYX{root@am57xx-evm:~# ls -l /sys/kernel/debug/remoteproc/ root@am57xx-evm:~# cat /sys/kernel/debug/remoteproc/remoteproc*/namejZj/jbj!jdjjf}r|1(jjjk]jj]jh]ji]jn]ujpMjqhjr]r}1j{X{root@am57xx-evm:~# ls -l /sys/kernel/debug/remoteproc/ root@am57xx-evm:~# cat /sys/kernel/debug/remoteproc/remoteproc*/namer~1r1}r1(jYUjZjz1ubaubj)r1}r1(jYXqThe results of the commands will be a one-to-one mapping. For example, 58820000.ipu corresponds with remoteproc0.r1jZj/jbj!jdjjf}r1(jh]ji]jj]jk]jn]ujpMBjqhjr]r1j{XqThe results of the commands will be a one-to-one mapping. For example, 58820000.ipu corresponds with remoteproc0.r1r1}r1(jYj1jZj1ubaubj)r1}r1(jYX7Similarly, to see the power state of each of the cores:r1jZj/jbj!jdjjf}r1(jh]ji]jj]jk]jn]ujpMEjqhjr]r1j{X7Similarly, to see the power state of each of the cores:r1r1}r1(jYj1jZj1ubaubj)r1}r1(jYX>root@am57xx-evm:~# cat /sys/class/remoteproc/remoteproc*/statejZj/jbj!jdjjf}r1(jjjk]jj]jh]ji]jn]ujpMjqhjr]r1j{X>root@am57xx-evm:~# cat /sys/class/remoteproc/remoteproc*/stater1r1}r1(jYUjZj1ubaubj)r1}r1(jYXThe state can be suspended, running, offline, etc. You can only attach JTAG if the state is "running". If it shows as "suspended" then you must force it to run. For example, let's say DSP0 is "suspended". You can run the following command to force it on:r1jZj/jbj!jdjjf}r1(jh]ji]jj]jk]jn]ujpMKjqhjr]r1j{XThe state can be suspended, running, offline, etc. You can only attach JTAG if the state is "running". If it shows as "suspended" then you must force it to run. For example, let's say DSP0 is "suspended". You can run the following command to force it on:r1r1}r1(jYj1jZj1ubaubj)r1}r1(jYXQroot@am57xx-evm:~# echo on > /sys/bus/platform/devices/40800000.dsp/power/controljZj/jbj!jdjjf}r1(jjjk]jj]jh]ji]jn]ujpMjqhjr]r1j{XQroot@am57xx-evm:~# echo on > /sys/bus/platform/devices/40800000.dsp/power/controlr1r1}r1(jYUjZj1ubaubj)r1}r1(jYXxThe same is true for any of the cores, but replace 40800000.dsp with the associated System FS name from the chart above.r1jZj/jbj!jdjjf}r1(jh]ji]jj]jk]jn]ujpMTjqhjr]r1j{XxThe same is true for any of the cores, but replace 40800000.dsp with the associated System FS name from the chart above.r1r1}r1(jYj1jZj1ubaubeubj[)r1}r1(jYUjZj!jbj!jdjejf}r1(jh]ji]jj]jk]r1U2(jYj:2jZj82jbj!jdjjf}r?2(jh]ji]jj]jk]jn]ujpMjr]r@2j{X@Some edits were made to the LED blink example to allow it to runrA2rB2}rC2(jYj:2jZj=2ubaubaubj)rD2}rE2(jYXin a Linux environment, specifically, removed the GPIO interrupts and then added a Clock object to call the LED GPIO toggle function on a periodic bases.rF2jZj1jbj!jdjjf}rG2(jh]ji]jj]jk]jn]ujpMjqhjr]rH2j{Xin a Linux environment, specifically, removed the GPIO interrupts and then added a Clock object to call the LED GPIO toggle function on a periodic bases.rI2rJ2}rK2(jYjF2jZjD2ubaubj)rL2}rM2(jYX1Make CCS project out of ex02_messageq IPC examplerN2jZj1jbj!jdjjf}rO2(jk]rP2U1make-ccs-project-out-of-ex02-messageq-ipc-examplerQ2ajj]jh]ji]jn]rR2hbaujpNjqhjr]rS2j{X1Make CCS project out of ex02_messageq IPC examplerT2rU2}rV2(jYjN2jZjL2ubaubj)rW2}rX2(jYXoTODO - fill this section in with instructions on how to make a CCS project out of the IPC example source files.rY2jZj1jbj!jdjjf}rZ2(jh]ji]jj]jk]jn]ujpMjqhjr]r[2j{XoTODO - fill this section in with instructions on how to make a CCS project out of the IPC example source files.r\2r]2}r^2(jYjY2jZjW2ubaubjZ)r_2}r`2(jYUjZj1jbj!jdj]jf}ra2(jh]ji]jj]jk]jn]ujpMjqhjr]rb2j`)rc2}rd2(jYUjcKjZj_2jbj!jdjpjf}re2(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)rf2}rg2(jYX Add IPC to the LED Blink Examplerh2jZj1jbj!jdjjf}ri2(jk]rj2U add-ipc-to-the-led-blink-examplerk2ajj]jh]ji]jn]rl2jaujpNjqhjr]rm2j{X Add IPC to the LED Blink Examplern2ro2}rp2(jYjh2jZjf2ubaubj)rq2}rr2(jYXThe first step is to clone our out-of-box LED blink CCS project and rename it to denote it's using IPC. The easiest way to do this is using CCS. Here are the steps...rs2jZj1jbj!jdjjf}rt2(jh]ji]jj]jk]jn]ujpMjqhjr]ru2j{XThe first step is to clone our out-of-box LED blink CCS project and rename it to denote it's using IPC. The easiest way to do this is using CCS. Here are the steps...rv2rw2}rx2(jYjs2jZjq2ubaubjC)ry2}rz2(jYUjZj1jbj!jdj`jf}r{2(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]r|2(j/)r}2}r~2(jYXIn the *Edit* perspective, go into your *Project Explorer* window and right click on your GPIO_LedBlink_evmAM572x+c66xExampleProject project and select *copy* from the pop-up menu. Maske sure the project is not is a closed state.jZjy2jbj!jdj2jf}r2(jh]ji]jj]jk]jn]ujpNjqhjr]r2j)r2}r2(jYXIn the *Edit* perspective, go into your *Project Explorer* window and right click on your GPIO_LedBlink_evmAM572x+c66xExampleProject project and select *copy* from the pop-up menu. Maske sure the project is not is a closed state.jZj}2jbj!jdjjf}r2(jh]ji]jj]jk]jn]ujpMjr]r2(j{XIn the r2r2}r2(jYXIn the jZj2ubj')r2}r2(jYX*Edit*jf}r2(jh]ji]jj]jk]jn]ujZj2jr]r2j{XEditr2r2}r2(jYUjZj2ubajdj'ubj{X perspective, go into your r2r2}r2(jYX perspective, go into your jZj2ubj')r2}r2(jYX*Project Explorer*jf}r2(jh]ji]jj]jk]jn]ujZj2jr]r2j{XProject Explorerr2r2}r2(jYUjZj2ubajdj'ubj{X^ window and right click on your GPIO_LedBlink_evmAM572x+c66xExampleProject project and select r2r2}r2(jYX^ window and right click on your GPIO_LedBlink_evmAM572x+c66xExampleProject project and select jZj2ubj')r2}r2(jYX*copy*jf}r2(jh]ji]jj]jk]jn]ujZj2jr]r2j{Xcopyr2r2}r2(jYUjZj2ubajdj'ubj{XG from the pop-up menu. Maske sure the project is not is a closed state.r2r2}r2(jYXG from the pop-up menu. Maske sure the project is not is a closed state.jZj2ubeubaubj/)r2}r2(jYXLRick click in and empty area of the project explorer window and select past.jZjy2jbj!jdj2jf}r2(jh]ji]jj]jk]jn]ujpNjqhjr]r2j)r2}r2(jYXLRick click in and empty area of the project explorer window and select past.r2jZj2jbj!jdjjf}r2(jh]ji]jj]jk]jn]ujpMjr]r2j{XLRick click in and empty area of the project explorer window and select past.r2r2}r2(jYj2jZj2ubaubaubj/)r2}r2(jYXA dialog box pops up, modify the name to denote it's using IPC. A good name is GPIO_LedBlink_evmAM572x+c66xExampleProjec_with_ipc. jZjy2jbj!jdj2jf}r2(jh]ji]jj]jk]jn]ujpNjqhjr]r2j)r2}r2(jYXA dialog box pops up, modify the name to denote it's using IPC. A good name is GPIO_LedBlink_evmAM572x+c66xExampleProjec_with_ipc.r2jZj2jbj!jdjjf}r2(jh]ji]jj]jk]jn]ujpMjr]r2j{XA dialog box pops up, modify the name to denote it's using IPC. A good name is GPIO_LedBlink_evmAM572x+c66xExampleProjec_with_ipc.r2r2}r2(jYj2jZj2ubaubaubeubjZ)r2}r2(jYUjZj1jbj!jdj]jf}r2(jh]ji]jj]jk]jn]ujpMjqhjr]r2j`)r2}r2(jYUjcKjZj2jbj!jdjpjf}r2(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r2}r2(jYXThis is the project we'll be working with from here on. The next thing we want to do is select the proper RTSC platform and other components. To do this, follow these steps.r2jZj1jbj!jdjjf}r2(jh]ji]jj]jk]jn]ujpMjqhjr]r2j{XThis is the project we'll be working with from here on. The next thing we want to do is select the proper RTSC platform and other components. To do this, follow these steps.r2r2}r2(jYj2jZj2ubaubjC)r2}r2(jYUjZj1jbj!jdj`jf}r2(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]r2(j/)r2}r2(jYXeRight click on the GPIO_LedBlink_evmAM572x+c66xExampleProjec_with_ipc project and select *Properties*jZj2jbj!jdj2jf}r2(jh]ji]jj]jk]jn]ujpNjqhjr]r2j)r2}r2(jYXeRight click on the GPIO_LedBlink_evmAM572x+c66xExampleProjec_with_ipc project and select *Properties*jZj2jbj!jdjjf}r2(jh]ji]jj]jk]jn]ujpMjr]r2(j{XYRight click on the GPIO_LedBlink_evmAM572x+c66xExampleProjec_with_ipc project and select r2r2}r2(jYXYRight click on the GPIO_LedBlink_evmAM572x+c66xExampleProjec_with_ipc project and select jZj2ubj')r2}r2(jYX *Properties*jf}r2(jh]ji]jj]jk]jn]ujZj2jr]r2j{X Propertiesr2r2}r2(jYUjZj2ubajdj'ubeubaubj/)r2}r2(jYX.In the left hand pane, click on *CCS General*.r2jZj2jbj!jdj2jf}r2(jh]ji]jj]jk]jn]ujpNjqhjr]r2j)r2}r2(jYj2jZj2jbj!jdjjf}r2(jh]ji]jj]jk]jn]ujpMjr]r2(j{X In the left hand pane, click on r2r2}r2(jYX In the left hand pane, click on jZj2ubj')r2}r2(jYX *CCS General*jf}r2(jh]ji]jj]jk]jn]ujZj2jr]r2j{X CCS Generalr2r2}r2(jYUjZj2ubajdj'ubj{X.r2}r2(jYX.jZj2ubeubaubj/)r2}r2(jYX/On the right hand side, click on the *RTSC* tabr2jZj2jbj!jdj2jf}r2(jh]ji]jj]jk]jn]ujpNjqhjr]r2j)r2}r2(jYj2jZj2jbj!jdjjf}r2(jh]ji]jj]jk]jn]ujpMjr]r3(j{X%On the right hand side, click on the r3r3}r3(jYX%On the right hand side, click on the jZj2ubj')r3}r3(jYX*RTSC*jf}r3(jh]ji]jj]jk]jn]ujZj2jr]r3j{XRTSCr3r 3}r 3(jYUjZj3ubajdj'ubj{X tabr 3r 3}r 3(jYX tabjZj2ubeubaubj/)r3}r3(jYX-For *XDCtools version:* select 3.32.0.06_corer3jZj2jbj!jdj2jf}r3(jh]ji]jj]jk]jn]ujpNjqhjr]r3j)r3}r3(jYj3jZj3jbj!jdjjf}r3(jh]ji]jj]jk]jn]ujpMjr]r3(j{XFor r3r3}r3(jYXFor jZj3ubj')r3}r3(jYX*XDCtools version:*jf}r3(jh]ji]jj]jk]jn]ujZj3jr]r3j{XXDCtools version:r3r3}r 3(jYUjZj3ubajdj'ubj{X select 3.32.0.06_corer!3r"3}r#3(jYX select 3.32.0.06_corejZj3ubeubaubj/)r$3}r%3(jYXIn the list of *Products and Repositories*, *check* the following... - IPC 3.43.2.04 - SYS/BIOS 6.45.1.29 - am57xx PDK 1.0.4 jZj2jbNjdj2jf}r&3(jh]ji]jj]jk]jn]ujpNjqhjr]r'3(j)r(3}r)3(jYXDIn the list of *Products and Repositories*, *check* the following...jZj$3jbj!jdjjf}r*3(jh]ji]jj]jk]jn]ujpMjr]r+3(j{XIn the list of r,3r-3}r.3(jYXIn the list of jZj(3ubj')r/3}r03(jYX*Products and Repositories*jf}r13(jh]ji]jj]jk]jn]ujZj(3jr]r23j{XProducts and Repositoriesr33r43}r53(jYUjZj/3ubajdj'ubj{X, r63r73}r83(jYX, jZj(3ubj')r93}r:3(jYX*check*jf}r;3(jh]ji]jj]jk]jn]ujZj(3jr]r<3j{Xcheckr=3r>3}r?3(jYUjZj93ubajdj'ubj{X the following...r@3rA3}rB3(jYX the following...jZj(3ubeubjC)rC3}rD3(jYUjf}rE3(jGX-jk]jj]jh]ji]jn]ujZj$3jr]rF3(j/)rG3}rH3(jYX IPC 3.43.2.04rI3jf}rJ3(jh]ji]jj]jk]jn]ujZjC3jr]rK3j)rL3}rM3(jYjI3jZjG3jbj!jdjjf}rN3(jh]ji]jj]jk]jn]ujpMjr]rO3j{X IPC 3.43.2.04rP3rQ3}rR3(jYjI3jZjL3ubaubajdj2ubj/)rS3}rT3(jYXSYS/BIOS 6.45.1.29rU3jf}rV3(jh]ji]jj]jk]jn]ujZjC3jr]rW3j)rX3}rY3(jYjU3jZjS3jbj!jdjjf}rZ3(jh]ji]jj]jk]jn]ujpMjr]r[3j{XSYS/BIOS 6.45.1.29r\3r]3}r^3(jYjU3jZjX3ubaubajdj2ubj/)r_3}r`3(jYXam57xx PDK 1.0.4 jf}ra3(jh]ji]jj]jk]jn]ujZjC3jr]rb3j)rc3}rd3(jYXam57xx PDK 1.0.4re3jZj_3jbj!jdjjf}rf3(jh]ji]jj]jk]jn]ujpMjr]rg3j{Xam57xx PDK 1.0.4rh3ri3}rj3(jYje3jZjc3ubaubajdj2ubejdj`ubeubj/)rk3}rl3(jYX'For *Target*, select ti.targets.elf.C66rm3jZj2jbj!jdj2jf}rn3(jh]ji]jj]jk]jn]ujpNjqhjr]ro3j)rp3}rq3(jYjm3jZjk3jbj!jdjjf}rr3(jh]ji]jj]jk]jn]ujpMjr]rs3(j{XFor rt3ru3}rv3(jYXFor jZjp3ubj')rw3}rx3(jYX*Target*jf}ry3(jh]ji]jj]jk]jn]ujZjp3jr]rz3j{XTargetr{3r|3}r}3(jYUjZjw3ubajdj'ubj{X, select ti.targets.elf.C66r~3r3}r3(jYX, select ti.targets.elf.C66jZjp3ubeubaubj/)r3}r3(jYX-For *Platform*, select ti.platforms.evmDRA7XXr3jZj2jbj!jdj2jf}r3(jh]ji]jj]jk]jn]ujpNjqhjr]r3j)r3}r3(jYj3jZj3jbj!jdjjf}r3(jh]ji]jj]jk]jn]ujpMjr]r3(j{XFor r3r3}r3(jYXFor jZj3ubj')r3}r3(jYX *Platform*jf}r3(jh]ji]jj]jk]jn]ujZj3jr]r3j{XPlatformr3r3}r3(jYUjZj3ubajdj'ubj{X, select ti.platforms.evmDRA7XXr3r3}r3(jYX, select ti.platforms.evmDRA7XXjZj3ubeubaubj/)r3}r3(jYXOnce the platform is selected, edit its name buy hand and append :dsp1 to the end. After this it should be ti.platforms.evmDRA7XX:dsp1jZj2jbj!jdj2jf}r3(jh]ji]jj]jk]jn]ujpNjqhjr]r3j)r3}r3(jYXOnce the platform is selected, edit its name buy hand and append :dsp1 to the end. After this it should be ti.platforms.evmDRA7XX:dsp1r3jZj3jbj!jdjjf}r3(jh]ji]jj]jk]jn]ujpMjr]r3j{XOnce the platform is selected, edit its name buy hand and append :dsp1 to the end. After this it should be ti.platforms.evmDRA7XX:dsp1r3r3}r3(jYj3jZj3ubaubaubj/)r3}r3(jYX4Go ahead and leave the *Build-profile* set to debug.r3jZj2jbj!jdj2jf}r3(jh]ji]jj]jk]jn]ujpNjqhjr]r3j)r3}r3(jYj3jZj3jbj!jdjjf}r3(jh]ji]jj]jk]jn]ujpMjr]r3(j{XGo ahead and leave the r3r3}r3(jYXGo ahead and leave the jZj3ubj')r3}r3(jYX*Build-profile*jf}r3(jh]ji]jj]jk]jn]ujZj3jr]r3j{X Build-profiler3r3}r3(jYUjZj3ubajdj'ubj{X set to debug.r3r3}r3(jYX set to debug.jZj3ubeubaubj/)r3}r3(jYXHit the OK button. jZj2jbj!jdj2jf}r3(jh]ji]jj]jk]jn]ujpNjqhjr]r3j)r3}r3(jYXHit the OK button.r3jZj3jbj!jdjjf}r3(jh]ji]jj]jk]jn]ujpMjr]r3j{XHit the OK button.r3r3}r3(jYj3jZj3ubaubaubeubjZ)r3}r3(jYUjZj1jbj!jdj]jf}r3(jh]ji]jj]jk]jn]ujpMjqhjr]r3j`)r3}r3(jYUjcKjZj3jbj!jdjpjf}r3(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r3}r3(jYXYNow we want to copy configuration and source files from the ex02_messageq IPC example into our project. The IPC example is located at *C:/ti/ipc_3_43_02_04/examples/DRA7XX_linux_elf/ex02_messageq*. To copy files into your CCS project, you can simply select the files you want in Windows explorer then drag and drop them into your project in CCS.jZj1jbj!jdjjf}r3(jh]ji]jj]jk]jn]ujpMjqhjr]r3(j{XNow we want to copy configuration and source files from the ex02_messageq IPC example into our project. The IPC example is located at r3r3}r3(jYXNow we want to copy configuration and source files from the ex02_messageq IPC example into our project. The IPC example is located at jZj3ubj')r3}r3(jYX>*C:/ti/ipc_3_43_02_04/examples/DRA7XX_linux_elf/ex02_messageq*jf}r3(jh]ji]jj]jk]jn]ujZj3jr]r3j{X<C:/ti/ipc_3_43_02_04/examples/DRA7XX_linux_elf/ex02_messageqr3r3}r3(jYUjZj3ubajdj'ubj{X. To copy files into your CCS project, you can simply select the files you want in Windows explorer then drag and drop them into your project in CCS.r3r3}r3(jYX. To copy files into your CCS project, you can simply select the files you want in Windows explorer then drag and drop them into your project in CCS.jZj3ubeubj)r3}r3(jYX)Copy these files into your CCS project...r3jZj1jbj!jdjjf}r3(jh]ji]jj]jk]jn]ujpMjqhjr]r3j{X)Copy these files into your CCS project...r3r3}r3(jYj3jZj3ubaubjC)r3}r3(jYUjZj1jbj!jdj`jf}r3(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]r3(j/)r3}r3(jYXOC:/ti/ipc_3_43_02_04/examples/DRA7XX_linux_elf/ex02_messageq/shared/AppCommon.hr3jZj3jbj!jdj2jf}r3(jh]ji]jj]jk]jn]ujpNjqhjr]r3j)r3}r3(jYj3jZj3jbj!jdjjf}r3(jh]ji]jj]jk]jn]ujpMjr]r3j{XOC:/ti/ipc_3_43_02_04/examples/DRA7XX_linux_elf/ex02_messageq/shared/AppCommon.hr3r3}r3(jYj3jZj3ubaubaubj/)r3}r3(jYXNC:/ti/ipc_3_43_02_04/examples/DRA7XX_linux_elf/ex02_messageq/shared/config.bldr3jZj3jbj!jdj2jf}r3(jh]ji]jj]jk]jn]ujpNjqhjr]r3j)r3}r3(jYj3jZj3jbj!jdjjf}r3(jh]ji]jj]jk]jn]ujpMjr]r3j{XNC:/ti/ipc_3_43_02_04/examples/DRA7XX_linux_elf/ex02_messageq/shared/config.bldr3r3}r4(jYj3jZj3ubaubaubj/)r4}r4(jYXOC:/ti/ipc_3_43_02_04/examples/DRA7XX_linux_elf/ex02_messageq/shared/ipc.cfg.xs jZj3jbj!jdj2jf}r4(jh]ji]jj]jk]jn]ujpNjqhjr]r4j)r4}r4(jYXNC:/ti/ipc_3_43_02_04/examples/DRA7XX_linux_elf/ex02_messageq/shared/ipc.cfg.xsr4jZj4jbj!jdjjf}r4(jh]ji]jj]jk]jn]ujpMjr]r 4j{XNC:/ti/ipc_3_43_02_04/examples/DRA7XX_linux_elf/ex02_messageq/shared/ipc.cfg.xsr 4r 4}r 4(jYj4jZj4ubaubaubeubjZ)r 4}r4(jYUjZj1jbj!jdj]jf}r4(jh]ji]jj]jk]jn]ujpMjqhjr]r4j`)r4}r4(jYUjcKjZj 4jbj!jdjpjf}r4(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r4}r4(jYX-Now copy these files into your CCS project...r4jZj1jbj!jdjjf}r4(jh]ji]jj]jk]jn]ujpMjqhjr]r4j{X-Now copy these files into your CCS project...r4r4}r4(jYj4jZj4ubaubjC)r4}r4(jYUjZj1jbj!jdj`jf}r4(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]r4(j/)r 4}r!4(jYXJC:/ti/ipc_3_43_02_04/examples/DRA7XX_linux_elf/ex02_messageq/dsp1/Dsp1.cfgr"4jZj4jbj!jdj2jf}r#4(jh]ji]jj]jk]jn]ujpNjqhjr]r$4j)r%4}r&4(jYj"4jZj 4jbj!jdjjf}r'4(jh]ji]jj]jk]jn]ujpMjr]r(4j{XJC:/ti/ipc_3_43_02_04/examples/DRA7XX_linux_elf/ex02_messageq/dsp1/Dsp1.cfgr)4r*4}r+4(jYj"4jZj%4ubaubaubj/)r,4}r-4(jYXLC:/ti/ipc_3_43_02_04/examples/DRA7XX_linux_elf/ex02_messageq/dsp1/MainDsp1.cr.4jZj4jbj!jdj2jf}r/4(jh]ji]jj]jk]jn]ujpNjqhjr]r04j)r14}r24(jYj.4jZj,4jbj!jdjjf}r34(jh]ji]jj]jk]jn]ujpMjr]r44j{XLC:/ti/ipc_3_43_02_04/examples/DRA7XX_linux_elf/ex02_messageq/dsp1/MainDsp1.cr54r64}r74(jYj.4jZj14ubaubaubj/)r84}r94(jYXJC:/ti/ipc_3_43_02_04/examples/DRA7XX_linux_elf/ex02_messageq/dsp1/Server.cr:4jZj4jbj!jdj2jf}r;4(jh]ji]jj]jk]jn]ujpNjqhjr]r<4j)r=4}r>4(jYj:4jZj84jbj!jdjjf}r?4(jh]ji]jj]jk]jn]ujpMjr]r@4j{XJC:/ti/ipc_3_43_02_04/examples/DRA7XX_linux_elf/ex02_messageq/dsp1/Server.crA4rB4}rC4(jYj:4jZj=4ubaubaubj/)rD4}rE4(jYXKC:/ti/ipc_3_43_02_04/examples/DRA7XX_linux_elf/ex02_messageq/dsp1/Server.h jZj4jbj!jdj2jf}rF4(jh]ji]jj]jk]jn]ujpNjqhjr]rG4j)rH4}rI4(jYXJC:/ti/ipc_3_43_02_04/examples/DRA7XX_linux_elf/ex02_messageq/dsp1/Server.hrJ4jZjD4jbj!jdjjf}rK4(jh]ji]jj]jk]jn]ujpMjr]rL4j{XJC:/ti/ipc_3_43_02_04/examples/DRA7XX_linux_elf/ex02_messageq/dsp1/Server.hrM4rN4}rO4(jYjJ4jZjH4ubaubaubeubj)rP4}rQ4(jYXWhen you copy Dsp1.cfg into your CCS project, it should show up greyed out. This is because the LED blink example already has a cfg file (gpio_test_evmAM572x.cfg). The Dsp1.cfg will be used for copying and pasting. When it's all done, you can delete it from your project.jZj1jbj!jdjjf}rR4(jh]ji]jj]jk]jn]ujpNjqhjr]rS4j)rT4}rU4(jYXWhen you copy Dsp1.cfg into your CCS project, it should show up greyed out. This is because the LED blink example already has a cfg file (gpio_test_evmAM572x.cfg). The Dsp1.cfg will be used for copying and pasting. When it's all done, you can delete it from your project.rV4jZjP4jbj!jdjjf}rW4(jh]ji]jj]jk]jn]ujpMjr]rX4j{XWhen you copy Dsp1.cfg into your CCS project, it should show up greyed out. This is because the LED blink example already has a cfg file (gpio_test_evmAM572x.cfg). The Dsp1.cfg will be used for copying and pasting. When it's all done, you can delete it from your project.rY4rZ4}r[4(jYjV4jZjT4ubaubaubj)r\4}r]4(jYXiFinally, you will likely want to use a custom resource table so copy these files into your CCS project...r^4jZj1jbj!jdjjf}r_4(jh]ji]jj]jk]jn]ujpMjqhjr]r`4j{XiFinally, you will likely want to use a custom resource table so copy these files into your CCS project...ra4rb4}rc4(jYj^4jZj\4ubaubjC)rd4}re4(jYUjZj1jbj!jdj`jf}rf4(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]rg4(j/)rh4}ri4(jYXDC:/ti/ipc_3_43_02_04/packages/ti/ipc/remoteproc/rsc_table_vayu_dsp.hrj4jZjd4jbj!jdj2jf}rk4(jh]ji]jj]jk]jn]ujpNjqhjr]rl4j)rm4}rn4(jYjj4jZjh4jbj!jdjjf}ro4(jh]ji]jj]jk]jn]ujpMjr]rp4j{XDC:/ti/ipc_3_43_02_04/packages/ti/ipc/remoteproc/rsc_table_vayu_dsp.hrq4rr4}rs4(jYjj4jZjm4ubaubaubj/)rt4}ru4(jYX<C:/ti/ipc_3_43_02_04/packages/ti/ipc/remoteproc/rsc_types.h jZjd4jbj!jdj2jf}rv4(jh]ji]jj]jk]jn]ujpNjqhjr]rw4j)rx4}ry4(jYX;C:/ti/ipc_3_43_02_04/packages/ti/ipc/remoteproc/rsc_types.hrz4jZjt4jbj!jdjjf}r{4(jh]ji]jj]jk]jn]ujpMjr]r|4j{X;C:/ti/ipc_3_43_02_04/packages/ti/ipc/remoteproc/rsc_types.hr}4r~4}r4(jYjz4jZjx4ubaubaubeubj)r4}r4(jYX`The rsc_table_vayu_dsp.h file defines an initialized structure so let's make a *.c* source file.jZj1jbj!jdjjf}r4(jh]ji]jj]jk]jn]ujpMjqhjr]r4(j{XOThe rsc_table_vayu_dsp.h file defines an initialized structure so let's make a r4r4}r4(jYXOThe rsc_table_vayu_dsp.h file defines an initialized structure so let's make a jZj4ubj')r4}r4(jYX*.c*jf}r4(jh]ji]jj]jk]jn]ujZj4jr]r4j{X.cr4r4}r4(jYUjZj4ubajdj'ubj{X source file.r4r4}r4(jYX source file.jZj4ubeubjC)r4}r4(jYUjZj1jbj!jdj`jf}r4(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]r4j/)r4}r4(jYXIIn your CCS project, rename rsc_table_vayu_dsp.h to rsc_table_vayu_dsp.c jZj4jbj!jdj2jf}r4(jh]ji]jj]jk]jn]ujpNjqhjr]r4j)r4}r4(jYXHIn your CCS project, rename rsc_table_vayu_dsp.h to rsc_table_vayu_dsp.cr4jZj4jbj!jdjjf}r4(jh]ji]jj]jk]jn]ujpMjr]r4j{XHIn your CCS project, rename rsc_table_vayu_dsp.h to rsc_table_vayu_dsp.cr4r4}r4(jYj4jZj4ubaubaubaubjZ)r4}r4(jYUjZj1jbj!jdj]jf}r4(jh]ji]jj]jk]jn]ujpMjqhjr]r4(j`)r4}r4(jYUjcKjZj4jbj!jdjpjf}r4(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)r4}r4(jYX~Now we want to *merge* the IPC example configuration file with the LED blink example configuration file. Follow these steps...jcKjZj4jbj!jdjpjf}r4(jh]ji]jj]jk]jn]ujpMjqhjr]r4(j{XNow we want to r4r4}r4(jYXNow we want to jZj4ubj')r4}r4(jYX*merge*jf}r4(jh]ji]jj]jk]jn]ujZj4jr]r4j{Xmerger4r4}r4(jYUjZj4ubajdj'ubj{Xh the IPC example configuration file with the LED blink example configuration file. Follow these steps...r4r4}r4(jYXh the IPC example configuration file with the LED blink example configuration file. Follow these steps...jZj4ubeubeubjC)r4}r4(jYUjZj1jbj!jdj`jf}r4(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]r4(j/)r4}r4(jYXOpen up *Dsp1.cfg* using a text editor (don't open it using the GUI). Right click on it and select *Open With -> XDCscript Editor*jZj4jbj!jdj2jf}r4(jh]ji]jj]jk]jn]ujpNjqhjr]r4j)r4}r4(jYXOpen up *Dsp1.cfg* using a text editor (don't open it using the GUI). Right click on it and select *Open With -> XDCscript Editor*jZj4jbj!jdjjf}r4(jh]ji]jj]jk]jn]ujpMjr]r4(j{XOpen up r4r4}r4(jYXOpen up jZj4ubj')r4}r4(jYX *Dsp1.cfg*jf}r4(jh]ji]jj]jk]jn]ujZj4jr]r4j{XDsp1.cfgr4r4}r4(jYUjZj4ubajdj'ubj{XQ using a text editor (don't open it using the GUI). Right click on it and select r4r4}r4(jYXQ using a text editor (don't open it using the GUI). Right click on it and select jZj4ubj')r4}r4(jYX*Open With -> XDCscript Editor*jf}r4(jh]ji]jj]jk]jn]ujZj4jr]r4j{XOpen With -> XDCscript Editorr4r4}r4(jYUjZj4ubajdj'ubeubaubj/)r4}r4(jYXLWe want to copy the entire contents into the clipboard. Select all and copy.jZj4jbj!jdj2jf}r4(jh]ji]jj]jk]jn]ujpNjqhjr]r4j)r4}r4(jYXLWe want to copy the entire contents into the clipboard. Select all and copy.r4jZj4jbj!jdjjf}r4(jh]ji]jj]jk]jn]ujpMjr]r4j{XLWe want to copy the entire contents into the clipboard. Select all and copy.r4r4}r4(jYj4jZj4ubaubaubj/)r4}r4(jYXNow just like above, open the gpio_test_evmAM572x.cfg config file in the text editor. Go to the very bottom and *paste* in the contents from the Dsp1.cfg file. Basically we've appended the contents of Dsp1.cfg into gpio_test_evmAM572x.cfg. jZj4jbj!jdj2jf}r4(jh]ji]jj]jk]jn]ujpNjqhjr]r4j)r4}r4(jYXNow just like above, open the gpio_test_evmAM572x.cfg config file in the text editor. Go to the very bottom and *paste* in the contents from the Dsp1.cfg file. Basically we've appended the contents of Dsp1.cfg into gpio_test_evmAM572x.cfg.jZj4jbj!jdjjf}r4(jh]ji]jj]jk]jn]ujpMjr]r4(j{XpNow just like above, open the gpio_test_evmAM572x.cfg config file in the text editor. Go to the very bottom and r4r4}r4(jYXpNow just like above, open the gpio_test_evmAM572x.cfg config file in the text editor. Go to the very bottom and jZj4ubj')r4}r4(jYX*paste*jf}r4(jh]ji]jj]jk]jn]ujZj4jr]r4j{Xpaster4r4}r4(jYUjZj4ubajdj'ubj{Xx in the contents from the Dsp1.cfg file. Basically we've appended the contents of Dsp1.cfg into gpio_test_evmAM572x.cfg.r4r4}r4(jYXx in the contents from the Dsp1.cfg file. Basically we've appended the contents of Dsp1.cfg into gpio_test_evmAM572x.cfg.jZj4ubeubaubeubjZ)r4}r4(jYUjZj1jbj!jdj]jf}r4(jh]ji]jj]jk]jn]ujpMjqhjr]r4j`)r4}r4(jYUjcKjZj4jbj!jdjpjf}r5(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r5}r5(jYXWe've now added in all the necessary configuration and source files into our project. Don't expect it to build at this point, we have to make edits first. These edits are listed below.r5jZj1jbj!jdjjf}r5(jh]ji]jj]jk]jn]ujpMjqhjr]r5j{XWe've now added in all the necessary configuration and source files into our project. Don't expect it to build at this point, we have to make edits first. These edits are listed below.r5r5}r5(jYj5jZj5ubaubj)r 5}r 5(jYXxYou can download the full CCS project with source files to use as a reference. See link towards the end of this section.jZj1jbj!jdjjf}r 5(jh]ji]jj]jk]jn]ujpNjqhjr]r 5j)r 5}r5(jYXxYou can download the full CCS project with source files to use as a reference. See link towards the end of this section.r5jZj 5jbj!jdjjf}r5(jh]ji]jj]jk]jn]ujpMjr]r5j{XxYou can download the full CCS project with source files to use as a reference. See link towards the end of this section.r5r5}r5(jYj5jZj 5ubaubaubjC)r5}r5(jYUjZj1jbj!jdj`jf}r5(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]r5j/)r5}r5(jYX!Edit **gpio_test_evmAM572x.cfg** jZj5jbj!jdj2jf}r5(jh]ji]jj]jk]jn]ujpNjqhjr]r5j)r5}r5(jYX Edit **gpio_test_evmAM572x.cfg**jZj5jbj!jdjjf}r5(jh]ji]jj]jk]jn]ujpMjr]r 5(j{XEdit r!5r"5}r#5(jYXEdit jZj5ubj)r$5}r%5(jYX**gpio_test_evmAM572x.cfg**jf}r&5(jh]ji]jj]jk]jn]ujZj5jr]r'5j{Xgpio_test_evmAM572x.cfgr(5r)5}r*5(jYUjZj$5ubajdjubeubaubaubjZ)r+5}r,5(jYUjZj1jbj!jdj]jf}r-5(jh]ji]jj]jk]jn]ujpMjqhjr]r.5j`)r/5}r05(jYUjcKjZj+5jbj!jdjpjf}r15(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r25}r35(jYX=Add the following to the beginning of your configuration filer45jZj1jbj!jdjjf}r55(jh]ji]jj]jk]jn]ujpMjqhjr]r65j{X=Add the following to the beginning of your configuration filer75r85}r95(jYj45jZj25ubaubj)r:5}r;5(jYX/var Program = xdc.useModule('xdc.cfg.Program');jZj1jbj!jdjjf}r<5(jjX javascriptjjjk]jj]jh]j }ji]jn]ujpMjqhjr]r=5j{X/var Program = xdc.useModule('xdc.cfg.Program');r>5r?5}r@5(jYUjZj:5ubaubjZ)rA5}rB5(jYUjZj1jbj!jdj]jf}rC5(jh]ji]jj]jk]jn]ujpMjqhjr]rD5j`)rE5}rF5(jYUjcKjZjA5jbj!jdjpjf}rG5(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)rH5}rI5(jYX<Comment out the Memory sections configuration as shown belowrJ5jZj1jbj!jdjjf}rK5(jh]ji]jj]jk]jn]ujpMjqhjr]rL5j{X<Comment out the Memory sections configuration as shown belowrM5rN5}rO5(jYjJ5jZjH5ubaubj)rP5}rQ5(jYX5/* ================ Memory sections configuration ================ */ //Program.sectMap[".text"] = "EXT_RAM"; //Program.sectMap[".const"] = "EXT_RAM"; //Program.sectMap[".plt"] = "EXT_RAM"; /* Program.sectMap["BOARD_IO_DELAY_DATA"] = "OCMC_RAM1"; */ /* Program.sectMap["BOARD_IO_DELAY_CODE"] = "OCMC_RAM1"; */jZj1jbj!jdjjf}rR5(jjX javascriptjjjk]jj]jh]j }ji]jn]ujpMjqhjr]rS5j{X5/* ================ Memory sections configuration ================ */ //Program.sectMap[".text"] = "EXT_RAM"; //Program.sectMap[".const"] = "EXT_RAM"; //Program.sectMap[".plt"] = "EXT_RAM"; /* Program.sectMap["BOARD_IO_DELAY_DATA"] = "OCMC_RAM1"; */ /* Program.sectMap["BOARD_IO_DELAY_CODE"] = "OCMC_RAM1"; */rT5rU5}rV5(jYUjZjP5ubaubjZ)rW5}rX5(jYUjZj1jbj!jdj]jf}rY5(jh]ji]jj]jk]jn]ujpMjqhjr]rZ5j`)r[5}r\5(jYUjcKjZjW5jbj!jdjpjf}r]5(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r^5}r_5(jYXGSince we are no longer using a shared folder, make the following changer`5jZj1jbj!jdjjf}ra5(jh]ji]jj]jk]jn]ujpMjqhjr]rb5j{XGSince we are no longer using a shared folder, make the following changerc5rd5}re5(jYj`5jZj^5ubaubj)rf5}rg5(jYXh//var ipc_cfg = xdc.loadCapsule("../shared/ipc.cfg.xs"); var ipc_cfg = xdc.loadCapsule("../ipc.cfg.xs");jZj1jbj!jdjjf}rh5(jjX javascriptjjjk]jj]jh]j }ji]jn]ujpMjqhjr]ri5j{Xh//var ipc_cfg = xdc.loadCapsule("../shared/ipc.cfg.xs"); var ipc_cfg = xdc.loadCapsule("../ipc.cfg.xs");rj5rk5}rl5(jYUjZjf5ubaubjZ)rm5}rn5(jYUjZj1jbj!jdj]jf}ro5(jh]ji]jj]jk]jn]ujpMjqhjr]rp5j`)rq5}rr5(jYUjcKjZjm5jbj!jdjpjf}rs5(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)rt5}ru5(jYXMComment out the following. We'll be calling this function directly from main.rv5jZj1jbj!jdjjf}rw5(jh]ji]jj]jk]jn]ujpMjqhjr]rx5j{XMComment out the following. We'll be calling this function directly from main.ry5rz5}r{5(jYjv5jZjt5ubaubj)r|5}r}5(jYX4//BIOS.addUserStartupFunction('&IpcMgr_ipcStartup');jZj1jbj!jdjjf}r~5(jjX javascriptjjjk]jj]jh]j }ji]jn]ujpMjqhjr]r5j{X4//BIOS.addUserStartupFunction('&IpcMgr_ipcStartup');r5r5}r5(jYUjZj|5ubaubjZ)r5}r5(jYUjZj1jbj!jdj]jf}r5(jh]ji]jj]jk]jn]ujpM!jqhjr]r5j`)r5}r5(jYUjcKjZj5jbj!jdjpjf}r5(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r5}r5(jYXIncrease the system stack sizer5jZj1jbj!jdjjf}r5(jh]ji]jj]jk]jn]ujpM#jqhjr]r5j{XIncrease the system stack sizer5r5}r5(jYj5jZj5ubaubj)r5}r5(jYX1//Program.stack = 0x1000; Program.stack = 0x8000;jZj1jbj!jdjjf}r5(jjX javascriptjjjk]jj]jh]j }ji]jn]ujpM%jqhjr]r5j{X1//Program.stack = 0x1000; Program.stack = 0x8000;r5r5}r5(jYUjZj5ubaubjZ)r5}r5(jYUjZj1jbj!jdj]jf}r5(jh]ji]jj]jk]jn]ujpM*jqhjr]r5j`)r5}r5(jYUjcKjZj5jbj!jdjpjf}r5(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r5}r5(jYX#Comment out the entire TICK sectionr5jZj1jbj!jdjjf}r5(jh]ji]jj]jk]jn]ujpM,jqhjr]r5j{X#Comment out the entire TICK sectionr5r5}r5(jYj5jZj5ubaubj)r5}r5(jYX=/* --------------------------- TICK --------------------------------------*/ // var Clock = xdc.useModule('ti.sysbios.knl.Clock'); // Clock.tickSource = Clock.TickSource_NULL; // //Clock.tickSource = Clock.TickSource_USER; // /* Configure BIOS clock source as GPTimer5 */ // //Clock.timerId = 0; // // var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer'); // // /* Skip the Timer frequency verification check. Need to remove this later */ // Timer.checkFrequency = false; // // /* Match this to the SYS_CLK frequency sourcing the dmTimers. // * Not needed once the SYS/BIOS family settings is updated. */ // Timer.intFreq.hi = 0; // Timer.intFreq.lo = 19200000; // // //var timerParams = new Timer.Params(); // //timerParams.period = Clock.tickPeriod; // //timerParams.periodType = Timer.PeriodType_MICROSECS; // /* Switch off Software Reset to make the below settings effective */ // //timerParams.tiocpCfg.softreset = 0x0; // /* Smart-idle wake-up-capable mode */ // //timerParams.tiocpCfg.idlemode = 0x3; // /* Wake-up generation for Overflow */ // //timerParams.twer.ovf_wup_ena = 0x1; // //Timer.create(Clock.timerId, Clock.doTick, timerParams); // // var Idle = xdc.useModule('ti.sysbios.knl.Idle'); // var Deh = xdc.useModule('ti.deh.Deh'); // // /* Must be placed before pwr mgmt */ // Idle.addFunc('&ti_deh_Deh_idleBegin');jZj1jbj!jdjjf}r5(jjX javascriptjjjk]jj]jh]j }ji]jn]ujpM.jqhjr]r5j{X=/* --------------------------- TICK --------------------------------------*/ // var Clock = xdc.useModule('ti.sysbios.knl.Clock'); // Clock.tickSource = Clock.TickSource_NULL; // //Clock.tickSource = Clock.TickSource_USER; // /* Configure BIOS clock source as GPTimer5 */ // //Clock.timerId = 0; // // var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer'); // // /* Skip the Timer frequency verification check. Need to remove this later */ // Timer.checkFrequency = false; // // /* Match this to the SYS_CLK frequency sourcing the dmTimers. // * Not needed once the SYS/BIOS family settings is updated. */ // Timer.intFreq.hi = 0; // Timer.intFreq.lo = 19200000; // // //var timerParams = new Timer.Params(); // //timerParams.period = Clock.tickPeriod; // //timerParams.periodType = Timer.PeriodType_MICROSECS; // /* Switch off Software Reset to make the below settings effective */ // //timerParams.tiocpCfg.softreset = 0x0; // /* Smart-idle wake-up-capable mode */ // //timerParams.tiocpCfg.idlemode = 0x3; // /* Wake-up generation for Overflow */ // //timerParams.twer.ovf_wup_ena = 0x1; // //Timer.create(Clock.timerId, Clock.doTick, timerParams); // // var Idle = xdc.useModule('ti.sysbios.knl.Idle'); // var Deh = xdc.useModule('ti.deh.Deh'); // // /* Must be placed before pwr mgmt */ // Idle.addFunc('&ti_deh_Deh_idleBegin');r5r5}r5(jYUjZj5ubaubjZ)r5}r5(jYUjZj1jbj!jdj]jf}r5(jh]ji]jj]jk]jn]ujpMRjqhjr]r5j`)r5}r5(jYUjcKjZj5jbj!jdjpjf}r5(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r5}r5(jYXSMake configuration change to use custom resource table. Add to the end of the file.r5jZj1jbj!jdjjf}r5(jh]ji]jj]jk]jn]ujpMTjqhjr]r5j{XSMake configuration change to use custom resource table. Add to the end of the file.r5r5}r5(jYj5jZj5ubaubj)r5}r5(jYX/* Override the default resource table with my own */ var Resource = xdc.useModule('ti.ipc.remoteproc.Resource'); Resource.customTable = true;jZj1jbj!jdjjf}r5(jjX javascriptjjjk]jj]jh]j }ji]jn]ujpMWjqhjr]r5j{X/* Override the default resource table with my own */ var Resource = xdc.useModule('ti.ipc.remoteproc.Resource'); Resource.customTable = true;r5r5}r5(jYUjZj5ubaubjZ)r5}r5(jYUjZj1jbj!jdj]jf}r5(jh]ji]jj]jk]jn]ujpM]jqhjr]r5j`)r5}r5(jYUjcKjZj5jbj!jdjpjf}r5(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjZ)r5}r5(jYUjZj1jbj!jdj]jf}r5(jh]ji]jj]jk]jn]ujpM_jqhjr]r5j`)r5}r5(jYUjcKjZj5jbj!jdjpjf}r5(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjC)r5}r5(jYUjZj1jbj!jdj`jf}r5(jGX-jk]jj]jh]ji]jn]ujpM`jqhjr]r5j/)r5}r5(jYXEdit **main_led_blink.c** jZj5jbj!jdj2jf}r5(jh]ji]jj]jk]jn]ujpNjqhjr]r5j)r5}r5(jYXEdit **main_led_blink.c**jZj5jbj!jdjjf}r5(jh]ji]jj]jk]jn]ujpM`jr]r5(j{XEdit r5r5}r5(jYXEdit jZj5ubj)r5}r5(jYX**main_led_blink.c**jf}r5(jh]ji]jj]jk]jn]ujZj5jr]r5j{Xmain_led_blink.cr5r5}r5(jYUjZj5ubajdjubeubaubaubjZ)r5}r5(jYUjZj1jbj!jdj]jf}r5(jh]ji]jj]jk]jn]ujpMbjqhjr]r5j`)r5}r5(jYUjcKjZj5jbj!jdjpjf}r5(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r5}r5(jYX'Add the following external declarationsr5jZj1jbj!jdjjf}r5(jh]ji]jj]jk]jn]ujpMdjqhjr]r5j{X'Add the following external declarationsr5r5}r5(jYj5jZj5ubaubj)r5}r5(jYX;extern Int ipc_main(); extern Void IpcMgr_ipcStartup(Void);jZj1jbj!jdjjf}r5(jjXcjjjk]jj]jh]j }ji]jn]ujpMfjqhjr]r5j{X;extern Int ipc_main(); extern Void IpcMgr_ipcStartup(Void);r5r5}r5(jYUjZj5ubaubjZ)r5}r6(jYUjZj1jbj!jdj]jf}r6(jh]ji]jj]jk]jn]ujpMkjqhjr]r6j`)r6}r6(jYUjcKjZj5jbj!jdjpjf}r6(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r6}r6(jYXTIn main(), add a call to ipc_main() and IpcMgr_ipcStartup() just before BIOS_start()r6jZj1jbj!jdjjf}r 6(jh]ji]jj]jk]jn]ujpMmjqhjr]r 6j{XTIn main(), add a call to ipc_main() and IpcMgr_ipcStartup() just before BIOS_start()r 6r 6}r 6(jYj6jZj6ubaubj)r6}r6(jYXiipc_main(); if (callIpcStartup) { IpcMgr_ipcStartup(); } /* Start BIOS */ BIOS_start(); return (0);jZj1jbj!jdjjf}r6(jjXcjjjk]jj]jh]j }ji]jn]ujpMpjqhjr]r6j{Xiipc_main(); if (callIpcStartup) { IpcMgr_ipcStartup(); } /* Start BIOS */ BIOS_start(); return (0);r6r6}r6(jYUjZj6ubaubjZ)r6}r6(jYUjZj1jbj!jdj]jf}r6(jh]ji]jj]jk]jn]ujpM|jqhjr]r6j`)r6}r6(jYUjcKjZj6jbj!jdjpjf}r6(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r6}r6(jYXComment out the line that calls Board_init(boardCfg). This call is in the original example because it assumes TI-RTOS is running on the Arm but in our case here, we are running Linux and this call is destructive so we comment it out.r6jZj1jbj!jdjjf}r6(jh]ji]jj]jk]jn]ujpM~jqhjr]r 6j{XComment out the line that calls Board_init(boardCfg). This call is in the original example because it assumes TI-RTOS is running on the Arm but in our case here, we are running Linux and this call is destructive so we comment it out.r!6r"6}r#6(jYj6jZj6ubaubj)r$6}r%6(jYX#if defined(EVM_K2E) || defined(EVM_C6678) boardCfg = BOARD_INIT_MODULE_CLOCK | BOARD_INIT_UART_STDIO; #else boardCfg = BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_MODULE_CLOCK | BOARD_INIT_UART_STDIO; #endif //Board_init(boardCfg);jZj1jbj!jdjjf}r&6(jjXcjjjk]jj]jh]j }ji]jn]ujpMjqhjr]r'6j{X#if defined(EVM_K2E) || defined(EVM_C6678) boardCfg = BOARD_INIT_MODULE_CLOCK | BOARD_INIT_UART_STDIO; #else boardCfg = BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_MODULE_CLOCK | BOARD_INIT_UART_STDIO; #endif //Board_init(boardCfg);r(6r)6}r*6(jYUjZj$6ubaubjZ)r+6}r,6(jYUjZj1jbj!jdj]jf}r-6(jh]ji]jj]jk]jn]ujpMjqhjr]r.6j`)r/6}r06(jYUjcKjZj+6jbj!jdjpjf}r16(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjZ)r26}r36(jYUjZj1jbj!jdj]jf}r46(jh]ji]jj]jk]jn]ujpMjqhjr]r56j`)r66}r76(jYUjcKjZj26jbj!jdjpjf}r86(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjC)r96}r:6(jYUjZj1jbj!jdj`jf}r;6(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]r<6j/)r=6}r>6(jYXEdit **MainDsp1.c** jZj96jbj!jdj2jf}r?6(jh]ji]jj]jk]jn]ujpNjqhjr]r@6j)rA6}rB6(jYXEdit **MainDsp1.c**jZj=6jbj!jdjjf}rC6(jh]ji]jj]jk]jn]ujpMjr]rD6(j{XEdit rE6rF6}rG6(jYXEdit jZjA6ubj)rH6}rI6(jYX**MainDsp1.c**jf}rJ6(jh]ji]jj]jk]jn]ujZjA6jr]rK6j{X MainDsp1.crL6rM6}rN6(jYUjZjH6ubajdjubeubaubaubjZ)rO6}rP6(jYUjZj1jbj!jdj]jf}rQ6(jh]ji]jj]jk]jn]ujpMjqhjr]rR6j`)rS6}rT6(jYUjcKjZjO6jbj!jdjpjf}rU6(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)rV6}rW6(jYXGThe app now has it's own main(), so rename this one and get rid of argsrX6jZj1jbj!jdjjf}rY6(jh]ji]jj]jk]jn]ujpMjqhjr]rZ6j{XGThe app now has it's own main(), so rename this one and get rid of argsr[6r\6}r]6(jYjX6jZjV6ubaubj)r^6}r_6(jYX3//Int main(Int argc, Char* argv[]) Int ipc_main() {jZj1jbj!jdjjf}r`6(jjXcjjjk]jj]jh]j }ji]jn]ujpMjqhjr]ra6j{X3//Int main(Int argc, Char* argv[]) Int ipc_main() {rb6rc6}rd6(jYUjZj^6ubaubjZ)re6}rf6(jYUjZj1jbj!jdj]jf}rg6(jh]ji]jj]jk]jn]ujpMjqhjr]rh6j`)ri6}rj6(jYUjcKjZje6jbj!jdjpjf}rk6(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)rl6}rm6(jYX+No longer using args so comment these linesrn6jZj1jbj!jdjjf}ro6(jh]ji]jj]jk]jn]ujpMjqhjr]rp6j{X+No longer using args so comment these linesrq6rr6}rs6(jYjn6jZjl6ubaubj)rt6}ru6(jYX?//taskParams.arg0 = (UArg)argc; //taskParams.arg1 = (UArg)argv;jZj1jbj!jdjjf}rv6(jjjk]jj]jh]ji]jn]ujpM2jqhjr]rw6j{X?//taskParams.arg0 = (UArg)argc; //taskParams.arg1 = (UArg)argv;rx6ry6}rz6(jYUjZjt6ubaubjZ)r{6}r|6(jYUjZj1jbj!jdj]jf}r}6(jh]ji]jj]jk]jn]ujpMjqhjr]r~6j`)r6}r6(jYUjcKjZj{6jbj!jdjpjf}r6(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r6}r6(jYX=BIOS_start() is done in the app main() so comment it out herer6jZj1jbj!jdjjf}r6(jh]ji]jj]jk]jn]ujpMjqhjr]r6j{X=BIOS_start() is done in the app main() so comment it out herer6r6}r6(jYj6jZj6ubaubj)r6}r6(jYX9/* start scheduler, this never returns */ //BIOS_start();jZj1jbj!jdjjf}r6(jjjk]jj]jh]ji]jn]ujpM;jqhjr]r6j{X9/* start scheduler, this never returns */ //BIOS_start();r6r6}r6(jYUjZj6ubaubjZ)r6}r6(jYUjZj1jbj!jdj]jf}r6(jh]ji]jj]jk]jn]ujpMjqhjr]r6j`)r6}r6(jYUjcKjZj6jbj!jdjpjf}r6(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r6}r6(jYXComment this outr6jZj1jbj!jdjjf}r6(jh]ji]jj]jk]jn]ujpMjqhjr]r6j{XComment this outr6r6}r6(jYj6jZj6ubaubj)r6}r6(jYX&//Log_print0(Diags_EXIT, "<-- main:");jZj1jbj!jdjjf}r6(jjjk]jj]jh]ji]jn]ujpMDjqhjr]r6j{X&//Log_print0(Diags_EXIT, "<-- main:");r6r6}r6(jYUjZj6ubaubjZ)r6}r6(jYUjZj1jbj!jdj]jf}r6(jh]ji]jj]jk]jn]ujpMjqhjr]r6j`)r6}r6(jYUjcKjZj6jbj!jdjpjf}r6(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjC)r6}r6(jYUjZj1jbj!jdj`jf}r6(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]r6j/)r6}r6(jYXEdit **rsc_table_vayu_dsp.c** jZj6jbj!jdj2jf}r6(jh]ji]jj]jk]jn]ujpNjqhjr]r6j)r6}r6(jYXEdit **rsc_table_vayu_dsp.c**jZj6jbj!jdjjf}r6(jh]ji]jj]jk]jn]ujpMjr]r6(j{XEdit r6r6}r6(jYXEdit jZj6ubj)r6}r6(jYX**rsc_table_vayu_dsp.c**jf}r6(jh]ji]jj]jk]jn]ujZj6jr]r6j{Xrsc_table_vayu_dsp.cr6r6}r6(jYUjZj6ubajdjubeubaubaubjZ)r6}r6(jYUjZj1jbj!jdj]jf}r6(jh]ji]jj]jk]jn]ujpMjqhjr]r6j`)r6}r6(jYUjcKjZj6jbj!jdjpjf}r6(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r6}r6(jYXDSet this #define before it's used to select PHYS_MEM_IPC_VRING valuer6jZj1jbj!jdjjf}r6(jh]ji]jj]jk]jn]ujpMjqhjr]r6j{XDSet this #define before it's used to select PHYS_MEM_IPC_VRING valuer6r6}r6(jYj6jZj6ubaubj)r6}r6(jYX#define VAYU_DSP_1jZj1jbj!jdjjf}r6(jjjk]jj]jh]ji]jn]ujpMOjqhjr]r6j{X#define VAYU_DSP_1r6r6}r6(jYUjZj6ubaubjZ)r6}r6(jYUjZj1jbj!jdj]jf}r6(jh]ji]jj]jk]jn]ujpMjqhjr]r6j`)r6}r6(jYUjcKjZj6jbj!jdjpjf}r6(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r6}r6(jYX:Add this extern declaration prior to the symbol being usedr6jZj1jbj!jdjjf}r6(jh]ji]jj]jk]jn]ujpMjqhjr]r6j{X:Add this extern declaration prior to the symbol being usedr6r6}r6(jYj6jZj6ubaubj)r6}r6(jYX5extern char ti_trace_SysMin_Module_State_0_outbuf__A;jZj1jbj!jdjjf}r6(jjjk]jj]jh]ji]jn]ujpMVjqhjr]r6j{X5extern char ti_trace_SysMin_Module_State_0_outbuf__A;r6r6}r6(jYUjZj6ubaubjZ)r6}r6(jYUjZj1jbj!jdj]jf}r6(jh]ji]jj]jk]jn]ujpMjqhjr]r6j`)r6}r6(jYUjcKjZj6jbj!jdjpjf}r6(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjC)r6}r6(jYUjZj1jbj!jdj`jf}r6(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]r6j/)r6}r6(jYXEdit **Server.c** jZj6jbj!jdj2jf}r6(jh]ji]jj]jk]jn]ujpNjqhjr]r6j)r6}r7(jYXEdit **Server.c**jZj6jbj!jdjjf}r7(jh]ji]jj]jk]jn]ujpMjr]r7(j{XEdit r7r7}r7(jYXEdit jZj6ubj)r7}r7(jYX **Server.c**jf}r7(jh]ji]jj]jk]jn]ujZj6jr]r 7j{XServer.cr 7r 7}r 7(jYUjZj7ubajdjubeubaubaubjZ)r 7}r7(jYUjZj1jbj!jdj]jf}r7(jh]ji]jj]jk]jn]ujpMjqhjr]r7j`)r7}r7(jYUjcKjZj 7jbj!jdjpjf}r7(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjZ)r7}r7(jYUjZj1jbj!jdj]jf}r7(jh]ji]jj]jk]jn]ujpMjqhjr]r7j`)r7}r7(jYUjcKjZj7jbj!jdjpjf}r7(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r7}r7(jYX3No longer have shared folder so change include pathr7jZj1jbj!jdjjf}r7(jh]ji]jj]jk]jn]ujpMjqhjr]r7j{X3No longer have shared folder so change include pathr 7r!7}r"7(jYj7jZj7ubaubj)r#7}r$7(jYXU/* local header files */ //#include "../shared/AppCommon.h" #include "../AppCommon.h"jZj1jbj!jdjjf}r%7(jjjk]jj]jh]ji]jn]ujpMbjqhjr]r&7j{XU/* local header files */ //#include "../shared/AppCommon.h" #include "../AppCommon.h"r'7r(7}r)7(jYUjZj#7ubaubjZ)r*7}r+7(jYUjZj1jbj!jdj]jf}r,7(jh]ji]jj]jk]jn]ujpMjqhjr]r-7j`)r.7}r/7(jYUjcKjZj*7jbj!jdjpjf}r07(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r17}r27(jYXDownload the Full CCS Projectr37jZj1jbj!jdjjf}r47(jk]r57Udownload-the-full-ccs-projectr67ajj]jh]ji]jn]r77haujpNjqhjr]r87j{XDownload the Full CCS Projectr97r:7}r;7(jYj37jZj17ubaubjZ)r<7}r=7(jYUjZj1jbj!jdj]jf}r>7(jh]ji]jj]jk]jn]ujpMjqhjr]r?7j`)r@7}rA7(jYUjcKjZj<7jbj!jdjpjf}rB7(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)rC7}rD7(jYX`GPIO_LedBlink_evmAM572x_c66xExampleProject_with_ipc.zip `__rE7jZj1jbj!jdjjf}rF7(jh]ji]jj]jk]jn]ujpMjqhjr]rG7j)rH7}rI7(jYjE7jf}rJ7(UnameX7GPIO_LedBlink_evmAM572x_c66xExampleProject_with_ipc.zipjXahttp://processors.wiki.ti.com/images/c/c9/GPIO_LedBlink_evmAM572x_c66xExampleProject_with_ipc.zipjk]jj]jh]ji]jn]ujZjC7jr]rK7j{X7GPIO_LedBlink_evmAM572x_c66xExampleProject_with_ipc.ziprL7rM7}rN7(jYUjZjH7ubajdjubaubj)rO7}rP7(jYX8Adding IPC to an existing TI RTOS application on the IPUrQ7jZj1jbj!jdjjf}rR7(jk]rS7U8adding-ipc-to-an-existing-ti-rtos-application-on-the-ipurT7ajj]jh]ji]jn]rU7hgaujpNjqhjr]rV7j{X8Adding IPC to an existing TI RTOS application on the IPUrW7rX7}rY7(jYjQ7jZjO7ubaubjZ)rZ7}r[7(jYUjZj1jbj!jdj]jf}r\7(jh]ji]jj]jk]jn]ujpMjqhjr]r]7j`)r^7}r_7(jYUjcKjZjZ7jbj!jdjpjf}r`7(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)ra7}rb7(jYXLA common thing people want to do is take an existing IPU application that may be controlling serial or control interfaces and add IPC to it so that the firmware can be loaded from the ARM. This is common when migrating from a IPU only solution to a heterogeneous SoC with an MPUSS (ARM) and IPUSS. This is the focus of this section.rc7jZj1jbj!jdjjf}rd7(jh]ji]jj]jk]jn]ujpMjqhjr]re7j{XLA common thing people want to do is take an existing IPU application that may be controlling serial or control interfaces and add IPC to it so that the firmware can be loaded from the ARM. This is common when migrating from a IPU only solution to a heterogeneous SoC with an MPUSS (ARM) and IPUSS. This is the focus of this section.rf7rg7}rh7(jYjc7jZja7ubaubjZ)ri7}rj7(jYUjZj1jbj!jdj]jf}rk7(jh]ji]jj]jk]jn]ujpMjqhjr]rl7j`)rm7}rn7(jYUjcKjZji7jbj!jdjpjf}ro7(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)rp7}rq7(jYXzIn order to describe this process, we need an example TI RTOS test case to work with. For this purpose, we'll be using the UART_BasicExample_evmAM572x_m4ExampleProject example that's part of the PDK (installed as part of the Processor SDK RTOS). This example uses TI RTOS and does serial IO using UART3 port on the AM572x GP EVM, it's labeled Serial Debug on the EVM silkscreen.rr7jZj1jbj!jdjjf}rs7(jh]ji]jj]jk]jn]ujpMjqhjr]rt7j{XzIn order to describe this process, we need an example TI RTOS test case to work with. For this purpose, we'll be using the UART_BasicExample_evmAM572x_m4ExampleProject example that's part of the PDK (installed as part of the Processor SDK RTOS). This example uses TI RTOS and does serial IO using UART3 port on the AM572x GP EVM, it's labeled Serial Debug on the EVM silkscreen.ru7rv7}rw7(jYjr7jZjp7ubaubjZ)rx7}ry7(jYUjZj1jbj!jdj]jf}rz7(jh]ji]jj]jk]jn]ujpMjqhjr]r{7j`)r|7}r}7(jYUjcKjZjx7jbj!jdjpjf}r~7(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r7}r7(jYXuThere were several steps taken to make this whole process work, each of which will be described in following sectionsr7jZj1jbj!jdjjf}r7(jh]ji]jj]jk]jn]ujpMjqhjr]r7j{XuThere were several steps taken to make this whole process work, each of which will be described in following sectionsr7r7}r7(jYj7jZj7ubaubj%)r7}r7(jYUjZj1jbj!jdj(jf}r7(j*U.jk]jj]jh]j+Uji]jn]j,j-ujpMjqhjr]r7(j/)r7}r7(jYXXBuild and run the out-of-box UART M4 example on the EVM using Code Composer Studio (CCS)jZj7jbj!jdj2jf}r7(jh]ji]jj]jk]jn]ujpNjqhjr]r7j)r7}r7(jYXXBuild and run the out-of-box UART M4 example on the EVM using Code Composer Studio (CCS)r7jZj7jbj!jdjjf}r7(jh]ji]jj]jk]jn]ujpMjr]r7j{XXBuild and run the out-of-box UART M4 example on the EVM using Code Composer Studio (CCS)r7r7}r7(jYj7jZj7ubaubaubj/)r7}r7(jYX"Build and run the ex02_messageQ example from the IPC software bundle and turn it into a CCS project. Build it and modify the Linux startup code to use this new image. This is just a sanity check step to make sure we can build the IPC examples in CCS and have them run at boot up on the EVM.jZj7jbj!jdj2jf}r7(jh]ji]jj]jk]jn]ujpNjqhjr]r7j)r7}r7(jYX"Build and run the ex02_messageQ example from the IPC software bundle and turn it into a CCS project. Build it and modify the Linux startup code to use this new image. This is just a sanity check step to make sure we can build the IPC examples in CCS and have them run at boot up on the EVM.r7jZj7jbj!jdjjf}r7(jh]ji]jj]jk]jn]ujpMjr]r7j{X"Build and run the ex02_messageQ example from the IPC software bundle and turn it into a CCS project. Build it and modify the Linux startup code to use this new image. This is just a sanity check step to make sure we can build the IPC examples in CCS and have them run at boot up on the EVM.r7r7}r7(jYj7jZj7ubaubaubj/)r7}r7(jYXIn CCS, make a clone of the out-of-box UART M4 example and rename it to denote it's the IPC version of the example. Then using the ex02_messageq example as a reference, add in the IPC pieces to the UART example code. Build from CCS then add it to the Linux firmware folder. jZj7jbj!jdj2jf}r7(jh]ji]jj]jk]jn]ujpNjqhjr]r7j)r7}r7(jYXIn CCS, make a clone of the out-of-box UART M4 example and rename it to denote it's the IPC version of the example. Then using the ex02_messageq example as a reference, add in the IPC pieces to the UART example code. Build from CCS then add it to the Linux firmware folder.r7jZj7jbj!jdjjf}r7(jh]ji]jj]jk]jn]ujpMjr]r7j{XIn CCS, make a clone of the out-of-box UART M4 example and rename it to denote it's the IPC version of the example. Then using the ex02_messageq example as a reference, add in the IPC pieces to the UART example code. Build from CCS then add it to the Linux firmware folder.r7r7}r7(jYj7jZj7ubaubaubeubj)r7}r7(jYX,Running UART Read/Write PDK Example from CCSr7jZj1jbj!jdjjf}r7(jk]r7U+running-uart-readwrite-pdk-example-from-ccsr7ajj]jh]ji]jn]r7h aujpNjqhjr]r7j{X,Running UART Read/Write PDK Example from CCSr7r7}r7(jYj7jZj7ubaubj)r7}r7(jYXDevelopers are required to run pdkProjectCreate script to generate this example as described in the `Processor SDK RTOS wiki article `__.jZj1jbj!jdjjf}r7(jh]ji]jj]jk]jn]ujpMjqhjr]r7(j{XdDevelopers are required to run pdkProjectCreate script to generate this example as described in the r7r7}r7(jYXdDevelopers are required to run pdkProjectCreate script to generate this example as described in the jZj7ubj)r7}r7(jYXa`Processor SDK RTOS wiki article `__jf}r7(UnameXProcessor SDK RTOS wiki articlejX;index_how_to_guides.html#rebuild-drivers-from-pdk-directoryjk]jj]jh]ji]jn]ujZj7jr]r7j{XProcessor SDK RTOS wiki articler7r7}r7(jYUjZj7ubajdjubj{X.r7}r7(jYX.jZj7ubeubj)r7}r7(jYXDFor the UART M4 example run the script with the following arguments:r7jZj1jbj!jdjjf}r7(jh]ji]jj]jk]jn]ujpM jqhjr]r7j{XDFor the UART M4 example run the script with the following arguments:r7r7}r7(jYj7jZj7ubaubj)r7}r7(jYX4pdkProjectCreate.bat AM572x evmAM572x little uart m4jZj1jbj!jdjjf}r7(jjjk]jj]jh]ji]jn]ujpMjqhjr]r7j{X4pdkProjectCreate.bat AM572x evmAM572x little uart m4r7r7}r7(jYUjZj7ubaubjZ)r7}r7(jYUjZj1jbj!jdj]jf}r7(jh]ji]jj]jk]jn]ujpMjqhjr]r7(j`)r7}r7(jYUjcKjZj7jbj!jdjpjf}r7(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)r7}r7(jYUjcKjZj7jbj!jdjpjf}r7(jh]ji]jj]jk]jn]ujpKjqhjr]ubeubj)r7}r7(jYXAfter you run the script, you can find the UART M4 example project at /pdk_am57xx_1_0_4/packages/MyExampleProjects/UART_BasicExample_evmAM572x_m4ExampleProject.r7jZj1jbj!jdjjf}r7(jh]ji]jj]jk]jn]ujpMjqhjr]r7j{XAfter you run the script, you can find the UART M4 example project at /pdk_am57xx_1_0_4/packages/MyExampleProjects/UART_BasicExample_evmAM572x_m4ExampleProject.r7r7}r7(jYj7jZj7ubaubj)r7}r7(jYXImport the project in CCS and build the example. You can now connect to the EVM using an emulator and CCS using the instructions provided here: http://processors.wiki.ti.com/index.php/AM572x_GP_EVM_Hardware_SetupjZj1jbj!jdjjf}r7(jh]ji]jj]jk]jn]ujpMjqhjr]r7(j{XImport the project in CCS and build the example. You can now connect to the EVM using an emulator and CCS using the instructions provided here: r7r7}r7(jYXImport the project in CCS and build the example. You can now connect to the EVM using an emulator and CCS using the instructions provided here: jZj7ubj)r7}r7(jYXDhttp://processors.wiki.ti.com/index.php/AM572x_GP_EVM_Hardware_Setupr7jf}r7(Urefurij7jk]jj]jh]ji]jn]ujZj7jr]r7j{XDhttp://processors.wiki.ti.com/index.php/AM572x_GP_EVM_Hardware_Setupr7r7}r7(jYUjZj7ubajdjubeubj)r7}r7(jYXConnect to the ARM core and make sure GEL runs multicore initialization and brings the IPUSS out of reset. Connect to IPU2 core0 and load and run the M4 UART example. When you run the code you should see the following log on the serial IO console:r7jZj1jbj!jdjjf}r7(jh]ji]jj]jk]jn]ujpMjqhjr]r7j{XConnect to the ARM core and make sure GEL runs multicore initialization and brings the IPUSS out of reset. Connect to IPU2 core0 and load and run the M4 UART example. When you run the code you should see the following log on the serial IO console:r7r8}r8(jYj7jZj7ubaubj)r8}r8(jYXuart driver and utils example test cases : Enter 16 characters or press Esc 1234567890123456 <- user input Data received is 1234567890123456 <- loopback from user input uart driver and utils example test cases : Enter 16 characters or press EscjZj1jbj!jdjjf}r8(jjjk]jj]jh]ji]jn]ujpMjqhjr]r8j{Xuart driver and utils example test cases : Enter 16 characters or press Esc 1234567890123456 <- user input Data received is 1234567890123456 <- loopback from user input uart driver and utils example test cases : Enter 16 characters or press Escr8r8}r8(jYUjZj8ubaubjZ)r 8}r 8(jYUjZj1jbj!jdj]jf}r 8(jh]ji]jj]jk]jn]ujpM*jqhjr]r 8j`)r 8}r8(jYUjcKjZj 8jbj!jdjpjf}r8(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjZ)r8}r8(jYUjZj1jbj!jdj]jf}r8(jh]ji]jj]jk]jn]ujpM,jqhjr]r8j`)r8}r8(jYUjcKjZj8jbj!jdjpjf}r8(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r8}r8(jYX'Build and Run ex02_messageq IPC exampler8jZj1jbj!jdjjf}r8(jk]r8U'build-and-run-ex02-messageq-ipc-exampler8ajj]jh]ji]jn]r8haujpNjqhjr]r8j{X'Build and Run ex02_messageq IPC exampler8r 8}r!8(jYj8jZj8ubaubj)r"8}r#8(jYXFollow instructions described in Article `Run IPC Linux Examples `__jZj1jbj!jdjjf}r$8(jh]ji]jj]jk]jn]ujpM1jqhjr]r%8(j{X)Follow instructions described in Article r&8r'8}r(8(jYX)Follow instructions described in Article jZj"8ubj)r)8}r*8(jYX`Run IPC Linux Examples `__jf}r+8(UnameXRun IPC Linux ExamplesjXbhttp://processors.wiki.ti.com/index.php/Processor_SDK_IPC_Quick_Start_Guide#Run_IPC_Linux_examplesjk]jj]jh]ji]jn]ujZj"8jr]r,8j{XRun IPC Linux Examplesr-8r.8}r/8(jYUjZj)8ubajdjubeubj)r08}r18(jYXLUpdate Linux Kernel device tree to remove UART that will be controlled by M4r28jZj1jbj!jdjjf}r38(jk]r48ULupdate-linux-kernel-device-tree-to-remove-uart-that-will-be-controlled-by-m4r58ajj]jh]ji]jn]r68j&aujpNjqhjr]r78j{XLUpdate Linux Kernel device tree to remove UART that will be controlled by M4r88r98}r:8(jYj28jZj08ubaubj)r;8}r<8(jYXLinux kernel enables all SOC HW modules which are required for its configuration. Appropriate drivers configure required clocks and initialize HW registers. For all unused IPs clocks are not configured.r=8jZj1jbj!jdjjf}r>8(jh]ji]jj]jk]jn]ujpM8jqhjr]r?8j{XLinux kernel enables all SOC HW modules which are required for its configuration. Appropriate drivers configure required clocks and initialize HW registers. For all unused IPs clocks are not configured.r@8rA8}rB8(jYj=8jZj;8ubaubj)rC8}rD8(jYXrThe uart3 node is disabled in kernel using device tree. Also this restricts kernel to put those IPs to sleep mode.rE8jZj1jbj!jdjjf}rF8(jh]ji]jj]jk]jn]ujpM<jqhjr]rG8j{XrThe uart3 node is disabled in kernel using device tree. Also this restricts kernel to put those IPs to sleep mode.rH8rI8}rJ8(jYjE8jZjC8ubaubj)rK8}rL8(jYX4&uart3 { status = "disabled"; ti,no-idle; };jZj1jbj!jdjjf}rM8(jjjk]jj]jh]ji]jn]ujpMjqhjr]rN8j{X4&uart3 { status = "disabled"; ti,no-idle; };rO8rP8}rQ8(jYUjZjK8ubaubj)rR8}rS8(jYXAdd IPC to the UART ExamplerT8jZj1jbj!jdjjf}rU8(jk]rV8Uadd-ipc-to-the-uart-examplerW8ajj]jh]ji]jn]rX8haujpNjqhjr]rY8j{XAdd IPC to the UART ExamplerZ8r[8}r\8(jYjT8jZjR8ubaubj)r]8}r^8(jYXThe first step is to clone our out-of-box UART example CCS project and rename it to denote it's using IPC. The easiest way to do this is using CCS. Here are the steps...r_8jZj1jbj!jdjjf}r`8(jh]ji]jj]jk]jn]ujpMIjqhjr]ra8j{XThe first step is to clone our out-of-box UART example CCS project and rename it to denote it's using IPC. The easiest way to do this is using CCS. Here are the steps...rb8rc8}rd8(jYj_8jZj]8ubaubjC)re8}rf8(jYUjZj1jbj!jdj`jf}rg8(jGX-jk]jj]jh]ji]jn]ujpMMjqhjr]rh8(j/)ri8}rj8(jYXIn the *Edit* perspective, go into your *Project Explorer* window and right click on your UART_BasicExample_evmAM572x_m4ExampleProject project and select *copy* from the pop-up menu. Maske sure the project is not is a closed state.jZje8jbj!jdj2jf}rk8(jh]ji]jj]jk]jn]ujpNjqhjr]rl8j)rm8}rn8(jYXIn the *Edit* perspective, go into your *Project Explorer* window and right click on your UART_BasicExample_evmAM572x_m4ExampleProject project and select *copy* from the pop-up menu. Maske sure the project is not is a closed state.jZji8jbj!jdjjf}ro8(jh]ji]jj]jk]jn]ujpMMjr]rp8(j{XIn the rq8rr8}rs8(jYXIn the jZjm8ubj')rt8}ru8(jYX*Edit*jf}rv8(jh]ji]jj]jk]jn]ujZjm8jr]rw8j{XEditrx8ry8}rz8(jYUjZjt8ubajdj'ubj{X perspective, go into your r{8r|8}r}8(jYX perspective, go into your jZjm8ubj')r~8}r8(jYX*Project Explorer*jf}r8(jh]ji]jj]jk]jn]ujZjm8jr]r8j{XProject Explorerr8r8}r8(jYUjZj~8ubajdj'ubj{X` window and right click on your UART_BasicExample_evmAM572x_m4ExampleProject project and select r8r8}r8(jYX` window and right click on your UART_BasicExample_evmAM572x_m4ExampleProject project and select jZjm8ubj')r8}r8(jYX*copy*jf}r8(jh]ji]jj]jk]jn]ujZjm8jr]r8j{Xcopyr8r8}r8(jYUjZj8ubajdj'ubj{XG from the pop-up menu. Maske sure the project is not is a closed state.r8r8}r8(jYXG from the pop-up menu. Maske sure the project is not is a closed state.jZjm8ubeubaubj/)r8}r8(jYXLRick click in and empty area of the project explorer window and select past.jZje8jbj!jdj2jf}r8(jh]ji]jj]jk]jn]ujpNjqhjr]r8j)r8}r8(jYXLRick click in and empty area of the project explorer window and select past.r8jZj8jbj!jdjjf}r8(jh]ji]jj]jk]jn]ujpMQjr]r8j{XLRick click in and empty area of the project explorer window and select past.r8r8}r8(jYj8jZj8ubaubaubj/)r8}r8(jYXA dialog box pops up, modify the name to denote it's using IPC. A good name is UART_BasicExample_evmAM572x_m4ExampleProject_with_ipc. jZje8jbj!jdj2jf}r8(jh]ji]jj]jk]jn]ujpNjqhjr]r8j)r8}r8(jYXA dialog box pops up, modify the name to denote it's using IPC. A good name is UART_BasicExample_evmAM572x_m4ExampleProject_with_ipc.r8jZj8jbj!jdjjf}r8(jh]ji]jj]jk]jn]ujpMSjr]r8j{XA dialog box pops up, modify the name to denote it's using IPC. A good name is UART_BasicExample_evmAM572x_m4ExampleProject_with_ipc.r8r8}r8(jYj8jZj8ubaubaubeubjZ)r8}r8(jYUjZj1jbj!jdj]jf}r8(jh]ji]jj]jk]jn]ujpMVjqhjr]r8j`)r8}r8(jYUjcKjZj8jbj!jdjpjf}r8(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r8}r8(jYXThis is the project we'll be working with from here on. The next thing we want to do is select the proper RTSC platform and other components. To do this, follow these steps.r8jZj1jbj!jdjjf}r8(jh]ji]jj]jk]jn]ujpMXjqhjr]r8j{XThis is the project we'll be working with from here on. The next thing we want to do is select the proper RTSC platform and other components. To do this, follow these steps.r8r8}r8(jYj8jZj8ubaubjC)r8}r8(jYUjZj1jbj!jdj`jf}r8(jGX-jk]jj]jh]ji]jn]ujpM\jqhjr]r8(j/)r8}r8(jYXhRight click on the UART_BasicExample_evmAM572x_m4ExampleProject_with_ipc project and select *Properties*jZj8jbj!jdj2jf}r8(jh]ji]jj]jk]jn]ujpNjqhjr]r8j)r8}r8(jYXhRight click on the UART_BasicExample_evmAM572x_m4ExampleProject_with_ipc project and select *Properties*jZj8jbj!jdjjf}r8(jh]ji]jj]jk]jn]ujpM\jr]r8(j{X\Right click on the UART_BasicExample_evmAM572x_m4ExampleProject_with_ipc project and select r8r8}r8(jYX\Right click on the UART_BasicExample_evmAM572x_m4ExampleProject_with_ipc project and select jZj8ubj')r8}r8(jYX *Properties*jf}r8(jh]ji]jj]jk]jn]ujZj8jr]r8j{X Propertiesr8r8}r8(jYUjZj8ubajdj'ubeubaubj/)r8}r8(jYX.In the left hand pane, click on *CCS General*.r8jZj8jbj!jdj2jf}r8(jh]ji]jj]jk]jn]ujpNjqhjr]r8j)r8}r8(jYj8jZj8jbj!jdjjf}r8(jh]ji]jj]jk]jn]ujpM_jr]r8(j{X In the left hand pane, click on r8r8}r8(jYX In the left hand pane, click on jZj8ubj')r8}r8(jYX *CCS General*jf}r8(jh]ji]jj]jk]jn]ujZj8jr]r8j{X CCS Generalr8r8}r8(jYUjZj8ubajdj'ubj{X.r8}r8(jYX.jZj8ubeubaubj/)r8}r8(jYX/On the right hand side, click on the *RTSC* tabr8jZj8jbj!jdj2jf}r8(jh]ji]jj]jk]jn]ujpNjqhjr]r8j)r8}r8(jYj8jZj8jbj!jdjjf}r8(jh]ji]jj]jk]jn]ujpM`jr]r8(j{X%On the right hand side, click on the r8r8}r8(jYX%On the right hand side, click on the jZj8ubj')r8}r8(jYX*RTSC*jf}r8(jh]ji]jj]jk]jn]ujZj8jr]r8j{XRTSCr8r8}r8(jYUjZj8ubajdj'ubj{X tabr8r8}r8(jYX tabjZj8ubeubaubj/)r8}r8(jYX-For *XDCtools version:* select 3.xx.x.xx_corer8jZj8jbj!jdj2jf}r8(jh]ji]jj]jk]jn]ujpNjqhjr]r8j)r8}r9(jYj8jZj8jbj!jdjjf}r9(jh]ji]jj]jk]jn]ujpMajr]r9(j{XFor r9r9}r9(jYXFor jZj8ubj')r9}r9(jYX*XDCtools version:*jf}r9(jh]ji]jj]jk]jn]ujZj8jr]r 9j{XXDCtools version:r 9r 9}r 9(jYUjZj9ubajdj'ubj{X select 3.xx.x.xx_corer 9r9}r9(jYX select 3.xx.x.xx_corejZj8ubeubaubj/)r9}r9(jYXIn the list of *Products and Repositories*, *check* the following... - IPC 3.xx.x.xx - SYS/BIOS 6.4x.x.xx - am57xx PDK x.x.x jZj8jbNjdj2jf}r9(jh]ji]jj]jk]jn]ujpNjqhjr]r9(j)r9}r9(jYXDIn the list of *Products and Repositories*, *check* the following...jZj9jbj!jdjjf}r9(jh]ji]jj]jk]jn]ujpMbjr]r9(j{XIn the list of r9r9}r9(jYXIn the list of jZj9ubj')r9}r9(jYX*Products and Repositories*jf}r9(jh]ji]jj]jk]jn]ujZj9jr]r9j{XProducts and Repositoriesr9r 9}r!9(jYUjZj9ubajdj'ubj{X, r"9r#9}r$9(jYX, jZj9ubj')r%9}r&9(jYX*check*jf}r'9(jh]ji]jj]jk]jn]ujZj9jr]r(9j{Xcheckr)9r*9}r+9(jYUjZj%9ubajdj'ubj{X the following...r,9r-9}r.9(jYX the following...jZj9ubeubjC)r/9}r09(jYUjf}r19(jGX-jk]jj]jh]ji]jn]ujZj9jr]r29(j/)r39}r49(jYX IPC 3.xx.x.xxr59jf}r69(jh]ji]jj]jk]jn]ujZj/9jr]r79j)r89}r99(jYj59jZj39jbj!jdjjf}r:9(jh]ji]jj]jk]jn]ujpMdjr]r;9j{X IPC 3.xx.x.xxr<9r=9}r>9(jYj59jZj89ubaubajdj2ubj/)r?9}r@9(jYXSYS/BIOS 6.4x.x.xxrA9jf}rB9(jh]ji]jj]jk]jn]ujZj/9jr]rC9j)rD9}rE9(jYjA9jZj?9jbj!jdjjf}rF9(jh]ji]jj]jk]jn]ujpMejr]rG9j{XSYS/BIOS 6.4x.x.xxrH9rI9}rJ9(jYjA9jZjD9ubaubajdj2ubj/)rK9}rL9(jYXam57xx PDK x.x.x jf}rM9(jh]ji]jj]jk]jn]ujZj/9jr]rN9j)rO9}rP9(jYXam57xx PDK x.x.xrQ9jZjK9jbj!jdjjf}rR9(jh]ji]jj]jk]jn]ujpMfjr]rS9j{Xam57xx PDK x.x.xrT9rU9}rV9(jYjQ9jZjO9ubaubajdj2ubejdj`ubeubj/)rW9}rX9(jYX.For *Target*, select **ti.targets.arm.elf.M4**rY9jZj8jbj!jdj2jf}rZ9(jh]ji]jj]jk]jn]ujpNjqhjr]r[9j)r\9}r]9(jYjY9jZjW9jbj!jdjjf}r^9(jh]ji]jj]jk]jn]ujpMhjr]r_9(j{XFor r`9ra9}rb9(jYXFor jZj\9ubj')rc9}rd9(jYX*Target*jf}re9(jh]ji]jj]jk]jn]ujZj\9jr]rf9j{XTargetrg9rh9}ri9(jYUjZjc9ubajdj'ubj{X , select rj9rk9}rl9(jYX , select jZj\9ubj)rm9}rn9(jYX**ti.targets.arm.elf.M4**jf}ro9(jh]ji]jj]jk]jn]ujZj\9jr]rp9j{Xti.targets.arm.elf.M4rq9rr9}rs9(jYUjZjm9ubajdjubeubaubj/)rt9}ru9(jYX1For *Platform*, select **ti.platforms.evmDRA7XX**rv9jZj8jbj!jdj2jf}rw9(jh]ji]jj]jk]jn]ujpNjqhjr]rx9j)ry9}rz9(jYjv9jZjt9jbj!jdjjf}r{9(jh]ji]jj]jk]jn]ujpMijr]r|9(j{XFor r}9r~9}r9(jYXFor jZjy9ubj')r9}r9(jYX *Platform*jf}r9(jh]ji]jj]jk]jn]ujZjy9jr]r9j{XPlatformr9r9}r9(jYUjZj9ubajdj'ubj{X , select r9r9}r9(jYX , select jZjy9ubj)r9}r9(jYX**ti.platforms.evmDRA7XX**jf}r9(jh]ji]jj]jk]jn]ujZjy9jr]r9j{Xti.platforms.evmDRA7XXr9r9}r9(jYUjZj9ubajdjubeubaubj/)r9}r9(jYXOnce the platform is selected, edit its name buy hand and append :ipu2 to the end. After this it should be ti.platforms.evmDRA7XX:ipu2jZj8jbj!jdj2jf}r9(jh]ji]jj]jk]jn]ujpNjqhjr]r9j)r9}r9(jYXOnce the platform is selected, edit its name buy hand and append :ipu2 to the end. After this it should be ti.platforms.evmDRA7XX:ipu2r9jZj9jbj!jdjjf}r9(jh]ji]jj]jk]jn]ujpMjjr]r9j{XOnce the platform is selected, edit its name buy hand and append :ipu2 to the end. After this it should be ti.platforms.evmDRA7XX:ipu2r9r9}r9(jYj9jZj9ubaubaubj/)r9}r9(jYX4Go ahead and leave the *Build-profile* set to debug.r9jZj8jbj!jdj2jf}r9(jh]ji]jj]jk]jn]ujpNjqhjr]r9j)r9}r9(jYj9jZj9jbj!jdjjf}r9(jh]ji]jj]jk]jn]ujpMmjr]r9(j{XGo ahead and leave the r9r9}r9(jYXGo ahead and leave the jZj9ubj')r9}r9(jYX*Build-profile*jf}r9(jh]ji]jj]jk]jn]ujZj9jr]r9j{X Build-profiler9r9}r9(jYUjZj9ubajdj'ubj{X set to debug.r9r9}r9(jYX set to debug.jZj9ubeubaubj/)r9}r9(jYXHit the OK button. jZj8jbj!jdj2jf}r9(jh]ji]jj]jk]jn]ujpNjqhjr]r9j)r9}r9(jYXHit the OK button.r9jZj9jbj!jdjjf}r9(jh]ji]jj]jk]jn]ujpMnjr]r9j{XHit the OK button.r9r9}r9(jYj9jZj9ubaubaubeubjZ)r9}r9(jYUjZj1jbj!jdj]jf}r9(jh]ji]jj]jk]jn]ujpMpjqhjr]r9j`)r9}r9(jYUjcKjZj9jbj!jdjpjf}r9(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r9}r9(jYXYNow we want to copy configuration and source files from the ex02_messageq IPC example into our project. The IPC example is located at *C:/ti/ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf/ex02_messageq*. To copy files into your CCS project, you can simply select the files you want in Windows explorer then drag and drop them into your project in CCS.jZj1jbj!jdjjf}r9(jh]ji]jj]jk]jn]ujpMrjqhjr]r9(j{XNow we want to copy configuration and source files from the ex02_messageq IPC example into our project. The IPC example is located at r9r9}r9(jYXNow we want to copy configuration and source files from the ex02_messageq IPC example into our project. The IPC example is located at jZj9ubj')r9}r9(jYX>*C:/ti/ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf/ex02_messageq*jf}r9(jh]ji]jj]jk]jn]ujZj9jr]r9j{X<C:/ti/ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf/ex02_messageqr9r9}r9(jYUjZj9ubajdj'ubj{X. To copy files into your CCS project, you can simply select the files you want in Windows explorer then drag and drop them into your project in CCS.r9r9}r9(jYX. To copy files into your CCS project, you can simply select the files you want in Windows explorer then drag and drop them into your project in CCS.jZj9ubeubj)r9}r9(jYX)Copy these files into your CCS project...r9jZj1jbj!jdjjf}r9(jh]ji]jj]jk]jn]ujpMyjqhjr]r9j{X)Copy these files into your CCS project...r9r9}r9(jYj9jZj9ubaubjC)r9}r9(jYUjZj1jbj!jdj`jf}r9(jGX-jk]jj]jh]ji]jn]ujpM{jqhjr]r9(j/)r9}r9(jYXOC:/ti/ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf/ex02_messageq/shared/AppCommon.hr9jZj9jbj!jdj2jf}r9(jh]ji]jj]jk]jn]ujpNjqhjr]r9j)r9}r9(jYj9jZj9jbj!jdjjf}r9(jh]ji]jj]jk]jn]ujpM{jr]r9j{XOC:/ti/ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf/ex02_messageq/shared/AppCommon.hr9r9}r9(jYj9jZj9ubaubaubj/)r9}r9(jYXNC:/ti/ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf/ex02_messageq/shared/config.bldr9jZj9jbj!jdj2jf}r9(jh]ji]jj]jk]jn]ujpNjqhjr]r9j)r9}r9(jYj9jZj9jbj!jdjjf}r9(jh]ji]jj]jk]jn]ujpM|jr]r9j{XNC:/ti/ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf/ex02_messageq/shared/config.bldr9r9}r9(jYj9jZj9ubaubaubj/)r9}r9(jYXOC:/ti/ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf/ex02_messageq/shared/ipc.cfg.xs jZj9jbj!jdj2jf}r9(jh]ji]jj]jk]jn]ujpNjqhjr]r9j)r9}r:(jYXNC:/ti/ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf/ex02_messageq/shared/ipc.cfg.xsr:jZj9jbj!jdjjf}r:(jh]ji]jj]jk]jn]ujpM}jr]r:j{XNC:/ti/ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf/ex02_messageq/shared/ipc.cfg.xsr:r:}r:(jYj:jZj9ubaubaubeubjZ)r:}r:(jYUjZj1jbj!jdj]jf}r :(jh]ji]jj]jk]jn]ujpMjqhjr]r :j`)r :}r :(jYUjcKjZj:jbj!jdjpjf}r :(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r:}r:(jYX-Now copy these files into your CCS project...r:jZj1jbj!jdjjf}r:(jh]ji]jj]jk]jn]ujpMjqhjr]r:j{X-Now copy these files into your CCS project...r:r:}r:(jYj:jZj:ubaubjC)r:}r:(jYUjZj1jbj!jdj`jf}r:(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]r:(j/)r:}r:(jYXJC:/ti/ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf/ex02_messageq/ipu2/Ipu2.cfgr:jZj:jbj!jdj2jf}r:(jh]ji]jj]jk]jn]ujpNjqhjr]r:j)r:}r :(jYj:jZj:jbj!jdjjf}r!:(jh]ji]jj]jk]jn]ujpMjr]r":j{XJC:/ti/ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf/ex02_messageq/ipu2/Ipu2.cfgr#:r$:}r%:(jYj:jZj:ubaubaubj/)r&:}r':(jYXLC:/ti/ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf/ex02_messageq/ipu2/MainIpu2.cr(:jZj:jbj!jdj2jf}r):(jh]ji]jj]jk]jn]ujpNjqhjr]r*:j)r+:}r,:(jYj(:jZj&:jbj!jdjjf}r-:(jh]ji]jj]jk]jn]ujpMjr]r.:j{XLC:/ti/ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf/ex02_messageq/ipu2/MainIpu2.cr/:r0:}r1:(jYj(:jZj+:ubaubaubj/)r2:}r3:(jYXJC:/ti/ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf/ex02_messageq/ipu2/Server.cr4:jZj:jbj!jdj2jf}r5:(jh]ji]jj]jk]jn]ujpNjqhjr]r6:j)r7:}r8:(jYj4:jZj2:jbj!jdjjf}r9:(jh]ji]jj]jk]jn]ujpMjr]r::j{XJC:/ti/ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf/ex02_messageq/ipu2/Server.cr;:r<:}r=:(jYj4:jZj7:ubaubaubj/)r>:}r?:(jYXKC:/ti/ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf/ex02_messageq/ipu2/Server.h jZj:jbj!jdj2jf}r@:(jh]ji]jj]jk]jn]ujpNjqhjr]rA:j)rB:}rC:(jYXJC:/ti/ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf/ex02_messageq/ipu2/Server.hrD:jZj>:jbj!jdjjf}rE:(jh]ji]jj]jk]jn]ujpMjr]rF:j{XJC:/ti/ipc_3_xx_xx_xx/examples/DRA7XX_linux_elf/ex02_messageq/ipu2/Server.hrG:rH:}rI:(jYjD:jZjB:ubaubaubeubj)rJ:}rK:(jYX7When you copy Ipu2.cfg into your CCS project, it should show up greyed out. If not, right click and exclude it from build. This is because the UART example already has a cfg file (uart_m4_evmAM572x.cfg). The Ipu2.cfg will be used for copying and pasting. When it's all done, you can delete it from your project.jZj1jbj!jdjjf}rL:(jh]ji]jj]jk]jn]ujpNjqhjr]rM:j)rN:}rO:(jYX7When you copy Ipu2.cfg into your CCS project, it should show up greyed out. If not, right click and exclude it from build. This is because the UART example already has a cfg file (uart_m4_evmAM572x.cfg). The Ipu2.cfg will be used for copying and pasting. When it's all done, you can delete it from your project.rP:jZjJ:jbj!jdjjf}rQ:(jh]ji]jj]jk]jn]ujpMjr]rR:j{X7When you copy Ipu2.cfg into your CCS project, it should show up greyed out. If not, right click and exclude it from build. This is because the UART example already has a cfg file (uart_m4_evmAM572x.cfg). The Ipu2.cfg will be used for copying and pasting. When it's all done, you can delete it from your project.rS:rT:}rU:(jYjP:jZjN:ubaubaubj)rV:}rW:(jYXiFinally, you will likely want to use a custom resource table so copy these files into your CCS project...rX:jZj1jbj!jdjjf}rY:(jh]ji]jj]jk]jn]ujpMjqhjr]rZ:j{XiFinally, you will likely want to use a custom resource table so copy these files into your CCS project...r[:r\:}r]:(jYjX:jZjV:ubaubjC)r^:}r_:(jYUjZj1jbj!jdj`jf}r`:(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]ra:(j/)rb:}rc:(jYXDC:/ti/ipc_3_xx_xx_xx/packages/ti/ipc/remoteproc/rsc_table_vayu_ipu.hrd:jZj^:jbj!jdj2jf}re:(jh]ji]jj]jk]jn]ujpNjqhjr]rf:j)rg:}rh:(jYjd:jZjb:jbj!jdjjf}ri:(jh]ji]jj]jk]jn]ujpMjr]rj:j{XDC:/ti/ipc_3_xx_xx_xx/packages/ti/ipc/remoteproc/rsc_table_vayu_ipu.hrk:rl:}rm:(jYjd:jZjg:ubaubaubj/)rn:}ro:(jYX<C:/ti/ipc_3_xx_xx_xx/packages/ti/ipc/remoteproc/rsc_types.h jZj^:jbj!jdj2jf}rp:(jh]ji]jj]jk]jn]ujpNjqhjr]rq:j)rr:}rs:(jYX;C:/ti/ipc_3_xx_xx_xx/packages/ti/ipc/remoteproc/rsc_types.hrt:jZjn:jbj!jdjjf}ru:(jh]ji]jj]jk]jn]ujpMjr]rv:j{X;C:/ti/ipc_3_xx_xx_xx/packages/ti/ipc/remoteproc/rsc_types.hrw:rx:}ry:(jYjt:jZjr:ubaubaubeubj)rz:}r{:(jYX`The rsc_table_vayu_dsp.h file defines an initialized structure so let's make a *.c* source file.jZj1jbj!jdjjf}r|:(jh]ji]jj]jk]jn]ujpMjqhjr]r}:(j{XOThe rsc_table_vayu_dsp.h file defines an initialized structure so let's make a r~:r:}r:(jYXOThe rsc_table_vayu_dsp.h file defines an initialized structure so let's make a jZjz:ubj')r:}r:(jYX*.c*jf}r:(jh]ji]jj]jk]jn]ujZjz:jr]r:j{X.cr:r:}r:(jYUjZj:ubajdj'ubj{X source file.r:r:}r:(jYX source file.jZjz:ubeubjC)r:}r:(jYUjZj1jbj!jdj`jf}r:(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]r:j/)r:}r:(jYXIIn your CCS project, rename rsc_table_vayu_ipu.h to rsc_table_vayu_ipu.c jZj:jbj!jdj2jf}r:(jh]ji]jj]jk]jn]ujpNjqhjr]r:j)r:}r:(jYXHIn your CCS project, rename rsc_table_vayu_ipu.h to rsc_table_vayu_ipu.cr:jZj:jbj!jdjjf}r:(jh]ji]jj]jk]jn]ujpMjr]r:j{XHIn your CCS project, rename rsc_table_vayu_ipu.h to rsc_table_vayu_ipu.cr:r:}r:(jYj:jZj:ubaubaubaubjZ)r:}r:(jYUjZj1jbj!jdj]jf}r:(jh]ji]jj]jk]jn]ujpMjqhjr]r:j`)r:}r:(jYUjcKjZj:jbj!jdjpjf}r:(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r:}r:(jYX~Now we want to *merge* the IPC example configuration file with the LED blink example configuration file. Follow these steps...jZj1jbj!jdjjf}r:(jh]ji]jj]jk]jn]ujpMjqhjr]r:(j{XNow we want to r:r:}r:(jYXNow we want to jZj:ubj')r:}r:(jYX*merge*jf}r:(jh]ji]jj]jk]jn]ujZj:jr]r:j{Xmerger:r:}r:(jYUjZj:ubajdj'ubj{Xh the IPC example configuration file with the LED blink example configuration file. Follow these steps...r:r:}r:(jYXh the IPC example configuration file with the LED blink example configuration file. Follow these steps...jZj:ubeubjC)r:}r:(jYUjZj1jbj!jdj`jf}r:(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]r:(j/)r:}r:(jYXOpen up *Ipu2.cfg* using a text editor (don't open it using the GUI). Right click on it and select *Open With -> XDCscript Editor*jZj:jbj!jdj2jf}r:(jh]ji]jj]jk]jn]ujpNjqhjr]r:j)r:}r:(jYXOpen up *Ipu2.cfg* using a text editor (don't open it using the GUI). Right click on it and select *Open With -> XDCscript Editor*jZj:jbj!jdjjf}r:(jh]ji]jj]jk]jn]ujpMjr]r:(j{XOpen up r:r:}r:(jYXOpen up jZj:ubj')r:}r:(jYX *Ipu2.cfg*jf}r:(jh]ji]jj]jk]jn]ujZj:jr]r:j{XIpu2.cfgr:r:}r:(jYUjZj:ubajdj'ubj{XQ using a text editor (don't open it using the GUI). Right click on it and select r:r:}r:(jYXQ using a text editor (don't open it using the GUI). Right click on it and select jZj:ubj')r:}r:(jYX*Open With -> XDCscript Editor*jf}r:(jh]ji]jj]jk]jn]ujZj:jr]r:j{XOpen With -> XDCscript Editorr:r:}r:(jYUjZj:ubajdj'ubeubaubj/)r:}r:(jYXLWe want to copy the entire contents into the clipboard. Select all and copy.jZj:jbj!jdj2jf}r:(jh]ji]jj]jk]jn]ujpNjqhjr]r:j)r:}r:(jYXLWe want to copy the entire contents into the clipboard. Select all and copy.r:jZj:jbj!jdjjf}r:(jh]ji]jj]jk]jn]ujpMjr]r:j{XLWe want to copy the entire contents into the clipboard. Select all and copy.r:r:}r:(jYj:jZj:ubaubaubj/)r:}r:(jYXNow just like above, open the uart_m4_evmAM572x.cfg config file in the text editor. Go to the very bottom and *paste* in the contents from the Ipu2.cfg file. Basically we've appended the contents of Ipu2.cfg into uart_m4_evmAM572x.cfg. jZj:jbj!jdj2jf}r:(jh]ji]jj]jk]jn]ujpNjqhjr]r:j)r:}r:(jYXNow just like above, open the uart_m4_evmAM572x.cfg config file in the text editor. Go to the very bottom and *paste* in the contents from the Ipu2.cfg file. Basically we've appended the contents of Ipu2.cfg into uart_m4_evmAM572x.cfg.jZj:jbj!jdjjf}r:(jh]ji]jj]jk]jn]ujpMjr]r:(j{XnNow just like above, open the uart_m4_evmAM572x.cfg config file in the text editor. Go to the very bottom and r:r:}r:(jYXnNow just like above, open the uart_m4_evmAM572x.cfg config file in the text editor. Go to the very bottom and jZj:ubj')r:}r:(jYX*paste*jf}r:(jh]ji]jj]jk]jn]ujZj:jr]r:j{Xpaster:r:}r:(jYUjZj:ubajdj'ubj{Xv in the contents from the Ipu2.cfg file. Basically we've appended the contents of Ipu2.cfg into uart_m4_evmAM572x.cfg.r:r:}r:(jYXv in the contents from the Ipu2.cfg file. Basically we've appended the contents of Ipu2.cfg into uart_m4_evmAM572x.cfg.jZj:ubeubaubeubjZ)r:}r:(jYUjZj1jbj!jdj]jf}r:(jh]ji]jj]jk]jn]ujpMjqhjr]r:j`)r:}r:(jYUjcKjZj:jbj!jdjpjf}r:(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r:}r:(jYXWe've now added in all the necessary configuration and source files into our project. Don't expect it to build at this point, we have to make edits first. These edits are listed below.r:jZj1jbj!jdjjf}r:(jh]ji]jj]jk]jn]ujpMjqhjr]r:j{XWe've now added in all the necessary configuration and source files into our project. Don't expect it to build at this point, we have to make edits first. These edits are listed below.r;r;}r;(jYj:jZj:ubaubj)r;}r;(jYXxYou can download the full CCS project with source files to use as a reference. See link towards the end of this section.jZj1jbj!jdjjf}r;(jh]ji]jj]jk]jn]ujpNjqhjr]r;j)r;}r;(jYXxYou can download the full CCS project with source files to use as a reference. See link towards the end of this section.r ;jZj;jbj!jdjjf}r ;(jh]ji]jj]jk]jn]ujpMjr]r ;j{XxYou can download the full CCS project with source files to use as a reference. See link towards the end of this section.r ;r ;}r;(jYj ;jZj;ubaubaubjC)r;}r;(jYUjZj1jbj!jdj`jf}r;(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]r;j/)r;}r;(jYXEdit **uart_m4_evmAM572x.cfg** jZj;jbj!jdj2jf}r;(jh]ji]jj]jk]jn]ujpNjqhjr]r;j)r;}r;(jYXEdit **uart_m4_evmAM572x.cfg**jZj;jbj!jdjjf}r;(jh]ji]jj]jk]jn]ujpMjr]r;(j{XEdit r;r;}r;(jYXEdit jZj;ubj)r;}r;(jYX**uart_m4_evmAM572x.cfg**jf}r ;(jh]ji]jj]jk]jn]ujZj;jr]r!;j{Xuart_m4_evmAM572x.cfgr";r#;}r$;(jYUjZj;ubajdjubeubaubaubjZ)r%;}r&;(jYUjZj1jbj!jdj]jf}r';(jh]ji]jj]jk]jn]ujpMjqhjr]r(;j`)r);}r*;(jYUjcKjZj%;jbj!jdjpjf}r+;(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r,;}r-;(jYXIAdd the following to the beginning(at the top) of your configuration filer.;jZj1jbj!jdjjf}r/;(jh]ji]jj]jk]jn]ujpMjqhjr]r0;j{XIAdd the following to the beginning(at the top) of your configuration filer1;r2;}r3;(jYj.;jZj,;ubaubj)r4;}r5;(jYX/var Program = xdc.useModule('xdc.cfg.Program');jZj1jbj!jdjjf}r6;(jjjk]jj]jh]ji]jn]ujpMGjqhjr]r7;j{X/var Program = xdc.useModule('xdc.cfg.Program');r8;r9;}r:;(jYUjZj4;ubaubjZ)r;;}r<;(jYUjZj1jbj!jdj]jf}r=;(jh]ji]jj]jk]jn]ujpMjqhjr]r>;j`)r?;}r@;(jYUjcKjZj;;jbj!jdjpjf}rA;(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjZ)rB;}rC;(jYUjZj1jbj!jdj]jf}rD;(jh]ji]jj]jk]jn]ujpMjqhjr]rE;j`)rF;}rG;(jYUjcKjZjB;jbj!jdjpjf}rH;(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)rI;}rJ;(jYXGSince we are no longer using a shared folder, make the following changerK;jZj1jbj!jdjjf}rL;(jh]ji]jj]jk]jn]ujpMjqhjr]rM;j{XGSince we are no longer using a shared folder, make the following changerN;rO;}rP;(jYjK;jZjI;ubaubj)rQ;}rR;(jYXh//var ipc_cfg = xdc.loadCapsule("../shared/ipc.cfg.xs"); var ipc_cfg = xdc.loadCapsule("../ipc.cfg.xs");jZj1jbj!jdjjf}rS;(jjjk]jj]jh]ji]jn]ujpMQjqhjr]rT;j{Xh//var ipc_cfg = xdc.loadCapsule("../shared/ipc.cfg.xs"); var ipc_cfg = xdc.loadCapsule("../ipc.cfg.xs");rU;rV;}rW;(jYUjZjQ;ubaubjZ)rX;}rY;(jYUjZj1jbj!jdj]jf}rZ;(jh]ji]jj]jk]jn]ujpMjqhjr]r[;j`)r\;}r];(jYUjcKjZjX;jbj!jdjpjf}r^;(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r_;}r`;(jYXMComment out the following. We'll be calling this function directly from main.ra;jZj1jbj!jdjjf}rb;(jh]ji]jj]jk]jn]ujpMjqhjr]rc;j{XMComment out the following. We'll be calling this function directly from main.rd;re;}rf;(jYja;jZj_;ubaubj)rg;}rh;(jYX4//BIOS.addUserStartupFunction('&IpcMgr_ipcStartup');jZj1jbj!jdjjf}ri;(jjjk]jj]jh]ji]jn]ujpM[jqhjr]rj;j{X4//BIOS.addUserStartupFunction('&IpcMgr_ipcStartup');rk;rl;}rm;(jYUjZjg;ubaubjZ)rn;}ro;(jYUjZj1jbj!jdj]jf}rp;(jh]ji]jj]jk]jn]ujpMjqhjr]rq;j`)rr;}rs;(jYUjcKjZjn;jbj!jdjpjf}rt;(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)ru;}rv;(jYXIncrease the system stack sizerw;jZj1jbj!jdjjf}rx;(jh]ji]jj]jk]jn]ujpMjqhjr]ry;j{XIncrease the system stack sizerz;r{;}r|;(jYjw;jZju;ubaubj)r};}r~;(jYX1//Program.stack = 0x1000; Program.stack = 0x8000;jZj1jbj!jdjjf}r;(jjjk]jj]jh]ji]jn]ujpMcjqhjr]r;j{X1//Program.stack = 0x1000; Program.stack = 0x8000;r;r;}r;(jYUjZj};ubaubjZ)r;}r;(jYUjZj1jbj!jdj]jf}r;(jh]ji]jj]jk]jn]ujpMjqhjr]r;j`)r;}r;(jYUjcKjZj;jbj!jdjpjf}r;(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r;}r;(jYX#Comment out the entire TICK sectionr;jZj1jbj!jdjjf}r;(jh]ji]jj]jk]jn]ujpMjqhjr]r;j{X#Comment out the entire TICK sectionr;r;}r;(jYj;jZj;ubaubj)r;}r;(jYX=/* --------------------------- TICK --------------------------------------*/ // var Clock = xdc.useModule('ti.sysbios.knl.Clock'); // Clock.tickSource = Clock.TickSource_NULL; // //Clock.tickSource = Clock.TickSource_USER; // /* Configure BIOS clock source as GPTimer5 */ // //Clock.timerId = 0; // // var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer'); // // /* Skip the Timer frequency verification check. Need to remove this later */ // Timer.checkFrequency = false; // // /* Match this to the SYS_CLK frequency sourcing the dmTimers. // * Not needed once the SYS/BIOS family settings is updated. */ // Timer.intFreq.hi = 0; // Timer.intFreq.lo = 19200000; // // //var timerParams = new Timer.Params(); // //timerParams.period = Clock.tickPeriod; // //timerParams.periodType = Timer.PeriodType_MICROSECS; // /* Switch off Software Reset to make the below settings effective */ // //timerParams.tiocpCfg.softreset = 0x0; // /* Smart-idle wake-up-capable mode */ // //timerParams.tiocpCfg.idlemode = 0x3; // /* Wake-up generation for Overflow */ // //timerParams.twer.ovf_wup_ena = 0x1; // //Timer.create(Clock.timerId, Clock.doTick, timerParams); // // var Idle = xdc.useModule('ti.sysbios.knl.Idle'); // var Deh = xdc.useModule('ti.deh.Deh'); // // /* Must be placed before pwr mgmt */ // Idle.addFunc('&ti_deh_Deh_idleBegin');jZj1jbj!jdjjf}r;(jjjk]jj]jh]ji]jn]ujpMljqhjr]r;j{X=/* --------------------------- TICK --------------------------------------*/ // var Clock = xdc.useModule('ti.sysbios.knl.Clock'); // Clock.tickSource = Clock.TickSource_NULL; // //Clock.tickSource = Clock.TickSource_USER; // /* Configure BIOS clock source as GPTimer5 */ // //Clock.timerId = 0; // // var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer'); // // /* Skip the Timer frequency verification check. Need to remove this later */ // Timer.checkFrequency = false; // // /* Match this to the SYS_CLK frequency sourcing the dmTimers. // * Not needed once the SYS/BIOS family settings is updated. */ // Timer.intFreq.hi = 0; // Timer.intFreq.lo = 19200000; // // //var timerParams = new Timer.Params(); // //timerParams.period = Clock.tickPeriod; // //timerParams.periodType = Timer.PeriodType_MICROSECS; // /* Switch off Software Reset to make the below settings effective */ // //timerParams.tiocpCfg.softreset = 0x0; // /* Smart-idle wake-up-capable mode */ // //timerParams.tiocpCfg.idlemode = 0x3; // /* Wake-up generation for Overflow */ // //timerParams.twer.ovf_wup_ena = 0x1; // //Timer.create(Clock.timerId, Clock.doTick, timerParams); // // var Idle = xdc.useModule('ti.sysbios.knl.Idle'); // var Deh = xdc.useModule('ti.deh.Deh'); // // /* Must be placed before pwr mgmt */ // Idle.addFunc('&ti_deh_Deh_idleBegin');r;r;}r;(jYUjZj;ubaubjZ)r;}r;(jYUjZj1jbj!jdj]jf}r;(jh]ji]jj]jk]jn]ujpMjqhjr]r;j`)r;}r;(jYUjcKjZj;jbj!jdjpjf}r;(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r;}r;(jYXSMake configuration change to use custom resource table. Add to the end of the file.r;jZj1jbj!jdjjf}r;(jh]ji]jj]jk]jn]ujpMjqhjr]r;j{XSMake configuration change to use custom resource table. Add to the end of the file.r;r;}r;(jYj;jZj;ubaubj)r;}r;(jYX/* Override the default resource table with my own */ var Resource = xdc.useModule('ti.ipc.remoteproc.Resource'); Resource.customTable = true;jZj1jbj!jdjjf}r;(jjjk]jj]jh]ji]jn]ujpMjqhjr]r;j{X/* Override the default resource table with my own */ var Resource = xdc.useModule('ti.ipc.remoteproc.Resource'); Resource.customTable = true;r;r;}r;(jYUjZj;ubaubjZ)r;}r;(jYUjZj1jbj!jdj]jf}r;(jh]ji]jj]jk]jn]ujpM jqhjr]r;j`)r;}r;(jYUjcKjZj;jbj!jdjpjf}r;(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjZ)r;}r;(jYUjZj1jbj!jdj]jf}r;(jh]ji]jj]jk]jn]ujpMjqhjr]r;j`)r;}r;(jYUjcKjZj;jbj!jdjpjf}r;(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjC)r;}r;(jYUjZj1jbj!jdj`jf}r;(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]r;j/)r;}r;(jYXEdit **main_uart_example.c** jZj;jbj!jdj2jf}r;(jh]ji]jj]jk]jn]ujpNjqhjr]r;j)r;}r;(jYXEdit **main_uart_example.c**jZj;jbj!jdjjf}r;(jh]ji]jj]jk]jn]ujpMjr]r;(j{XEdit r;r;}r;(jYXEdit jZj;ubj)r;}r;(jYX**main_uart_example.c**jf}r;(jh]ji]jj]jk]jn]ujZj;jr]r;j{Xmain_uart_example.cr;r;}r;(jYUjZj;ubajdjubeubaubaubjZ)r;}r;(jYUjZj1jbj!jdj]jf}r;(jh]ji]jj]jk]jn]ujpMjqhjr]r;j`)r;}r;(jYUjcKjZj;jbj!jdjpjf}r;(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r;}r;(jYX'Add the following external declarationsr;jZj1jbj!jdjjf}r;(jh]ji]jj]jk]jn]ujpMjqhjr]r;j{X'Add the following external declarationsr;r;}r;(jYj;jZj;ubaubj)r;}r;(jYX;extern Int ipc_main(); extern Void IpcMgr_ipcStartup(Void);jZj1jbj!jdjjf}r;(jjjk]jj]jh]ji]jn]ujpMjqhjr]r;j{X;extern Int ipc_main(); extern Void IpcMgr_ipcStartup(Void);r;r;}r;(jYUjZj;ubaubjZ)r;}r;(jYUjZj1jbj!jdj]jf}r;(jh]ji]jj]jk]jn]ujpMjqhjr]r;j`)r;}r;(jYUjcKjZj;jbj!jdjpjf}r;(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r;}r;(jYXTIn main(), add a call to ipc_main() and IpcMgr_ipcStartup() just before BIOS_start()r;jZj1jbj!jdjjf}r;(jh]ji]jj]jk]jn]ujpMjqhjr]r;j{XTIn main(), add a call to ipc_main() and IpcMgr_ipcStartup() just before BIOS_start()r;r;}r;(jYj;jZj;ubaubj)r;}r;(jYXjipc_main(); if (callIpcStartup) { IpcMgr_ipcStartup(); } /* Start BIOS */ BIOS_start(); return (0);jZj1jbj!jdjjf}r;(jjXcjjjk]jj]jh]j }ji]jn]ujpM jqhjr]r;j{Xjipc_main(); if (callIpcStartup) { IpcMgr_ipcStartup(); } /* Start BIOS */ BIOS_start(); return (0);r;r;}r;(jYUjZj;ubaubjZ)r<}r<(jYUjZj1jbj!jdj]jf}r<(jh]ji]jj]jk]jn]ujpM*jqhjr]r<j`)r<}r<(jYUjcKjZj<jbj!jdjpjf}r<(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r<}r<(jYXMComment out the line that calls Board_init(boardCfg). This call is in the original example because it assumes TI-RTOS is running on the Arm but in our case here, we are running Linux and this call is destructive so we comment it out. The board init call does all pinmux configuration, module clock and UART peripheral initialization.r <jZj1jbj!jdjjf}r <(jh]ji]jj]jk]jn]ujpM,jqhjr]r <j{XMComment out the line that calls Board_init(boardCfg). This call is in the original example because it assumes TI-RTOS is running on the Arm but in our case here, we are running Linux and this call is destructive so we comment it out. The board init call does all pinmux configuration, module clock and UART peripheral initialization.r <r <}r<(jYj <jZj<ubaubj)r<}r<(jYX=In order to run the UART Example on M4, you need to disable the UART in the Linux DTB file and interact with the Linux kernel using Telnet (This will be described later in the article). Since Linux will be running uboot performs the pinmux configuration but clock and UART Stdio setup needs to be performed by the M4.r<jZj1jbj!jdjjf}r<(jh]ji]jj]jk]jn]ujpM2jqhjr]r<j{X=In order to run the UART Example on M4, you need to disable the UART in the Linux DTB file and interact with the Linux kernel using Telnet (This will be described later in the article). Since Linux will be running uboot performs the pinmux configuration but clock and UART Stdio setup needs to be performed by the M4.r<r<}r<(jYj<jZj<ubaubjZ)r<}r<(jYUjZj1jbj!jdj]jf}r<(jh]ji]jj]jk]jn]ujpM8jqhjr]r<j`)r<}r<(jYUjcKjZj<jbj!jdjpjf}r<(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r<}r<(jYX**Original code**r <jZj1jbj!jdjjf}r!<(jh]ji]jj]jk]jn]ujpM9jqhjr]r"<j)r#<}r$<(jYj <jf}r%<(jh]ji]jj]jk]jn]ujZj<jr]r&<j{X Original coder'<r(<}r)<(jYUjZj#<ubajdjubaubj)r*<}r+<(jYX#if defined(EVM_K2E) || defined(EVM_C6678) boardCfg = BOARD_INIT_MODULE_CLOCK | BOARD_INIT_UART_STDIO; #else boardCfg = BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_MODULE_CLOCK | BOARD_INIT_UART_STDIO; #endif Board_init(boardCfg);jZj1jbj!jdjjf}r,<(jjXcjjjk]jj]jh]j }ji]jn]ujpM;jqhjr]r-<j{X#if defined(EVM_K2E) || defined(EVM_C6678) boardCfg = BOARD_INIT_MODULE_CLOCK | BOARD_INIT_UART_STDIO; #else boardCfg = BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_MODULE_CLOCK | BOARD_INIT_UART_STDIO; #endif Board_init(boardCfg);r.<r/<}r0<(jYUjZj*<ubaubjZ)r1<}r2<(jYUjZj1jbj!jdj]jf}r3<(jh]ji]jj]jk]jn]ujpMDjqhjr]r4<j`)r5<}r6<(jYUjcKjZj1<jbj!jdjpjf}r7<(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjZ)r8<}r9<(jYUjZj1jbj!jdj]jf}r:<(jh]ji]jj]jk]jn]ujpMFjqhjr]r;<j`)r<<}r=<(jYUjcKjZj8<jbj!jdjpjf}r><(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r?<}r@<(jYX**Modified Code :**rA<jZj1jbj!jdjjf}rB<(jh]ji]jj]jk]jn]ujpMGjqhjr]rC<j)rD<}rE<(jYjA<jf}rF<(jh]ji]jj]jk]jn]ujZj?<jr]rG<j{XModified Code :rH<rI<}rJ<(jYUjZjD<ubajdjubaubj)rK<}rL<(jYX7boardCfg = BOARD_INIT_UART_STDIO; Board_init(boardCfg);jZj1jbj!jdjjf}rM<(jjXcjjjk]jj]jh]j }ji]jn]ujpMIjqhjr]rN<j{X7boardCfg = BOARD_INIT_UART_STDIO; Board_init(boardCfg);rO<rP<}rQ<(jYUjZjK<ubaubjZ)rR<}rS<(jYUjZj1jbj!jdj]jf}rT<(jh]ji]jj]jk]jn]ujpMNjqhjr]rU<j`)rV<}rW<(jYUjcKjZjR<jbj!jdjpjf}rX<(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)rY<}rZ<(jYXWe are not done yet as we still need to configure turn the clock control on for the UART without impacting the other clocks. We can do that by adding the following code before Board_init API call:r[<jZj1jbj!jdjjf}r\<(jh]ji]jj]jk]jn]ujpMPjqhjr]r]<j{XWe are not done yet as we still need to configure turn the clock control on for the UART without impacting the other clocks. We can do that by adding the following code before Board_init API call:r^<r_<}r`<(jYj[<jZjY<ubaubj)ra<}rb<(jYXCSL_l4per_cm_core_componentRegs *l4PerCmReg = (CSL_l4per_cm_core_componentRegs *)CSL_MPU_L4PER_CM_CORE_REGS; CSL_FINST(l4PerCmReg->CM_L4PER_UART3_CLKCTRL_REG, L4PER_CM_CORE_COMPONENT_CM_L4PER_UART3_CLKCTRL_REG_MODULEMODE, ENABLE); while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_UART3_CLKCTRL_REG_IDLEST_FUNC != CSL_FEXT(l4PerCmReg->CM_L4PER_UART3_CLKCTRL_REG, L4PER_CM_CORE_COMPONENT_CM_L4PER_UART3_CLKCTRL_REG_IDLEST));jZj1jbj!jdjjf}rc<(jjjk]jj]jh]ji]jn]ujpMjqhjr]rd<j{XCSL_l4per_cm_core_componentRegs *l4PerCmReg = (CSL_l4per_cm_core_componentRegs *)CSL_MPU_L4PER_CM_CORE_REGS; CSL_FINST(l4PerCmReg->CM_L4PER_UART3_CLKCTRL_REG, L4PER_CM_CORE_COMPONENT_CM_L4PER_UART3_CLKCTRL_REG_MODULEMODE, ENABLE); while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_UART3_CLKCTRL_REG_IDLEST_FUNC != CSL_FEXT(l4PerCmReg->CM_L4PER_UART3_CLKCTRL_REG, L4PER_CM_CORE_COMPONENT_CM_L4PER_UART3_CLKCTRL_REG_IDLEST));re<rf<}rg<(jYUjZja<ubaubjC)rh<}ri<(jYUjZj1jbj!jdj`jf}rj<(jGX-jk]jj]jh]ji]jn]ujpM^jqhjr]rk<j/)rl<}rm<(jYXEdit **MainIpu2.c** jZjh<jbj!jdj2jf}rn<(jh]ji]jj]jk]jn]ujpNjqhjr]ro<j)rp<}rq<(jYXEdit **MainIpu2.c**jZjl<jbj!jdjjf}rr<(jh]ji]jj]jk]jn]ujpM^jr]rs<(j{XEdit rt<ru<}rv<(jYXEdit jZjp<ubj)rw<}rx<(jYX**MainIpu2.c**jf}ry<(jh]ji]jj]jk]jn]ujZjp<jr]rz<j{X MainIpu2.cr{<r|<}r}<(jYUjZjw<ubajdjubeubaubaubjZ)r~<}r<(jYUjZj1jbj!jdj]jf}r<(jh]ji]jj]jk]jn]ujpM`jqhjr]r<j`)r<}r<(jYUjcKjZj~<jbj!jdjpjf}r<(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r<}r<(jYXGThe app now has it's own main(), so rename this one and get rid of argsr<jZj1jbj!jdjjf}r<(jh]ji]jj]jk]jn]ujpMbjqhjr]r<j{XGThe app now has it's own main(), so rename this one and get rid of argsr<r<}r<(jYj<jZj<ubaubj)r<}r<(jYX3//Int main(Int argc, Char* argv[]) Int ipc_main() {jZj1jbj!jdjjf}r<(jjXcjjjk]jj]jh]j }ji]jn]ujpMdjqhjr]r<j{X3//Int main(Int argc, Char* argv[]) Int ipc_main() {r<r<}r<(jYUjZj<ubaubj)r<}r<(jYX+No longer using args so comment these linesr<jZj1jbj!jdjjf}r<(jh]ji]jj]jk]jn]ujpMjjqhjr]r<j{X+No longer using args so comment these linesr<r<}r<(jYj<jZj<ubaubj)r<}r<(jYX?//taskParams.arg0 = (UArg)argc; //taskParams.arg1 = (UArg)argv;jZj1jbj!jdjjf}r<(jjjk]jj]jh]ji]jn]ujpMjqhjr]r<j{X?//taskParams.arg0 = (UArg)argc; //taskParams.arg1 = (UArg)argv;r<r<}r<(jYUjZj<ubaubj)r<}r<(jYX=BIOS_start() is done in the app main() so comment it out herer<jZj1jbj!jdjjf}r<(jh]ji]jj]jk]jn]ujpMqjqhjr]r<j{X=BIOS_start() is done in the app main() so comment it out herer<r<}r<(jYj<jZj<ubaubj)r<}r<(jYX9/* start scheduler, this never returns */ //BIOS_start();jZj1jbj!jdjjf}r<(jjjk]jj]jh]ji]jn]ujpMjqhjr]r<j{X9/* start scheduler, this never returns */ //BIOS_start();r<r<}r<(jYUjZj<ubaubjZ)r<}r<(jYUjZj1jbj!jdj]jf}r<(jh]ji]jj]jk]jn]ujpMxjqhjr]r<j`)r<}r<(jYUjcKjZj<jbj!jdjpjf}r<(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r<}r<(jYXComment this outr<jZj1jbj!jdjjf}r<(jh]ji]jj]jk]jn]ujpMzjqhjr]r<j{XComment this outr<r<}r<(jYj<jZj<ubaubj)r<}r<(jYX&//Log_print0(Diags_EXIT, "<-- main:");jZj1jbj!jdjjf}r<(jjjk]jj]jh]ji]jn]ujpM jqhjr]r<j{X&//Log_print0(Diags_EXIT, "<-- main:");r<r<}r<(jYUjZj<ubaubjZ)r<}r<(jYUjZj1jbj!jdj]jf}r<(jh]ji]jj]jk]jn]ujpMjqhjr]r<j`)r<}r<(jYUjcKjZj<jbj!jdjpjf}r<(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjC)r<}r<(jYUjZj1jbj!jdj`jf}r<(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]r<j/)r<}r<(jYXEdit **rsc_table_vayu_ipu.c** jZj<jbj!jdj2jf}r<(jh]ji]jj]jk]jn]ujpNjqhjr]r<j)r<}r<(jYXEdit **rsc_table_vayu_ipu.c**jZj<jbj!jdjjf}r<(jh]ji]jj]jk]jn]ujpMjr]r<(j{XEdit r<r<}r<(jYXEdit jZj<ubj)r<}r<(jYX**rsc_table_vayu_ipu.c**jf}r<(jh]ji]jj]jk]jn]ujZj<jr]r<j{Xrsc_table_vayu_ipu.cr<r<}r<(jYUjZj<ubajdjubeubaubaubjZ)r<}r<(jYUjZj1jbj!jdj]jf}r<(jh]ji]jj]jk]jn]ujpMjqhjr]r<j`)r<}r<(jYUjcKjZj<jbj!jdjpjf}r<(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r<}r<(jYXDSet this #define before it's used to select PHYS_MEM_IPC_VRING valuer<jZj1jbj!jdjjf}r<(jh]ji]jj]jk]jn]ujpMjqhjr]r<j{XDSet this #define before it's used to select PHYS_MEM_IPC_VRING valuer<r<}r<(jYj<jZj<ubaubj)r<}r<(jYX#define VAYU_IPU_2jZj1jbj!jdjjf}r<(jjjk]jj]jh]ji]jn]ujpMjqhjr]r<j{X#define VAYU_IPU_2r<r<}r<(jYUjZj<ubaubjZ)r<}r<(jYUjZj1jbj!jdj]jf}r<(jh]ji]jj]jk]jn]ujpMjqhjr]r<j`)r<}r=(jYUjcKjZj<jbj!jdjpjf}r=(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r=}r=(jYX:Add this extern declaration prior to the symbol being usedr=jZj1jbj!jdjjf}r=(jh]ji]jj]jk]jn]ujpMjqhjr]r=j{X:Add this extern declaration prior to the symbol being usedr=r=}r =(jYj=jZj=ubaubj)r =}r =(jYX5extern char ti_trace_SysMin_Module_State_0_outbuf__A;jZj1jbj!jdjjf}r =(jjjk]jj]jh]ji]jn]ujpMjqhjr]r =j{X5extern char ti_trace_SysMin_Module_State_0_outbuf__A;r=r=}r=(jYUjZj =ubaubjZ)r=}r=(jYUjZj1jbj!jdj]jf}r=(jh]ji]jj]jk]jn]ujpMjqhjr]r=j`)r=}r=(jYUjcKjZj=jbj!jdjpjf}r=(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjZ)r=}r=(jYUjZj1jbj!jdj]jf}r=(jh]ji]jj]jk]jn]ujpMjqhjr]r=j`)r=}r=(jYUjcKjZj=jbj!jdjpjf}r=(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjC)r=}r =(jYUjZj1jbj!jdj`jf}r!=(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]r"=j/)r#=}r$=(jYXEdit **Server.c** jZj=jbj!jdj2jf}r%=(jh]ji]jj]jk]jn]ujpNjqhjr]r&=j)r'=}r(=(jYXEdit **Server.c**jZj#=jbj!jdjjf}r)=(jh]ji]jj]jk]jn]ujpMjr]r*=(j{XEdit r+=r,=}r-=(jYXEdit jZj'=ubj)r.=}r/=(jYX **Server.c**jf}r0=(jh]ji]jj]jk]jn]ujZj'=jr]r1=j{XServer.cr2=r3=}r4=(jYUjZj.=ubajdjubeubaubaubjZ)r5=}r6=(jYUjZj1jbj!jdj]jf}r7=(jh]ji]jj]jk]jn]ujpMjqhjr]r8=j`)r9=}r:=(jYUjcKjZj5=jbj!jdjpjf}r;=(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r<=}r==(jYX3No longer have shared folder so change include pathr>=jZj1jbj!jdjjf}r?=(jh]ji]jj]jk]jn]ujpMjqhjr]r@=j{X3No longer have shared folder so change include pathrA=rB=}rC=(jYj>=jZj<=ubaubj)rD=}rE=(jYXU/* local header files */ //#include "../shared/AppCommon.h" #include "../AppCommon.h"jZj1jbj!jdjjf}rF=(jjjk]jj]jh]ji]jn]ujpM-jqhjr]rG=j{XU/* local header files */ //#include "../shared/AppCommon.h" #include "../AppCommon.h"rH=rI=}rJ=(jYUjZjD=ubaubjZ)rK=}rL=(jYUjZj1jbj!jdj]jf}rM=(jh]ji]jj]jk]jn]ujpMjqhjr]rN=j`)rO=}rP=(jYUjcKjZjK=jbj!jdjpjf}rQ=(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)rR=}rS=(jYX*Handling AMMU (L1 Unicache MMU) and L2 MMUrT=jZj1jbj!jdjjf}rU=(jk]rV=U(handling-ammu-l1-unicache-mmu-and-l2-mmurW=ajj]jh]ji]jn]rX=hNaujpNjqhjr]rY=j{X*Handling AMMU (L1 Unicache MMU) and L2 MMUrZ=r[=}r\=(jYjT=jZjR=ubaubj)r]=}r^=(jYX>There are two MMUs inside each of the IPU1, and IPU2 subsystems. The L1 MMU is referred to as IPU_UNICACHE_MMU or AMMU and L2 MMU. The description of how this is configured in IPC-remoteproc has been described in section `Changing_Cortex_M4_IPU_Memory_Map `__. IPC handling of L1 and L2 MMU is different from how the PDK driver examples setup the memory access using these MMUs which the users need to manage when integrating the components. This difference is highlighted below:jZj1jbj!jdjjf}r_=(jh]ji]jj]jk]jn]ujpMjqhjr]r`=(j{XThere are two MMUs inside each of the IPU1, and IPU2 subsystems. The L1 MMU is referred to as IPU_UNICACHE_MMU or AMMU and L2 MMU. The description of how this is configured in IPC-remoteproc has been described in section ra=rb=}rc=(jYXThere are two MMUs inside each of the IPU1, and IPU2 subsystems. The L1 MMU is referred to as IPU_UNICACHE_MMU or AMMU and L2 MMU. The description of how this is configured in IPC-remoteproc has been described in section jZj]=ubj)rd=}re=(jYX`Changing_Cortex_M4_IPU_Memory_Map `__jf}rf=(UnameX!Changing_Cortex_M4_IPU_Memory_MapjX]http://processors.wiki.ti.com/index.php/Linux_IPC_on_AM57xx#Changing_Cortex_M4_IPU_Memory_Mapjk]jj]jh]ji]jn]ujZj]=jr]rg=j{X!Changing_Cortex_M4_IPU_Memory_Maprh=ri=}rj=(jYUjZjd=ubajdjubj{X. IPC handling of L1 and L2 MMU is different from how the PDK driver examples setup the memory access using these MMUs which the users need to manage when integrating the components. This difference is highlighted below:rk=rl=}rm=(jYX. IPC handling of L1 and L2 MMU is different from how the PDK driver examples setup the memory access using these MMUs which the users need to manage when integrating the components. This difference is highlighted below:jZj]=ubeubjB)rn=}ro=(jYX3.. Image:: ../images/IPU_MMU_Peripheral_access.png jZj1jbj!jdjEjf}rp=(UuriX,rtos/../images/IPU_MMU_Peripheral_access.pngrq=jk]jj]jh]ji]jH}rr=U*jq=sjn]ujpMjqhjr]ubjC)rs=}rt=(jYUjZj1jbj!jdj`jf}ru=(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]rv=(j/)rw=}rx=(jYXPDK examples use addresses (0x4X000000) to peripheral registers and use following MMU setting - L2 MMU uses default 1:1 Mapping - AMMU configuration translates physical 0x4X000000 access to logical 0x4X000000 jZjs=jbNjdj2jf}ry=(jh]ji]jj]jk]jn]ujpNjqhjr]rz=(j)r{=}r|=(jYX]PDK examples use addresses (0x4X000000) to peripheral registers and use following MMU settingr}=jZjw=jbj!jdjjf}r~=(jh]ji]jj]jk]jn]ujpMjr]r=j{X]PDK examples use addresses (0x4X000000) to peripheral registers and use following MMU settingr=r=}r=(jYj}=jZj{=ubaubjC)r=}r=(jYUjf}r=(jGX-jk]jj]jh]ji]jn]ujZjw=jr]r=(j/)r=}r=(jYXL2 MMU uses default 1:1 Mappingr=jf}r=(jh]ji]jj]jk]jn]ujZj=jr]r=j)r=}r=(jYj=jZj=jbj!jdjjf}r=(jh]ji]jj]jk]jn]ujpMjr]r=j{XL2 MMU uses default 1:1 Mappingr=r=}r=(jYj=jZj=ubaubajdj2ubj/)r=}r=(jYXOAMMU configuration translates physical 0x4X000000 access to logical 0x4X000000 jf}r=(jh]ji]jj]jk]jn]ujZj=jr]r=j)r=}r=(jYXNAMMU configuration translates physical 0x4X000000 access to logical 0x4X000000r=jZj=jbj!jdjjf}r=(jh]ji]jj]jk]jn]ujpMjr]r=j{XNAMMU configuration translates physical 0x4X000000 access to logical 0x4X000000r=r=}r=(jYj=jZj=ubaubajdj2ubejdj`ubeubj/)r=}r=(jYXIPC+ Remote Proc ARM+M4 requires IPU to use logical address (0x6X000000) and uses following MMU setting - L2 MMU is configured such that MMU translates 0x6X000000 access to addresss 0x4X000000 - AMMU is configured for 1:1 mapping 0x6X000000 and 0x6X000000 jZjs=jbNjdj2jf}r=(jh]ji]jj]jk]jn]ujpNjqhjr]r=(j)r=}r=(jYXgIPC+ Remote Proc ARM+M4 requires IPU to use logical address (0x6X000000) and uses following MMU settingr=jZj=jbj!jdjjf}r=(jh]ji]jj]jk]jn]ujpMjr]r=j{XgIPC+ Remote Proc ARM+M4 requires IPU to use logical address (0x6X000000) and uses following MMU settingr=r=}r=(jYj=jZj=ubaubjC)r=}r=(jYUjf}r=(jGX-jk]jj]jh]ji]jn]ujZj=jr]r=(j/)r=}r=(jYXVL2 MMU is configured such that MMU translates 0x6X000000 access to addresss 0x4X000000jf}r=(jh]ji]jj]jk]jn]ujZj=jr]r=j)r=}r=(jYXVL2 MMU is configured such that MMU translates 0x6X000000 access to addresss 0x4X000000r=jZj=jbj!jdjjf}r=(jh]ji]jj]jk]jn]ujpMjr]r=j{XVL2 MMU is configured such that MMU translates 0x6X000000 access to addresss 0x4X000000r=r=}r=(jYj=jZj=ubaubajdj2ubj/)r=}r=(jYX=AMMU is configured for 1:1 mapping 0x6X000000 and 0x6X000000 jf}r=(jh]ji]jj]jk]jn]ujZj=jr]r=j)r=}r=(jYX<AMMU is configured for 1:1 mapping 0x6X000000 and 0x6X000000r=jZj=jbj!jdjjf}r=(jh]ji]jj]jk]jn]ujpMjr]r=j{X<AMMU is configured for 1:1 mapping 0x6X000000 and 0x6X000000r=r=}r=(jYj=jZj=ubaubajdj2ubejdj`ubeubeubj)r=}r=(jYXTherefore after integrating IPC with PDK drivers, it is recommended that the alias addresses are used to access peripherals and PRCM registers. This requires changes to the addresses used by PDK drivers and in application code.r=jZj1jbj!jdjjf}r=(jh]ji]jj]jk]jn]ujpMjqhjr]r=j{XTherefore after integrating IPC with PDK drivers, it is recommended that the alias addresses are used to access peripherals and PRCM registers. This requires changes to the addresses used by PDK drivers and in application code.r=r=}r=(jYj=jZj=ubaubj)r=}r=(jYXHThe following changes were then made to the IPU application source code:r=jZj1jbj!jdjjf}r=(jh]ji]jj]jk]jn]ujpMjqhjr]r=j{XHThe following changes were then made to the IPU application source code:r=r=}r=(jYj=jZj=ubaubj)r=}r=(jYXAdd UART_soc.c file to the project and modify the base addresses for all IPU UART register instance in the UART_HwAttrs to use alias addresses:r=jZj1jbj!jdjjf}r=(jh]ji]jj]jk]jn]ujpMjqhjr]r=j{XAdd UART_soc.c file to the project and modify the base addresses for all IPU UART register instance in the UART_HwAttrs to use alias addresses:r=r=}r=(jYj=jZj=ubaubj)r=}r=(jYX#ifdef _TMS320C6X CSL_DSP_UART3_REGS, OSAL_REGINT_INTVEC_EVENT_COMBINER, #elif defined(__ARM_ARCH_7A__) CSL_MPU_UART3_REGS, 106, #else (CSL_IPU_UART3_REGS + 0x20000000), //Base Addr = 0x48000000 + 0x20000000 = 0x68000000 45, #endifjZj1jbj!jdjjf}r=(jjXcjjjk]jj]jh]j }ji]jn]ujpMjqhjr]r=j{X#ifdef _TMS320C6X CSL_DSP_UART3_REGS, OSAL_REGINT_INTVEC_EVENT_COMBINER, #elif defined(__ARM_ARCH_7A__) CSL_MPU_UART3_REGS, 106, #else (CSL_IPU_UART3_REGS + 0x20000000), //Base Addr = 0x48000000 + 0x20000000 = 0x68000000 45, #endifr=r=}r=(jYUjZj=ubaubj)r=}r=(jYXAdding custom SOC configuration also means that you should use the generic UART driver instead of driver with built in SOC setup. To do this comment the following line in .cfg:r=jZj1jbj!jdjjf}r=(jh]ji]jj]jk]jn]ujpMjqhjr]r=j{XAdding custom SOC configuration also means that you should use the generic UART driver instead of driver with built in SOC setup. To do this comment the following line in .cfg:r=r=}r=(jYj=jZj=ubaubj)r=}r=(jYXZvar Uart = xdc.loadPackage('ti.drv.uart'); //Uart.Settings.socType = socType;jZj1jbj!jdjjf}r=(jjjk]jj]jh]ji]jn]ujpMmjqhjr]r=j{XZvar Uart = xdc.loadPackage('ti.drv.uart'); //Uart.Settings.socType = socType;r=r=}r=(jYUjZj=ubaubj)r=}r=(jYX~There is also an instance in the application code where we added pointer to PRCM registers that need to be changed as follows.r=jZj1jbj!jdjjf}r=(jh]ji]jj]jk]jn]ujpMjqhjr]r=j{X~There is also an instance in the application code where we added pointer to PRCM registers that need to be changed as follows.r=r=}r=(jYj=jZj=ubaubj)r=}r=(jYX| CSL_l4per_cm_core_componentRegs *l4PerCmReg = (CSL_l4per_cm_core_componentRegs *) 0x6a009700; //CSL_MPU_L4PER_CM_CORE_REGS;jZj1jbj!jdjjf}r=(jjjk]jj]jh]ji]jn]ujpMujqhjr]r>j{X| CSL_l4per_cm_core_componentRegs *l4PerCmReg = (CSL_l4per_cm_core_componentRegs *) 0x6a009700; //CSL_MPU_L4PER_CM_CORE_REGS;r>r>}r>(jYUjZj=ubaubj)r>}r>(jYXNow, you are ready to build the firmware. After the .out is built, change the extension to .xem4 and copy it over to the location in the filesystem that is used to load M4 firmware.r>jZj1jbj!jdjjf}r>(jh]ji]jj]jk]jn]ujpMjqhjr]r>j{XNow, you are ready to build the firmware. After the .out is built, change the extension to .xem4 and copy it over to the location in the filesystem that is used to load M4 firmware.r >r >}r >(jYj>jZj>ubaubeubeubj[)r >}r >(jYUjZj!jbjcjdjejf}r>(jh]ji]jj]jk]r>UNcustomizing-memory-map-for-creating-multicore-applications-on-am57xx-using-ipcr>ajn]r>haujpKYjqhjr]r>(jt)r>}r>(jYXNCustomizing Memory map for creating Multicore Applications on AM57xx using IPCr>jZj >jbjcjdjxjf}r>(jh]ji]jj]jk]jn]ujpKYjqhjr]r>j{XNCustomizing Memory map for creating Multicore Applications on AM57xx using IPCr>r>}r>(jYj>jZj>ubaubj)r>}r>(jYX2``__r>jZj >jbjcjdjjf}r>(jh]ji]jj]jk]jn]ujpKZjqhjr]r>j)r >}r!>(jYj>jf}r">(UnameX,http://www.ti.com/lit/an/sprac60/sprac60.pdfr#>jj#>jk]jj]jh]ji]jn]ujZj>jr]r$>j{X,http://www.ti.com/lit/an/sprac60/sprac60.pdfr%>r&>}r'>(jYUjZj >ubajdjubaubeubj[)r(>}r)>(jYUjZj!jbjcjdjejf}r*>(jh]ji]jj]jk]r+>U,ipc-debugging-tools-and-techniques-on-am57xxr,>ajn]r->h aujpK]jqhjr]r.>(jt)r/>}r0>(jYX,IPC Debugging Tools and Techniques on AM57xxr1>jZj(>jbjcjdjxjf}r2>(jh]ji]jj]jk]jn]ujpK]jqhjr]r3>j{X,IPC Debugging Tools and Techniques on AM57xxr4>r5>}r6>(jYj1>jZj/>ubaubj)r7>}r8>(jYXMhttp://processors.wiki.ti.com/index.php/Running_IPC_Examples_on_DRA7xx/AM572xjZj(>jbjXfsource/rtos/How_to_Guides/Host/System_Integration/IPC_Debugging_Tools_and_Techniques_on_AM57xx.rst.incr9>r:>}r;>bjdjjf}r<>(jjjk]jj]jh]ji]jn]ujpKjqhjr]r=>j{XMhttp://processors.wiki.ti.com/index.php/Running_IPC_Examples_on_DRA7xx/AM572xr>>r?>}r@>(jYUjZj7>ubaubj)rA>}rB>(jYXThe sections relevant to AM57xx have been pulled from the `Debugging Tools and Techniques With IPC3.x Application Note `_ and placed here.rC>jZj(>jbj:>jdjjf}rD>(jh]ji]jj]jk]jn]ujpKjqhjr]rE>(j{X:The sections relevant to AM57xx have been pulled from the rF>rG>}rH>(jYX:The sections relevant to AM57xx have been pulled from the jZjA>ubj)rI>}rJ>(jYXm`Debugging Tools and Techniques With IPC3.x Application Note `_jf}rK>(UnameX;Debugging Tools and Techniques With IPC3.x Application NotejX,http://www.ti.com/lit/an/sprac12/sprac12.pdfrL>jk]jj]jh]ji]jn]ujZjA>jr]rM>j{X;Debugging Tools and Techniques With IPC3.x Application NoterN>rO>}rP>(jYUjZjI>ubajdjubj)rQ>}rR>(jYX/ jKjZjA>jdjjf}rS>(UrefurijL>jk]rT>U;debugging-tools-and-techniques-with-ipc3-x-application-noterU>ajj]jh]ji]jn]rV>haujr]ubj{X and placed here.rW>rX>}rY>(jYX and placed here.jZjA>ubeubj[)rZ>}r[>(jYUjKjZj(>jbj:>jdjejf}r\>(jh]r]>X introductionr^>aji]jj]jk]r_>Uid32r`>ajn]ujpKjqhjr]ra>(jt)rb>}rc>(jYX Introductionrd>jZjZ>jbj:>jdjxjf}re>(jh]ji]jj]jk]jn]ujpKjqhjr]rf>j{X Introductionrg>rh>}ri>(jYjd>jZjb>ubaubj)rj>}rk>(jYXDuring development of software, it is common to encounter issues that must be debugged to provide a robust software offering. When developing software that uses the IPC3.x product for inter-processor communication, there are tools and techniques available to aid in the debugging process. These tools and techniques help to more quickly understand and debug the issue. This document addresses all three HLOS’s supported by IPC3.x: Android™ platform, Linux®, and QNX®. Where applicable, differences between the OS's are noted. This document aims to provide tools, techniques, and resources for debugging issues encountered when using the IPC3.x to communicate with remote core software.rl>jZjZ>jbj:>jdjjf}rm>(jh]ji]jj]jk]jn]ujpKjqhjr]rn>j{XDuring development of software, it is common to encounter issues that must be debugged to provide a robust software offering. When developing software that uses the IPC3.x product for inter-processor communication, there are tools and techniques available to aid in the debugging process. These tools and techniques help to more quickly understand and debug the issue. This document addresses all three HLOS’s supported by IPC3.x: Android™ platform, Linux®, and QNX®. Where applicable, differences between the OS's are noted. This document aims to provide tools, techniques, and resources for debugging issues encountered when using the IPC3.x to communicate with remote core software.ro>rp>}rq>(jYjl>jZjj>ubaubeubj[)rr>}rs>(jYUjZj(>jbj:>jdjejf}rt>(jh]ji]jj]jk]ru>U debug-toolsrv>ajn]rw>j1aujpKjqhjr]rx>(jt)ry>}rz>(jYX Debug Toolsr{>jZjr>jbj:>jdjxjf}r|>(jh]ji]jj]jk]jn]ujpKjqhjr]r}>j{X Debug Toolsr~>r>}r>(jYj{>jZjy>ubaubj)r>}r>(jYXThere are several tools that can be leveraged for debugging the IPC, from simple tracing to using Code Composer Studio™ (CCS) to attach to the remote cores. Each provides different advantages in the debugging process.r>jZjr>jbj:>jdjjf}r>(jh]ji]jj]jk]jn]ujpKjqhjr]r>j{XThere are several tools that can be leveraged for debugging the IPC, from simple tracing to using Code Composer Studio™ (CCS) to attach to the remote cores. Each provides different advantages in the debugging process.r>r>}r>(jYj>jZj>ubaubj[)r>}r>(jYUjZjr>jbj:>jdjejf}r>(jh]ji]jj]jk]r>Utracingr>ajn]r>haujpKjqhjr]r>(jt)r>}r>(jYXTracingr>jZj>jbj:>jdjxjf}r>(jh]ji]jj]jk]jn]ujpKjqhjr]r>j{XTracingr>r>}r>(jYj>jZj>ubaubj)r>}r>(jYXWhen an issue occurs, checking the traces is often the first thing done. The traces can give quick insight into what may be happening. In normal, non-error cases, you might see little to no traces from the IPC. But when there is an error, there often is an error trace that can be used to shed light on the issue. An error trace often gives an error code and a module or function name that can be used to identify where the error was thrown.r>jZj>jbj:>jdjjf}r>(jh]ji]jj]jk]jn]ujpKjqhjr]r>j{XWhen an issue occurs, checking the traces is often the first thing done. The traces can give quick insight into what may be happening. In normal, non-error cases, you might see little to no traces from the IPC. But when there is an error, there often is an error trace that can be used to shed light on the issue. An error trace often gives an error code and a module or function name that can be used to identify where the error was thrown.r>r>}r>(jYj>jZj>ubaubeubj[)r>}r>(jYUjZjr>jbj:>jdjejf}r>(jh]ji]jj]jk]r>Ulinux-and-android-debugfsr>ajn]r>jFaujpKjqhjr]r>(jt)r>}r>(jYXLinux and Android - Debugfsr>jZj>jbj:>jdjxjf}r>(jh]ji]jj]jk]jn]ujpKjqhjr]r>j{XLinux and Android - Debugfsr>r>}r>(jYj>jZj>ubaubj)r>}r>(jYXAnother useful place to look for debug info is in the debugfs. Information for each remote processor can be found there, as well as remote core traces, state information, and more.r>jZj>jbj:>jdjjf}r>(jh]ji]jj]jk]jn]ujpK jqhjr]r>j{XAnother useful place to look for debug info is in the debugfs. Information for each remote processor can be found there, as well as remote core traces, state information, and more.r>r>}r>(jYj>jZj>ubaubeubj[)r>}r>(jYUjZjr>jbj:>jdjejf}r>(jh]ji]jj]jk]r>Ucode-composer-studior>ajn]r>jIaujpK$jqhjr]r>(jt)r>}r>(jYXCode Composer Studior>jZj>jbj:>jdjxjf}r>(jh]ji]jj]jk]jn]ujpK$jqhjr]r>j{XCode Composer Studior>r>}r>(jYj>jZj>ubaubj)r>}r>(jYXConnecting over JTAG using Code Composer Studio provides the ability to see exactly what is happening on the remote core, providing access to a wealth of information including viewing memory, registers, and stepping through the code.r>jZj>jbj:>jdjjf}r>(jh]ji]jj]jk]jn]ujpK%jqhjr]r>j{XConnecting over JTAG using Code Composer Studio provides the ability to see exactly what is happening on the remote core, providing access to a wealth of information including viewing memory, registers, and stepping through the code.r>r>}r>(jYj>jZj>ubaubeubeubj[)r>}r>(jYUjZj(>jbj:>jdjejf}r>(jh]ji]jj]jk]r>Utracesr>ajn]r>hVaujpK*jqhjr]r>(jt)r>}r>(jYXTracesr>jZj>jbj:>jdjxjf}r>(jh]ji]jj]jk]jn]ujpK*jqhjr]r>j{XTracesr>r>}r>(jYj>jZj>ubaubj)r>}r>(jYXThe first place to check when an issue occurs is the traces. Often an error code or a trace regarding an error gives some clue. Both the remote core traces and the HLOS-side traces can be checked.r>jZj>jbj:>jdjjf}r>(jh]ji]jj]jk]jn]ujpK+jqhjr]r>j{XThe first place to check when an issue occurs is the traces. Often an error code or a trace regarding an error gives some clue. Both the remote core traces and the HLOS-side traces can be checked.r>r>}r>(jYj>jZj>ubaubj[)r>}r>(jYUjZj>jbj:>jdjejf}r>(jh]ji]jj]jk]r>U%linux-and-android-enabling-ipc-tracesr>ajn]r>j6aujpK/jqhjr]r>(jt)r>}r>(jYX'Linux and Android - Enabling IPC Tracesr>jZj>jbj:>jdjxjf}r>(jh]ji]jj]jk]jn]ujpK/jqhjr]r>j{X'Linux and Android - Enabling IPC Tracesr>r>}r>(jYj>jZj>ubaubj)r>}r>(jYXBy default, the IPC only prints error traces. To enable additional tracing, use the IPC_DEBUG environment variable at runtime. This feature is only supported on Linux and is available starting in IPC 3.22.00.05. Table 1 lists the two levels of tracing supported.r>jZj>jbj:>jdjjf}r>(jh]ji]jj]jk]jn]ujpK0jqhjr]r>j{XBy default, the IPC only prints error traces. To enable additional tracing, use the IPC_DEBUG environment variable at runtime. This feature is only supported on Linux and is available starting in IPC 3.22.00.05. Table 1 lists the two levels of tracing supported.r>r>}r>(jYj>jZj>ubaubj)r>}r>(jYXTable 1. IPC_DEBUG Trace Levelsr>jZj>jbj:>jdjjf}r>(jh]ji]jj]jk]jn]ujpK4jqhjr]r?j{XTable 1. IPC_DEBUG Trace Levelsr?r?}r?(jYj>jZj>ubaubjd$)r?}r?(jYUjZj>jbj:>jdjg$jf}r?(jh]ji]jj]jk]jn]ujpNjqhjr]r?jj$)r?}r ?(jYUjf}r ?(jk]jj]jh]ji]jn]UcolsKujZj?jr]r ?(jo$)r ?}r ?(jYUjf}r?(jk]jj]jh]ji]jn]UcolwidthK ujZj?jr]jdjs$ubjo$)r?}r?(jYUjf}r?(jk]jj]jh]ji]jn]UcolwidthKBujZj?jr]jdjs$ubjz$)r?}r?(jYUjf}r?(jh]ji]jj]jk]jn]ujZj?jr]r?j$)r?}r?(jYUjf}r?(jh]ji]jj]jk]jn]ujZj?jr]r?(j$)r?}r?(jYUjf}r?(jh]ji]jj]jk]jn]ujZj?jr]r?j)r?}r?(jYX Trace Levelr ?jZj?jbj:>jdjjf}r!?(jh]ji]jj]jk]jn]ujpK7jr]r"?j{X Trace Levelr#?r$?}r%?(jYj ?jZj?ubaubajdj$ubj$)r&?}r'?(jYUjf}r(?(jh]ji]jj]jk]jn]ujZj?jr]r)?j)r*?}r+?(jYX Descriptionr,?jZj&?jbj:>jdjjf}r-?(jh]ji]jj]jk]jn]ujpK7jr]r.?j{X Descriptionr/?r0?}r1?(jYj,?jZj*?ubaubajdj$ubejdj$ubajdj$ubj$)r2?}r3?(jYUjf}r4?(jh]ji]jj]jk]jn]ujZj?jr]r5?(j$)r6?}r7?(jYUjf}r8?(jh]ji]jj]jk]jn]ujZj2?jr]r9?(j$)r:?}r;?(jYUjf}r?}r??(jYX1jZj:?jbj:>jdjjf}r@?(jh]ji]jj]jk]jn]ujpK9jr]rA?j{X1rB?}rC?(jYX1jZj>?ubaubajdj$ubj$)rD?}rE?(jYUjf}rF?(jh]ji]jj]jk]jn]ujZj6?jr]rG?j)rH?}rI?(jYX-Enables all warnings and errors to be printedrJ?jZjD?jbj:>jdjjf}rK?(jh]ji]jj]jk]jn]ujpK9jr]rL?j{X-Enables all warnings and errors to be printedrM?rN?}rO?(jYjJ?jZjH?ubaubajdj$ubejdj$ubj$)rP?}rQ?(jYUjf}rR?(jh]ji]jj]jk]jn]ujZj2?jr]rS?(j$)rT?}rU?(jYUjf}rV?(jh]ji]jj]jk]jn]ujZjP?jr]rW?j)rX?}rY?(jYX2jZjT?jbj:>jdjjf}rZ?(jh]ji]jj]jk]jn]ujpK;jr]r[?j{X2r\?}r]?(jYX2jZjX?ubaubajdj$ubj$)r^?}r_?(jYUjf}r`?(jh]ji]jj]jk]jn]ujZjP?jr]ra?j)rb?}rc?(jYX?Turns on all tracing (including socket and LAD client tracing).rd?jZj^?jbj:>jdjjf}re?(jh]ji]jj]jk]jn]ujpK;jr]rf?j{X?Turns on all tracing (including socket and LAD client tracing).rg?rh?}ri?(jYjd?jZjb?ubaubajdj$ubejdj$ubejdjy%ubejdjz%ubaubeubj[)rj?}rk?(jYUjZj>jbj:>jdjejf}rl?(jh]ji]jj]jk]rm?Uqnx-enabling-ipc-tracesrn?ajn]ro?jEaujpK?jqhjr]rp?(jt)rq?}rr?(jYXQNX – Enabling IPC Tracesrs?jZjj?jbj:>jdjxjf}rt?(jh]ji]jj]jk]jn]ujpK?jqhjr]ru?j{XQNX – Enabling IPC Tracesrv?rw?}rx?(jYjs?jZjq?ubaubj)ry?}rz?(jYXWhen using QNX, additional traces are enabled by setting environment variables. There are separate environment variables for enabling traces in the resource manager and the user libraries.r{?jZjj?jbj:>jdjjf}r|?(jh]ji]jj]jk]jn]ujpK@jqhjr]r}?j{XWhen using QNX, additional traces are enabled by setting environment variables. There are separate environment variables for enabling traces in the resource manager and the user libraries.r~?r?}r?(jYj{?jZjy?ubaubj)r?}r?(jYX**Resource Manager Traces**r?jZjj?jbj:>jdjjf}r?(jh]ji]jj]jk]jn]ujpKCjqhjr]r?j)r?}r?(jYj?jf}r?(jh]ji]jj]jk]jn]ujZj?jr]r?j{XResource Manager Tracesr?r?}r?(jYUjZj?ubajdjubaubj)r?}r?(jYX5Enable additional traces in the slog by setting the environment variable IPC_DEBUG_SLOG_LEVEL at runtime. By default, only errors and warnings are printed. The IPC_DEBUG_SLOG_LEVEL can be set before launching IPC to enable more traces. Setting the level to 7 enables all IPC traces. The default level is 2. ::jZjj?jbj:>jdjjf}r?(jh]ji]jj]jk]jn]ujpKEjqhjr]r?j{X2Enable additional traces in the slog by setting the environment variable IPC_DEBUG_SLOG_LEVEL at runtime. By default, only errors and warnings are printed. The IPC_DEBUG_SLOG_LEVEL can be set before launching IPC to enable more traces. Setting the level to 7 enables all IPC traces. The default level is 2.r?r?}r?(jYX2Enable additional traces in the slog by setting the environment variable IPC_DEBUG_SLOG_LEVEL at runtime. By default, only errors and warnings are printed. The IPC_DEBUG_SLOG_LEVEL can be set before launching IPC to enable more traces. Setting the level to 7 enables all IPC traces. The default level is 2.jZj?ubaubj)r?}r?(jYXexport IPC_DEBUG_SLOG_LEVEL=7jZjj?jbj:>jdjjf}r?(jjjk]jj]jh]ji]jn]ujpMjqhjr]r?j{Xexport IPC_DEBUG_SLOG_LEVEL=7r?r?}r?(jYUjZj?ubaubj)r?}r?(jYXThese traces are printed to the slog, and can be viewed by using the sloginfo command. All IPC traces use 42 as identification in the slog, and you can filter the slog to view only these traces::jZjj?jbj:>jdjjf}r?(jh]ji]jj]jk]jn]ujpKMjqhjr]r?j{XThese traces are printed to the slog, and can be viewed by using the sloginfo command. All IPC traces use 42 as identification in the slog, and you can filter the slog to view only these traces:r?r?}r?(jYXThese traces are printed to the slog, and can be viewed by using the sloginfo command. All IPC traces use 42 as identification in the slog, and you can filter the slog to view only these traces:jZj?ubaubj)r?}r?(jYXsloginfo –m42jZjj?jbj:>jdjjf}r?(jjjk]jj]jh]ji]jn]ujpMjqhjr]r?j{Xsloginfo –m42r?r?}r?(jYUjZj?ubaubj)r?}r?(jYX**User Library Traces**r?jZjj?jbj:>jdjjf}r?(jh]ji]jj]jk]jn]ujpKRjqhjr]r?j)r?}r?(jYj?jf}r?(jh]ji]jj]jk]jn]ujZj?jr]r?j{XUser Library Tracesr?r?}r?(jYUjZj?ubajdjubaubj)r?}r?(jYXUser library traces can be enabled by using the variable IPC_DEBUG when launching the application. Valid levels are 1 to 3, with 3 being the most verbose. For example::jZjj?jbj:>jdjjf}r?(jh]ji]jj]jk]jn]ujpKTjqhjr]r?j{XUser library traces can be enabled by using the variable IPC_DEBUG when launching the application. Valid levels are 1 to 3, with 3 being the most verbose. For example:r?r?}r?(jYXUser library traces can be enabled by using the variable IPC_DEBUG when launching the application. Valid levels are 1 to 3, with 3 being the most verbose. For example:jZj?ubaubj)r?}r?(jYXIPC_DEBUG= app_hostjZjj?jbj:>jdjjf}r?(jjjk]jj]jh]ji]jn]ujpMjqhjr]r?j{XIPC_DEBUG= app_hostr?r?}r?(jYUjZj?ubaubeubj[)r?}r?(jYUjKjZj>jbj:>jdjejf}r?(jh]ji]jj]jk]r?U$linux-and-android-remote-core-tracesr?ajn]r?h/aujpKZjqhjr]r?(jt)r?}r?(jYX&Linux and Android - Remote Core Tracesr?jZj?jbj:>jdjxjf}r?(jh]ji]jj]jk]jn]ujpKZjqhjr]r?j{X&Linux and Android - Remote Core Tracesr?r?}r?(jYj?jZj?ubaubj)r?}r?(jYXThe remote core traces can be checked by using debugfs. Run the following command, replacing the “X” with the core-id for the remote core to be checked. ::jZj?jbj:>jdjjf}r?(jh]ji]jj]jk]jn]ujpK[jqhjr]r?j{XThe remote core traces can be checked by using debugfs. Run the following command, replacing the “X” with the core-id for the remote core to be checked.r?r?}r?(jYXThe remote core traces can be checked by using debugfs. Run the following command, replacing the “X” with the core-id for the remote core to be checked.jZj?ubaubj)r?}r?(jYX3cat /sys/kernel/debug/remoteproc/remoteprocX/trace0jZj?jbj:>jdjjf}r?(jjjk]jj]jh]ji]jn]ujpMjqhjr]r?j{X3cat /sys/kernel/debug/remoteproc/remoteprocX/trace0r?r?}r?(jYUjZj?ubaubj)r?}r?(jYXSCheck the following when checking the traces after an error recovery has occurred::r?jZj?jbj:>jdjjf}r?(jh]ji]jj]jk]jn]ujpKajqhjr]r?j{XRCheck the following when checking the traces after an error recovery has occurred:r?r?}r?(jYXRCheck the following when checking the traces after an error recovery has occurred:jZj?ubaubj)r?}r?(jYX8cat /sys/kernel/debug/remoteproc/remoteprocX/trace0_lastjZj?jbj:>jdjjf}r?(jjjk]jj]jh]ji]jn]ujpMjqhjr]r?j{X8cat /sys/kernel/debug/remoteproc/remoteprocX/trace0_lastr?r?}r?(jYUjZj?ubaubj)r?}r?(jYXThis provides the last traces that happened before error recovery was triggered. For more information about debugging remote core faults and exceptions, see `Debugging MMU Faults and Exceptions`_.jZj?jbj:>jdjjf}r?(jh]ji]jj]jk]jn]ujpKejqhjr]r?(j{XThis provides the last traces that happened before error recovery was triggered. For more information about debugging remote core faults and exceptions, see r?r?}r?(jYXThis provides the last traces that happened before error recovery was triggered. For more information about debugging remote core faults and exceptions, see jZj?ubj)r?}r?(jYX&`Debugging MMU Faults and Exceptions`_jKjZj?jdjjf}r?(UnameX#Debugging MMU Faults and Exceptionsjk]jj]jh]ji]jn]jU#debugging-mmu-faults-and-exceptionsr?ujr]r?j{X#Debugging MMU Faults and Exceptionsr?r?}r?(jYUjZj?ubaubj{X.r?}r?(jYX.jZj?ubeubj)r@}r@(jYXfThe core-id, “X”, starts at 0 and increments to include all of the remote cores supported by the remoteproc module in the dts file. Because the number of remoteprocs supported can vary depending on the dts configuration, it is not ensured that a certain remote core will always have a certain core-id if the remoteprocs supported in the dts file changes.r@jZj?jbj:>jdjjf}r@(jh]ji]jj]jk]jn]ujpKhjqhjr]r@j{XfThe core-id, “X”, starts at 0 and increments to include all of the remote cores supported by the remoteproc module in the dts file. Because the number of remoteprocs supported can vary depending on the dts configuration, it is not ensured that a certain remote core will always have a certain core-id if the remoteprocs supported in the dts file changes.r@r@}r@(jYj@jZj@ubaubj)r@}r @(jYXThe core associated with a particular core-id can be found by checking the name of the remoteproc (see `Linux and Android - Remoteproc`_). Table 2 associates the remoteproc name with the common name of the remote processor. ::jZj?jbj:>jdjjf}r @(jh]ji]jj]jk]jn]ujpKmjqhjr]r @(j{XgThe core associated with a particular core-id can be found by checking the name of the remoteproc (see r @r @}r@(jYXgThe core associated with a particular core-id can be found by checking the name of the remoteproc (see jZj@ubj)r@}r@(jYX!`Linux and Android - Remoteproc`_jKjZj@jdjjf}r@(UnameXLinux and Android - Remoteprocjk]jj]jh]ji]jn]jUlinux-and-android-remoteprocr@ujr]r@j{XLinux and Android - Remoteprocr@r@}r@(jYUjZj@ubaubj{XW). Table 2 associates the remoteproc name with the common name of the remote processor.r@r@}r@(jYXW). Table 2 associates the remoteproc name with the common name of the remote processor.jZj@ubeubj)r@}r@(jYX1cat /sys/kernel/debug/remoteproc/remoteprocX/namejZj?jbj:>jdjjf}r@(jjjk]jj]jh]ji]jn]ujpMjqhjr]r@j{X1cat /sys/kernel/debug/remoteproc/remoteprocX/namer@r@}r @(jYUjZj@ubaubj)r!@}r"@(jYX$Table 2. Remoteproc Names for AM57xxr#@jZj?jbj:>jdjjf}r$@(jh]ji]jj]jk]jn]ujpKsjqhjr]r%@j{X$Table 2. Remoteproc Names for AM57xxr&@r'@}r(@(jYj#@jZj!@ubaubjd$)r)@}r*@(jYUjZj?jbj:>jdjg$jf}r+@(jh]ji]jj]jk]jn]ujpNjqhjr]r,@jj$)r-@}r.@(jYUjf}r/@(jk]jj]jh]ji]jn]UcolsKujZj)@jr]r0@(jo$)r1@}r2@(jYUjf}r3@(jk]jj]jh]ji]jn]UcolwidthKujZj-@jr]jdjs$ubjo$)r4@}r5@(jYUjf}r6@(jk]jj]jh]ji]jn]UcolwidthKujZj-@jr]jdjs$ubjz$)r7@}r8@(jYUjf}r9@(jh]ji]jj]jk]jn]ujZj-@jr]r:@j$)r;@}r<@(jYUjf}r=@(jh]ji]jj]jk]jn]ujZj7@jr]r>@(j$)r?@}r@@(jYUjf}rA@(jh]ji]jj]jk]jn]ujZj;@jr]rB@j)rC@}rD@(jYX Debugfs NamerE@jZj?@jbj:>jdjjf}rF@(jh]ji]jj]jk]jn]ujpKvjr]rG@j{X Debugfs NamerH@rI@}rJ@(jYjE@jZjC@ubaubajdj$ubj$)rK@}rL@(jYUjf}rM@(jh]ji]jj]jk]jn]ujZj;@jr]rN@j)rO@}rP@(jYXRemote Core NamerQ@jZjK@jbj:>jdjjf}rR@(jh]ji]jj]jk]jn]ujpKvjr]rS@j{XRemote Core NamerT@rU@}rV@(jYjQ@jZjO@ubaubajdj$ubejdj$ubajdj$ubj$)rW@}rX@(jYUjf}rY@(jh]ji]jj]jk]jn]ujZj-@jr]rZ@(j$)r[@}r\@(jYUjf}r]@(jh]ji]jj]jk]jn]ujZjW@jr]r^@(j$)r_@}r`@(jYUjf}ra@(jh]ji]jj]jk]jn]ujZj[@jr]rb@j)rc@}rd@(jYX 58820000.ipure@jZj_@jbj:>jdjjf}rf@(jh]ji]jj]jk]jn]ujpKxjr]rg@j{X 58820000.ipurh@ri@}rj@(jYje@jZjc@ubaubajdj$ubj$)rk@}rl@(jYUjf}rm@(jh]ji]jj]jk]jn]ujZj[@jr]rn@j)ro@}rp@(jYXIPU1rq@jZjk@jbj:>jdjjf}rr@(jh]ji]jj]jk]jn]ujpKxjr]rs@j{XIPU1rt@ru@}rv@(jYjq@jZjo@ubaubajdj$ubejdj$ubj$)rw@}rx@(jYUjf}ry@(jh]ji]jj]jk]jn]ujZjW@jr]rz@(j$)r{@}r|@(jYUjf}r}@(jh]ji]jj]jk]jn]ujZjw@jr]r~@j)r@}r@(jYX 55020000.ipur@jZj{@jbj:>jdjjf}r@(jh]ji]jj]jk]jn]ujpKzjr]r@j{X 55020000.ipur@r@}r@(jYj@jZj@ubaubajdj$ubj$)r@}r@(jYUjf}r@(jh]ji]jj]jk]jn]ujZjw@jr]r@j)r@}r@(jYXIPU2r@jZj@jbj:>jdjjf}r@(jh]ji]jj]jk]jn]ujpKzjr]r@j{XIPU2r@r@}r@(jYj@jZj@ubaubajdj$ubejdj$ubj$)r@}r@(jYUjf}r@(jh]ji]jj]jk]jn]ujZjW@jr]r@(j$)r@}r@(jYUjf}r@(jh]ji]jj]jk]jn]ujZj@jr]r@j)r@}r@(jYX 40800000.dspr@jZj@jbj:>jdjjf}r@(jh]ji]jj]jk]jn]ujpK|jr]r@j{X 40800000.dspr@r@}r@(jYj@jZj@ubaubajdj$ubj$)r@}r@(jYUjf}r@(jh]ji]jj]jk]jn]ujZj@jr]r@j)r@}r@(jYXDSP1r@jZj@jbj:>jdjjf}r@(jh]ji]jj]jk]jn]ujpK|jr]r@j{XDSP1r@r@}r@(jYj@jZj@ubaubajdj$ubejdj$ubj$)r@}r@(jYUjf}r@(jh]ji]jj]jk]jn]ujZjW@jr]r@(j$)r@}r@(jYUjf}r@(jh]ji]jj]jk]jn]ujZj@jr]r@j)r@}r@(jYX 41000000.dspr@jZj@jbj:>jdjjf}r@(jh]ji]jj]jk]jn]ujpK~jr]r@j{X 41000000.dspr@r@}r@(jYj@jZj@ubaubajdj$ubj$)r@}r@(jYUjf}r@(jh]ji]jj]jk]jn]ujZj@jr]r@j)r@}r@(jYXDSP2r@jZj@jbj:>jdjjf}r@(jh]ji]jj]jk]jn]ujpK~jr]r@j{XDSP2r@r@}r@(jYj@jZj@ubaubajdj$ubejdj$ubejdjy%ubejdjz%ubaubeubj[)r@}r@(jYUjZj>jbj:>jdjejf}r@(jh]ji]jj]jk]r@Uqnx-remote-core-tracesr@ajn]r@haujpKjqhjr]r@(jt)r@}r@(jYXQNX - Remote Core Tracesr@jZj@jbj:>jdjxjf}r@(jh]ji]jj]jk]jn]ujpKjqhjr]r@j{XQNX - Remote Core Tracesr@r@}r@(jYj@jZj@ubaubj)r@}r@(jYXThe remote core traces can be checked by using sysfs. Run the following command, replacing with the core name for the remote core to check. Valid core names for AM57xx are IPU1, IPU2, DSP1, and DSP2. ::jZj@jbj:>jdjjf}r@(jh]ji]jj]jk]jn]ujpKjqhjr]r@j{XThe remote core traces can be checked by using sysfs. Run the following command, replacing with the core name for the remote core to check. Valid core names for AM57xx are IPU1, IPU2, DSP1, and DSP2.r@r@}r@(jYXThe remote core traces can be checked by using sysfs. Run the following command, replacing with the core name for the remote core to check. Valid core names for AM57xx are IPU1, IPU2, DSP1, and DSP2.jZj@ubaubj)r@}r@(jYXcat /dev/ipc-trace/jZj@jbj:>jdjjf}r@(jjjk]jj]jh]ji]jn]ujpMjqhjr]r@j{Xcat /dev/ipc-trace/r@r@}r@(jYUjZj@ubaubj)r@}r@(jYX~When checking the traces after error recovery has happened, check the logfile specified at IPC startup, if one was specified. When starting IPC, specify a logfile using the “-c” option. When an error recovery happens, the last traces are dumped to this log file. For more information about debugging remote core faults and exceptions, see `Debugging MMU Faults and Exceptions`_.jZj@jbj:>jdjjf}r@(jh]ji]jj]jk]jn]ujpKjqhjr]r@(j{XWWhen checking the traces after error recovery has happened, check the logfile specified at IPC startup, if one was specified. When starting IPC, specify a logfile using the “-c” option. When an error recovery happens, the last traces are dumped to this log file. For more information about debugging remote core faults and exceptions, see r@r@}r@(jYXWWhen checking the traces after error recovery has happened, check the logfile specified at IPC startup, if one was specified. When starting IPC, specify a logfile using the “-c” option. When an error recovery happens, the last traces are dumped to this log file. For more information about debugging remote core faults and exceptions, see jZj@ubj)r@}r@(jYX&`Debugging MMU Faults and Exceptions`_jKjZj@jdjjf}r@(UnameX#Debugging MMU Faults and Exceptionsjk]jj]jh]ji]jn]jj?ujr]r@j{X#Debugging MMU Faults and Exceptionsr@r@}r@(jYUjZj@ubaubj{X.r@}r@(jYX.jZj@ubeubeubj[)r@}r@(jYUjZj>jbj:>jdjejf}r@(jh]ji]jj]jk]r@Uqnx-adding-tracesr@ajn]r@jaujpKjqhjr]r@(jt)r@}rA(jYXQNX - Adding TracesrAjZj@jbj:>jdjxjf}rA(jh]ji]jj]jk]jn]ujpKjqhjr]rAj{XQNX - Adding TracesrArA}rA(jYjAjZj@ubaubj)rA}rA(jYXIn some cases, you may want to add traces to get more information about the issue. If the issue is reliably reproducible, one technique is to add additional traces to get more information. If the issue is timing-related, this technique may not be helpful, as it may mask the issuer AjZj@jbj:>jdjjf}r A(jh]ji]jj]jk]jn]ujpKjqhjr]r Aj{XIn some cases, you may want to add traces to get more information about the issue. If the issue is reliably reproducible, one technique is to add additional traces to get more information. If the issue is timing-related, this technique may not be helpful, as it may mask the issuer Ar A}rA(jYj AjZjAubaubj)rA}rA(jYX **SYS-BIOS**rAjZj@jbj:>jdjjf}rA(jh]ji]jj]jk]jn]ujpKjqhjr]rAj)rA}rA(jYjAjf}rA(jh]ji]jj]jk]jn]ujZjAjr]rAj{XSYS-BIOSrArA}rA(jYUjZjAubajdjubaubj)rA}rA(jYXaYou can add traces in the SYS-BIOS IPC code that come to the trace buffer by using the System_printf() API. After adding traces to the SYS-BIOS IPC and rebuilding the IPC, you must rebuild the remote core image. The traces come to the remote core trace buffer and can be viewed by following the instructions in `Linux and Android - Remote Core Traces`_.jZj@jbj:>jdjjf}rA(jh]ji]jj]jk]jn]ujpKjqhjr]rA(j{X7You can add traces in the SYS-BIOS IPC code that come to the trace buffer by using the System_printf() API. After adding traces to the SYS-BIOS IPC and rebuilding the IPC, you must rebuild the remote core image. The traces come to the remote core trace buffer and can be viewed by following the instructions in rAr A}r!A(jYX7You can add traces in the SYS-BIOS IPC code that come to the trace buffer by using the System_printf() API. After adding traces to the SYS-BIOS IPC and rebuilding the IPC, you must rebuild the remote core image. The traces come to the remote core trace buffer and can be viewed by following the instructions in jZjAubj)r"A}r#A(jYX)`Linux and Android - Remote Core Traces`_jKjZjAjdjjf}r$A(UnameX&Linux and Android - Remote Core Tracesjk]jj]jh]ji]jn]jj?ujr]r%Aj{X&Linux and Android - Remote Core Tracesr&Ar'A}r(A(jYUjZj"Aubaubj{X.r)A}r*A(jYX.jZjAubeubj)r+A}r,A(jYX **Linux**r-AjZj@jbj:>jdjjf}r.A(jh]ji]jj]jk]jn]ujpKjqhjr]r/Aj)r0A}r1A(jYj-Ajf}r2A(jh]ji]jj]jk]jn]ujZj+Ajr]r3Aj{XLinuxr4Ar5A}r6A(jYUjZj0Aubajdjubaubj)r7A}r8A(jYXAdditionally, traces can be added in the Linux code. The modules of interest when adding traces are the remoteproc, iommu, and rpmsg modules in the kernel, and the MessageQ, MMRPC, and LAD modules in the user space.r9AjZj@jbj:>jdjjf}r:A(jh]ji]jj]jk]jn]ujpKjqhjr]r;Aj{XAdditionally, traces can be added in the Linux code. The modules of interest when adding traces are the remoteproc, iommu, and rpmsg modules in the kernel, and the MessageQ, MMRPC, and LAD modules in the user space.rA(jYj9AjZj7Aubaubj)r?A}r@A(jYX7In the kernel are these modules in the following paths:rAAjZj@jbj:>jdjjf}rBA(jh]ji]jj]jk]jn]ujpKjqhjr]rCAj{X7In the kernel are these modules in the following paths:rDArEA}rFA(jYjAAjZj?AubaubjC)rGA}rHA(jYUjZj@jbj:>jdj`jf}rIA(jGX*jk]jj]jh]ji]jn]ujpKjqhjr]rJA(j/)rKA}rLA(jYXdrivers/remoteproc/rMAjZjGAjbj:>jdj2jf}rNA(jh]ji]jj]jk]jn]ujpNjqhjr]rOAj)rPA}rQA(jYjMAjZjKAjbj:>jdjjf}rRA(jh]ji]jj]jk]jn]ujpKjr]rSAj{Xdrivers/remoteproc/rTArUA}rVA(jYjMAjZjPAubaubaubj/)rWA}rXA(jYXdrivers/iommu/rYAjZjGAjbj:>jdj2jf}rZA(jh]ji]jj]jk]jn]ujpNjqhjr]r[Aj)r\A}r]A(jYjYAjZjWAjbj:>jdjjf}r^A(jh]ji]jj]jk]jn]ujpKjr]r_Aj{Xdrivers/iommu/r`AraA}rbA(jYjYAjZj\Aubaubaubj/)rcA}rdA(jYXdrivers/rpmsg/ jZjGAjbj:>jdj2jf}reA(jh]ji]jj]jk]jn]ujpNjqhjr]rfAj)rgA}rhA(jYXdrivers/rpmsg/riAjZjcAjbj:>jdjjf}rjA(jh]ji]jj]jk]jn]ujpKjr]rkAj{Xdrivers/rpmsg/rlArmA}rnA(jYjiAjZjgAubaubaubeubj)roA}rpA(jYXMost of the user space code can be found in the IPC package, in the linux folder. The MMRPC code is found in the packages/ti/ipc/mm/ folder.rqAjZj@jbj:>jdjjf}rrA(jh]ji]jj]jk]jn]ujpKjqhjr]rsAj{XMost of the user space code can be found in the IPC package, in the linux folder. The MMRPC code is found in the packages/ti/ipc/mm/ folder.rtAruA}rvA(jYjqAjZjoAubaubeubeubj[)rwA}rxA(jYUjZj(>jbj:>jdjejf}ryA(jh]ji]jj]jk]rzAUremote-core-status-informationr{Aajn]r|AjaujpKjqhjr]r}A(jt)r~A}rA(jYXRemote Core Status InformationrAjZjwAjbj:>jdjxjf}rA(jh]ji]jj]jk]jn]ujpKjqhjr]rAj{XRemote Core Status InformationrArA}rA(jYjAjZj~Aubaubj)rA}rA(jYXPUseful information about the status of the remote cores can be found in debugfs.rAjZjwAjbj:>jdjjf}rA(jh]ji]jj]jk]jn]ujpKjqhjr]rAj{XPUseful information about the status of the remote cores can be found in debugfs.rArA}rA(jYjAjZjAubaubj[)rA}rA(jYUjKjZjwAjbj:>jdjejf}rA(jh]ji]jj]jk]rAj@ajn]rAhaujpKjqhjr]rA(jt)rA}rA(jYXLinux and Android - RemoteprocrAjZjAjbj:>jdjxjf}rA(jh]ji]jj]jk]jn]ujpKjqhjr]rAj{XLinux and Android - RemoteprocrArA}rA(jYjAjZjAubaubj)rA}rA(jYXInformation about each remote core can be found in the following, where the “X” can be replaced with the remote core id. ::jZjAjbj:>jdjjf}rA(jh]ji]jj]jk]jn]ujpKjqhjr]rAj{X|Information about each remote core can be found in the following, where the “X” can be replaced with the remote core id.rArA}rA(jYX|Information about each remote core can be found in the following, where the “X” can be replaced with the remote core id.jZjAubaubj)rA}rA(jYX4cat /sys/kernel/debug/remoteproc/remoteprocX/jZjAjbj:>jdjjf}rA(jjjk]jj]jh]ji]jn]ujpM@jqhjr]rAj{X4cat /sys/kernel/debug/remoteproc/remoteprocX/rArA}rA(jYUjZjAubaubj)rA}rA(jYX.Table 3 lists what can be found for each core.rAjZjAjbj:>jdjjf}rA(jh]ji]jj]jk]jn]ujpKjqhjr]rAj{X.Table 3 lists what can be found for each core.rArA}rA(jYjAjZjAubaubj)rA}rA(jYX#Table 3. Remoteproc Debugfs EntriesrAjZjAjbj:>jdjjf}rA(jh]ji]jj]jk]jn]ujpKjqhjr]rAj{X#Table 3. Remoteproc Debugfs EntriesrArA}rA(jYjAjZjAubaubjd$)rA}rA(jYUjZjAjbj:>jdjg$jf}rA(jh]ji]jj]jk]jn]ujpNjqhjr]rAjj$)rA}rA(jYUjf}rA(jk]jj]jh]ji]jn]UcolsKujZjAjr]rA(jo$)rA}rA(jYUjf}rA(jk]jj]jh]ji]jn]UcolwidthKujZjAjr]jdjs$ubjo$)rA}rA(jYUjf}rA(jk]jj]jh]ji]jn]UcolwidthK[ujZjAjr]jdjs$ubjz$)rA}rA(jYUjf}rA(jh]ji]jj]jk]jn]ujZjAjr]rAj$)rA}rA(jYUjf}rA(jh]ji]jj]jk]jn]ujZjAjr]rA(j$)rA}rA(jYUjf}rA(jh]ji]jj]jk]jn]ujZjAjr]rAj)rA}rA(jYXEntryrAjZjAjbj:>jdjjf}rA(jh]ji]jj]jk]jn]ujpKjr]rAj{XEntryrArA}rA(jYjAjZjAubaubajdj$ubj$)rA}rA(jYUjf}rA(jh]ji]jj]jk]jn]ujZjAjr]rAj)rA}rA(jYX DescriptionrAjZjAjbj:>jdjjf}rA(jh]ji]jj]jk]jn]ujpKjr]rAj{X DescriptionrArA}rA(jYjAjZjAubaubajdj$ubejdj$ubajdj$ubj$)rA}rA(jYUjf}rA(jh]ji]jj]jk]jn]ujZjAjr]rA(j$)rA}rA(jYUjf}rA(jh]ji]jj]jk]jn]ujZjAjr]rA(j$)rA}rA(jYUjf}rA(jh]ji]jj]jk]jn]ujZjAjr]rAj)rA}rA(jYXnamerAjZjAjbj:>jdjjf}rA(jh]ji]jj]jk]jn]ujpKjr]rAj{XnamerArA}rA(jYjAjZjAubaubajdj$ubj$)rA}rA(jYUjf}rA(jh]ji]jj]jk]jn]ujZjAjr]rAj)rB}rB(jYXProcessor name, comprised of the RAM address and the processor type, (for example, 58820000.ipu for IPU1). For a complete list of names, see Table 2.rBjZjAjbj:>jdjjf}rB(jh]ji]jj]jk]jn]ujpKjr]rBj{XProcessor name, comprised of the RAM address and the processor type, (for example, 58820000.ipu for IPU1). For a complete list of names, see Table 2.rBrB}rB(jYjBjZjBubaubajdj$ubejdj$ubj$)rB}r B(jYUjf}r B(jh]ji]jj]jk]jn]ujZjAjr]r B(j$)r B}r B(jYUjf}rB(jh]ji]jj]jk]jn]ujZjBjr]rBj)rB}rB(jYXrecoveryrBjZj Bjbj:>jdjjf}rB(jh]ji]jj]jk]jn]ujpKjr]rBj{XrecoveryrBrB}rB(jYjBjZjBubaubajdj$ubj$)rB}rB(jYUjf}rB(jh]ji]jj]jk]jn]ujZjBjr]rBj)rB}rB(jYXwReturns either “enabled” or “disabled”, indicating if recovery is enabled or disabled for the remote processor.rBjZjBjbj:>jdjjf}rB(jh]ji]jj]jk]jn]ujpKjr]r Bj{XwReturns either “enabled” or “disabled”, indicating if recovery is enabled or disabled for the remote processor.r!Br"B}r#B(jYjBjZjBubaubajdj$ubejdj$ubj$)r$B}r%B(jYUjf}r&B(jh]ji]jj]jk]jn]ujZjAjr]r'B(j$)r(B}r)B(jYUjf}r*B(jh]ji]jj]jk]jn]ujZj$Bjr]r+Bj)r,B}r-B(jYXstater.BjZj(Bjbj:>jdjjf}r/B(jh]ji]jj]jk]jn]ujpKjr]r0Bj{Xstater1Br2B}r3B(jYj.BjZj,Bubaubajdj$ubj$)r4B}r5B(jYUjf}r6B(jh]ji]jj]jk]jn]ujZj$Bjr]r7Bj)r8B}r9B(jYXsGives the state of the remote processor. State is one of: * offline (0) * suspended (1) * running (2) * crashed (3)r:BjZj4Bjbj:>jdjjf}r;B(jh]ji]jj]jk]jn]ujpKjr]rB}r?B(jYj:BjZj8Bubaubajdj$ubejdj$ubj$)r@B}rAB(jYUjf}rBB(jh]ji]jj]jk]jn]ujZjAjr]rCB(j$)rDB}rEB(jYUjf}rFB(jh]ji]jj]jk]jn]ujZj@Bjr]rGBj)rHB}rIB(jYXtrace0rJBjZjDBjbj:>jdjjf}rKB(jh]ji]jj]jk]jn]ujpKjr]rLBj{Xtrace0rMBrNB}rOB(jYjJBjZjHBubaubajdj$ubj$)rPB}rQB(jYUjf}rRB(jh]ji]jj]jk]jn]ujZj@Bjr]rSBj)rTB}rUB(jYX:Returns the contents of the remote processor trace buffer.rVBjZjPBjbj:>jdjjf}rWB(jh]ji]jj]jk]jn]ujpKjr]rXBj{X:Returns the contents of the remote processor trace buffer.rYBrZB}r[B(jYjVBjZjTBubaubajdj$ubejdj$ubj$)r\B}r]B(jYUjf}r^B(jh]ji]jj]jk]jn]ujZjAjr]r_B(j$)r`B}raB(jYUjf}rbB(jh]ji]jj]jk]jn]ujZj\Bjr]rcBj)rdB}reB(jYX trace0_lastrfBjZj`Bjbj:>jdjjf}rgB(jh]ji]jj]jk]jn]ujpKjr]rhBj{X trace0_lastriBrjB}rkB(jYjfBjZjdBubaubajdj$ubj$)rlB}rmB(jYUjf}rnB(jh]ji]jj]jk]jn]ujZj\Bjr]roBj)rpB}rqB(jYXCreated after recovering the remote core. Returns the contents of the remote processor trace buffer before recovery was triggered.rrBjZjlBjbj:>jdjjf}rsB(jh]ji]jj]jk]jn]ujpKjr]rtBj{XCreated after recovering the remote core. Returns the contents of the remote processor trace buffer before recovery was triggered.ruBrvB}rwB(jYjrBjZjpBubaubajdj$ubejdj$ubj$)rxB}ryB(jYUjf}rzB(jh]ji]jj]jk]jn]ujZjAjr]r{B(j$)r|B}r}B(jYUjf}r~B(jh]ji]jj]jk]jn]ujZjxBjr]rBj)rB}rB(jYXversionrBjZj|Bjbj:>jdjjf}rB(jh]ji]jj]jk]jn]ujpKjr]rBj{XversionrBrB}rB(jYjBjZjBubaubajdj$ubj$)rB}rB(jYUjf}rB(jh]ji]jj]jk]jn]ujZjxBjr]rBj)rB}rB(jYX/Returns the version. Currently returns nothing.rBjZjBjbj:>jdjjf}rB(jh]ji]jj]jk]jn]ujpKjr]rBj{X/Returns the version. Currently returns nothing.rBrB}rB(jYjBjZjBubaubajdj$ubejdj$ubejdjy%ubejdjz%ubaubeubj[)rB}rB(jYUjZjwAjbj:>jdjejf}rB(jh]ji]jj]jk]rBUlinux-and-android-iommu-inforBajn]rBhaujpKjqhjr]rB(jt)rB}rB(jYXLinux and Android - IOMMU InforBjZjBjbj:>jdjxjf}rB(jh]ji]jj]jk]jn]ujpKjqhjr]rBj{XLinux and Android - IOMMU InforBrB}rB(jYjBjZjBubaubj)rB}rB(jYXInformation about the IOMMU can also be found in debugfs. It can be found in the following path, where “XXXXXXXX” is replaced by the register address for the remote core MMU registers. ::jZjBjbj:>jdjjf}rB(jh]ji]jj]jk]jn]ujpKjqhjr]rBj{XInformation about the IOMMU can also be found in debugfs. It can be found in the following path, where “XXXXXXXX” is replaced by the register address for the remote core MMU registers.rBrB}rB(jYXInformation about the IOMMU can also be found in debugfs. It can be found in the following path, where “XXXXXXXX” is replaced by the register address for the remote core MMU registers.jZjBubaubj)rB}rB(jYX5cat /sys/kernel/debug/omap_iommu/XXXXXXXX.mmu/jZjBjbj:>jdjjf}rB(jjjk]jj]jh]ji]jn]ujpMcjqhjr]rBj{X5cat /sys/kernel/debug/omap_iommu/XXXXXXXX.mmu/rBrB}rB(jYUjZjBubaubj)rB}rB(jYXgTable 4 gives the corresponding core name for each MMU for AM57xx, and the register address in the TRM.rBjZjBjbj:>jdjjf}rB(jh]ji]jj]jk]jn]ujpKjqhjr]rBj{XgTable 4 gives the corresponding core name for each MMU for AM57xx, and the register address in the TRM.rBrB}rB(jYjBjZjBubaubj)rB}rB(jYXTable 4. IOMMU Entry NamesrBjZjBjbj:>jdjjf}rB(jh]ji]jj]jk]jn]ujpKjqhjr]rBj{XTable 4. IOMMU Entry NamesrBrB}rB(jYjBjZjBubaubjd$)rB}rB(jYUjZjBjbj:>jdjg$jf}rB(jh]ji]jj]jk]jn]ujpNjqhjr]rBjj$)rB}rB(jYUjf}rB(jk]jj]jh]ji]jn]UcolsKujZjBjr]rB(jo$)rB}rB(jYUjf}rB(jk]jj]jh]ji]jn]UcolwidthKujZjBjr]jdjs$ubjo$)rB}rB(jYUjf}rB(jk]jj]jh]ji]jn]UcolwidthK ujZjBjr]jdjs$ubjz$)rB}rB(jYUjf}rB(jh]ji]jj]jk]jn]ujZjBjr]rBj$)rB}rB(jYUjf}rB(jh]ji]jj]jk]jn]ujZjBjr]rB(j$)rB}rB(jYUjf}rB(jh]ji]jj]jk]jn]ujZjBjr]rBj)rB}rB(jYX IOMMU EntryrBjZjBjbj:>jdjjf}rB(jh]ji]jj]jk]jn]ujpKjr]rBj{X IOMMU EntryrBrB}rB(jYjBjZjBubaubajdj$ubj$)rB}rB(jYUjf}rB(jh]ji]jj]jk]jn]ujZjBjr]rBj)rB}rB(jYX Core NamerBjZjBjbj:>jdjjf}rB(jh]ji]jj]jk]jn]ujpKjr]rBj{X Core NamerBrB}rB(jYjBjZjBubaubajdj$ubejdj$ubajdj$ubj$)rB}rB(jYUjf}rB(jh]ji]jj]jk]jn]ujZjBjr]rB(j$)rB}rB(jYUjf}rB(jh]ji]jj]jk]jn]ujZjBjr]rB(j$)rB}rB(jYUjf}rB(jh]ji]jj]jk]jn]ujZjBjr]rBj)rB}rB(jYX 58882000.mmurBjZjBjbj:>jdjjf}rB(jh]ji]jj]jk]jn]ujpKjr]rBj{X 58882000.mmurCrC}rC(jYjBjZjBubaubajdj$ubj$)rC}rC(jYUjf}rC(jh]ji]jj]jk]jn]ujZjBjr]rCj)rC}rC(jYXIPU1r CjZjCjbj:>jdjjf}r C(jh]ji]jj]jk]jn]ujpKjr]r Cj{XIPU1r Cr C}rC(jYj CjZjCubaubajdj$ubejdj$ubj$)rC}rC(jYUjf}rC(jh]ji]jj]jk]jn]ujZjBjr]rC(j$)rC}rC(jYUjf}rC(jh]ji]jj]jk]jn]ujZjCjr]rCj)rC}rC(jYX 55082000.mmurCjZjCjbj:>jdjjf}rC(jh]ji]jj]jk]jn]ujpKjr]rCj{X 55082000.mmurCrC}rC(jYjCjZjCubaubajdj$ubj$)rC}r C(jYUjf}r!C(jh]ji]jj]jk]jn]ujZjCjr]r"Cj)r#C}r$C(jYXIPU2r%CjZjCjbj:>jdjjf}r&C(jh]ji]jj]jk]jn]ujpKjr]r'Cj{XIPU2r(Cr)C}r*C(jYj%CjZj#Cubaubajdj$ubejdj$ubj$)r+C}r,C(jYUjf}r-C(jh]ji]jj]jk]jn]ujZjBjr]r.C(j$)r/C}r0C(jYUjf}r1C(jh]ji]jj]jk]jn]ujZj+Cjr]r2Cj)r3C}r4C(jYX 40d01000.mmur5CjZj/Cjbj:>jdjjf}r6C(jh]ji]jj]jk]jn]ujpKjr]r7Cj{X 40d01000.mmur8Cr9C}r:C(jYj5CjZj3Cubaubajdj$ubj$)r;C}rCj)r?C}r@C(jYX DSP1 (MMU1)rACjZj;Cjbj:>jdjjf}rBC(jh]ji]jj]jk]jn]ujpKjr]rCCj{X DSP1 (MMU1)rDCrEC}rFC(jYjACjZj?Cubaubajdj$ubejdj$ubj$)rGC}rHC(jYUjf}rIC(jh]ji]jj]jk]jn]ujZjBjr]rJC(j$)rKC}rLC(jYUjf}rMC(jh]ji]jj]jk]jn]ujZjGCjr]rNCj)rOC}rPC(jYX 40d02000.mmurQCjZjKCjbj:>jdjjf}rRC(jh]ji]jj]jk]jn]ujpKjr]rSCj{X 40d02000.mmurTCrUC}rVC(jYjQCjZjOCubaubajdj$ubj$)rWC}rXC(jYUjf}rYC(jh]ji]jj]jk]jn]ujZjGCjr]rZCj)r[C}r\C(jYX DSP1 (MMU2)r]CjZjWCjbj:>jdjjf}r^C(jh]ji]jj]jk]jn]ujpKjr]r_Cj{X DSP1 (MMU2)r`CraC}rbC(jYj]CjZj[Cubaubajdj$ubejdj$ubj$)rcC}rdC(jYUjf}reC(jh]ji]jj]jk]jn]ujZjBjr]rfC(j$)rgC}rhC(jYUjf}riC(jh]ji]jj]jk]jn]ujZjcCjr]rjCj)rkC}rlC(jYX 41501000.mmurmCjZjgCjbj:>jdjjf}rnC(jh]ji]jj]jk]jn]ujpKjr]roCj{X 41501000.mmurpCrqC}rrC(jYjmCjZjkCubaubajdj$ubj$)rsC}rtC(jYUjf}ruC(jh]ji]jj]jk]jn]ujZjcCjr]rvCj)rwC}rxC(jYX DSP2 (MMU1)ryCjZjsCjbj:>jdjjf}rzC(jh]ji]jj]jk]jn]ujpKjr]r{Cj{X DSP2 (MMU1)r|Cr}C}r~C(jYjyCjZjwCubaubajdj$ubejdj$ubj$)rC}rC(jYUjf}rC(jh]ji]jj]jk]jn]ujZjBjr]rC(j$)rC}rC(jYUjf}rC(jh]ji]jj]jk]jn]ujZjCjr]rCj)rC}rC(jYX 41502000.mmurCjZjCjbj:>jdjjf}rC(jh]ji]jj]jk]jn]ujpKjr]rCj{X 41502000.mmurCrC}rC(jYjCjZjCubaubajdj$ubj$)rC}rC(jYUjf}rC(jh]ji]jj]jk]jn]ujZjCjr]rCj)rC}rC(jYX DSP2 (MMU2)rCjZjCjbj:>jdjjf}rC(jh]ji]jj]jk]jn]ujpKjr]rCj{X DSP2 (MMU2)rCrC}rC(jYjCjZjCubaubajdj$ubejdj$ubejdjy%ubejdjz%ubaubj)rC}rC(jYXoSome of this information is inaccessible from a suspended state. Table 5 lists what can be found for each core.rCjZjBjbj:>jdjjf}rC(jh]ji]jj]jk]jn]ujpKjqhjr]rCj{XoSome of this information is inaccessible from a suspended state. Table 5 lists what can be found for each core.rCrC}rC(jYjCjZjCubaubj)rC}rC(jYXTable 5. IOMMU Debugfs EntriesrCjZjBjbj:>jdjjf}rC(jh]ji]jj]jk]jn]ujpKjqhjr]rCj{XTable 5. IOMMU Debugfs EntriesrCrC}rC(jYjCjZjCubaubjd$)rC}rC(jYUjZjBjbj:>jdjg$jf}rC(jh]ji]jj]jk]jn]ujpNjqhjr]rCjj$)rC}rC(jYUjf}rC(jk]jj]jh]ji]jn]UcolsKujZjCjr]rC(jo$)rC}rC(jYUjf}rC(jk]jj]jh]ji]jn]UcolwidthKujZjCjr]jdjs$ubjo$)rC}rC(jYUjf}rC(jk]jj]jh]ji]jn]UcolwidthK'ujZjCjr]jdjs$ubjz$)rC}rC(jYUjf}rC(jh]ji]jj]jk]jn]ujZjCjr]rCj$)rC}rC(jYUjf}rC(jh]ji]jj]jk]jn]ujZjCjr]rC(j$)rC}rC(jYUjf}rC(jh]ji]jj]jk]jn]ujZjCjr]rCj)rC}rC(jYXEntryrCjZjCjbj:>jdjjf}rC(jh]ji]jj]jk]jn]ujpKjr]rCj{XEntryrCrC}rC(jYjCjZjCubaubajdj$ubj$)rC}rC(jYUjf}rC(jh]ji]jj]jk]jn]ujZjCjr]rCj)rC}rC(jYX DescriptionrCjZjCjbj:>jdjjf}rC(jh]ji]jj]jk]jn]ujpKjr]rCj{X DescriptionrCrC}rC(jYjCjZjCubaubajdj$ubejdj$ubajdj$ubj$)rC}rC(jYUjf}rC(jh]ji]jj]jk]jn]ujZjCjr]rC(j$)rC}rC(jYUjf}rC(jh]ji]jj]jk]jn]ujZjCjr]rC(j$)rC}rC(jYUjf}rC(jh]ji]jj]jk]jn]ujZjCjr]rCj)rC}rC(jYXnr_tlb_entriesrCjZjCjbj:>jdjjf}rC(jh]ji]jj]jk]jn]ujpKjr]rCj{Xnr_tlb_entriesrCrC}rC(jYjCjZjCubaubajdj$ubj$)rC}rC(jYUjf}rC(jh]ji]jj]jk]jn]ujZjCjr]rCj)rC}rC(jYXGives the number of tlb entriesrCjZjCjbj:>jdjjf}rC(jh]ji]jj]jk]jn]ujpKjr]rCj{XGives the number of tlb entriesrCrC}rC(jYjCjZjCubaubajdj$ubejdj$ubj$)rC}rC(jYUjf}rC(jh]ji]jj]jk]jn]ujZjCjr]rC(j$)rC}rC(jYUjf}rC(jh]ji]jj]jk]jn]ujZjCjr]rDj)rD}rD(jYX pagetablerDjZjCjbj:>jdjjf}rD(jh]ji]jj]jk]jn]ujpKjr]rDj{X pagetablerDrD}rD(jYjDjZjDubaubajdj$ubj$)r D}r D(jYUjf}r D(jh]ji]jj]jk]jn]ujZjCjr]r Dj)r D}rD(jYXDumps the pagetable entriesrDjZj Djbj:>jdjjf}rD(jh]ji]jj]jk]jn]ujpKjr]rDj{XDumps the pagetable entriesrDrD}rD(jYjDjZj Dubaubajdj$ubejdj$ubj$)rD}rD(jYUjf}rD(jh]ji]jj]jk]jn]ujZjCjr]rD(j$)rD}rD(jYUjf}rD(jh]ji]jj]jk]jn]ujZjDjr]rDj)rD}rD(jYXregsrDjZjDjbj:>jdjjf}r D(jh]ji]jj]jk]jn]ujpKjr]r!Dj{Xregsr"Dr#D}r$D(jYjDjZjDubaubajdj$ubj$)r%D}r&D(jYUjf}r'D(jh]ji]jj]jk]jn]ujZjDjr]r(Dj)r)D}r*D(jYX%Gives the values of the MMU registersr+DjZj%Djbj:>jdjjf}r,D(jh]ji]jj]jk]jn]ujpKjr]r-Dj{X%Gives the values of the MMU registersr.Dr/D}r0D(jYj+DjZj)Dubaubajdj$ubejdj$ubj$)r1D}r2D(jYUjf}r3D(jh]ji]jj]jk]jn]ujZjCjr]r4D(j$)r5D}r6D(jYUjf}r7D(jh]ji]jj]jk]jn]ujZj1Djr]r8Dj)r9D}r:D(jYXtlbr;DjZj5Djbj:>jdjjf}rDr?D}r@D(jYj;DjZj9Dubaubajdj$ubj$)rAD}rBD(jYUjf}rCD(jh]ji]jj]jk]jn]ujZj1Djr]rDDj)rED}rFD(jYXLists the tlb entries.rGDjZjADjbj:>jdjjf}rHD(jh]ji]jj]jk]jn]ujpKjr]rIDj{XLists the tlb entries.rJDrKD}rLD(jYjGDjZjEDubaubajdj$ubejdj$ubejdjy%ubejdjz%ubaubeubj[)rMD}rND(jYUjZjwAjbj:>jdjejf}rOD(jh]ji]jj]jk]rPDU!qnx-remote-core-state-informationrQDajn]rRDh*aujpKjqhjr]rSD(jt)rTD}rUD(jYX%QNX – Remote Core State InformationrVDjZjMDjbj:>jdjxjf}rWD(jh]ji]jj]jk]jn]ujpKjqhjr]rXDj{X%QNX – Remote Core State InformationrYDrZD}r[D(jYjVDjZjTDubaubj)r\D}r]D(jYXRFind out the current state of the remote core by issuing the following command: ::jZjMDjbj:>jdjjf}r^D(jh]ji]jj]jk]jn]ujpKjqhjr]r_Dj{XOFind out the current state of the remote core by issuing the following command:r`DraD}rbD(jYXOFind out the current state of the remote core by issuing the following command:jZj\Dubaubj)rcD}rdD(jYXcat /dev/ipc-state/jZjMDjbj:>jdjjf}reD(jjjk]jj]jh]ji]jn]ujpMjqhjr]rfDj{Xcat /dev/ipc-state/rgDrhD}riD(jYUjZjcDubaubj)rjD}rkD(jYXThe “core_name” is the name of the remote core. Valid names for AM57xx are IPU1, IPU2, DSP1, and DSP2. The current state will show as “running” or “reset”.rlDjZjMDjbj:>jdjjf}rmD(jh]ji]jj]jk]jn]ujpMjqhjr]rnDj{XThe “core_name” is the name of the remote core. Valid names for AM57xx are IPU1, IPU2, DSP1, and DSP2. The current state will show as “running” or “reset”.roDrpD}rqD(jYjlDjZjjDubaubeubeubj[)rrD}rsD(jYUjZj(>jbj:>jdjejf}rtD(jh]ji]jj]jk]ruDUusing-code-composer-studiorvDajn]rwDhaujpMjqhjr]rxD(jt)ryD}rzD(jYXUsing Code Composer Studior{DjZjrDjbj:>jdjxjf}r|D(jh]ji]jj]jk]jn]ujpMjqhjr]r}Dj{XUsing Code Composer Studior~DrD}rD(jYj{DjZjyDubaubj)rD}rD(jYXA useful tool for debugging issues is Code Composer Studio. CCS allows easy connection to the remote core in order to see the state of the remote core.rDjZjrDjbj:>jdjjf}rD(jh]ji]jj]jk]jn]ujpM jqhjr]rDj{XA useful tool for debugging issues is Code Composer Studio. CCS allows easy connection to the remote core in order to see the state of the remote core.rDrD}rD(jYjDjZjDubaubj[)rD}rD(jYUjZjrDjbj:>jdjejf}rD(jh]ji]jj]jk]rDU debug-symbolsrDajn]rDhaujpM jqhjr]rD(jt)rD}rD(jYX Debug SymbolsrDjZjDjbj:>jdjxjf}rD(jh]ji]jj]jk]jn]ujpM jqhjr]rDj{X Debug SymbolsrDrD}rD(jYjDjZjDubaubj)rD}rD(jYXsThe remote core image must be built with debug symbols to see information such as the call stack and variables. Once attached, load the symbols. The symbols are built into the executable itself. When loading symbols, point to the same executable that is loaded on the target (or the unstripped version locally, if it is stripped to save space when loading to the target.)rDjZjDjbj:>jdjjf}rD(jh]ji]jj]jk]jn]ujpMjqhjr]rDj{XsThe remote core image must be built with debug symbols to see information such as the call stack and variables. Once attached, load the symbols. The symbols are built into the executable itself. When loading symbols, point to the same executable that is loaded on the target (or the unstripped version locally, if it is stripped to save space when loading to the target.)rDrD}rD(jYjDjZjDubaubeubj[)rD}rD(jYUjKjZjrDjbj:>jdjejf}rD(jh]ji]jj]jk]rDU3linux-and-android-disabling-remoteproc-auto-suspendrDajn]rDjaujpMjqhjr]rD(jt)rD}rD(jYX5Linux and Android - Disabling Remoteproc Auto-SuspendrDjZjDjbj:>jdjxjf}rD(jh]ji]jj]jk]jn]ujpMjqhjr]rDj{X5Linux and Android - Disabling Remoteproc Auto-SuspendrDrD}rD(jYjDjZjDubaubj)rD}rD(jYXYou may want to disable auto-suspend of the remote cores (provided that is not what is being debugged). When the core is suspended, you will not be able to connect to the remote core using CCS. Auto-suspend can be disabled by setting the power control to “on” for the remote core. ::jZjDjbj:>jdjjf}rD(jh]ji]jj]jk]jn]ujpMjqhjr]rDj{XYou may want to disable auto-suspend of the remote cores (provided that is not what is being debugged). When the core is suspended, you will not be able to connect to the remote core using CCS. Auto-suspend can be disabled by setting the power control to “on” for the remote core.rDrD}rD(jYXYou may want to disable auto-suspend of the remote cores (provided that is not what is being debugged). When the core is suspended, you will not be able to connect to the remote core using CCS. Auto-suspend can be disabled by setting the power control to “on” for the remote core.jZjDubaubj)rD}rD(jYX:echo on > /sys/bus/platform/devices//power/controljZjDjbj:>jdjjf}rD(jjjk]jj]jh]ji]jn]ujpMjqhjr]rDj{X:echo on > /sys/bus/platform/devices//power/controlrDrD}rD(jYUjZjDubaubj)rD}rD(jYXIThe remote core device name for each remote core can be found in Table 2.rDjZjDjbj:>jdjjf}rD(jh]ji]jj]jk]jn]ujpMjqhjr]rDj{XIThe remote core device name for each remote core can be found in Table 2.rDrD}rD(jYjDjZjDubaubeubj[)rD}rD(jYUjKjZjrDjbj:>jdjejf}rD(jh]ji]jj]jk]rDU$linux-and-android-disabling-watchdogrDajn]rDj2aujpMjqhjr]rD(jt)rD}rD(jYX(Linux and Android – Disabling WatchdogrDjZjDjbj:>jdjxjf}rD(jh]ji]jj]jk]jn]ujpMjqhjr]rDj{X(Linux and Android – Disabling WatchdogrDrD}rD(jYjDjZjDubaubj)rD}rD(jYX`You may decide to disable the watchdog timers when debugging and using CCS. Otherwise, while connected to the target, the watchdog may expire, triggering an abort sequence. Disable the watchdog timers for a remote core by removing their definitions from the dts file. For example, to disable the watchdog timers for IPU1, change the dts file as below::jZjDjbj:>jdjjf}rD(jh]ji]jj]jk]jn]ujpMjqhjr]rDj{X_You may decide to disable the watchdog timers when debugging and using CCS. Otherwise, while connected to the target, the watchdog may expire, triggering an abort sequence. Disable the watchdog timers for a remote core by removing their definitions from the dts file. For example, to disable the watchdog timers for IPU1, change the dts file as below:rDrD}rD(jYX_You may decide to disable the watchdog timers when debugging and using CCS. Otherwise, while connected to the target, the watchdog may expire, triggering an abort sequence. Disable the watchdog timers for a remote core by removing their definitions from the dts file. For example, to disable the watchdog timers for IPU1, change the dts file as below:jZjDubaubj)rD}rD(jYX&ipu1 { status = "okay"; memory-region = <&ipu1_cma_pool>; mboxes = <&mailbox5 &mbox_ipu1_legacy>; timers = <&timer11>; - watchdog-timers = <&timer7>, <&timer8>; + /*watchdog-timers = <&timer7>, <&timer8>;*/jZjDjbj:>jdjjf}rD(jjjk]jj]jh]ji]jn]ujpMjqhjr]rDj{X&ipu1 { status = "okay"; memory-region = <&ipu1_cma_pool>; mboxes = <&mailbox5 &mbox_ipu1_legacy>; timers = <&timer11>; - watchdog-timers = <&timer7>, <&timer8>; + /*watchdog-timers = <&timer7>, <&timer8>;*/rDrD}rD(jYUjZjDubaubeubj[)rD}rD(jYUjZjrDjbj:>jdjejf}rD(jh]ji]jj]jk]rDUsys-bios-disabling-watchdogrDajn]rDhaujpM3jqhjr]rD(jt)rD}rD(jYXSYS/BIOS – Disabling WatchdogrDjZjDjbj:>jdjxjf}rD(jh]ji]jj]jk]jn]ujpM3jqhjr]rDj{XSYS/BIOS – Disabling WatchdogrDrD}rD(jYjDjZjDubaubj)rD}rD(jYXWhen using QNX, you can disable the watchdog from within the remote core image itself. If using Linux or Android, this step is not required; simply follow the instructions in `Linux and Android – Disabling Watchdog`_.jZjDjbj:>jdjjf}rD(jh]ji]jj]jk]jn]ujpM4jqhjr]rD(j{XWhen using QNX, you can disable the watchdog from within the remote core image itself. If using Linux or Android, this step is not required; simply follow the instructions in rDrD}rD(jYXWhen using QNX, you can disable the watchdog from within the remote core image itself. If using Linux or Android, this step is not required; simply follow the instructions in jZjDubj)rD}rD(jYX+`Linux and Android – Disabling Watchdog`_jKjZjDjdjjf}rD(UnameX(Linux and Android – Disabling Watchdogjk]jj]jh]ji]jn]jjDujr]rDj{X(Linux and Android – Disabling WatchdogrDrD}rD(jYUjZjDubaubj{X.rD}rE(jYX.jZjDubeubj)rE}rE(jYX,To disable the usage of the watchdog from the remote core without completely disabling the device exception module (DEH), comment out the calls to Watchdog_init in the SYS/BIOS IPC code. These calls can be found in packages/ti/deh/Deh.c, packages/ti/deh/DehDsp.c, and packages/ti/ipc/ipcmgr/IpcMgr.c.rEjZjDjbj:>jdjjf}rE(jh]ji]jj]jk]jn]ujpM7jqhjr]rEj{X,To disable the usage of the watchdog from the remote core without completely disabling the device exception module (DEH), comment out the calls to Watchdog_init in the SYS/BIOS IPC code. These calls can be found in packages/ti/deh/Deh.c, packages/ti/deh/DehDsp.c, and packages/ti/ipc/ipcmgr/IpcMgr.c.rErE}rE(jYjEjZjEubaubj)r E}r E(jYXpackages/ti/deh/Deh.c::r EjZjDjbj:>jdjjf}r E(jh]ji]jj]jk]jn]ujpM;jqhjr]r Ej{Xpackages/ti/deh/Deh.c:rErE}rE(jYXpackages/ti/deh/Deh.c:jZj Eubaubj)rE}rE(jYX,/* * ======== Deh_Module_startup ======== */ Int Deh_Module_startup(Int phase) { if (AMMU_Module_startupDone() == TRUE) { - Watchdog_init(ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I); + //Watchdog_init(ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I); return Startup_DONE; } return Startup_NOTDONE; }jZjDjbj:>jdjjf}rE(jjjk]jj]jh]ji]jn]ujpMjqhjr]rEj{X,/* * ======== Deh_Module_startup ======== */ Int Deh_Module_startup(Int phase) { if (AMMU_Module_startupDone() == TRUE) { - Watchdog_init(ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I); + //Watchdog_init(ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I); return Startup_DONE; } return Startup_NOTDONE; }rErE}rE(jYUjZjEubaubj)rE}rE(jYXpackages/ti/deh/DehDsp.c::rEjZjDjbj:>jdjjf}rE(jh]ji]jj]jk]jn]ujpMKjqhjr]rEj{Xpackages/ti/deh/DehDsp.c:rErE}rE(jYXpackages/ti/deh/DehDsp.c:jZjEubaubj)r E}r!E(jYXInt Deh_Module_startup(Int phase) { #if defined(HAS_AMMU) if (AMMU_Module_startupDone() == TRUE) { - Watchdog_init((Void (*)(Void))ti_sysbios_family_c64p_Exception_handler); + //Watchdog_init((Void (*)(Void))ti_sysbios_family_c64p_Exception_handler); return Startup_DONE; } return Startup_NOTDONE; #else - Watchdog_init((Void (*)(Void))ti_sysbios_family_c64p_Exception_handler); + //Watchdog_init((Void (*)(Void))ti_sysbios_family_c64p_Exception_handler); return Startup_DONE; #endifjZjDjbj:>jdjjf}r"E(jjjk]jj]jh]ji]jn]ujpMjqhjr]r#Ej{XInt Deh_Module_startup(Int phase) { #if defined(HAS_AMMU) if (AMMU_Module_startupDone() == TRUE) { - Watchdog_init((Void (*)(Void))ti_sysbios_family_c64p_Exception_handler); + //Watchdog_init((Void (*)(Void))ti_sysbios_family_c64p_Exception_handler); return Startup_DONE; } return Startup_NOTDONE; #else - Watchdog_init((Void (*)(Void))ti_sysbios_family_c64p_Exception_handler); + //Watchdog_init((Void (*)(Void))ti_sysbios_family_c64p_Exception_handler); return Startup_DONE; #endifr$Er%E}r&E(jYUjZj Eubaubj)r'E}r(E(jYX!packages/ti/ipc/ipcmgr/IpcMgr.c::r)EjZjDjbj:>jdjjf}r*E(jh]ji]jj]jk]jn]ujpM\jqhjr]r+Ej{X packages/ti/ipc/ipcmgr/IpcMgr.c:r,Er-E}r.E(jYX packages/ti/ipc/ipcmgr/IpcMgr.c:jZj'Eubaubj)r/E}r0E(jYXuVoid IpcMgr_rpmsgStartup(Void) { Assert_isTrue(MultiProc_self() != MultiProc_getId("HOST"), NULL); RPMessage_init(MultiProc_getId("HOST")); -#ifdef IpcMgr_USEDEH +#if 0 /* * When using DEH, initialize the Watchdog timers if not already done * (i.e. late-attach) */ #ifdef IpcMgr_DSP Watchdog_init((Void (*)(Void))ti_sysbios_family_c64p_Exception_handler); #elif IpcMgr_IPU Watchdog_init(ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I); #endif #endif } [...] Void IpcMgr_ipcStartup(Void) { UInt procId = MultiProc_getId("HOST"); Int status; /* TransportRpmsgSetup will busy wait until host kicks ready to recv: */ status = TransportRpmsgSetup_attach(procId, 0); Assert_isTrue(status >= 0, NULL); /* Sets up to communicate with host's NameServer: */ status = NameServerRemoteRpmsg_attach(procId, 0); Assert_isTrue(status >= 0, NULL); -#ifdef IpcMgr_USEDEH +#if 0 /* * When using DEH, initialize the Watchdog timers if not already done * (i.e. late-attach) */ #ifdef IpcMgr_DSP Watchdog_init((Void (*)(Void))ti_sysbios_family_c64p_Exception_handler); #elif IpcMgr_IPU Watchdog_init(ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I); #endif #endif }jZjDjbj:>jdjjf}r1E(jjjk]jj]jh]ji]jn]ujpMjqhjr]r2Ej{XuVoid IpcMgr_rpmsgStartup(Void) { Assert_isTrue(MultiProc_self() != MultiProc_getId("HOST"), NULL); RPMessage_init(MultiProc_getId("HOST")); -#ifdef IpcMgr_USEDEH +#if 0 /* * When using DEH, initialize the Watchdog timers if not already done * (i.e. late-attach) */ #ifdef IpcMgr_DSP Watchdog_init((Void (*)(Void))ti_sysbios_family_c64p_Exception_handler); #elif IpcMgr_IPU Watchdog_init(ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I); #endif #endif } [...] Void IpcMgr_ipcStartup(Void) { UInt procId = MultiProc_getId("HOST"); Int status; /* TransportRpmsgSetup will busy wait until host kicks ready to recv: */ status = TransportRpmsgSetup_attach(procId, 0); Assert_isTrue(status >= 0, NULL); /* Sets up to communicate with host's NameServer: */ status = NameServerRemoteRpmsg_attach(procId, 0); Assert_isTrue(status >= 0, NULL); -#ifdef IpcMgr_USEDEH +#if 0 /* * When using DEH, initialize the Watchdog timers if not already done * (i.e. late-attach) */ #ifdef IpcMgr_DSP Watchdog_init((Void (*)(Void))ti_sysbios_family_c64p_Exception_handler); #elif IpcMgr_IPU Watchdog_init(ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I); #endif #endif }r3Er4E}r5E(jYUjZj/Eubaubj)r6E}r7E(jYXrFollowing this, rebuild the IPC and the remote core image to have an image with DEH, but without watchdog enabled.r8EjZjDjbj:>jdjjf}r9E(jh]ji]jj]jk]jn]ujpMjqhjr]r:Ej{XrFollowing this, rebuild the IPC and the remote core image to have an image with DEH, but without watchdog enabled.r;ErE}r?E(jYUjZjrDjbj:>jdjejf}r@E(jh]ji]jj]jk]rAEUattaching-before-the-issuerBEajn]rCEhaujpMjqhjr]rDE(jt)rEE}rFE(jYXAttaching Before the IssuerGEjZj>Ejbj:>jdjxjf}rHE(jh]ji]jj]jk]jn]ujpMjqhjr]rIEj{XAttaching Before the IssuerJErKE}rLE(jYjGEjZjEEubaubj)rME}rNE(jYX$In certain cases, you may want to attach to the remote core before the issue has occurred. If the issue is reliably reproducible and always occurs at the same location, then adding a breakpoint close to where the issue happens could be a good way to get a better picture of what is happening.rOEjZj>Ejbj:>jdjjf}rPE(jh]ji]jj]jk]jn]ujpMjqhjr]rQEj{X$In certain cases, you may want to attach to the remote core before the issue has occurred. If the issue is reliably reproducible and always occurs at the same location, then adding a breakpoint close to where the issue happens could be a good way to get a better picture of what is happening.rRErSE}rTE(jYjOEjZjMEubaubj)rUE}rVE(jYXOne instance where it may be difficult is if the issue is happening during boot-up of the remote core. In this case, it may be necessary to add a while loop in the main function, to attach before the issue occurs. Add a loop similar to this::jZj>Ejbj:>jdjjf}rWE(jh]ji]jj]jk]jn]ujpMjqhjr]rXEj{XOne instance where it may be difficult is if the issue is happening during boot-up of the remote core. In this case, it may be necessary to add a while loop in the main function, to attach before the issue occurs. Add a loop similar to this:rYErZE}r[E(jYXOne instance where it may be difficult is if the issue is happening during boot-up of the remote core. In this case, it may be necessary to add a while loop in the main function, to attach before the issue occurs. Add a loop similar to this:jZjUEubaubj)r\E}r]E(jYX&{ volatile int foo = 1; while (foo); }jZj>Ejbj:>jdjjf}r^E(jjjk]jj]jh]ji]jn]ujpM!jqhjr]r_Ej{X&{ volatile int foo = 1; while (foo); }r`EraE}rbE(jYUjZj\Eubaubj)rcE}rdE(jYXjThen, after attaching, load the symbols, add the breakpoints, change “foo” to 0, and continue running.reEjZj>Ejbj:>jdjjf}rfE(jh]ji]jj]jk]jn]ujpMjqhjr]rgEj{XjThen, after attaching, load the symbols, add the breakpoints, change “foo” to 0, and continue running.rhEriE}rjE(jYjeEjZjcEubaubeubj[)rkE}rlE(jYUjZjrDjbj:>jdjejf}rmE(jh]ji]jj]jk]rnEUattaching-after-the-issueroEajn]rpEhaujpMjqhjr]rqE(jt)rrE}rsE(jYXAttaching After the IssuertEjZjkEjbj:>jdjxjf}ruE(jh]ji]jj]jk]jn]ujpMjqhjr]rvEj{XAttaching After the IssuerwErxE}ryE(jYjtEjZjrEubaubj)rzE}r{E(jYXYou can also attach to the core after the issue, load the symbols, and see the state and view memory. You can view the Exception module’s exception CallStack ROV view and the task module’s per task CallStack ROV view. For more information about the runtime object viewer (ROV) in the RTSC documentation online, see `Runtime Object Viewer `_.jZjkEjbj:>jdjjf}r|E(jh]ji]jj]jk]jn]ujpMjqhjr]r}E(j{X?You can also attach to the core after the issue, load the symbols, and see the state and view memory. You can view the Exception module’s exception CallStack ROV view and the task module’s per task CallStack ROV view. For more information about the runtime object viewer (ROV) in the RTSC documentation online, see r~ErE}rE(jYX?You can also attach to the core after the issue, load the symbols, and see the state and view memory. You can view the Exception module’s exception CallStack ROV view and the task module’s per task CallStack ROV view. For more information about the runtime object viewer (ROV) in the RTSC documentation online, see jZjzEubj)rE}rE(jYXR`Runtime Object Viewer `_jf}rE(UnameXRuntime Object ViewerjX7http://rtsc.eclipse.org/docs-tip/Runtime_Object_Viewer/rEjk]jj]jh]ji]jn]ujZjzEjr]rEj{XRuntime Object ViewerrErE}rE(jYUjZjEubajdjubj)rE}rE(jYX: jKjZjzEjdjjf}rE(UrefurijEjk]rEUruntime-object-viewerrEajj]jh]ji]jn]rEhaujr]ubj{X.rE}rE(jYX.jZjzEubeubeubj[)rE}rE(jYUjZjrDjbj:>jdjejf}rE(jh]ji]jj]jk]rEU$viewing-the-state-of-the-remote-corerEajn]rEhaujpMjqhjr]rE(jt)rE}rE(jYX$Viewing the State of the Remote CorerEjZjEjbj:>jdjxjf}rE(jh]ji]jj]jk]jn]ujpMjqhjr]rEj{X$Viewing the State of the Remote CorerErE}rE(jYjEjZjEubaubj)rE}rE(jYXOnce attached and with symbols loaded, the state of the processor can be inspected. You can see the program counter, memory windows, registers, call stack, and the ROV, among other things.rEjZjEjbj:>jdjjf}rE(jh]ji]jj]jk]jn]ujpMjqhjr]rEj{XOnce attached and with symbols loaded, the state of the processor can be inspected. You can see the program counter, memory windows, registers, call stack, and the ROV, among other things.rErE}rE(jYjEjZjEubaubeubeubj[)rE}rE(jYUjKjZj(>jbj:>jdjejf}rE(jh]ji]jj]jk]rEj?ajn]rEh0aujpMjqhjr]rE(jt)rE}rE(jYX#Debugging MMU Faults and ExceptionsrEjZjEjbj:>jdjxjf}rE(jh]ji]jj]jk]jn]ujpMjqhjr]rEj{X#Debugging MMU Faults and ExceptionsrErE}rE(jYjEjZjEubaubj)rE}rE(jYXErrors commonly manifest as MMU faults, exceptions, and watchdog errors (if using a version of IPC with watchdog available and enabled).rEjZjEjbj:>jdjjf}rE(jh]ji]jj]jk]jn]ujpMjqhjr]rEj{XErrors commonly manifest as MMU faults, exceptions, and watchdog errors (if using a version of IPC with watchdog available and enabled).rErE}rE(jYjEjZjEubaubj[)rE}rE(jYUjKjZjEjbj:>jdjejf}rE(jh]ji]jj]jk]rEU*linux-and-android-disabling-error-recoveryrEajn]rEj,aujpMjqhjr]rE(jt)rE}rE(jYX,Linux and Android - Disabling Error RecoveryrEjZjEjbj:>jdjxjf}rE(jh]ji]jj]jk]jn]ujpMjqhjr]rEj{X,Linux and Android - Disabling Error RecoveryrErE}rE(jYjEjZjEubaubj)rE}rE(jYXTo debug an error, it may be necessary to turn of error recovery. Error recovery can be disabled by giving the following command::jZjEjbj:>jdjjf}rE(jh]ji]jj]jk]jn]ujpMjqhjr]rEj{XTo debug an error, it may be necessary to turn of error recovery. Error recovery can be disabled by giving the following command:rErE}rE(jYXTo debug an error, it may be necessary to turn of error recovery. Error recovery can be disabled by giving the following command:jZjEubaubj)rE}rE(jYXAecho disabled > /sys/kernel/debug/remoteproc/remoteprocX/recoveryjZjEjbj:>jdjjf}rE(jjjk]jj]jh]ji]jn]ujpM>jqhjr]rEj{XAecho disabled > /sys/kernel/debug/remoteproc/remoteprocX/recoveryrErE}rE(jYUjZjEubaubj)rE}rE(jYX;See `Linux and Android - Remoteproc`_ for more information.rEjZjEjbj:>jdjjf}rE(jh]ji]jj]jk]jn]ujpMjqhjr]rE(j{XSee rErE}rE(jYXSee jZjEubj)rE}rE(jYX!`Linux and Android - Remoteproc`_jKjZjEjdjjf}rE(UnameXLinux and Android - Remoteprocjk]jj]jh]ji]jn]jj@ujr]rEj{XLinux and Android - RemoteprocrErE}rE(jYUjZjEubaubj{X for more information.rErE}rE(jYX for more information.jZjEubeubeubj[)rE}rE(jYUjZjEjbj:>jdjejf}rE(jh]ji]jj]jk]rEUqnx-disabling-error-recoveryrEajn]rEj3aujpMjqhjr]rE(jt)rE}rE(jYX QNX – Disabling Error RecoveryrEjZjEjbj:>jdjxjf}rE(jh]ji]jj]jk]jn]ujpMjqhjr]rEj{X QNX – Disabling Error RecoveryrErE}rE(jYjEjZjEubaubj)rE}rE(jYXTo disable error recovery on QNX using IPC version 3.22 and above, give the -d option when launching the ipc binary. For example::jZjEjbj:>jdjjf}rE(jh]ji]jj]jk]jn]ujpMjqhjr]rEj{XTo disable error recovery on QNX using IPC version 3.22 and above, give the -d option when launching the ipc binary. For example:rFrF}rF(jYXTo disable error recovery on QNX using IPC version 3.22 and above, give the -d option when launching the ipc binary. For example:jZjEubaubj)rF}rF(jYX ipc –d IPU2 dra7x-ipu2-fw.xem4jZjEjbj:>jdjjf}rF(jjjk]jj]jh]ji]jn]ujpMGjqhjr]rFj{X ipc –d IPU2 dra7x-ipu2-fw.xem4rFrF}r F(jYUjZjFubaubeubj[)r F}r F(jYUjKjZjEjbj:>jdjejf}r F(jh]ji]jj]jk]r FU crash-dumprFajn]rFhIaujpMjqhjr]rF(jt)rF}rF(jYX Crash DumprFjZj Fjbj:>jdjxjf}rF(jh]ji]jj]jk]jn]ujpMjqhjr]rFj{X Crash DumprFrF}rF(jYjFjZjFubaubj)rF}rF(jYXIf any of these three errors are encountered, you will get a crash dump from the remote core which is visible in the remote core traces. If error recovery is disabled, the dump can be found in trace0 (when using Linux/Android) or in /dev/ipc-trace/ (when using QNX); otherwise, the trace is found in trace0_last (when using Linux/Android) and in the logfile (when using QNX).rFjZj Fjbj:>jdjjf}rF(jh]ji]jj]jk]jn]ujpMjqhjr]rFj{XIf any of these three errors are encountered, you will get a crash dump from the remote core which is visible in the remote core traces. If error recovery is disabled, the dump can be found in trace0 (when using Linux/Android) or in /dev/ipc-trace/ (when using QNX); otherwise, the trace is found in trace0_last (when using Linux/Android) and in the logfile (when using QNX).rFrF}r F(jYjFjZjFubaubj)r!F}r"F(jYX2An example of the crash dump will look like this::r#FjZj Fjbj:>jdjjf}r$F(jh]ji]jj]jk]jn]ujpMjqhjr]r%Fj{X1An example of the crash dump will look like this:r&Fr'F}r(F(jYX1An example of the crash dump will look like this:jZj!Fubaubj)r)F}r*F(jYX [0] [ 91.045] Exception occurred at (PC) = 0000c976 [0] [ 91.045] CPU context: thread [0] [ 91.045] BIOS Task name: {empty-instance-name} handle: 0x80060090. [0] [ 91.045] BIOS Task stack base: 0x800600e0. [0] [ 91.045] BIOS Task stack size: 0x800. [0] [ 91.045] [t=0x18f6df13] ti.sysbios.family.arm.m3.Hwi: ERROR: line 1078: E_hardFault: FORCED [0] [ 91.045] ti.sysbios.family.arm.m3.Hwi: line 1078: E_hardFault: FORCED [0] [ 91.045] [t=0x18f9a0cb] ti.sysbios.family.arm.m3.Hwi: ERROR: line 1155: E_busFault: PRECISERR: Immediate Bus Fault, exact addr known, address: 96000000 [0] [ 91.045] ti.sysbios.family.arm.m3.Hwi: line 1155: E_busFault: PRECISERR: Immediate Bus Fault, exact addr known, address: 96000000 [0] [ 91.045] R0 = 0x96000000 R8 = 0xffffffff [0] [ 91.045] R1 = 0x00000000 R9 = 0xffffffff [0] [ 91.045] R2 = 0x00000000 R10 = 0xffffffff [0] [ 91.045] R3 = 0x80060814 R11 = 0xffffffff [0] [ 91.045] R4 = 0x00013098 R12 = 0x8006074c [0] [ 91.045] R5 = 0x0000000a SP(R13) = 0x80060820 [0] [ 91.045] R6 = 0xffffffff LR(R14) = 0x0000c973 [0] [ 91.045] R7 = 0xffffffff PC(R15) = 0x0000c976 [0] [ 91.045] PSR = 0x61000000 [0] [ 91.045] ICSR = 0x00438803 [0] [ 91.045] MMFSR = 0x00 [0] [ 91.045] BFSR = 0x82 [0] [ 91.045] UFSR = 0x0000 [0] [ 91.045] HFSR = 0x40000000 [0] [ 91.045] DFSR = 0x00000000 [0] [ 91.045] MMAR = 0x96000000 [0] [ 91.045] BFAR = 0x96000000 [0] [ 91.045] AFSR = 0x00000000 [0] [ 91.045] Stack trace [0] [ 91.045] 00 [op faaaf00e] 00006abd (ret from call to 00015010) [0] [ 91.045] 01 [op ff49f005] 00006ac3 (ret from call to 0000c954) [0] [ 91.045] -- [op 98009000] 000154c9 [0] [ 91.045] -- [op 00000000] 000a0001 [0] [ 91.045] -- [op 80084a64] 0000fec9 [0] [ 91.045] -- [op 0001a75c] 000068b9 [0] [ 91.045] -- [op 80084a64] 0000fec9 [0] [ 91.045] -- [op bd0ef919] 00015b91 [0] [ 91.045] Stack dump base 800600e0 size 2048 sp 80060820: [0] [ 91.045] 80060820: 00000001 00006abd 96000000 00000000 ffffffff 00006ac3 0000000a 00006bf4 [0] [ 91.045] 80060840: 00000000 00000000 80041800 80060ab0 00000080 56414c53 50495f45 be003155 [0] [ 91.045] 80060860: bebebebe bebebebe bebebebe bebebebe bebebebe bebebebe bebebebe bebebebe [0] [ 91.045] 80060880: bebebebe bebebebe bebebebe bebebebe bebebebe 00000000 00000000 00000001 [0] [ 91.045] 800608a0: 00000001 000154c9 0001309a 0000000a 00000000 80041820 00000001 ffffffff [0] [ 91.045] 800608c0: ffffffff 0000fec9 00000000 00000000 000068b9 0000fec9 00015b91 bebebebe [0] [ 91.045] Terminating execution...jZj Fjbj:>jdjjf}r+F(jjjk]jj]jh]ji]jn]ujpMRjqhjr]r,Fj{X [0] [ 91.045] Exception occurred at (PC) = 0000c976 [0] [ 91.045] CPU context: thread [0] [ 91.045] BIOS Task name: {empty-instance-name} handle: 0x80060090. [0] [ 91.045] BIOS Task stack base: 0x800600e0. [0] [ 91.045] BIOS Task stack size: 0x800. [0] [ 91.045] [t=0x18f6df13] ti.sysbios.family.arm.m3.Hwi: ERROR: line 1078: E_hardFault: FORCED [0] [ 91.045] ti.sysbios.family.arm.m3.Hwi: line 1078: E_hardFault: FORCED [0] [ 91.045] [t=0x18f9a0cb] ti.sysbios.family.arm.m3.Hwi: ERROR: line 1155: E_busFault: PRECISERR: Immediate Bus Fault, exact addr known, address: 96000000 [0] [ 91.045] ti.sysbios.family.arm.m3.Hwi: line 1155: E_busFault: PRECISERR: Immediate Bus Fault, exact addr known, address: 96000000 [0] [ 91.045] R0 = 0x96000000 R8 = 0xffffffff [0] [ 91.045] R1 = 0x00000000 R9 = 0xffffffff [0] [ 91.045] R2 = 0x00000000 R10 = 0xffffffff [0] [ 91.045] R3 = 0x80060814 R11 = 0xffffffff [0] [ 91.045] R4 = 0x00013098 R12 = 0x8006074c [0] [ 91.045] R5 = 0x0000000a SP(R13) = 0x80060820 [0] [ 91.045] R6 = 0xffffffff LR(R14) = 0x0000c973 [0] [ 91.045] R7 = 0xffffffff PC(R15) = 0x0000c976 [0] [ 91.045] PSR = 0x61000000 [0] [ 91.045] ICSR = 0x00438803 [0] [ 91.045] MMFSR = 0x00 [0] [ 91.045] BFSR = 0x82 [0] [ 91.045] UFSR = 0x0000 [0] [ 91.045] HFSR = 0x40000000 [0] [ 91.045] DFSR = 0x00000000 [0] [ 91.045] MMAR = 0x96000000 [0] [ 91.045] BFAR = 0x96000000 [0] [ 91.045] AFSR = 0x00000000 [0] [ 91.045] Stack trace [0] [ 91.045] 00 [op faaaf00e] 00006abd (ret from call to 00015010) [0] [ 91.045] 01 [op ff49f005] 00006ac3 (ret from call to 0000c954) [0] [ 91.045] -- [op 98009000] 000154c9 [0] [ 91.045] -- [op 00000000] 000a0001 [0] [ 91.045] -- [op 80084a64] 0000fec9 [0] [ 91.045] -- [op 0001a75c] 000068b9 [0] [ 91.045] -- [op 80084a64] 0000fec9 [0] [ 91.045] -- [op bd0ef919] 00015b91 [0] [ 91.045] Stack dump base 800600e0 size 2048 sp 80060820: [0] [ 91.045] 80060820: 00000001 00006abd 96000000 00000000 ffffffff 00006ac3 0000000a 00006bf4 [0] [ 91.045] 80060840: 00000000 00000000 80041800 80060ab0 00000080 56414c53 50495f45 be003155 [0] [ 91.045] 80060860: bebebebe bebebebe bebebebe bebebebe bebebebe bebebebe bebebebe bebebebe [0] [ 91.045] 80060880: bebebebe bebebebe bebebebe bebebebe bebebebe 00000000 00000000 00000001 [0] [ 91.045] 800608a0: 00000001 000154c9 0001309a 0000000a 00000000 80041820 00000001 ffffffff [0] [ 91.045] 800608c0: ffffffff 0000fec9 00000000 00000000 000068b9 0000fec9 00015b91 bebebebe [0] [ 91.045] Terminating execution...r-Fr.F}r/F(jYUjZj)Fubaubeubj[)r0F}r1F(jYUjZjEjbj:>jdjejf}r2F(jh]ji]jj]jk]r3FUexception-dump-decodingr4Fajn]r5FhaujpM!jqhjr]r6F(jt)r7F}r8F(jYXException Dump Decodingr9FjZj0Fjbj:>jdjxjf}r:F(jh]ji]jj]jk]jn]ujpM!jqhjr]r;Fj{XException Dump DecodingrF(jYj9FjZj7Fubaubj)r?F}r@F(jYXzSome useful information that can be found in the dump is the fault address, PC address, register contents, and call stack.rAFjZj0Fjbj:>jdjjf}rBF(jh]ji]jj]jk]jn]ujpM"jqhjr]rCFj{XzSome useful information that can be found in the dump is the fault address, PC address, register contents, and call stack.rDFrEF}rFF(jYjAFjZj?Fubaubj)rGF}rHF(jYXpWhen an error occurs, you gets a crash dump from the remote core that looks similar to the one in `Crash Dump`_.rIFjZj0Fjbj:>jdjjf}rJF(jh]ji]jj]jk]jn]ujpM$jqhjr]rKF(j{XbWhen an error occurs, you gets a crash dump from the remote core that looks similar to the one in rLFrMF}rNF(jYXbWhen an error occurs, you gets a crash dump from the remote core that looks similar to the one in jZjGFubj)rOF}rPF(jYX `Crash Dump`_jKjZjGFjdjjf}rQF(UnameX Crash Dumpjk]jj]jh]ji]jn]jjFujr]rRFj{X Crash DumprSFrTF}rUF(jYUjZjOFubaubj{X.rVF}rWF(jYX.jZjGFubeubj)rXF}rYF(jYXThe particular dump example above is from a MMU read fault. This dump provides important information in helping to understand what has happened. Some of the useful parts are broken down in the following section.rZFjZj0Fjbj:>jdjjf}r[F(jh]ji]jj]jk]jn]ujpM&jqhjr]r\Fj{XThe particular dump example above is from a MMU read fault. This dump provides important information in helping to understand what has happened. Some of the useful parts are broken down in the following section.r]Fr^F}r_F(jYjZFjZjXFubaubj)r`F}raF(jYX **Timestamp**rbFjZj0Fjbj:>jdjjf}rcF(jh]ji]jj]jk]jn]ujpM*jqhjr]rdFj)reF}rfF(jYjbFjf}rgF(jh]ji]jj]jk]jn]ujZj`Fjr]rhFj{X TimestampriFrjF}rkF(jYUjZjeFubajdjubaubj)rlF}rmF(jYX~All traces (not just exception dumps) provide a timestamp for each trace. The time starts from the booting of the remote core.rnFjZj0Fjbj:>jdjjf}roF(jh]ji]jj]jk]jn]ujpM,jqhjr]rpFj{X~All traces (not just exception dumps) provide a timestamp for each trace. The time starts from the booting of the remote core.rqFrrF}rsF(jYjnFjZjlFubaubj=)rtF}ruF(jYUjZj0Fjbj:>jdj@jf}rvF(jh]ji]jj]jk]jn]ujpNjqhjr]rwF(j)rxF}ryF(jYX7[0] **[ 91.045]** Exception occurred at (PC) = 0000c976jZjtFjbj:>jdjjf}rzF(jh]ji]jj]jk]jn]ujpM/jr]r{F(j{X[0] r|Fr}F}r~F(jYX[0] jZjxFubj)rF}rF(jYX **[ 91.045]**jf}rF(jh]ji]jj]jk]jn]ujZjxFjr]rFj{X [ 91.045]rFrF}rF(jYUjZjFubajdjubj{X& Exception occurred at (PC) = 0000c976rFrF}rF(jYX& Exception occurred at (PC) = 0000c976jZjxFubeubj)rF}rF(jYX%[0] **[ 91.045]** CPU context: threadjZjtFjbj:>jdjjf}rF(jh]ji]jj]jk]jn]ujpM1jr]rF(j{X[0] rFrF}rF(jYX[0] jZjFubj)rF}rF(jYX **[ 91.045]**jf}rF(jh]ji]jj]jk]jn]ujZjFjr]rFj{X [ 91.045]rFrF}rF(jYUjZjFubajdjubj{X CPU context: threadrFrF}rF(jYX CPU context: threadjZjFubeubj)rF}rF(jYXK[0] **[ 91.045]** BIOS Task name: {empty-instance-name} handle: 0x80060090.jZjtFjbj:>jdjjf}rF(jh]ji]jj]jk]jn]ujpM3jr]rF(j{X[0] rFrF}rF(jYX[0] jZjFubj)rF}rF(jYX **[ 91.045]**jf}rF(jh]ji]jj]jk]jn]ujZjFjr]rFj{X [ 91.045]rFrF}rF(jYUjZjFubajdjubj{X: BIOS Task name: {empty-instance-name} handle: 0x80060090.rFrF}rF(jYX: BIOS Task name: {empty-instance-name} handle: 0x80060090.jZjFubeubeubj)rF}rF(jYXThe timestamp information can be useful even in non-crash situations, indicating the amount of time taken between two events. You can add traces at each event and then see when the events run.rFjZj0Fjbj:>jdjjf}rF(jh]ji]jj]jk]jn]ujpM5jqhjr]rFj{XThe timestamp information can be useful even in non-crash situations, indicating the amount of time taken between two events. You can add traces at each event and then see when the events run.rFrF}rF(jYjFjZjFubaubj)rF}rF(jYXFor example, to check that a certain event is happening every second, put a trace at that event, then check the timestamps to see that it is happening as expected.rFjZj0Fjbj:>jdjjf}rF(jh]ji]jj]jk]jn]ujpM8jqhjr]rFj{XFor example, to check that a certain event is happening every second, put a trace at that event, then check the timestamps to see that it is happening as expected.rFrF}rF(jYjFjZjFubaubj)rF}rF(jYX**PC Address**rFjZj0Fjbj:>jdjjf}rF(jh]ji]jj]jk]jn]ujpM;jqhjr]rFj)rF}rF(jYjFjf}rF(jh]ji]jj]jk]jn]ujZjFjr]rFj{X PC AddressrFrF}rF(jYUjZjFubajdjubaubj)rF}rF(jYXThe PC address where the exception occurred is also provided. This can be used, in conjunction with the map file or CCS, to identify the line of code where the exception happened.rFjZj0Fjbj:>jdjjf}rF(jh]ji]jj]jk]jn]ujpM=jqhjr]rFj{XThe PC address where the exception occurred is also provided. This can be used, in conjunction with the map file or CCS, to identify the line of code where the exception happened.rFrF}rF(jYjFjZjFubaubj=)rF}rF(jYUjZj0Fjbj:>jdj@jf}rF(jh]ji]jj]jk]jn]ujpNjqhjr]rF(j)rF}rF(jYX7[0] [ 91.045] **Exception occurred at (PC) = 0000c976**jZjFjbj:>jdjjf}rF(jh]ji]jj]jk]jn]ujpM@jr]rF(j{X[0] [ 91.045] rFrF}rF(jYX[0] [ 91.045] jZjFubj)rF}rF(jYX)**Exception occurred at (PC) = 0000c976**jf}rF(jh]ji]jj]jk]jn]ujZjFjr]rFj{X%Exception occurred at (PC) = 0000c976rFrF}rF(jYUjZjFubajdjubeubj)rF}rF(jYX![0] [ 91.045] CPU context: threadrFjZjFjbj:>jdjjf}rF(jh]ji]jj]jk]jn]ujpMBjr]rFj{X![0] [ 91.045] CPU context: threadrFrF}rF(jYjFjZjFubaubj)rF}rF(jYXG[0] [ 91.045] BIOS Task name: {empty-instance-name} handle: 0x80060090.rFjZjFjbj:>jdjjf}rF(jh]ji]jj]jk]jn]ujpMDjr]rFj{XG[0] [ 91.045] BIOS Task name: {empty-instance-name} handle: 0x80060090.rFrF}rF(jYjFjZjFubaubeubj)rF}rF(jYX**Task Information**rFjZj0Fjbj:>jdjjf}rF(jh]ji]jj]jk]jn]ujpMFjqhjr]rFj)rF}rF(jYjFjf}rF(jh]ji]jj]jk]jn]ujZjFjr]rFj{XTask InformationrFrF}rF(jYUjZjFubajdjubaubj)rF}rF(jYX_The information about the task that was executing when the exception occurred is also provided.rFjZj0Fjbj:>jdjjf}rG(jh]ji]jj]jk]jn]ujpMHjqhjr]rGj{X_The information about the task that was executing when the exception occurred is also provided.rGrG}rG(jYjFjZjFubaubj=)rG}rG(jYUjZj0Fjbj:>jdj@jf}rG(jh]ji]jj]jk]jn]ujpNjqhjr]rG(j)r G}r G(jYX3[0] [ 91.045] Exception occurred at (PC) = 0000c976r GjZjGjbj:>jdjjf}r G(jh]ji]jj]jk]jn]ujpMJjr]r Gj{X3[0] [ 91.045] Exception occurred at (PC) = 0000c976rGrG}rG(jYj GjZj Gubaubj)rG}rG(jYX![0] [ 91.045] CPU context: threadrGjZjGjbj:>jdjjf}rG(jh]ji]jj]jk]jn]ujpMLjr]rGj{X![0] [ 91.045] CPU context: threadrGrG}rG(jYjGjZjGubaubj)rG}rG(jYXK[0] **[ 91.045] BIOS Task name: {empty-instance-name} handle: 0x80060090.**jZjGjbj:>jdjjf}rG(jh]ji]jj]jk]jn]ujpMNjr]rG(j{X[0] rGrG}rG(jYX[0] jZjGubj)r G}r!G(jYXG**[ 91.045] BIOS Task name: {empty-instance-name} handle: 0x80060090.**jf}r"G(jh]ji]jj]jk]jn]ujZjGjr]r#Gj{XC[ 91.045] BIOS Task name: {empty-instance-name} handle: 0x80060090.r$Gr%G}r&G(jYUjZj Gubajdjubeubj)r'G}r(G(jYX3[0] **[ 91.045] BIOS Task stack base: 0x800600e0.**jZjGjbj:>jdjjf}r)G(jh]ji]jj]jk]jn]ujpMPjr]r*G(j{X[0] r+Gr,G}r-G(jYX[0] jZj'Gubj)r.G}r/G(jYX/**[ 91.045] BIOS Task stack base: 0x800600e0.**jf}r0G(jh]ji]jj]jk]jn]ujZj'Gjr]r1Gj{X+[ 91.045] BIOS Task stack base: 0x800600e0.r2Gr3G}r4G(jYUjZj.Gubajdjubeubj)r5G}r6G(jYX.[0] **[ 91.045] BIOS Task stack size: 0x800.**jZjGjbj:>jdjjf}r7G(jh]ji]jj]jk]jn]ujpMRjr]r8G(j{X[0] r9Gr:G}r;G(jYX[0] jZj5Gubj)rG(jh]ji]jj]jk]jn]ujZj5Gjr]r?Gj{X&[ 91.045] BIOS Task stack size: 0x800.r@GrAG}rBG(jYUjZjjdjjf}rFG(jh]ji]jj]jk]jn]ujpMTjqhjr]rGGj)rHG}rIG(jYjEGjf}rJG(jh]ji]jj]jk]jn]ujZjCGjr]rKGj{XFault InformationrLGrMG}rNG(jYUjZjHGubajdjubaubj)rOG}rPG(jYXThe information about the fault is also provided. This can look different depending on the type of exception that occurred, but often provides a fault address to identify the source of the fault.rQGjZj0Fjbj:>jdjjf}rRG(jh]ji]jj]jk]jn]ujpMVjqhjr]rSGj{XThe information about the fault is also provided. This can look different depending on the type of exception that occurred, but often provides a fault address to identify the source of the fault.rTGrUG}rVG(jYjQGjZjOGubaubj=)rWG}rXG(jYUjZj0Fjbj:>jdj@jf}rYG(jh]ji]jj]jk]jn]ujpNjqhjr]rZG(j)r[G}r\G(jYX3[0] [ 91.045] Exception occurred at (PC) = 0000c976r]GjZjWGjbj:>jdjjf}r^G(jh]ji]jj]jk]jn]ujpMYjr]r_Gj{X3[0] [ 91.045] Exception occurred at (PC) = 0000c976r`GraG}rbG(jYj]GjZj[Gubaubj)rcG}rdG(jYX![0] [ 91.045] CPU context: threadreGjZjWGjbj:>jdjjf}rfG(jh]ji]jj]jk]jn]ujpM[jr]rgGj{X![0] [ 91.045] CPU context: threadrhGriG}rjG(jYjeGjZjcGubaubj)rkG}rlG(jYXG[0] [ 91.045] BIOS Task name: {empty-instance-name} handle: 0x80060090.rmGjZjWGjbj:>jdjjf}rnG(jh]ji]jj]jk]jn]ujpM]jr]roGj{XG[0] [ 91.045] BIOS Task name: {empty-instance-name} handle: 0x80060090.rpGrqG}rrG(jYjmGjZjkGubaubj)rsG}rtG(jYX/[0] [ 91.045] BIOS Task stack base: 0x800600e0.ruGjZjWGjbj:>jdjjf}rvG(jh]ji]jj]jk]jn]ujpM_jr]rwGj{X/[0] [ 91.045] BIOS Task stack base: 0x800600e0.rxGryG}rzG(jYjuGjZjsGubaubj)r{G}r|G(jYX*[0] [ 91.045] BIOS Task stack size: 0x800.r}GjZjWGjbj:>jdjjf}r~G(jh]ji]jj]jk]jn]ujpMajr]rGj{X*[0] [ 91.045] BIOS Task stack size: 0x800.rGrG}rG(jYj}GjZj{Gubaubj)rG}rG(jYXd[0] [ 91.045] **[t=0x18f6df13] ti.sysbios.family.arm.m3.Hwi: ERROR: line 1078: E_hardFault: FORCED**jZjWGjbj:>jdjjf}rG(jh]ji]jj]jk]jn]ujpMcjr]rG(j{X[0] [ 91.045] rGrG}rG(jYX[0] [ 91.045] jZjGubj)rG}rG(jYXV**[t=0x18f6df13] ti.sysbios.family.arm.m3.Hwi: ERROR: line 1078: E_hardFault: FORCED**jf}rG(jh]ji]jj]jk]jn]ujZjGjr]rGj{XR[t=0x18f6df13] ti.sysbios.family.arm.m3.Hwi: ERROR: line 1078: E_hardFault: FORCEDrGrG}rG(jYUjZjGubajdjubeubj)rG}rG(jYXN[0] [ 91.045] **ti.sysbios.family.arm.m3.Hwi: line 1078: E_hardFault: FORCED**jZjWGjbj:>jdjjf}rG(jh]ji]jj]jk]jn]ujpMejr]rG(j{X[0] [ 91.045] rGrG}rG(jYX[0] [ 91.045] jZjGubj)rG}rG(jYX@**ti.sysbios.family.arm.m3.Hwi: line 1078: E_hardFault: FORCED**jf}rG(jh]ji]jj]jk]jn]ujZjGjr]rGj{X<ti.sysbios.family.arm.m3.Hwi: line 1078: E_hardFault: FORCEDrGrG}rG(jYUjZjGubajdjubeubj)rG}rG(jYX[0] [ 91.045] **[t=0x18f9a0cb] ti.sysbios.family.arm.m3.Hwi: ERROR: line 1155: E_busFault: PRECISERR: Immediate Bus Fault, exact addr known, address: 96000000**jZjWGjbj:>jdjjf}rG(jh]ji]jj]jk]jn]ujpMgjr]rG(j{X[0] [ 91.045] rGrG}rG(jYX[0] [ 91.045] jZjGubj)rG}rG(jYX**[t=0x18f9a0cb] ti.sysbios.family.arm.m3.Hwi: ERROR: line 1155: E_busFault: PRECISERR: Immediate Bus Fault, exact addr known, address: 96000000**jf}rG(jh]ji]jj]jk]jn]ujZjGjr]rGj{X[t=0x18f9a0cb] ti.sysbios.family.arm.m3.Hwi: ERROR: line 1155: E_busFault: PRECISERR: Immediate Bus Fault, exact addr known, address: 96000000rGrG}rG(jYUjZjGubajdjubeubj)rG}rG(jYX[0] [ 91.045] **ti.sysbios.family.arm.m3.Hwi: line 1155: E_busFault: PRECISERR: Immediate Bus Fault, exact addr known, address: 96000000**jZjWGjbj:>jdjjf}rG(jh]ji]jj]jk]jn]ujpMijr]rG(j{X[0] [ 91.045] rGrG}rG(jYX[0] [ 91.045] jZjGubj)rG}rG(jYX|**ti.sysbios.family.arm.m3.Hwi: line 1155: E_busFault: PRECISERR: Immediate Bus Fault, exact addr known, address: 96000000**jf}rG(jh]ji]jj]jk]jn]ujZjGjr]rGj{Xxti.sysbios.family.arm.m3.Hwi: line 1155: E_busFault: PRECISERR: Immediate Bus Fault, exact addr known, address: 96000000rGrG}rG(jYUjZjGubajdjubeubeubj)rG}rG(jYX **Registers**rGjZj0Fjbj:>jdjjf}rG(jh]ji]jj]jk]jn]ujpMkjqhjr]rGj)rG}rG(jYjGjf}rG(jh]ji]jj]jk]jn]ujZjGjr]rGj{X RegistersrGrG}rG(jYUjZjGubajdjubaubj)rG}rG(jYXNA dump of the register contents at the time of the exception is also provided.rGjZj0Fjbj:>jdjjf}rG(jh]ji]jj]jk]jn]ujpMmjqhjr]rGj{XNA dump of the register contents at the time of the exception is also provided.rGrG}rG(jYjGjZjGubaubjB)rG}rG(jYX&.. image:: ../images/RegisterDump.PNG jZj0Fjbj:>jdjEjf}rG(UuriXrtos/../images/RegisterDump.PNGrGjk]jj]jh]ji]jH}rGU*jGsjn]ujpMpjqhjr]ubj)rG}rG(jYX**Stack Trace**rGjZj0Fjbj:>jdjjf}rG(jh]ji]jj]jk]jn]ujpMqjqhjr]rGj)rG}rG(jYjGjf}rG(jh]ji]jj]jk]jn]ujZjGjr]rGj{X Stack TracerGrG}rG(jYUjZjGubajdjubaubj)rG}rG(jYXThe stack trace is also provided (see Figure 6). This can be used in conjunction with the source code and the map file or CCS to get more information about what was executing at the time of the crash.rGjZj0Fjbj:>jdjjf}rG(jh]ji]jj]jk]jn]ujpMsjqhjr]rGj{XThe stack trace is also provided (see Figure 6). This can be used in conjunction with the source code and the map file or CCS to get more information about what was executing at the time of the crash.rGrG}rG(jYjGjZjGubaubjB)rG}rG(jYX(.. image:: ../images/StackTraceDump.PNG jZj0Fjbj:>jdjEjf}rG(UuriX!rtos/../images/StackTraceDump.PNGrGjk]jj]jh]ji]jH}rGU*jGsjn]ujpMwjqhjr]ubeubj[)rG}rG(jYUjZjEjbj:>jdjejf}rG(jh]ji]jj]jk]rGU mmu-faultsrGajn]rGjaujpMyjqhjr]rG(jt)rG}rG(jYX MMU FaultsrGjZjGjbj:>jdjxjf}rG(jh]ji]jj]jk]jn]ujpMyjqhjr]rGj{X MMU FaultsrGrG}rG(jYjGjZjGubaubj)rG}rG(jYXMMU faults occur when an address that is not mapped to the remote core MMU is accessed. This can be due to a read, write, or an attempt to execute the address. When an MMU fault occurs, a crash dump from the remote core occurs that looks similar to the example provided in `Crash Dump`_.jZjGjbj:>jdjjf}rG(jh]ji]jj]jk]jn]ujpM{jqhjr]rG(j{XMMU faults occur when an address that is not mapped to the remote core MMU is accessed. This can be due to a read, write, or an attempt to execute the address. When an MMU fault occurs, a crash dump from the remote core occurs that looks similar to the example provided in rHrH}rH(jYXMMU faults occur when an address that is not mapped to the remote core MMU is accessed. This can be due to a read, write, or an attempt to execute the address. When an MMU fault occurs, a crash dump from the remote core occurs that looks similar to the example provided in jZjGubj)rH}rH(jYX `Crash Dump`_jKjZjGjdjjf}rH(UnameX Crash Dumpjk]jj]jh]ji]jn]jjFujr]rHj{X Crash DumprHrH}r H(jYUjZjHubaubj{X.r H}r H(jYX.jZjGubeubj)r H}r H(jYX}Some debugging techniques, as well as common times when an MMU fault occurs, are given as examples in the following sections.rHjZjGjbj:>jdjjf}rH(jh]ji]jj]jk]jn]ujpMjqhjr]rHj{X}Some debugging techniques, as well as common times when an MMU fault occurs, are given as examples in the following sections.rHrH}rH(jYjHjZj Hubaubj)rH}rH(jYX5**Using CCS to Halt the Code When the Fault Happens**rHjZjGjbj:>jdjjf}rH(jh]ji]jj]jk]jn]ujpMjqhjr]rHj)rH}rH(jYjHjf}rH(jh]ji]jj]jk]jn]ujZjHjr]rHj{X1Using CCS to Halt the Code When the Fault HappensrHrH}rH(jYUjZjHubajdjubaubj)r H}r!H(jYXIIf the fault always happens at the same address, pre-map the location and then set up CCS with a breakpoint for that address. In this way, you can view the state of the remote core when the fault happens and see the call stack. From there, put a breakpoint at the surrounding code and step through to see where the fault happens.r"HjZjGjbj:>jdjjf}r#H(jh]ji]jj]jk]jn]ujpMjqhjr]r$Hj{XIIf the fault always happens at the same address, pre-map the location and then set up CCS with a breakpoint for that address. In this way, you can view the state of the remote core when the fault happens and see the call stack. From there, put a breakpoint at the surrounding code and step through to see where the fault happens.r%Hr&H}r'H(jYj"HjZj Hubaubj)r(H}r)H(jYX)Pre-mapping the address can be done either through the remote core resource table, or through CCS. With CCS, you can connect to the debug DAP and then bring up a memory window to inspect the MMU registers. Directly program the MMU from here to map some unused memory to the fault address location.r*HjZjGjbj:>jdjjf}r+H(jh]ji]jj]jk]jn]ujpMjqhjr]r,Hj{X)Pre-mapping the address can be done either through the remote core resource table, or through CCS. With CCS, you can connect to the debug DAP and then bring up a memory window to inspect the MMU registers. Directly program the MMU from here to map some unused memory to the fault address location.r-Hr.H}r/H(jYj*HjZj(Hubaubj)r0H}r1H(jYX For example:r2HjZjGjbj:>jdjjf}r3H(jh]ji]jj]jk]jn]ujpMjqhjr]r4Hj{X For example:r5Hr6H}r7H(jYj2HjZj0HubaubjC)r8H}r9H(jYUjZjGjbj:>jdj`jf}r:H(jGX*jk]jj]jh]ji]jn]ujpMjqhjr]r;H(j/)rHjZj8Hjbj:>jdj2jf}r?H(jh]ji]jj]jk]jn]ujpNjqhjr]r@Hj)rAH}rBH(jYj>HjZjjdjjf}rCH(jh]ji]jj]jk]jn]ujpMjr]rDHj{XMMU CAM: 0x9600000E (Change the most significant 20 bits here to match the fault address. For example, it would be 96000 if the fault address is 0x96000010)rEHrFH}rGH(jYj>HjZjAHubaubaubj/)rHH}rIH(jYXxMMU RAM: 0xBA300000 (Change the most significant 20 bits here to match an unused 4-KB physical region in the memory map)rJHjZj8Hjbj:>jdj2jf}rKH(jh]ji]jj]jk]jn]ujpNjqhjr]rLHj)rMH}rNH(jYjJHjZjHHjbj:>jdjjf}rOH(jh]ji]jj]jk]jn]ujpMjr]rPHj{XxMMU RAM: 0xBA300000 (Change the most significant 20 bits here to match an unused 4-KB physical region in the memory map)rQHrRH}rSH(jYjJHjZjMHubaubaubj/)rTH}rUH(jYXMMU Lock: 0x00000400rVHjZj8Hjbj:>jdj2jf}rWH(jh]ji]jj]jk]jn]ujpNjqhjr]rXHj)rYH}rZH(jYjVHjZjTHjbj:>jdjjf}r[H(jh]ji]jj]jk]jn]ujpMjr]r\Hj{XMMU Lock: 0x00000400r]Hr^H}r_H(jYjVHjZjYHubaubaubj/)r`H}raH(jYXMMU LD: 0x00000001 jZj8Hjbj:>jdj2jf}rbH(jh]ji]jj]jk]jn]ujpNjqhjr]rcHj)rdH}reH(jYXMMU LD: 0x00000001rfHjZj`Hjbj:>jdjjf}rgH(jh]ji]jj]jk]jn]ujpMjr]rhHj{XMMU LD: 0x00000001riHrjH}rkH(jYjfHjZjdHubaubaubeubj)rlH}rmH(jYX:**Using the Crash Dump to Find the Location of the Fault**rnHjZjGjbj:>jdjjf}roH(jh]ji]jj]jk]jn]ujpMjqhjr]rpHj)rqH}rrH(jYjnHjf}rsH(jh]ji]jj]jk]jn]ujZjlHjr]rtHj{X6Using the Crash Dump to Find the Location of the FaultruHrvH}rwH(jYUjZjqHubajdjubaubj)rxH}ryH(jYXThe crash dump call stack can indicate where the crash occurred. Using that information, connect to the remote core with CCS and put a breakpoint in the code at the most recent function in the call stack before the crash. From there, step through the code until the crash happens.rzHjZjGjbj:>jdjjf}r{H(jh]ji]jj]jk]jn]ujpMjqhjr]r|Hj{XThe crash dump call stack can indicate where the crash occurred. Using that information, connect to the remote core with CCS and put a breakpoint in the code at the most recent function in the call stack before the crash. From there, step through the code until the crash happens.r}Hr~H}rH(jYjzHjZjxHubaubj)rH}rH(jYX<**Example – Accessing a Memory Region That is Not Mapped**rHjZjGjbj:>jdjjf}rH(jh]ji]jj]jk]jn]ujpMjqhjr]rHj)rH}rH(jYjHjf}rH(jh]ji]jj]jk]jn]ujZjHjr]rHj{X8Example – Accessing a Memory Region That is Not MappedrHrH}rH(jYUjZjHubajdjubaubj)rH}rH(jYXWhen using the L2 MMU, every address accessed by the remote core must be mapped. An attempt to access an un-mapped address results in an MMU fault. The following example explores the crash dump of an access to an un-mapped area.rHjZjGjbj:>jdjjf}rH(jh]ji]jj]jk]jn]ujpMjqhjr]rHj{XWhen using the L2 MMU, every address accessed by the remote core must be mapped. An attempt to access an un-mapped address results in an MMU fault. The following example explores the crash dump of an access to an un-mapped area.rHrH}rH(jYjHjZjHubaubj)rH}rH(jYXHere is an example fault dump:rHjZjGjbj:>jdjjf}rH(jh]ji]jj]jk]jn]ujpMjqhjr]rHj{XHere is an example fault dump:rHrH}rH(jYjHjZjHubaubjB)rH}rH(jYX).. image:: ../images/StackTraceDump2.PNG jZjGjbj:>jdjEjf}rH(UuriX"rtos/../images/StackTraceDump2.PNGrHjk]jj]jh]ji]jH}rHU*jHsjn]ujpMjqhjr]ubj)rH}rH(jYXFrom the crash dump, the fault address is 0x96000000. The address will not be found in the resource table, which is why the fault occurred.rHjZjGjbj:>jdjjf}rH(jh]ji]jj]jk]jn]ujpMjqhjr]rHj{XFrom the crash dump, the fault address is 0x96000000. The address will not be found in the resource table, which is why the fault occurred.rHrH}rH(jYjHjZjHubaubj)rH}rH(jYXJAvoid hard-coding of virtual addresses for peripherals and memory blocks with a one-time physical to virtual address lookup using the resource table. There is an API available for this called Resource_physToVirt() in the resource module. This alerts that the address is not mapped in the resource table when the translation fails.rHjZjGjbj:>jdjjf}rH(jh]ji]jj]jk]jn]ujpMjqhjr]rHj{XJAvoid hard-coding of virtual addresses for peripherals and memory blocks with a one-time physical to virtual address lookup using the resource table. There is an API available for this called Resource_physToVirt() in the resource module. This alerts that the address is not mapped in the resource table when the translation fails.rHrH}rH(jYjHjZjHubaubj)rH}rH(jYXFrom here, either use the crash dump to see the PC and call stack or follow the instructions under the section "Using CCS to Halt the Code When the Fault Happens." Error recovery, watchdog timers, and remoteproc autosuspend may need to be disabled to connect CCS. See `Linux and Android - Disabling Error Recovery`_, `Linux and Android – Disabling Watchdog`_, and `Linux and Android - Disabling Remoteproc Auto-Suspend`_ for more information on disabling these.jZjGjbj:>jdjjf}rH(jh]ji]jj]jk]jn]ujpMjqhjr]rH(j{X From here, either use the crash dump to see the PC and call stack or follow the instructions under the section "Using CCS to Halt the Code When the Fault Happens." Error recovery, watchdog timers, and remoteproc autosuspend may need to be disabled to connect CCS. See rHrH}rH(jYX From here, either use the crash dump to see the PC and call stack or follow the instructions under the section "Using CCS to Halt the Code When the Fault Happens." Error recovery, watchdog timers, and remoteproc autosuspend may need to be disabled to connect CCS. See jZjHubj)rH}rH(jYX/`Linux and Android - Disabling Error Recovery`_jKjZjHjdjjf}rH(UnameX,Linux and Android - Disabling Error Recoveryjk]jj]jh]ji]jn]jjEujr]rHj{X,Linux and Android - Disabling Error RecoveryrHrH}rH(jYUjZjHubaubj{X, rHrH}rH(jYX, jZjHubj)rH}rH(jYX+`Linux and Android – Disabling Watchdog`_jKjZjHjdjjf}rH(UnameX(Linux and Android – Disabling Watchdogjk]jj]jh]ji]jn]jjDujr]rHj{X(Linux and Android – Disabling WatchdogrHrH}rH(jYUjZjHubaubj{X, and rHrH}rH(jYX, and jZjHubj)rH}rH(jYX8`Linux and Android - Disabling Remoteproc Auto-Suspend`_jKjZjHjdjjf}rH(UnameX5Linux and Android - Disabling Remoteproc Auto-Suspendjk]jj]jh]ji]jn]jjDujr]rHj{X5Linux and Android - Disabling Remoteproc Auto-SuspendrHrH}rH(jYUjZjHubaubj{X) for more information on disabling these.rHrH}rH(jYX) for more information on disabling these.jZjHubeubj)rH}rH(jYXSFor this example, use the PC address which, as seen in the crash dump, is at 0xcfa6rHjZjGjbj:>jdjjf}rH(jh]ji]jj]jk]jn]ujpMjqhjr]rHj{XSFor this example, use the PC address which, as seen in the crash dump, is at 0xcfa6rHrH}rH(jYjHjZjHubaubj)rH}rH(jYX4[0] [ 107.092] Exception occurred at (PC) = 0000cfa6jZjGjbj:>jdjjf}rH(jjjk]jj]jh]ji]jn]ujpM@jqhjr]rHj{X4[0] [ 107.092] Exception occurred at (PC) = 0000cfa6rHrH}rH(jYUjZjHubaubj)rH}rH(jYXFind the corresponding function by looking this address up in the map file for the remote core image. If the PC address is invalid due to an issue such as stack corruption, then this may not yield useful results. In this case, something useful is found:rHjZjGjbj:>jdjjf}rH(jh]ji]jj]jk]jn]ujpMjqhjr]rHj{XFind the corresponding function by looking this address up in the map file for the remote core image. If the PC address is invalid due to an issue such as stack corruption, then this may not yield useful results. In this case, something useful is found:rHrH}rH(jYjHjZjHubaubjB)rH}rH(jYX0.. image:: ../images/SourceInsightCrashDump.PNG jZjGjbj:>jdjEjf}rH(UuriX)rtos/../images/SourceInsightCrashDump.PNGrHjk]jj]jh]ji]jH}rHU*jHsjn]ujpMjqhjr]ubj)rH}rH(jYXAlternatively, use CCS to see the location of the fault. If CCS was already connected to the remote core before the fault happened, the core will have halted in the abort function. From here, directly set the PC address and see the line that caused the fault:rHjZjGjbj:>jdjjf}rH(jh]ji]jj]jk]jn]ujpMjqhjr]rHj{XAlternatively, use CCS to see the location of the fault. If CCS was already connected to the remote core before the fault happened, the core will have halted in the abort function. From here, directly set the PC address and see the line that caused the fault:rHrH}rH(jYjHjZjHubaubjB)rH}rH(jYX".. image:: ../images/CCSFault.PNG jZjGjbj:>jdjEjf}rH(UuriXrtos/../images/CCSFault.PNGrHjk]jj]jh]ji]jH}rHU*jHsjn]ujpMjqhjr]ubj)rH}rI(jYXUse this technique at any time after booting the remote core to see what a PC address corresponds to. It will display the line that caused the error. This may, however, prevent proper execution because the registers and call stack won’t have proper values.rIjZjGjbj:>jdjjf}rI(jh]ji]jj]jk]jn]ujpMjqhjr]rIj{XUse this technique at any time after booting the remote core to see what a PC address corresponds to. It will display the line that caused the error. This may, however, prevent proper execution because the registers and call stack won’t have proper values.rIrI}rI(jYjIjZjHubaubj)rI}rI(jYXYou can now isolate the particular line in the fxnFault() function that was executing. That code is found in the file /packages/ti/ipc/tests/fault.c::jZjGjbj:>jdjjf}r I(jh]ji]jj]jk]jn]ujpMjqhjr]r Ij{XYou can now isolate the particular line in the fxnFault() function that was executing. That code is found in the file /packages/ti/ipc/tests/fault.c:r Ir I}r I(jYXYou can now isolate the particular line in the fxnFault() function that was executing. That code is found in the file /packages/ti/ipc/tests/fault.c:jZjIubaubj)rI}rI(jYX{case 1: System_printf("Generating read MMU Fault...\n"); a = *(volatile int *) (0x96000000); break;jZjGjbj:>jdjjf}rI(jjjk]jj]jh]ji]jn]ujpMUjqhjr]rIj{X{case 1: System_printf("Generating read MMU Fault...\n"); a = *(volatile int *) (0x96000000); break;rIrI}rI(jYUjZjIubaubj)rI}rI(jYXDFigure 8 clearly shows what caused the fault in this code, but when it is not clear, use CCS to see the fault in action. Once connected and the symbols are loaded, put a breakpoint in this function (if this function does not happen often). Once the breakpoint is hit, step through the code to find what is causing the fault.rIjZjGjbj:>jdjjf}rI(jh]ji]jj]jk]jn]ujpMjqhjr]rIj{XDFigure 8 clearly shows what caused the fault in this code, but when it is not clear, use CCS to see the fault in action. Once connected and the symbols are loaded, put a breakpoint in this function (if this function does not happen often). Once the breakpoint is hit, step through the code to find what is causing the fault.rIrI}rI(jYjIjZjIubaubj)rI}rI(jYXUpon stepping through, observe that the variable, a, is being set to the contents of 0x96000000, which is equal to the fault address. This is the fault in this example.rIjZjGjbj:>jdjjf}r I(jh]ji]jj]jk]jn]ujpMjqhjr]r!Ij{XUpon stepping through, observe that the variable, a, is being set to the contents of 0x96000000, which is equal to the fault address. This is the fault in this example.r"Ir#I}r$I(jYjIjZjIubaubj)r%I}r&I(jYXNext, decide if this is a valid value that needs mapping, or if this is an invalid value that passed due to some error in the code. If it is still not known where the value is coming from, use CCS to trace it back through the call stack to fix the code. If it turns out that the address is an address that must be accessible to the remote core, then map it through the resource table to the appropriate physical memory.r'IjZjGjbj:>jdjjf}r(I(jh]ji]jj]jk]jn]ujpMjqhjr]r)Ij{XNext, decide if this is a valid value that needs mapping, or if this is an invalid value that passed due to some error in the code. If it is still not known where the value is coming from, use CCS to trace it back through the call stack to fix the code. If it turns out that the address is an address that must be accessible to the remote core, then map it through the resource table to the appropriate physical memory.r*Ir+I}r,I(jYj'IjZj%Iubaubeubeubeubeubeubjbjcjdjejf}r-I(jh]ji]jj]jk]r.IUsetupr/Iajn]r0IhaujpKjqhjr]r1I(jt)r2I}r3I(jYXSetupr4IjZjjbjcjdjxjf}r5I(jh]ji]jj]jk]jn]ujpKjqhjr]r6Ij{XSetupr7Ir8I}r9I(jYj4IjZj2Iubaubj)r:I}r;I(jYX(Setup CCS for EVM and Processor-SDK RTOSjZjjbjcjdjjf}rIr?I}r@I(jYUjZj:Iubaubj)rAI}rBI(jYX*------------------------------------------jZjjbjcjdjjf}rCI(jjjk]jj]jh]ji]jn]ujpK"jqhjr]rDIj{X*------------------------------------------rEIrFI}rGI(jYUjZjAIubaubj)rHI}rII(jYX'.. _Processor-SDK-RTOS-Setup-CCS-label:jZjjbjcjdjjf}rJI(jk]jj]jh]ji]jn]jU"processor-sdk-rtos-setup-ccs-labelrKIujpM=jqhjr]ubjj[)rLI}rMI(jYUjZjjbjXIsource/rtos/How_to_Guides/Host/Setup/Update_ENV_for_a_Custom_Path.rst.incrNIrOI}rPIbj}rQIh1j)rRI}rSI(jYX4.. _Processor-SDK-RTOS-Install-In-Custom-Path-label:jZj[)rTI}rUI(jYUjZjjbjXLsource/rtos/How_to_Guides/Host/Setup/Setup_CCS_for_EVM_and_PSDK_RTOS.rst.incrVIrWI}rXIbjdjejf}rYI(jh]ji]jj]jk]rZIUtroubleshootingr[Iajn]r\IhaujpMUjqhjr]r]I(jt)r^I}r_I(jYXTroubleshootingr`IjZjTIjbjWIjdjxjf}raI(jh]ji]jj]jk]jn]ujpMUjqhjr]rbIj{XTroubleshootingrcIrdI}reI(jYj`IjZj^Iubaubj)rfI}rgI(jYX8If you face any problems, first check these basic items:rhIjZjTIjbjWIjdjjf}riI(jh]ji]jj]jk]jn]ujpMWjqhjr]rjIj{X8If you face any problems, first check these basic items:rkIrlI}rmI(jYjhIjZjfIubaubjC)rnI}roI(jYUjZjTIjbjWIjdj`jf}rpI(jGX-jk]jj]jh]ji]jn]ujpMYjqhjr]rqI(j/)rrI}rsI(jYX**Power cycle your target.**rtIjZjnIjbjWIjdj2jf}ruI(jh]ji]jj]jk]jn]ujpNjqhjr]rvIj)rwI}rxI(jYjtIjZjrIjbjWIjdjjf}ryI(jh]ji]jj]jk]jn]ujpMYjr]rzIj)r{I}r|I(jYjtIjf}r}I(jh]ji]jj]jk]jn]ujZjwIjr]r~Ij{XPower cycle your target.rIrI}rI(jYUjZj{Iubajdjubaubaubj/)rI}rI(jYXv**Check the USB cable.** One simple way to do this is to connect another device to the USB and ensure the cable works.jZjnIjbjWIjdj2jf}rI(jh]ji]jj]jk]jn]ujpNjqhjr]rIj)rI}rI(jYXv**Check the USB cable.** One simple way to do this is to connect another device to the USB and ensure the cable works.jZjIjbjWIjdjjf}rI(jh]ji]jj]jk]jn]ujpMZjr]rI(j)rI}rI(jYX**Check the USB cable.**jf}rI(jh]ji]jj]jk]jn]ujZjIjr]rIj{XCheck the USB cable.rIrI}rI(jYUjZjIubajdjubj{X^ One simple way to do this is to connect another device to the USB and ensure the cable works.rIrI}rI(jYX^ One simple way to do this is to connect another device to the USB and ensure the cable works.jZjIubeubaubj/)rI}rI(jYX**Check host driver.** Even with CCS turned off, your host should list the TI XDS as a USB device. If this does not work, try a different USB port.jZjnIjbjWIjdj2jf}rI(jh]ji]jj]jk]jn]ujpNjqhjr]rIj)rI}rI(jYX**Check host driver.** Even with CCS turned off, your host should list the TI XDS as a USB device. If this does not work, try a different USB port.jZjIjbjWIjdjjf}rI(jh]ji]jj]jk]jn]ujpM\jr]rI(j)rI}rI(jYX**Check host driver.**jf}rI(jh]ji]jj]jk]jn]ujZjIjr]rIj{XCheck host driver.rIrI}rI(jYUjZjIubajdjubj{X} Even with CCS turned off, your host should list the TI XDS as a USB device. If this does not work, try a different USB port.rIrI}rI(jYX} Even with CCS turned off, your host should list the TI XDS as a USB device. If this does not work, try a different USB port.jZjIubeubaubj/)rI}rI(jYX**Latest emulation package.** Ensure that you have the latest emulation files as specified in the `Getting Started Guide `__. jZjnIjbjWIjdj2jf}rI(jh]ji]jj]jk]jn]ujpNjqhjr]rIj)rI}rI(jYX**Latest emulation package.** Ensure that you have the latest emulation files as specified in the `Getting Started Guide `__.jZjIjbjWIjdjjf}rI(jh]ji]jj]jk]jn]ujpM_jr]rI(j)rI}rI(jYX**Latest emulation package.**jf}rI(jh]ji]jj]jk]jn]ujZjIjr]rIj{XLatest emulation package.rIrI}rI(jYUjZjIubajdjubj{XE Ensure that you have the latest emulation files as specified in the rIrI}rI(jYXE Ensure that you have the latest emulation files as specified in the jZjIubj)rI}rI(jYX@`Getting Started Guide `__jf}rI(UnameXGetting Started GuidejX$index_overview.html#emulator-supportjk]jj]jh]ji]jn]ujZjIjr]rIj{XGetting Started GuiderIrI}rI(jYUjZjIubajdjubj{X.rI}rI(jYX.jZjIubeubaubeubj)rI}rI(jYXFIf this does not resolve your problem, see these additional resources:rIjZjTIjbjWIjdjjf}rI(jh]ji]jj]jk]jn]ujpMbjqhjr]rIj{XFIf this does not resolve your problem, see these additional resources:rIrI}rI(jYjIjZjIubaubjC)rI}rI(jYUjZjTIjbjWIjdj`jf}rI(jGX-jk]jj]jh]ji]jn]ujpMdjqhjr]rI(j/)rI}rI(jYXT`Troubleshoot CCS `__jZjIjbjWIjdj2jf}rI(jh]ji]jj]jk]jn]ujpNjqhjr]rIj)rI}rI(jYXT`Troubleshoot CCS `__rIjZjIjbjWIjdjjf}rI(jh]ji]jj]jk]jn]ujpMdjr]rIj)rI}rI(jYjIjf}rI(UnameXTroubleshoot CCSjX=http://processors.wiki.ti.com/index.php/Troubleshooting_CCSv6jk]jj]jh]ji]jn]ujZjIjr]rIj{XTroubleshoot CCSrIrI}rI(jYUjZjIubajdjubaubaubj/)rI}rI(jYXX`Troubleshoot XDS100 `__jZjIjbjWIjdj2jf}rI(jh]ji]jj]jk]jn]ujpNjqhjr]rIj)rI}rI(jYXX`Troubleshoot XDS100 `__rIjZjIjbjWIjdjjf}rI(jh]ji]jj]jk]jn]ujpMfjr]rIj)rI}rI(jYjIjf}rI(UnameXTroubleshoot XDS100jX>http://processors.wiki.ti.com/index.php/XDS100#Troubleshootingjk]jj]jh]ji]jn]ujZjIjr]rIj{XTroubleshoot XDS100rIrI}rI(jYUjZjIubajdjubaubaubj/)rI}rI(jYXX`Troubleshoot XDS200 `__jZjIjbjWIjdj2jf}rI(jh]ji]jj]jk]jn]ujpNjqhjr]rIj)rI}rI(jYXX`Troubleshoot XDS200 `__rIjZjIjbjWIjdjjf}rI(jh]ji]jj]jk]jn]ujpMhjr]rIj)rI}rI(jYjIjf}rI(UnameXTroubleshoot XDS200jX>http://processors.wiki.ti.com/index.php/XDS200#Troubleshootingjk]jj]jh]ji]jn]ujZjIjr]rIj{XTroubleshoot XDS200rIrI}rI(jYUjZjIubajdjubaubaubj/)rI}rI(jYXd`Troubleshoot XDS560 `__ jZjIjbjWIjdj2jf}rI(jh]ji]jj]jk]jn]ujpNjqhjr]rJj)rJ}rJ(jYXc`Troubleshoot XDS560 `__rJjZjIjbjWIjdjjf}rJ(jh]ji]jj]jk]jn]ujpMjjr]rJj)rJ}rJ(jYjJjf}rJ(UnameXTroubleshoot XDS560jXIhttp://processors.wiki.ti.com/index.php/XDS560#Frequently_Asked_Questionsjk]jj]jh]ji]jn]ujZjJjr]r Jj{XTroubleshoot XDS560r Jr J}r J(jYUjZjJubajdjubaubaubeubjZ)r J}rJ(jYUjZjTIjbjWIjdj]jf}rJ(jh]ji]jj]jk]jn]ujpMmjqhjr]rJj`)rJ}rJ(jYUjcKjZj JjbjWIjdjpjf}rJ(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)rJ}rJ(jYX3Update environment when installing to a custom pathjZjTIjbjcjdjjf}rJ(jjjk]jj]jh]ji]jn]ujpK'jqhjr]rJj{X3Update environment when installing to a custom pathrJrJ}rJ(jYUjZjJubaubj)rJ}rJ(jYX5-----------------------------------------------------jZjTIjbjcjdjjf}rJ(jjjk]jj]jh]ji]jn]ujpK(jqhjr]rJj{X5-----------------------------------------------------rJr J}r!J(jYUjZjJubaubjRIeubjbjcjdjjf}r"J(jk]jj]jh]ji]jn]jU/processor-sdk-rtos-install-in-custom-path-labelr#JujpMjqhjr]ubsjdjejf}r$J(jh]ji]jj]jk]r%J(U3update-environment-when-installing-to-a-custom-pathr&Jj#Jejn]r'J(hh1eujpKjqhj}r(Jj#JjRIsjr]r)J(jt)r*J}r+J(jYX3Update environment when installing to a custom pathr,JjZjLIjbjOIjdjxjf}r-J(jh]ji]jj]jk]jn]ujpKjqhjr]r.Jj{X3Update environment when installing to a custom pathr/Jr0J}r1J(jYj,JjZj*Jubaubj)r2J}r3J(jYXQhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_Install_In_Custom_PathjZjLIjbjOIjdjjf}r4J(jjjk]jj]jh]ji]jn]ujpKjqhjr]r5Jj{XQhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_Install_In_Custom_Pathr6Jr7J}r8J(jYUjZj2Jubaubj[)r9J}r:J(jYUjKjZjLIjbjOIjdjejf}r;J(jh]rJUid24r?Jajn]ujpKjqhjr]r@J(jt)rAJ}rBJ(jYXOverviewrCJjZj9JjbjOIjdjxjf}rDJ(jh]ji]jj]jk]jn]ujpKjqhjr]rEJj{XOverviewrFJrGJ}rHJ(jYjCJjZjAJubaubj)rIJ}rJJ(jYXZThis page will provide configuration information if the SDK is installed in a custom path.rKJjZj9JjbjOIjdjjf}rLJ(jh]ji]jj]jk]jn]ujpK jqhjr]rMJj{XZThis page will provide configuration information if the SDK is installed in a custom path.rNJrOJ}rPJ(jYjKJjZjIJubaubj)rQJ}rRJ(jYX**Useful Tip**rSJjZj9JjbjOIjdjjf}rTJ(jh]ji]jj]jk]jn]ujpK jqhjr]rUJj)rVJ}rWJ(jYjSJjf}rXJ(jh]ji]jj]jk]jn]ujZjQJjr]rYJj{X Useful TiprZJr[J}r\J(jYUjZjVJubajdjubaubj)r]J}r^J(jYXTo avoid changing environment variable for each new shell, modify environment variable file directly. This file is the *setupenv* file located in the SDK root directory.jZj9JjbjOIjdjjf}r_J(jh]ji]jj]jk]jn]ujpKjqhjr]r`J(j{XwTo avoid changing environment variable for each new shell, modify environment variable file directly. This file is the raJrbJ}rcJ(jYXwTo avoid changing environment variable for each new shell, modify environment variable file directly. This file is the jZj]Jubj')rdJ}reJ(jYX *setupenv*jf}rfJ(jh]ji]jj]jk]jn]ujZj]Jjr]rgJj{XsetupenvrhJriJ}rjJ(jYUjZjdJubajdj'ubj{X( file located in the SDK root directory.rkJrlJ}rmJ(jYX( file located in the SDK root directory.jZj]Jubeubeubj[)rnJ}roJ(jYUjZjLIjbjOIjdjejf}rpJ(jh]ji]jj]jk]rqJUchanges-to-ccs-configurationrrJajn]rsJhaujpKjqhjr]rtJ(jt)ruJ}rvJ(jYXChanges to CCS ConfigurationrwJjZjnJjbjOIjdjxjf}rxJ(jh]ji]jj]jk]jn]ujpKjqhjr]ryJj{XChanges to CCS ConfigurationrzJr{J}r|J(jYjwJjZjuJubaubj)r}J}r~J(jYXInstalling the SDK in a folder other than where CCS is installed will require modifications to CCS to be able to discover the SDK. See the `Setup CCS `__ **How To** page explaining how to update CCS configuration.jZjnJjbjOIjdjjf}rJ(jh]ji]jj]jk]jn]ujpKjqhjr]rJ(j{XInstalling the SDK in a folder other than where CCS is installed will require modifications to CCS to be able to discover the SDK. See the rJrJ}rJ(jYXInstalling the SDK in a folder other than where CCS is installed will require modifications to CCS to be able to discover the SDK. See the jZj}Jubj)rJ}rJ(jYX7`Setup CCS `__jf}rJ(UnameX Setup CCSjX'/index.php/Processor_SDK_RTOS_Setup_CCSjk]jj]jh]ji]jn]ujZj}Jjr]rJj{X Setup CCSrJrJ}rJ(jYUjZjJubajdjubj{X rJ}rJ(jYX jZj}Jubj)rJ}rJ(jYX **How To**jf}rJ(jh]ji]jj]jk]jn]ujZj}Jjr]rJj{XHow TorJrJ}rJ(jYUjZjJubajdjubj{X1 page explaining how to update CCS configuration.rJrJ}rJ(jYX1 page explaining how to update CCS configuration.jZj}Jubeubeubj[)rJ}rJ(jYUjZjLIjbjOIjdjejf}rJ(jh]ji]jj]jk]rJUrebuilding-the-sdk-rtosrJajn]rJh2aujpKjqhjr]rJ(jt)rJ}rJ(jYXRebuilding the SDK RTOSrJjZjJjbjOIjdjxjf}rJ(jh]ji]jj]jk]jn]ujpKjqhjr]rJj{XRebuilding the SDK RTOSrJrJ}rJ(jYjJjZjJubaubj)rJ}rJ(jYXInstalling the SDK in a folder other than the default (``C:\TI`` for Windows, ``/home/[user]/ti`` for Linux) requires modifications to SDK RTOS scripts in order for recompilation and example/test creation to work properly.jZjJjbjOIjdjjf}rJ(jh]ji]jj]jk]jn]ujpK!jqhjr]rJ(j{X7Installing the SDK in a folder other than the default (rJrJ}rJ(jYX7Installing the SDK in a folder other than the default (jZjJubji')rJ}rJ(jYX ``C:\TI``jf}rJ(jh]ji]jj]jk]jn]ujZjJjr]rJj{XC:\TIrJrJ}rJ(jYUjZjJubajdjq'ubj{X for Windows, rJrJ}rJ(jYX for Windows, jZjJubji')rJ}rJ(jYX``/home/[user]/ti``jf}rJ(jh]ji]jj]jk]jn]ujZjJjr]rJj{X/home/[user]/tirJrJ}rJ(jYUjZjJubajdjq'ubj{X} for Linux) requires modifications to SDK RTOS scripts in order for recompilation and example/test creation to work properly.rJrJ}rJ(jYX} for Linux) requires modifications to SDK RTOS scripts in order for recompilation and example/test creation to work properly.jZjJubeubj)rJ}rJ(jYXaIn all the commands below, replace *[version]* with the appropriate version of the software/tool.jZjJjbjOIjdjjf}rJ(jh]ji]jj]jk]jn]ujpK&jqhjr]rJ(j{X#In all the commands below, replace rJrJ}rJ(jYX#In all the commands below, replace jZjJubj')rJ}rJ(jYX *[version]*jf}rJ(jh]ji]jj]jk]jn]ujZjJjr]rJj{X [version]rJrJ}rJ(jYUjZjJubajdj'ubj{X3 with the appropriate version of the software/tool.rJrJ}rJ(jYX3 with the appropriate version of the software/tool.jZjJubeubj[)rJ}rJ(jYUjZjJjbjOIjdjejf}rJ(jh]ji]jj]jk]rJU/ccs-in-custom-path-and-sdk-rtos-in-default-pathrJajn]rJhaujpK*jqhjr]rJ(jt)rJ}rJ(jYX/CCS in Custom Path and SDK RTOS in Default PathrJjZjJjbjOIjdjxjf}rJ(jh]ji]jj]jk]jn]ujpK*jqhjr]rJj{X/CCS in Custom Path and SDK RTOS in Default PathrJrJ}rJ(jYjJjZjJubaubj)rJ}rJ(jYX CCS installation and toolchain paths can be customized by setting the TOOLS_INSTALL_PATH environment variable prior to running the SDK level setupenv script. This feature is used if CCS and the toolchains are installed somewhere other than the default C:\\ti location.jZjJjbjOIjdjjf}rJ(jh]ji]jj]jk]jn]ujpK,jqhjr]rJj{X CCS installation and toolchain paths can be customized by setting the TOOLS_INSTALL_PATH environment variable prior to running the SDK level setupenv script. This feature is used if CCS and the toolchains are installed somewhere other than the default C:\ti location.rJrJ}rJ(jYX CCS installation and toolchain paths can be customized by setting the TOOLS_INSTALL_PATH environment variable prior to running the SDK level setupenv script. This feature is used if CCS and the toolchains are installed somewhere other than the default C:\\ti location.jZjJubaubj)rJ}rJ(jYXFor example, environment configuration assuming CCS is installed to [os_base]\\ti_temp and SDK RTOS has been installed to default path, [os_base]\\ti :jZjJjbjOIjdjjf}rJ(jh]ji]jj]jk]jn]ujpK1jqhjr]rJj{XFor example, environment configuration assuming CCS is installed to [os_base]\ti_temp and SDK RTOS has been installed to default path, [os_base]\ti :rJrJ}rJ(jYXFor example, environment configuration assuming CCS is installed to [os_base]\\ti_temp and SDK RTOS has been installed to default path, [os_base]\\ti :jZjJubaubjC)rJ}rJ(jYUjZjJjbjOIjdj`jf}rJ(jGX-jk]jj]jh]ji]jn]ujpK5jqhjr]rJj/)rJ}rJ(jYXWindows jZjJjbjOIjdj2jf}rJ(jh]ji]jj]jk]jn]ujpNjqhjr]rJj)rJ}rJ(jYXWindowsrJjZjJjbjOIjdjjf}rJ(jh]ji]jj]jk]jn]ujpK5jr]rJj{XWindowsrJrJ}rJ(jYjJjZjJubaubaubaubj)rJ}rK(jYX&C:\> set TOOLS_INSTALL_PATH=C:\ti_tempjZjJjbjOIjdjjf}rK(jjjk]jj]jh]ji]jn]ujpMjqhjr]rKj{X&C:\> set TOOLS_INSTALL_PATH=C:\ti_temprKrK}rK(jYUjZjJubaubj)rK}rK(jYX0C:\> cd C:\ti\processor_sdk_rtos_[soc]_[version]jZjJjbjOIjdjjf}rK(jjjk]jj]jh]ji]jn]ujpMjqhjr]r Kj{X0C:\> cd C:\ti\processor_sdk_rtos_[soc]_[version]r Kr K}r K(jYUjZjKubaubj)r K}rK(jYX6C:\ti\processor_sdk_rtos_[soc]_[version]> setupenv.batjZjJjbjOIjdjjf}rK(jjjk]jj]jh]ji]jn]ujpMjqhjr]rKj{X6C:\ti\processor_sdk_rtos_[soc]_[version]> setupenv.batrKrK}rK(jYUjZj Kubaubj)rK}rK(jYXGives the output:rKjZjJjbjOIjdjjf}rK(jh]ji]jj]jk]jn]ujpKCjqhjr]rKj{XGives the output:rKrK}rK(jYjKjZjKubaubj)rK}rK(jYXZOptional parameter not configured : CG_XML_BIN_INSTALL_PATH REQUIRED for xdc release build Example: set CG_XML_BIN_INSTALL_PATH=C:/ti/cg_xml/bin Optional parameter not configured : DOXYGEN_INSTALL_PATH REQUIRED for xdc release build Example: set DOXYGEN_INSTALL_PATH=C:/ti/Doxygen/doxygen/1.5.1-p1/bin ************************************************************************** Environment Configuration: PDK Directory  : /ti/PDK_AM~3/packages/ CGTOOL INSTALL Directory  : C:/ti_temp/ccsv6/tools/compiler/ti-cgt-c6000_[version] TOOLCHAIN A15 Directory  : C:/ti_temp/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN A8 Directory  : C:/ti_temp/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN A9 Directory  : C:/ti_temp/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN M4 Directory  : C:/ti_temp/ccsv6/tools/compiler/ti-cgt-arm_[version] FPULIB_PATH  : C:/ti_temp/ccsv6/tools/compiler/gcc-arm-none-eabi-[version]/lib/gcc/arm-none-eabi/[version]/fpu CROSS_TOOL_PRFX  : arm-none-eabi- XDC_INSTALL_PATH  : C:/ti/xdctools_[version]_core BIOS_INSTALL_PATH  : C:/ti/bios_[version] IPC_INSTALL_PATH  : C:/ti/ipc_[version] EDMA3LLD_BIOS6_INSTALLDIR : C:/ti/edma3_lld_[version] NDK_INSTALL_PATH  : C:/ti/ndk_[version] IMGLIB_INSTALL_PATH  : C:/ti/imglib_c66x_[version] UIA_INSTALL_PATH  : C:/ti/uia_[version] PROC_SDK_INSTALL_PATH  : C:/ti/processor_sdk_rtos_[soc]_[version] ************************************************************************** Changing to short name to support directory names containing spaces current directory: C:/ti/processor_sdk_rtos_[soc]_[version] PROCESSOR SDK BUILD ENVIRONMENT CONFIGURED **************************************************************************jZjJjbjOIjdjjf}rK(jjjk]jj]jh]ji]jn]ujpMjqhjr]rKj{XZOptional parameter not configured : CG_XML_BIN_INSTALL_PATH REQUIRED for xdc release build Example: set CG_XML_BIN_INSTALL_PATH=C:/ti/cg_xml/bin Optional parameter not configured : DOXYGEN_INSTALL_PATH REQUIRED for xdc release build Example: set DOXYGEN_INSTALL_PATH=C:/ti/Doxygen/doxygen/1.5.1-p1/bin ************************************************************************** Environment Configuration: PDK Directory  : /ti/PDK_AM~3/packages/ CGTOOL INSTALL Directory  : C:/ti_temp/ccsv6/tools/compiler/ti-cgt-c6000_[version] TOOLCHAIN A15 Directory  : C:/ti_temp/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN A8 Directory  : C:/ti_temp/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN A9 Directory  : C:/ti_temp/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN M4 Directory  : C:/ti_temp/ccsv6/tools/compiler/ti-cgt-arm_[version] FPULIB_PATH  : C:/ti_temp/ccsv6/tools/compiler/gcc-arm-none-eabi-[version]/lib/gcc/arm-none-eabi/[version]/fpu CROSS_TOOL_PRFX  : arm-none-eabi- XDC_INSTALL_PATH  : C:/ti/xdctools_[version]_core BIOS_INSTALL_PATH  : C:/ti/bios_[version] IPC_INSTALL_PATH  : C:/ti/ipc_[version] EDMA3LLD_BIOS6_INSTALLDIR : C:/ti/edma3_lld_[version] NDK_INSTALL_PATH  : C:/ti/ndk_[version] IMGLIB_INSTALL_PATH  : C:/ti/imglib_c66x_[version] UIA_INSTALL_PATH  : C:/ti/uia_[version] PROC_SDK_INSTALL_PATH  : C:/ti/processor_sdk_rtos_[soc]_[version] ************************************************************************** Changing to short name to support directory names containing spaces current directory: C:/ti/processor_sdk_rtos_[soc]_[version] PROCESSOR SDK BUILD ENVIRONMENT CONFIGURED **************************************************************************r Kr!K}r"K(jYUjZjKubaubjC)r#K}r$K(jYUjZjJjbjOIjdj`jf}r%K(jGX-jk]jj]jh]ji]jn]ujpKejqhjr]r&Kj/)r'K}r(K(jYXLinux jZj#KjbjOIjdj2jf}r)K(jh]ji]jj]jk]jn]ujpNjqhjr]r*Kj)r+K}r,K(jYXLinuxr-KjZj'KjbjOIjdjjf}r.K(jh]ji]jj]jk]jn]ujpKejr]r/Kj{XLinuxr0Kr1K}r2K(jYj-KjZj+Kubaubaubaubj)r3K}r4K(jYX%$ export TOOLS_INSTALL_PATH=~/ti_tempjZjJjbjOIjdjjf}r5K(jjjk]jj]jh]ji]jn]ujpM"jqhjr]r6Kj{X%$ export TOOLS_INSTALL_PATH=~/ti_tempr7Kr8K}r9K(jYUjZj3Kubaubj)r:K}r;K(jYX-$ cd ~/ti/processor_sdk_rtos_[soc]_[version]/jZjJjbjOIjdjjf}rKr?K}r@K(jYUjZj:Kubaubj)rAK}rBK(jYX;~/ti/processor_sdk_rtos_[soc]_[version]$ source setupenv.shjZjJjbjOIjdjjf}rCK(jjjk]jj]jh]ji]jn]ujpM*jqhjr]rDKj{X;~/ti/processor_sdk_rtos_[soc]_[version]$ source setupenv.shrEKrFK}rGK(jYUjZjAKubaubj)rHK}rIK(jYXGives the output:rJKjZjJjbjOIjdjjf}rKK(jh]ji]jj]jk]jn]ujpKsjqhjr]rLKj{XGives the output:rMKrNK}rOK(jYjJKjZjHKubaubj)rPK}rQK(jYX?Optional parameter not configured : CG_XML_BIN_INSTALL_PATH REQUIRED for xdc release build Example: export CG_XML_BIN_INSTALL_PATH="~/ti/cg_xml/bin" Optional parameter not configured : DOXYGEN_INSTALL_PATH REQUIRED for xdc release build Example: export DOXYGEN_INSTALL_PATH="~/ti/Doxygen/doxygen/1.5.1-p1/bin" ************************************************************************** Environment Configuration: PDK Directory  : /home/[user]/ti/pdk_[soc]_[version]/packages CGTOOL INSTALL Directory  : /home/[user]/ti_temp/ccsv6/tools/compiler/ti-cgt-c6000_[version] TOOLCHAIN A15 Directory  : /home/[user]/ti_temp/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN A8 Directory  : /home/[user]/ti_temp/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN A9 Directory  : /home/[user]/ti_temp/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN M4 Directory  : /home/[user]/ti_temp/ccsv6/tools/compiler/ti-cgt-arm_[version] FPULIB_PATH  : /home/[user]/ti_temp/ccsv6/tools/compiler/gcc-arm-none-eabi-[version]/lib/gcc/arm-none-eabi/[version]/fpu CROSS_TOOL_PRFX  : arm-none-eabi- XDC_INSTALL_PATH  : /home/[user]/ti/xdctools_[version]_core BIOS_INSTALL_PATH  : /home/[user]/ti/bios_[version] IPC_INSTALL_PATH  : /home/[user]/ti/ipc_[version] EDMA3LLD_BIOS6_INSTALLDIR : /home/[user]/ti/edma3_lld_[version] NDK_INSTALL_PATH  : /home/[user]/ti/ndk_[version] IMGLIB_INSTALL_PATH  : /home/[user]/ti/imglib_c66x_[version] UIA_INSTALL_PATH  : /home/[user]/ti/uia_[version] PROC_SDK_INSTALL_PATH  : /home/[user]/ti/processor_sdk_rtos_[soc]_[version] PROCESSOR SDK BUILD ENVIRONMENT CONFIGURED *******************************************************************************jZjJjbjOIjdjjf}rRK(jjjk]jj]jh]ji]jn]ujpM0jqhjr]rSKj{X?Optional parameter not configured : CG_XML_BIN_INSTALL_PATH REQUIRED for xdc release build Example: export CG_XML_BIN_INSTALL_PATH="~/ti/cg_xml/bin" Optional parameter not configured : DOXYGEN_INSTALL_PATH REQUIRED for xdc release build Example: export DOXYGEN_INSTALL_PATH="~/ti/Doxygen/doxygen/1.5.1-p1/bin" ************************************************************************** Environment Configuration: PDK Directory  : /home/[user]/ti/pdk_[soc]_[version]/packages CGTOOL INSTALL Directory  : /home/[user]/ti_temp/ccsv6/tools/compiler/ti-cgt-c6000_[version] TOOLCHAIN A15 Directory  : /home/[user]/ti_temp/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN A8 Directory  : /home/[user]/ti_temp/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN A9 Directory  : /home/[user]/ti_temp/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN M4 Directory  : /home/[user]/ti_temp/ccsv6/tools/compiler/ti-cgt-arm_[version] FPULIB_PATH  : /home/[user]/ti_temp/ccsv6/tools/compiler/gcc-arm-none-eabi-[version]/lib/gcc/arm-none-eabi/[version]/fpu CROSS_TOOL_PRFX  : arm-none-eabi- XDC_INSTALL_PATH  : /home/[user]/ti/xdctools_[version]_core BIOS_INSTALL_PATH  : /home/[user]/ti/bios_[version] IPC_INSTALL_PATH  : /home/[user]/ti/ipc_[version] EDMA3LLD_BIOS6_INSTALLDIR : /home/[user]/ti/edma3_lld_[version] NDK_INSTALL_PATH  : /home/[user]/ti/ndk_[version] IMGLIB_INSTALL_PATH  : /home/[user]/ti/imglib_c66x_[version] UIA_INSTALL_PATH  : /home/[user]/ti/uia_[version] PROC_SDK_INSTALL_PATH  : /home/[user]/ti/processor_sdk_rtos_[soc]_[version] PROCESSOR SDK BUILD ENVIRONMENT CONFIGURED *******************************************************************************rTKrUK}rVK(jYUjZjPKubaubj)rWK}rXK(jYXThe `RTOS SDK top level Makefile `__ can now be used to rebuild SDK RTOS components with CCS and toolchains installed in a custom installation path.jZjJjbjOIjdjjf}rYK(jh]ji]jj]jk]jn]ujpKjqhjr]rZK(j{XThe r[Kr\K}r]K(jYXThe jZjWKubj)r^K}r_K(jYXH`RTOS SDK top level Makefile `__jf}r`K(UnameXRTOS SDK top level MakefilejX&index_overview.html#top-level-makefilejk]jj]jh]ji]jn]ujZjWKjr]raKj{XRTOS SDK top level MakefilerbKrcK}rdK(jYUjZj^Kubajdjubj{Xp can now be used to rebuild SDK RTOS components with CCS and toolchains installed in a custom installation path.reKrfK}rgK(jYXp can now be used to rebuild SDK RTOS components with CCS and toolchains installed in a custom installation path.jZjWKubeubeubj[)rhK}riK(jYUjZjJjbjOIjdjejf}rjK(jh]ji]jj]jk]rkKU/ccs-in-default-path-and-sdk-rtos-in-custom-pathrlKajn]rmKh:aujpKjqhjr]rnK(jt)roK}rpK(jYX/CCS in Default Path and SDK RTOS in Custom PathrqKjZjhKjbjOIjdjxjf}rrK(jh]ji]jj]jk]jn]ujpKjqhjr]rsKj{X/CCS in Default Path and SDK RTOS in Custom PathrtKruK}rvK(jYjqKjZjoKubaubj)rwK}rxK(jYXSDK RTOS component installation paths can be customized by setting the SDK_INSTALL_PATH variable prior to running the SDK level setupenv script. This feature is used if the SDK is installed somewhere other than the default ``C:\ti`` location.jZjhKjbjOIjdjjf}ryK(jh]ji]jj]jk]jn]ujpKjqhjr]rzK(j{XSDK RTOS component installation paths can be customized by setting the SDK_INSTALL_PATH variable prior to running the SDK level setupenv script. This feature is used if the SDK is installed somewhere other than the default r{Kr|K}r}K(jYXSDK RTOS component installation paths can be customized by setting the SDK_INSTALL_PATH variable prior to running the SDK level setupenv script. This feature is used if the SDK is installed somewhere other than the default jZjwKubji')r~K}rK(jYX ``C:\ti``jf}rK(jh]ji]jj]jk]jn]ujZjwKjr]rKj{XC:\tirKrK}rK(jYUjZj~Kubajdjq'ubj{X location.rKrK}rK(jYX location.jZjwKubeubj)rK}rK(jYXFor example, environment configuration assuming CCS is installed to the default path, ``[os_base]\ti`` and SDK RTOS has been installed to ``[os_base]\ti_temp``:jZjhKjbjOIjdjjf}rK(jh]ji]jj]jk]jn]ujpKjqhjr]rK(j{XVFor example, environment configuration assuming CCS is installed to the default path, rKrK}rK(jYXVFor example, environment configuration assuming CCS is installed to the default path, jZjKubji')rK}rK(jYX``[os_base]\ti``jf}rK(jh]ji]jj]jk]jn]ujZjKjr]rKj{X [os_base]\tirKrK}rK(jYUjZjKubajdjq'ubj{X$ and SDK RTOS has been installed to rKrK}rK(jYX$ and SDK RTOS has been installed to jZjKubji')rK}rK(jYX``[os_base]\ti_temp``jf}rK(jh]ji]jj]jk]jn]ujZjKjr]rKj{X[os_base]\ti_temprKrK}rK(jYUjZjKubajdjq'ubj{X:rK}rK(jYX:jZjKubeubjC)rK}rK(jYUjZjhKjbjOIjdj`jf}rK(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]rKj/)rK}rK(jYXWindows jZjKjbjOIjdj2jf}rK(jh]ji]jj]jk]jn]ujpNjqhjr]rKj)rK}rK(jYXWindowsrKjZjKjbjOIjdjjf}rK(jh]ji]jj]jk]jn]ujpKjr]rKj{XWindowsrKrK}rK(jYjKjZjKubaubaubaubj)rK}rK(jYX$C:\> set SDK_INSTALL_PATH=C:/ti_tempjZjhKjbjOIjdjjf}rK(jjjk]jj]jh]ji]jn]ujpMajqhjr]rKj{X$C:\> set SDK_INSTALL_PATH=C:/ti_temprKrK}rK(jYUjZjKubaubj)rK}rK(jYX5C:\> cd C:\ti_temp\processor_sdk_rtos_[soc]_[version]jZjhKjbjOIjdjjf}rK(jjjk]jj]jh]ji]jn]ujpMejqhjr]rKj{X5C:\> cd C:\ti_temp\processor_sdk_rtos_[soc]_[version]rKrK}rK(jYUjZjKubaubj)rK}rK(jYX;C:\ti_temp\processor_sdk_rtos_[soc]_[version]> setupenv.batjZjhKjbjOIjdjjf}rK(jjjk]jj]jh]ji]jn]ujpMijqhjr]rKj{X;C:\ti_temp\processor_sdk_rtos_[soc]_[version]> setupenv.batrKrK}rK(jYUjZjKubaubj)rK}rK(jYXGives the output:rKjZjhKjbjOIjdjjf}rK(jh]ji]jj]jk]jn]ujpKjqhjr]rKj{XGives the output:rKrK}rK(jYjKjZjKubaubj)rK}rK(jYXnOptional parameter not configured : CG_XML_BIN_INSTALL_PATH REQUIRED for xdc release build Example: set CG_XML_BIN_INSTALL_PATH=C:/ti/cg_xml/bin Optional parameter not configured : DOXYGEN_INSTALL_PATH REQUIRED for xdc release build Example: set DOXYGEN_INSTALL_PATH=C:/ti/Doxygen/doxygen/1.5.1-p1/bin ************************************************************************** Environment Configuration: PDK Directory  : /ti_temp/PDK_AM~3/packages/ CGTOOL INSTALL Directory  : C:/ti/ccsv6/tools/compiler/ti-cgt-c6000_[version] TOOLCHAIN A15 Directory  : C:/ti/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN A8 Directory  : C:/ti/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN A9 Directory  : C:/ti/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN M4 Directory  : C:/ti/ccsv6/tools/compiler/ti-cgt-arm_[version] FPULIB_PATH  : C:/ti/ccsv6/tools/compiler/gcc-arm-none-eabi-[version]/lib/gcc/arm-none-eabi/[version]/fpu CROSS_TOOL_PRFX  : arm-none-eabi- XDC_INSTALL_PATH  : C:/ti_temp/xdctools_[version]_core BIOS_INSTALL_PATH  : C:/ti_temp/bios_[version] IPC_INSTALL_PATH  : C:/ti_temp/ipc_[version] EDMA3LLD_BIOS6_INSTALLDIR : C:/ti_temp/edma3_lld_[version] NDK_INSTALL_PATH  : C:/ti_temp/ndk_[version] IMGLIB_INSTALL_PATH  : C:/ti_temp/imglib_c66x_[version] UIA_INSTALL_PATH  : C:/ti_temp/uia_[version] PROC_SDK_INSTALL_PATH  : C:/ti_temp/processor_sdk_rtos_[soc]_[version] ************************************************************************** Changing to short name to support directory names containing spaces current directory: C:/ti_temp/processor_sdk_rtos_[soc]_[version] PROCESSOR SDK BUILD ENVIRONMENT CONFIGURED **************************************************************************jZjhKjbjOIjdjjf}rK(jjjk]jj]jh]ji]jn]ujpMojqhjr]rKj{XnOptional parameter not configured : CG_XML_BIN_INSTALL_PATH REQUIRED for xdc release build Example: set CG_XML_BIN_INSTALL_PATH=C:/ti/cg_xml/bin Optional parameter not configured : DOXYGEN_INSTALL_PATH REQUIRED for xdc release build Example: set DOXYGEN_INSTALL_PATH=C:/ti/Doxygen/doxygen/1.5.1-p1/bin ************************************************************************** Environment Configuration: PDK Directory  : /ti_temp/PDK_AM~3/packages/ CGTOOL INSTALL Directory  : C:/ti/ccsv6/tools/compiler/ti-cgt-c6000_[version] TOOLCHAIN A15 Directory  : C:/ti/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN A8 Directory  : C:/ti/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN A9 Directory  : C:/ti/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN M4 Directory  : C:/ti/ccsv6/tools/compiler/ti-cgt-arm_[version] FPULIB_PATH  : C:/ti/ccsv6/tools/compiler/gcc-arm-none-eabi-[version]/lib/gcc/arm-none-eabi/[version]/fpu CROSS_TOOL_PRFX  : arm-none-eabi- XDC_INSTALL_PATH  : C:/ti_temp/xdctools_[version]_core BIOS_INSTALL_PATH  : C:/ti_temp/bios_[version] IPC_INSTALL_PATH  : C:/ti_temp/ipc_[version] EDMA3LLD_BIOS6_INSTALLDIR : C:/ti_temp/edma3_lld_[version] NDK_INSTALL_PATH  : C:/ti_temp/ndk_[version] IMGLIB_INSTALL_PATH  : C:/ti_temp/imglib_c66x_[version] UIA_INSTALL_PATH  : C:/ti_temp/uia_[version] PROC_SDK_INSTALL_PATH  : C:/ti_temp/processor_sdk_rtos_[soc]_[version] ************************************************************************** Changing to short name to support directory names containing spaces current directory: C:/ti_temp/processor_sdk_rtos_[soc]_[version] PROCESSOR SDK BUILD ENVIRONMENT CONFIGURED **************************************************************************rKrK}rK(jYUjZjKubaubjC)rK}rK(jYUjZjhKjbjOIjdj`jf}rK(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]rKj/)rK}rK(jYXLinux jZjKjbjOIjdj2jf}rK(jh]ji]jj]jk]jn]ujpNjqhjr]rKj)rK}rK(jYXLinuxrKjZjKjbjOIjdjjf}rK(jh]ji]jj]jk]jn]ujpKjr]rKj{XLinuxrKrK}rK(jYjKjZjKubaubaubaubj)rK}rK(jYX#$ export SDK_INSTALL_PATH=~/ti_tempjZjhKjbjOIjdjjf}rK(jjjk]jj]jh]ji]jn]ujpMjqhjr]rKj{X#$ export SDK_INSTALL_PATH=~/ti_temprKrK}rK(jYUjZjKubaubj)rK}rK(jYX2$ cd ~/ti_temp/processor_sdk_rtos_[soc]_[version]/jZjhKjbjOIjdjjf}rK(jjjk]jj]jh]ji]jn]ujpMjqhjr]rKj{X2$ cd ~/ti_temp/processor_sdk_rtos_[soc]_[version]/rKrK}rK(jYUjZjKubaubj)rK}rK(jYX@~/ti_temp/processor_sdk_rtos_[soc]_[version]$ source setupenv.shjZjhKjbjOIjdjjf}rK(jjjk]jj]jh]ji]jn]ujpMjqhjr]rKj{X@~/ti_temp/processor_sdk_rtos_[soc]_[version]$ source setupenv.shrKrK}rK(jYUjZjKubaubj)rK}rK(jYXGives the output:rKjZjhKjbjOIjdjjf}rK(jh]ji]jj]jk]jn]ujpKjqhjr]rKj{XGives the output:rLrL}rL(jYjKjZjKubaubj)rL}rL(jYXNOptional parameter not configured : CG_XML_BIN_INSTALL_PATH REQUIRED for xdc release build Example: export CG_XML_BIN_INSTALL_PATH="~/ti/cg_xml/bin" Optional parameter not configured : DOXYGEN_INSTALL_PATH REQUIRED for xdc release build Example: export DOXYGEN_INSTALL_PATH="~/ti/Doxygen/doxygen/1.5.1-p1/bin" ************************************************************************** Environment Configuration: PDK Directory  : /home/[user]/ti_temp/pdk_[soc]_[version]/packages CGTOOL INSTALL Directory  : /home/[user]/ti/ccsv6/tools/compiler/ti-cgt-c6000_[version] TOOLCHAIN A15 Directory  : /home/[user]/ti/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN A8 Directory  : /home/[user]/ti/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN A9 Directory  : /home/[user]/ti/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN M4 Directory  : /home/[user]/ti/ccsv6/tools/compiler/ti-cgt-arm_[version] FPULIB_PATH  : /home/[user]/ti/ccsv6/tools/compiler/gcc-arm-none-eabi-[version]/lib/gcc/arm-none-eabi/[version]/fpu CROSS_TOOL_PRFX  : arm-none-eabi- XDC_INSTALL_PATH  : /home/[user]/ti_temp/xdctools_[version]_core BIOS_INSTALL_PATH  : /home/[user]/ti_temp/bios_[version] IPC_INSTALL_PATH  : /home/[user]/ti_temp/ipc_[version] EDMA3LLD_BIOS6_INSTALLDIR : /home/[user]/ti_temp/edma3_lld_[version] NDK_INSTALL_PATH  : /home/[user]/ti_temp/ndk_[version] IMGLIB_INSTALL_PATH  : /home/[user]/ti_temp/imglib_c66x_[version] UIA_INSTALL_PATH  : /home/[user]/ti_temp/uia_[version] PROC_SDK_INSTALL_PATH  : /home/[user]/ti_temp/processor_sdk_rtos_[soc]_[version] PROCESSOR SDK BUILD ENVIRONMENT CONFIGURED *******************************************************************************jZjhKjbjOIjdjjf}rL(jjjk]jj]jh]ji]jn]ujpMjqhjr]rLj{XNOptional parameter not configured : CG_XML_BIN_INSTALL_PATH REQUIRED for xdc release build Example: export CG_XML_BIN_INSTALL_PATH="~/ti/cg_xml/bin" Optional parameter not configured : DOXYGEN_INSTALL_PATH REQUIRED for xdc release build Example: export DOXYGEN_INSTALL_PATH="~/ti/Doxygen/doxygen/1.5.1-p1/bin" ************************************************************************** Environment Configuration: PDK Directory  : /home/[user]/ti_temp/pdk_[soc]_[version]/packages CGTOOL INSTALL Directory  : /home/[user]/ti/ccsv6/tools/compiler/ti-cgt-c6000_[version] TOOLCHAIN A15 Directory  : /home/[user]/ti/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN A8 Directory  : /home/[user]/ti/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN A9 Directory  : /home/[user]/ti/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN M4 Directory  : /home/[user]/ti/ccsv6/tools/compiler/ti-cgt-arm_[version] FPULIB_PATH  : /home/[user]/ti/ccsv6/tools/compiler/gcc-arm-none-eabi-[version]/lib/gcc/arm-none-eabi/[version]/fpu CROSS_TOOL_PRFX  : arm-none-eabi- XDC_INSTALL_PATH  : /home/[user]/ti_temp/xdctools_[version]_core BIOS_INSTALL_PATH  : /home/[user]/ti_temp/bios_[version] IPC_INSTALL_PATH  : /home/[user]/ti_temp/ipc_[version] EDMA3LLD_BIOS6_INSTALLDIR : /home/[user]/ti_temp/edma3_lld_[version] NDK_INSTALL_PATH  : /home/[user]/ti_temp/ndk_[version] IMGLIB_INSTALL_PATH  : /home/[user]/ti_temp/imglib_c66x_[version] UIA_INSTALL_PATH  : /home/[user]/ti_temp/uia_[version] PROC_SDK_INSTALL_PATH  : /home/[user]/ti_temp/processor_sdk_rtos_[soc]_[version] PROCESSOR SDK BUILD ENVIRONMENT CONFIGURED *******************************************************************************rLrL}r L(jYUjZjLubaubj)r L}r L(jYXThe `RTOS SDK top level Makefile `__ can now be used to rebuild SDK RTOS components installed in the custom installation path.jZjhKjbjOIjdjjf}r L(jh]ji]jj]jk]jn]ujpMjqhjr]r L(j{XThe rLrL}rL(jYXThe jZj Lubj)rL}rL(jYXH`RTOS SDK top level Makefile `__jf}rL(UnameXRTOS SDK top level MakefilejX&index_overview.html#top-level-makefilejk]jj]jh]ji]jn]ujZj Ljr]rLj{XRTOS SDK top level MakefilerLrL}rL(jYUjZjLubajdjubj{XZ can now be used to rebuild SDK RTOS components installed in the custom installation path.rLrL}rL(jYXZ can now be used to rebuild SDK RTOS components installed in the custom installation path.jZj Lubeubj)rL}rL(jYX The following known issue impacts this step: **PRSDK-1263**: PDK AM437x: Make fails on Windows if CCS is installed in custom path. **Workaround:** Edit the UTILS_INSTALL_DIR variable in /packages/ti/starterware/Rules.make to point to the CCS installation on your Windows PC.jZjhKjbjOIjdjjf}rL(jh]ji]jj]jk]jn]ujpNjqhjr]rLj)rL}r L(jYX The following known issue impacts this step: **PRSDK-1263**: PDK AM437x: Make fails on Windows if CCS is installed in custom path. **Workaround:** Edit the UTILS_INSTALL_DIR variable in /packages/ti/starterware/Rules.make to point to the CCS installation on your Windows PC.jZjLjbjOIjdjjf}r!L(jh]ji]jj]jk]jn]ujpMjr]r"L(j{X-The following known issue impacts this step: r#Lr$L}r%L(jYX-The following known issue impacts this step: jZjLubj)r&L}r'L(jYX**PRSDK-1263**jf}r(L(jh]ji]jj]jk]jn]ujZjLjr]r)Lj{X PRSDK-1263r*Lr+L}r,L(jYUjZj&Lubajdjubj{XH: PDK AM437x: Make fails on Windows if CCS is installed in custom path. r-Lr.L}r/L(jYXH: PDK AM437x: Make fails on Windows if CCS is installed in custom path. jZjLubj)r0L}r1L(jYX**Workaround:**jf}r2L(jh]ji]jj]jk]jn]ujZjLjr]r3Lj{X Workaround:r4Lr5L}r6L(jYUjZj0Lubajdjubj{X Edit the UTILS_INSTALL_DIR variable in /packages/ti/starterware/Rules.make to point to the CCS installation on your Windows PC.r7Lr8L}r9L(jYX Edit the UTILS_INSTALL_DIR variable in /packages/ti/starterware/Rules.make to point to the CCS installation on your Windows PC.jZjLubeubaubeubj[)r:L}r;L(jYUjZjJjbjOIjdjejf}rLajn]r?LheaujpMjqhjr]r@L(jt)rAL}rBL(jYXCCS and SDK RTOS in Custom PathrCLjZj:LjbjOIjdjxjf}rDL(jh]ji]jj]jk]jn]ujpMjqhjr]rELj{XCCS and SDK RTOS in Custom PathrFLrGL}rHL(jYjCLjZjALubaubj)rIL}rJL(jYX=When CCS and the SDK RTOS are both installed to custom paths the SDK can be rebuilt by setting the SDK_INSTALL_PATH and TOOLS_INSTALL_PATH variables prior to running the SDK RTOS top level environment setup script. The Windows and Linux environment setup scripts can be found in the following locations, respectively:rKLjZj:LjbjOIjdjjf}rLL(jh]ji]jj]jk]jn]ujpMjqhjr]rMLj{X=When CCS and the SDK RTOS are both installed to custom paths the SDK can be rebuilt by setting the SDK_INSTALL_PATH and TOOLS_INSTALL_PATH variables prior to running the SDK RTOS top level environment setup script. The Windows and Linux environment setup scripts can be found in the following locations, respectively:rNLrOL}rPL(jYjKLjZjILubaubjC)rQL}rRL(jYUjZj:LjbjOIjdj`jf}rSL(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]rTL(j/)rUL}rVL(jYXUWindows - C:\\custom\\install\\path\\processor_sdk_rtos_[soc]_[version]\\setupenv.batjZjQLjbjOIjdj2jf}rWL(jh]ji]jj]jk]jn]ujpNjqhjr]rXLj)rYL}rZL(jYXUWindows - C:\\custom\\install\\path\\processor_sdk_rtos_[soc]_[version]\\setupenv.batjZjULjbjOIjdjjf}r[L(jh]ji]jj]jk]jn]ujpMjr]r\Lj{XPWindows - C:\custom\install\path\processor_sdk_rtos_[soc]_[version]\setupenv.batr]Lr^L}r_L(jYXUWindows - C:\\custom\\install\\path\\processor_sdk_rtos_[soc]_[version]\\setupenv.batjZjYLubaubaubj/)r`L}raL(jYXXLinux - /home/[user]/custom/install/path/processor_sdk_rtos_[soc]_[version]/setupenv.sh jZjQLjbjOIjdj2jf}rbL(jh]ji]jj]jk]jn]ujpNjqhjr]rcLj)rdL}reL(jYXWLinux - /home/[user]/custom/install/path/processor_sdk_rtos_[soc]_[version]/setupenv.shrfLjZj`LjbjOIjdjjf}rgL(jh]ji]jj]jk]jn]ujpMjr]rhLj{XWLinux - /home/[user]/custom/install/path/processor_sdk_rtos_[soc]_[version]/setupenv.shriLrjL}rkL(jYjfLjZjdLubaubaubeubj)rlL}rmL(jYXThe SDK_INSTALL_PATH and TOOLS_INSTALL_PATH environment variables must be set to the custom install path **prior to running** the environment setup script.jZj:LjbjOIjdjjf}rnL(jh]ji]jj]jk]jn]ujpMjqhjr]roL(j{XiThe SDK_INSTALL_PATH and TOOLS_INSTALL_PATH environment variables must be set to the custom install path rpLrqL}rrL(jYXiThe SDK_INSTALL_PATH and TOOLS_INSTALL_PATH environment variables must be set to the custom install path jZjlLubj)rsL}rtL(jYX**prior to running**jf}ruL(jh]ji]jj]jk]jn]ujZjlLjr]rvLj{Xprior to runningrwLrxL}ryL(jYUjZjsLubajdjubj{X the environment setup script.rzLr{L}r|L(jYX the environment setup script.jZjlLubeubj)r}L}r~L(jYXvFor example, environment configuration assuming CCS and the SDK have been installed to [os_base]\\new_sdk_release\\ :jZj:LjbjOIjdjjf}rL(jh]ji]jj]jk]jn]ujpM jqhjr]rLj{XtFor example, environment configuration assuming CCS and the SDK have been installed to [os_base]\new_sdk_release\ :rLrL}rL(jYXvFor example, environment configuration assuming CCS and the SDK have been installed to [os_base]\\new_sdk_release\\ :jZj}LubaubjC)rL}rL(jYUjZj:LjbjOIjdj`jf}rL(jGX-jk]jj]jh]ji]jn]ujpM#jqhjr]rLj/)rL}rL(jYXWindows jZjLjbjOIjdj2jf}rL(jh]ji]jj]jk]jn]ujpNjqhjr]rLj)rL}rL(jYXWindowsrLjZjLjbjOIjdjjf}rL(jh]ji]jj]jk]jn]ujpM#jr]rLj{XWindowsrLrL}rL(jYjLjZjLubaubaubaubj)rL}rL(jYX[C:\> set SDK_INSTALL_PATH=C:\new_sdk_release C:\> set TOOLS_INSTALL_PATH=C:\new_sdk_releasejZj:LjbjOIjdjjf}rL(jjjk]jj]jh]ji]jn]ujpMjqhjr]rLj{X[C:\> set SDK_INSTALL_PATH=C:\new_sdk_release C:\> set TOOLS_INSTALL_PATH=C:\new_sdk_releaserLrL}rL(jYUjZjLubaubj)rL}rL(jYX=C:\> cd C:\new_sdk_release\processor_sdk_rtos_[soc]_[version]jZj:LjbjOIjdjjf}rL(jjjk]jj]jh]ji]jn]ujpMjqhjr]rLj{X=C:\> cd C:\new_sdk_release\processor_sdk_rtos_[soc]_[version]rLrL}rL(jYUjZjLubaubj)rL}rL(jYXCC:\new_sdk_release\processor_sdk_rtos_[soc]_[version]> setupenv.batjZj:LjbjOIjdjjf}rL(jjjk]jj]jh]ji]jn]ujpMjqhjr]rLj{XCC:\new_sdk_release\processor_sdk_rtos_[soc]_[version]> setupenv.batrLrL}rL(jYUjZjLubaubj)rL}rL(jYXGives the output:rLjZj:LjbjOIjdjjf}rL(jh]ji]jj]jk]jn]ujpM2jqhjr]rLj{XGives the output:rLrL}rL(jYjLjZjLubaubj)rL}rL(jYXOptional parameter not configured : CG_XML_BIN_INSTALL_PATH REQUIRED for xdc release build Example: set CG_XML_BIN_INSTALL_PATH=C:/ti/cg_xml/bin Optional parameter not configured : DOXYGEN_INSTALL_PATH REQUIRED for xdc release build Example: set DOXYGEN_INSTALL_PATH=C:/ti/Doxygen/doxygen/1.5.1-p1/bin ************************************************************************** Environment Configuration: PDK Directory  : /NEW_SD~1/PDK_AM~1/packages/ CGTOOL INSTALL Directory  : C:/new_sdk_release/ccsv6/tools/compiler/ti-cgt-c6000_[version] TOOLCHAIN A15 Directory  : C:/new_sdk_release/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN A8 Directory  : C:/new_sdk_release/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN A9 Directory  : C:/new_sdk_release/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN M4 Directory  : C:/new_sdk_release/ccsv6/tools/compiler/ti-cgt-arm_[version] FPULIB_PATH  : C:/new_sdk_release/ccsv6/tools/compiler/gcc-arm-none-eabi-[version]/lib/gcc/arm-none-eabi/[version]/fpu CROSS_TOOL_PRFX  : arm-none-eabi- XDC_INSTALL_PATH  : C:/new_sdk_release/xdctools_[version]_core BIOS_INSTALL_PATH  : C:/new_sdk_release/bios_[version] IPC_INSTALL_PATH  : C:/new_sdk_release/ipc_[version] EDMA3LLD_BIOS6_INSTALLDIR : C:/new_sdk_release/edma3_lld_[version] NDK_INSTALL_PATH  : C:/new_sdk_release/ndk_[version] IMGLIB_INSTALL_PATH  : C:/new_sdk_release/imglib_c66x_[version] UIA_INSTALL_PATH  : C:/new_sdk_release/uia_[version] PROC_SDK_INSTALL_PATH  : C:/new_sdk_release/processor_sdk_rtos_[soc]_[version] ************************************************************************** Changing to short name to support directory names containing spaces current directory: C:/new_sdk_release/processor_sdk_rtos_[soc]_[version] PROCESSOR SDK BUILD ENVIRONMENT CONFIGURED **************************************************************************jZj:LjbjOIjdjjf}rL(jjjk]jj]jh]ji]jn]ujpMjqhjr]rLj{XOptional parameter not configured : CG_XML_BIN_INSTALL_PATH REQUIRED for xdc release build Example: set CG_XML_BIN_INSTALL_PATH=C:/ti/cg_xml/bin Optional parameter not configured : DOXYGEN_INSTALL_PATH REQUIRED for xdc release build Example: set DOXYGEN_INSTALL_PATH=C:/ti/Doxygen/doxygen/1.5.1-p1/bin ************************************************************************** Environment Configuration: PDK Directory  : /NEW_SD~1/PDK_AM~1/packages/ CGTOOL INSTALL Directory  : C:/new_sdk_release/ccsv6/tools/compiler/ti-cgt-c6000_[version] TOOLCHAIN A15 Directory  : C:/new_sdk_release/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN A8 Directory  : C:/new_sdk_release/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN A9 Directory  : C:/new_sdk_release/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN M4 Directory  : C:/new_sdk_release/ccsv6/tools/compiler/ti-cgt-arm_[version] FPULIB_PATH  : C:/new_sdk_release/ccsv6/tools/compiler/gcc-arm-none-eabi-[version]/lib/gcc/arm-none-eabi/[version]/fpu CROSS_TOOL_PRFX  : arm-none-eabi- XDC_INSTALL_PATH  : C:/new_sdk_release/xdctools_[version]_core BIOS_INSTALL_PATH  : C:/new_sdk_release/bios_[version] IPC_INSTALL_PATH  : C:/new_sdk_release/ipc_[version] EDMA3LLD_BIOS6_INSTALLDIR : C:/new_sdk_release/edma3_lld_[version] NDK_INSTALL_PATH  : C:/new_sdk_release/ndk_[version] IMGLIB_INSTALL_PATH  : C:/new_sdk_release/imglib_c66x_[version] UIA_INSTALL_PATH  : C:/new_sdk_release/uia_[version] PROC_SDK_INSTALL_PATH  : C:/new_sdk_release/processor_sdk_rtos_[soc]_[version] ************************************************************************** Changing to short name to support directory names containing spaces current directory: C:/new_sdk_release/processor_sdk_rtos_[soc]_[version] PROCESSOR SDK BUILD ENVIRONMENT CONFIGURED **************************************************************************rLrL}rL(jYUjZjLubaubjC)rL}rL(jYUjZj:LjbjOIjdj`jf}rL(jGX-jk]jj]jh]ji]jn]ujpMTjqhjr]rLj/)rL}rL(jYXLinux jZjLjbjOIjdj2jf}rL(jh]ji]jj]jk]jn]ujpNjqhjr]rLj)rL}rL(jYXLinuxrLjZjLjbjOIjdjjf}rL(jh]ji]jj]jk]jn]ujpMTjr]rLj{XLinuxrLrL}rL(jYjLjZjLubaubaubaubj)rL}rL(jYXY$ export SDK_INSTALL_PATH=~/new_sdk_release $ export TOOLS_INSTALL_PATH=~/new_sdk_releasejZj:LjbjOIjdjjf}rL(jjjk]jj]jh]ji]jn]ujpMjqhjr]rLj{XY$ export SDK_INSTALL_PATH=~/new_sdk_release $ export TOOLS_INSTALL_PATH=~/new_sdk_releaserLrL}rL(jYUjZjLubaubj)rL}rL(jYX:$ cd ~/new_sdk_release/processor_sdk_rtos_[soc]_[version]/jZj:LjbjOIjdjjf}rL(jjjk]jj]jh]ji]jn]ujpMjqhjr]rLj{X:$ cd ~/new_sdk_release/processor_sdk_rtos_[soc]_[version]/rLrL}rL(jYUjZjLubaubj)rL}rL(jYXH~/new_sdk_release/processor_sdk_rtos_[soc]_[version]$ source setupenv.shjZj:LjbjOIjdjjf}rL(jjjk]jj]jh]ji]jn]ujpMjqhjr]rLj{XH~/new_sdk_release/processor_sdk_rtos_[soc]_[version]$ source setupenv.shrLrL}rL(jYUjZjLubaubj)rL}rL(jYXGives the output:rLjZj:LjbjOIjdjjf}rL(jh]ji]jj]jk]jn]ujpMcjqhjr]rLj{XGives the output:rLrL}rL(jYjLjZjLubaubj)rL}rL(jYXOptional parameter not configured : CG_XML_BIN_INSTALL_PATH REQUIRED for xdc release build Example: export CG_XML_BIN_INSTALL_PATH="~/ti/cg_xml/bin" Optional parameter not configured : DOXYGEN_INSTALL_PATH REQUIRED for xdc release build Example: export DOXYGEN_INSTALL_PATH="~/ti/Doxygen/doxygen/1.5.1-p1/bin" ************************************************************************** Environment Configuration: PDK Directory  : /home/[user]/new_sdk_release/pdk_[soc]_[version]/packages CGTOOL INSTALL Directory  : /home/[user]/new_sdk_release/ccsv6/tools/compiler/ti-cgt-c6000_[version] TOOLCHAIN A15 Directory  : /home/[user]/new_sdk_release/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN A8 Directory  : /home/[user]/new_sdk_release/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN A9 Directory  : /home/[user]/new_sdk_release/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN M4 Directory  : /home/[user]/new_sdk_release/ccsv6/tools/compiler/ti-cgt-arm_[version] FPULIB_PATH  : /home/[user]/new_sdk_release/ccsv6/tools/compiler/gcc-arm-none-eabi-[version]/lib/gcc/arm-none-eabi/[version]/fpu CROSS_TOOL_PRFX  : arm-none-eabi- XDC_INSTALL_PATH  : /home/[user]/new_sdk_release/xdctools_[version]_core BIOS_INSTALL_PATH  : /home/[user]/new_sdk_release/bios_[version] IPC_INSTALL_PATH  : /home/[user]/new_sdk_release/ipc_[version] EDMA3LLD_BIOS6_INSTALLDIR : /home/[user]/new_sdk_release/edma3_lld_[version] NDK_INSTALL_PATH  : /home/[user]/new_sdk_release/ndk_[version] IMGLIB_INSTALL_PATH  : /home/[user]/new_sdk_release/imglib_c66x_[version] UIA_INSTALL_PATH  : /home/[user]/new_sdk_release/uia_[version] PROC_SDK_INSTALL_PATH  : /home/[user]/new_sdk_release/processor_sdk_rtos_[soc]_[version] PROCESSOR SDK BUILD ENVIRONMENT CONFIGURED *******************************************************************************jZj:LjbjOIjdjjf}rL(jjjk]jj]jh]ji]jn]ujpM jqhjr]rLj{XOptional parameter not configured : CG_XML_BIN_INSTALL_PATH REQUIRED for xdc release build Example: export CG_XML_BIN_INSTALL_PATH="~/ti/cg_xml/bin" Optional parameter not configured : DOXYGEN_INSTALL_PATH REQUIRED for xdc release build Example: export DOXYGEN_INSTALL_PATH="~/ti/Doxygen/doxygen/1.5.1-p1/bin" ************************************************************************** Environment Configuration: PDK Directory  : /home/[user]/new_sdk_release/pdk_[soc]_[version]/packages CGTOOL INSTALL Directory  : /home/[user]/new_sdk_release/ccsv6/tools/compiler/ti-cgt-c6000_[version] TOOLCHAIN A15 Directory  : /home/[user]/new_sdk_release/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN A8 Directory  : /home/[user]/new_sdk_release/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN A9 Directory  : /home/[user]/new_sdk_release/ccsv6/tools/compiler/gcc-arm-none-eabi-[version] TOOLCHAIN M4 Directory  : /home/[user]/new_sdk_release/ccsv6/tools/compiler/ti-cgt-arm_[version] FPULIB_PATH  : /home/[user]/new_sdk_release/ccsv6/tools/compiler/gcc-arm-none-eabi-[version]/lib/gcc/arm-none-eabi/[version]/fpu CROSS_TOOL_PRFX  : arm-none-eabi- XDC_INSTALL_PATH  : /home/[user]/new_sdk_release/xdctools_[version]_core BIOS_INSTALL_PATH  : /home/[user]/new_sdk_release/bios_[version] IPC_INSTALL_PATH  : /home/[user]/new_sdk_release/ipc_[version] EDMA3LLD_BIOS6_INSTALLDIR : /home/[user]/new_sdk_release/edma3_lld_[version] NDK_INSTALL_PATH  : /home/[user]/new_sdk_release/ndk_[version] IMGLIB_INSTALL_PATH  : /home/[user]/new_sdk_release/imglib_c66x_[version] UIA_INSTALL_PATH  : /home/[user]/new_sdk_release/uia_[version] PROC_SDK_INSTALL_PATH  : /home/[user]/new_sdk_release/processor_sdk_rtos_[soc]_[version] PROCESSOR SDK BUILD ENVIRONMENT CONFIGURED *******************************************************************************rLrL}rL(jYUjZjLubaubj)rL}rL(jYXThe `RTOS SDK top level Makefile `__ can now be used to rebuild SDK RTOS components installed in the custom installation path using CCS and toolchains installed in a custom path as well.jZj:LjbjOIjdjjf}rL(jh]ji]jj]jk]jn]ujpMjqhjr]rL(j{XThe rLrL}rL(jYXThe jZjLubj)rL}rL(jYXH`RTOS SDK top level Makefile `__jf}rL(UnameXRTOS SDK top level MakefilejX&index_overview.html#top-level-makefilejk]jj]jh]ji]jn]ujZjLjr]rLj{XRTOS SDK top level MakefilerLrL}rL(jYUjZjLubajdjubj{X can now be used to rebuild SDK RTOS components installed in the custom installation path using CCS and toolchains installed in a custom path as well.rLrL}rL(jYX can now be used to rebuild SDK RTOS components installed in the custom installation path using CCS and toolchains installed in a custom path as well.jZjLubeubeubeubj[)rL}rL(jYUjZjLIjbjOIjdjejf}rL(jh]ji]jj]jk]rMUrebuilding-the-pdkrMajn]rMh@aujpMjqhjr]rM(jt)rM}rM(jYXRebuilding the PDKrMjZjLjbjOIjdjxjf}rM(jh]ji]jj]jk]jn]ujpMjqhjr]rMj{XRebuilding the PDKr Mr M}r M(jYjMjZjMubaubj)r M}r M(jYXInstalling the PDK in a folder other than the default (C:\TI for Windows, /home/[user]/ti for Linux) requires modifications to PDK scripts in order for recompilation and example/test creation to work properly.jZjLjbjOIjdjjf}rM(jh]ji]jj]jk]jn]ujpMjqhjr]rMj{XInstalling the PDK in a folder other than the default (C:TI for Windows, /home/[user]/ti for Linux) requires modifications to PDK scripts in order for recompilation and example/test creation to work properly.rMrM}rM(jYXInstalling the PDK in a folder other than the default (C:\TI for Windows, /home/[user]/ti for Linux) requires modifications to PDK scripts in order for recompilation and example/test creation to work properly.jZj Mubaubj[)rM}rM(jYUjZjLjbjOIjdjejf}rM(jh]ji]jj]jk]rMU*ccs-in-custom-path-and-pdk-in-default-pathrMajn]rMhjaujpMjqhjr]rM(jt)rM}rM(jYX*CCS in Custom Path and PDK in Default PathrMjZjMjbjOIjdjxjf}rM(jh]ji]jj]jk]jn]ujpMjqhjr]rMj{X*CCS in Custom Path and PDK in Default PathrMr M}r!M(jYjMjZjMubaubj)r"M}r#M(jYXThe instructions provided in the `CCS in Custom Path and SDK RTOS in Default Path `__ section can be used to rebuild components at the PDK level. The only difference is the PDK level setup script should be used instead of the SDK RTOS level setup script. The PDK level setup scripts are found in the following locations on Windows and Linux, respectively:jZjMjbjOIjdjjf}r$M(jh]ji]jj]jk]jn]ujpMjqhjr]r%M(j{X!The instructions provided in the r&Mr'M}r(M(jYX!The instructions provided in the jZj"Mubj)r)M}r*M(jYX`CCS in Custom Path and SDK RTOS in Default Path `__jf}r+M(UnameX/CCS in Custom Path and SDK RTOS in Default PathjXd/index.php/Processor_SDK_RTOS_Install_In_Custom_Path#CCS_in_Custom_Path_and_SDK_RTOS_in_Default_Pathjk]jj]jh]ji]jn]ujZj"Mjr]r,Mj{X/CCS in Custom Path and SDK RTOS in Default Pathr-Mr.M}r/M(jYUjZj)Mubajdjubj{X section can be used to rebuild components at the PDK level. The only difference is the PDK level setup script should be used instead of the SDK RTOS level setup script. The PDK level setup scripts are found in the following locations on Windows and Linux, respectively:r0Mr1M}r2M(jYX section can be used to rebuild components at the PDK level. The only difference is the PDK level setup script should be used instead of the SDK RTOS level setup script. The PDK level setup scripts are found in the following locations on Windows and Linux, respectively:jZj"MubeubjC)r3M}r4M(jYUjZjMjbjOIjdj`jf}r5M(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]r6M(j/)r7M}r8M(jYXSWindows - C:\\custom\\install\\path\\pdk_[soc]_[version]\\packages\\pdksetupenv.batjZj3MjbjOIjdj2jf}r9M(jh]ji]jj]jk]jn]ujpNjqhjr]r:Mj)r;M}rMj{XMWindows - C:\custom\install\path\pdk_[soc]_[version]\packages\pdksetupenv.batr?Mr@M}rAM(jYXSWindows - C:\\custom\\install\\path\\pdk_[soc]_[version]\\packages\\pdksetupenv.batjZj;Mubaubaubj/)rBM}rCM(jYXULinux - /home/[user]/custom/install/path/pdk_[soc]_[version]/packages/pdksetupenv.sh jZj3MjbjOIjdj2jf}rDM(jh]ji]jj]jk]jn]ujpNjqhjr]rEMj)rFM}rGM(jYXTLinux - /home/[user]/custom/install/path/pdk_[soc]_[version]/packages/pdksetupenv.shrHMjZjBMjbjOIjdjjf}rIM(jh]ji]jj]jk]jn]ujpMjr]rJMj{XTLinux - /home/[user]/custom/install/path/pdk_[soc]_[version]/packages/pdksetupenv.shrKMrLM}rMM(jYjHMjZjFMubaubaubeubeubj[)rNM}rOM(jYUjZjLjbjOIjdjejf}rPM(jh]ji]jj]jk]rQMU*ccs-in-default-path-and-pdk-in-custom-pathrRMajn]rSMhaujpMjqhjr]rTM(jt)rUM}rVM(jYX*CCS in Default Path and PDK in Custom PathrWMjZjNMjbjOIjdjxjf}rXM(jh]ji]jj]jk]jn]ujpMjqhjr]rYMj{X*CCS in Default Path and PDK in Custom PathrZMr[M}r\M(jYjWMjZjUMubaubj)r]M}r^M(jYXThe instructions provided in the `CCS in Default Path and SDK RTOS in Custom Path `__ section can be used to rebuild components at the PDK level. The only difference is the PDK level setup script should be used instead of the SDK RTOS level setup script. The PDK level setup scripts are found in the following locations on Windows and Linux, respectively:jZjNMjbjOIjdjjf}r_M(jh]ji]jj]jk]jn]ujpMjqhjr]r`M(j{X!The instructions provided in the raMrbM}rcM(jYX!The instructions provided in the jZj]Mubj)rdM}reM(jYX`CCS in Default Path and SDK RTOS in Custom Path `__jf}rfM(UnameX/CCS in Default Path and SDK RTOS in Custom PathjXd/index.php/Processor_SDK_RTOS_Install_In_Custom_Path#CCS_in_Default_Path_and_SDK_RTOS_in_Custom_Pathjk]jj]jh]ji]jn]ujZj]Mjr]rgMj{X/CCS in Default Path and SDK RTOS in Custom PathrhMriM}rjM(jYUjZjdMubajdjubj{X section can be used to rebuild components at the PDK level. The only difference is the PDK level setup script should be used instead of the SDK RTOS level setup script. The PDK level setup scripts are found in the following locations on Windows and Linux, respectively:rkMrlM}rmM(jYX section can be used to rebuild components at the PDK level. The only difference is the PDK level setup script should be used instead of the SDK RTOS level setup script. The PDK level setup scripts are found in the following locations on Windows and Linux, respectively:jZj]MubeubjC)rnM}roM(jYUjZjNMjbjOIjdj`jf}rpM(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]rqM(j/)rrM}rsM(jYXSWindows - C:\\custom\\install\\path\\pdk_[soc]_[version]\\packages\\pdksetupenv.batjZjnMjbjOIjdj2jf}rtM(jh]ji]jj]jk]jn]ujpNjqhjr]ruMj)rvM}rwM(jYXSWindows - C:\\custom\\install\\path\\pdk_[soc]_[version]\\packages\\pdksetupenv.batjZjrMjbjOIjdjjf}rxM(jh]ji]jj]jk]jn]ujpMjr]ryMj{XMWindows - C:\custom\install\path\pdk_[soc]_[version]\packages\pdksetupenv.batrzMr{M}r|M(jYXSWindows - C:\\custom\\install\\path\\pdk_[soc]_[version]\\packages\\pdksetupenv.batjZjvMubaubaubj/)r}M}r~M(jYXULinux - /home/[user]/custom/install/path/pdk_[soc]_[version]/packages/pdksetupenv.sh jZjnMjbjOIjdj2jf}rM(jh]ji]jj]jk]jn]ujpNjqhjr]rMj)rM}rM(jYXTLinux - /home/[user]/custom/install/path/pdk_[soc]_[version]/packages/pdksetupenv.shrMjZj}MjbjOIjdjjf}rM(jh]ji]jj]jk]jn]ujpMjr]rMj{XTLinux - /home/[user]/custom/install/path/pdk_[soc]_[version]/packages/pdksetupenv.shrMrM}rM(jYjMjZjMubaubaubeubeubj[)rM}rM(jYUjZjLjbjOIjdjejf}rM(jh]ji]jj]jk]rMUccs-and-pdk-in-custom-pathrMajn]rMh\aujpMjqhjr]rM(jt)rM}rM(jYXCCS and PDK in Custom PathrMjZjMjbjOIjdjxjf}rM(jh]ji]jj]jk]jn]ujpMjqhjr]rMj{XCCS and PDK in Custom PathrMrM}rM(jYjMjZjMubaubj)rM}rM(jYXThe instructions provided in the `CCS and SDK RTOS in Custom Path `__ section can be used to rebuild components at the PDK level. The only difference is the PDK level setup script should be used instead of the SDK RTOS level setup script. The PDK level setup scripts are found in the following locations on Windows and Linux, respectively:jZjMjbjOIjdjjf}rM(jh]ji]jj]jk]jn]ujpMjqhjr]rM(j{X!The instructions provided in the rMrM}rM(jYX!The instructions provided in the jZjMubj)rM}rM(jYXz`CCS and SDK RTOS in Custom Path `__jf}rM(UnameXCCS and SDK RTOS in Custom PathjXT/index.php/Processor_SDK_RTOS_Install_In_Custom_Path#CCS_and_SDK_RTOS_in_Custom_Pathjk]jj]jh]ji]jn]ujZjMjr]rMj{XCCS and SDK RTOS in Custom PathrMrM}rM(jYUjZjMubajdjubj{X section can be used to rebuild components at the PDK level. The only difference is the PDK level setup script should be used instead of the SDK RTOS level setup script. The PDK level setup scripts are found in the following locations on Windows and Linux, respectively:rMrM}rM(jYX section can be used to rebuild components at the PDK level. The only difference is the PDK level setup script should be used instead of the SDK RTOS level setup script. The PDK level setup scripts are found in the following locations on Windows and Linux, respectively:jZjMubeubjC)rM}rM(jYUjZjMjbjOIjdj`jf}rM(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]rM(j/)rM}rM(jYXSWindows - C:\\custom\\install\\path\\pdk_[soc]_[version]\\packages\\pdksetupenv.batjZjMjbjOIjdj2jf}rM(jh]ji]jj]jk]jn]ujpNjqhjr]rMj)rM}rM(jYXSWindows - C:\\custom\\install\\path\\pdk_[soc]_[version]\\packages\\pdksetupenv.batjZjMjbjOIjdjjf}rM(jh]ji]jj]jk]jn]ujpMjr]rMj{XMWindows - C:\custom\install\path\pdk_[soc]_[version]\packages\pdksetupenv.batrMrM}rM(jYXSWindows - C:\\custom\\install\\path\\pdk_[soc]_[version]\\packages\\pdksetupenv.batjZjMubaubaubj/)rM}rM(jYXVLinux - /home/[user]/custom/install/path/pdk_[soc]_[version]/packages/pdksetupenv.sh jZjMjbjOIjdj2jf}rM(jh]ji]jj]jk]jn]ujpNjqhjr]rMj)rM}rM(jYXTLinux - /home/[user]/custom/install/path/pdk_[soc]_[version]/packages/pdksetupenv.shrMjZjMjbjOIjdjjf}rM(jh]ji]jj]jk]jn]ujpMjr]rMj{XTLinux - /home/[user]/custom/install/path/pdk_[soc]_[version]/packages/pdksetupenv.shrMrM}rM(jYjMjZjMubaubaubeubeubeubj[)rM}rM(jYUjZjLIjbjOIjdjejf}rM(jh]ji]jj]jk]rMUGcreating-pdk-example-test-projects-when-ccs-is-installed-to-custom-pathrMajn]rMhXaujpMjqhjr]rM(jt)rM}rM(jYXGCreating PDK Example/Test Projects When CCS is Installed to Custom PathrMjZjMjbjOIjdjxjf}rM(jh]ji]jj]jk]jn]ujpMjqhjr]rMj{XGCreating PDK Example/Test Projects When CCS is Installed to Custom PathrMrM}rM(jYjMjZjMubaubj)rM}rM(jYXThe pdkProjectCreate scripts must be modified in order to build PDK example and test projects only if CCS has been installed to a custom path. The modification is the same for both Windows and Linux. Inside the pdkProjectCreate scripts is a CCS_INSTALL_PATH variable which points to the Code Composer Studio root directory. This variable must be redefined to the new location of the CCS root directory if CCS is installed to a custom path.rMjZjMjbjOIjdjjf}rM(jh]ji]jj]jk]jn]ujpMjqhjr]rMj{XThe pdkProjectCreate scripts must be modified in order to build PDK example and test projects only if CCS has been installed to a custom path. The modification is the same for both Windows and Linux. Inside the pdkProjectCreate scripts is a CCS_INSTALL_PATH variable which points to the Code Composer Studio root directory. This variable must be redefined to the new location of the CCS root directory if CCS is installed to a custom path.rMrM}rM(jYjMjZjMubaubjC)rM}rM(jYUjZjMjbjOIjdj`jf}rM(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]rMj/)rM}rM(jYXWindows jZjMjbjOIjdj2jf}rM(jh]ji]jj]jk]jn]ujpNjqhjr]rMj)rM}rM(jYXWindowsrMjZjMjbjOIjdjjf}rM(jh]ji]jj]jk]jn]ujpMjr]rMj{XWindowsrMrM}rM(jYjMjZjMubaubaubaubj)rM}rM(jYX?REM Install Location for CCS set CCS_INSTALL_PATH="C:\ti\ccsv6"jZjMjbjOIjdjjf}rM(jjjk]jj]jh]ji]jn]ujpMjqhjr]rMj{X?REM Install Location for CCS set CCS_INSTALL_PATH="C:\ti\ccsv6"rMrM}rM(jYUjZjMubaubjC)rM}rM(jYUjZjMjbjOIjdj`jf}rM(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]rMj/)rM}rM(jYXLinux jZjMjbjOIjdj2jf}rM(jh]ji]jj]jk]jn]ujpNjqhjr]rMj)rM}rM(jYXLinuxrMjZjMjbjOIjdjjf}rM(jh]ji]jj]jk]jn]ujpMjr]rMj{XLinuxrMrN}rN(jYjMjZjMubaubaubaubj)rN}rN(jYX=# Install Location for CCS export CCS_INSTALL_PATH=~/ti/ccsv6jZjMjbjOIjdjjf}rN(jjjk]jj]jh]ji]jn]ujpMjqhjr]rNj{X=# Install Location for CCS export CCS_INSTALL_PATH=~/ti/ccsv6rNrN}rN(jYUjZjNubaubj)r N}r N(jYXPrior to invoking the pdkProjectCreate script, make sure to start CCS and register the SDK RTOS components installed. Project creation will fail if the RTOS SDK components installed to the custom path have not been registered with CCS. Please see `CCS and SDK installed in different directories `__ for instructions on how to register SDK RTOS components installed to a custom path with CCSjZjMjbjOIjdjjf}r N(jh]ji]jj]jk]jn]ujpNjqhjr]r Nj)r N}rN(jYXPrior to invoking the pdkProjectCreate script, make sure to start CCS and register the SDK RTOS components installed. Project creation will fail if the RTOS SDK components installed to the custom path have not been registered with CCS. Please see `CCS and SDK installed in different directories `__ for instructions on how to register SDK RTOS components installed to a custom path with CCSjZj NjbjOIjdjjf}rN(jh]ji]jj]jk]jn]ujpMjr]rN(j{XPrior to invoking the pdkProjectCreate script, make sure to start CCS and register the SDK RTOS components installed. Project creation will fail if the RTOS SDK components installed to the custom path have not been registered with CCS. Please see rNrN}rN(jYXPrior to invoking the pdkProjectCreate script, make sure to start CCS and register the SDK RTOS components installed. Project creation will fail if the RTOS SDK components installed to the custom path have not been registered with CCS. Please see jZj Nubj)rN}rN(jYX`CCS and SDK installed in different directories `__jf}rN(UnameX.CCS and SDK installed in different directoriesjXV/index.php/Processor_SDK_RTOS_Setup_CCS#CCS_and_SDK_installed_in_different_directoriesjk]jj]jh]ji]jn]ujZj Njr]rNj{X.CCS and SDK installed in different directoriesrNrN}rN(jYUjZjNubajdjubj{X\ for instructions on how to register SDK RTOS components installed to a custom path with CCSrNrN}rN(jYX\ for instructions on how to register SDK RTOS components installed to a custom path with CCSjZj Nubeubaubeubeubj[)rN}rN(jYUjZjjbjcjdjejf}r N(jh]ji]jj]jk]r!NU.prevent-beaglebone-board-reset-on-jtag-connectr"Najn]r#Nj$aujpK.jqhjr]r$N(jt)r%N}r&N(jYX.Prevent BeagleBone board reset on JTAG Connectr'NjZjNjbjcjdjxjf}r(N(jh]ji]jj]jk]jn]ujpK.jqhjr]r)Nj{X.Prevent BeagleBone board reset on JTAG Connectr*Nr+N}r,N(jYj'NjZj%Nubaubj)r-N}r.N(jYX]``__r/NjZjNjbjcjdjjf}r0N(jh]ji]jj]jk]jn]ujpK/jqhjr]r1Nj)r2N}r3N(jYj/Njf}r4N(UnameXWhttps://elinux.org/Beagleboard:BeagleBone#Board_Reset_on_JTAG_Connect.28A3.2CA4.2CA5.29r5Njj5Njk]jj]jh]ji]jn]ujZj-Njr]r6Nj{XWhttps://elinux.org/Beagleboard:BeagleBone#Board_Reset_on_JTAG_Connect.28A3.2CA4.2CA5.29r7Nr8N}r9N(jYUjZj2Nubajdjubaubeubj[)r:N}r;N(jYUjZjjbjcjdjejf}rNajn]r?NjaujpK3jqhjr]r@N(jt)rAN}rBN(jYX"Rebuild drivers from PDK directoryrCNjZj:Njbjcjdjxjf}rDN(jh]ji]jj]jk]jn]ujpK3jqhjr]rENj{X"Rebuild drivers from PDK directoryrFNrGN}rHN(jYjCNjZjANubaubj)rIN}rJN(jYXfRefer `Rebuilding the PDK `__ for details on rebuilding the PDK components.rKNjZj:Njbjcjdjjf}rLN(jh]ji]jj]jk]jn]ujpK4jqhjr]rMN(j{XRefer rNNrON}rPN(jYXRefer jZjINubj)rQN}rRN(jYX2`Rebuilding the PDK `__jf}rSN(UnameXRebuilding the PDKjXOverview.html#rebuild-pdkjk]jj]jh]ji]jn]ujZjINjr]rTNj{XRebuilding the PDKrUNrVN}rWN(jYUjZjQNubajdjubj{X. for details on rebuilding the PDK components.rXNrYN}rZN(jYX. for details on rebuilding the PDK components.jZjINubeubeubeubjbjWIj}r[NjAjHIsjdjejf}r\N(jh]ji]jj]jk]r]N(U(setup-ccs-for-evm-and-processor-sdk-rtosr^NjKIejn]r_N(h}jAeujpKjqhj}r`NjKIjHIsjr]raN(jt)rbN}rcN(jYX(Setup CCS for EVM and Processor-SDK RTOSrdNjZjjbjWIjdjxjf}reN(jh]ji]jj]jk]jn]ujpKjqhjr]rfNj{X(Setup CCS for EVM and Processor-SDK RTOSrgNrhN}riN(jYjdNjZjbNubaubj)rjN}rkN(jYXDhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_Setup_CCSjZjjbjWIjdjjf}rlN(jjjk]jj]jh]ji]jn]ujpKjqhjr]rmNj{XDhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_Setup_CCSrnNroN}rpN(jYUjZjjNubaubj[)rqN}rrN(jYUjKjZjjbjWIjdjejf}rsN(jh]rtNj=Jaji]jj]jk]ruNUoverviewrvNajn]ujpKjqhjr]rwN(jt)rxN}ryN(jYXOverviewrzNjZjqNjbjWIjdjxjf}r{N(jh]ji]jj]jk]jn]ujpKjqhjr]r|Nj{XOverviewr}Nr~N}rN(jYjzNjZjxNubaubj)rN}rN(jYXkThis page provides information on configuring CCS to work with both the EVM and the Processor-SDK for RTOS.rNjZjqNjbjWIjdjjf}rN(jh]ji]jj]jk]jn]ujpK jqhjr]rNj{XkThis page provides information on configuring CCS to work with both the EVM and the Processor-SDK for RTOS.rNrN}rN(jYjNjZjNubaubeubjeubjbjWIjdjejf}rN(jh]ji]jj]jk]rNUdiscovering-sdk-productsrNajn]rNh"aujpK jqhjr]rN(jt)rN}rN(jYXDiscovering SDK productsrNjZjjbjWIjdjxjf}rN(jh]ji]jj]jk]jn]ujpK jqhjr]rNj{XDiscovering SDK productsrNrN}rN(jYjNjZjNubaubjj[)rN}rN(jYUjZjjbjWIjdjejf}rN(jh]ji]jj]jk]rNU.ccs-and-sdk-installed-in-different-directoriesrNajn]rNhaujpKjqhjr]rN(jt)rN}rN(jYX.CCS and SDK installed in different directoriesrNjZjNjbjWIjdjxjf}rN(jh]ji]jj]jk]jn]ujpKjqhjr]rNj{X.CCS and SDK installed in different directoriesrNrN}rN(jYjNjZjNubaubj)rN}rN(jYXLIf you chose to install the SDK package in a different folder from where CCS is installed (e.g. C:\\TEMP\\RTOS-SDK\\am57x), then you will need to add the path to the search path for CCS to locate the new packages. The screenshots below demonstrate the process to setup the CCS environment; the sequence for a Linux host is the same.jZjNjbjWIjdjjf}rN(jh]ji]jj]jk]jn]ujpKjqhjr]rNj{XIIf you chose to install the SDK package in a different folder from where CCS is installed (e.g. C:\TEMP\RTOS-SDK\am57x), then you will need to add the path to the search path for CCS to locate the new packages. The screenshots below demonstrate the process to setup the CCS environment; the sequence for a Linux host is the same.rNrN}rN(jYXLIf you chose to install the SDK package in a different folder from where CCS is installed (e.g. C:\\TEMP\\RTOS-SDK\\am57x), then you will need to add the path to the search path for CCS to locate the new packages. The screenshots below demonstrate the process to setup the CCS environment; the sequence for a Linux host is the same.jZjNubaubj[)rN}rN(jYUjZjNjbjWIjdjejf}rN(jh]ji]jj]jk]rNUgo-to-product-preferencerNajn]rNhaujpK!jqhjr]rN(jt)rN}rN(jYXGo to product preferencerNjZjNjbjWIjdjxjf}rN(jh]ji]jj]jk]jn]ujpK!jqhjr]rNj{XGo to product preferencerNrN}rN(jYjNjZjNubaubj)rN}rN(jYX)From CCS, select "Window -> Preferences":rNjZjNjbjWIjdjjf}rN(jh]ji]jj]jk]jn]ujpK#jqhjr]rNj{X)From CCS, select "Window -> Preferences":rNrN}rN(jYjNjZjNubaubjB)rN}rN(jYX9.. Image:: ../images/CCS-GP57x-EVM-Custom-Preferences.pngrNjZjNjbjWIjdjEjf}rN(UuriX3rtos/../images/CCS-GP57x-EVM-Custom-Preferences.pngrNjk]jj]jh]ji]jH}rNU*jNsjn]ujpK%jqhjr]ubjZ)rN}rN(jYUjZjNjbjWIjdj]jf}rN(jh]ji]jj]jk]jn]ujpK&jqhjr]rNj`)rN}rN(jYUjcKjZjNjbjWIjdjpjf}rN(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubj[)rN}rN(jYUjZjNjbjWIjdjejf}rN(jh]ji]jj]jk]rNUenter-path-to-sdkrNajn]rNj/aujpK(jqhjr]rN(jt)rN}rN(jYXEnter path to SDKrNjZjNjbjWIjdjxjf}rN(jh]ji]jj]jk]jn]ujpK(jqhjr]rNj{XEnter path to SDKrNrN}rN(jYjNjZjNubaubj)rN}rN(jYXIn the Preferences window, select "Code Composer Studio -> RTSC -> Products" in the panel on the left. Then, press the "Add" button on the panel on the right:rNjZjNjbjWIjdjjf}rN(jh]ji]jj]jk]jn]ujpK*jqhjr]rNj{XIn the Preferences window, select "Code Composer Studio -> RTSC -> Products" in the panel on the left. Then, press the "Add" button on the panel on the right:rNrN}rN(jYjNjZjNubaubjB)rN}rN(jYX1.. Image:: ../images/CCS-GP57x-EVM-Custom-Add.pngrNjZjNjbjWIjdjEjf}rN(UuriX+rtos/../images/CCS-GP57x-EVM-Custom-Add.pngrNjk]jj]jh]ji]jH}rNU*jNsjn]ujpK.jqhjr]ubjZ)rN}rN(jYUjZjNjbjWIjdj]jf}rN(jh]ji]jj]jk]jn]ujpK/jqhjr]rNj`)rN}rN(jYUjcKjZjNjbjWIjdjpjf}rN(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubj[)rN}rN(jYUjZjNjbjWIjdjejf}rN(jh]ji]jj]jk]rNUverify-componentsrNajn]rNhaujpK1jqhjr]rN(jt)rN}rN(jYXVerify componentsrNjZjNjbjWIjdjxjf}rN(jh]ji]jj]jk]jn]ujpK1jqhjr]rNj{XVerify componentsrNrO}rO(jYjNjZjNubaubj)rO}rO(jYXnNext, verify the newly discovered products. If everything is correct, press the "Finish" button on the bottom:rOjZjNjbjWIjdjjf}rO(jh]ji]jj]jk]jn]ujpK3jqhjr]rOj{XnNext, verify the newly discovered products. If everything is correct, press the "Finish" button on the bottom:rOrO}r O(jYjOjZjOubaubjB)r O}r O(jYX4.. Image:: ../images/CCS-GP57x-EVM-Custom-Finish.pngr OjZjNjbjWIjdjEjf}r O(UuriX.rtos/../images/CCS-GP57x-EVM-Custom-Finish.pngrOjk]jj]jh]ji]jH}rOU*jOsjn]ujpK6jqhjr]ubjZ)rO}rO(jYUjZjNjbjWIjdj]jf}rO(jh]ji]jj]jk]jn]ujpK7jqhjr]rOj`)rO}rO(jYUjcKjZjOjbjWIjdjpjf}rO(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubj[)rO}rO(jYUjZjNjbjWIjdjejf}rO(jh]ji]jj]jk]rOU restart-ccsrOajn]rOjLaujpK9jqhjr]rO(jt)rO}rO(jYX Restart CCSr OjZjOjbjWIjdjxjf}r!O(jh]ji]jj]jk]jn]ujpK9jqhjr]r"Oj{X Restart CCSr#Or$O}r%O(jYj OjZjOubaubj)r&O}r'O(jYXsWhen prompted, restart CCS for changes to take effect. You will see newly discovered products from the custom path.r(OjZjOjbjWIjdjjf}r)O(jh]ji]jj]jk]jn]ujpK;jqhjr]r*Oj{XsWhen prompted, restart CCS for changes to take effect. You will see newly discovered products from the custom path.r+Or,O}r-O(jYj(OjZj&OubaubjB)r.O}r/O(jYX5.. Image:: ../images/CCS-GP57x-EVM-Custom-Confirm.pngr0OjZjOjbjWIjdjEjf}r1O(UuriX/rtos/../images/CCS-GP57x-EVM-Custom-Confirm.pngr2Ojk]jj]jh]ji]jH}r3OU*j2Osjn]ujpK>jqhjr]ubjZ)r4O}r5O(jYUjZjOjbjWIjdj]jf}r6O(jh]ji]jj]jk]jn]ujpK?jqhjr]r7Oj`)r8O}r9O(jYUjcKjZj4OjbjWIjdjpjf}r:O(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubeubj[)r;O}rOUBinstall-latest-emulation-package-and-sitara-device-support-packager?Oajn]r@OhaujpKBjqhjr]rAO(jt)rBO}rCO(jYXBInstall Latest Emulation Package and Sitara Device Support PackagerDOjZj;OjbjWIjdjxjf}rEO(jh]ji]jj]jk]jn]ujpKBjqhjr]rFOj{XBInstall Latest Emulation Package and Sitara Device Support PackagerGOrHO}rIO(jYjDOjZjBOubaubj)rJO}rKO(jYXv1. In CCS, navigate to Help -> Check for Updates and select "Sitara device support" and "TI Emulators" and click Next.rLOjZj;OjbjWIjdjjf}rMO(jh]ji]jj]jk]jn]ujpKCjqhjr]rNOj{Xv1. In CCS, navigate to Help -> Check for Updates and select "Sitara device support" and "TI Emulators" and click Next.rOOrPO}rQO(jYjLOjZjJOubaubj=)rRO}rSO(jYUjZj;OjbNjdj@jf}rTO(jh]ji]jj]jk]jn]ujpNjqhjr]rUOjB)rVO}rWO(jYXJ.. image:: ../images/TMDX654_EVM_Hardware_Setup/CCS_Check_for_Updates.PNG jf}rXO(UuriXCrtos/../images/TMDX654_EVM_Hardware_Setup/CCS_Check_for_Updates.PNGrYOjk]jj]jh]ji]jH}rZOU*jYOsjn]ujZjROjr]jdjEubaubj)r[O}r\O(jYXx2. Click "Next" again, select "I accept the terms of the license agreements" and click Finish to begin the installation.r]OjZj;OjbjWIjdjjf}r^O(jh]ji]jj]jk]jn]ujpKHjqhjr]r_Oj{Xx2. Click "Next" again, select "I accept the terms of the license agreements" and click Finish to begin the installation.r`OraO}rbO(jYj]OjZj[Oubaubj=)rcO}rdO(jYUjZj;OjbNjdj@jf}reO(jh]ji]jj]jk]jn]ujpNjqhjr]rfOjB)rgO}rhO(jYXJ.. image:: ../images/TMDX654_EVM_Hardware_Setup/CCS_Updating_Software.png jf}riO(UuriXCrtos/../images/TMDX654_EVM_Hardware_Setup/CCS_Updating_Software.pngrjOjk]jj]jh]ji]jH}rkOU*jjOsjn]ujZjcOjr]jdjEubaubj)rlO}rmO(jYX3. You may be prompted to restart CCS for the updates to take effect. Click "Restart Now" when prompted to complete the installation.rnOjZj;OjbjWIjdjjf}roO(jh]ji]jj]jk]jn]ujpKMjqhjr]rpOj{X3. You may be prompted to restart CCS for the updates to take effect. Click "Restart Now" when prompted to complete the installation.rqOrrO}rsO(jYjnOjZjlOubaubeubj[)rtO}ruO(jYUjZjjbjWIjdjejf}rvO(jh]ji]jj]jk]rwOU(create-target-configuration-file-for-evmrxOajn]ryOhaujpKRjqhjr]rzO(jt)r{O}r|O(jYX(Create Target Configuration File for EVMr}OjZjtOjbjWIjdjxjf}r~O(jh]ji]jj]jk]jn]ujpKRjqhjr]rOj{X(Create Target Configuration File for EVMrOrO}rO(jYj}OjZj{Oubaubj)rO}rO(jYXIn CCS, you need to create a *Target Configuration* for your EVM to be able to connect to the target. This configuration defines your:jZjtOjbjWIjdjjf}rO(jh]ji]jj]jk]jn]ujpKTjqhjr]rO(j{XIn CCS, you need to create a rOrO}rO(jYXIn CCS, you need to create a jZjOubj')rO}rO(jYX*Target Configuration*jf}rO(jh]ji]jj]jk]jn]ujZjOjr]rOj{XTarget ConfigurationrOrO}rO(jYUjZjOubajdj'ubj{XS for your EVM to be able to connect to the target. This configuration defines your:rOrO}rO(jYXS for your EVM to be able to connect to the target. This configuration defines your:jZjOubeubjC)rO}rO(jYUjZjtOjbjWIjdj`jf}rO(jGX-jk]jj]jh]ji]jn]ujpKWjqhjr]rO(j/)rO}rO(jYX)Connection to the target (XDS, FET, etc.)rOjZjOjbjWIjdj2jf}rO(jh]ji]jj]jk]jn]ujpNjqhjr]rOj)rO}rO(jYjOjZjOjbjWIjdjjf}rO(jh]ji]jj]jk]jn]ujpKWjr]rOj{X)Connection to the target (XDS, FET, etc.)rOrO}rO(jYjOjZjOubaubaubj/)rO}rO(jYX1Target device (AM437x GP EVM, AM57x GP EVM, etc.)rOjZjOjbjWIjdj2jf}rO(jh]ji]jj]jk]jn]ujpNjqhjr]rOj)rO}rO(jYjOjZjOjbjWIjdjjf}rO(jh]ji]jj]jk]jn]ujpKXjr]rOj{X1Target device (AM437x GP EVM, AM57x GP EVM, etc.)rOrO}rO(jYjOjZjOubaubaubj/)rO}rO(jYXGEL file for hardware initialization. A GEL file is basically a “batch file” that sets up the CCS debug environment including memory map, PLL, clock, etc. jZjOjbjWIjdj2jf}rO(jh]ji]jj]jk]jn]ujpNjqhjr]rOj)rO}rO(jYXGEL file for hardware initialization. A GEL file is basically a “batch file” that sets up the CCS debug environment including memory map, PLL, clock, etc.rOjZjOjbjWIjdjjf}rO(jh]ji]jj]jk]jn]ujpKYjr]rOj{XGEL file for hardware initialization. A GEL file is basically a “batch file” that sets up the CCS debug environment including memory map, PLL, clock, etc.rOrO}rO(jYjOjZjOubaubaubeubj)rO}rO(jYXCCS comes with basic configuration that can be used to configure your particular setup. In the example below, we provide details for a GP AM437x EVM; configuration information for other supported EVMs are also provided as needed.rOjZjtOjbjWIjdjjf}rO(jh]ji]jj]jk]jn]ujpK]jqhjr]rOj{XCCS comes with basic configuration that can be used to configure your particular setup. In the example below, we provide details for a GP AM437x EVM; configuration information for other supported EVMs are also provided as needed.rOrO}rO(jYjOjZjOubaubj)rO}rO(jYXFor EVM specific instructions, refer to the **Hardware User's Guide** for your `EVM `__jZjtOjbjWIjdjjf}rO(jh]ji]jj]jk]jn]ujpKbjqhjr]rO(j{X,For EVM specific instructions, refer to the rOrO}rO(jYX,For EVM specific instructions, refer to the jZjOubj)rO}rO(jYX**Hardware User's Guide**jf}rO(jh]ji]jj]jk]jn]ujZjOjr]rOj{XHardware User's GuiderOrO}rO(jYUjZjOubajdjubj{X for your rOrO}rO(jYX for your jZjOubj)rO}rO(jYXF`EVM `__jf}rO(UnameXEVMjX<index_release_specific.html#supported-platforms-and-versionsjk]jj]jh]ji]jn]ujZjOjr]rOj{XEVMrOrO}rO(jYUjZjOubajdjubeubj)rO}rO(jYX**Note for K2G devices:** If using CCS v6.1.2 and Keystone2 device support v1.1.7, 66AK2G02 would not show up in the list of devices when creating the target configuration. This is due to an incompatibility in the XML parser in CCS v6.1.2 with the K2G device xml. In order to work-around this issue, make the change in 66AK2G02.xml as illustrated below in order to have 66AK2G02 display in the device list. This problem does not exist in CCS v6.1.3 onwards as the XML parser has been updated. :: C:\ti\ccsv6\ccs_base\common\targetdb\devices\66AK2G02.xml Line #1 to jZjtOjbjWIjdjjf}rO(jh]ji]jj]jk]jn]ujpNjqhjr]rO(j)rO}rO(jYX**Note for K2G devices:** If using CCS v6.1.2 and Keystone2 device support v1.1.7, 66AK2G02 would not show up in the list of devices when creating the target configuration. This is due to an incompatibility in the XML parser in CCS v6.1.2 with the K2G device xml. In order to work-around this issue, make the change in 66AK2G02.xml as illustrated below in order to have 66AK2G02 display in the device list. This problem does not exist in CCS v6.1.3 onwards as the XML parser has been updated.jZjOjbjWIjdjjf}rO(jh]ji]jj]jk]jn]ujpKfjr]rO(j)rO}rO(jYX**Note for K2G devices:**jf}rO(jh]ji]jj]jk]jn]ujZjOjr]rOj{XNote for K2G devices:rOrO}rO(jYUjZjOubajdjubj{X If using CCS v6.1.2 and Keystone2 device support v1.1.7, 66AK2G02 would not show up in the list of devices when creating the target configuration. This is due to an incompatibility in the XML parser in CCS v6.1.2 with the K2G device xml. In order to work-around this issue, make the change in 66AK2G02.xml as illustrated below in order to have 66AK2G02 display in the device list. This problem does not exist in CCS v6.1.3 onwards as the XML parser has been updated.rOrO}rO(jYX If using CCS v6.1.2 and Keystone2 device support v1.1.7, 66AK2G02 would not show up in the list of devices when creating the target configuration. This is due to an incompatibility in the XML parser in CCS v6.1.2 with the K2G device xml. In order to work-around this issue, make the change in 66AK2G02.xml as illustrated below in order to have 66AK2G02 display in the device list. This problem does not exist in CCS v6.1.3 onwards as the XML parser has been updated.jZjOubeubj)rO}rO(jYXC:\ti\ccsv6\ccs_base\common\targetdb\devices\66AK2G02.xml Line #1 to jZjOjdjjf}rO(jjjk]jj]jh]ji]jn]ujpMjr]rOj{XC:\ti\ccsv6\ccs_base\common\targetdb\devices\66AK2G02.xml Line #1 to rOrO}rO(jYUjZjOubaubeubj[)rO}rO(jYUjZjtOjbjWIjdjejf}rO(jh]ji]jj]jk]rOU"open-new-target-configuration-filerOajn]rOhHaujpKyjqhjr]rO(jt)rO}rO(jYX"Open new target configuration filerOjZjOjbjWIjdjxjf}rO(jh]ji]jj]jk]jn]ujpKyjqhjr]rPj{X"Open new target configuration filerPrP}rP(jYjOjZjOubaubj)rP}rP(jYX<From CCS, select "File -> New -> Target Configuration File":rPjZjOjbjWIjdjjf}rP(jh]ji]jj]jk]jn]ujpK{jqhjr]rPj{X<From CCS, select "File -> New -> Target Configuration File":r Pr P}r P(jYjPjZjPubaubjB)r P}r P(jYX2.. Image:: ../images/CCS-GP437x-EVM-New-Target.pngrPjZjOjbjWIjdjEjf}rP(UuriX,rtos/../images/CCS-GP437x-EVM-New-Target.pngrPjk]jj]jh]ji]jH}rPU*jPsjn]ujpK}jqhjr]ubjZ)rP}rP(jYUjZjOjbjWIjdj]jf}rP(jh]ji]jj]jk]jn]ujpK~jqhjr]rPj`)rP}rP(jYUjcKjZjPjbjWIjdjpjf}rP(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubj[)rP}rP(jYUjZjtOjbjWIjdjejf}rP(jh]ji]jj]jk]rPU#select-target-configuration-optionsrPajn]rPj=aujpKjqhjr]rP(jt)r P}r!P(jYX#Select target configuration optionsr"PjZjPjbjWIjdjxjf}r#P(jh]ji]jj]jk]jn]ujpKjqhjr]r$Pj{X#Select target configuration optionsr%Pr&P}r'P(jYj"PjZj Pubaubj)r(P}r)P(jYXdThe AM437x GP EVM supports embedded XDS100V2 USB Emulation through the MicroUSB AB connector. Selectr*PjZjPjbjWIjdjjf}r+P(jh]ji]jj]jk]jn]ujpKjqhjr]r,Pj{XdThe AM437x GP EVM supports embedded XDS100V2 USB Emulation through the MicroUSB AB connector. Selectr-Pr.P}r/P(jYj*PjZj(PubaubjC)r0P}r1P(jYUjZjPjbjWIjdj`jf}r2P(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]r3P(j/)r4P}r5P(jYX:**Connection**: Texas Instruments XDS100v2 USB Debug Prober6PjZj0PjbjWIjdj2jf}r7P(jh]ji]jj]jk]jn]ujpNjqhjr]r8Pj)r9P}r:P(jYj6PjZj4PjbjWIjdjjf}r;P(jh]ji]jj]jk]jn]ujpKjr]rP(jYX**Connection**jf}r?P(jh]ji]jj]jk]jn]ujZj9Pjr]r@Pj{X ConnectionrAPrBP}rCP(jYUjZj=Pubajdjubj{X,: Texas Instruments XDS100v2 USB Debug ProberDPrEP}rFP(jYX,: Texas Instruments XDS100v2 USB Debug ProbejZj9Pubeubaubj/)rGP}rHP(jYX**Board or Device**: EVMAM437X jZj0PjbjWIjdj2jf}rIP(jh]ji]jj]jk]jn]ujpNjqhjr]rJPj)rKP}rLP(jYX**Board or Device**: EVMAM437XjZjGPjbjWIjdjjf}rMP(jh]ji]jj]jk]jn]ujpKjr]rNP(j)rOP}rPP(jYX**Board or Device**jf}rQP(jh]ji]jj]jk]jn]ujZjKPjr]rRPj{XBoard or DevicerSPrTP}rUP(jYUjZjOPubajdjubj{X : EVMAM437XrVPrWP}rXP(jYX : EVMAM437XjZjKPubeubaubeubjB)rYP}rZP(jYX8.. Image:: ../images/CCS-GP437x-EVM-Configure-Target.pngr[PjZjPjbjWIjdjEjf}r\P(UuriX2rtos/../images/CCS-GP437x-EVM-Configure-Target.pngr]Pjk]jj]jh]ji]jH}r^PU*j]Psjn]ujpKjqhjr]ubjZ)r_P}r`P(jYUjZjPjbjWIjdj]jf}raP(jh]ji]jj]jk]jn]ujpKjqhjr]rbPj`)rcP}rdP(jYUjcKjZj_PjbjWIjdjpjf}reP(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)rfP}rgP(jYX**Useful Tip**rhPjZjPjbjWIjdjjf}riP(jh]ji]jj]jk]jn]ujpKjqhjr]rjPj)rkP}rlP(jYjhPjf}rmP(jh]ji]jj]jk]jn]ujZjfPjr]rnPj{X Useful TiproPrpP}rqP(jYUjZjkPubajdjubaubj)rrP}rsP(jYXzIf you enter the starting numbers of your device in the **Board or Device** field, the list will show the relevant subset.jZjPjbjWIjdjjf}rtP(jh]ji]jj]jk]jn]ujpKjqhjr]ruP(j{X8If you enter the starting numbers of your device in the rvPrwP}rxP(jYX8If you enter the starting numbers of your device in the jZjrPubj)ryP}rzP(jYX**Board or Device**jf}r{P(jh]ji]jj]jk]jn]ujZjrPjr]r|Pj{XBoard or Devicer}Pr~P}rP(jYUjZjyPubajdjubj{X/ field, the list will show the relevant subset.rPrP}rP(jYX/ field, the list will show the relevant subset.jZjrPubeubj)rP}rP(jYXcHere is a table showing configuration information for all supported EVMs in the Processor-SDK RTOS:rPjZjPjbjWIjdjjf}rP(jh]ji]jj]jk]jn]ujpKjqhjr]rPj{XcHere is a table showing configuration information for all supported EVMs in the Processor-SDK RTOS:rPrP}rP(jYjPjZjPubaubjd$)rP}rP(jYUjZjPjbjWIjdjg$jf}rP(jh]ji]jj]jk]jn]ujpNjqhjr]rPjj$)rP}rP(jYUjf}rP(jk]jj]jh]ji]jn]UcolsKujZjPjr]rP(jo$)rP}rP(jYUjf}rP(jk]jj]jh]ji]jn]UcolwidthKujZjPjr]jdjs$ubjo$)rP}rP(jYUjf}rP(jk]jj]jh]ji]jn]UcolwidthKujZjPjr]jdjs$ubjo$)rP}rP(jYUjf}rP(jk]jj]jh]ji]jn]UcolwidthKujZjPjr]jdjs$ubjz$)rP}rP(jYUjf}rP(jh]ji]jj]jk]jn]ujZjPjr]rPj$)rP}rP(jYUjf}rP(jh]ji]jj]jk]jn]ujZjPjr]rP(j$)rP}rP(jYUjf}rP(jh]ji]jj]jk]jn]ujZjPjr]rPj)rP}rP(jYXEVMrPjZjPjbjWIjdjjf}rP(jh]ji]jj]jk]jn]ujpKjr]rPj{XEVMrPrP}rP(jYjPjZjPubaubajdj$ubj$)rP}rP(jYUjf}rP(jh]ji]jj]jk]jn]ujZjPjr]rPj)rP}rP(jYX ConnectionrPjZjPjbjWIjdjjf}rP(jh]ji]jj]jk]jn]ujpKjr]rPj{X ConnectionrPrP}rP(jYjPjZjPubaubajdj$ubj$)rP}rP(jYUjf}rP(jh]ji]jj]jk]jn]ujZjPjr]rPj)rP}rP(jYXBoardrPjZjPjbjWIjdjjf}rP(jh]ji]jj]jk]jn]ujpKjr]rPj{XBoardrPrP}rP(jYjPjZjPubaubajdj$ubejdj$ubajdj$ubj$)rP}rP(jYUjf}rP(jh]ji]jj]jk]jn]ujZjPjr]rP(j$)rP}rP(jYUjf}rP(jh]ji]jj]jk]jn]ujZjPjr]rP(j$)rP}rP(jYUjf}rP(jh]ji]jj]jk]jn]ujZjPjr]rPj)rP}rP(jYX AM65x EVMrPjZjPjbjWIjdjjf}rP(jh]ji]jj]jk]jn]ujpKjr]rPj{X AM65x EVMrPrP}rP(jYjPjZjPubaubajdj$ubj$)rP}rP(jYUjf}rP(jh]ji]jj]jk]jn]ujZjPjr]rPj)rP}rP(jYX(Texas Instruments XDS110 USB Debug ProberPjZjPjbjWIjdjjf}rP(jh]ji]jj]jk]jn]ujpKjr]rPj{X(Texas Instruments XDS110 USB Debug ProberPrP}rP(jYjPjZjPubaubajdj$ubj$)rP}rP(jYUjf}rP(jh]ji]jj]jk]jn]ujZjPjr]rPj)rP}rP(jYX GPEVM_AM65xrPjZjPjbjWIjdjjf}rP(jh]ji]jj]jk]jn]ujpKjr]rPj{X GPEVM_AM65xrPrP}rP(jYjPjZjPubaubajdj$ubejdj$ubj$)rP}rP(jYUjf}rP(jh]ji]jj]jk]jn]ujZjPjr]rP(j$)rP}rP(jYUjf}rP(jh]ji]jj]jk]jn]ujZjPjr]rPj)rP}rP(jYX AM65x IDKrPjZjPjbjWIjdjjf}rP(jh]ji]jj]jk]jn]ujpKjr]rQj{X AM65x IDKrQrQ}rQ(jYjPjZjPubaubajdj$ubj$)rQ}rQ(jYUjf}rQ(jh]ji]jj]jk]jn]ujZjPjr]rQj)rQ}r Q(jYX(Texas Instruments XDS110 USB Debug Prober QjZjQjbjWIjdjjf}r Q(jh]ji]jj]jk]jn]ujpKjr]r Qj{X(Texas Instruments XDS110 USB Debug Prober QrQ}rQ(jYj QjZjQubaubajdj$ubj$)rQ}rQ(jYUjf}rQ(jh]ji]jj]jk]jn]ujZjPjr]rQj)rQ}rQ(jYX IDK_AM65xrQjZjQjbjWIjdjjf}rQ(jh]ji]jj]jk]jn]ujpKjr]rQj{X IDK_AM65xrQrQ}rQ(jYjQjZjQubaubajdj$ubejdj$ubj$)rQ}rQ(jYUjf}rQ(jh]ji]jj]jk]jn]ujZjPjr]rQ(j$)r Q}r!Q(jYUjf}r"Q(jh]ji]jj]jk]jn]ujZjQjr]r#Qj)r$Q}r%Q(jYXGP335xr&QjZj QjbjWIjdjjf}r'Q(jh]ji]jj]jk]jn]ujpKjr]r(Qj{XGP335xr)Qr*Q}r+Q(jYj&QjZj$Qubaubajdj$ubj$)r,Q}r-Q(jYUjf}r.Q(jh]ji]jj]jk]jn]ujZjQjr]r/Qj)r0Q}r1Q(jYXLExternal Emulator Supplied by User. EVM includes a TI 20 pin JTAG connector.r2QjZj,QjbjWIjdjjf}r3Q(jh]ji]jj]jk]jn]ujpKjr]r4Qj{XLExternal Emulator Supplied by User. EVM includes a TI 20 pin JTAG connector.r5Qr6Q}r7Q(jYj2QjZj0Qubaubajdj$ubj$)r8Q}r9Q(jYUjf}r:Q(jh]ji]jj]jk]jn]ujZjQjr]r;Qj)rQjZj8QjbjWIjdjjf}r?Q(jh]ji]jj]jk]jn]ujpKjr]r@Qj{X EVMAM3358rAQrBQ}rCQ(jYj>QjZjRjZj8RjbjWIjdjjf}r?R(jh]ji]jj]jk]jn]ujpKjr]r@Rj{XX15rARrBR}rCR(jYj>RjZjS}r?S(jYj:SjZj8Subaubajdj$ubj$)r@S}rAS(jYUjf}rBS(jh]ji]jj]jk]jn]ujZj$Sjr]rCSj)rDS}rES(jYX TCI6630K2LrFSjZj@SjbjWIjdjjf}rGS(jh]ji]jj]jk]jn]ujpKjr]rHSj{X TCI6630K2LrISrJS}rKS(jYjFSjZjDSubaubajdj$ubejdj$ubj$)rLS}rMS(jYUjf}rNS(jh]ji]jj]jk]jn]ujZjPjr]rOS(j$)rPS}rQS(jYUjf}rRS(jh]ji]jj]jk]jn]ujZjLSjr]rSSj)rTS}rUS(jYX K2G GP EVMrVSjZjPSjbjWIjdjjf}rWS(jh]ji]jj]jk]jn]ujpKjr]rXSj{X K2G GP EVMrYSrZS}r[S(jYjVSjZjTSubaubajdj$ubj$)r\S}r]S(jYUjf}r^S(jh]ji]jj]jk]jn]ujZjLSjr]r_Sj)r`S}raS(jYX0Texas Instruments XDS2xx USB Onboard Debug ProberbSjZj\SjbjWIjdjjf}rcS(jh]ji]jj]jk]jn]ujpKjr]rdSj{X0Texas Instruments XDS2xx USB Onboard Debug ProbereSrfS}rgS(jYjbSjZj`Subaubajdj$ubj$)rhS}riS(jYUjf}rjS(jh]ji]jj]jk]jn]ujZjLSjr]rkSj)rlS}rmS(jYX66AK2G02rnSjZjhSjbjWIjdjjf}roS(jh]ji]jj]jk]jn]ujpKjr]rpSj{X66AK2G02rqSrrS}rsS(jYjnSjZjlSubaubajdj$ubejdj$ubj$)rtS}ruS(jYUjf}rvS(jh]ji]jj]jk]jn]ujZjPjr]rwS(j$)rxS}ryS(jYUjf}rzS(jh]ji]jj]jk]jn]ujZjtSjr]r{Sj)r|S}r}S(jYX OMAPL137 EVMr~SjZjxSjbjWIjdjjf}rS(jh]ji]jj]jk]jn]ujpKjr]rSj{X OMAPL137 EVMrSrS}rS(jYj~SjZj|Subaubajdj$ubj$)rS}rS(jYUjf}rS(jh]ji]jj]jk]jn]ujZjtSjr]rSj)rS}rS(jYX#Spectrum Digital XDS510USB EmulatorrSjZjSjbjWIjdjjf}rS(jh]ji]jj]jk]jn]ujpKjr]rSj{X#Spectrum Digital XDS510USB EmulatorrSrS}rS(jYjSjZjSubaubajdj$ubj$)rS}rS(jYUjf}rS(jh]ji]jj]jk]jn]ujZjtSjr]rSj)rS}rS(jYX OMAPL137SKrSjZjSjbjWIjdjjf}rS(jh]ji]jj]jk]jn]ujpKjr]rSj{X OMAPL137SKrSrS}rS(jYjSjZjSubaubajdj$ubejdj$ubj$)rS}rS(jYUjf}rS(jh]ji]jj]jk]jn]ujZjPjr]rS(j$)rS}rS(jYUjf}rS(jh]ji]jj]jk]jn]ujZjSjr]rSj)rS}rS(jYX OMAPL138 LCDKrSjZjSjbjWIjdjjf}rS(jh]ji]jj]jk]jn]ujpKjr]rSj{X OMAPL138 LCDKrSrS}rS(jYjSjZjSubaubajdj$ubj$)rS}rS(jYUjf}rS(jh]ji]jj]jk]jn]ujZjSjr]rSj)rS}rS(jYXLExternal Emulator Supplied by User. EVM includes a TI 14 pin JTAG connector.rSjZjSjbjWIjdjjf}rS(jh]ji]jj]jk]jn]ujpKjr]rSj{XLExternal Emulator Supplied by User. EVM includes a TI 14 pin JTAG connector.rSrS}rS(jYjSjZjSubaubajdj$ubj$)rS}rS(jYUjf}rS(jh]ji]jj]jk]jn]ujZjSjr]rSj)rS}rS(jYX OMAPL138LCDKrSjZjSjbjWIjdjjf}rS(jh]ji]jj]jk]jn]ujpKjr]rSj{X OMAPL138LCDKrSrS}rS(jYjSjZjSubaubajdj$ubejdj$ubejdjy%ubejdjz%ubaubjZ)rS}rS(jYUjZjPjbjWIjdj]jf}rS(jh]ji]jj]jk]jn]ujpKjqhjr]rSj`)rS}rS(jYUjcKjZjSjbjWIjdjpjf}rS(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubj[)rS}rS(jYUjZjtOjbjWIjdjejf}rS(jh]ji]jj]jk]rSUsave-target-configurationrSajn]rShaujpKjqhjr]rS(jt)rS}rS(jYXSave target configurationrSjZjSjbjWIjdjxjf}rS(jh]ji]jj]jk]jn]ujpKjqhjr]rSj{XSave target configurationrSrS}rS(jYjSjZjSubaubj)rS}rS(jYXDNext, save the target configuration by pressing the **Save** button:rSjZjSjbjWIjdjjf}rS(jh]ji]jj]jk]jn]ujpKjqhjr]rS(j{X4Next, save the target configuration by pressing the rSrS}rS(jYX4Next, save the target configuration by pressing the jZjSubj)rS}rS(jYX**Save**jf}rS(jh]ji]jj]jk]jn]ujZjSjr]rSj{XSaverSrS}rS(jYUjZjSubajdjubj{X button:rSrS}rS(jYX button:jZjSubeubjB)rS}rS(jYX3.. Image:: ../images/CCS-GP437x-EVM-Save-Target.pngrSjZjSjbjWIjdjEjf}rS(UuriX-rtos/../images/CCS-GP437x-EVM-Save-Target.pngrSjk]jj]jh]ji]jH}rSU*jSsjn]ujpKjqhjr]ubjZ)rS}rS(jYUjZjSjbjWIjdj]jf}rS(jh]ji]jj]jk]jn]ujpKjqhjr]rSj`)rS}rS(jYUjcKjZjSjbjWIjdjpjf}rS(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubj[)rS}rS(jYUjZjtOjbjWIjdjejf}rS(jh]ji]jj]jk]rSUtest-target-configurationrSajn]rSjPaujpKjqhjr]rS(jt)rT}rT(jYXTest target configurationrTjZjSjbjWIjdjxjf}rT(jh]ji]jj]jk]jn]ujpKjqhjr]rTj{XTest target configurationrTrT}rT(jYjTjZjTubaubj)rT}r T(jYXNext, test the target configuration by pressing the **Test Connection** button. This will confirm that you have successfully created an emulator connection with your board.jZjSjbjWIjdjjf}r T(jh]ji]jj]jk]jn]ujpKjqhjr]r T(j{X4Next, test the target configuration by pressing the r Tr T}rT(jYX4Next, test the target configuration by pressing the jZjTubj)rT}rT(jYX**Test Connection**jf}rT(jh]ji]jj]jk]jn]ujZjTjr]rTj{XTest ConnectionrTrT}rT(jYUjZjTubajdjubj{Xe button. This will confirm that you have successfully created an emulator connection with your board.rTrT}rT(jYXe button. This will confirm that you have successfully created an emulator connection with your board.jZjTubeubjB)rT}rT(jYX/.. Image:: ../images/AM4-GP-test-connection.pngrTjZjSjbjWIjdjEjf}rT(UuriX)rtos/../images/AM4-GP-test-connection.pngrTjk]jj]jh]ji]jH}rTU*jTsjn]ujpKjqhjr]ubjZ)rT}r T(jYUjZjSjbjWIjdj]jf}r!T(jh]ji]jj]jk]jn]ujpMjqhjr]r"Tj`)r#T}r$T(jYUjcKjZjTjbjWIjdjpjf}r%T(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubj[)r&T}r'T(jYUjZjtOjbjWIjdjejf}r(T(jh]ji]jj]jk]r)TUview-target-configurationsr*Tajn]r+Tj aujpMjqhjr]r,T(jt)r-T}r.T(jYXView target configurationsr/TjZj&TjbjWIjdjxjf}r0T(jh]ji]jj]jk]jn]ujpMjqhjr]r1Tj{XView target configurationsr2Tr3T}r4T(jYj/TjZj-Tubaubj)r5T}r6T(jYX1From CCS, select "View -> Target Configurations":r7TjZj&TjbjWIjdjjf}r8T(jh]ji]jj]jk]jn]ujpMjqhjr]r9Tj{X1From CCS, select "View -> Target Configurations":r:Tr;T}rT(jYX3.. Image:: ../images/CCS-GP437x-EVM-View-Target.pngr?TjZj&TjbjWIjdjEjf}r@T(UuriX-rtos/../images/CCS-GP437x-EVM-View-Target.pngrATjk]jj]jh]ji]jH}rBTU*jATsjn]ujpMjqhjr]ubjZ)rCT}rDT(jYUjZj&TjbjWIjdj]jf}rET(jh]ji]jj]jk]jn]ujpMjqhjr]rFTj`)rGT}rHT(jYUjcKjZjCTjbjWIjdjpjf}rIT(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubj[)rJT}rKT(jYUjZjtOjbjWIjdjejf}rLT(jh]ji]jj]jk]rMTUlaunch-target-configurationrNTajn]rOThYaujpM jqhjr]rPT(jt)rQT}rRT(jYXLaunch target configurationrSTjZjJTjbjWIjdjxjf}rTT(jh]ji]jj]jk]jn]ujpM jqhjr]rUTj{XLaunch target configurationrVTrWT}rXT(jYjSTjZjQTubaubj)rYT}rZT(jYXOpen "User Defined" list and right click on the target configuration file that was just saved and select "Launch Selected Configuration":r[TjZjJTjbjWIjdjjf}r\T(jh]ji]jj]jk]jn]ujpM jqhjr]r]Tj{XOpen "User Defined" list and right click on the target configuration file that was just saved and select "Launch Selected Configuration":r^Tr_T}r`T(jYj[TjZjYTubaubjB)raT}rbT(jYX5.. Image:: ../images/CCS-GP437x-EVM-Launch-Target.pngrcTjZjJTjbjWIjdjEjf}rdT(UuriX/rtos/../images/CCS-GP437x-EVM-Launch-Target.pngreTjk]jj]jh]ji]jH}rfTU*jeTsjn]ujpMjqhjr]ubjZ)rgT}rhT(jYUjZjJTjbjWIjdj]jf}riT(jh]ji]jj]jk]jn]ujpMjqhjr]rjTj`)rkT}rlT(jYUjcKjZjgTjbjWIjdjpjf}rmT(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubj[)rnT}roT(jYUjZjtOjbjWIjdjejf}rpT(jh]ji]jj]jk]rqTUconnect-targetrrTajn]rsThaujpMjqhjr]rtT(jt)ruT}rvT(jYXConnect targetrwTjZjnTjbjWIjdjxjf}rxT(jh]ji]jj]jk]jn]ujpMjqhjr]ryTj{XConnect targetrzTr{T}r|T(jYjwTjZjuTubaubj)r}T}r~T(jYXmAfter launch, you can connect to a core. For GP AM437x EVM, select **Cortex A9** and select "Connect Target":jZjnTjbjWIjdjjf}rT(jh]ji]jj]jk]jn]ujpMjqhjr]rT(j{XCAfter launch, you can connect to a core. For GP AM437x EVM, select rTrT}rT(jYXCAfter launch, you can connect to a core. For GP AM437x EVM, select jZj}Tubj)rT}rT(jYX **Cortex A9**jf}rT(jh]ji]jj]jk]jn]ujZj}Tjr]rTj{X Cortex A9rTrT}rT(jYUjZjTubajdjubj{X and select "Connect Target":rTrT}rT(jYX and select "Connect Target":jZj}TubeubjB)rT}rT(jYX8.. Image:: ../images/CCS-GP437x-EVM-Connnect-Target.png jZjnTjbjWIjdjEjf}rT(UuriX1rtos/../images/CCS-GP437x-EVM-Connnect-Target.pngrTjk]jj]jh]ji]jH}rTU*jTsjn]ujpMjqhjr]ubjZ)rT}rT(jYUjZjnTjbjWIjdj]jf}rT(jh]ji]jj]jk]jn]ujpMjqhjr]rTj`)rT}rT(jYUjcKjZjTjbjWIjdjpjf}rT(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubj[)rT}rT(jYUjZjtOjbjWIjdjejf}rT(jh]ji]jj]jk]rTUsuccessrTajn]rThaujpMjqhjr]rT(jt)rT}rT(jYXSuccess!rTjZjTjbjWIjdjxjf}rT(jh]ji]jj]jk]jn]ujpMjqhjr]rTj{XSuccess!rTrT}rT(jYjTjZjTubaubj)rT}rT(jYXAfter connecting to target, check the console for status. Typically, the end of the configuration will indicate success or failure. For GP AM437x EVM, you will see the message "AM437x GP EVM Initialization is Done":rTjZjTjbjWIjdjjf}rT(jh]ji]jj]jk]jn]ujpMjqhjr]rTj{XAfter connecting to target, check the console for status. Typically, the end of the configuration will indicate success or failure. For GP AM437x EVM, you will see the message "AM437x GP EVM Initialization is Done":rTrT}rT(jYjTjZjTubaubjB)rT}rT(jYX2.. Image:: ../images/CCS-GP437x-EVM-Run-Target.pngrTjZjTjbjWIjdjEjf}rT(UuriX,rtos/../images/CCS-GP437x-EVM-Run-Target.pngrTjk]jj]jh]ji]jH}rTU*jTsjn]ujpM!jqhjr]ubjZ)rT}rT(jYUjZjTjbjWIjdj]jf}rT(jh]ji]jj]jk]jn]ujpM"jqhjr]rTj`)rT}rT(jYUjcKjZjTjbjWIjdjpjf}rT(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubeubj[)rT}rT(jYUjZjjbjWIjdjejf}rT(jh]ji]jj]jk]rTUadditional-notes-for-am57xrTajn]rThaujpM$jqhjr]rT(jt)rT}rT(jYXAdditional Notes for AM57xrTjZjTjbjWIjdjxjf}rT(jh]ji]jj]jk]jn]ujpM$jqhjr]rTj{XAdditional Notes for AM57xrTrT}rT(jYjTjZjTubaubj[)rT}rT(jYUjZjTjbjWIjdjejf}rT(jh]ji]jj]jk]rTUconnect-to-am57x-slave-coresrTajn]rThaujpM'jqhjr]rT(jt)rT}rT(jYXConnect to AM57x Slave CoresrTjZjTjbjWIjdjxjf}rT(jh]ji]jj]jk]jn]ujpM'jqhjr]rTj{XConnect to AM57x Slave CoresrTrT}rT(jYjTjZjTubaubj)rT}rT(jYXAfter connecting to the boot master core -- typically the ARM core -- you may need to connect to a slave core in order to run code. Depending on your SOC, the slave core can berTjZjTjbjWIjdjjf}rT(jh]ji]jj]jk]jn]ujpM)jqhjr]rTj{XAfter connecting to the boot master core -- typically the ARM core -- you may need to connect to a slave core in order to run code. Depending on your SOC, the slave core can berTrT}rT(jYjTjZjTubaubjC)rT}rT(jYUjZjTjbjWIjdj`jf}rT(jGX-jk]jj]jh]ji]jn]ujpM-jqhjr]rT(j/)rT}rT(jYXDSP C66xrTjZjTjbjWIjdj2jf}rT(jh]ji]jj]jk]jn]ujpNjqhjr]rTj)rT}rT(jYjTjZjTjbjWIjdjjf}rT(jh]ji]jj]jk]jn]ujpM-jr]rTj{XDSP C66xrTrT}rT(jYjTjZjTubaubaubj/)rT}rT(jYXARM M4rTjZjTjbjWIjdj2jf}rT(jh]ji]jj]jk]jn]ujpNjqhjr]rTj)rT}rT(jYjTjZjTjbjWIjdjjf}rT(jh]ji]jj]jk]jn]ujpM.jr]rTj{XARM M4rTrT}rT(jYjTjZjTubaubaubj/)rU}rU(jYXPRUSSrUjZjTjbjWIjdj2jf}rU(jh]ji]jj]jk]jn]ujpNjqhjr]rUj)rU}rU(jYjUjZjUjbjWIjdjjf}rU(jh]ji]jj]jk]jn]ujpM/jr]rUj{XPRUSSr Ur U}r U(jYjUjZjUubaubaubj/)r U}r U(jYXIVAHD jZjTjbjWIjdj2jf}rU(jh]ji]jj]jk]jn]ujpNjqhjr]rUj)rU}rU(jYXIVAHDrUjZj UjbjWIjdjjf}rU(jh]ji]jj]jk]jn]ujpM0jr]rUj{XIVAHDrUrU}rU(jYjUjZjUubaubaubeubj)rU}rU(jYXTypically the slave cores will wait in reset state until the master core wakes up the slave core to run code. To connect to the slave core on AM57x, go to **Scripts** menu in CCS Debug View and under **AM572x MULTICORE Initialization** enable the corresponding sub system clock. For example, enable ``DSP11SSClkEnable_API`` for the first DSP core. After running the clock enable option, you can connect to the core.jZjTjbjWIjdjjf}rU(jh]ji]jj]jk]jn]ujpM2jqhjr]rU(j{XTypically the slave cores will wait in reset state until the master core wakes up the slave core to run code. To connect to the slave core on AM57x, go to rUrU}rU(jYXTypically the slave cores will wait in reset state until the master core wakes up the slave core to run code. To connect to the slave core on AM57x, go to jZjUubj)rU}r U(jYX **Scripts**jf}r!U(jh]ji]jj]jk]jn]ujZjUjr]r"Uj{XScriptsr#Ur$U}r%U(jYUjZjUubajdjubj{X" menu in CCS Debug View and under r&Ur'U}r(U(jYX" menu in CCS Debug View and under jZjUubj)r)U}r*U(jYX#**AM572x MULTICORE Initialization**jf}r+U(jh]ji]jj]jk]jn]ujZjUjr]r,Uj{XAM572x MULTICORE Initializationr-Ur.U}r/U(jYUjZj)Uubajdjubj{X@ enable the corresponding sub system clock. For example, enable r0Ur1U}r2U(jYX@ enable the corresponding sub system clock. For example, enable jZjUubji')r3U}r4U(jYX``DSP11SSClkEnable_API``jf}r5U(jh]ji]jj]jk]jn]ujZjUjr]r6Uj{XDSP11SSClkEnable_APIr7Ur8U}r9U(jYUjZj3Uubajdjq'ubj{X\ for the first DSP core. After running the clock enable option, you can connect to the core.r:Ur;U}rU(jYX).. Image:: ../images/Multicore-Enable.jpgr?UjZjTjbjWIjdjEjf}r@U(UuriX#rtos/../images/Multicore-Enable.jpgrAUjk]jj]jh]ji]jH}rBUU*jAUsjn]ujpM9jqhjr]ubjZ)rCU}rDU(jYUjZjTjbjWIjdj]jf}rEU(jh]ji]jj]jk]jn]ujpM:jqhjr]rFUj`)rGU}rHU(jYUjcKjZjCUjbjWIjdjpjf}rIU(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubj[)rJU}rKU(jYUjZjTjbjWIjdjejf}rLU(jh]ji]jj]jk]rMUU%timer-suspend-control-options-for-dsprNUajn]rOUhqaujpM<jqhjr]rPU(jt)rQU}rRU(jYX%Timer Suspend Control Options for DSPrSUjZjJUjbjWIjdjxjf}rTU(jh]ji]jj]jk]jn]ujpM<jqhjr]rUUj{X%Timer Suspend Control Options for DSPrVUrWU}rXU(jYjSUjZjQUubaubj)rYU}rZU(jYX+On AM57xx devices, all the timers on the chip have their suspend control signal routed to the A15 core. Which means that if any of the slave cores are using these timers, the timers will continue to run even when the slave core has been paused. The timer will only pause when the A15 core is halted.r[UjZjJUjbjWIjdjjf}r\U(jh]ji]jj]jk]jn]ujpM>jqhjr]r]Uj{X+On AM57xx devices, all the timers on the chip have their suspend control signal routed to the A15 core. Which means that if any of the slave cores are using these timers, the timers will continue to run even when the slave core has been paused. The timer will only pause when the A15 core is halted.r^Ur_U}r`U(jYj[UjZjYUubaubj)raU}rbU(jYXThis is confusing while debugging code on slave cores if you are relying on timer for logging, inserting delays or if the timer keeps firing interrupts even when the core is halted. One such scenario occurs with *GPtimer5* when DSP developers are using SYS/BIOS. The OS uses *GPtimer5* on the DSP and forces a frequency check to confirm the timer configuration, however the OS can't gain access to the timer due to the hook up of the suspend control signals.jZjJUjbjWIjdjjf}rcU(jh]ji]jj]jk]jn]ujpMDjqhjr]rdU(j{XThis is confusing while debugging code on slave cores if you are relying on timer for logging, inserting delays or if the timer keeps firing interrupts even when the core is halted. One such scenario occurs with reUrfU}rgU(jYXThis is confusing while debugging code on slave cores if you are relying on timer for logging, inserting delays or if the timer keeps firing interrupts even when the core is halted. One such scenario occurs with jZjaUubj')rhU}riU(jYX *GPtimer5*jf}rjU(jh]ji]jj]jk]jn]ujZjaUjr]rkUj{XGPtimer5rlUrmU}rnU(jYUjZjhUubajdj'ubj{X5 when DSP developers are using SYS/BIOS. The OS uses roUrpU}rqU(jYX5 when DSP developers are using SYS/BIOS. The OS uses jZjaUubj')rrU}rsU(jYX *GPtimer5*jf}rtU(jh]ji]jj]jk]jn]ujZjaUjr]ruUj{XGPtimer5rvUrwU}rxU(jYUjZjrUubajdj'ubj{X on the DSP and forces a frequency check to confirm the timer configuration, however the OS can't gain access to the timer due to the hook up of the suspend control signals.ryUrzU}r{U(jYX on the DSP and forces a frequency check to confirm the timer configuration, however the OS can't gain access to the timer due to the hook up of the suspend control signals.jZjaUubeubj)r|U}r}U(jYXDue to this issue the SYS/BIOS developers will need to configure an additional CCS configuration check to connect the GPTimer suspend control signal to the DSP as shown in the image below:r~UjZjJUjbjWIjdjjf}rU(jh]ji]jj]jk]jn]ujpMLjqhjr]rUj{XDue to this issue the SYS/BIOS developers will need to configure an additional CCS configuration check to connect the GPTimer suspend control signal to the DSP as shown in the image below:rUrU}rU(jYj~UjZj|UubaubjB)rU}rU(jYX-.. Image:: ../images/GPtimer5_DSPConnect.png jZjJUjbjWIjdjEjf}rU(UuriX&rtos/../images/GPtimer5_DSPConnect.pngrUjk]jj]jh]ji]jH}rUU*jUsjn]ujpMQjqhjr]ubjZ)rU}rU(jYUjZjJUjbjWIjdj]jf}rU(jh]ji]jj]jk]jn]ujpMRjqhjr]rUj`)rU}rU(jYUjcKjZjUjbjWIjdjpjf}rU(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubeubjTIeubjbjWIjdjejf}rU(jh]ji]jj]jk]rUU'ccs-and-sdk-installed-in-same-directoryrUajn]rUhaujpKjqhjr]rU(jt)rU}rU(jYX'CCS and SDK installed in same directoryrUjZjjbjWIjdjxjf}rU(jh]ji]jj]jk]jn]ujpKjqhjr]rUj{X'CCS and SDK installed in same directoryrUrU}rU(jYjUjZjUubaubj)rU}rU(jYXAfter installing the Processor-SDK RTOS, start CCS and it will automatically detect the newly installed components (*products*):jZjjbjWIjdjjf}rU(jh]ji]jj]jk]jn]ujpKjqhjr]rU(j{XtAfter installing the Processor-SDK RTOS, start CCS and it will automatically detect the newly installed components (rUrU}rU(jYXtAfter installing the Processor-SDK RTOS, start CCS and it will automatically detect the newly installed components (jZjUubj')rU}rU(jYX *products*jf}rU(jh]ji]jj]jk]jn]ujZjUjr]rUj{XproductsrUrU}rU(jYUjZjUubajdj'ubj{X):rUrU}rU(jYX):jZjUubeubjB)rU}rU(jYX0.. Image:: ../images/CCS-discovered-products.pngrUjZjjbjWIjdjEjf}rU(UuriX*rtos/../images/CCS-discovered-products.pngrUjk]jj]jh]ji]jH}rUU*jUsjn]ujpKjqhjr]ubjZ)rU}rU(jYUjZjjbjWIjdj]jf}rU(jh]ji]jj]jk]jn]ujpKjqhjr]rUj`)rU}rU(jYUjcKjZjUjbjWIjdjpjf}rU(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubjbjWIjdj jf}rU(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineKUtypej ujpKjqhjr]rUj)rU}rU(jYX?Explicit markup ends without a blank line; unexpected unindent.jf}rU(jh]ji]jj]jk]jn]ujZjjr]rUj{X?Explicit markup ends without a blank line; unexpected unindent.rUrU}rU(jYUjZjUubajdjubaubjV)rU}rU(jYUjZjjbjWIjdj jf}rU(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineKUtypej ujpKjqhjr]rUj)rU}rU(jYX%Line block ends without a blank line.jf}rU(jh]ji]jj]jk]jn]ujZjUjr]rUj{X%Line block ends without a blank line.rUrU}rU(jYUjZjUubajdjubaubjV)rU}rU(jYUjZjNjbjWIjdj jf}rU(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineK&Utypej ujpK%jqhjr]rUj)rU}rU(jYX?Explicit markup ends without a blank line; unexpected unindent.jf}rU(jh]ji]jj]jk]jn]ujZjUjr]rUj{X?Explicit markup ends without a blank line; unexpected unindent.rUrU}rU(jYUjZjUubajdjubaubjV)rU}rU(jYUjZjNjbjWIjdj jf}rU(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineK'Utypej ujpK&jqhjr]rUj)rU}rU(jYX%Line block ends without a blank line.jf}rU(jh]ji]jj]jk]jn]ujZjUjr]rUj{X%Line block ends without a blank line.rUrU}rU(jYUjZjUubajdjubaubjV)rU}rU(jYUjZjNjbjWIjdj jf}rU(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineK/Utypej ujpK.jqhjr]rUj)rU}rU(jYX?Explicit markup ends without a blank line; unexpected unindent.jf}rU(jh]ji]jj]jk]jn]ujZjUjr]rUj{X?Explicit markup ends without a blank line; unexpected unindent.rUrU}rU(jYUjZjUubajdjubaubjV)rU}rU(jYUjZjNjbjWIjdj jf}rU(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineK0Utypej ujpK/jqhjr]rUj)rU}rU(jYX%Line block ends without a blank line.jf}rU(jh]ji]jj]jk]jn]ujZjUjr]rUj{X%Line block ends without a blank line.rUrU}rU(jYUjZjUubajdjubaubjV)rU}rU(jYUjZjNjbjWIjdj jf}rU(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineK7Utypej ujpK6jqhjr]rUj)rU}rV(jYX?Explicit markup ends without a blank line; unexpected unindent.jf}rV(jh]ji]jj]jk]jn]ujZjUjr]rVj{X?Explicit markup ends without a blank line; unexpected unindent.rVrV}rV(jYUjZjUubajdjubaubjV)rV}rV(jYUjZjNjbjWIjdj jf}rV(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineK8Utypej ujpK7jqhjr]r Vj)r V}r V(jYX%Line block ends without a blank line.jf}r V(jh]ji]jj]jk]jn]ujZjVjr]r Vj{X%Line block ends without a blank line.rVrV}rV(jYUjZj VubajdjubaubjV)rV}rV(jYUjZjOjbjWIjdj jf}rV(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineK?Utypej ujpK>jqhjr]rVj)rV}rV(jYX?Explicit markup ends without a blank line; unexpected unindent.jf}rV(jh]ji]jj]jk]jn]ujZjVjr]rVj{X?Explicit markup ends without a blank line; unexpected unindent.rVrV}rV(jYUjZjVubajdjubaubjV)rV}rV(jYUjZjOjbjWIjdj jf}rV(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineK~Utypej ujpK}jqhjr]rVj)r V}r!V(jYX?Explicit markup ends without a blank line; unexpected unindent.jf}r"V(jh]ji]jj]jk]jn]ujZjVjr]r#Vj{X?Explicit markup ends without a blank line; unexpected unindent.r$Vr%V}r&V(jYUjZj VubajdjubaubjV)r'V}r(V(jYUjZjOjbjWIjdj jf}r)V(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineKUtypej ujpK~jqhjr]r*Vj)r+V}r,V(jYX%Line block ends without a blank line.jf}r-V(jh]ji]jj]jk]jn]ujZj'Vjr]r.Vj{X%Line block ends without a blank line.r/Vr0V}r1V(jYUjZj+VubajdjubaubjV)r2V}r3V(jYUjZjPjbjWIjdj jf}r4V(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineKUtypej ujpKjqhjr]r5Vj)r6V}r7V(jYX?Explicit markup ends without a blank line; unexpected unindent.jf}r8V(jh]ji]jj]jk]jn]ujZj2Vjr]r9Vj{X?Explicit markup ends without a blank line; unexpected unindent.r:Vr;V}rV(jYUjZjPjbjWIjdj jf}r?V(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineKUtypej ujpKjqhjr]r@Vj)rAV}rBV(jYX%Line block ends without a blank line.jf}rCV(jh]ji]jj]jk]jn]ujZj=Vjr]rDVj{X%Line block ends without a blank line.rEVrFV}rGV(jYUjZjAVubajdjubaubjV)rHV}rIV(jYUjZjPjbjWIjdj jf}rJV(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineKUtypej ujpKjqhjr]rKVj)rLV}rMV(jYX%Line block ends without a blank line.jf}rNV(jh]ji]jj]jk]jn]ujZjHVjr]rOVj{X%Line block ends without a blank line.rPVrQV}rRV(jYUjZjLVubajdjubaubjV)rSV}rTV(jYUjZjSjbjWIjdj jf}rUV(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineKUtypej ujpKjqhjr]rVVj)rWV}rXV(jYX?Explicit markup ends without a blank line; unexpected unindent.jf}rYV(jh]ji]jj]jk]jn]ujZjSVjr]rZVj{X?Explicit markup ends without a blank line; unexpected unindent.r[Vr\V}r]V(jYUjZjWVubajdjubaubjV)r^V}r_V(jYUjZjSjbjWIjdj jf}r`V(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineKUtypej ujpKjqhjr]raVj)rbV}rcV(jYX%Line block ends without a blank line.jf}rdV(jh]ji]jj]jk]jn]ujZj^Vjr]reVj{X%Line block ends without a blank line.rfVrgV}rhV(jYUjZjbVubajdjubaubjV)riV}rjV(jYUjZjSjbjWIjdj jf}rkV(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineMUtypej ujpKjqhjr]rlVj)rmV}rnV(jYX?Explicit markup ends without a blank line; unexpected unindent.jf}roV(jh]ji]jj]jk]jn]ujZjiVjr]rpVj{X?Explicit markup ends without a blank line; unexpected unindent.rqVrrV}rsV(jYUjZjmVubajdjubaubjV)rtV}ruV(jYUjZjSjbjWIjdj jf}rvV(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineMUtypej ujpMjqhjr]rwVj)rxV}ryV(jYX%Line block ends without a blank line.jf}rzV(jh]ji]jj]jk]jn]ujZjtVjr]r{Vj{X%Line block ends without a blank line.r|Vr}V}r~V(jYUjZjxVubajdjubaubjV)rV}rV(jYUjZj&TjbjWIjdj jf}rV(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineMUtypej ujpMjqhjr]rVj)rV}rV(jYX?Explicit markup ends without a blank line; unexpected unindent.jf}rV(jh]ji]jj]jk]jn]ujZjVjr]rVj{X?Explicit markup ends without a blank line; unexpected unindent.rVrV}rV(jYUjZjVubajdjubaubjV)rV}rV(jYUjZj&TjbjWIjdj jf}rV(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineMUtypej ujpMjqhjr]rVj)rV}rV(jYX%Line block ends without a blank line.jf}rV(jh]ji]jj]jk]jn]ujZjVjr]rVj{X%Line block ends without a blank line.rVrV}rV(jYUjZjVubajdjubaubjV)rV}rV(jYUjZjJTjbjWIjdj jf}rV(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineMUtypej ujpMjqhjr]rVj)rV}rV(jYX?Explicit markup ends without a blank line; unexpected unindent.jf}rV(jh]ji]jj]jk]jn]ujZjVjr]rVj{X?Explicit markup ends without a blank line; unexpected unindent.rVrV}rV(jYUjZjVubajdjubaubjV)rV}rV(jYUjZjJTjbjWIjdj jf}rV(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineMUtypej ujpMjqhjr]rVj)rV}rV(jYX%Line block ends without a blank line.jf}rV(jh]ji]jj]jk]jn]ujZjVjr]rVj{X%Line block ends without a blank line.rVrV}rV(jYUjZjVubajdjubaubjV)rV}rV(jYUjZjTjbjWIjdj jf}rV(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineM"Utypej ujpM!jqhjr]rVj)rV}rV(jYX?Explicit markup ends without a blank line; unexpected unindent.jf}rV(jh]ji]jj]jk]jn]ujZjVjr]rVj{X?Explicit markup ends without a blank line; unexpected unindent.rVrV}rV(jYUjZjVubajdjubaubjV)rV}rV(jYUjZjTjbjWIjdj jf}rV(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineM#Utypej ujpM"jqhjr]rVj)rV}rV(jYX%Line block ends without a blank line.jf}rV(jh]ji]jj]jk]jn]ujZjVjr]rVj{X%Line block ends without a blank line.rVrV}rV(jYUjZjVubajdjubaubjV)rV}rV(jYUjZjTjbjWIjdj jf}rV(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineM:Utypej ujpM9jqhjr]rVj)rV}rV(jYX?Explicit markup ends without a blank line; unexpected unindent.jf}rV(jh]ji]jj]jk]jn]ujZjVjr]rVj{X?Explicit markup ends without a blank line; unexpected unindent.rVrV}rV(jYUjZjVubajdjubaubjV)rV}rV(jYUjZjTjbjWIjdj jf}rV(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineM;Utypej ujpM:jqhjr]rVj)rV}rV(jYX%Line block ends without a blank line.jf}rV(jh]ji]jj]jk]jn]ujZjVjr]rVj{X%Line block ends without a blank line.rVrV}rV(jYUjZjVubajdjubaubjV)rV}rV(jYUjZjTIjbXcinternal padding after source/rtos/How_to_Guides/Host/Setup/Setup_CCS_for_EVM_and_PSDK_RTOS.rst.incrVjdj jf}rV(jh]UlevelKjk]jj]UsourcejWIji]jn]UlineMoUtypej ujpMqjqhjr]rV(j)rV}rV(jYX;Content block expected for the "raw" directive; none found.jf}rV(jh]ji]jj]jk]jn]ujZjVjr]rVj{X;Content block expected for the "raw" directive; none found.rVrV}rV(jYUjZjVubajdjubj)rV}rV(jYX.. raw:: html jf}rV(jjjk]jj]jh]ji]jn]ujZjVjr]rVj{X.. raw:: html rVrV}rV(jYUjZjVubajdjubeubjV)rV}rV(jYUjZj9JjbjOIjdj jf}rV(jh]UlevelKjk]jj]rVj?JaUsourcejOIji]jn]UlineKUtypej ujpKjqhjr]rVj)rV}rV(jYX+Duplicate implicit target name: "overview".jf}rV(jh]ji]jj]jk]jn]ujZjVjr]rVj{X+Duplicate implicit target name: "overview".rVrV}rV(jYUjZjVubajdjubaubjV)rV}rV(jYUjZjMjbX`internal padding after source/rtos/How_to_Guides/Host/Setup/Update_ENV_for_a_Custom_Path.rst.incrVjdj jf}rV(jh]UlevelKjk]jj]UsourcejOIji]jn]UlineMUtypej ujpMjqhjr]rV(j)rV}rV(jYX;Content block expected for the "raw" directive; none found.jf}rV(jh]ji]jj]jk]jn]ujZjVjr]rVj{X;Content block expected for the "raw" directive; none found.rVrW}rW(jYUjZjVubajdjubj)rW}rW(jYX.. raw:: html jf}rW(jjjk]jj]jh]ji]jn]ujZjVjr]rWj{X.. raw:: html rWrW}rW(jYUjZjWubajdjubeubjV)r W}r W(jYUjf}r W(jh]UlevelKjk]jj]Usourcej ji]jn]UlineK Utypej ujr]r W(j)r W}rW(jYUjf}rW(jh]ji]jj]jk]jn]ujZj Wjr]rWj{XTitle underline too short.rWrW}rW(jYUjZj Wubajdjubj)rW}rW(jYX`RTSC Diagnostics: Understanding XDC build errors ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^jf}rW(jjjk]jj]jh]ji]jn]ujZj Wjr]rWj{X`RTSC Diagnostics: Understanding XDC build errors ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^rWrW}rW(jYUjZjWubajdjubejdj ubjV)rW}rW(jYUjZjijbj jdj jf}rW(jh]UlevelKjk]jj]Usourcej ji]jn]UlineK Utypej ujpK jqhjr]rW(j)rW}r W(jYXTitle underline too short.jf}r!W(jh]ji]jj]jk]jn]ujZjWjr]r"Wj{XTitle underline too short.r#Wr$W}r%W(jYUjZjWubajdjubj)r&W}r'W(jYX`RTSC Diagnostics: Understanding XDC build errors ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^jf}r(W(jjjk]jj]jh]ji]jn]ujZjWjr]r)Wj{X`RTSC Diagnostics: Understanding XDC build errors ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^r*Wr+W}r,W(jYUjZj&WubajdjubeubjV)r-W}r.W(jYUjZjjbj jdj jf}r/W(jh]UlevelKjk]jj]Usourcej ji]jn]UlineK2Utypej ujpK2jqhjr]r0Wj)r1W}r2W(jYXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.jf}r3W(jh]ji]jj]jk]jn]ujZj-Wjr]r4Wj{XfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.r5Wr6W}r7W(jYUjZj1WubajdjubaubjV)r8W}r9W(jYUjZjjbj jdj jf}r:W(jh]UlevelKjk]jj]Usourcej ji]jn]UlineKjUtypej ujpKjjqhjr]r;Wj)rW(jh]ji]jj]jk]jn]ujZj8Wjr]r?Wj{XfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.r@WrAW}rBW(jYUjZjXj{XfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.r?Xr@X}rAX(jYUjZj;XubajdjubaubjV)rBX}rCX(jYUjZjjbj jdj jf}rDX(jh]UlevelKjk]jj]Usourcej ji]jn]UlineKUtypej ujpKjqhjr]rEXj)rFX}rGX(jYXUnexpected indentation.jf}rHX(jh]ji]jj]jk]jn]ujZjBXjr]rIXj{XUnexpected indentation.rJXrKX}rLX(jYUjZjFXubajdjubaubjV)rMX}rNX(jYUjZjjbj jdj jf}rOX(jh]UlevelKjk]jj]Usourcej ji]jn]UlineM Utypej ujpM jqhjr]rPXj)rQX}rRX(jYX=Literal block ends without a blank line; unexpected unindent.jf}rSX(jh]ji]jj]jk]jn]ujZjMXjr]rTXj{X=Literal block ends without a blank line; unexpected unindent.rUXrVX}rWX(jYUjZjQXubajdjubaubjV)rXX}rYX(jYUjZjjbj jdj jf}rZX(jh]UlevelKjk]jj]Usourcej ji]jn]UlineM3Utypej ujpM3jqhjr]r[Xj)r\X}r]X(jYXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.jf}r^X(jh]ji]jj]jk]jn]ujZjXXjr]r_Xj{XfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.r`XraX}rbX(jYUjZj\XubajdjubaubjV)rcX}rdX(jYUjZjjbj jdj jf}reX(jh]UlevelKjk]jj]Usourcej ji]jn]UlineM4Utypej ujpM3jqhjr]rfXj)rgX}rhX(jYXUnexpected indentation.jf}riX(jh]ji]jj]jk]jn]ujZjcXjr]rjXj{XUnexpected indentation.rkXrlX}rmX(jYUjZjgXubajdjubaubjV)rnX}roX(jYUjZjjbj jdj jf}rpX(jh]UlevelKjk]jj]Usourcej ji]jn]UlineM5Utypej ujpM4jqhjr]rqXj)rrX}rsX(jYX=Literal block ends without a blank line; unexpected unindent.jf}rtX(jh]ji]jj]jk]jn]ujZjnXjr]ruXj{X=Literal block ends without a blank line; unexpected unindent.rvXrwX}rxX(jYUjZjrXubajdjubaubjV)ryX}rzX(jYUjZjjbj jdj jf}r{X(jh]UlevelKjk]jj]Usourcej ji]jn]UlineM6Utypej ujpM5jqhjr]r|Xj)r}X}r~X(jYX%Line block ends without a blank line.jf}rX(jh]ji]jj]jk]jn]ujZjyXjr]rXj{X%Line block ends without a blank line.rXrX}rX(jYUjZj}XubajdjubaubjV)rX}rX(jYUjZj<jbj jdj jf}rX(jh]UlevelKjk]jj]Usourcej ji]jn]UlineM<Utypej ujpM<jqhjr]rXj)rX}rX(jYXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.jf}rX(jh]ji]jj]jk]jn]ujZjXjr]rXj{XfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rXrX}rX(jYUjZjXubajdjubaubjV)rX}rX(jYUjZj<jbj jdj jf}rX(jh]UlevelKjk]jj]Usourcej ji]jn]UlineM=Utypej ujpM<jqhjr]rXj)rX}rX(jYXUnexpected indentation.jf}rX(jh]ji]jj]jk]jn]ujZjXjr]rXj{XUnexpected indentation.rXrX}rX(jYUjZjXubajdjubaubjV)rX}rX(jYUjZj<jbj jdj jf}rX(jh]UlevelKjk]jj]Usourcej ji]jn]UlineM?Utypej ujpM>jqhjr]rXj)rX}rX(jYX=Literal block ends without a blank line; unexpected unindent.jf}rX(jh]ji]jj]jk]jn]ujZjXjr]rXj{X=Literal block ends without a blank line; unexpected unindent.rXrX}rX(jYUjZjXubajdjubaubjV)rX}rX(jYUjZj<jbj jdj jf}rX(jh]UlevelKjk]jj]Usourcej ji]jn]UlineM@Utypej ujpM?jqhjr]rXj)rX}rX(jYX%Line block ends without a blank line.jf}rX(jh]ji]jj]jk]jn]ujZjXjr]rXj{X%Line block ends without a blank line.rXrX}rX(jYUjZjXubajdjubaubjV)rX}rX(jYUjZj<jbj jdj jf}rX(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMFUtypej ujpMFjqhjr]rXj)rX}rX(jYXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.jf}rX(jh]ji]jj]jk]jn]ujZjXjr]rXj{XfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rXrX}rX(jYUjZjXubajdjubaubjV)rX}rX(jYUjZj<jbj jdj jf}rX(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMGUtypej ujpMFjqhjr]rXj)rX}rX(jYXUnexpected indentation.jf}rX(jh]ji]jj]jk]jn]ujZjXjr]rXj{XUnexpected indentation.rXrX}rX(jYUjZjXubajdjubaubjV)rX}rX(jYUjZj<jbj jdj jf}rX(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMIUtypej ujpMHjqhjr]rXj)rX}rX(jYX=Literal block ends without a blank line; unexpected unindent.jf}rX(jh]ji]jj]jk]jn]ujZjXjr]rXj{X=Literal block ends without a blank line; unexpected unindent.rXrX}rX(jYUjZjXubajdjubaubjV)rX}rX(jYUjZjjbj jdj jf}rX(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMSUtypej ujpMSjqhjr]rXj)rX}rX(jYXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.jf}rX(jh]ji]jj]jk]jn]ujZjXjr]rXj{XfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rXrX}rX(jYUjZjXubajdjubaubjV)rX}rX(jYUjZjjbj jdj jf}rX(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMTUtypej ujpMSjqhjr]rXj)rX}rX(jYXUnexpected indentation.jf}rX(jh]ji]jj]jk]jn]ujZjXjr]rXj{XUnexpected indentation.rXrX}rX(jYUjZjXubajdjubaubjV)rX}rX(jYUjZjjbj jdj jf}rX(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMWUtypej ujpMVjqhjr]rXj)rX}rX(jYX=Literal block ends without a blank line; unexpected unindent.jf}rX(jh]ji]jj]jk]jn]ujZjXjr]rXj{X=Literal block ends without a blank line; unexpected unindent.rXrX}rX(jYUjZjXubajdjubaubjV)rX}rX(jYUjZjjbj jdj jf}rX(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMXUtypej ujpMWjqhjr]rXj)rX}rX(jYX%Line block ends without a blank line.jf}rX(jh]ji]jj]jk]jn]ujZjXjr]rXj{X%Line block ends without a blank line.rXrX}rX(jYUjZjXubajdjubaubjV)rX}rX(jYUjZjjbj jdj jf}rX(jh]UlevelKjk]jj]Usourcej ji]jn]UlineM]Utypej ujpM]jqhjr]rYj)rY}rY(jYXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.jf}rY(jh]ji]jj]jk]jn]ujZjXjr]rYj{XfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rYrY}rY(jYUjZjYubajdjubaubjV)rY}r Y(jYUjZjjbj jdj jf}r Y(jh]UlevelKjk]jj]Usourcej ji]jn]UlineM^Utypej ujpM]jqhjr]r Yj)r Y}r Y(jYXUnexpected indentation.jf}rY(jh]ji]jj]jk]jn]ujZjYjr]rYj{XUnexpected indentation.rYrY}rY(jYUjZj YubajdjubaubjV)rY}rY(jYUjZjjbj jdj jf}rY(jh]UlevelKjk]jj]Usourcej ji]jn]UlineM_Utypej ujpM^jqhjr]rYj)rY}rY(jYX=Literal block ends without a blank line; unexpected unindent.jf}rY(jh]ji]jj]jk]jn]ujZjYjr]rYj{X=Literal block ends without a blank line; unexpected unindent.rYrY}rY(jYUjZjYubajdjubaubjV)rY}rY(jYUjZjjbj jdj jf}r Y(jh]UlevelKjk]jj]Usourcej ji]jn]UlineM`Utypej ujpM_jqhjr]r!Yj)r"Y}r#Y(jYX%Line block ends without a blank line.jf}r$Y(jh]ji]jj]jk]jn]ujZjYjr]r%Yj{X%Line block ends without a blank line.r&Yr'Y}r(Y(jYUjZj"YubajdjubaubjV)r)Y}r*Y(jYUjZj jbj jdj jf}r+Y(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMlUtypej ujpMljqhjr]r,Yj)r-Y}r.Y(jYXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.jf}r/Y(jh]ji]jj]jk]jn]ujZj)Yjr]r0Yj{XfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.r1Yr2Y}r3Y(jYUjZj-YubajdjubaubjV)r4Y}r5Y(jYUjZj jbj jdj jf}r6Y(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMmUtypej ujpMljqhjr]r7Yj)r8Y}r9Y(jYXUnexpected indentation.jf}r:Y(jh]ji]jj]jk]jn]ujZj4Yjr]r;Yj{XUnexpected indentation.rY(jYUjZj8YubajdjubaubjV)r?Y}r@Y(jYUjZj jbj jdj jf}rAY(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMoUtypej ujpMnjqhjr]rBYj)rCY}rDY(jYX=Literal block ends without a blank line; unexpected unindent.jf}rEY(jh]ji]jj]jk]jn]ujZj?Yjr]rFYj{X=Literal block ends without a blank line; unexpected unindent.rGYrHY}rIY(jYUjZjCYubajdjubaubjV)rJY}rKY(jYUjZjtjbj jdj jf}rLY(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMUtypej ujpMjqhjr]rMYj)rNY}rOY(jYXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.jf}rPY(jh]ji]jj]jk]jn]ujZjJYjr]rQYj{XfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rRYrSY}rTY(jYUjZjNYubajdjubaubjV)rUY}rVY(jYUjZjtjbj jdj jf}rWY(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMUtypej ujpMjqhjr]rXYj)rYY}rZY(jYXUnexpected indentation.jf}r[Y(jh]ji]jj]jk]jn]ujZjUYjr]r\Yj{XUnexpected indentation.r]Yr^Y}r_Y(jYUjZjYYubajdjubaubjV)r`Y}raY(jYUjZjtjbj jdj jf}rbY(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMUtypej ujpMjqhjr]rcYj)rdY}reY(jYX=Literal block ends without a blank line; unexpected unindent.jf}rfY(jh]ji]jj]jk]jn]ujZj`Yjr]rgYj{X=Literal block ends without a blank line; unexpected unindent.rhYriY}rjY(jYUjZjdYubajdjubaubjV)rkY}rlY(jYUjZjtjbj jdj jf}rmY(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMUtypej ujpMjqhjr]rnYj)roY}rpY(jYX%Line block ends without a blank line.jf}rqY(jh]ji]jj]jk]jn]ujZjkYjr]rrYj{X%Line block ends without a blank line.rsYrtY}ruY(jYUjZjoYubajdjubaubjV)rvY}rwY(jYUjZjjbj jdj jf}rxY(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMUtypej ujpMjqhjr]ryYj)rzY}r{Y(jYXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.jf}r|Y(jh]ji]jj]jk]jn]ujZjvYjr]r}Yj{XfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.r~YrY}rY(jYUjZjzYubajdjubaubjV)rY}rY(jYUjZjjbj jdj jf}rY(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMUtypej ujpMjqhjr]rYj)rY}rY(jYXUnexpected indentation.jf}rY(jh]ji]jj]jk]jn]ujZjYjr]rYj{XUnexpected indentation.rYrY}rY(jYUjZjYubajdjubaubjV)rY}rY(jYUjZjjbj jdj jf}rY(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMUtypej ujpMjqhjr]rYj)rY}rY(jYX=Literal block ends without a blank line; unexpected unindent.jf}rY(jh]ji]jj]jk]jn]ujZjYjr]rYj{X=Literal block ends without a blank line; unexpected unindent.rYrY}rY(jYUjZjYubajdjubaubjV)rY}rY(jYUjZjjbj jdj jf}rY(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMUtypej ujpMjqhjr]rYj)rY}rY(jYX?Explicit markup ends without a blank line; unexpected unindent.jf}rY(jh]ji]jj]jk]jn]ujZjYjr]rYj{X?Explicit markup ends without a blank line; unexpected unindent.rYrY}rY(jYUjZjYubajdjubaubjV)rY}rY(jYUjZjyjbj jdj jf}rY(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMUtypej ujpMjqhjr]rYj)rY}rY(jYXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.jf}rY(jh]ji]jj]jk]jn]ujZjYjr]rYj{XfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rYrY}rY(jYUjZjYubajdjubaubjV)rY}rY(jYUjZjyjbj jdj jf}rY(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMUtypej ujpMjqhjr]rYj)rY}rY(jYXUnexpected indentation.jf}rY(jh]ji]jj]jk]jn]ujZjYjr]rYj{XUnexpected indentation.rYrY}rY(jYUjZjYubajdjubaubjV)rY}rY(jYUjZjyjbj jdj jf}rY(jh]UlevelKjk]rYjajj]rYjaUsourcej ji]jn]UlineMUtypej ujpMjqhjr]rYj)rY}rY(jYX0Inline emphasis start-string without end-string.jf}rY(jh]ji]jj]jk]jn]ujZjYjr]rYj{X0Inline emphasis start-string without end-string.rYrY}rY(jYUjZjYubajdjubaubjV)rY}rY(jYUjZjyjbj jdj jf}rY(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMUtypej ujpMjqhjr]rYj)rY}rY(jYX=Literal block ends without a blank line; unexpected unindent.jf}rY(jh]ji]jj]jk]jn]ujZjYjr]rYj{X=Literal block ends without a blank line; unexpected unindent.rYrY}rY(jYUjZjYubajdjubaubjV)rY}rY(jYUjZjgjbj jdj jf}rY(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMUtypej ujpMjqhjr]rYj)rY}rY(jYXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.jf}rY(jh]ji]jj]jk]jn]ujZjYjr]rYj{XfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rYrY}rY(jYUjZjYubajdjubaubjV)rY}rY(jYUjZjgjbj jdj jf}rY(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMUtypej ujpMjqhjr]rYj)rY}rY(jYXUnexpected indentation.jf}rY(jh]ji]jj]jk]jn]ujZjYjr]rYj{XUnexpected indentation.rYrY}rY(jYUjZjYubajdjubaubjV)rY}rY(jYUjZjgjbj jdj jf}rY(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMUtypej ujpMjqhjr]rYj)rY}rY(jYX=Literal block ends without a blank line; unexpected unindent.jf}rY(jh]ji]jj]jk]jn]ujZjYjr]rYj{X=Literal block ends without a blank line; unexpected unindent.rYrY}rY(jYUjZjYubajdjubaubjV)rY}rY(jYUjZjgjbj jdj jf}rY(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMUtypej ujpMjqhjr]rYj)rY}rY(jYX%Line block ends without a blank line.jf}rY(jh]ji]jj]jk]jn]ujZjYjr]rYj{X%Line block ends without a blank line.rYrY}rY(jYUjZjYubajdjubaubjV)rY}rY(jYUjZjgjbj jdj jf}rY(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMUtypej ujpMjqhjr]rYj)rZ}rZ(jYXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.jf}rZ(jh]ji]jj]jk]jn]ujZjYjr]rZj{XfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rZrZ}rZ(jYUjZjZubajdjubaubjV)rZ}rZ(jYUjZjgjbj jdj jf}r Z(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMUtypej ujpMjqhjr]r Zj)r Z}r Z(jYXUnexpected indentation.jf}r Z(jh]ji]jj]jk]jn]ujZjZjr]rZj{XUnexpected indentation.rZrZ}rZ(jYUjZj ZubajdjubaubjV)rZ}rZ(jYUjZjgjbj jdj jf}rZ(jh]UlevelKjk]jj]Usourcej ji]jn]UlineMUtypej ujpMjqhjr]rZj)rZ}rZ(jYX=Literal block ends without a blank line; unexpected unindent.jf}rZ(jh]ji]jj]jk]jn]ujZjZjr]rZj{X=Literal block ends without a blank line; unexpected unindent.rZrZ}rZ(jYUjZjZubajdjubaubjV)rZ}rZ(jYUjZjjbjjdj jf}rZ(jh]UlevelKjk]jj]r ZjaUsourcejji]jn]UlineKUtypej ujpKjqhjr]r!Zj)r"Z}r#Z(jYX+Duplicate implicit target name: "overview".jf}r$Z(jh]ji]jj]jk]jn]ujZjZjr]r%Zj{X+Duplicate implicit target name: "overview".r&Zr'Z}r(Z(jYUjZj"ZubajdjubaubjV)r)Z}r*Z(jYUjZj-jbXeinternal padding after source/rtos/How_to_Guides/Host/Flashing_and_Boot/Flash_bootable_images.rst.incr+Zjdj jf}r,Z(jh]UlevelKjk]jj]Usourcejji]jn]UlineMUUtypej ujpMWjqhjr]r-Z(j)r.Z}r/Z(jYX;Content block expected for the "raw" directive; none found.jf}r0Z(jh]ji]jj]jk]jn]ujZj)Zjr]r1Zj{X;Content block expected for the "raw" directive; none found.r2Zr3Z}r4Z(jYUjZj.Zubajdjubj)r5Z}r6Z(jYX.. raw:: html jf}r7Z(jjjk]jj]jh]ji]jn]ujZj)Zjr]r8Zj{X.. raw:: html r9Zr:Z}r;Z(jYUjZj5ZubajdjubeubjV)rZjdj jf}r?Z(jh]UlevelKjk]jj]Usourcejlji]jn]UlineMUtypej ujpMjqhjr]r@Z(j)rAZ}rBZ(jYX;Content block expected for the "raw" directive; none found.jf}rCZ(jh]ji]jj]jk]jn]ujZj[}r?[(jYUjZj9[ubajdjubaubjV)r@[}rA[(jYUjZj1jbj!jdj jf}rB[(jh]UlevelKjk]jj]Usourcej!ji]jn]UlineMUtypej ujpMjqhjr]rC[j)rD[}rE[(jYX?Explicit markup ends without a blank line; unexpected unindent.jf}rF[(jh]ji]jj]jk]jn]ujZj@[jr]rG[j{X?Explicit markup ends without a blank line; unexpected unindent.rH[rI[}rJ[(jYUjZjD[ubajdjubaubjV)rK[}rL[(jYUjZj1jbj!jdj jf}rM[(jh]UlevelKjk]jj]Usourcej!ji]jn]UlineM`Utypej ujpM_jqhjr]rN[j)rO[}rP[(jYX%Line block ends without a blank line.jf}rQ[(jh]ji]jj]jk]jn]ujZjK[jr]rR[j{X%Line block ends without a blank line.rS[rT[}rU[(jYUjZjO[ubajdjubaubjV)rV[}rW[(jYUjZj1jbj!jdj jf}rX[(jh]UlevelKjk]jj]Usourcej!ji]jn]UlineMUtypej ujpMjqhjr]rY[j)rZ[}r[[(jYX=Literal block ends without a blank line; unexpected unindent.jf}r\[(jh]ji]jj]jk]jn]ujZjV[jr]r][j{X=Literal block ends without a blank line; unexpected unindent.r^[r_[}r`[(jYUjZjZ[ubajdjubaubjV)ra[}rb[(jYUjZj1jbj!jdj jf}rc[(jh]UlevelKjk]jj]Usourcej!ji]jn]UlineMUtypej ujpMjqhjr]rd[j)re[}rf[(jYX=Literal block ends without a blank line; unexpected unindent.jf}rg[(jh]ji]jj]jk]jn]ujZja[jr]rh[j{X=Literal block ends without a blank line; unexpected unindent.ri[rj[}rk[(jYUjZje[ubajdjubaubjV)rl[}rm[(jYUjZj1jbj!jdj jf}rn[(jh]UlevelKjk]jj]Usourcej!ji]jn]UlineMUtypej ujpMjqhjr]ro[j)rp[}rq[(jYX=Literal block ends without a blank line; unexpected unindent.jf}rr[(jh]ji]jj]jk]jn]ujZjl[jr]rs[j{X=Literal block ends without a blank line; unexpected unindent.rt[ru[}rv[(jYUjZjp[ubajdjubaubjV)rw[}rx[(jYUjZj1jbj!jdj jf}ry[(jh]UlevelKjk]jj]Usourcej!ji]jn]UlineMUtypej ujpMjqhjr]rz[j)r{[}r|[(jYX=Literal block ends without a blank line; unexpected unindent.jf}r}[(jh]ji]jj]jk]jn]ujZjw[jr]r~[j{X=Literal block ends without a blank line; unexpected unindent.r[r[}r[(jYUjZj{[ubajdjubaubjV)r[}r[(jYUjZj1jbj!jdj jf}r[(jh]UlevelKjk]jj]Usourcej!ji]jn]UlineMUtypej ujpMjqhjr]r[j)r[}r[(jYX=Literal block ends without a blank line; unexpected unindent.jf}r[(jh]ji]jj]jk]jn]ujZj[jr]r[j{X=Literal block ends without a blank line; unexpected unindent.r[r[}r[(jYUjZj[ubajdjubaubjV)r[}r[(jYUjZj1jbj!jdj jf}r[(jh]UlevelKjk]jj]Usourcej!ji]jn]UlineMUtypej ujpMjqhjr]r[j)r[}r[(jYX%Line block ends without a blank line.jf}r[(jh]ji]jj]jk]jn]ujZj[jr]r[j{X%Line block ends without a blank line.r[r[}r[(jYUjZj[ubajdjubaubjV)r[}r[(jYUjZj1jbj!jdj jf}r[(jh]UlevelKjk]jj]Usourcej!ji]jn]UlineMUtypej ujpMjqhjr]r[j)r[}r[(jYX%Line block ends without a blank line.jf}r[(jh]ji]jj]jk]jn]ujZj[jr]r[j{X%Line block ends without a blank line.r[r[}r[(jYUjZj[ubajdjubaubjV)r[}r[(jYUjZj1jbj!jdj jf}r[(jh]UlevelKjk]jj]Usourcej!ji]jn]UlineMUtypej ujpMjqhjr]r[j)r[}r[(jYX%Line block ends without a blank line.jf}r[(jh]ji]jj]jk]jn]ujZj[jr]r[j{X%Line block ends without a blank line.r[r[}r[(jYUjZj[ubajdjubaubjV)r[}r[(jYUjZj1jbj!jdj jf}r[(jh]UlevelKjk]jj]Usourcej!ji]jn]UlineMUtypej ujpMjqhjr]r[j)r[}r[(jYX%Line block ends without a blank line.jf}r[(jh]ji]jj]jk]jn]ujZj[jr]r[j{X%Line block ends without a blank line.r[r[}r[(jYUjZj[ubajdjubaubjV)r[}r[(jYUjZj1jbj!jdj jf}r[(jh]UlevelKjk]jj]Usourcej!ji]jn]UlineMUtypej ujpMjqhjr]r[j)r[}r[(jYX%Line block ends without a blank line.jf}r[(jh]ji]jj]jk]jn]ujZj[jr]r[j{X%Line block ends without a blank line.r[r[}r[(jYUjZj[ubajdjubaubjV)r[}r[(jYUjZj1jbj!jdj jf}r[(jh]UlevelKjk]jj]Usourcej!ji]jn]UlineMUtypej ujpMjqhjr]r[j)r[}r[(jYX%Line block ends without a blank line.jf}r[(jh]ji]jj]jk]jn]ujZj[jr]r[j{X%Line block ends without a blank line.r[r[}r[(jYUjZj[ubajdjubaubjV)r[}r[(jYUjZj1jbj!jdj jf}r[(jh]UlevelKjk]jj]Usourcej!ji]jn]UlineMUtypej ujpMjqhjr]r[j)r[}r[(jYX%Line block ends without a blank line.jf}r[(jh]ji]jj]jk]jn]ujZj[jr]r[j{X%Line block ends without a blank line.r[r[}r[(jYUjZj[ubajdjubaubjV)r[}r[(jYUjZj1jbj!jdj jf}r[(jh]UlevelKjk]jj]Usourcej!ji]jn]UlineMUtypej ujpMjqhjr]r[j)r[}r[(jYX%Line block ends without a blank line.jf}r[(jh]ji]jj]jk]jn]ujZj[jr]r[j{X%Line block ends without a blank line.r[r[}r[(jYUjZj[ubajdjubaubjV)r[}r[(jYUjZj1jbj!jdj jf}r[(jh]UlevelKjk]jj]Usourcej!ji]jn]UlineM9Utypej ujpM8jqhjr]r[j)r[}r[(jYX%Line block ends without a blank line.jf}r[(jh]ji]jj]jk]jn]ujZj[jr]r[j{X%Line block ends without a blank line.r[r[}r[(jYUjZj[ubajdjubaubjV)r[}r[(jYUjZj1jbj!jdj jf}r[(jh]UlevelKjk]jj]Usourcej!ji]jn]UlineMGUtypej ujpMFjqhjr]r[j)r[}r[(jYX%Line block ends without a blank line.jf}r[(jh]ji]jj]jk]jn]ujZj[jr]r[j{X%Line block ends without a blank line.r[r[}r[(jYUjZj[ubajdjubaubjV)r[}r[(jYUjZj1jbj!jdj jf}r[(jh]UlevelKjk]jj]Usourcej!ji]jn]UlineMUtypej ujpNjqhjr]r[(j)r[}r\(jYX2Error in "rubric" directive: no content permitted.jf}r\(jh]ji]jj]jk]jn]ujZj[jr]r\j{X2Error in "rubric" directive: no content permitted.r\r\}r\(jYUjZj[ubajdjubj)r\}r\(jYX.. rubric:: Download the Full CCS Project :name: download-the-full-ccs-project-1 `UART_BasicExample_evmAM572x_m4ExampleProject_with_ipc.zip `__ jf}r\(jjjk]jj]jh]ji]jn]ujZj[jr]r \j{X.. rubric:: Download the Full CCS Project :name: download-the-full-ccs-project-1 `UART_BasicExample_evmAM572x_m4ExampleProject_with_ipc.zip `__ r \r \}r \(jYUjZj\ubajdjubeubjV)r \}r\(jYUjZj1jbXinternal padding after source/rtos/How_to_Guides/Host/System_Integration/Create_DSP_and_IPU_FW_using_PDK_and_IPC_to_load_from_ARM_AM57xx.rst.incr\jdj jf}r\(jh]UlevelKjk]jj]Usourcej!ji]jn]UlineMUtypej ujpMjqhjr]r\(j)r\}r\(jYX;Content block expected for the "raw" directive; none found.jf}r\(jh]ji]jj]jk]jn]ujZj \jr]r\j{X;Content block expected for the "raw" directive; none found.r\r\}r\(jYUjZj\ubajdjubj)r\}r\(jYX.. raw:: html jf}r\(jjjk]jj]jh]ji]jn]ujZj \jr]r\j{X.. raw:: html r\r\}r\(jYUjZj\ubajdjubeubjV)r \}r!\(jYUjZjZ>jbj:>jdj jf}r"\(jh]UlevelKjk]jj]r#\j`>aUsourcej:>ji]jn]UlineKUtypej ujpKjqhjr]r$\j)r%\}r&\(jYX/Duplicate implicit target name: "introduction".jf}r'\(jh]ji]jj]jk]jn]ujZj \jr]r(\j{X/Duplicate implicit target name: "introduction".r)\r*\}r+\(jYUjZj%\ubajdjubaubjV)r,\}r-\(jYUjZjMDjbj:>jdj jf}r.\(jh]UlevelKjk]jj]Usourcej:>ji]jn]UlineMUtypej ujpMjqhjr]r/\j)r0\}r1\(jYXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.jf}r2\(jh]ji]jj]jk]jn]ujZj,\jr]r3\j{XfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.r4\r5\}r6\(jYUjZj0\ubajdjubaubjV)r7\}r8\(jYUjZjGjbX}internal padding after source/rtos/How_to_Guides/Host/System_Integration/IPC_Debugging_Tools_and_Techniques_on_AM57xx.rst.incr9\jdj jf}r:\(jh]UlevelKjk]jj]Usourcej:>ji]jn]UlineMUtypej ujpMjqhjr]r;\(j)r<\}r=\(jYX;Content block expected for the "raw" directive; none found.jf}r>\(jh]ji]jj]jk]jn]ujZj7\jr]r?\j{X;Content block expected for the "raw" directive; none found.r@\rA\}rB\(jYUjZj<\ubajdjubj)rC\}rD\(jYX.. raw:: html jf}rE\(jjjk]jj]jh]ji]jn]ujZj7\jr]rF\j{X.. raw:: html rG\rH\}rI\(jYUjZjC\ubajdjubeubjV)rJ\}rK\(jYUjZj[)rL\}rM\(jYUjKjZj[)rN\}rO\(jYUjKjZj[)rP\}rQ\(jYUjZj[)rR\}rS\(jYUjZhjbjcjdjejf}rT\(jh]ji]jj]jk]rU\Uevm-hardware-setuprV\ajn]rW\haujpKbjqhjr]rX\(jt)rY\}rZ\(jYXEVM Hardware Setupr[\jZjR\jbjcjdjxjf}r\\(jh]ji]jj]jk]jn]ujpKbjqhjr]r]\j{XEVM Hardware Setupr^\r_\}r`\(jYj[\jZjY\ubaubj)ra\}rb\(jYX AM65x EVMjZjR\jbjcjdjjf}rc\(jjjk]jj]jh]ji]jn]ujpKdjqhjr]rd\j{X AM65x EVMre\rf\}rg\(jYUjZja\ubaubj)rh\}ri\(jYX4====================================================jZjR\jbjcjdjjf}rj\(jjjk]jj]jh]ji]jn]ujpKejqhjr]rk\j{X4====================================================rl\rm\}rn\(jYUjZjh\ubaubjP\j[)ro\}rp\(jYUjZjR\jbjXEsource/common/EVM_Hardware_Setup/AM572x_GP_EVM_Hardware_Setup.rst.incrq\rr\}rs\bjdjejf}rt\(jh]ji]jj]jk]ru\Uam572x-gp-evm-hardware-setuprv\ajn]rw\jaujpKjqhjr]rx\(jt)ry\}rz\(jYXAM572x GP EVM Hardware Setupr{\jZjo\jbjr\jdjxjf}r|\(jh]ji]jj]jk]jn]ujpKjqhjr]r}\j{XAM572x GP EVM Hardware Setupr~\r\}r\(jYj{\jZjy\ubaubj)r\}r\(jYX Descriptionr\jKjZjo\jbjr\jdjjf}r\(jk]r\Uid33r\ajj]jh]r\X descriptionr\aji]jn]ujpNjqhjr]r\j{X Descriptionr\r\}r\(jYj\jZj\ubaubj)r\}r\(jYXThe AM572x Evaluation Module provides an affordable platform to quickly start evaluation of Sitara™ ARM® Cortex®-A15 AM57x Processors (AM5728, AM5726, AM5718, AM5716) and accelerate development for HMI, machine vision, networking, medical imaging and many other industrial applications. It is a development platform based on the dual ARM Cortex-A15, dual C66x DSP processor that is integrated with tons of connectivity such as PCIe, SATA, HDMI, USB 3.0/2.0, Dual Gigabit Ethernet, and more.r\jZjo\jbjr\jdjjf}r\(jh]ji]jj]jk]jn]ujpK jqhjr]r\j{XThe AM572x Evaluation Module provides an affordable platform to quickly start evaluation of Sitara™ ARM® Cortex®-A15 AM57x Processors (AM5728, AM5726, AM5718, AM5716) and accelerate development for HMI, machine vision, networking, medical imaging and many other industrial applications. It is a development platform based on the dual ARM Cortex-A15, dual C66x DSP processor that is integrated with tons of connectivity such as PCIe, SATA, HDMI, USB 3.0/2.0, Dual Gigabit Ethernet, and more.r\r\}r\(jYj\jZj\ubaubj)r\}r\(jYXThe AM572x Evaluation Module also integrates video and 3D/2D graphics acceleration, as well as a qual-core Programmable Real-time Unit (PRU) and dual ARM Cortex-M4 cores.r\jZjo\jbjr\jdjjf}r\(jh]ji]jj]jk]jn]ujpKjqhjr]r\j{XThe AM572x Evaluation Module also integrates video and 3D/2D graphics acceleration, as well as a qual-core Programmable Real-time Unit (PRU) and dual ARM Cortex-M4 cores.r\r\}r\(jYj\jZj\ubaubj)r\}r\(jYXContents of the kitr\jZjo\jbjr\jdjjf}r\(jk]r\Ucontents-of-the-kitr\ajj]jh]ji]jn]r\h[aujpNjqhjr]r\j{XContents of the kitr\r\}r\(jYj\jZj\ubaubjB)r\}r\(jYX+.. Image:: ../../../images/EVM_modules.png jZjo\jbjr\jdjEjf}r\(UuriX$rtos/../../../images/EVM_modules.pngr\jk]jj]jh]ji]jH}r\U*j\sjn]ujpKjqhjr]ubj)r\}r\(jYX **Module:**r\jZjo\jbjr\jdjjf}r\(jh]ji]jj]jk]jn]ujpKjqhjr]r\j)r\}r\(jYj\jf}r\(jh]ji]jj]jk]jn]ujZj\jr]r\j{XModule:r\r\}r\(jYUjZj\ubajdjubaubjC)r\}r\(jYUjZjo\jbjr\jdj`jf}r\(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]r\(j/)r\}r\(jYXProcessor Moduler\jZj\jbjr\jdj2jf}r\(jh]ji]jj]jk]jn]ujpNjqhjr]r\j)r\}r\(jYj\jZj\jbjr\jdjjf}r\(jh]ji]jj]jk]jn]ujpKjr]r\j{XProcessor Moduler\r\}r\(jYj\jZj\ubaubaubj/)r\}r\(jYX LCD Moduler\jZj\jbjr\jdj2jf}r\(jh]ji]jj]jk]jn]ujpNjqhjr]r\j)r\}r\(jYj\jZj\jbjr\jdjjf}r\(jh]ji]jj]jk]jn]ujpKjr]r\j{X LCD Moduler\r\}r\(jYj\jZj\ubaubaubj/)r\}r\(jYXCamera Module jZj\jbjr\jdj2jf}r\(jh]ji]jj]jk]jn]ujpNjqhjr]r\j)r\}r\(jYX Camera Moduler\jZj\jbjr\jdjjf}r\(jh]ji]jj]jk]jn]ujpKjr]r\j{X Camera Moduler\r\}r\(jYj\jZj\ubaubaubeubj)r\}r\(jYX**Other components:**r\jZjo\jbjr\jdjjf}r\(jh]ji]jj]jk]jn]ujpK!jqhjr]r\j)r\}r\(jYj\jf}r\(jh]ji]jj]jk]jn]ujZj\jr]r\j{XOther components:r\r\}r\(jYUjZj\ubajdjubaubjC)r\}r\(jYUjZjo\jbjr\jdj`jf}r\(jGX-jk]jj]jh]ji]jn]ujpK#jqhjr]r\(j/)r\}r\(jYXµSD card with Linux SDKr\jZj\jbjr\jdj2jf}r\(jh]ji]jj]jk]jn]ujpNjqhjr]r\j)r\}r\(jYj\jZj\jbjr\jdjjf}r\(jh]ji]jj]jk]jn]ujpK#jr]r\j{XµSD card with Linux SDKr\r\}r\(jYj\jZj\ubaubaubj/)r\}r\(jYXUSB-to-serial debug cabler\jZj\jbjr\jdj2jf}r](jh]ji]jj]jk]jn]ujpNjqhjr]r]j)r]}r](jYj\jZj\jbjr\jdjjf}r](jh]ji]jj]jk]jn]ujpK$jr]r]j{XUSB-to-serial debug cabler]r]}r](jYj\jZj]ubaubaubj/)r ]}r ](jYX(HDMI cable for optional external displayr ]jZj\jbjr\jdj2jf}r ](jh]ji]jj]jk]jn]ujpNjqhjr]r ]j)r]}r](jYj ]jZj ]jbjr\jdjjf}r](jh]ji]jj]jk]jn]ujpK%jr]r]j{X(HDMI cable for optional external displayr]r]}r](jYj ]jZj]ubaubaubj/)r]}r](jYX LCD brackets jZj\jbjr\jdj2jf}r](jh]ji]jj]jk]jn]ujpNjqhjr]r]j)r]}r](jYX LCD bracketsr]jZj]jbjr\jdjjf}r](jh]ji]jj]jk]jn]ujpK&jr]r]j{X LCD bracketsr]r]}r ](jYj]jZj]ubaubaubeubj)r!]}r"](jYX**Printed documentation:**r#]jZjo\jbjr\jdjjf}r$](jh]ji]jj]jk]jn]ujpK(jqhjr]r%]j)r&]}r'](jYj#]jf}r(](jh]ji]jj]jk]jn]ujZj!]jr]r)]j{XPrinted documentation:r*]r+]}r,](jYUjZj&]ubajdjubaubjC)r-]}r.](jYUjZjo\jbjr\jdj`jf}r/](jGX-jk]jj]jh]ji]jn]ujpK*jqhjr]r0]j/)r1]}r2](jYXE`Quick start guide `__ jZj-]jbjr\jdj2jf}r3](jh]ji]jj]jk]jn]ujpNjqhjr]r4]j)r5]}r6](jYXD`Quick start guide `__r7]jZj1]jbjr\jdjjf}r8](jh]ji]jj]jk]jn]ujpK*jr]r9]j)r:]}r;](jYj7]jf}r<](UnameXQuick start guidejX,http://www.ti.com/lit/ug/sprw275/sprw275.pdfjk]jj]jh]ji]jn]ujZj5]jr]r=]j{XQuick start guider>]r?]}r@](jYUjZj:]ubajdjubaubaubaubj)rA]}rB](jYXEVM Layout and Key ComponentsrC]jKjZjo\jbjr\jdjjf}rD](jk]rE]Uid34rF]ajj]jh]rG]Xevm-layout-and-key-componentsrH]aji]jn]ujpNjqhjr]rI]j{XEVM Layout and Key ComponentsrJ]rK]}rL](jYjC]jZjA]ubaubjB)rM]}rN](jYX6.. Image:: ../../../images/AM572X_GP_EVM_Overview.png jZjo\jbjr\jdjEjf}rO](UuriX/rtos/../../../images/AM572X_GP_EVM_Overview.pngrP]jk]jj]jh]ji]jH}rQ]U*jP]sjn]ujpK0jqhjr]ubj)rR]}rS](jYX+JTAG debug probes (aka Emulators) supportedrT]jKjZjo\jbjr\jdjjf}rU](jk]rV]U)jtag-debug-probes-aka-emulators-supportedrW]ajj]jh]rX]X)jtag-debug-probes-aka-emulators-supportedrY]aji]jn]ujpNjqhjr]rZ]j{X+JTAG debug probes (aka Emulators) supportedr[]r\]}r]](jYjT]jZjR]ubaubj)r^]}r_](jYX/List of standalone JTAG debug probes supported:r`]jZjo\jbjr\jdjjf}ra](jh]ji]jj]jk]jn]ujpK4jqhjr]rb]j{X/List of standalone JTAG debug probes supported:rc]rd]}re](jYj`]jZj^]ubaubjC)rf]}rg](jYUjZjo\jbjr\jdj`jf}rh](jGX-jk]jj]jh]ji]jn]ujpK6jqhjr]ri](j/)rj]}rk](jYXVXDS100-class JTAG debug probes (low cost, low performance). XDS100v1 is not supported.jZjf]jbjr\jdj2jf}rl](jh]ji]jj]jk]jn]ujpNjqhjr]rm]j)rn]}ro](jYXVXDS100-class JTAG debug probes (low cost, low performance). XDS100v1 is not supported.rp]jZjj]jbjr\jdjjf}rq](jh]ji]jj]jk]jn]ujpK6jr]rr]j{XVXDS100-class JTAG debug probes (low cost, low performance). XDS100v1 is not supported.rs]rt]}ru](jYjp]jZjn]ubaubaubj/)rv]}rw](jYX,XDS200-class JTAG debug probes (recommended)rx]jZjf]jbjr\jdj2jf}ry](jh]ji]jj]jk]jn]ujpNjqhjr]rz]j)r{]}r|](jYjx]jZjv]jbjr\jdjjf}r}](jh]ji]jj]jk]jn]ujpK8jr]r~]j{X,XDS200-class JTAG debug probes (recommended)r]r]}r](jYjx]jZj{]ubaubaubj/)r]}r](jYX4XDS560v2-class JTAG debug probes (high performance) jZjf]jbjr\jdj2jf}r](jh]ji]jj]jk]jn]ujpNjqhjr]r]j)r]}r](jYX3XDS560v2-class JTAG debug probes (high performance)r]jZj]jbjr\jdjjf}r](jh]ji]jj]jk]jn]ujpK9jr]r]j{X3XDS560v2-class JTAG debug probes (high performance)r]r]}r](jYj]jZj]ubaubaubeubjZ)r]}r](jYUjZjo\jbjr\jdj]jf}r](jh]ji]jj]jk]jn]ujpK;jqhjr]r]j`)r]}r](jYUjcKjZj]jbjr\jdjpjf}r](jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r]}r](jYX Host Driversr]jZjo\jbjr\jdjjf}r](jk]r]U host-driversr]ajj]jh]ji]jn]r]haujpNjqhjr]r]j{X Host Driversr]r]}r](jYj]jZj]ubaubj)r]}r](jYXgDownload and install Virtual COM Port Drivers for TTL-232R-3V3 USB to UART cable from the FTDI website:r]jZjo\jbjr\jdjjf}r](jh]ji]jj]jk]jn]ujpK@jqhjr]r]j{XgDownload and install Virtual COM Port Drivers for TTL-232R-3V3 USB to UART cable from the FTDI website:r]r]}r](jYj]jZj]ubaubjC)r]}r](jYUjZjo\jbjr\jdj`jf}r](jGX-jk]jj]jh]ji]jn]ujpKCjqhjr]r](j/)r]}r](jYX9`VCP Drivers `__r]jZj]jbjr\jdj2jf}r](jh]ji]jj]jk]jn]ujpNjqhjr]r]j)r]}r](jYj]jZj]jbjr\jdjjf}r](jh]ji]jj]jk]jn]ujpKCjr]r]j)r]}r](jYj]jf}r](UnameX VCP DriversjX'http://www.ftdichip.com/Drivers/VCP.htmjk]jj]jh]ji]jn]ujZj]jr]r]j{X VCP Driversr]r]}r](jYUjZj]ubajdjubaubaubj/)r]}r](jYXT`TTL-232R-3V3 product `__ jZj]jbjr\jdj2jf}r](jh]ji]jj]jk]jn]ujpNjqhjr]r]j)r]}r](jYXS`TTL-232R-3V3 product `__r]jZj]jbjr\jdjjf}r](jh]ji]jj]jk]jn]ujpKDjr]r]j)r]}r](jYj]jf}r](UnameXTTL-232R-3V3 productjX8http://www.ftdichip.com/Products/Cables/USBTTLSerial.htmjk]jj]jh]ji]jn]ujZj]jr]r]j{XTTL-232R-3V3 productr]r]}r](jYUjZj]ubajdjubaubaubeubj)r]}r](jYXMinimal EVM setupr]jKjZjo\jbjr\jdjjf}r](jk]r]Uminimal-evm-setupr]ajj]jh]r]Xminimal-evm-setupr]aji]jn]ujpNjqhjr]r]j{XMinimal EVM setupr]r]}r](jYj]jZj]ubaubj)r]}r](jYXSetting boot switchesr]jKjZjo\jbjr\jdjjf}r](jk]r]Usetting-boot-switchesr]ajj]jh]r]Xsetting-boot-switchesr]aji]jn]ujpNjqhjr]r]j{XSetting boot switchesr]r]}r](jYj]jZj]ubaubjB)r]}r](jYX-.. Image:: ../../../images/Boot_Switches.png jZjo\jbjr\jdjEjf}r](UuriX&rtos/../../../images/Boot_Switches.pngr]jk]jj]jh]ji]jH}r]U*j]sjn]ujpKNjqhjr]ubj)r]}r](jYXOther Boot Pin configurations: `GP EVM Boot Options `__jZjo\jbjr\jdjjf}r](jh]ji]jj]jk]jn]ujpKOjqhjr]r](j{XOther Boot Pin configurations: r]r]}r](jYXOther Boot Pin configurations: jZj]ubj)r]}r](jYXy`GP EVM Boot Options `__jf}r](UnameXGP EVM Boot OptionsjX_http://processors.wiki.ti.com/AM572x_General_Purpose_EVM_HW_User_Guide#Boot_and_emulation_setupjk]jj]jh]ji]jn]ujZj]jr]r]j{XGP EVM Boot Optionsr]r]}r](jYUjZj]ubajdjubeubjZ)r]}r](jYUjZjo\jbjr\jdj]jf}r](jh]ji]jj]jk]jn]ujpKRjqhjr]r]j`)r]}r](jYUjcKjZj]jbjr\jdjpjf}r](jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r]}r](jYXConnecting Emulatorr^jKjZjo\jbjr\jdjjf}r^(jk]r^Uconnecting-emulatorr^ajj]jh]r^Xconnecting-emulatorr^aji]jn]ujpNjqhjr]r^j{XConnecting Emulatorr^r^}r ^(jYj^jZj]ubaubj)r ^}r ^(jYX**Note: This EVM setup is only required for developers who need to connect to cores using Code Composer studio to load application.**r ^jZjo\jbjr\jdjjf}r ^(jh]ji]jj]jk]jn]ujpKWjqhjr]r^j)r^}r^(jYj ^jf}r^(jh]ji]jj]jk]jn]ujZj ^jr]r^j{XNote: This EVM setup is only required for developers who need to connect to cores using Code Composer studio to load application.r^r^}r^(jYUjZj^ubajdjubaubj)r^}r^(jYXThe JTAG emulation pins for the EVM are on the back of the processor module. User need to carefully unmount the processor module from the LCD panel in order to get access to the JTAG pins.r^jZjo\jbjr\jdjjf}r^(jh]ji]jj]jk]jn]ujpKZjqhjr]r^j{XThe JTAG emulation pins for the EVM are on the back of the processor module. User need to carefully unmount the processor module from the LCD panel in order to get access to the JTAG pins.r^r^}r^(jYj^jZj^ubaubj)r^}r^(jYX\Refer to the image below for how to safely separate the processor module from the LCD panel.r ^jZjo\jbjr\jdjjf}r!^(jh]ji]jj]jk]jn]ujpK^jqhjr]r"^j{X\Refer to the image below for how to safely separate the processor module from the LCD panel.r#^r$^}r%^(jYj ^jZj^ubaubjd$)r&^}r'^(jYUjZjo\jbNjdjg$jf}r(^(jh]ji]jj]jk]jn]ujpNjqhjr]r)^jj$)r*^}r+^(jYUjf}r,^(jk]jj]jh]ji]jn]UcolsKujZj&^jr]r-^(jo$)r.^}r/^(jYUjf}r0^(jk]jj]jh]ji]jn]UcolwidthK7ujZj*^jr]jdjs$ubjo$)r1^}r2^(jYUjf}r3^(jk]jj]jh]ji]jn]UcolwidthK1ujZj*^jr]jdjs$ubj$)r4^}r5^(jYUjf}r6^(jh]ji]jj]jk]jn]ujZj*^jr]r7^j$)r8^}r9^(jYUjf}r:^(jh]ji]jj]jk]jn]ujZj4^jr]r;^(j$)r<^}r=^(jYUjf}r>^(jh]ji]jj]jk]jn]ujZj8^jr]r?^jB)r@^}rA^(jYX5.. Image:: ../../../images/X15_PModule_disconnect.jpgjf}rB^(UuriX/rtos/../../../images/X15_PModule_disconnect.jpgrC^jk]jj]jh]ji]jH}rD^U*jC^sjn]ujZj<^jr]jdjEubajdj$ubj$)rE^}rF^(jYUjf}rG^(jh]ji]jj]jk]jn]ujZj8^jr]rH^jB)rI^}rJ^(jYX'.. Image:: ../../../images/JMI_0065.jpgjf}rK^(UuriX!rtos/../../../images/JMI_0065.jpgrL^jk]jj]jh]ji]jH}rM^U*jL^sjn]ujZjE^jr]jdjEubajdj$ubejdj$ubajdjy%ubejdjz%ubaubjZ)rN^}rO^(jYUjZjo\jbjr\jdj]jf}rP^(jh]ji]jj]jk]jn]ujpKejqhjr]rQ^(j`)rR^}rS^(jYUjcKjZjN^jbjr\jdjpjf}rT^(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)rU^}rV^(jYXQImage for how to connect the XDS200 Emulator to the 20 pin header is shown below:rW^jcKjZjN^jbjr\jdjpjf}rX^(jh]ji]jj]jk]jn]ujpKgjqhjr]rY^j{XQImage for how to connect the XDS200 Emulator to the 20 pin header is shown below:rZ^r[^}r\^(jYjW^jZjU^ubaubeubjB)r]^}r^^(jYX;.. Image:: ../../../images/GPEVM_XDS200.jpg :scale: 50% jZjo\jbjr\jdjEjf}r_^(UscaleK2UuriX%rtos/../../../images/GPEVM_XDS200.jpgr`^jk]jj]jh]ji]jH}ra^U*j`^sjn]ujpNjqhjr]ubj)rb^}rc^(jYXPowering up the EVMrd^jKjZjo\jbjr\jdjjf}re^(jk]rf^Upowering-up-the-evmrg^ajj]jh]rh^Xpowering-up-the-evmri^aji]jn]ujpNjqhjr]rj^j{XPowering up the EVMrk^rl^}rm^(jYjd^jZjb^ubaubj)rn^}ro^(jYXPower Supply specificationsrp^jKjZjo\jbjr\jdjjf}rq^(jk]rr^Upower-supply-specificationsrs^ajj]jh]rt^Xpower-supply-specificationsru^aji]jn]ujpNjqhjr]rv^j{XPower Supply specificationsrw^rx^}ry^(jYjp^jZjn^ubaubjB)rz^}r{^(jYX9.. Image:: ../../../images/CUI_Isolated_Power_Supply.png jZjo\jbjr\jdjEjf}r|^(UuriX2rtos/../../../images/CUI_Isolated_Power_Supply.pngr}^jk]jj]jh]ji]jH}r~^U*j}^sjn]ujpKsjqhjr]ubj)r^}r^(jYXPlease note that a power supply is NOT included with the AM572x Evaluation Module and needs to be purchased separately. A power supply with the following specs is needed:r^jZjo\jbjr\jdjjf}r^(jh]ji]jj]jk]jn]ujpKtjqhjr]r^j{XPlease note that a power supply is NOT included with the AM572x Evaluation Module and needs to be purchased separately. A power supply with the following specs is needed:r^r^}r^(jYj^jZj^ubaubjC)r^}r^(jYUjZjo\jbjr\jdj`jf}r^(jGX-jk]jj]jh]ji]jn]ujpKxjqhjr]r^(j/)r^}r^(jYX 12V DC outputr^jZj^jbjr\jdj2jf}r^(jh]ji]jj]jk]jn]ujpNjqhjr]r^j)r^}r^(jYj^jZj^jbjr\jdjjf}r^(jh]ji]jj]jk]jn]ujpKxjr]r^j{X 12V DC outputr^r^}r^(jYj^jZj^ubaubaubj/)r^}r^(jYX 5A outputr^jZj^jbjr\jdj2jf}r^(jh]ji]jj]jk]jn]ujpNjqhjr]r^j)r^}r^(jYj^jZj^jbjr\jdjjf}r^(jh]ji]jj]jk]jn]ujpKyjr]r^j{X 5A outputr^r^}r^(jYj^jZj^ubaubaubj/)r^}r^(jYX+Positive inner and negative outer terminalsr^jZj^jbjr\jdj2jf}r^(jh]ji]jj]jk]jn]ujpNjqhjr]r^j)r^}r^(jYj^jZj^jbjr\jdjjf}r^(jh]ji]jj]jk]jn]ujpKzjr]r^j{X+Positive inner and negative outer terminalsr^r^}r^(jYj^jZj^ubaubaubj/)r^}r^(jYX@Female barrel with 2.5mm inner diameter and 5.5mm outer diameterr^jZj^jbjr\jdj2jf}r^(jh]ji]jj]jk]jn]ujpNjqhjr]r^j)r^}r^(jYj^jZj^jbjr\jdjjf}r^(jh]ji]jj]jk]jn]ujpK{jr]r^j{X@Female barrel with 2.5mm inner diameter and 5.5mm outer diameterr^r^}r^(jYj^jZj^ubaubaubj/)r^}r^(jYXIsolated power supply jZj^jbjr\jdj2jf}r^(jh]ji]jj]jk]jn]ujpNjqhjr]r^j)r^}r^(jYXIsolated power supplyr^jZj^jbjr\jdjjf}r^(jh]ji]jj]jk]jn]ujpK|jr]r^j{XIsolated power supplyr^r^}r^(jYj^jZj^ubaubaubeubj)r^}r^(jYX!PMIC auto-off after seven secondsr^jZjo\jbjr\jdjjf}r^(jk]r^U!pmic-auto-off-after-seven-secondsr^ajj]jh]ji]jn]r^haujpNjqhjr]r^j{X!PMIC auto-off after seven secondsr^r^}r^(jYj^jZj^ubaubj)r^}r^(jYXThe Power Management Integrated Circuit (PMIC) on the TMDSEVM572X turns off the board in seven seconds after power on to work around a hardware errata. After seven seconds, the PMIC powers off unless software writes to a PMIC register to keep it on.r^jZjo\jbjr\jdjjf}r^(jh]ji]jj]jk]jn]ujpKjqhjr]r^j{XThe Power Management Integrated Circuit (PMIC) on the TMDSEVM572X turns off the board in seven seconds after power on to work around a hardware errata. After seven seconds, the PMIC powers off unless software writes to a PMIC register to keep it on.r^r^}r^(jYj^jZj^ubaubj)r^}r^(jYXIn emulation setup, the GEL file will keep the PMIC on after you connect to the A15 core on the SoC. While booting from ROM bootloader user application software, would need to keep the PMIC ON while initializing the board.r^jZjo\jbjr\jdjjf}r^(jh]ji]jj]jk]jn]ujpKjqhjr]r^j{XIn emulation setup, the GEL file will keep the PMIC on after you connect to the A15 core on the SoC. While booting from ROM bootloader user application software, would need to keep the PMIC ON while initializing the board.r^r^}r^(jYj^jZj^ubaubj)r^}r^(jYXIn Linux boot, the uboot code keeps the PMIC On and in the TI RTOS boot scenario, the SBL component provides the same functionalityr^jZjo\jbjr\jdjjf}r^(jh]ji]jj]jk]jn]ujpKjqhjr]r^j{XIn Linux boot, the uboot code keeps the PMIC On and in the TI RTOS boot scenario, the SBL component provides the same functionalityr^r^}r^(jYj^jZj^ubaubj)r^}r^(jYX**NOTE**r^jZjo\jbjr\jdjjf}r^(jh]ji]jj]jk]jn]ujpKjqhjr]r^j)r^}r^(jYj^jf}r^(jh]ji]jj]jk]jn]ujZj^jr]r^j{XNOTEr^r^}r^(jYUjZj^ubajdjubaubjC)r^}r^(jYUjZjo\jbjr\jdj`jf}r^(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]r^(j/)r^}r^(jYXTo allow quicker execution of the GEL before the PMIC shuts off, you can increase the JTAG TCLK Frequency in Advance settings of your target configuration to 15Mhz or to the maximum (20Mhz).jZj^jbjr\jdj2jf}r^(jh]ji]jj]jk]jn]ujpNjqhjr]r^j)r^}r^(jYXTo allow quicker execution of the GEL before the PMIC shuts off, you can increase the JTAG TCLK Frequency in Advance settings of your target configuration to 15Mhz or to the maximum (20Mhz).r_jZj^jbjr\jdjjf}r_(jh]ji]jj]jk]jn]ujpKjr]r_j{XTo allow quicker execution of the GEL before the PMIC shuts off, you can increase the JTAG TCLK Frequency in Advance settings of your target configuration to 15Mhz or to the maximum (20Mhz).r_r_}r_(jYj_jZj^ubaubaubj/)r_}r_(jYXWIf the above CCS connect sequence does not work in the first attempt, it means that the PMIC switched off before the GEL could initialize I2C and modify the PMIC settings. In that case, the connection has failed, hit connect in CCS debug view without removing the power cable and then immediately hit the power switch besides the power plug. jZj^jbjr\jdj2jf}r_(jh]ji]jj]jk]jn]ujpNjqhjr]r _j)r _}r _(jYXUIf the above CCS connect sequence does not work in the first attempt, it means that the PMIC switched off before the GEL could initialize I2C and modify the PMIC settings. In that case, the connection has failed, hit connect in CCS debug view without removing the power cable and then immediately hit the power switch besides the power plug.r _jZj_jbjr\jdjjf}r _(jh]ji]jj]jk]jn]ujpKjr]r_j{XUIf the above CCS connect sequence does not work in the first attempt, it means that the PMIC switched off before the GEL could initialize I2C and modify the PMIC settings. In that case, the connection has failed, hit connect in CCS debug view without removing the power cable and then immediately hit the power switch besides the power plug.r_r_}r_(jYj _jZj _ubaubaubeubj)r_}r_(jYXConnect Power to the EVMr_jZjo\jbjr\jdjjf}r_(jk]r_Uconnect-power-to-the-evmr_ajj]jh]ji]jn]r_haujpNjqhjr]r_j{XConnect Power to the EVMr_r_}r_(jYj_jZj_ubaubjB)r_}r_(jYX... Image:: ../../../images/Push_Power_EVM.png jZjo\jbjr\jdjEjf}r_(UuriX'rtos/../../../images/Push_Power_EVM.pngr _jk]jj]jh]ji]jH}r!_U*j _sjn]ujpKjqhjr]ubj)r"_}r#_(jYX CCS Setupr$_jKjZjo\jbjr\jdjjf}r%_(jk]r&_U ccs-setupr'_ajj]jh]r(_X ccs-setupr)_aji]jn]ujpNjqhjr]r*_j{X CCS Setupr+_r,_}r-_(jYj$_jZj"_ubaubj)r._}r/_(jYX6There are two scenarios while connecting to the EVM :r0_jZjo\jbjr\jdjjf}r1_(jh]ji]jj]jk]jn]ujpKjqhjr]r2_j{X6There are two scenarios while connecting to the EVM :r3_r4_}r5_(jYj0_jZj._ubaubjC)r6_}r7_(jYUjZjo\jbjr\jdj`jf}r8_(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]r9_(j/)r:_}r;_(jYX?**Connect to EVM without a SD card boot image to boot the EVM**r<_jZj6_jbjr\jdj2jf}r=_(jh]ji]jj]jk]jn]ujpNjqhjr]r>_j)r?_}r@_(jYj<_jZj:_jbjr\jdjjf}rA_(jh]ji]jj]jk]jn]ujpKjr]rB_j)rC_}rD_(jYj<_jf}rE_(jh]ji]jj]jk]jn]ujZj?_jr]rF_j{X;Connect to EVM without a SD card boot image to boot the EVMrG_rH_}rI_(jYUjZjC_ubajdjubaubaubj/)rJ_}rK_(jYX<**Connect to EVM after booting an image from the SD card**. jZj6_jbjr\jdj2jf}rL_(jh]ji]jj]jk]jn]ujpNjqhjr]rM_j)rN_}rO_(jYX;**Connect to EVM after booting an image from the SD card**.jZjJ_jbjr\jdjjf}rP_(jh]ji]jj]jk]jn]ujpKjr]rQ_(j)rR_}rS_(jYX:**Connect to EVM after booting an image from the SD card**jf}rT_(jh]ji]jj]jk]jn]ujZjN_jr]rU_j{X6Connect to EVM after booting an image from the SD cardrV_rW_}rX_(jYUjZjR_ubajdjubj{X.rY_}rZ_(jYX.jZjN_ubeubaubeubj)r[_}r\_(jYX$Connect without a SD card boot imager]_jKjZjo\jbjr\jdjjf}r^_(jk]r__U$connect-without-a-sd-card-boot-imager`_ajj]jh]ra_X$connect-without-a-sd-card-boot-imagerb_aji]jn]ujpNjqhjr]rc_j{X$Connect without a SD card boot imagerd_re_}rf_(jYj]_jZj[_ubaubj)rg_}rh_(jYX&Configuring target configuration filesri_jKjZjo\jbjr\jdjjf}rj_(jk]rk_U&configuring-target-configuration-filesrl_ajj]jh]rm_X&configuring-target-configuration-filesrn_aji]jn]ujpNjqhjr]ro_j{X&Configuring target configuration filesrp_rq_}rr_(jYji_jZjg_ubaubj)rs_}rt_(jYXLaunch CCS and create new target configuration(File->New->Target Configuration file) as shown in the images below and provide appropriate name to the configuration. Select Spectrum digital XDS200 emulator and target as GPEVM\_AM572x\_SiRevA.jZjo\jbjr\jdjjf}ru_(jh]ji]jj]jk]jn]ujpKjqhjr]rv_j{XLaunch CCS and create new target configuration(File->New->Target Configuration file) as shown in the images below and provide appropriate name to the configuration. Select Spectrum digital XDS200 emulator and target as GPEVM_AM572x_SiRevA.rw_rx_}ry_(jYXLaunch CCS and create new target configuration(File->New->Target Configuration file) as shown in the images below and provide appropriate name to the configuration. Select Spectrum digital XDS200 emulator and target as GPEVM\_AM572x\_SiRevA.jZjs_ubaubj)rz_}r{_(jYX **Note:** For older revisions of CCSv6, If you don\`t find the GPEVM\_AM572x\_SiRevA target make sure you have installed the CCSv6 package with support for Sitara Processors and done the software update correctly from the Help Menu to get the latest Sitara CSP package.jZjo\jbjr\jdjjf}r|_(jh]ji]jj]jk]jn]ujpKjqhjr]r}_(j)r~_}r_(jYX **Note:**jf}r_(jh]ji]jj]jk]jn]ujZjz_jr]r_j{XNote:r_r_}r_(jYUjZj~_ubajdjubj{X For older revisions of CCSv6, If you don`t find the GPEVM_AM572x_SiRevA target make sure you have installed the CCSv6 package with support for Sitara Processors and done the software update correctly from the Help Menu to get the latest Sitara CSP package.r_r_}r_(jYX For older revisions of CCSv6, If you don\`t find the GPEVM\_AM572x\_SiRevA target make sure you have installed the CCSv6 package with support for Sitara Processors and done the software update correctly from the Help Menu to get the latest Sitara CSP package.jZjz_ubeubjB)r_}r_(jYX:.. Image:: ../../../images/GPEVM_Target_configuration.jpg jZjo\jbjr\jdjEjf}r_(UuriX3rtos/../../../images/GPEVM_Target_configuration.jpgr_jk]jj]jh]ji]jH}r_U*j_sjn]ujpKjqhjr]ubjZ)r_}r_(jYUjZjo\jbjr\jdj]jf}r_(jh]ji]jj]jk]jn]ujpKjqhjr]r_j`)r_}r_(jYUjcKjZj_jbjr\jdjpjf}r_(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r_}r_(jYXIn advance settings, make sure that the gel files are populated correctly. The following GEL files and their corresponding cores are provided below:r_jZjo\jbjr\jdjjf}r_(jh]ji]jj]jk]jn]ujpKjqhjr]r_j{XIn advance settings, make sure that the gel files are populated correctly. The following GEL files and their corresponding cores are provided below:r_r_}r_(jYj_jZj_ubaubjC)r_}r_(jYUjZjo\jbjr\jdj`jf}r_(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]r_(j/)r_}r_(jYX)IcePick\_D: AM572x\_ICEPickD\_Utility.gelr_jZj_jbjr\jdj2jf}r_(jh]ji]jj]jk]jn]ujpNjqhjr]r_j)r_}r_(jYj_jZj_jbjr\jdjjf}r_(jh]ji]jj]jk]jn]ujpKjr]r_j{X&IcePick_D: AM572x_ICEPickD_Utility.gelr_r_}r_(jYX)IcePick\_D: AM572x\_ICEPickD\_Utility.geljZj_ubaubaubj/)r_}r_(jYX*CS\_DAP\_DebugSS: AM572x\_dap\_startup.gelr_jZj_jbjr\jdj2jf}r_(jh]ji]jj]jk]jn]ujpNjqhjr]r_j)r_}r_(jYj_jZj_jbjr\jdjjf}r_(jh]ji]jj]jk]jn]ujpKjr]r_j{X&CS_DAP_DebugSS: AM572x_dap_startup.gelr_r_}r_(jYX*CS\_DAP\_DebugSS: AM572x\_dap\_startup.geljZj_ubaubaubj/)r_}r_(jYX-CS\_DAP\_PC: AM572x\_CS\_DAP\_PC\_Utility.gelr_jZj_jbjr\jdj2jf}r_(jh]ji]jj]jk]jn]ujpNjqhjr]r_j)r_}r_(jYj_jZj_jbjr\jdjjf}r_(jh]ji]jj]jk]jn]ujpKjr]r_j{X'CS_DAP_PC: AM572x_CS_DAP_PC_Utility.gelr_r_}r_(jYX-CS\_DAP\_PC: AM572x\_CS\_DAP\_PC\_Utility.geljZj_ubaubaubj/)r_}r_(jYX,A15\_0: AM572x\_cortexa15\_cpu0\_startup.gelr_jZj_jbjr\jdj2jf}r_(jh]ji]jj]jk]jn]ujpNjqhjr]r_j)r_}r_(jYj_jZj_jbjr\jdjjf}r_(jh]ji]jj]jk]jn]ujpKjr]r_j{X(A15_0: AM572x_cortexa15_cpu0_startup.gelr_r_}r_(jYX,A15\_0: AM572x\_cortexa15\_cpu0\_startup.geljZj_ubaubaubj/)r_}r_(jYX,A15\_1: AM572x\_cortexa15\_cpu1\_startup.gelr_jZj_jbjr\jdj2jf}r_(jh]ji]jj]jk]jn]ujpNjqhjr]r_j)r_}r_(jYj_jZj_jbjr\jdjjf}r_(jh]ji]jj]jk]jn]ujpKjr]r_j{X(A15_1: AM572x_cortexa15_cpu1_startup.gelr_r_}r_(jYX,A15\_1: AM572x\_cortexa15\_cpu1\_startup.geljZj_ubaubaubj/)r_}r_(jYX!C66x\_0: AM572x\_dsp\_startup.gelr_jZj_jbjr\jdj2jf}r_(jh]ji]jj]jk]jn]ujpNjqhjr]r_j)r_}r_(jYj_jZj_jbjr\jdjjf}r_(jh]ji]jj]jk]jn]ujpKjr]r_j{XC66x_0: AM572x_dsp_startup.gelr_r_}r_(jYX!C66x\_0: AM572x\_dsp\_startup.geljZj_ubaubaubj/)r_}r_(jYX!C66x\_1: AM572x\_dsp\_startup.gelr_jZj_jbjr\jdj2jf}r_(jh]ji]jj]jk]jn]ujpNjqhjr]r_j)r_}r_(jYj_jZj_jbjr\jdjjf}r_(jh]ji]jj]jk]jn]ujpKjr]r_j{XC66x_1: AM572x_dsp_startup.gelr_r_}r_(jYX!C66x\_1: AM572x\_dsp\_startup.geljZj_ubaubaubj/)r_}r_(jYX-M4\_IPU\_1\_C0: AM572x\_cortexM4\_startup.gelr_jZj_jbjr\jdj2jf}r_(jh]ji]jj]jk]jn]ujpNjqhjr]r_j)r_}r_(jYj_jZj_jbjr\jdjjf}r_(jh]ji]jj]jk]jn]ujpKjr]r_j{X(M4_IPU_1_C0: AM572x_cortexM4_startup.gelr_r_}r_(jYX-M4\_IPU\_1\_C0: AM572x\_cortexM4\_startup.geljZj_ubaubaubj/)r`}r`(jYX-M4\_IPU\_1\_C1: AM572x\_cortexM4\_startup.gelr`jZj_jbjr\jdj2jf}r`(jh]ji]jj]jk]jn]ujpNjqhjr]r`j)r`}r`(jYj`jZj`jbjr\jdjjf}r`(jh]ji]jj]jk]jn]ujpKjr]r`j{X(M4_IPU_1_C1: AM572x_cortexM4_startup.gelr `r `}r `(jYX-M4\_IPU\_1\_C1: AM572x\_cortexM4\_startup.geljZj`ubaubaubj/)r `}r `(jYX-M4\_IPU\_2\_C0: AM572x\_cortexM4\_startup.gelr`jZj_jbjr\jdj2jf}r`(jh]ji]jj]jk]jn]ujpNjqhjr]r`j)r`}r`(jYj`jZj `jbjr\jdjjf}r`(jh]ji]jj]jk]jn]ujpKjr]r`j{X(M4_IPU_2_C0: AM572x_cortexM4_startup.gelr`r`}r`(jYX-M4\_IPU\_2\_C0: AM572x\_cortexM4\_startup.geljZj`ubaubaubj/)r`}r`(jYX-M4\_IPU\_2\_C1: AM572x\_cortexM4\_startup.gelr`jZj_jbjr\jdj2jf}r`(jh]ji]jj]jk]jn]ujpNjqhjr]r`j)r`}r`(jYj`jZj`jbjr\jdjjf}r`(jh]ji]jj]jk]jn]ujpKjr]r `j{X(M4_IPU_2_C1: AM572x_cortexM4_startup.gelr!`r"`}r#`(jYX-M4\_IPU\_2\_C1: AM572x\_cortexM4\_startup.geljZj`ubaubaubj/)r$`}r%`(jYX"IVAHD: AM572x\_ivahd\_startup.gel jZj_jbjr\jdj2jf}r&`(jh]ji]jj]jk]jn]ujpNjqhjr]r'`j)r(`}r)`(jYX!IVAHD: AM572x\_ivahd\_startup.geljZj$`jbjr\jdjjf}r*`(jh]ji]jj]jk]jn]ujpKjr]r+`j{XIVAHD: AM572x_ivahd_startup.gelr,`r-`}r.`(jYX!IVAHD: AM572x\_ivahd\_startup.geljZj(`ubaubaubeubjZ)r/`}r0`(jYUjZjo\jbjr\jdj]jf}r1`(jh]ji]jj]jk]jn]ujpKjqhjr]r2`j`)r3`}r4`(jYUjcKjZj/`jbjr\jdjpjf}r5`(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r6`}r7`(jYXConnecting to targetr8`jKjZjo\jbjr\jdjjf}r9`(jk]r:`Uconnecting-to-targetr;`ajj]jh]r<`Xconnecting-to-targetr=`aji]jn]ujpNjqhjr]r>`j{XConnecting to targetr?`r@`}rA`(jYj8`jZj6`ubaubj)rB`}rC`(jYXz**Step1 :** Download Code composer Studio and AM572x Sitara CSP package as described in the wiki article mentioned below:jZjo\jbjr\jdjjf}rD`(jh]ji]jj]jk]jn]ujpKjqhjr]rE`(j)rF`}rG`(jYX **Step1 :**jf}rH`(jh]ji]jj]jk]jn]ujZjB`jr]rI`j{XStep1 :rJ`rK`}rL`(jYUjZjF`ubajdjubj{Xn Download Code composer Studio and AM572x Sitara CSP package as described in the wiki article mentioned below:rM`rN`}rO`(jYXn Download Code composer Studio and AM572x Sitara CSP package as described in the wiki article mentioned below:jZjB`ubeubj)rP`}rQ`(jYX`Install Code composer Studio v6 for AM572x `__rR`jZjo\jbjr\jdjjf}rS`(jh]ji]jj]jk]jn]ujpKjqhjr]rT`j)rU`}rV`(jYjR`jf}rW`(UnameX*Install Code composer Studio v6 for AM572xjXehttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_Getting_Started_Guide#Code_Composer_Studiojk]jj]jh]ji]jn]ujZjP`jr]rX`j{X*Install Code composer Studio v6 for AM572xrY`rZ`}r[`(jYUjZjU`ubajdjubaubj)r\`}r]`(jYX**Step2:** AM572x EVM doesn\`t have any boot switches to configure for emulation mode. so configure the boot switches to SD Boot Mode. Dont Populate the uSD card when the intent is to connect and load code over emulator and not to boot the device using uSD card.jZjo\jbjr\jdjjf}r^`(jh]ji]jj]jk]jn]ujpKjqhjr]r_`(j)r``}ra`(jYX **Step2:**jf}rb`(jh]ji]jj]jk]jn]ujZj\`jr]rc`j{XStep2:rd`re`}rf`(jYUjZj``ubajdjubj{X AM572x EVM doesn`t have any boot switches to configure for emulation mode. so configure the boot switches to SD Boot Mode. Dont Populate the uSD card when the intent is to connect and load code over emulator and not to boot the device using uSD card.rg`rh`}ri`(jYX AM572x EVM doesn\`t have any boot switches to configure for emulation mode. so configure the boot switches to SD Boot Mode. Dont Populate the uSD card when the intent is to connect and load code over emulator and not to boot the device using uSD card.jZj\`ubeubj)rj`}rk`(jYX**Step3:** Connect an XDS200 Emulator to emulation pins at the back of the GP EVM as shown in section.\ `Connecting\_Emulator `__jZjo\jbjr\jdjjf}rl`(jh]ji]jj]jk]jn]ujpKjqhjr]rm`(j)rn`}ro`(jYX **Step3:**jf}rp`(jh]ji]jj]jk]jn]ujZjj`jr]rq`j{XStep3:rr`rs`}rt`(jYUjZjn`ubajdjubj{X\ Connect an XDS200 Emulator to emulation pins at the back of the GP EVM as shown in section.ru`rv`}rw`(jYX^ Connect an XDS200 Emulator to emulation pins at the back of the GP EVM as shown in section.\ jZjj`ubj)rx`}ry`(jYXs`Connecting\_Emulator `__jf}rz`(UnameXConnecting_EmulatorjXXhttp://processors.wiki.ti.com/index.php/AM572x_GP_EVM_Hardware_Setup#Connecting_Emulatorjk]jj]jh]ji]jn]ujZjj`jr]r{`j{XConnecting_Emulatorr|`r}`}r~`(jYUjZjx`ubajdjubeubj)r`}r`(jYX_**Step4:** Launch CCS and create new target configuration as discussed in the previous section.jZjo\jbjr\jdjjf}r`(jh]ji]jj]jk]jn]ujpKjqhjr]r`(j)r`}r`(jYX **Step4:**jf}r`(jh]ji]jj]jk]jn]ujZj`jr]r`j{XStep4:r`r`}r`(jYUjZj`ubajdjubj{XU Launch CCS and create new target configuration as discussed in the previous section.r`r`}r`(jYXU Launch CCS and create new target configuration as discussed in the previous section.jZj`ubeubjZ)r`}r`(jYUjZjo\jbjr\jdj]jf}r`(jh]ji]jj]jk]jn]ujpKjqhjr]r`(j`)r`}r`(jYUjcKjZj`jbjr\jdjpjf}r`(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)r`}r`(jYX&**Step5**: Launch Target configuration you just created. AM572x is an ARM master boot device so connect to the A15\_0 first. It is also recommended that you do a CPU reset from (Run->Reset->CPU Reset) Menu on the A15 to put it in a clean state as the EVM is designed to come up in SD boot mode.jcKjZj`jbjr\jdjpjf}r`(jh]ji]jj]jk]jn]ujpKjqhjr]r`(j)r`}r`(jYX **Step5**jf}r`(jh]ji]jj]jk]jn]ujZj`jr]r`j{XStep5r`r`}r`(jYUjZj`ubajdjubj{X: Launch Target configuration you just created. AM572x is an ARM master boot device so connect to the A15_0 first. It is also recommended that you do a CPU reset from (Run->Reset->CPU Reset) Menu on the A15 to put it in a clean state as the EVM is designed to come up in SD boot mode.r`r`}r`(jYX: Launch Target configuration you just created. AM572x is an ARM master boot device so connect to the A15\_0 first. It is also recommended that you do a CPU reset from (Run->Reset->CPU Reset) Menu on the A15 to put it in a clean state as the EVM is designed to come up in SD boot mode.jZj`ubeubeubjZ)r`}r`(jYUjZjo\jbjr\jdj]jf}r`(jh]ji]jj]jk]jn]ujpKjqhjr]r`(j`)r`}r`(jYUjcKjZj`jbjr\jdjpjf}r`(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)r`}r`(jYX**Note: Keep in mind the PMIC shutdown issue discussed in previous section while connecting to the target cores. Due to the PMIC shutdown issue, users need to connect to A15\_0 as soon as you push the power button to enable power to the SoC.**jcKjZj`jbjr\jdjpjf}r`(jh]ji]jj]jk]jn]ujpKjqhjr]r`j)r`}r`(jYX**Note: Keep in mind the PMIC shutdown issue discussed in previous section while connecting to the target cores. Due to the PMIC shutdown issue, users need to connect to A15\_0 as soon as you push the power button to enable power to the SoC.**jf}r`(jh]ji]jj]jk]jn]ujZj`jr]r`j{XNote: Keep in mind the PMIC shutdown issue discussed in previous section while connecting to the target cores. Due to the PMIC shutdown issue, users need to connect to A15_0 as soon as you push the power button to enable power to the SoC.r`r`}r`(jYUjZj`ubajdjubaubeubjZ)r`}r`(jYUjZjo\jbjr\jdj]jf}r`(jh]ji]jj]jk]jn]ujpKjqhjr]r`(j`)r`}r`(jYUjcKjZj`jbjr\jdjpjf}r`(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)r`}r`(jYX4Complete GEL log from A15 connect is provided below:r`jcKjZj`jbjr\jdjpjf}r`(jh]ji]jj]jk]jn]ujpKjqhjr]r`j{X4Complete GEL log from A15 connect is provided below:r`r`}r`(jYj`jZj`ubaubeubj)r`}r`(jYXbIcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset. IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset. CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs <<<--- CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress... CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<---- CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> --- CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<---- CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do. CortexA15_0: GEL Output: --->>> AM572x GP EVM <<<--- CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence Begins ... <<<--- CortexA15_0: GEL Output: --->>> I2C Init <<<--- CortexA15_0: GEL Output: --->>> AM572x Begin MMC2 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> AM572x End MMC2 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> AM572x PG2.0 GP device <<<--- CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<--- CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: Cortex A15 DPLL is already locked, now unlocking... CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 is DONE! CortexA15_0: GEL Output: IVA DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: IVA DPLL OPP 0 is DONE! CortexA15_0: GEL Output: PER DPLL OPP 0 clock config in progress... CortexA15_0: GEL Output: PER DPLL already locked, now unlocking CortexA15_0: GEL Output: PER DPLL OPP 0 is DONE! CortexA15_0: GEL Output: CORE DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: CORE DPLL OPP already locked, now unlocking.... CortexA15_0: GEL Output: CORE DPLL OPP 0 is DONE! CortexA15_0: GEL Output: ABE DPLL OPP 0 clock config in progress... CortexA15_0: GEL Output: ABE DPLL OPP 0 is DONE! CortexA15_0: GEL Output: GMAC DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: GMAC DPLL OPP 0 is DONE! CortexA15_0: GEL Output: GPU DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: GPU DPLL OPP 0 is DONE! CortexA15_0: GEL Output: DSP DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: DSP DPLL OPP 0 is DONE! CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 is DONE! CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<--- CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<--- CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<--- CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in progress... CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in DONE! CortexA15_0: GEL Output: Launch full leveling CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers CortexA15_0: GEL Output: as per HW leveling output CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from CortexA15_0: GEL Output: PHY_STATUSx registers CortexA15_0: GEL Output: Launch full leveling CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers CortexA15_0: GEL Output: as per HW leveling output CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from CortexA15_0: GEL Output: PHY_STATUSx registers CortexA15_0: GEL Output: Two EMIFs in interleaved mode - (2GB total) CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence DONE !!!!! <<<--- CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: >> START ==> Enable L3 Clk CortexA15_0: GEL Output: >> Change Suspend source for GPTimer5 to DSP1 CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<--- CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---jZjo\jbjr\jdjjf}r`(jjjk]jj]jh]ji]jn]ujpMjqhjr]r`j{XbIcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset. IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset. CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs <<<--- CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress... CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<---- CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> --- CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<---- CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do. CortexA15_0: GEL Output: --->>> AM572x GP EVM <<<--- CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence Begins ... <<<--- CortexA15_0: GEL Output: --->>> I2C Init <<<--- CortexA15_0: GEL Output: --->>> AM572x Begin MMC2 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> AM572x End MMC2 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> AM572x PG2.0 GP device <<<--- CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<--- CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: Cortex A15 DPLL is already locked, now unlocking... CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 is DONE! CortexA15_0: GEL Output: IVA DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: IVA DPLL OPP 0 is DONE! CortexA15_0: GEL Output: PER DPLL OPP 0 clock config in progress... CortexA15_0: GEL Output: PER DPLL already locked, now unlocking CortexA15_0: GEL Output: PER DPLL OPP 0 is DONE! CortexA15_0: GEL Output: CORE DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: CORE DPLL OPP already locked, now unlocking.... CortexA15_0: GEL Output: CORE DPLL OPP 0 is DONE! CortexA15_0: GEL Output: ABE DPLL OPP 0 clock config in progress... CortexA15_0: GEL Output: ABE DPLL OPP 0 is DONE! CortexA15_0: GEL Output: GMAC DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: GMAC DPLL OPP 0 is DONE! CortexA15_0: GEL Output: GPU DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: GPU DPLL OPP 0 is DONE! CortexA15_0: GEL Output: DSP DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: DSP DPLL OPP 0 is DONE! CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 is DONE! CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<--- CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<--- CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<--- CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in progress... CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in DONE! CortexA15_0: GEL Output: Launch full leveling CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers CortexA15_0: GEL Output: as per HW leveling output CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from CortexA15_0: GEL Output: PHY_STATUSx registers CortexA15_0: GEL Output: Launch full leveling CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers CortexA15_0: GEL Output: as per HW leveling output CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from CortexA15_0: GEL Output: PHY_STATUSx registers CortexA15_0: GEL Output: Two EMIFs in interleaved mode - (2GB total) CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence DONE !!!!! <<<--- CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: >> START ==> Enable L3 Clk CortexA15_0: GEL Output: >> Change Suspend source for GPTimer5 to DSP1 CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<--- CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---r`r`}r`(jYUjZj`ubaubjZ)r`}r`(jYUjZjo\jbjr\jdj]jf}r`(jh]ji]jj]jk]jn]ujpMGjqhjr]r`j`)r`}r`(jYUjcKjZj`jbjr\jdjpjf}r`(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r`}r`(jYXMulti-core Initializationr`jZjo\jbjr\jdjjf}r`(jk]r`Umulti-core-initializationr`ajj]jh]ji]jn]r`haujpNjqhjr]r`j{XMulti-core Initializationr`r`}r`(jYj`jZj`ubaubj)r`}r`(jYXAfter connecting to the boot master core -- typically the ARM core -- you may need to connect to a slave core in order to run code. Depending on your SOC, the slave core can ber`jZjo\jbjr\jdjjf}r`(jh]ji]jj]jk]jn]ujpMLjqhjr]r`j{XAfter connecting to the boot master core -- typically the ARM core -- you may need to connect to a slave core in order to run code. Depending on your SOC, the slave core can ber`r`}r`(jYj`jZj`ubaubjC)r`}r`(jYUjZjo\jbjr\jdj`jf}r`(jGX-jk]jj]jh]ji]jn]ujpMPjqhjr]r`(j/)r`}r`(jYXDSP C66xr`jZj`jbjr\jdj2jf}r`(jh]ji]jj]jk]jn]ujpNjqhjr]r`j)r`}r`(jYj`jZj`jbjr\jdjjf}r`(jh]ji]jj]jk]jn]ujpMPjr]r`j{XDSP C66xr`r`}r`(jYj`jZj`ubaubaubj/)r`}r`(jYXARM M4r`jZj`jbjr\jdj2jf}r`(jh]ji]jj]jk]jn]ujpNjqhjr]r`j)r`}r`(jYj`jZj`jbjr\jdjjf}r`(jh]ji]jj]jk]jn]ujpMQjr]r`j{XARM M4r`r`}r`(jYj`jZj`ubaubaubj/)ra}ra(jYXPRUSSrajZj`jbjr\jdj2jf}ra(jh]ji]jj]jk]jn]ujpNjqhjr]raj)ra}ra(jYjajZjajbjr\jdjjf}ra(jh]ji]jj]jk]jn]ujpMRjr]raj{XPRUSSr ar a}r a(jYjajZjaubaubaubj/)r a}r a(jYXIVAHD jZj`jbjr\jdj2jf}ra(jh]ji]jj]jk]jn]ujpNjqhjr]raj)ra}ra(jYXIVAHDrajZj ajbjr\jdjjf}ra(jh]ji]jj]jk]jn]ujpMSjr]raj{XIVAHDrara}ra(jYjajZjaubaubaubeubj)ra}ra(jYXTypically the slave cores will wait in reset state until the master core wakes up the slave core to run code. To connect to the slave core on AM57x, go to **Scripts** menu in CCS Debug View and under **AM572x MULTICORE Initialization** enable the corresponding sub system clock. For example, enable ``DSP11SSClkEnable_API`` for the first DSP core. After running the clock enable option, you can connect to the core.jZjo\jbjr\jdjjf}ra(jh]ji]jj]jk]jn]ujpMUjqhjr]ra(j{XTypically the slave cores will wait in reset state until the master core wakes up the slave core to run code. To connect to the slave core on AM57x, go to rara}ra(jYXTypically the slave cores will wait in reset state until the master core wakes up the slave core to run code. To connect to the slave core on AM57x, go to jZjaubj)ra}r a(jYX **Scripts**jf}r!a(jh]ji]jj]jk]jn]ujZjajr]r"aj{XScriptsr#ar$a}r%a(jYUjZjaubajdjubj{X" menu in CCS Debug View and under r&ar'a}r(a(jYX" menu in CCS Debug View and under jZjaubj)r)a}r*a(jYX#**AM572x MULTICORE Initialization**jf}r+a(jh]ji]jj]jk]jn]ujZjajr]r,aj{XAM572x MULTICORE Initializationr-ar.a}r/a(jYUjZj)aubajdjubj{X@ enable the corresponding sub system clock. For example, enable r0ar1a}r2a(jYX@ enable the corresponding sub system clock. For example, enable jZjaubji')r3a}r4a(jYX``DSP11SSClkEnable_API``jf}r5a(jh]ji]jj]jk]jn]ujZjajr]r6aj{XDSP11SSClkEnable_APIr7ar8a}r9a(jYUjZj3aubajdjq'ubj{X\ for the first DSP core. After running the clock enable option, you can connect to the core.r:ar;a}ra(jYX0.. Image:: ../../../images/Multicore-Enable.jpg jZjo\jbjr\jdjEjf}r?a(UuriX)rtos/../../../images/Multicore-Enable.jpgr@ajk]jj]jh]ji]jH}rAaU*j@asjn]ujpM]jqhjr]ubj)rBa}rCa(jYXIf you wish to run TI RTOS code on DSP, please also run the `Timer Suspend Control Options `__.jZjo\jbjr\jdjjf}rDa(jh]ji]jj]jk]jn]ujpM^jqhjr]rEa(j{X<If you wish to run TI RTOS code on DSP, please also run the rFarGa}rHa(jYX<If you wish to run TI RTOS code on DSP, please also run the jZjBaubj)rIa}rJa(jYX`Timer Suspend Control Options `__jf}rKa(UnameXTimer Suspend Control OptionsjXjhttp://processors.wiki.ti.com/index.php/AM572x_GP_EVM_Hardware_Setup#Timer_Suspend_Control_Options_for_DSPjk]jj]jh]ji]jn]ujZjBajr]rLaj{XTimer Suspend Control OptionsrMarNa}rOa(jYUjZjIaubajdjubj{X.rPa}rQa(jYX.jZjBaubeubjZ)rRa}rSa(jYUjZjo\jbjr\jdj]jf}rTa(jh]ji]jj]jk]jn]ujpMbjqhjr]rUaj`)rVa}rWa(jYUjcKjZjRajbjr\jdjpjf}rXa(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)rYa}rZa(jYX"Connect after booting from SD cardr[ajZjo\jbjr\jdjjf}r\a(jk]r]aU"connect-after-booting-from-sd-cardr^aajj]jh]ji]jn]r_ahaujpNjqhjr]r`aj{X"Connect after booting from SD cardraarba}rca(jYj[ajZjYaubaubj)rda}rea(jYXWhen you boot an image from the SD card, the secondary boot loader will configure the device clocks, DDR and wake up the slave cores on the AM572x processor on GP EVM hence you don\`t need the GEL initialization scripts to redo the clock and DDR settings.jZjo\jbjr\jdjjf}rfa(jh]ji]jj]jk]jn]ujpMgjqhjr]rgaj{XWhen you boot an image from the SD card, the secondary boot loader will configure the device clocks, DDR and wake up the slave cores on the AM572x processor on GP EVM hence you don`t need the GEL initialization scripts to redo the clock and DDR settings.rharia}rja(jYXWhen you boot an image from the SD card, the secondary boot loader will configure the device clocks, DDR and wake up the slave cores on the AM572x processor on GP EVM hence you don\`t need the GEL initialization scripts to redo the clock and DDR settings.jZjdaubaubj)rka}rla(jYX**Note:** If you are running the Image processing demo or have created an SD card with the SBL (mlo) for booting the board then please follow the following procedurejZjo\jbjr\jdjjf}rma(jh]ji]jj]jk]jn]ujpMljqhjr]rna(j)roa}rpa(jYX **Note:**jf}rqa(jh]ji]jj]jk]jn]ujZjkajr]rraj{XNote:rsarta}rua(jYUjZjoaubajdjubj{X If you are running the Image processing demo or have created an SD card with the SBL (mlo) for booting the board then please follow the following procedurervarwa}rxa(jYX If you are running the Image processing demo or have created an SD card with the SBL (mlo) for booting the board then please follow the following procedurejZjkaubeubj)rya}rza(jYX&Configuring target configuration filesr{ajZjo\jbjr\jdjjf}r|a(jk]r}aU(configuring-target-configuration-files-1r~aajj]jh]ji]jn]rahaujpNjqhjr]raj{X&Configuring target configuration filesrara}ra(jYj{ajZjyaubaubj)ra}ra(jYX;Launch CCS and create new target configuration(File->New->Target Configuration file) as shown in the images below and provide appropriate name to the configuration. Select Spectrum digital XDS200 emulator and target as AM5728\_RevA. This target setting will not populate the GEL files when you connect to the targetjZjo\jbjr\jdjjf}ra(jh]ji]jj]jk]jn]ujpMsjqhjr]raj{X:Launch CCS and create new target configuration(File->New->Target Configuration file) as shown in the images below and provide appropriate name to the configuration. Select Spectrum digital XDS200 emulator and target as AM5728_RevA. This target setting will not populate the GEL files when you connect to the targetrara}ra(jYX;Launch CCS and create new target configuration(File->New->Target Configuration file) as shown in the images below and provide appropriate name to the configuration. Select Spectrum digital XDS200 emulator and target as AM5728\_RevA. This target setting will not populate the GEL files when you connect to the targetjZjaubaubj)ra}ra(jYX**Note:** If you don\`t find the AM572x\_RevA target make sure you have installed the CCSv6.1.1 package and done the software update correctly.jZjo\jbjr\jdjjf}ra(jh]ji]jj]jk]jn]ujpMyjqhjr]ra(j)ra}ra(jYX **Note:**jf}ra(jh]ji]jj]jk]jn]ujZjajr]raj{XNote:rara}ra(jYUjZjaubajdjubj{X If you don`t find the AM572x_RevA target make sure you have installed the CCSv6.1.1 package and done the software update correctly.rara}ra(jYX If you don\`t find the AM572x\_RevA target make sure you have installed the CCSv6.1.1 package and done the software update correctly.jZjaubeubjZ)ra}ra(jYUjZjo\jbjr\jdj]jf}ra(jh]ji]jj]jk]jn]ujpM|jqhjr]raj`)ra}ra(jYUjcKjZjajbjr\jdjpjf}ra(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjB)ra}ra(jYXB.. Image:: ../../../images/COnfigure_targetConfigFiles_SDboot.png jZjo\jbjr\jdjEjf}ra(UuriX;rtos/../../../images/COnfigure_targetConfigFiles_SDboot.pngrajk]jj]jh]ji]jH}raU*jasjn]ujpMjqhjr]ubj)ra}ra(jYXGEL file optionsrajZjo\jbjr\jdjjf}ra(jk]raUgel-file-optionsraajj]jh]ji]jn]raj0aujpNjqhjr]raj{XGEL file optionsrara}ra(jYjajZjaubaubj)ra}ra(jYXChanging SoC Operating pointrajZjo\jbjr\jdjjf}ra(jk]raUchanging-soc-operating-pointraajj]jh]ji]jn]rajaujpNjqhjr]raj{XChanging SoC Operating pointrara}ra(jYjajZjaubaubj)ra}ra(jYXkThe GEL file for setting the clocks on the SoC provides 3 Operating points OPP\_NOM, OPP\_OD and OPP\_HIGH.jZjo\jbjr\jdjjf}ra(jh]ji]jj]jk]jn]ujpMjqhjr]raj{XhThe GEL file for setting the clocks on the SoC provides 3 Operating points OPP_NOM, OPP_OD and OPP_HIGH.rara}ra(jYXkThe GEL file for setting the clocks on the SoC provides 3 Operating points OPP\_NOM, OPP\_OD and OPP\_HIGH.jZjaubaubj)ra}ra(jYX**OPP\_NOM PLL Settings:**rajZjo\jbjr\jdjjf}ra(jh]ji]jj]jk]jn]ujpMjqhjr]raj)ra}ra(jYX**OPP\_NOM PLL Settings:**jf}ra(jh]ji]jj]jk]jn]ujZjajr]raj{XOPP_NOM PLL Settings:rara}ra(jYUjZjaubajdjubaubjC)ra}ra(jYUjZjo\jbjr\jdj`jf}ra(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]ra(j/)ra}ra(jYXARM = 1000 MHzrajZjajbjr\jdj2jf}ra(jh]ji]jj]jk]jn]ujpNjqhjr]raj)ra}ra(jYjajZjajbjr\jdjjf}ra(jh]ji]jj]jk]jn]ujpMjr]raj{XARM = 1000 MHzrara}ra(jYjajZjaubaubaubj/)ra}ra(jYX DSP = 600 MhzrajZjajbjr\jdj2jf}ra(jh]ji]jj]jk]jn]ujpNjqhjr]raj)ra}ra(jYjajZjajbjr\jdjjf}ra(jh]ji]jj]jk]jn]ujpMjr]raj{X DSP = 600 Mhzrara}ra(jYjajZjaubaubaubj/)ra}ra(jYXIVA = 532 Mhz jZjajbjr\jdj2jf}ra(jh]ji]jj]jk]jn]ujpNjqhjr]raj)ra}ra(jYX IVA = 532 MhzrajZjajbjr\jdjjf}ra(jh]ji]jj]jk]jn]ujpMjr]raj{X IVA = 532 Mhzrara}ra(jYjajZjaubaubaubeubj)ra}ra(jYX**OPP\_OD PLL Settings:**rajZjo\jbjr\jdjjf}ra(jh]ji]jj]jk]jn]ujpMjqhjr]raj)ra}ra(jYX**OPP\_OD PLL Settings:**jf}ra(jh]ji]jj]jk]jn]ujZjajr]raj{XOPP_OD PLL Settings:rarb}rb(jYUjZjaubajdjubaubjC)rb}rb(jYUjZjo\jbjr\jdj`jf}rb(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]rb(j/)rb}rb(jYXARM = 1176 MHzrbjZjbjbjr\jdj2jf}r b(jh]ji]jj]jk]jn]ujpNjqhjr]r bj)r b}r b(jYjbjZjbjbjr\jdjjf}r b(jh]ji]jj]jk]jn]ujpMjr]rbj{XARM = 1176 MHzrbrb}rb(jYjbjZj bubaubaubj/)rb}rb(jYX DSP = 600 MhzrbjZjbjbjr\jdj2jf}rb(jh]ji]jj]jk]jn]ujpNjqhjr]rbj)rb}rb(jYjbjZjbjbjr\jdjjf}rb(jh]ji]jj]jk]jn]ujpMjr]rbj{X DSP = 600 Mhzrbrb}rb(jYjbjZjbubaubaubj/)rb}rb(jYX IVA = 430 Mhzr bjZjbjbjr\jdj2jf}r!b(jh]ji]jj]jk]jn]ujpNjqhjr]r"bj)r#b}r$b(jYj bjZjbjbjr\jdjjf}r%b(jh]ji]jj]jk]jn]ujpMjr]r&bj{X IVA = 430 Mhzr'br(b}r)b(jYj bjZj#bubaubaubj/)r*b}r+b(jYX GPU =500 Mhz jZjbjbjr\jdj2jf}r,b(jh]ji]jj]jk]jn]ujpNjqhjr]r-bj)r.b}r/b(jYX GPU =500 Mhzr0bjZj*bjbjr\jdjjf}r1b(jh]ji]jj]jk]jn]ujpMjr]r2bj{X GPU =500 Mhzr3br4b}r5b(jYj0bjZj.bubaubaubeubj)r6b}r7b(jYX**OPP\_HIGH PLL Settings:**r8bjZjo\jbjr\jdjjf}r9b(jh]ji]jj]jk]jn]ujpMjqhjr]r:bj)r;b}rbj{XOPP_HIGH PLL Settings:r?br@b}rAb(jYUjZj;bubajdjubaubjC)rBb}rCb(jYUjZjo\jbjr\jdj`jf}rDb(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]rEb(j/)rFb}rGb(jYXARM = 1500 MHzrHbjZjBbjbjr\jdj2jf}rIb(jh]ji]jj]jk]jn]ujpNjqhjr]rJbj)rKb}rLb(jYjHbjZjFbjbjr\jdjjf}rMb(jh]ji]jj]jk]jn]ujpMjr]rNbj{XARM = 1500 MHzrObrPb}rQb(jYjHbjZjKbubaubaubj/)rRb}rSb(jYX DSP = 700 MhzrTbjZjBbjbjr\jdj2jf}rUb(jh]ji]jj]jk]jn]ujpNjqhjr]rVbj)rWb}rXb(jYjTbjZjRbjbjr\jdjjf}rYb(jh]ji]jj]jk]jn]ujpMjr]rZbj{X DSP = 700 Mhzr[br\b}r]b(jYjTbjZjWbubaubaubj/)r^b}r_b(jYX GPU = 425 Mhzr`bjZjBbjbjr\jdj2jf}rab(jh]ji]jj]jk]jn]ujpNjqhjr]rbbj)rcb}rdb(jYj`bjZj^bjbjr\jdjjf}reb(jh]ji]jj]jk]jn]ujpMjr]rfbj{X GPU = 425 Mhzrgbrhb}rib(jYj`bjZjcbubaubaubj/)rjb}rkb(jYXIVA = 388.3 Mhz jZjBbjbjr\jdj2jf}rlb(jh]ji]jj]jk]jn]ujpNjqhjr]rmbj)rnb}rob(jYXIVA = 388.3 MhzrpbjZjjbjbjr\jdjjf}rqb(jh]ji]jj]jk]jn]ujpMjr]rrbj{XIVA = 388.3 Mhzrsbrtb}rub(jYjpbjZjnbubaubaubeubjZ)rvb}rwb(jYUjZjo\jbjr\jdj]jf}rxb(jh]ji]jj]jk]jn]ujpMjqhjr]rybj`)rzb}r{b(jYUjcKjZjvbjbjr\jdjpjf}r|b(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r}b}r~b(jYX%Timer Suspend Control Options for DSPrbjZjo\jbjr\jdjjf}rb(jk]rbUid35rbajj]jh]ji]jn]rbhaujpNjqhjr]rbj{X%Timer Suspend Control Options for DSPrbrb}rb(jYjbjZj}bubaubj)rb}rb(jYX+On AM57xx devices, all the timers on the chip have their suspend control signal routed to the A15 core. Which means that if any of the slave cores are using these timers, the timers will continue to run even when the slave core has been paused. The timer will only pause when the A15 core is halted.rbjZjo\jbjr\jdjjf}rb(jh]ji]jj]jk]jn]ujpMjqhjr]rbj{X+On AM57xx devices, all the timers on the chip have their suspend control signal routed to the A15 core. Which means that if any of the slave cores are using these timers, the timers will continue to run even when the slave core has been paused. The timer will only pause when the A15 core is halted.rbrb}rb(jYjbjZjbubaubj)rb}rb(jYXThis is confusing while debugging code on slave cores if you are relying on timer for logging, inserting delays or if the timer keeps firing interrupts even when the core is halted. One such scenario occurs with *GPtimer5* when DSP developers are using SYS/BIOS. The OS uses *GPtimer5* on the DSP and forces a frequency check to confirm the timer configuration, however the OS can't gain access to the timer due to the hook up of the suspend control signals.jZjo\jbjr\jdjjf}rb(jh]ji]jj]jk]jn]ujpMjqhjr]rb(j{XThis is confusing while debugging code on slave cores if you are relying on timer for logging, inserting delays or if the timer keeps firing interrupts even when the core is halted. One such scenario occurs with rbrb}rb(jYXThis is confusing while debugging code on slave cores if you are relying on timer for logging, inserting delays or if the timer keeps firing interrupts even when the core is halted. One such scenario occurs with jZjbubj')rb}rb(jYX *GPtimer5*jf}rb(jh]ji]jj]jk]jn]ujZjbjr]rbj{XGPtimer5rbrb}rb(jYUjZjbubajdj'ubj{X5 when DSP developers are using SYS/BIOS. The OS uses rbrb}rb(jYX5 when DSP developers are using SYS/BIOS. The OS uses jZjbubj')rb}rb(jYX *GPtimer5*jf}rb(jh]ji]jj]jk]jn]ujZjbjr]rbj{XGPtimer5rbrb}rb(jYUjZjbubajdj'ubj{X on the DSP and forces a frequency check to confirm the timer configuration, however the OS can't gain access to the timer due to the hook up of the suspend control signals.rbrb}rb(jYX on the DSP and forces a frequency check to confirm the timer configuration, however the OS can't gain access to the timer due to the hook up of the suspend control signals.jZjbubeubj)rb}rb(jYXDue to this issue the SYS/BIOS developers will need to configure an additional CCS configuration check to connect the GPTimer suspend control signal to the DSP as shown in the image below:rbjZjo\jbjr\jdjjf}rb(jh]ji]jj]jk]jn]ujpMjqhjr]rbj{XDue to this issue the SYS/BIOS developers will need to configure an additional CCS configuration check to connect the GPTimer suspend control signal to the DSP as shown in the image below:rbrb}rb(jYjbjZjbubaubjB)rb}rb(jYX3.. Image:: ../../../images/GPtimer5_DSPConnect.png jZjo\jbjr\jdjEjf}rb(UuriX,rtos/../../../images/GPtimer5_DSPConnect.pngrbjk]jj]jh]ji]jH}rbU*jbsjn]ujpMjqhjr]ubj)rb}rb(jYXOther How-To OptionsrbjZjo\jbjr\jdjjf}rb(jk]rbUother-how-to-optionsrbajj]jh]ji]jn]rbj:aujpNjqhjr]rbj{XOther How-To Optionsrbrb}rb(jYjbjZjbubaubj)rb}rb(jYXConnecting the UARTrbjZjo\jbjr\jdjjf}rb(jk]rbUconnecting-the-uartrbajj]jh]ji]jn]rbh;aujpNjqhjr]rbj{XConnecting the UARTrbrb}rb(jYjbjZjbubaubj)rb}rb(jYX?Connecting FTDI cable to the 6 pin UART header for serial debugrbjZjo\jbjr\jdjjf}rb(jh]ji]jj]jk]jn]ujpMjqhjr]rbj{X?Connecting FTDI cable to the 6 pin UART header for serial debugrbrb}rb(jYjbjZjbubaubjB)rb}rb(jYX:.. Image:: ../../../images/GP_EVM_UART.jpg :scale: 50% jZjo\jbjr\jdjEjf}rb(UscaleK2UuriX$rtos/../../../images/GP_EVM_UART.jpgrbjk]jj]jh]ji]jH}rbU*jbsjn]ujpNjqhjr]ubj)rb}rb(jYX&**Note:** Pin 1 corresponds to ground.rbjZjo\jbjr\jdjjf}rb(jh]ji]jj]jk]jn]ujpMjqhjr]rb(j)rb}rb(jYX **Note:**jf}rb(jh]ji]jj]jk]jn]ujZjbjr]rbj{XNote:rbrb}rb(jYUjZjbubajdjubj{X Pin 1 corresponds to ground.rbrb}rb(jYX Pin 1 corresponds to ground.jZjbubeubj)rb}rb(jYXConnect the USB end to the host. If you connect to the EVM UART, use the following host configuration setup in the serial terminal software (Minicom, Teraterm, etc) Baud Rate: 115200 Data Bits: 8 Parity: None Flow Control: OffrbjZjo\jbjr\jdjjf}rb(jh]ji]jj]jk]jn]ujpMjqhjr]rbj{XConnect the USB end to the host. If you connect to the EVM UART, use the following host configuration setup in the serial terminal software (Minicom, Teraterm, etc) Baud Rate: 115200 Data Bits: 8 Parity: None Flow Control: Offrbrb}rb(jYjbjZjbubaubj)rb}rb(jYX5Connect Ethernet cable to enable Network ConnectivityrbjZjo\jbjr\jdjjf}rb(jk]rbU5connect-ethernet-cable-to-enable-network-connectivityrbajj]jh]ji]jn]rbh aujpNjqhjr]rbj{X5Connect Ethernet cable to enable Network Connectivityrbrb}rb(jYjbjZjbubaubj)rb}rb(jYXjFor ethernet connectivity connect the ethernet cable to the top serial port which is port 0 on the GP EVM.rbjZjo\jbjr\jdjjf}rc(jh]ji]jj]jk]jn]ujpMjqhjr]rcj{XjFor ethernet connectivity connect the ethernet cable to the top serial port which is port 0 on the GP EVM.rcrc}rc(jYjbjZjbubaubjB)rc}rc(jYXM.. Image:: ../../../images/AM572x_GP_EVM_Ethernet_connect.jpg :scale: 50% jZjo\jbjr\jdjEjf}rc(UscaleK2UuriX7rtos/../../../images/AM572x_GP_EVM_Ethernet_connect.jpgrcjk]jj]jh]ji]jH}r cU*jcsjn]ujpNjqhjr]ubj)r c}r c(jYXYou can connect the other end of the cable directly to the host or through a network switch based on the configuration required for your test setup.r cjZjo\jbjr\jdjjf}r c(jh]ji]jj]jk]jn]ujpMjqhjr]rcj{XYou can connect the other end of the cable directly to the host or through a network switch based on the configuration required for your test setup.rcrc}rc(jYj cjZj cubaubj)rc}rc(jYXTMDXIDK5728 Hardware SetupjZjo\jbjcjdjjf}rc(jjjk]jj]jh]ji]jn]ujpKljqhjr]rcj{XTMDXIDK5728 Hardware Setuprcrc}rc(jYUjZjcubaubj)rc}rc(jYX4====================================================jZjo\jbjcjdjjf}rc(jjjk]jj]jh]ji]jn]ujpKmjqhjr]rcj{X4====================================================rcrc}rc(jYUjZjcubaubj)r c}r!c(jYXBhttp://processors.wiki.ti.com/index.php/TMDXIDK5728_Hardware_SetupjZjo\jbjXCsource/common/EVM_Hardware_Setup/TMDXIDK5728_Hardware_Setup.rst.incr"cr#c}r$cbjdjjf}r%c(jjjk]jj]jh]ji]jn]ujpKjqhjr]r&cj{XBhttp://processors.wiki.ti.com/index.php/TMDXIDK5728_Hardware_Setupr'cr(c}r)c(jYUjZj cubaubeubj[)r*c}r+c(jYUjZjR\jbj#cjdjejf}r,c(jh]ji]jj]jk]r-cUtmdxidk5728-hardware-setupr.cajn]r/chiaujpKjqhjr]r0c(jt)r1c}r2c(jYXTMDXIDK5728 Hardware Setupr3cjZj*cjbj#cjdjxjf}r4c(jh]ji]jj]jk]jn]ujpKjqhjr]r5cj{XTMDXIDK5728 Hardware Setupr6cr7c}r8c(jYj3cjZj1cubaubj)r9c}r:c(jYX Descriptionr;cjKjZj*cjbj#cjdjjf}rcajj]jh]r?cj\aji]jn]ujpNjqhjr]r@cj{X DescriptionrAcrBc}rCc(jYj;cjZj9cubaubj)rDc}rEc(jYX%The TMDXIDK5728 is a standalone test, development, and evaluation module system that enables developers to write software and develop hardware for industrial communication type applications. It has been equipped with a TI AM572x processor and a defined set of features to allow the user to experience industrial communication solutions using serial or Ethernet based interfaces. Using standard interfaces, the IDK may interface to other processors or systems and act as a communication gateway in this case. In addition it can directly operate as a standard remote I/O system or simple sensor connected to an industrial communication network. The embedded emulation logic allows emulation and debug using standard development tools such as TI’s Code Composer Studio by just using the supplied USB cable.rFcjZj*cjbj#cjdjjf}rGc(jh]ji]jj]jk]jn]ujpK jqhjr]rHcj{X%The TMDXIDK5728 is a standalone test, development, and evaluation module system that enables developers to write software and develop hardware for industrial communication type applications. It has been equipped with a TI AM572x processor and a defined set of features to allow the user to experience industrial communication solutions using serial or Ethernet based interfaces. Using standard interfaces, the IDK may interface to other processors or systems and act as a communication gateway in this case. In addition it can directly operate as a standard remote I/O system or simple sensor connected to an industrial communication network. The embedded emulation logic allows emulation and debug using standard development tools such as TI’s Code Composer Studio by just using the supplied USB cable.rIcrJc}rKc(jYjFcjZjDcubaubj)rLc}rMc(jYXEVM Layout and key componentsrNcjKjZj*cjbj#cjdjjf}rOc(jk]rPcUid37rQcajj]jh]rRcjH]aji]jn]ujpNjqhjr]rScj{XEVM Layout and key componentsrTcrUc}rVc(jYjNcjZjLcubaubjB)rWc}rXc(jYX1.. Image:: ../../../images/AM572x_IDK_layout.png jZj*cjbj#cjdjEjf}rYc(UuriX*rtos/../../../images/AM572x_IDK_layout.pngrZcjk]jj]jh]ji]jH}r[cU*jZcsjn]ujpKjqhjr]ubjC)r\c}r]c(jYUjZj*cjbj#cjdj`jf}r^c(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]r_cj/)r`c}rac(jYX1PRU1ETH0 and PRU2ETH0 are not enabled by default jZj\cjbj#cjdj2jf}rbc(jh]ji]jj]jk]jn]ujpNjqhjr]rccj)rdc}rec(jYX0PRU1ETH0 and PRU2ETH0 are not enabled by defaultrfcjZj`cjbj#cjdjjf}rgc(jh]ji]jj]jk]jn]ujpKjr]rhcj{X0PRU1ETH0 and PRU2ETH0 are not enabled by defaultricrjc}rkc(jYjfcjZjdcubaubaubaubj)rlc}rmc(jYXQuick Start GuiderncjZj*cjbj#cjdjjf}roc(jk]rpcUquick-start-guiderqcajj]jh]ji]jn]rrchJaujpNjqhjr]rscj{XQuick Start Guidertcruc}rvc(jYjncjZjlcubaubj)rwc}rxc(jYXThis section talks about how to quickly setup the AM572x Industrial Development Kit (IDK) EVM. This guide is a Beta version and it is designed to help you through the initial setup of the EVM.rycjZj*cjbj#cjdjjf}rzc(jh]ji]jj]jk]jn]ujpK jqhjr]r{cj{XThis section talks about how to quickly setup the AM572x Industrial Development Kit (IDK) EVM. This guide is a Beta version and it is designed to help you through the initial setup of the EVM.r|cr}c}r~c(jYjycjZjwcubaubjZ)rc}rc(jYUjZj*cjbj#cjdj]jf}rc(jh]ji]jj]jk]jn]ujpK$jqhjr]rcj`)rc}rc(jYUjcKjZjcjbj#cjdjpjf}rc(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjd$)rc}rc(jYUjZj*cjbNjdjg$jf}rc(jh]ji]jj]jk]jn]ujpNjqhjr]rcjj$)rc}rc(jYUjf}rc(jk]jj]jh]ji]jn]UcolsKujZjcjr]rc(jo$)rc}rc(jYUjf}rc(jk]jj]jh]ji]jn]UcolwidthKJujZjcjr]jdjs$ubj$)rc}rc(jYUjf}rc(jh]ji]jj]jk]jn]ujZjcjr]rc(j$)rc}rc(jYUjf}rc(jh]ji]jj]jk]jn]ujZjcjr]rcj$)rc}rc(jYUjf}rc(jh]ji]jj]jk]jn]ujZjcjr]rcj)rc}rc(jYX**1. Once you have received the TI-RTOS or Linux™ software from your TI representative, create a bootable µSD card (using the included blank µSD) and insert it into the EVM**rcjZjcjbj#cjdjjf}rc(jh]ji]jj]jk]jn]ujpK'jr]rcj)rc}rc(jYjcjf}rc(jh]ji]jj]jk]jn]ujZjcjr]rcj{X1. Once you have received the TI-RTOS or Linux™ software from your TI representative, create a bootable µSD card (using the included blank µSD) and insert it into the EVMrcrc}rc(jYUjZjcubajdjubaubajdj$ubajdj$ubj$)rc}rc(jYUjf}rc(jh]ji]jj]jk]jn]ujZjcjr]rcj$)rc}rc(jYUjf}rc(jh]ji]jj]jk]jn]ujZjcjr]rc(cdocutils.nodes raw rc)rc}rc(jYX
jZjcjbj#cjdUrawrcjf}rc(UformatXhtmljjjk]jj]jh]ji]jn]ujpK+jr]rcj{X
rcrc}rc(jYUjZjcubaubjc)rc}rc(jYX-
jZjcjbj#cjdjcjf}rc(UformatXhtmljjjk]jj]jh]ji]jn]ujpK/jr]rcj{X-
rcrc}rc(jYUjZjcubaubjc)rc}rc(jYX
jZjcjbj#cjdjcjf}rc(UformatXhtmljjjk]jj]jh]ji]jn]ujpK3jr]rcj{X
rcrc}rc(jYUjZjcubaubjc)rc}rc(jYX
jZjcjbj#cjdjcjf}rc(UformatXhtmljjjk]jj]jh]ji]jn]ujpK7jr]rcj{X
rcrc}rc(jYUjZjcubaubjB)rc}rc(jYX&.. Image:: ../../../images/IDK_uSD.pngjf}rc(UuriX rtos/../../../images/IDK_uSD.pngrcjk]jj]jh]ji]jH}rcU*jcsjn]ujZjcjr]jdjEubejdj$ubajdj$ubejdjy%ubejdjz%ubaubjd$)rc}rc(jYUjZj*cjbNjdjg$jf}rc(jh]ji]jj]jk]jn]ujpNjqhjr]rcjj$)rc}rc(jYUjf}rc(jk]jj]jh]ji]jn]UcolsKujZjcjr]rc(jo$)rc}rc(jYUjf}rc(jk]jj]jh]ji]jn]UcolwidthKJujZjcjr]jdjs$ubj$)rc}rc(jYUjf}rc(jh]ji]jj]jk]jn]ujZjcjr]rc(j$)rc}rc(jYUjf}rc(jh]ji]jj]jk]jn]ujZjcjr]rcj$)rc}rc(jYUjf}rc(jh]ji]jj]jk]jn]ujZjcjr]rcj)rc}rc(jYX_**2. Connect the power cable to the power jack on the board and plug in to an AC power source**rcjZjcjbj#cjdjjf}rc(jh]ji]jj]jk]jn]ujpK?jr]rcj)rc}rc(jYjcjf}rc(jh]ji]jj]jk]jn]ujZjcjr]rcj{X[2. Connect the power cable to the power jack on the board and plug in to an AC power sourcercrc}rc(jYUjZjcubajdjubaubajdj$ubajdj$ubj$)rc}rc(jYUjf}rc(jh]ji]jj]jk]jn]ujZjcjr]rcj$)rc}rc(jYUjf}rc(jh]ji]jj]jk]jn]ujZjcjr]rc(jc)rc}rd(jYX
jZjcjbj#cjdjcjf}rd(UformatXhtmljjjk]jj]jh]ji]jn]ujpKBjr]rdj{X
rdrd}rd(jYUjZjcubaubjc)rd}rd(jYX-
jZjcjbj#cjdjcjf}rd(UformatXhtmljjjk]jj]jh]ji]jn]ujpKFjr]r dj{X-
r dr d}r d(jYUjZjdubaubjc)r d}rd(jYX
jZjcjbj#cjdjcjf}rd(UformatXhtmljjjk]jj]jh]ji]jn]ujpKJjr]rdj{X
rdrd}rd(jYUjZj dubaubjc)rd}rd(jYX
jZjcjbj#cjdjcjf}rd(UformatXhtmljjjk]jj]jh]ji]jn]ujpKNjr]rdj{X
rdrd}rd(jYUjZjdubaubjB)rd}rd(jYX2.. Image:: ../../../images/Power_cord_connect.png jf}rd(UuriX+rtos/../../../images/Power_cord_connect.pngrdjk]jj]jh]ji]jH}rdU*jdsjn]ujZjcjr]jdjEubejdj$ubajdj$ubejdjy%ubejdjz%ubaubj)r d}r!d(jYXvNote: When powering this IDK, always use the recommended power supply (GlobTek Part Number TR9CA6500LCP-N, Model Number GT-43008-3306-1.0-T3) or equivalent model having output voltage of +5VDC and output current max 6.5 Amp as well as the applicable regional product regulatory/safety certification requirements requirements such as (by example) UL, CSA, VDE, CCC, PSE, etc.r"djZj*cjbj#cjdjjf}r#d(jh]ji]jj]jk]jn]ujpKVjqhjr]r$dj{XvNote: When powering this IDK, always use the recommended power supply (GlobTek Part Number TR9CA6500LCP-N, Model Number GT-43008-3306-1.0-T3) or equivalent model having output voltage of +5VDC and output current max 6.5 Amp as well as the applicable regional product regulatory/safety certification requirements requirements such as (by example) UL, CSA, VDE, CCC, PSE, etc.r%dr&d}r'd(jYj"djZj dubaubjZ)r(d}r)d(jYUjZj*cjbj#cjdj]jf}r*d(jh]ji]jj]jk]jn]ujpK]jqhjr]r+dj`)r,d}r-d(jYUjcKjZj(djbj#cjdjpjf}r.d(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjd$)r/d}r0d(jYUjZj*cjbNjdjg$jf}r1d(jh]ji]jj]jk]jn]ujpNjqhjr]r2djj$)r3d}r4d(jYUjf}r5d(jk]jj]jh]ji]jn]UcolsKujZj/djr]r6d(jo$)r7d}r8d(jYUjf}r9d(jk]jj]jh]ji]jn]UcolwidthKJujZj3djr]jdjs$ubj$)r:d}r;d(jYUjf}rd}r?d(jYUjf}r@d(jh]ji]jj]jk]jn]ujZj:djr]rAdj$)rBd}rCd(jYUjf}rDd(jh]ji]jj]jk]jn]ujZj>djr]rEdj)rFd}rGd(jYX**3. Connect the microUSB cable to USB JTAG/Console port on the EVM and connect to the USB on the host. Connect Ethernet cable to GIG ETH0 if Network connectivity is required**rHdjZjBdjbj#cjdjjf}rId(jh]ji]jj]jk]jn]ujpK`jr]rJdj)rKd}rLd(jYjHdjf}rMd(jh]ji]jj]jk]jn]ujZjFdjr]rNdj{X3. Connect the microUSB cable to USB JTAG/Console port on the EVM and connect to the USB on the host. Connect Ethernet cable to GIG ETH0 if Network connectivity is requiredrOdrPd}rQd(jYUjZjKdubajdjubaubajdj$ubajdj$ubj$)rRd}rSd(jYUjf}rTd(jh]ji]jj]jk]jn]ujZj:djr]rUdj$)rVd}rWd(jYUjf}rXd(jh]ji]jj]jk]jn]ujZjRdjr]rYd(jc)rZd}r[d(jYX
jZjVdjbj#cjdjcjf}r\d(UformatXhtmljjjk]jj]jh]ji]jn]ujpKdjr]r]dj{X
r^dr_d}r`d(jYUjZjZdubaubjc)rad}rbd(jYX-
jZjVdjbj#cjdjcjf}rcd(UformatXhtmljjjk]jj]jh]ji]jn]ujpKhjr]rddj{X-
redrfd}rgd(jYUjZjadubaubjc)rhd}rid(jYX
jZjVdjbj#cjdjcjf}rjd(UformatXhtmljjjk]jj]jh]ji]jn]ujpKljr]rkdj{X
rldrmd}rnd(jYUjZjhdubaubjc)rod}rpd(jYX
jZjVdjbj#cjdjcjf}rqd(UformatXhtmljjjk]jj]jh]ji]jn]ujpKpjr]rrdj{X
rsdrtd}rud(jYUjZjodubaubjB)rvd}rwd(jYX+.. Image:: ../../../images/JTAGUSB_UART.pngjf}rxd(UuriX%rtos/../../../images/JTAGUSB_UART.pngrydjk]jj]jh]ji]jH}rzdU*jydsjn]ujZjVdjr]jdjEubejdj$ubajdj$ubejdjy%ubejdjz%ubaubj)r{d}r|d(jYXU**Note:** The serial port will not show up on the host PC until you power on the EVM.jZj*cjbj#cjdjjf}r}d(jh]ji]jj]jk]jn]ujpKwjqhjr]r~d(j)rd}rd(jYX **Note:**jf}rd(jh]ji]jj]jk]jn]ujZj{djr]rdj{XNote:rdrd}rd(jYUjZjdubajdjubj{XL The serial port will not show up on the host PC until you power on the EVM.rdrd}rd(jYXL The serial port will not show up on the host PC until you power on the EVM.jZj{dubeubjd$)rd}rd(jYUjZj*cjbNjdjg$jf}rd(jh]ji]jj]jk]jn]ujpNjqhjr]rdjj$)rd}rd(jYUjf}rd(jk]jj]jh]ji]jn]UcolsKujZjdjr]rd(jo$)rd}rd(jYUjf}rd(jk]jj]jh]ji]jn]UcolwidthKJujZjdjr]jdjs$ubj$)rd}rd(jYUjf}rd(jh]ji]jj]jk]jn]ujZjdjr]rd(j$)rd}rd(jYUjf}rd(jh]ji]jj]jk]jn]ujZjdjr]rdj$)rd}rd(jYUjf}rd(jh]ji]jj]jk]jn]ujZjdjr]rdj)rd}rd(jYX7**4. Select the power ON button to run power the IDK.**rdjZjdjbj#cjdjjf}rd(jh]ji]jj]jk]jn]ujpK{jr]rdj)rd}rd(jYjdjf}rd(jh]ji]jj]jk]jn]ujZjdjr]rdj{X34. Select the power ON button to run power the IDK.rdrd}rd(jYUjZjdubajdjubaubajdj$ubajdj$ubj$)rd}rd(jYUjf}rd(jh]ji]jj]jk]jn]ujZjdjr]rdj$)rd}rd(jYUjf}rd(jh]ji]jj]jk]jn]ujZjdjr]rd(jc)rd}rd(jYX
jZjdjbj#cjdjcjf}rd(UformatXhtmljjjk]jj]jh]ji]jn]ujpK}jr]rdj{X
rdrd}rd(jYUjZjdubaubjc)rd}rd(jYX-
jZjdjbj#cjdjcjf}rd(UformatXhtmljjjk]jj]jh]ji]jn]ujpKjr]rdj{X-
rdrd}rd(jYUjZjdubaubjc)rd}rd(jYX
jZjdjbj#cjdjcjf}rd(UformatXhtmljjjk]jj]jh]ji]jn]ujpKjr]rdj{X
rdrd}rd(jYUjZjdubaubjc)rd}rd(jYX
jZjdjbj#cjdjcjf}rd(UformatXhtmljjjk]jj]jh]ji]jn]ujpKjr]rdj{X
rdrd}rd(jYUjZjdubaubjB)rd}rd(jYX&.. Image:: ../../../images/PowerON.pngjf}rd(UuriX rtos/../../../images/PowerON.pngrdjk]jj]jh]ji]jH}rdU*jdsjn]ujZjdjr]jdjEubejdj$ubajdj$ubejdjy%ubejdjz%ubaubj)rd}rd(jYXAfter, you power on the EVM the Status, Industrial LED2, Industrial LED3 will turn on. If the microUSB cable is pluged in then the LED corresponding to FTDI UARTtoUSB will be turned on.rdjZj*cjbj#cjdjjf}rd(jh]ji]jj]jk]jn]ujpKjqhjr]rdj{XAfter, you power on the EVM the Status, Industrial LED2, Industrial LED3 will turn on. If the microUSB cable is pluged in then the LED corresponding to FTDI UARTtoUSB will be turned on.rdrd}rd(jYjdjZjdubaubjd$)rd}rd(jYUjZj*cjbNjdjg$jf}rd(jh]ji]jj]jk]jn]ujpNjqhjr]rdjj$)rd}rd(jYUjf}rd(jk]jj]jh]ji]jn]UcolsKujZjdjr]rd(jo$)rd}rd(jYUjf}rd(jk]jj]jh]ji]jn]UcolwidthK/ujZjdjr]jdjs$ubjo$)rd}rd(jYUjf}rd(jk]jj]jh]ji]jn]UcolwidthK-ujZjdjr]jdjs$ubj$)rd}rd(jYUjf}rd(jh]ji]jj]jk]jn]ujZjdjr]rd(j$)rd}rd(jYUjf}rd(jh]ji]jj]jk]jn]ujZjdjr]rdj$)rd}rd(jYUjf}rd(jk]UmorecolsKjj]jh]ji]jn]ujZjdjr]rdj)rd}rd(jYX/**5.** **Users can now connect to UART and the on board XDS100 emulator from the host machine.For UART port connections set the serial terminal software Tera term/minicom/hyperterminal to baudrate 115200 to see log messages. Connecting to target using emulator has been discussed in the section below.**jZjdjbj#cjdjjf}rd(jh]ji]jj]jk]jn]ujpKjr]rd(j)rd}rd(jYX**5.**jf}rd(jh]ji]jj]jk]jn]ujZjdjr]rdj{X5.rdre}re(jYUjZjdubajdjubj{X re}re(jYX jZjdubj)re}re(jYX(**Users can now connect to UART and the on board XDS100 emulator from the host machine.For UART port connections set the serial terminal software Tera term/minicom/hyperterminal to baudrate 115200 to see log messages. Connecting to target using emulator has been discussed in the section below.**jf}re(jh]ji]jj]jk]jn]ujZjdjr]rej{X$Users can now connect to UART and the on board XDS100 emulator from the host machine.For UART port connections set the serial terminal software Tera term/minicom/hyperterminal to baudrate 115200 to see log messages. Connecting to target using emulator has been discussed in the section below.rer e}r e(jYUjZjeubajdjubeubajdj$ubajdj$ubj$)r e}r e(jYUjf}r e(jh]ji]jj]jk]jn]ujZjdjr]re(j$)re}re(jYUjf}re(jh]ji]jj]jk]jn]ujZj ejr]re(jc)re}re(jYX
jZjejbj#cjdjcjf}re(UformatXhtmljjjk]jj]jh]ji]jn]ujpKjr]rej{X
rere}re(jYUjZjeubaubjc)re}re(jYX
jZjejbj#cjdjcjf}re(UformatXhtmljjjk]jj]jh]ji]jn]ujpKjr]rej{X
rere}r e(jYUjZjeubaubjc)r!e}r"e(jYX-
jZjejbj#cjdjcjf}r#e(UformatXhtmljjjk]jj]jh]ji]jn]ujpKjr]r$ej{X-
r%er&e}r'e(jYUjZj!eubaubjB)r(e}r)e(jYX... Image:: ../../../images/Serial_connect.jpg jf}r*e(UuriX'rtos/../../../images/Serial_connect.jpgr+ejk]jj]jh]ji]jH}r,eU*j+esjn]ujZjejr]jdjEubjc)r-e}r.e(jYX
jZjejbj#cjdjcjf}r/e(UformatXhtmljjjk]jj]jh]ji]jn]ujpKjr]r0ej{X
r1er2e}r3e(jYUjZj-eubaubjc)r4e}r5e(jYX
jZjejbj#cjdjcjf}r6e(UformatXhtmljjjk]jj]jh]ji]jn]ujpKjr]r7ej{X
r8er9e}r:e(jYUjZj4eubaubejdj$ubj$)r;e}re(jc)r?e}r@e(jYX
jZj;ejbj#cjdjcjf}rAe(UformatXhtmljjjk]jj]jh]ji]jn]ujpKjr]rBej{X
rCerDe}rEe(jYUjZj?eubaubjc)rFe}rGe(jYX
jZj;ejbj#cjdjcjf}rHe(UformatXhtmljjjk]jj]jh]ji]jn]ujpKjr]rIej{X
rJerKe}rLe(jYUjZjFeubaubjc)rMe}rNe(jYX-
jZj;ejbj#cjdjcjf}rOe(UformatXhtmljjjk]jj]jh]ji]jn]ujpKjr]rPej{X-
rQerRe}rSe(jYUjZjMeubaubjB)rTe}rUe(jYX(.. Image:: ../../../images/Baudrate.jpg jf}rVe(UuriX!rtos/../../../images/Baudrate.jpgrWejk]jj]jh]ji]jH}rXeU*jWesjn]ujZj;ejr]jdjEubjc)rYe}rZe(jYX
jZj;ejbj#cjdjcjf}r[e(UformatXhtmljjjk]jj]jh]ji]jn]ujpKjr]r\ej{X
r]er^e}r_e(jYUjZjYeubaubjc)r`e}rae(jYX
jZj;ejbj#cjdjcjf}rbe(UformatXhtmljjjk]jj]jh]ji]jn]ujpKjr]rcej{X
rderee}rfe(jYUjZj`eubaubejdj$ubejdj$ubejdjy%ubejdjz%ubaubj)rge}rhe(jYX*Connecting IDK EVM to Code Composer StudioriejZj*cjbj#cjdjjf}rje(jk]rkeU*connecting-idk-evm-to-code-composer-studiorleajj]jh]ji]jn]rmej aujpNjqhjr]rnej{X*Connecting IDK EVM to Code Composer Studioroerpe}rqe(jYjiejZjgeubaubj)rre}rse(jYXz**Step1 :** Download Code composer Studio and AM572x Sitara CSP package as described in the wiki article mentioned below:jZj*cjbj#cjdjjf}rte(jh]ji]jj]jk]jn]ujpKjqhjr]rue(j)rve}rwe(jYX **Step1 :**jf}rxe(jh]ji]jj]jk]jn]ujZjrejr]ryej{XStep1 :rzer{e}r|e(jYUjZjveubajdjubj{Xn Download Code composer Studio and AM572x Sitara CSP package as described in the wiki article mentioned below:r}er~e}re(jYXn Download Code composer Studio and AM572x Sitara CSP package as described in the wiki article mentioned below:jZjreubeubj)re}re(jYX`Install Code composer Studio for AM572x `__rejZj*cjbj#cjdjjf}re(jh]ji]jj]jk]jn]ujpKjqhjr]rej)re}re(jYjejf}re(UnameX'Install Code composer Studio for AM572xjXhhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_Getting_Started_Guide#Code_Composer_Studio%7Cjk]jj]jh]ji]jn]ujZjejr]rej{X'Install Code composer Studio for AM572xrere}re(jYUjZjeubajdjubaubj)re}re(jYXM**Step2:** Connect IDK EVM as described in the `Quick Start Guide `__. Populating the uSD card is not required as the intent is to connect and load code over emulator and not to boot the device using uSD card. AM572x IDK doesn\`t have any boot switches to configure for emulation mode.jZj*cjbj#cjdjjf}re(jh]ji]jj]jk]jn]ujpKjqhjr]re(j)re}re(jYX **Step2:**jf}re(jh]ji]jj]jk]jn]ujZjejr]rej{XStep2:rere}re(jYUjZjeubajdjubj{X% Connect IDK EVM as described in the rere}re(jYX% Connect IDK EVM as described in the jZjeubj)re}re(jYXF`Quick Start Guide `__jf}re(UnameXQuick Start GuidejX.http://www.ti.com/lit/ml/sprw282a/sprw282a.pdfjk]jj]jh]ji]jn]ujZjejr]rej{XQuick Start Guiderere}re(jYUjZjeubajdjubj{X. Populating the uSD card is not required as the intent is to connect and load code over emulator and not to boot the device using uSD card. AM572x IDK doesn`t have any boot switches to configure for emulation mode.rere}re(jYX. Populating the uSD card is not required as the intent is to connect and load code over emulator and not to boot the device using uSD card. AM572x IDK doesn\`t have any boot switches to configure for emulation mode.jZjeubeubj)re}re(jYX**Step3:** Launch CCS and create new target configuration(File->New->Target Configuration file) as shown in the images below and provide appropriate name to the configuration. Select Texas Instuments XDS100v2 emulator and target as IDK\_AM572x.jZj*cjbj#cjdjjf}re(jh]ji]jj]jk]jn]ujpKjqhjr]re(j)re}re(jYX **Step3:**jf}re(jh]ji]jj]jk]jn]ujZjejr]rej{XStep3:rere}re(jYUjZjeubajdjubj{X Launch CCS and create new target configuration(File->New->Target Configuration file) as shown in the images below and provide appropriate name to the configuration. Select Texas Instuments XDS100v2 emulator and target as IDK_AM572x.rere}re(jYX Launch CCS and create new target configuration(File->New->Target Configuration file) as shown in the images below and provide appropriate name to the configuration. Select Texas Instuments XDS100v2 emulator and target as IDK\_AM572x.jZjeubeubjc)re}re(jYXh
jZj*cjbj#cjdjcjf}re(UformatXhtmljjjk]jj]jh]ji]jn]ujpKjqhjr]rej{Xh
rere}re(jYUjZjeubaubj)re}re(jYX**NOTE** If you don\`t find the IDK\_AM572x target make sure you have installed the Sitara Device support version 1.3.x package correctlyjZj*cjbj#cjdjjf}re(jh]ji]jj]jk]jn]ujpKjqhjr]re(j)re}re(jYX**NOTE**jf}re(jh]ji]jj]jk]jn]ujZjejr]rej{XNOTErere}re(jYUjZjeubajdjubj{X If you don`t find the IDK_AM572x target make sure you have installed the Sitara Device support version 1.3.x package correctlyrere}re(jYX If you don\`t find the IDK\_AM572x target make sure you have installed the Sitara Device support version 1.3.x package correctlyjZjeubeubjc)re}re(jYX
jZj*cjbj#cjdjcjf}re(UformatXhtmljjjk]jj]jh]ji]jn]ujpKjqhjr]rej{X
rere}re(jYUjZjeubaubjB)re}re(jYX4.. Image:: ../../../images/Target_configuration.png jZj*cjbj#cjdjEjf}re(UuriX-rtos/../../../images/Target_configuration.pngrejk]jj]jh]ji]jH}reU*jesjn]ujpKjqhjr]ubjZ)re}re(jYUjZj*cjbj#cjdj]jf}re(jh]ji]jj]jk]jn]ujpKjqhjr]re(j`)re}re(jYUjcKjZjejbj#cjdjpjf}re(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)re}re(jYX**Step4:** In advance settings, Make sure that the corresponding IDK GEL file are populated for all the cores. The following GEL files and their corresponding cores are provided below:jcKjZjejbj#cjdjpjf}re(jh]ji]jj]jk]jn]ujpKjqhjr]re(j)re}re(jYX **Step4:**jf}re(jh]ji]jj]jk]jn]ujZjejr]rej{XStep4:rere}re(jYUjZjeubajdjubj{X In advance settings, Make sure that the corresponding IDK GEL file are populated for all the cores. The following GEL files and their corresponding cores are provided below:rere}re(jYX In advance settings, Make sure that the corresponding IDK GEL file are populated for all the cores. The following GEL files and their corresponding cores are provided below:jZjeubeubeubjC)re}re(jYUjZj*cjbj#cjdj`jf}re(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]re(j/)re}re(jYXGCortex\_A15\_0: ..\\..\\emulation\\boards\\am572x\\gel\\idk\_am572x.geljZjejbj#cjdj2jf}re(jh]ji]jj]jk]jn]ujpNjqhjr]rej)re}re(jYXGCortex\_A15\_0: ..\\..\\emulation\\boards\\am572x\\gel\\idk\_am572x.geljZjejbj#cjdjjf}re(jh]ji]jj]jk]jn]ujpKjr]rej{X>Cortex_A15_0: ..\..\emulation\boards\am572x\gel\idk_am572x.gelrere}re(jYXGCortex\_A15\_0: ..\\..\\emulation\\boards\\am572x\\gel\\idk\_am572x.geljZjeubaubaubj/)re}re(jYXLC66x\_DSP1: ..\\..\\emulation\\boards\\am572x\\gel\\AM572x\_dsp\_startup.geljZjejbj#cjdj2jf}re(jh]ji]jj]jk]jn]ujpNjqhjr]rej)re}re(jYXLC66x\_DSP1: ..\\..\\emulation\\boards\\am572x\\gel\\AM572x\_dsp\_startup.geljZjejbj#cjdjjf}re(jh]ji]jj]jk]jn]ujpKjr]rej{XCC66x_DSP1: ..\..\emulation\boards\am572x\gel\AM572x_dsp_startup.gelrerf}rf(jYXLC66x\_DSP1: ..\\..\\emulation\\boards\\am572x\\gel\\AM572x\_dsp\_startup.geljZjeubaubaubj/)rf}rf(jYX\Cortex\_M4\_IPU1\_C0: ..\\..\\emulation\\boards\\am572x\\gel\\AM572x\_cortexM4\_startup.gel jZjejbj#cjdj2jf}rf(jh]ji]jj]jk]jn]ujpNjqhjr]rfj)rf}rf(jYX[Cortex\_M4\_IPU1\_C0: ..\\..\\emulation\\boards\\am572x\\gel\\AM572x\_cortexM4\_startup.geljZjfjbj#cjdjjf}rf(jh]ji]jj]jk]jn]ujpKjr]r fj{XPCortex_M4_IPU1_C0: ..\..\emulation\boards\am572x\gel\AM572x_cortexM4_startup.gelr fr f}r f(jYX[Cortex\_M4\_IPU1\_C0: ..\\..\\emulation\\boards\\am572x\\gel\\AM572x\_cortexM4\_startup.geljZjfubaubaubeubj)r f}rf(jYXuNote: GEL files are located under ccsv6\\ccs\_base\\emulation\\boards\\am572x\\gel after the CSP package is installedjZj*cjbj#cjdjjf}rf(jh]ji]jj]jk]jn]ujpKjqhjr]rfj{XoNote: GEL files are located under ccsv6\ccs_base\emulation\boards\am572x\gel after the CSP package is installedrfrf}rf(jYXuNote: GEL files are located under ccsv6\\ccs\_base\\emulation\\boards\\am572x\\gel after the CSP package is installedjZj fubaubjZ)rf}rf(jYUjZj*cjbj#cjdj]jf}rf(jh]ji]jj]jk]jn]ujpKjqhjr]rf(j`)rf}rf(jYUjcKjZjfjbj#cjdjpjf}rf(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)rf}rf(jYX&**Step5**: Launch Target configuration you just created. AM572x is an ARM master boot device so connect to the A15\_0 first. It is also recommended that you do a CPU reset from (Run->Reset->CPU Reset) Menu on the A15 to put it in a clean state as the IDK is designed to come up in SD boot mode.jcKjZjfjbj#cjdjpjf}rf(jh]ji]jj]jk]jn]ujpKjqhjr]rf(j)rf}r f(jYX **Step5**jf}r!f(jh]ji]jj]jk]jn]ujZjfjr]r"fj{XStep5r#fr$f}r%f(jYUjZjfubajdjubj{X: Launch Target configuration you just created. AM572x is an ARM master boot device so connect to the A15_0 first. It is also recommended that you do a CPU reset from (Run->Reset->CPU Reset) Menu on the A15 to put it in a clean state as the IDK is designed to come up in SD boot mode.r&fr'f}r(f(jYX: Launch Target configuration you just created. AM572x is an ARM master boot device so connect to the A15\_0 first. It is also recommended that you do a CPU reset from (Run->Reset->CPU Reset) Menu on the A15 to put it in a clean state as the IDK is designed to come up in SD boot mode.jZjfubeubeubjZ)r)f}r*f(jYUjZj*cjbj#cjdj]jf}r+f(jh]ji]jj]jk]jn]ujpKjqhjr]r,f(j`)r-f}r.f(jYUjcKjZj)fjbj#cjdjpjf}r/f(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)r0f}r1f(jYX4Complete GEL log from A15 connect is provided below:r2fjcKjZj)fjbj#cjdjpjf}r3f(jh]ji]jj]jk]jn]ujpKjqhjr]r4fj{X4Complete GEL log from A15 connect is provided below:r5fr6f}r7f(jYj2fjZj0fubaubeubj)r8f}r9f(jYX CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence Begins ... <<<--- CortexA15_0: GEL Output: --->>> AM572x Begin MMC2 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> AM572x End MMC2 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> AM572x PG1.1 GP device <<<--- CortexA15_0: GEL Output: --->>> I2C Init <<<--- CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<--- CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: Cortex A15 DPLL is already locked, now unlocking... CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 is DONE! CortexA15_0: GEL Output: IVA DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: IVA DPLL OPP 0 is DONE! CortexA15_0: GEL Output: PER DPLL OPP 0 clock config in progress... CortexA15_0: GEL Output: PER DPLL already locked, now unlocking CortexA15_0: GEL Output: PER DPLL OPP 0 is DONE! CortexA15_0: GEL Output: CORE DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: CORE DPLL OPP already locked, now unlocking.... CortexA15_0: GEL Output: CORE DPLL OPP 0 is DONE! CortexA15_0: GEL Output: ABE DPLL OPP 0 clock config in progress... CortexA15_0: GEL Output: ABE DPLL OPP 0 is DONE! CortexA15_0: GEL Output: GMAC DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: GMAC DPLL OPP 0 is DONE! CortexA15_0: GEL Output: GPU DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: GPU DPLL OPP 0 is DONE! CortexA15_0: GEL Output: DSP DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: DSP DPLL OPP 0 is DONE! CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 is DONE! CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<--- CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<--- CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<--- CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in progress... CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in DONE! CortexA15_0: GEL Output: DEBUG: Overall DDR configuration CortexA15_0: GEL Output: DEBUG: EMIF1 and EMIF1 DDR IOs config (CTRL_MODULE_CORE_PAD module) CortexA15_0: GEL Output: DEBUG: DDR PHY config (CTRL_MODULE_WKUP module) CortexA15_0: GEL Output: DEBUG: EMIF1 ctrl + associated DDR PHYs initial config (EMIF1 module) CortexA15_0: GEL Output: DEBUG: EMIF1 channel - Launch full levelling CortexA15_0: GEL Output: DEBUG: EMIF2 ctrl + associated DDR PHYs initial config (EMIF2 module) CortexA15_0: GEL Output: DEBUG: EMIF1 channel - Launch full levelling CortexA15_0: GEL Output: DEBUG: Setting LISA maps in non-interleaved dual-EMIF mode CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence DONE !!!!! <<>> AM572x Target Connect Sequence Begins ... <<<--- CortexA15_0: GEL Output: --->>> AM572x Begin MMC2 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> AM572x End MMC2 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> AM572x PG1.1 GP device <<<--- CortexA15_0: GEL Output: --->>> I2C Init <<<--- CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<--- CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: Cortex A15 DPLL is already locked, now unlocking... CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 is DONE! CortexA15_0: GEL Output: IVA DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: IVA DPLL OPP 0 is DONE! CortexA15_0: GEL Output: PER DPLL OPP 0 clock config in progress... CortexA15_0: GEL Output: PER DPLL already locked, now unlocking CortexA15_0: GEL Output: PER DPLL OPP 0 is DONE! CortexA15_0: GEL Output: CORE DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: CORE DPLL OPP already locked, now unlocking.... CortexA15_0: GEL Output: CORE DPLL OPP 0 is DONE! CortexA15_0: GEL Output: ABE DPLL OPP 0 clock config in progress... CortexA15_0: GEL Output: ABE DPLL OPP 0 is DONE! CortexA15_0: GEL Output: GMAC DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: GMAC DPLL OPP 0 is DONE! CortexA15_0: GEL Output: GPU DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: GPU DPLL OPP 0 is DONE! CortexA15_0: GEL Output: DSP DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: DSP DPLL OPP 0 is DONE! CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 is DONE! CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<--- CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<--- CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<--- CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in progress... CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in DONE! CortexA15_0: GEL Output: DEBUG: Overall DDR configuration CortexA15_0: GEL Output: DEBUG: EMIF1 and EMIF1 DDR IOs config (CTRL_MODULE_CORE_PAD module) CortexA15_0: GEL Output: DEBUG: DDR PHY config (CTRL_MODULE_WKUP module) CortexA15_0: GEL Output: DEBUG: EMIF1 ctrl + associated DDR PHYs initial config (EMIF1 module) CortexA15_0: GEL Output: DEBUG: EMIF1 channel - Launch full levelling CortexA15_0: GEL Output: DEBUG: EMIF2 ctrl + associated DDR PHYs initial config (EMIF2 module) CortexA15_0: GEL Output: DEBUG: EMIF1 channel - Launch full levelling CortexA15_0: GEL Output: DEBUG: Setting LISA maps in non-interleaved dual-EMIF mode CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence DONE !!!!! <<f(jYUjZj8fubaubjZ)r?f}r@f(jYUjZj*cjbj#cjdj]jf}rAf(jh]ji]jj]jk]jn]ujpM"jqhjr]rBfj`)rCf}rDf(jYUjcKjZj?fjbj#cjdjpjf}rEf(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)rFf}rGf(jYX**Step6** : To connect to the DSP, M4,PRUSS or to IVAHD go to Scripts menu and under AM572x MULTICORE Initialization enable the corresponding Sub system clock Enable API.For Eg. FOr DSP1 select DSP11SSClkEnable\_API. After running the clock enable option, you can connect to the core.jZj*cjbj#cjdjjf}rHf(jh]ji]jj]jk]jn]ujpM$jqhjr]rIf(j)rJf}rKf(jYX **Step6**jf}rLf(jh]ji]jj]jk]jn]ujZjFfjr]rMfj{XStep6rNfrOf}rPf(jYUjZjJfubajdjubj{X : To connect to the DSP, M4,PRUSS or to IVAHD go to Scripts menu and under AM572x MULTICORE Initialization enable the corresponding Sub system clock Enable API.For Eg. FOr DSP1 select DSP11SSClkEnable_API. After running the clock enable option, you can connect to the core.rQfrRf}rSf(jYX : To connect to the DSP, M4,PRUSS or to IVAHD go to Scripts menu and under AM572x MULTICORE Initialization enable the corresponding Sub system clock Enable API.For Eg. FOr DSP1 select DSP11SSClkEnable\_API. After running the clock enable option, you can connect to the core.jZjFfubeubjZ)rTf}rUf(jYUjZj*cjbj#cjdj]jf}rVf(jh]ji]jj]jk]jn]ujpM*jqhjr]rWfj`)rXf}rYf(jYUjcKjZjTfjbj#cjdjpjf}rZf(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjB)r[f}r\f(jYX0.. Image:: ../../../images/Multicore-Enable.jpg jZj*cjbj#cjdjEjf}r]f(UuriX)rtos/../../../images/Multicore-Enable.jpgr^fjk]jj]jh]ji]jH}r_fU*j^fsjn]ujpM-jqhjr]ubj)r`f}raf(jYX Related LinksrbfjZj*cjbj#cjdjjf}rcf(jk]rdfU related-linksrefajj]jh]ji]jn]rffhaujpNjqhjr]rgfj{X Related Linksrhfrif}rjf(jYjbfjZj`fubaubj)rkf}rlf(jYXd`AM572x\_Industrial\_EVM\_Hardware\_Users\_Guide `__rmfjZj*cjbj#cjdjjf}rnf(jh]ji]jj]jk]jn]ujpM1jqhjr]rofj)rpf}rqf(jYXd`AM572x\_Industrial\_EVM\_Hardware\_Users\_Guide `__jf}rrf(UnameX*AM572x_Industrial_EVM_Hardware_Users_GuidejX.http://www.ti.com/lit/ug/sprui64a/sprui64a.pdfjk]jj]jh]ji]jn]ujZjkfjr]rsfj{X*AM572x_Industrial_EVM_Hardware_Users_Guidertfruf}rvf(jYUjZjpfubajdjubaubj)rwf}rxf(jYX66AK2G02 GP EVM Hardware SetupjZj*cjbjcjdjjf}ryf(jjjk]jj]jh]ji]jn]ujpKpjqhjr]rzfj{X66AK2G02 GP EVM Hardware Setupr{fr|f}r}f(jYUjZjwfubaubj)r~f}rf(jYX4====================================================jZj*cjbjcjdjjf}rf(jjjk]jj]jh]ji]jn]ujpKqjqhjr]rfj{X4====================================================rfrf}rf(jYUjZj~fubaubj)rf}rf(jYXFhttp://processors.wiki.ti.com/index.php/66AK2G02_GP_EVM_Hardware_SetupjZj*cjbjXGsource/common/EVM_Hardware_Setup/66AK2G02_GP_EVM_Hardware_Setup.rst.incrfrf}rfbjdjjf}rf(jjjk]jj]jh]ji]jn]ujpKjqhjr]rfj{XFhttp://processors.wiki.ti.com/index.php/66AK2G02_GP_EVM_Hardware_Setuprfrf}rf(jYUjZjfubaubeubj[)rf}rf(jYUjZjR\jbjfjdjejf}rf(jh]ji]jj]jk]rfUak2gx-gp-evm-hardware-setuprfajn]rfhg}r?g(jYX$**High speed and Serial Interfaces**r@gjZjfjbjfjdjjf}rAg(jh]ji]jj]jk]jn]ujpKjqhjr]rBgj)rCg}rDg(jYj@gjf}rEg(jh]ji]jj]jk]jn]ujZj>gjr]rFgj{X High speed and Serial InterfacesrGgrHg}rIg(jYUjZjCgubajdjubaubjC)rJg}rKg(jYUjZjfjbjfjdj`jf}rLg(jGX-jk]jj]jh]ji]jn]ujpK!jqhjr]rMg(j/)rNg}rOg(jYXMGigabit Ethernet port supporting 10/100/1000 Mbps data rate on RJ45 connectorjZjJgjbjfjdj2jf}rPg(jh]ji]jj]jk]jn]ujpNjqhjr]rQgj)rRg}rSg(jYXMGigabit Ethernet port supporting 10/100/1000 Mbps data rate on RJ45 connectorrTgjZjNgjbjfjdjjf}rUg(jh]ji]jj]jk]jn]ujpK!jr]rVgj{XMGigabit Ethernet port supporting 10/100/1000 Mbps data rate on RJ45 connectorrWgrXg}rYg(jYjTgjZjRgubaubaubj/)rZg}r[g(jYXPCIe x1 card slotr\gjZjJgjbjfjdj2jf}r]g(jh]ji]jj]jk]jn]ujpNjqhjr]r^gj)r_g}r`g(jYj\gjZjZgjbjfjdjjf}rag(jh]ji]jj]jk]jn]ujpK#jr]rbgj{XPCIe x1 card slotrcgrdg}reg(jYj\gjZj_gubaubaubj/)rfg}rgg(jYXCOM8 interfacerhgjZjJgjbjfjdj2jf}rig(jh]ji]jj]jk]jn]ujpNjqhjr]rjgj)rkg}rlg(jYjhgjZjfgjbjfjdjjf}rmg(jh]ji]jj]jk]jn]ujpK$jr]rngj{XCOM8 interfacerogrpg}rqg(jYjhgjZjkgubaubaubj/)rrg}rsg(jYXDCAN and MLB interfacesrtgjZjJgjbjfjdj2jf}rug(jh]ji]jj]jk]jn]ujpNjqhjr]rvgj)rwg}rxg(jYjtgjZjrgjbjfjdjjf}ryg(jh]ji]jj]jk]jn]ujpK%jr]rzgj{XDCAN and MLB interfacesr{gr|g}r}g(jYjtgjZjwgubaubaubj/)r~g}rg(jYX.One USB2.0 host and one USB2.0 Dual-role portsrgjZjJgjbjfjdj2jf}rg(jh]ji]jj]jk]jn]ujpNjqhjr]rgj)rg}rg(jYjgjZj~gjbjfjdjjf}rg(jh]ji]jj]jk]jn]ujpK&jr]rgj{X.One USB2.0 host and one USB2.0 Dual-role portsrgrg}rg(jYjgjZjgubaubaubj/)rg}rg(jYXpOne RS232 serial interface on DB9 connector or UART over mini-USB connector, One UART interface on 6 pin header jZjJgjbjfjdj2jf}rg(jh]ji]jj]jk]jn]ujpNjqhjr]rgj)rg}rg(jYXoOne RS232 serial interface on DB9 connector or UART over mini-USB connector, One UART interface on 6 pin headerrgjZjgjbjfjdjjf}rg(jh]ji]jj]jk]jn]ujpK'jr]rgj{XoOne RS232 serial interface on DB9 connector or UART over mini-USB connector, One UART interface on 6 pin headerrgrg}rg(jYjgjZjgubaubaubeubj)rg}rg(jYX**Multimedia and display:**rgjZjfjbjfjdjjf}rg(jh]ji]jj]jk]jn]ujpK*jqhjr]rgj)rg}rg(jYjgjf}rg(jh]ji]jj]jk]jn]ujZjgjr]rgj{XMultimedia and display:rgrg}rg(jYUjZjgubajdjubaubjC)rg}rg(jYUjZjfjbjfjdj`jf}rg(jGX-jk]jj]jh]ji]jn]ujpK,jqhjr]rg(j/)rg}rg(jYX:4.3” LCD display with Capacitive touch (Sold separately)rgjZjgjbjfjdj2jf}rg(jh]ji]jj]jk]jn]ujpNjqhjr]rgj)rg}rg(jYjgjZjgjbjfjdjjf}rg(jh]ji]jj]jk]jn]ujpK,jr]rgj{X:4.3” LCD display with Capacitive touch (Sold separately)rgrg}rg(jYjgjZjgubaubaubj/)rg}rg(jYXHDMI transmitterrgjZjgjbjfjdj2jf}rg(jh]ji]jj]jk]jn]ujpNjqhjr]rgj)rg}rg(jYjgjZjgjbjfjdjjf}rg(jh]ji]jj]jk]jn]ujpK-jr]rgj{XHDMI transmitterrgrg}rg(jYjgjZjgubaubaubj/)rg}rg(jYXAudio Line In and Line Out jZjgjbjfjdj2jf}rg(jh]ji]jj]jk]jn]ujpNjqhjr]rgj)rg}rg(jYXAudio Line In and Line OutrgjZjgjbjfjdjjf}rg(jh]ji]jj]jk]jn]ujpK.jr]rgj{XAudio Line In and Line Outrgrg}rg(jYjgjZjgubaubaubeubj)rg}rg(jYX**JTAG and Emulation:**rgjZjfjbjfjdjjf}rg(jh]ji]jj]jk]jn]ujpK0jqhjr]rgj)rg}rg(jYjgjf}rg(jh]ji]jj]jk]jn]ujZjgjr]rgj{XJTAG and Emulation:rgrg}rg(jYUjZjgubajdjubaubjC)rg}rg(jYUjZjfjbjfjdj`jf}rg(jGX-jk]jj]jh]ji]jn]ujpK2jqhjr]rg(j/)rg}rg(jYXAMIPI 60-Pin JTAG header to support all types of external emulatorrgjZjgjbjfjdj2jf}rg(jh]ji]jj]jk]jn]ujpNjqhjr]rgj)rg}rg(jYjgjZjgjbjfjdjjf}rg(jh]ji]jj]jk]jn]ujpK2jr]rgj{XAMIPI 60-Pin JTAG header to support all types of external emulatorrgrg}rg(jYjgjZjgubaubaubj/)rg}rg(jYXOn Board XDS200 EmulatorrgjZjgjbjfjdj2jf}rg(jh]ji]jj]jk]jn]ujpNjqhjr]rgj)rg}rg(jYjgjZjgjbjfjdjjf}rg(jh]ji]jj]jk]jn]ujpK3jr]rgj{XOn Board XDS200 Emulatorrgrg}rg(jYjgjZjgubaubaubj/)rg}rg(jYX*Powered by DC power-wall adaptor (12V/5A) jZjgjbjfjdj2jf}rg(jh]ji]jj]jk]jn]ujpNjqhjr]rgj)rg}rg(jYX)Powered by DC power-wall adaptor (12V/5A)rgjZjgjbjfjdjjf}rg(jh]ji]jj]jk]jn]ujpK4jr]rgj{X)Powered by DC power-wall adaptor (12V/5A)rgrg}rg(jYjgjZjgubaubaubeubj)rg}rg(jYXEVM Layout and Key ComponentsrhjKjZjfjbjfjdjjf}rh(jk]rhUid39rhajj]jh]rhXevm-layout-and-key-componentsrhaji]jn]ujpNjqhjr]rhj{XEVM Layout and Key Componentsrhrh}r h(jYjhjZjgubaubjB)r h}r h(jYX).. Image:: ../../../images/TI_K2GEVM.png jZjfjbjfjdjEjf}r h(UuriX"rtos/../../../images/TI_K2GEVM.pngr hjk]jj]jh]ji]jH}rhU*j hsjn]ujpK:jqhjr]ubj)rh}rh(jYX+JTAG debug probes (aka Emulators) supportedrhjKjZjfjbjfjdjjf}rh(jk]rhUid40rhajj]jh]rhjY]aji]jn]ujpNjqhjr]rhj{X+JTAG debug probes (aka Emulators) supportedrhrh}rh(jYjhjZjhubaubj)rh}rh(jYX/List of standalone JTAG debug probes supported:rhjZjfjbjfjdjjf}rh(jh]ji]jj]jk]jn]ujpK>jqhjr]rhj{X/List of standalone JTAG debug probes supported:rhr h}r!h(jYjhjZjhubaubjC)r"h}r#h(jYUjZjfjbjfjdj`jf}r$h(jGX-jk]jj]jh]ji]jn]ujpK@jqhjr]r%h(j/)r&h}r'h(jYXVXDS100-class JTAG debug probes (low cost, low performance). XDS100v1 is not supported.jZj"hjbjfjdj2jf}r(h(jh]ji]jj]jk]jn]ujpNjqhjr]r)hj)r*h}r+h(jYXVXDS100-class JTAG debug probes (low cost, low performance). XDS100v1 is not supported.r,hjZj&hjbjfjdjjf}r-h(jh]ji]jj]jk]jn]ujpK@jr]r.hj{XVXDS100-class JTAG debug probes (low cost, low performance). XDS100v1 is not supported.r/hr0h}r1h(jYj,hjZj*hubaubaubj/)r2h}r3h(jYX,XDS200-class JTAG debug probes (recommended)r4hjZj"hjbjfjdj2jf}r5h(jh]ji]jj]jk]jn]ujpNjqhjr]r6hj)r7h}r8h(jYj4hjZj2hjbjfjdjjf}r9h(jh]ji]jj]jk]jn]ujpKBjr]r:hj{X,XDS200-class JTAG debug probes (recommended)r;hrh}r?h(jYX4XDS560v2-class JTAG debug probes (high performance) jZj"hjbjfjdj2jf}r@h(jh]ji]jj]jk]jn]ujpNjqhjr]rAhj)rBh}rCh(jYX3XDS560v2-class JTAG debug probes (high performance)rDhjZj>hjbjfjdjjf}rEh(jh]ji]jj]jk]jn]ujpKCjr]rFhj{X3XDS560v2-class JTAG debug probes (high performance)rGhrHh}rIh(jYjDhjZjBhubaubaubeubjZ)rJh}rKh(jYUjZjfjbjfjdj]jf}rLh(jh]ji]jj]jk]jn]ujpKEjqhjr]rMhj`)rNh}rOh(jYUjcKjZjJhjbjfjdjpjf}rPh(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)rQh}rRh(jYXMinimal EVM setuprShjKjZjfjbjfjdjjf}rTh(jk]rUhUid41rVhajj]jh]rWhj]aji]jn]ujpNjqhjr]rXhj{XMinimal EVM setuprYhrZh}r[h(jYjShjZjQhubaubj)r\h}r]h(jYX.. _SettingBootSwitches:jKjZjfjbjfjdjjf}r^h(jk]jj]jh]ji]jn]jUsettingbootswitchesr_hujpMjqhjr]ubj)r`h}rah(jYXSetting boot switchesrbhjKjZjfjbjfj}rchjj\hsjdjjf}rdh(jk]reh(Uid42rfhj_hejj]jh]rghj]aji]jn]rhhjaujpNjqhj}rihj_hj\hsjr]rjhj{XSetting boot switchesrkhrlh}rmh(jYjbhjZj`hubaubj)rnh}roh(jYXKThe DIP Switch /Boot mode switch (SW3) is used for selecting the boot mode.rphjZjfjbjfjdjjf}rqh(jh]ji]jj]jk]jn]ujpKOjqhjr]rrhj{XKThe DIP Switch /Boot mode switch (SW3) is used for selecting the boot mode.rshrth}ruh(jYjphjZjnhubaubjZ)rvh}rwh(jYUjZjfjbjfjdj]jf}rxh(jh]ji]jj]jk]jn]ujpKRjqhjr]ryh(j`)rzh}r{h(jYUjcKjZjvhjbjfjdjpjf}r|h(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)r}h}r~h(jYXI**For EVM Out of box experience uses SD/MMC boot as shown in the image**:jcKjZjvhjbjfjdjpjf}rh(jh]ji]jj]jk]jn]ujpKTjqhjr]rh(j)rh}rh(jYXH**For EVM Out of box experience uses SD/MMC boot as shown in the image**jf}rh(jh]ji]jj]jk]jn]ujZj}hjr]rhj{XDFor EVM Out of box experience uses SD/MMC boot as shown in the imagerhrh}rh(jYUjZjhubajdjubj{X:rh}rh(jYX:jZj}hubeubeubjB)rh}rh(jYX2.. Image:: ../../../images/Boot_switch_SDboot.jpg jZjfjbjfjdjEjf}rh(UuriX+rtos/../../../images/Boot_switch_SDboot.jpgrhjk]jj]jh]ji]jH}rhU*jhsjn]ujpKWjqhjr]ubjZ)rh}rh(jYUjZjfjbjfjdj]jf}rh(jh]ji]jj]jk]jn]ujpKXjqhjr]rh(j`)rh}rh(jYUjcKjZjhjbjfjdjpjf}rh(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)rh}rh(jYXK**For Debugging over emulator use "No Boot/Sleep" Setting as shown below**:jcKjZjhjbjfjdjpjf}rh(jh]ji]jj]jk]jn]ujpKZjqhjr]rh(j)rh}rh(jYXJ**For Debugging over emulator use "No Boot/Sleep" Setting as shown below**jf}rh(jh]ji]jj]jk]jn]ujZjhjr]rhj{XFFor Debugging over emulator use "No Boot/Sleep" Setting as shown belowrhrh}rh(jYUjZjhubajdjubj{X:rh}rh(jYX:jZjhubeubeubjB)rh}rh(jYXA.. Image:: ../../../images/Boot_Switch_NoBoot.jpg :scale: 50% jZjfjbjfjdjEjf}rh(UscaleK2UuriX+rtos/../../../images/Boot_Switch_NoBoot.jpgrhjk]jj]jh]ji]jH}rhU*jhsjn]ujpNjqhjr]ubjZ)rh}rh(jYUjZjfjbjfjdj]jf}rh(jh]ji]jj]jk]jn]ujpK_jqhjr]rh(j`)rh}rh(jYUjcKjZjhjbjfjdjpjf}rh(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)rh}rh(jYXOThe table below provides the list of all the boot modes supported on the GP EVMrhjcKjZjhjbjfjdjpjf}rh(jh]ji]jj]jk]jn]ujpKajqhjr]rhj{XOThe table below provides the list of all the boot modes supported on the GP EVMrhrh}rh(jYjhjZjhubaubeubj)rh}rh(jYXs**Note: Read the PCB marking around the boot switch for your EVM to interpret of ON and OFF marking on the switch**rhjZjfjbjfjdjjf}rh(jh]ji]jj]jk]jn]ujpKcjqhjr]rhj)rh}rh(jYjhjf}rh(jh]ji]jj]jk]jn]ujZjhjr]rhj{XoNote: Read the PCB marking around the boot switch for your EVM to interpret of ON and OFF marking on the switchrhrh}rh(jYUjZjhubajdjubaubjC)rh}rh(jYUjZjfjbjfjdj`jf}rh(jGX-jk]jj]jh]ji]jn]ujpKfjqhjr]rh(j/)rh}rh(jYX.For Rev C K2G02 GP EVM: ON = '0' and OFF = '1'rhjZjhjbjfjdj2jf}rh(jh]ji]jj]jk]jn]ujpNjqhjr]rhj)rh}rh(jYjhjZjhjbjfjdjjf}rh(jh]ji]jj]jk]jn]ujpKfjr]rhj{X.For Rev C K2G02 GP EVM: ON = '0' and OFF = '1'rhrh}rh(jYjhjZjhubaubaubj/)rh}rh(jYX5For Rev C/Rev D K2G12 GP EVM: ON = '1' and OFF = '0' jZjhjbjfjdj2jf}rh(jh]ji]jj]jk]jn]ujpNjqhjr]rhj)rh}rh(jYX4For Rev C/Rev D K2G12 GP EVM: ON = '1' and OFF = '0'rhjZjhjbjfjdjjf}rh(jh]ji]jj]jk]jn]ujpKgjr]rhj{X4For Rev C/Rev D K2G12 GP EVM: ON = '1' and OFF = '0'rhrh}rh(jYjhjZjhubaubaubeubj)rh}rh(jYXOther Boot Pin configurations:rhjZjfjbjfjdjjf}rh(jh]ji]jj]jk]jn]ujpKijqhjr]rhj{XOther Boot Pin configurations:rhrh}rh(jYjhjZjhubaubjZ)rh}rh(jYUjZjfjbjfjdj]jf}rh(jh]ji]jj]jk]jn]ujpKkjqhjr]rhj`)rh}rh(jYUjcKjZjhjbjfjdjpjf}rh(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjd$)rh}rh(jYUjZjfjbjfjdjg$jf}rh(jh]ji]jj]jk]jn]ujpNjqhjr]rhjj$)rh}rh(jYUjf}rh(jk]jj]jh]ji]jn]UcolsKujZjhjr]rh(jo$)rh}rh(jYUjf}rh(jk]jj]jh]ji]jn]UcolwidthKujZjhjr]jdjs$ubjo$)rh}rh(jYUjf}rh(jk]jj]jh]ji]jn]UcolwidthKujZjhjr]jdjs$ubjz$)rh}rh(jYUjf}rh(jh]ji]jj]jk]jn]ujZjhjr]rhj$)ri}ri(jYUjf}ri(jh]ji]jj]jk]jn]ujZjhjr]ri(j$)ri}ri(jYUjf}ri(jh]ji]jj]jk]jn]ujZjijr]rij)ri}r i(jYXSW3[4:1]r ijZjijbjfjdjjf}r i(jh]ji]jj]jk]jn]ujpKnjr]r ij{XSW3[4:1]r iri}ri(jYj ijZjiubaubajdj$ubj$)ri}ri(jYUjf}ri(jh]ji]jj]jk]jn]ujZjijr]rij)ri}ri(jYX BOOT MODErijZjijbjfjdjjf}ri(jh]ji]jj]jk]jn]ujpKnjr]rij{X BOOT MODEriri}ri(jYjijZjiubaubajdj$ubejdj$ubajdj$ubj$)ri}ri(jYUjf}ri(jh]ji]jj]jk]jn]ujZjhjr]ri(j$)r i}r!i(jYUjf}r"i(jh]ji]jj]jk]jn]ujZjijr]r#i(j$)r$i}r%i(jYUjf}r&i(jh]ji]jj]jk]jn]ujZj ijr]r'ij)r(i}r)i(jYX 0000 (0x0)r*ijZj$ijbjfjdjjf}r+i(jh]ji]jj]jk]jn]ujpKpjr]r,ij{X 0000 (0x0)r-ir.i}r/i(jYj*ijZj(iubaubajdj$ubj$)r0i}r1i(jYUjf}r2i(jh]ji]jj]jk]jn]ujZj ijr]r3ij)r4i}r5i(jYX Sleep/No Bootr6ijZj0ijbjfjdjjf}r7i(jh]ji]jj]jk]jn]ujpKpjr]r8ij{X Sleep/No Bootr9ir:i}r;i(jYj6ijZj4iubaubajdj$ubejdj$ubj$)ri(jh]ji]jj]jk]jn]ujZjijr]r?i(j$)r@i}rAi(jYUjf}rBi(jh]ji]jj]jk]jn]ujZjj(jh]ji]jj]jk]jn]ujZj8jjr]r?jj)r@j}rAj(jYX 1010 (0xa)rBjjZjk(jYXh
jZjfjbjfjdjcjf}r?k(UformatXhtmljjjk]jj]jh]ji]jn]ujpKjqhjr]r@kj{Xh
rAkrBk}rCk(jYUjZj=kubaubj)rDk}rEk(jYX **NOTE** On Rev C boards and earlier revisions of the board, users who plan to connect the USB cable to USB 3.0 cable need to follow the instructions to update Emulation firmware using steps described in the article `Updating\_the\_XDS200\_firmware `__ Without the firmware update, users are recommended to disconnect the mini USB cable from the XDS USB connector before powering up the EVM and reconnect after board power up is complete.jZjfjbjfjdjjf}rFk(jh]ji]jj]jk]jn]ujpKjqhjr]rGk(j)rHk}rIk(jYX**NOTE**jf}rJk(jh]ji]jj]jk]jn]ujZjDkjr]rKkj{XNOTErLkrMk}rNk(jYUjZjHkubajdjubj{X On Rev C boards and earlier revisions of the board, users who plan to connect the USB cable to USB 3.0 cable need to follow the instructions to update Emulation firmware using steps described in the article rOkrPk}rQk(jYX On Rev C boards and earlier revisions of the board, users who plan to connect the USB cable to USB 3.0 cable need to follow the instructions to update Emulation firmware using steps described in the article jZjDkubj)rRk}rSk(jYXw`Updating\_the\_XDS200\_firmware `__jf}rTk(UnameXUpdating_the_XDS200_firmwarejXQhttp://dev.ti.com/tirex/explore/node?node=AADzJ8Y-La4f7Bi5Ga0TcA__FUz-xrs__LATESTjk]jj]jh]ji]jn]ujZjDkjr]rUkj{XUpdating_the_XDS200_firmwarerVkrWk}rXk(jYUjZjRkubajdjubj{X Without the firmware update, users are recommended to disconnect the mini USB cable from the XDS USB connector before powering up the EVM and reconnect after board power up is complete.rYkrZk}r[k(jYX Without the firmware update, users are recommended to disconnect the mini USB cable from the XDS USB connector before powering up the EVM and reconnect after board power up is complete.jZjDkubeubjc)r\k}r]k(jYX
jZjfjbjfjdjcjf}r^k(UformatXhtmljjjk]jj]jh]ji]jn]ujpKjqhjr]r_kj{X
r`krak}rbk(jYUjZj\kubaubjZ)rck}rdk(jYUjZjfjbjfjdj]jf}rek(jh]ji]jj]jk]jn]ujpKjqhjr]rfk(j`)rgk}rhk(jYUjcKjZjckjbjfjdjpjf}rik(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)rjk}rkk(jYX7**MIPI 60-pin header for connecting External emulator**rlkjcKjZjckjbjfjdjpjf}rmk(jh]ji]jj]jk]jn]ujpKjqhjr]rnkj)rok}rpk(jYjlkjf}rqk(jh]ji]jj]jk]jn]ujZjjkjr]rrkj{X3MIPI 60-pin header for connecting External emulatorrskrtk}ruk(jYUjZjokubajdjubaubeubj)rvk}rwk(jYXIf you are using a different JTAG, you can connect it at MIPI60 connector (EMU1). The MIPI 60-pin JTAG header is provided on-board for high speed real-time emulation. All JTAG and EMUxx signals are terminated on MIPI 60-pin header.rxkjZjfjbjfjdjjf}ryk(jh]ji]jj]jk]jn]ujpKjqhjr]rzkj{XIf you are using a different JTAG, you can connect it at MIPI60 connector (EMU1). The MIPI 60-pin JTAG header is provided on-board for high speed real-time emulation. All JTAG and EMUxx signals are terminated on MIPI 60-pin header.r{kr|k}r}k(jYjxkjZjvkubaubj)r~k}rk(jYXNo emulation firmware upgrade is required if users plan to use an external emulator The MIPI 60-pin JTAG header supports all standard (XDS510 or XDS560) TI DSP emulators. Please refer to the documentation supplied with your emulator for connection assistance.rkjZjfjbjfjdjjf}rk(jh]ji]jj]jk]jn]ujpKjqhjr]rkj{XNo emulation firmware upgrade is required if users plan to use an external emulator The MIPI 60-pin JTAG header supports all standard (XDS510 or XDS560) TI DSP emulators. Please refer to the documentation supplied with your emulator for connection assistance.rkrk}rk(jYjkjZj~kubaubj)rk}rk(jYXPowering up the EVMrkjKjZjfjbjfjdjjf}rk(jk]rkUid44rkajj]jh]rkji^aji]jn]ujpNjqhjr]rkj{XPowering up the EVMrkrk}rk(jYjkjZjkubaubj)rk}rk(jYXPower Supply specificationsrkjKjZjfjbjfjdjjf}rk(jk]rkUid45rkajj]jh]rkju^aji]jn]ujpNjqhjr]rkj{XPower Supply specificationsrkrk}rk(jYjkjZjkubaubj)rk}rk(jYX,[[Image:CUI_Isolated_Power_Supply.png|300px]jZjfjbjfjdjjf}rk(jjjk]jj]jh]ji]jn]ujpKjqhjr]rkj{X,[[Image:CUI_Isolated_Power_Supply.png|300px]rkrk}rk(jYUjZjkubaubj)rk}rk(jYXThe EVMK2G can be powered from a single +12V / 5.0A DC (60W) external power supply connected to the DC power jack (J3). Internally, +12V input is converted into required voltage levels using local DC-DC convertersrkjZjfjbjfjdjjf}rk(jh]ji]jj]jk]jn]ujpKjqhjr]rkj{XThe EVMK2G can be powered from a single +12V / 5.0A DC (60W) external power supply connected to the DC power jack (J3). Internally, +12V input is converted into required voltage levels using local DC-DC convertersrkrk}rk(jYjkjZjkubaubj)rk}rk(jYX{Please note that a power supply is included with the 66AK2GX Evaluation Module. The power supply has the following specs :rkjZjfjbjfjdjjf}rk(jh]ji]jj]jk]jn]ujpKjqhjr]rkj{X{Please note that a power supply is included with the 66AK2GX Evaluation Module. The power supply has the following specs :rkrk}rk(jYjkjZjkubaubjC)rk}rk(jYUjZjfjbjfjdj`jf}rk(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]rk(j/)rk}rk(jYX 12V DC outputrkjZjkjbjfjdj2jf}rk(jh]ji]jj]jk]jn]ujpNjqhjr]rkj)rk}rk(jYjkjZjkjbjfjdjjf}rk(jh]ji]jj]jk]jn]ujpKjr]rkj{X 12V DC outputrkrk}rk(jYjkjZjkubaubaubj/)rk}rk(jYX 5A outputrkjZjkjbjfjdj2jf}rk(jh]ji]jj]jk]jn]ujpNjqhjr]rkj)rk}rk(jYjkjZjkjbjfjdjjf}rk(jh]ji]jj]jk]jn]ujpKjr]rkj{X 5A outputrkrk}rk(jYjkjZjkubaubaubj/)rk}rk(jYX+Positive inner and negative outer terminalsrkjZjkjbjfjdj2jf}rk(jh]ji]jj]jk]jn]ujpNjqhjr]rkj)rk}rk(jYjkjZjkjbjfjdjjf}rk(jh]ji]jj]jk]jn]ujpKjr]rkj{X+Positive inner and negative outer terminalsrkrk}rk(jYjkjZjkubaubaubj/)rk}rk(jYX@Female barrel with 2.5mm inner diameter and 5.5mm outer diameterrkjZjkjbjfjdj2jf}rk(jh]ji]jj]jk]jn]ujpNjqhjr]rkj)rk}rk(jYjkjZjkjbjfjdjjf}rk(jh]ji]jj]jk]jn]ujpKjr]rkj{X@Female barrel with 2.5mm inner diameter and 5.5mm outer diameterrkrk}rk(jYjkjZjkubaubaubj/)rk}rk(jYXIsolated power supply jZjkjbjfjdj2jf}rk(jh]ji]jj]jk]jn]ujpNjqhjr]rkj)rk}rk(jYXIsolated power supplyrkjZjkjbjfjdjjf}rk(jh]ji]jj]jk]jn]ujpKjr]rkj{XIsolated power supplyrkrk}rk(jYjkjZjkubaubaubeubj)rk}rk(jYX CCS SetuprkjKjZjfjbjfjdjjf}rk(jk]rkUid46rkajj]jh]rkj)_aji]jn]ujpNjqhjr]rkj{X CCS Setuprkrk}rk(jYjkjZjkubaubj)rk}rk(jYXuThis section describes the setup to connect to 66AK2GX GP EVM using Code composer Studio environment and an emulator.rljZjfjbjfjdjjf}rl(jh]ji]jj]jk]jn]ujpKjqhjr]rlj{XuThis section describes the setup to connect to 66AK2GX GP EVM using Code composer Studio environment and an emulator.rlrl}rl(jYjljZjkubaubj)rl}rl(jYX6There are two scenarios while connecting to the EVM :rljZjfjbjfjdjjf}r l(jh]ji]jj]jk]jn]ujpKjqhjr]r lj{X6There are two scenarios while connecting to the EVM :r lr l}r l(jYjljZjlubaubjC)rl}rl(jYUjZjfjbjfjdj`jf}rl(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]rl(j/)rl}rl(jYX?**Connect to EVM without a SD card boot image to boot the EVM**rljZjljbjfjdj2jf}rl(jh]ji]jj]jk]jn]ujpNjqhjr]rlj)rl}rl(jYjljZjljbjfjdjjf}rl(jh]ji]jj]jk]jn]ujpKjr]rlj)rl}rl(jYjljf}rl(jh]ji]jj]jk]jn]ujZjljr]rlj{X;Connect to EVM without a SD card boot image to boot the EVMrlr l}r!l(jYUjZjlubajdjubaubaubj/)r"l}r#l(jYX<**Connect to EVM after booting an image from the SD card**. jZjljbjfjdj2jf}r$l(jh]ji]jj]jk]jn]ujpNjqhjr]r%lj)r&l}r'l(jYX;**Connect to EVM after booting an image from the SD card**.jZj"ljbjfjdjjf}r(l(jh]ji]jj]jk]jn]ujpKjr]r)l(j)r*l}r+l(jYX:**Connect to EVM after booting an image from the SD card**jf}r,l(jh]ji]jj]jk]jn]ujZj&ljr]r-lj{X6Connect to EVM after booting an image from the SD cardr.lr/l}r0l(jYUjZj*lubajdjubj{X.r1l}r2l(jYX.jZj&lubeubaubeubj)r3l}r4l(jYXsBefore discussing both these scenarios, let us look at how to pull in the latest KeystoneII device support in CCSv6r5ljZjfjbjfjdjjf}r6l(jh]ji]jj]jk]jn]ujpKjqhjr]r7lj{XsBefore discussing both these scenarios, let us look at how to pull in the latest KeystoneII device support in CCSv6r8lr9l}r:l(jYj5ljZj3lubaubjZ)r;l}rlj`)r?l}r@l(jYUjcKjZj;ljbjfjdjpjf}rAl(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)rBl}rCl(jYX;Update CCS v6 to install Keystone II device Support packagerDljZjfjbjfjdjjf}rEl(jk]rFlU;update-ccs-v6-to-install-keystone-ii-device-support-packagerGlajj]jh]ji]jn]rHlhaujpNjqhjr]rIlj{X;Update CCS v6 to install Keystone II device Support packagerJlrKl}rLl(jYjDljZjBlubaubj)rMl}rNl(jYXnAll revisions of the board require this step to be performed in order to get the latest GEL files and the target content for the K2G. This step will not be required for CCS versions higher than version 6.1.3. CCSv6.1.3 package contain KeystoneII device support package v1.1.4 which doesn\`t contain 66AK2GX GPEVM specific target files hence we recommend this update.jZjfjbjfjdjjf}rOl(jh]ji]jj]jk]jn]ujpKjqhjr]rPlj{XmAll revisions of the board require this step to be performed in order to get the latest GEL files and the target content for the K2G. This step will not be required for CCS versions higher than version 6.1.3. CCSv6.1.3 package contain KeystoneII device support package v1.1.4 which doesn`t contain 66AK2GX GPEVM specific target files hence we recommend this update.rQlrRl}rSl(jYXnAll revisions of the board require this step to be performed in order to get the latest GEL files and the target content for the K2G. This step will not be required for CCS versions higher than version 6.1.3. CCSv6.1.3 package contain KeystoneII device support package v1.1.4 which doesn\`t contain 66AK2GX GPEVM specific target files hence we recommend this update.jZjMlubaubj)rTl}rUl(jYX**Step 1** All CCS v6.1.3 and earlier version users are required to update the Keystone Device Support package by going into the Help->Check For UpdatesjZjfjbjfjdjjf}rVl(jh]ji]jj]jk]jn]ujpMjqhjr]rWl(j)rXl}rYl(jYX **Step 1**jf}rZl(jh]ji]jj]jk]jn]ujZjTljr]r[lj{XStep 1r\lr]l}r^l(jYUjZjXlubajdjubj{X All CCS v6.1.3 and earlier version users are required to update the Keystone Device Support package by going into the Help->Check For Updatesr_lr`l}ral(jYX All CCS v6.1.3 and earlier version users are required to update the Keystone Device Support package by going into the Help->Check For UpdatesjZjTlubeubjB)rbl}rcl(jYX1.. Image:: ../../../images/Check_for_Updates.png jZjfjbjfjdjEjf}rdl(UuriX*rtos/../../../images/Check_for_Updates.pngreljk]jj]jh]ji]jH}rflU*jelsjn]ujpMjqhjr]ubj)rgl}rhl(jYXc**Step 2** Select Keystone2 device support package. Follow menu options to continue with the updatejZjfjbjfjdjjf}ril(jh]ji]jj]jk]jn]ujpMjqhjr]rjl(j)rkl}rll(jYX **Step 2**jf}rml(jh]ji]jj]jk]jn]ujZjgljr]rnlj{XStep 2rolrpl}rql(jYUjZjklubajdjubj{XY Select Keystone2 device support package. Follow menu options to continue with the updaterrlrsl}rtl(jYXY Select Keystone2 device support package. Follow menu options to continue with the updatejZjglubeubj)rul}rvl(jYX**Step 3** After the update is complete go to Help->Installation details and check that Keystone2 device support package v1.1.5 or later are installed as shown belowjZjfjbjfjdjjf}rwl(jh]ji]jj]jk]jn]ujpM jqhjr]rxl(j)ryl}rzl(jYX **Step 3**jf}r{l(jh]ji]jj]jk]jn]ujZjuljr]r|lj{XStep 3r}lr~l}rl(jYUjZjylubajdjubj{X After the update is complete go to Help->Installation details and check that Keystone2 device support package v1.1.5 or later are installed as shown belowrlrl}rl(jYX After the update is complete go to Help->Installation details and check that Keystone2 device support package v1.1.5 or later are installed as shown belowjZjulubeubjB)rl}rl(jYXA.. Image:: ../../../images/KeystoneII_device_support_package.png jZjfjbjfjdjEjf}rl(UuriX:rtos/../../../images/KeystoneII_device_support_package.pngrljk]jj]jh]ji]jH}rlU*jlsjn]ujpMjqhjr]ubj)rl}rl(jYXu**Note:** The package can be downloaded separately from the link below and manually unzipped into CCSv6 installation.jZjfjbjfjdjjf}rl(jh]ji]jj]jk]jn]ujpMjqhjr]rl(j)rl}rl(jYX **Note:**jf}rl(jh]ji]jj]jk]jn]ujZjljr]rlj{XNote:rlrl}rl(jYUjZjlubajdjubj{Xl The package can be downloaded separately from the link below and manually unzipped into CCSv6 installation.rlrl}rl(jYXl The package can be downloaded separately from the link below and manually unzipped into CCSv6 installation.jZjlubeubjC)rl}rl(jYUjZjfjbjfjdj`jf}rl(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]rlj/)rl}rl(jYXX`Device Support Files `__ jZjljbjfjdj2jf}rl(jh]ji]jj]jk]jn]ujpNjqhjr]rlj)rl}rl(jYXW`Device Support Files `__rljZjljbjfjdjjf}rl(jh]ji]jj]jk]jn]ujpMjr]rlj)rl}rl(jYjljf}rl(UnameXDevice Support FilesjX<http://processors.wiki.ti.com/index.php/Device_support_filesjk]jj]jh]ji]jn]ujZjljr]rlj{XDevice Support Filesrlrl}rl(jYUjZjlubajdjubaubaubaubjZ)rl}rl(jYUjZjfjbjfjdj]jf}rl(jh]ji]jj]jk]jn]ujpMjqhjr]rl(j`)rl}rl(jYUjcKjZjljbjfjdjpjf}rl(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)rl}rl(jYX**Note for K2G devices:** If using CCS v6.1.2 and Keystone2 device support v1.1.7, 66AK2G02 would not show up in the list of devices when creating the target configuration. This is due to an incompatibility in the XML parser in CCS v6.1.2 with the K2G device xml. In order to work-around this issue, make the change in 66AK2G02.xml as illustrated below in order to have 66AK2G02 display in the device list. This problem does not exist in CCS v6.1.3 onwards as the XML parser has been updated.jcKjZjljbjfjdjpjf}rl(jh]ji]jj]jk]jn]ujpMjqhjr]rl(j)rl}rl(jYX**Note for K2G devices:**jf}rl(jh]ji]jj]jk]jn]ujZjljr]rlj{XNote for K2G devices:rlrl}rl(jYUjZjlubajdjubj{X If using CCS v6.1.2 and Keystone2 device support v1.1.7, 66AK2G02 would not show up in the list of devices when creating the target configuration. This is due to an incompatibility in the XML parser in CCS v6.1.2 with the K2G device xml. In order to work-around this issue, make the change in 66AK2G02.xml as illustrated below in order to have 66AK2G02 display in the device list. This problem does not exist in CCS v6.1.3 onwards as the XML parser has been updated.rlrl}rl(jYX If using CCS v6.1.2 and Keystone2 device support v1.1.7, 66AK2G02 would not show up in the list of devices when creating the target configuration. This is due to an incompatibility in the XML parser in CCS v6.1.2 with the K2G device xml. In order to work-around this issue, make the change in 66AK2G02.xml as illustrated below in order to have 66AK2G02 display in the device list. This problem does not exist in CCS v6.1.3 onwards as the XML parser has been updated.jZjlubeubeubjZ)rl}rl(jYUjZjfjbjfjdj]jf}rl(jh]ji]jj]jk]jn]ujpM jqhjr]rlj`)rl}rl(jYXAC:\\ti\\ccsv6\\ccs\_base\\common\\targetdb\\devices\\66AK2G02.xmljcKjZjljbjfjdjpjf}rl(jh]ji]jj]jk]jn]ujpM jqhjr]rlj{X9C:\ti\ccsv6\ccs_base\common\targetdb\devices\66AK2G02.xmlrlrl}rl(jYXAC:\\ti\\ccsv6\\ccs\_base\\common\\targetdb\\devices\\66AK2G02.xmljZjlubaubaubjZ)rl}rl(jYUjZjfjbjfjdj]jf}rl(jh]ji]jj]jk]jn]ujpM"jqhjr]rlj`)rl}rl(jYXLine #1rljcKjZjljbjfjdjpjf}rl(jh]ji]jj]jk]jn]ujpM"jqhjr]rlj{XLine #1rlrl}rl(jYjljZjlubaubaubjZ)rl}rl(jYUjZjfjbjfjdj]jf}rl(jh]ji]jj]jk]jn]ujpM$jqhjr]rl(j`)rl}rl(jYX6rljcKjZjljbjfjdjpjf}rl(jh]ji]jj]jk]jn]ujpM$jqhjr]rlj{X6rlrl}rl(jYjljZjlubaubj`)rl}rl(jYXtorljcKjZjljbjfjdjpjf}rl(jh]ji]jj]jk]jn]ujpM%jqhjr]rlj{Xtorlrl}rl(jYjljZjlubaubj`)rl}rl(jYX6rljcKjZjljbjfjdjpjf}rl(jh]ji]jj]jk]jn]ujpM&jqhjr]rlj{X6rlrl}rl(jYjljZjlubaubeubjZ)rl}rl(jYUjZjfjbjfjdj]jf}rl(jh]ji]jj]jk]jn]ujpM(jqhjr]rlj`)rl}rl(jYUjcKjZjljbjfjdjpjf}rl(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjZ)rl}rl(jYUjZjfjbjfjdj]jf}rl(jh]ji]jj]jk]jn]ujpM*jqhjr]rlj`)rl}rl(jYUjcKjZjljbjfjdjpjf}rl(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)rm}rm(jYX$Connect without a SD card boot imagermjKjZjfjbjfjdjjf}rm(jk]rmUid47rmajj]jh]rmjb_aji]jn]ujpNjqhjr]rmj{X$Connect without a SD card boot imagermr m}r m(jYjmjZjmubaubj)r m}r m(jYX .. _ConfiguringTargetConfigFile:jKjZjfjbjfjdjjf}r m(jk]jj]jh]ji]jn]jUconfiguringtargetconfigfilermujpMjqhjr]ubj)rm}rm(jYX&Configuring target configuration filesrmjKjZjfjbjfj}rmj%j msjdjjf}rm(jk]rm(Uid48rmjmejj]jh]rmjn_aji]jn]rmj%aujpNjqhj}rmjmj msjr]rmj{X&Configuring target configuration filesrmrm}rm(jYjmjZjmubaubj)rm}rm(jYXqLaunch CCS and create new target configuration(File->New->Target Configuration file) as shown in the images belowrmjZjfjbjfjdjjf}r m(jh]ji]jj]jk]jn]ujpM4jqhjr]r!mj{XqLaunch CCS and create new target configuration(File->New->Target Configuration file) as shown in the images belowr"mr#m}r$m(jYjmjZjmubaubjB)r%m}r&m(jYX8.. Image:: ../../../images/CCS_target_configuration.png jZjfjbjfjdjEjf}r'm(UuriX1rtos/../../../images/CCS_target_configuration.pngr(mjk]jj]jh]ji]jH}r)mU*j(msjn]ujpM8jqhjr]ubj)r*m}r+m(jYXoProvide appropriate name to the configuration. Select Spectrum digital XDS200 emulator and target as K2G GPEVM.r,mjZjfjbjfjdjjf}r-m(jh]ji]jj]jk]jn]ujpM9jqhjr]r.mj{XoProvide appropriate name to the configuration. Select Spectrum digital XDS200 emulator and target as K2G GPEVM.r/mr0m}r1m(jYj,mjZj*mubaubj)r2m}r3m(jYX**Note:** If you don\`t find the 66AK2G02 target make sure you have installed the CCSv6.1.3 package or for CCSv6.1.2 and earlier ensure that you have done the software update correctly as shown in the how to section below.jZjfjbjfjdjjf}r4m(jh]ji]jj]jk]jn]ujpM<jqhjr]r5m(j)r6m}r7m(jYX **Note:**jf}r8m(jh]ji]jj]jk]jn]ujZj2mjr]r9mj{XNote:r:mr;m}rm}r?m(jYX If you don\`t find the 66AK2G02 target make sure you have installed the CCSv6.1.3 package or for CCSv6.1.2 and earlier ensure that you have done the software update correctly as shown in the how to section below.jZj2mubeubjB)r@m}rAm(jYX>.. Image:: ../../../images/K2G_GPEVM_Target_configuration.jpg jZjfjbjfjdjEjf}rBm(UuriX7rtos/../../../images/K2G_GPEVM_Target_configuration.jpgrCmjk]jj]jh]ji]jH}rDmU*jCmsjn]ujpMBjqhjr]ubj)rEm}rFm(jYXIn advance settings, make sure that the gel files are populated correctly. The following GEL files and their corresponding cores are provided below:rGmjZjfjbjfjdjjf}rHm(jh]ji]jj]jk]jn]ujpMCjqhjr]rImj{XIn advance settings, make sure that the gel files are populated correctly. The following GEL files and their corresponding cores are provided below:rJmrKm}rLm(jYjGmjZjEmubaubjC)rMm}rNm(jYUjZjfjbjfjdj`jf}rOm(jGX-jk]jj]jh]ji]jn]ujpMGjqhjr]rPm(j/)rQm}rRm(jYXC66X Core: evmk2g.gelrSmjZjMmjbjfjdj2jf}rTm(jh]ji]jj]jk]jn]ujpNjqhjr]rUmj)rVm}rWm(jYjSmjZjQmjbjfjdjjf}rXm(jh]ji]jj]jk]jn]ujpMGjr]rYmj{XC66X Core: evmk2g.gelrZmr[m}r\m(jYjSmjZjVmubaubaubj/)r]m}r^m(jYXA15 Core: evmk2g\_arm.gel jZjMmjbjfjdj2jf}r_m(jh]ji]jj]jk]jn]ujpNjqhjr]r`mj)ram}rbm(jYXA15 Core: evmk2g\_arm.geljZj]mjbjfjdjjf}rcm(jh]ji]jj]jk]jn]ujpMHjr]rdmj{XA15 Core: evmk2g_arm.gelremrfm}rgm(jYXA15 Core: evmk2g\_arm.geljZjamubaubaubeubj)rhm}rim(jYXConnecting to targetrjmjKjZjfjbjfjdjjf}rkm(jk]rlmUid49rmmajj]jh]rnmj=`aji]jn]ujpNjqhjr]romj{XConnecting to targetrpmrqm}rrm(jYjjmjZjhmubaubj)rsm}rtm(jYX**Step1 :** Download Code composer Studio v6.1.3 or for CCSv6.1.2 and earlier, ensure it contains Keystone device support package version 1.1.5 as described in the how to guidejZjfjbjfjdjjf}rum(jh]ji]jj]jk]jn]ujpMMjqhjr]rvm(j)rwm}rxm(jYX **Step1 :**jf}rym(jh]ji]jj]jk]jn]ujZjsmjr]rzmj{XStep1 :r{mr|m}r}m(jYUjZjwmubajdjubj{X Download Code composer Studio v6.1.3 or for CCSv6.1.2 and earlier, ensure it contains Keystone device support package version 1.1.5 as described in the how to guider~mrm}rm(jYX Download Code composer Studio v6.1.3 or for CCSv6.1.2 and earlier, ensure it contains Keystone device support package version 1.1.5 as described in the how to guidejZjsmubeubj)rm}rm(jYX`Install Code composer Studio v6 for K2G `__rmjZjfjbjfjdjjf}rm(jh]ji]jj]jk]jn]ujpMQjqhjr]rmj)rm}rm(jYjmjf}rm(UnameX'Install Code composer Studio v6 for K2GjXjhttp://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_overview.html#code-composer-studiojk]jj]jh]ji]jn]ujZjmjr]rmj{X'Install Code composer Studio v6 for K2Grmrm}rm(jYUjZjmubajdjubaubj )rm}rm(jYUjZjfjbjfjdj3 jf}rm(jh]ji]jj]jk]jn]ujpNjqhjr]rmj )rm}rm(jYX**Step2:** 66AK2GX GP EVM contains boot switches to configure for "No boot/sleep" mode. So configure the boot switches to No Boot Mode as described in the SettingBootSwitches_ jZjmjbjfjdj jf}rm(jh]ji]jj]jk]jn]ujpMVjr]rm(j )rm}rm(jYXE**Step2:** 66AK2GX GP EVM contains boot switches to configure for "NormjZjmjbjfjdj jf}rm(jh]ji]jj]jk]jn]ujpMVjr]rm(j)rm}rm(jYX **Step2:**jf}rm(jh]ji]jj]jk]jn]ujZjmjr]rmj{XStep2:rmrm}rm(jYUjZjmubajdjubj{X; 66AK2GX GP EVM contains boot switches to configure for "Normrm}rm(jYX; 66AK2GX GP EVM contains boot switches to configure for "NojZjmubeubj )rm}rm(jYUjf}rm(jh]ji]jj]jk]jn]ujZjmjr]rmj)rm}rm(jYXiboot/sleep" mode. So configure the boot switches to No Boot Mode as described in the SettingBootSwitches_jZjmjbjfjdjjf}rm(jh]ji]jj]jk]jn]ujpMUjr]rm(j{XUboot/sleep" mode. So configure the boot switches to No Boot Mode as described in the rmrm}rm(jYXUboot/sleep" mode. So configure the boot switches to No Boot Mode as described in the jZjmubj)rm}rm(jYXSettingBootSwitches_jKjZjmjdjjf}rm(UnameXSettingBootSwitchesjk]jj]jh]ji]jn]jj_hujr]rmj{XSettingBootSwitchesrmrm}rm(jYUjZjmubaubeubajdj2 ubeubaubj)rm}rm(jYX^**Step3:** Connect an XDS200 Emulator to XDS USB of the GP EVM as shown in ConnectingEmulator_rmjZjfjbjfjdjjf}rm(jh]ji]jj]jk]jn]ujpMXjqhjr]rm(j)rm}rm(jYX **Step3:**jf}rm(jh]ji]jj]jk]jn]ujZjmjr]rmj{XStep3:rmrm}rm(jYUjZjmubajdjubj{XA Connect an XDS200 Emulator to XDS USB of the GP EVM as shown in rmrm}rm(jYXA Connect an XDS200 Emulator to XDS USB of the GP EVM as shown in jZjmubj)rm}rm(jYXConnectingEmulator_jKjZjmjdjjf}rm(UnameXConnectingEmulatorjk]jj]jh]ji]jn]jjjujr]rmj{XConnectingEmulatorrmrm}rm(jYUjZjmubaubeubj)rm}rm(jYX{**Step4:** Launch CCS and create new target configuration as discussed in the previous section ConfiguringTargetConfigFile_jZjfjbjfjdjjf}rm(jh]ji]jj]jk]jn]ujpMZjqhjr]rm(j)rm}rm(jYX **Step4:**jf}rm(jh]ji]jj]jk]jn]ujZjmjr]rmj{XStep4:rmrm}rm(jYUjZjmubajdjubj{XU Launch CCS and create new target configuration as discussed in the previous section rmrm}rm(jYXU Launch CCS and create new target configuration as discussed in the previous section jZjmubj)rm}rm(jYXConfiguringTargetConfigFile_jKjZjmjdjjf}rm(UnameXConfiguringTargetConfigFilejk]jj]jh]ji]jn]jjmujr]rmj{XConfiguringTargetConfigFilermrm}rm(jYUjZjmubaubeubj)rm}rm(jYX8**Step5**: Launch Target configuration you just created.rmjZjfjbjfjdjjf}rm(jh]ji]jj]jk]jn]ujpM]jqhjr]rm(j)rm}rm(jYX **Step5**jf}rm(jh]ji]jj]jk]jn]ujZjmjr]rmj{XStep5rmrm}rm(jYUjZjmubajdjubj{X/: Launch Target configuration you just created.rmrm}rm(jYX/: Launch Target configuration you just created.jZjmubeubjB)rm}rm(jYX7.. Image:: ../../../images/K2G_Launch_targetConfig.png jZjfjbjfjdjEjf}rm(UuriX0rtos/../../../images/K2G_Launch_targetConfig.pngrmjk]jj]jh]ji]jH}rmU*jmsjn]ujpM`jqhjr]ubj )rm}rm(jYUjZjfjbjfjdj3 jf}rm(jh]ji]jj]jk]jn]ujpNjqhjr]rmj )rm}rm(jYX^**Step6**:K2G can be a DSP or an ARM master boot device so connect to the C66x or the A15\_0. jZjmjbjfjdj jf}rm(jh]ji]jj]jk]jn]ujpMbjr]rm(j )rm}rm(jYXE**Step6**:K2G can be a DSP or an ARM master boot device so connect tormjZjmjbjfjdj jf}rn(jh]ji]jj]jk]jn]ujpMbjr]rn(j)rn}rn(jYX **Step6**jf}rn(jh]ji]jj]jk]jn]ujZjmjr]rnj{XStep6rnrn}rn(jYUjZjnubajdjubj{X<:K2G can be a DSP or an ARM master boot device so connect tor nr n}r n(jYX<:K2G can be a DSP or an ARM master boot device so connect tojZjmubeubj )r n}r n(jYUjf}rn(jh]ji]jj]jk]jn]ujZjmjr]rnj)rn}rn(jYXthe C66x or the A15\_0.jZj njbjfjdjjf}rn(jh]ji]jj]jk]jn]ujpMbjr]rnj{Xthe C66x or the A15_0.rnrn}rn(jYXthe C66x or the A15\_0.jZjnubaubajdj2 ubeubaubj)rn}rn(jYX **GEL Log**rnjZjfjbjfjdjjf}rn(jh]ji]jj]jk]jn]ujpMdjqhjr]rnj)rn}rn(jYjnjf}rn(jh]ji]jj]jk]jn]ujZjnjr]rnj{XGEL Logr nr!n}r"n(jYUjZjnubajdjubaubj)r#n}r$n(jYXA15_0: GEL Output: PLL has been configured (24.0 MHz * 100 / 1 / 4 = 600.0 MHz) A15_0: GEL Output: ARM PLL has been configured with ref clock 24MHz, -sysclkp_period 41.6666 (24.0 MHz * 100 / 1 / 4 = 600.0 MHz) A15_0: GEL Output: Power on all PSC modules and DSP domains... A15_0: GEL Output: Power on PCIE PSC modules and DSP domains... Done. A15_0: GEL Output: UART PLL has been configured (24.0 MHz * 128 / 1 / 8 = 384.0 MHz) A15_0: GEL Output: NSS PLL has been configured (24.0 MHz * 250 / 3 / 2 = 1000.0 MHz) A15_0: GEL Output: ICSS PLL has been configured (24.0 MHz * 250 / 3 / 10 = 200.0 MHz) A15_0: GEL Output: DSS PLL has been configured (24.0 MHz * 198 / 12 / 16 = 24.75 MHz) A15_0: GEL Output: DDR PLL has been configured (24.0 MHz * 250 / 3 / 10 = 200.0 MHz) A15_0: GEL Output: XMC setup complete. A15_0: GEL Output: DDR3 PLL Setup ... A15_0: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 400MHz. A15_0: GEL Output: DDR3A initialization completejZjfjbjfjdjjf}r%n(jjjk]jj]jh]ji]jn]ujpM&jqhjr]r&nj{XA15_0: GEL Output: PLL has been configured (24.0 MHz * 100 / 1 / 4 = 600.0 MHz) A15_0: GEL Output: ARM PLL has been configured with ref clock 24MHz, -sysclkp_period 41.6666 (24.0 MHz * 100 / 1 / 4 = 600.0 MHz) A15_0: GEL Output: Power on all PSC modules and DSP domains... A15_0: GEL Output: Power on PCIE PSC modules and DSP domains... Done. A15_0: GEL Output: UART PLL has been configured (24.0 MHz * 128 / 1 / 8 = 384.0 MHz) A15_0: GEL Output: NSS PLL has been configured (24.0 MHz * 250 / 3 / 2 = 1000.0 MHz) A15_0: GEL Output: ICSS PLL has been configured (24.0 MHz * 250 / 3 / 10 = 200.0 MHz) A15_0: GEL Output: DSS PLL has been configured (24.0 MHz * 198 / 12 / 16 = 24.75 MHz) A15_0: GEL Output: DDR PLL has been configured (24.0 MHz * 250 / 3 / 10 = 200.0 MHz) A15_0: GEL Output: XMC setup complete. A15_0: GEL Output: DDR3 PLL Setup ... A15_0: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 400MHz. A15_0: GEL Output: DDR3A initialization completer'nr(n}r)n(jYUjZj#nubaubjZ)r*n}r+n(jYUjZjfjbjfjdj]jf}r,n(jh]ji]jj]jk]jn]ujpMujqhjr]r-nj`)r.n}r/n(jYUjcKjZj*njbjfjdjpjf}r0n(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r1n}r2n(jYX!Connect with a SD card boot imager3njZjfjbjfjdjjf}r4n(jk]r5nU!connect-with-a-sd-card-boot-imager6najj]jh]ji]jn]r7nj8aujpNjqhjr]r8nj{X!Connect with a SD card boot imager9nr:n}r;n(jYj3njZj1nubaubj)rNew->Target Configuration file) as shown in the images belowr>njZjfjbjfjdjjf}r?n(jh]ji]jj]jk]jn]ujpMzjqhjr]r@nj{XqLaunch CCS and create new target configuration(File->New->Target Configuration file) as shown in the images belowrAnrBn}rCn(jYj>njZj`__jZjfjbjfjdjjf}rn(jh]ji]jj]jk]jn]ujpMjqhjr]rn(j)rn}rn(jYX **Step7**jf}rn(jh]ji]jj]jk]jn]ujZjnjr]rnj{XStep7rnrn}rn(jYUjZjnubajdjubj{X SD card boot image will typically load a secondary bootloader like u-boot that will put the DSP in reset so user will need to follow the instructions on the page that talks about rnrn}rn(jYX SD card boot image will typically load a secondary bootloader like u-boot that will put the DSP in reset so user will need to follow the instructions on the page that talks about jZjnubj)rn}rn(jYX`Taking DSP out of reset `__jf}rn(UnameXTaking DSP out of resetjXhttp://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/How_to_Guides.html#taking-the-c66x-out-of-reset-with-linux-running-on-the-arm-a15jk]jj]jh]ji]jn]ujZjnjr]rnj{XTaking DSP out of resetrnrn}rn(jYUjZjnubajdjubeubj)rn}rn(jYX**Note:** RTOS users don\`t need to follow this step as the Secondary bootloader (SBL) will put the DSP in idle state and not in reset if there is no code running on the DSP.jZjfjbjfjdjjf}rn(jh]ji]jj]jk]jn]ujpMjqhjr]rn(j)rn}rn(jYX **Note:**jf}rn(jh]ji]jj]jk]jn]ujZjnjr]rnj{XNote:rnrn}rn(jYUjZjnubajdjubj{X RTOS users don`t need to follow this step as the Secondary bootloader (SBL) will put the DSP in idle state and not in reset if there is no code running on the DSP.rnrn}rn(jYX RTOS users don\`t need to follow this step as the Secondary bootloader (SBL) will put the DSP in idle state and not in reset if there is no code running on the DSP.jZjnubeubj)rn}rn(jYX How to guidernjZjfjbjfjdjjf}rn(jk]rnU how-to-guidernajj]jh]ji]jn]rnhaujpNjqhjr]rnj{X How to guidernrn}rn(jYjnjZjnubaubj)rn}rn(jYXThis section guides users who are using older versions of the GP EVM which may require an update to the firmware flashed on the EVM or hardware updates to workaround specific issues. Each section specifies the affected versions and the fix for the issue.rnjZjfjbjfjdjjf}rn(jh]ji]jj]jk]jn]ujpMjqhjr]rnj{XThis section guides users who are using older versions of the GP EVM which may require an update to the firmware flashed on the EVM or hardware updates to workaround specific issues. Each section specifies the affected versions and the fix for the issue.roro}ro(jYjnjZjnubaubj)ro}ro(jYX*Create SD card to boot Linux on the GP EVMrojZjfjbjfjdjjf}ro(jk]roU*create-sd-card-to-boot-linux-on-the-gp-evmroajj]jh]ji]jn]r ojDaujpNjqhjr]r oj{X*Create SD card to boot Linux on the GP EVMr or o}r o(jYjojZjoubaubj)ro}ro(jYXqAll pre-production boards (Rev C and earlier) will not contain a SD card image in the kit without an image flashed on it for the Out of Box experience described in the Quick start guide. User are required to download the image seperately from the Processor SDK Linux portal and run a script to create the SD boot image. The steps to create the image are provided below:rojZjfjbjfjdjjf}ro(jh]ji]jj]jk]jn]ujpMjqhjr]roj{XqAll pre-production boards (Rev C and earlier) will not contain a SD card image in the kit without an image flashed on it for the Out of Box experience described in the Quick start guide. User are required to download the image seperately from the Processor SDK Linux portal and run a script to create the SD boot image. The steps to create the image are provided below:roro}ro(jYjojZjoubaubj)ro}ro(jYX**Step 1** Download the image k2g-evm-linux-xx.xx.xx.xx.img.zip from the link `Latest Processor SDK Linux `__jZjfjbjfjdjjf}ro(jh]ji]jj]jk]jn]ujpMjqhjr]ro(j)ro}ro(jYX **Step 1**jf}ro(jh]ji]jj]jk]jn]ujZjojr]roj{XStep 1roro}r o(jYUjZjoubajdjubj{XD Download the image k2g-evm-linux-xx.xx.xx.xx.img.zip from the link r!or"o}r#o(jYXD Download the image k2g-evm-linux-xx.xx.xx.xx.img.zip from the link jZjoubj)r$o}r%o(jYXl`Latest Processor SDK Linux `__jf}r&o(UnameXLatest Processor SDK LinuxjXKhttp://software-dl.ti.com/processor-sdk-linux/esd/K2G/latest/index_FDS.htmljk]jj]jh]ji]jn]ujZjojr]r'oj{XLatest Processor SDK Linuxr(or)o}r*o(jYUjZj$oubajdjubeubj)r+o}r,o(jYX**Step 2** Follow instructions to create a SD card for the EVM using the instruction in the `SD Card Creation Guide `__jZjfjbjfjdjjf}r-o(jh]ji]jj]jk]jn]ujpMjqhjr]r.o(j)r/o}r0o(jYX **Step 2**jf}r1o(jh]ji]jj]jk]jn]ujZj+ojr]r2oj{XStep 2r3or4o}r5o(jYUjZj/oubajdjubj{XR Follow instructions to create a SD card for the EVM using the instruction in the r6or7o}r8o(jYXR Follow instructions to create a SD card for the EVM using the instruction in the jZj+oubj)r9o}r:o(jYX`SD Card Creation Guide `__jf}r;o(UnameXSD Card Creation GuidejXhttp://software-dl.ti.com/processor-sdk-linux/esd/docs/latest/linux/Overview_Getting_Started_Guide.html#linux-sd-card-creation-guidejk]jj]jh]ji]jn]ujZj+ojr]ro}r?o(jYUjZj9oubajdjubeubj)r@o}rAo(jYX"Update the BMC firmware on the EVMrBojZjfjbjfjdjjf}rCo(jk]rDoU"update-the-bmc-firmware-on-the-evmrEoajj]jh]ji]jn]rFoj7aujpNjqhjr]rGoj{X"Update the BMC firmware on the EVMrHorIo}rJo(jYjBojZj@oubaubj)rKo}rLo(jYXThe section describes how the Board Management controller firmware on the board can be updated through the BMC UART interface. All boards prior to RevC, require a BMC update for the following issue:rMojZjfjbjfjdjjf}rNo(jh]ji]jj]jk]jn]ujpMjqhjr]rOoj{XThe section describes how the Board Management controller firmware on the board can be updated through the BMC UART interface. All boards prior to RevC, require a BMC update for the following issue:rPorQo}rRo(jYjMojZjKoubaubjC)rSo}rTo(jYUjZjfjbjfjdj`jf}rUo(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]rVoj/)rWo}rXo(jYXCDCM chip on the board generates clocks to modules like PCIe and USB. It is possible to use PCIe only in external clock mode on the EVM. However there can be use-cases where PCIe clock should be enabled with SoC running in internal clock mode. jZjSojbjfjdj2jf}rYo(jh]ji]jj]jk]jn]ujpNjqhjr]rZoj)r[o}r\o(jYXCDCM chip on the board generates clocks to modules like PCIe and USB. It is possible to use PCIe only in external clock mode on the EVM. However there can be use-cases where PCIe clock should be enabled with SoC running in internal clock mode.r]ojZjWojbjfjdjjf}r^o(jh]ji]jj]jk]jn]ujpMjr]r_oj{XCDCM chip on the board generates clocks to modules like PCIe and USB. It is possible to use PCIe only in external clock mode on the EVM. However there can be use-cases where PCIe clock should be enabled with SoC running in internal clock mode.r`orao}rbo(jYj]ojZj[oubaubaubaubj)rco}rdo(jYXD**Step 1** Install the LM flash programmer from link provided below:reojZjfjbjfjdjjf}rfo(jh]ji]jj]jk]jn]ujpMjqhjr]rgo(j)rho}rio(jYX **Step 1**jf}rjo(jh]ji]jj]jk]jn]ujZjcojr]rkoj{XStep 1rlormo}rno(jYUjZjhoubajdjubj{X: Install the LM flash programmer from link provided below:roorpo}rqo(jYX: Install the LM flash programmer from link provided below:jZjcoubeubjC)rro}rso(jYUjZjfjbjfjdj`jf}rto(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]ruoj/)rvo}rwo(jYXF`LMflashProgrammer tool `__ jZjrojbjfjdj2jf}rxo(jh]ji]jj]jk]jn]ujpNjqhjr]ryoj)rzo}r{o(jYXE`LMflashProgrammer tool `__r|ojZjvojbjfjdjjf}r}o(jh]ji]jj]jk]jn]ujpMjr]r~oj)ro}ro(jYj|ojf}ro(UnameXLMflashProgrammer tooljX(http://www.ti.com/tool/lmflashprogrammerjk]jj]jh]ji]jn]ujZjzojr]roj{XLMflashProgrammer toolroro}ro(jYUjZjoubajdjubaubaubaubj)ro}ro(jYX5**Step 2** Obtain latest BMC software for the K2G GP EVM can be obtained from the board manufacturer or from local TI contact. Production EVMs are shipped with latest BMC version 0.6.1.0. You can check the version of the BMC software by observing the version indicated on BMC LCD on the GP EVM after power up.jZjfjbjfjdjjf}ro(jh]ji]jj]jk]jn]ujpMjqhjr]ro(j)ro}ro(jYX **Step 2**jf}ro(jh]ji]jj]jk]jn]ujZjojr]roj{XStep 2roro}ro(jYUjZjoubajdjubj{X+ Obtain latest BMC software for the K2G GP EVM can be obtained from the board manufacturer or from local TI contact. Production EVMs are shipped with latest BMC version 0.6.1.0. You can check the version of the BMC software by observing the version indicated on BMC LCD on the GP EVM after power up.roro}ro(jYX+ Obtain latest BMC software for the K2G GP EVM can be obtained from the board manufacturer or from local TI contact. Production EVMs are shipped with latest BMC version 0.6.1.0. You can check the version of the BMC software by observing the version indicated on BMC LCD on the GP EVM after power up.jZjoubeubj)ro}ro(jYXb**Step 3** Connect the mini USB cable between host PC and ‘USB to SoC UART0’ port (J23) on EVMjZjfjbjfjdjjf}ro(jh]ji]jj]jk]jn]ujpMjqhjr]ro(j)ro}ro(jYX **Step 3**jf}ro(jh]ji]jj]jk]jn]ujZjojr]roj{XStep 3roro}ro(jYUjZjoubajdjubj{XX Connect the mini USB cable between host PC and ‘USB to SoC UART0’ port (J23) on EVMroro}ro(jYXX Connect the mini USB cable between host PC and ‘USB to SoC UART0’ port (J23) on EVMjZjoubeubj)ro}ro(jYX9**Step 4** Remove the jumper J10 and power on the K2G EVMrojZjfjbjfjdjjf}ro(jh]ji]jj]jk]jn]ujpMjqhjr]ro(j)ro}ro(jYX **Step 4**jf}ro(jh]ji]jj]jk]jn]ujZjojr]roj{XStep 4roro}ro(jYUjZjoubajdjubj{X/ Remove the jumper J10 and power on the K2G EVMroro}ro(jYX/ Remove the jumper J10 and power on the K2G EVMjZjoubeubj)ro}ro(jYXL**Step 5** Open the LM Flash programmer utility on the windows host machine.jZjfjbjfjdjjf}ro(jh]ji]jj]jk]jn]ujpMjqhjr]ro(j)ro}ro(jYX **Step 5**jf}ro(jh]ji]jj]jk]jn]ujZjojr]roj{XStep 5roro}ro(jYUjZjoubajdjubj{XB Open the LM Flash programmer utility on the windows host machine.roro}ro(jYXB Open the LM Flash programmer utility on the windows host machine.jZjoubeubj)ro}ro(jYX**Step 6** In the LM Flash Programmer Utility ‘Configuration’ tab, in the interface section, select ‘Serial (UART)’ from the drop-down box on the left.Refer to the image provided below:jZjfjbjfjdjjf}ro(jh]ji]jj]jk]jn]ujpMjqhjr]ro(j)ro}ro(jYX **Step 6**jf}ro(jh]ji]jj]jk]jn]ujZjojr]roj{XStep 6roro}ro(jYUjZjoubajdjubj{X In the LM Flash Programmer Utility ‘Configuration’ tab, in the interface section, select ‘Serial (UART)’ from the drop-down box on the left.Refer to the image provided below:roro}ro(jYX In the LM Flash Programmer Utility ‘Configuration’ tab, in the interface section, select ‘Serial (UART)’ from the drop-down box on the left.Refer to the image provided below:jZjoubeubjB)ro}ro(jYX3.. Image:: ../../../images/LMflashProg_Config.png jZjfjbjfjdjEjf}ro(UuriX+rtos/../../../images/LMflashProg_Config.pngrojk]jj]jh]ji]jH}roU*josjn]ujpMjqhjr]ubj)ro}ro(jYXI**Step 7** Select the BMC COM Port and set the ‘Baud Rate’ to 115200.rojZjfjbjfjdjjf}ro(jh]ji]jj]jk]jn]ujpMjqhjr]ro(j)ro}ro(jYX **Step 7**jf}ro(jh]ji]jj]jk]jn]ujZjojr]roj{XStep 7roro}ro(jYUjZjoubajdjubj{X? Select the BMC COM Port and set the ‘Baud Rate’ to 115200.roro}ro(jYX? Select the BMC COM Port and set the ‘Baud Rate’ to 115200.jZjoubeubjC)ro}ro(jYUjZjfjbjfjdj`jf}ro(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]roj/)ro}ro(jYXgThere will be two COM ports that appears on EVMs ‘USB to SoC UART0’ port. Select the one which is connected to BMC. To find which port corresponds to the BMC, you can open a serial terminal program or Device Manager on your PC and check the port number corresponding to "Silicon Labs CP210x: USB to UART Bridge: Standard COM Port (COM##)" as shown below: jZjojbjfjdj2jf}ro(jh]ji]jj]jk]jn]ujpNjqhjr]roj)ro}ro(jYXfThere will be two COM ports that appears on EVMs ‘USB to SoC UART0’ port. Select the one which is connected to BMC. To find which port corresponds to the BMC, you can open a serial terminal program or Device Manager on your PC and check the port number corresponding to "Silicon Labs CP210x: USB to UART Bridge: Standard COM Port (COM##)" as shown below:rojZjojbjfjdjjf}ro(jh]ji]jj]jk]jn]ujpMjr]roj{XfThere will be two COM ports that appears on EVMs ‘USB to SoC UART0’ port. Select the one which is connected to BMC. To find which port corresponds to the BMC, you can open a serial terminal program or Device Manager on your PC and check the port number corresponding to "Silicon Labs CP210x: USB to UART Bridge: Standard COM Port (COM##)" as shown below:roro}ro(jYjojZjoubaubaubaubjB)ro}ro(jYX+.. Image:: ../../../images/BMCUARTPort.png jZjfjbjfjdjEjf}ro(UuriX$rtos/../../../images/BMCUARTPort.pngrojk]jj]jh]ji]jH}roU*josjn]ujpMjqhjr]ubj)ro}ro(jYX**Note:** BMC outputs boot logs to serial console when EVM is powered ON. Connect the ‘USB to SoC UART0’ port to standard serial console application to find the right COM port that is connected to BMC.jZjfjbjfjdjjf}ro(jh]ji]jj]jk]jn]ujpMjqhjr]ro(j)ro}ro(jYX **Note:**jf}ro(jh]ji]jj]jk]jn]ujZjojr]roj{XNote:roro}rp(jYUjZjoubajdjubj{X BMC outputs boot logs to serial console when EVM is powered ON. Connect the ‘USB to SoC UART0’ port to standard serial console application to find the right COM port that is connected to BMC.rprp}rp(jYX BMC outputs boot logs to serial console when EVM is powered ON. Connect the ‘USB to SoC UART0’ port to standard serial console application to find the right COM port that is connected to BMC.jZjoubeubj)rp}rp(jYXe**Step 8** Set ‘Transfer Size’ to 60, and make sure ‘Disable Auto Baud Support’ is unchecked.jZjfjbjfjdjjf}rp(jh]ji]jj]jk]jn]ujpMjqhjr]rp(j)rp}r p(jYX **Step 8**jf}r p(jh]ji]jj]jk]jn]ujZjpjr]r pj{XStep 8r pr p}rp(jYUjZjpubajdjubj{X[ Set ‘Transfer Size’ to 60, and make sure ‘Disable Auto Baud Support’ is unchecked.rprp}rp(jYX[ Set ‘Transfer Size’ to 60, and make sure ‘Disable Auto Baud Support’ is unchecked.jZjpubeubj)rp}rp(jYXt**Step 9** In the 'Program' tab, select the binary image file bmc\_evmKS2\_K2G.bin in the section 'Select.bin file'.jZjfjbjfjdjjf}rp(jh]ji]jj]jk]jn]ujpMjqhjr]rp(j)rp}rp(jYX **Step 9**jf}rp(jh]ji]jj]jk]jn]ujZjpjr]rpj{XStep 9rprp}rp(jYUjZjpubajdjubj{Xh In the 'Program' tab, select the binary image file bmc_evmKS2_K2G.bin in the section 'Select.bin file'.rprp}rp(jYXj In the 'Program' tab, select the binary image file bmc\_evmKS2\_K2G.bin in the section 'Select.bin file'.jZjpubeubjB)r p}r!p(jYX3.. Image:: ../../../images/LMflashProg_program.png jZjfjbjfjdjEjf}r"p(UuriX,rtos/../../../images/LMflashProg_program.pngr#pjk]jj]jh]ji]jH}r$pU*j#psjn]ujpMjqhjr]ubj)r%p}r&p(jYXS**Step 10** Leave all other options as default, and press the ‘Program’ button.jZjfjbjfjdjjf}r'p(jh]ji]jj]jk]jn]ujpMjqhjr]r(p(j)r)p}r*p(jYX **Step 10**jf}r+p(jh]ji]jj]jk]jn]ujZj%pjr]r,pj{XStep 10r-pr.p}r/p(jYUjZj)pubajdjubj{XH Leave all other options as default, and press the ‘Program’ button.r0pr1p}r2p(jYXH Leave all other options as default, and press the ‘Program’ button.jZj%pubeubj)r3p}r4p(jYXB**Step 11** Wait till 'Program Complete' status in the status bar.r5pjZjfjbjfjdjjf}r6p(jh]ji]jj]jk]jn]ujpMjqhjr]r7p(j)r8p}r9p(jYX **Step 11**jf}r:p(jh]ji]jj]jk]jn]ujZj3pjr]r;pj{XStep 11rp(jYUjZj8pubajdjubj{X7 Wait till 'Program Complete' status in the status bar.r?pr@p}rAp(jYX7 Wait till 'Program Complete' status in the status bar.jZj3pubeubj)rBp}rCp(jYX5**Step 12** Connect the jumper J10 and reboot the EVMrDpjZjfjbjfjdjjf}rEp(jh]ji]jj]jk]jn]ujpMjqhjr]rFp(j)rGp}rHp(jYX **Step 12**jf}rIp(jh]ji]jj]jk]jn]ujZjBpjr]rJpj{XStep 12rKprLp}rMp(jYUjZjGpubajdjubj{X* Connect the jumper J10 and reboot the EVMrNprOp}rPp(jYX* Connect the jumper J10 and reboot the EVMjZjBpubeubj)rQp}rRp(jYX<Update XDS200 firmware and hardware components on the GP EVMrSpjZjfjbjfjdjjf}rTp(jk]rUpU`__jZjfjbjfjdjjf}rp(jh]ji]jj]jk]jn]ujpMjqhjr]rp(j{XKSteps to update the XDS200 firmware on the EVM are archived on the article rprp}rp(jYXKSteps to update the XDS200 firmware on the EVM are archived on the article jZjpubj)rp}rp(jYXw`Updating\_the\_XDS200\_firmware `__jf}rp(UnameXUpdating_the_XDS200_firmwarejXQhttp://dev.ti.com/tirex/explore/node?node=AADzJ8Y-La4f7Bi5Ga0TcA__FUz-xrs__LATESTjk]jj]jh]ji]jn]ujZjpjr]rpj{XUpdating_the_XDS200_firmwarerprp}rp(jYUjZjpubajdjubeubj)rp}rp(jYXHardware updates requiredrpjZjfjbjfjdjjf}rp(jk]rpUhardware-updates-requiredrpajj]jh]ji]jn]rphaujpNjqhjr]rpj{XHardware updates requiredrprp}rp(jYjpjZjpubaubjC)rp}rp(jYUjZjfjbjfjdj`jf}rp(jGX-jk]jj]jh]ji]jn]ujpM!jqhjr]rp(j/)rp}rp(jYXReplace R431 & R442 to 200ErpjZjpjbjfjdj2jf}rp(jh]ji]jj]jk]jn]ujpNjqhjr]rpj)rp}rp(jYjpjZjpjbjfjdjjf}rp(jh]ji]jj]jk]jn]ujpM!jr]rpj{XReplace R431 & R442 to 200Erprp}rp(jYjpjZjpubaubaubj/)rp}rp(jYX&Mount resistors R95, R107, R108, R115.rpjZjpjbjfjdj2jf}rp(jh]ji]jj]jk]jn]ujpNjqhjr]rpj)rp}rp(jYjpjZjpjbjfjdjjf}rp(jh]ji]jj]jk]jn]ujpM"jr]rpj{X&Mount resistors R95, R107, R108, R115.rprp}rp(jYjpjZjpubaubaubj/)rp}rp(jYX Mount D2, R600, R599 components.rpjZjpjbjfjdj2jf}rp(jh]ji]jj]jk]jn]ujpNjqhjr]rpj)rp}rp(jYjpjZjpjbjfjdjjf}rp(jh]ji]jj]jk]jn]ujpM#jr]rpj{X Mount D2, R600, R599 components.rprp}rp(jYjpjZjpubaubaubj/)rp}rp(jYXyRemove FB3 and connect a wire from R64.2 ‘rVCC\_VBUS\_XDS’ and R67.2 ‘VCC5V0\_DCDC’ as shown in the image below: jZjpjbjfjdj2jf}rp(jh]ji]jj]jk]jn]ujpNjqhjr]rpj)rp}rp(jYXxRemove FB3 and connect a wire from R64.2 ‘rVCC\_VBUS\_XDS’ and R67.2 ‘VCC5V0\_DCDC’ as shown in the image below:jZjpjbjfjdjjf}rp(jh]ji]jj]jk]jn]ujpM$jr]rpj{XuRemove FB3 and connect a wire from R64.2 ‘rVCC_VBUS_XDS’ and R67.2 ‘VCC5V0_DCDC’ as shown in the image below:rprp}rq(jYXxRemove FB3 and connect a wire from R64.2 ‘rVCC\_VBUS\_XDS’ and R67.2 ‘VCC5V0\_DCDC’ as shown in the image below:jZjpubaubaubeubjB)rq}rq(jYX?.. Image:: ../../../images/R64_to_R67_HWMod.png :scale: 70% jZjfjbjfjdjEjf}rq(UscaleKFUuriX)rtos/../../../images/R64_to_R67_HWMod.pngrqjk]jj]jh]ji]jH}rqU*jqsjn]ujpNjqhjr]ubj)rq}rq(jYX+Update the EVM for improved USB performancerqjZjfjbjfjdjjf}r q(jk]r qU+update-the-evm-for-improved-usb-performancer qajj]jh]ji]jn]r qhaujpNjqhjr]r qj{X+Update the EVM for improved USB performancerqrq}rq(jYjqjZjqubaubj)rq}rq(jYXThe external resistors for the USB (R442 and R431) are currently 10k Ω. We recommend that users need to replace these with 200 Ω / 1%.rqjZjfjbjfjdjjf}rq(jh]ji]jj]jk]jn]ujpM-jqhjr]rqj{XThe external resistors for the USB (R442 and R431) are currently 10k Ω. We recommend that users need to replace these with 200 Ω / 1%.rqrq}rq(jYjqjZjqubaubjZ)rq}rq(jYUjZjfjbjfjdj]jf}rq(jh]ji]jj]jk]jn]ujpM0jqhjr]rqj`)rq}rq(jYUjcKjZjqjbjfjdjpjf}rq(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjZ)r q}r!q(jYUjZjfjbjfjdj]jf}r"q(jh]ji]jj]jk]jn]ujpM2jqhjr]r#qj`)r$q}r%q(jYUjcKjZj qjbjfjdjpjf}r&q(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r'q}r(q(jYXUseful Resources and Supportr)qjZjfjbjfjdjjf}r*q(jk]r+qUuseful-resources-and-supportr,qajj]jh]ji]jn]r-qhaujpNjqhjr]r.qj{XUseful Resources and Supportr/qr0q}r1q(jYj)qjZj'qubaubjC)r2q}r3q(jYUjZjfjbjfjdj`jf}r4q(jGX-jk]jj]jh]ji]jn]ujpM7jqhjr]r5q(j/)r6q}r7q(jYX@`66AK2G02 Product folder `__r8qjZj2qjbjfjdj2jf}r9q(jh]ji]jj]jk]jn]ujpNjqhjr]r:qj)r;q}rqj)r?q}r@q(jYj8qjf}rAq(UnameX66AK2G02 Product folderjX"http://www.ti.com/product/66ak2g02jk]jj]jh]ji]jn]ujZj;qjr]rBqj{X66AK2G02 Product folderrCqrDq}rEq(jYUjZj?qubajdjubaubaubj/)rFq}rGq(jYX@`66AK2G12 Product folder `__rHqjZj2qjbjfjdj2jf}rIq(jh]ji]jj]jk]jn]ujpNjqhjr]rJqj)rKq}rLq(jYjHqjZjFqjbjfjdjjf}rMq(jh]ji]jj]jk]jn]ujpM8jr]rNqj)rOq}rPq(jYjHqjf}rQq(UnameX66AK2G12 Product folderjX"http://www.ti.com/product/66ak2g12jk]jj]jh]ji]jn]ujZjKqjr]rRqj{X66AK2G12 Product folderrSqrTq}rUq(jYUjZjOqubajdjubaubaubj/)rVq}rWq(jYXR`66AK2Gx GP EVM Technical Reference Manual `__rXqjZj2qjbjfjdj2jf}rYq(jh]ji]jj]jk]jn]ujpNjqhjr]rZqj)r[q}r\q(jYjXqjZjVqjbjfjdjjf}r]q(jh]ji]jj]jk]jn]ujpM9jr]r^qj)r_q}r`q(jYjXqjf}raq(UnameX)66AK2Gx GP EVM Technical Reference ManualjX"http://www.ti.com/lit/pdf/sprui65ajk]jj]jh]ji]jn]ujZj[qjr]rbqj{X)66AK2Gx GP EVM Technical Reference Manualrcqrdq}req(jYUjZj_qubajdjubaubaubj/)rfq}rgq(jYXA`66AK2Gx GP EVM Product folder `__rhqjZj2qjbjfjdj2jf}riq(jh]ji]jj]jk]jn]ujpNjqhjr]rjqj)rkq}rlq(jYjhqjZjfqjbjfjdjjf}rmq(jh]ji]jj]jk]jn]ujpM:jr]rnqj)roq}rpq(jYjhqjf}rqq(UnameX66AK2Gx GP EVM Product folderjXhttp://www.ti.com/tool/evmk2gjk]jj]jh]ji]jn]ujZjkqjr]rrqj{X66AK2Gx GP EVM Product folderrsqrtq}ruq(jYUjZjoqubajdjubaubaubj/)rvq}rwq(jYXG`66AK2Gx 1GHz GP EVM Product folder `__rxqjZj2qjbjfjdj2jf}ryq(jh]ji]jj]jk]jn]ujpNjqhjr]rzqj)r{q}r|q(jYjxqjZjvqjbjfjdjjf}r}q(jh]ji]jj]jk]jn]ujpM;jr]r~qj)rq}rq(jYjxqjf}rq(UnameX"66AK2Gx 1GHz GP EVM Product folderjXhttp://www.ti.com/tool/evmk2gxjk]jj]jh]ji]jn]ujZj{qjr]rqj{X"66AK2Gx 1GHz GP EVM Product folderrqrq}rq(jYUjZjqubajdjubaubaubj/)rq}rq(jYX]`Keystone E2E Support Forum `__ jZj2qjbX^internal padding after source/common/EVM_Hardware_Setup/66AK2G02_GP_EVM_Hardware_Setup.rst.incrqjdj2jf}rq(jh]ji]jj]jk]jn]ujpNjqhjr]rqj)rq}rq(jYX[`Keystone E2E Support Forum `__rqjZjqjbjfjdjjf}rq(jh]ji]jj]jk]jn]ujpM<jr]rqj)rq}rq(jYjqjf}rq(UnameXKeystone E2E Support ForumjX:https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639jk]jj]jh]ji]jn]ujZjqjr]rqj{XKeystone E2E Support Forumrqrq}rq(jYUjZjqubajdjubaubaubeubj)rq}rq(jYX66AK2G02 ICE EVM Hardware SetupjZjfjbjcjdjjf}rq(jjjk]jj]jh]ji]jn]ujpKtjqhjr]rqj{X66AK2G02 ICE EVM Hardware Setuprqrq}rq(jYUjZjqubaubj)rq}rq(jYX4====================================================jZjfjbjcjdjjf}rq(jjjk]jj]jh]ji]jn]ujpKujqhjr]rqj{X4====================================================rqrq}rq(jYUjZjqubaubeubj[)rq}rq(jYUjZjR\jbjXHsource/common/EVM_Hardware_Setup/66AK2G02_ICE_EVM_Hardware_setup.rst.incrqrq}rqbjdjejf}rq(jh]ji]jj]jk]rqUak2g02-ice-evm-hardware-setuprqajn]rqj)aujpKjqhjr]rq(jt)rq}rq(jYX66AK2G02 ICE EVM Hardware SetuprqjZjqjbjqjdjxjf}rq(jh]ji]jj]jk]jn]ujpKjqhjr]rqj{X66AK2G02 ICE EVM Hardware Setuprqrq}rq(jYjqjZjqubaubj[)rq}rq(jYUjKjZjqjbjqjdjejf}rq(jh]rqX descriptionrqaji]jj]jk]rqUid50rqajn]ujpKjqhjr]rq(jt)rq}rq(jYX DescriptionrqjZjqjbjqjdjxjf}rq(jh]ji]jj]jk]jn]ujpKjqhjr]rqj{X Descriptionrqrq}rq(jYjqjZjqubaubj)rq}rq(jYXAThe K2G ICE EVM is a high performance, cost-efficient, standalone development platform that enables users to evaluate and develop industrial communications applications for the Texas Instrument’s Keystone2 System-on-Chip (SoC) 66AK2G02. The K2G SOC (66AK2G02) is the new device from TI’s Keystone II architecture withrqjZjqjbjqjdjjf}rq(jh]ji]jj]jk]jn]ujpKjqhjr]rqj{XAThe K2G ICE EVM is a high performance, cost-efficient, standalone development platform that enables users to evaluate and develop industrial communications applications for the Texas Instrument’s Keystone2 System-on-Chip (SoC) 66AK2G02. The K2G SOC (66AK2G02) is the new device from TI’s Keystone II architecture withrqrq}rq(jYjqjZjqubaubjC)rq}rq(jYUjZjqjbjqjdj`jf}rq(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]rq(j/)rq}rq(jYXKARM® Cortex® -A15 Microprocessor Unit (ARM A15) Subsystem at up to 600MHzjZjqjbjqjdj2jf}rq(jh]ji]jj]jk]jn]ujpNjqhjr]rqj)rq}rq(jYXKARM® Cortex® -A15 Microprocessor Unit (ARM A15) Subsystem at up to 600MHzrqjZjqjbjqjdjjf}rq(jh]ji]jj]jk]jn]ujpKjr]rqj{XKARM® Cortex® -A15 Microprocessor Unit (ARM A15) Subsystem at up to 600MHzrqrq}rq(jYjqjZjqubaubaubj/)rq}rq(jYXAC66x Fixed- and Floating-Point VLIW DSP Subsystem at up to 600MHzrqjZjqjbjqjdj2jf}rq(jh]ji]jj]jk]jn]ujpNjqhjr]rqj)rq}rq(jYjqjZjqjbjqjdjjf}rq(jh]ji]jj]jk]jn]ujpKjr]rqj{XAC66x Fixed- and Floating-Point VLIW DSP Subsystem at up to 600MHzrqrq}rq(jYjqjZjqubaubaubj/)rq}rq(jYXRTwo Programmable Real-Time Unit and Industrial Communication Subsystems (PRU-ICSS)jZjqjbjqjdj2jf}rq(jh]ji]jj]jk]jn]ujpNjqhjr]rqj)rq}rq(jYXRTwo Programmable Real-Time Unit and Industrial Communication Subsystems (PRU-ICSS)rqjZjqjbjqjdjjf}rq(jh]ji]jj]jk]jn]ujpKjr]rqj{XRTwo Programmable Real-Time Unit and Industrial Communication Subsystems (PRU-ICSS)rqrq}rq(jYjqjZjqubaubaubj/)rq}rq(jYXFMulticore Shared Memory Controller (MSMC) with 1024KB of Shared L2 RAMjZjqjbjqjdj2jf}rq(jh]ji]jj]jk]jn]ujpNjqhjr]rqj)rq}rq(jYXFMulticore Shared Memory Controller (MSMC) with 1024KB of Shared L2 RAMrqjZjqjbjqjdjjf}rq(jh]ji]jj]jk]jn]ujpKjr]rqj{XFMulticore Shared Memory Controller (MSMC) with 1024KB of Shared L2 RAMrrrr}rr(jYjqjZjqubaubaubj/)rr}rr(jYXUUp to 36-Bit DDR3 External Memory Interface (EMIF) with ECC (32-Bit Data + 4-Bit ECC)jZjqjbjqjdj2jf}rr(jh]ji]jj]jk]jn]ujpNjqhjr]rrj)rr}rr(jYXUUp to 36-Bit DDR3 External Memory Interface (EMIF) with ECC (32-Bit Data + 4-Bit ECC)r rjZjrjbjqjdjjf}r r(jh]ji]jj]jk]jn]ujpKjr]r rj{XUUp to 36-Bit DDR3 External Memory Interface (EMIF) with ECC (32-Bit Data + 4-Bit ECC)r rr r}rr(jYj rjZjrubaubaubj/)rr}rr(jYX*PCI-Express® 2.0 Port with Integrated PHYrrjZjqjbjqjdj2jf}rr(jh]ji]jj]jk]jn]ujpNjqhjr]rrj)rr}rr(jYjrjZjrjbjqjdjjf}rr(jh]ji]jj]jk]jn]ujpKjr]rrj{X*PCI-Express® 2.0 Port with Integrated PHYrrrr}rr(jYjrjZjrubaubaubj/)rr}rr(jYX8Three Multichannel Audio Serial Port (McASP) PeripheralsrrjZjqjbjqjdj2jf}rr(jh]ji]jj]jk]jn]ujpNjqhjr]rrj)r r}r!r(jYjrjZjrjbjqjdjjf}r"r(jh]ji]jj]jk]jn]ujpKjr]r#rj{X8Three Multichannel Audio Serial Port (McASP) Peripheralsr$rr%r}r&r(jYjrjZj rubaubaubj/)r'r}r(r(jYX)Multichannel Buffered Serial Port (McBSP)r)rjZjqjbjqjdj2jf}r*r(jh]ji]jj]jk]jn]ujpNjqhjr]r+rj)r,r}r-r(jYj)rjZj'rjbjqjdjjf}r.r(jh]ji]jj]jk]jn]ujpKjr]r/rj{X)Multichannel Buffered Serial Port (McBSP)r0rr1r}r2r(jYj)rjZj,rubaubaubj/)r3r}r4r(jYX=Six Enhanced High Resolution Pulse Width Modulation (eHRPWM) jZjqjbjqjdj2jf}r5r(jh]ji]jj]jk]jn]ujpNjqhjr]r6rj)r7r}r8r(jYX<Six Enhanced High Resolution Pulse Width Modulation (eHRPWM)r9rjZj3rjbjqjdjjf}r:r(jh]ji]jj]jk]jn]ujpKjr]r;rj{X<Six Enhanced High Resolution Pulse Width Modulation (eHRPWM)rr(jYj9rjZj7rubaubaubeubj)r?r}r@r(jYX The key features of the EVM are:rArjZjqjbjqjdjjf}rBr(jh]ji]jj]jk]jn]ujpKjqhjr]rCrj{X The key features of the EVM are:rDrrEr}rFr(jYjArjZj?rubaubjC)rGr}rHr(jYUjZjqjbjqjdj`jf}rIr(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]rJr(j/)rKr}rLr(jYXfK2G SoC 66AK2G02 is based on keystone II architecture with ARM cortex A15 @600MHz and C66x DSP @600MHzjZjGrjbjqjdj2jf}rMr(jh]ji]jj]jk]jn]ujpNjqhjr]rNrj)rOr}rPr(jYXfK2G SoC 66AK2G02 is based on keystone II architecture with ARM cortex A15 @600MHz and C66x DSP @600MHzrQrjZjKrjbjqjdjjf}rRr(jh]ji]jj]jk]jn]ujpKjr]rSrj{XfK2G SoC 66AK2G02 is based on keystone II architecture with ARM cortex A15 @600MHz and C66x DSP @600MHzrTrrUr}rVr(jYjQrjZjOrubaubaubj/)rWr}rXr(jYX515MByte of DDR3LrYrjZjGrjbjqjdj2jf}rZr(jh]ji]jj]jk]jn]ujpNjqhjr]r[rj)r\r}r]r(jYjYrjZjWrjbjqjdjjf}r^r(jh]ji]jj]jk]jn]ujpK jr]r_rj{X515MByte of DDR3Lr`rrar}rbr(jYjYrjZj\rubaubaubj/)rcr}rdr(jYX512Mbit of QSPI FlashrerjZjGrjbjqjdj2jf}rfr(jh]ji]jj]jk]jn]ujpNjqhjr]rgrj)rhr}rir(jYjerjZjcrjbjqjdjjf}rjr(jh]ji]jj]jk]jn]ujpK!jr]rkrj{X512Mbit of QSPI Flashrlrrmr}rnr(jYjerjZjhrubaubaubj/)ror}rpr(jYX128kByte of I2C EEPROMrqrjZjGrjbjqjdj2jf}rrr(jh]ji]jj]jk]jn]ujpNjqhjr]rsrj)rtr}rur(jYjqrjZjorjbjqjdjjf}rvr(jh]ji]jj]jk]jn]ujpK"jr]rwrj{X128kByte of I2C EEPROMrxrryr}rzr(jYjqrjZjtrubaubaubj/)r{r}r|r(jYXMicro SD-Card slotr}rjZjGrjbjqjdj2jf}r~r(jh]ji]jj]jk]jn]ujpNjqhjr]rrj)rr}rr(jYj}rjZj{rjbjqjdjjf}rr(jh]ji]jj]jk]jn]ujpK#jr]rrj{XMicro SD-Card slotrrrr}rr(jYj}rjZjrubaubaubj/)rr}rr(jYXMGigabit Ethernet port supporting 10/100/1000 Mbps data rate on RJ45 connectorjZjGrjbjqjdj2jf}rr(jh]ji]jj]jk]jn]ujpNjqhjr]rrj)rr}rr(jYXMGigabit Ethernet port supporting 10/100/1000 Mbps data rate on RJ45 connectorrrjZjrjbjqjdjjf}rr(jh]ji]jj]jk]jn]ujpK$jr]rrj{XMGigabit Ethernet port supporting 10/100/1000 Mbps data rate on RJ45 connectorrrrr}rr(jYjrjZjrubaubaubj/)rr}rr(jYX(4x 10/100 Industrial Ethernet connectorsrrjZjGrjbjqjdj2jf}rr(jh]ji]jj]jk]jn]ujpNjqhjr]rrj)rr}rr(jYjrjZjrjbjqjdjjf}rr(jh]ji]jj]jk]jn]ujpK&jr]rrj{X(4x 10/100 Industrial Ethernet connectorsrrrr}rr(jYjrjZjrubaubaubj/)rr}rr(jYXPCIe x1 card edge connectorrrjZjGrjbjqjdj2jf}rr(jh]ji]jj]jk]jn]ujpNjqhjr]rrj)rr}rr(jYjrjZjrjbjqjdjjf}rr(jh]ji]jj]jk]jn]ujpK'jr]rrj{XPCIe x1 card edge connectorrrrr}rr(jYjrjZjrubaubaubj/)rr}rr(jYX LCD displayrrjZjGrjbjqjdj2jf}rr(jh]ji]jj]jk]jn]ujpNjqhjr]rrj)rr}rr(jYjrjZjrjbjqjdjjf}rr(jh]ji]jj]jk]jn]ujpK(jr]rrj{X LCD displayrrrr}rr(jYjrjZjrubaubaubj/)rr}rr(jYX(Expansion connector for customer designsrrjZjGrjbjqjdj2jf}rr(jh]ji]jj]jk]jn]ujpNjqhjr]rrj)rr}rr(jYjrjZjrjbjqjdjjf}rr(jh]ji]jj]jk]jn]ujpK)jr]rrj{X(Expansion connector for customer designsrrrr}rr(jYjrjZjrubaubaubj/)rr}rr(jYX0XDS100 Emulator and UART over mini-USB connectorrrjZjGrjbjqjdj2jf}rr(jh]ji]jj]jk]jn]ujpNjqhjr]rrj)rr}rr(jYjrjZjrjbjqjdjjf}rr(jh]ji]jj]jk]jn]ujpK*jr]rrj{X0XDS100 Emulator and UART over mini-USB connectorrrrr}rr(jYjrjZjrubaubaubj/)rr}rr(jYX<20-Pin JTAG header to support all types of external emulatorrrjZjGrjbjqjdj2jf}rr(jh]ji]jj]jk]jn]ujpNjqhjr]rrj)rr}rr(jYjrjZjrjbjqjdjjf}rr(jh]ji]jj]jk]jn]ujpK+jr]rrj{X<20-Pin JTAG header to support all types of external emulatorrrrr}rr(jYjrjZjrubaubaubj/)rr}rr(jYXRoHS compliant designrrjZjGrjbjqjdj2jf}rr(jh]ji]jj]jk]jn]ujpNjqhjr]rrj)rr}rr(jYjrjZjrjbjqjdjjf}rr(jh]ji]jj]jk]jn]ujpK,jr]rrj{XRoHS compliant designrrrr}rr(jYjrjZjrubaubaubj/)rr}rr(jYXCPowered by DC power-wall adaptor (24V/2.5A) or PCIE Edge Connector jZjGrjbjqjdj2jf}rr(jh]ji]jj]jk]jn]ujpNjqhjr]rrj)rr}rr(jYXBPowered by DC power-wall adaptor (24V/2.5A) or PCIE Edge ConnectorrrjZjrjbjqjdjjf}rr(jh]ji]jj]jk]jn]ujpK-jr]rrj{XBPowered by DC power-wall adaptor (24V/2.5A) or PCIE Edge Connectorrrrr}rr(jYjrjZjrubaubaubeubeubj[)rr}rr(jYUjKjZjqjbjqjdjejf}rr(jh]rrXevm layout and key componentsrraji]jj]jk]rrUid51rrajn]ujpK0jqhjr]rr(jt)rr}rr(jYXEVM Layout and Key ComponentsrrjZjrjbjqjdjxjf}rr(jh]ji]jj]jk]jn]ujpK0jqhjr]rrj{XEVM Layout and Key Componentsrsrs}rs(jYjrjZjrubaubjB)rs}rs(jYXF.. Image:: ../../../images/TI_K2G_ICE_EVM_TOP.png :scale: 50% jZjrjbjqjdjEjf}rs(UscaleK2UuriX+rtos/../../../images/TI_K2G_ICE_EVM_TOP.pngrsjk]jj]jh]ji]jH}rsU*jssjn]ujpNjqhjr]ubjB)rs}r s(jYXI.. Image:: ../../../images/TI_K2G_ICE_EVM_BOTTOM.png :scale: 50% jZjrjbjqjdjEjf}r s(UscaleK2UuriX.rtos/../../../images/TI_K2G_ICE_EVM_BOTTOM.pngr sjk]jj]jh]ji]jH}r sU*j ssjn]ujpNjqhjr]ubeubj[)r s}rs(jYUjKjZjqjbjqjdjejf}rs(jh]rsX'supported jtag debug probes (emulators)rsaji]jj]jk]rsUid52rsajn]ujpK9jqhjr]rs(jt)rs}rs(jYX'Supported JTAG Debug Probes (Emulators)rsjZj sjbjqjdjxjf}rs(jh]ji]jj]jk]jn]ujpK9jqhjr]rsj{X'Supported JTAG Debug Probes (Emulators)rsrs}rs(jYjsjZjsubaubjC)rs}rs(jYUjZj sjbjqjdj`jf}rs(jGX-jk]jj]jh]ji]jn]ujpKs(jYX3XDS560v2-class JTAG debug probes (high performance)r?sjZj9sjbjqjdjjf}r@s(jh]ji]jj]jk]jn]ujpK>jr]rAsj{X3XDS560v2-class JTAG debug probes (high performance)rBsrCs}rDs(jYj?sjZj=subaubaubeubeubj[)rEs}rFs(jYUjZjqjbjqjdjejf}rGs(jh]ji]jj]jk]rHsUid53rIsajn]rJsjQaujpKBjqhjr]rKs(jt)rLs}rMs(jYXMinimal EVM setuprNsjZjEsjbjqjdjxjf}rOs(jh]ji]jj]jk]jn]ujpKBjqhjr]rPsj{XMinimal EVM setuprQsrRs}rSs(jYjNsjZjLsubaubj[)rTs}rUs(jYUjZjEsjbjqjdjejf}rVs(jh]ji]jj]jk]rWsUid54rXsajn]rYsj(aujpKEjqhjr]rZs(jt)r[s}r\s(jYXSetting Boot Switchesr]sjZjTsjbjqjdjxjf}r^s(jh]ji]jj]jk]jn]ujpKEjqhjr]r_sj{XSetting Boot Switchesr`sras}rbs(jYj]sjZj[subaubj)rcs}rds(jYX9The DIP switch (SW3) is used for selecting the boot mode.resjZjTsjbjqjdjjf}rfs(jh]ji]jj]jk]jn]ujpKGjqhjr]rgsj{X9The DIP switch (SW3) is used for selecting the boot mode.rhsris}rjs(jYjesjZjcsubaubj)rks}rls(jYXX**For the EVM Out-of-Box experience, use SD/MMC boot mode as shown in the image below**:rmsjZjTsjbjqjdjjf}rns(jh]ji]jj]jk]jn]ujpKJjqhjr]ros(j)rps}rqs(jYXW**For the EVM Out-of-Box experience, use SD/MMC boot mode as shown in the image below**jf}rrs(jh]ji]jj]jk]jn]ujZjksjr]rssj{XSFor the EVM Out-of-Box experience, use SD/MMC boot mode as shown in the image belowrtsrus}rvs(jYUjZjpsubajdjubj{X:rws}rxs(jYX:jZjksubeubjB)rys}rzs(jYXD.. Image:: ../../../images/K2GICE_Boot_MODE.png :scale: 50% jZjTsjbjqjdjEjf}r{s(UscaleK2UuriX)rtos/../../../images/K2GICE_Boot_MODE.pngr|sjk]jj]jh]ji]jH}r}sU*j|ssjn]ujpNjqhjr]ubjZ)r~s}rs(jYUjZjTsjbjqjdj]jf}rs(jh]ji]jj]jk]jn]ujpKOjqhjr]rsj`)rs}rs(jYUjcKjZj~sjbjqjdjpjf}rs(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)rs}rs(jYXEThe table below lists all of the boot modes supported on the ICE EVM.rsjZjTsjbjqjdjjf}rs(jh]ji]jj]jk]jn]ujpKQjqhjr]rsj{XEThe table below lists all of the boot modes supported on the ICE EVM.rsrs}rs(jYjsjZjsubaubjB)rs}rs(jYXB.. Image:: ../../../images/K2G_ICE_BOOTSW.png :scale: 50% jZjTsjbjqjdjEjf}rs(UscaleK2UuriX'rtos/../../../images/K2G_ICE_BOOTSW.pngrsjk]jj]jh]ji]jH}rsU*jssjn]ujpNjqhjr]ubeubj[)rs}rs(jYUjZjEsjbjqjdjejf}rs(jh]ji]jj]jk]rsUconnecting-an-emulatorrsajn]rsh5aujpKWjqhjr]rs(jt)rs}rs(jYXConnecting an EmulatorrsjZjsjbjqjdjxjf}rs(jh]ji]jj]jk]jn]ujpKWjqhjr]rsj{XConnecting an Emulatorrsrs}rs(jYjsjZjsubaubj)rs}rs(jYXThis EVM setup is only required for developers who need to connect to cores using Code Composer Studio (CCS) to load their application.rsjZjsjbjqjdjjf}rs(jh]ji]jj]jk]jn]ujpNjqhjr]rsj)rs}rs(jYjsjZjsjbjqjdjjf}rs(jh]ji]jj]jk]jn]ujpKYjr]rsj{XThis EVM setup is only required for developers who need to connect to cores using Code Composer Studio (CCS) to load their application.rsrs}rs(jYjsjZjsubaubaubj)rs}rs(jYXcThe EVM supports two types of emulation via the on-board XDS100 emulator or the 20-pin JTAG header.rsjZjsjbjqjdjjf}rs(jh]ji]jj]jk]jn]ujpK\jqhjr]rsj{XcThe EVM supports two types of emulation via the on-board XDS100 emulator or the 20-pin JTAG header.rsrs}rs(jYjsjZjsubaubj)rs}rs(jYXmWhen an external emulator is not connected to the 20-pin JTAG Header, the on-board XDS100 embedded JTAG emulator is the default type of emulation (SoC JTAG signals are routed to the XDS100 on-board emulator). When an external emulator is connected to the 20-pin JTAG Header, it is automatically detected and the SoC JTAG signals are routed to the external emulator.rsjZjsjbjqjdjjf}rs(jh]ji]jj]jk]jn]ujpK^jqhjr]rsj{XmWhen an external emulator is not connected to the 20-pin JTAG Header, the on-board XDS100 embedded JTAG emulator is the default type of emulation (SoC JTAG signals are routed to the XDS100 on-board emulator). When an external emulator is connected to the 20-pin JTAG Header, it is automatically detected and the SoC JTAG signals are routed to the external emulator.rsrs}rs(jYjsjZjsubaubj)rs}rs(jYX**On-board XDS100 Emulator**rsjZjsjbjqjdjjf}rs(jh]ji]jj]jk]jn]ujpKdjqhjr]rsj)rs}rs(jYjsjf}rs(jh]ji]jj]jk]jn]ujZjsjr]rsj{XOn-board XDS100 Emulatorrsrs}rs(jYUjZjsubajdjubaubj)rs}rs(jYXThe K2G ICE EVM has on-board XDS100 embedded JTAG emulation circuitry so an external emulator is not required. Users can connect to the target SoC via CCS by connecting the USB cable, supplied in the ICE EVM kit, as shown in the image below.rsjZjsjbjqjdjjf}rs(jh]ji]jj]jk]jn]ujpKfjqhjr]rsj{XThe K2G ICE EVM has on-board XDS100 embedded JTAG emulation circuitry so an external emulator is not required. Users can connect to the target SoC via CCS by connecting the USB cable, supplied in the ICE EVM kit, as shown in the image below.rsrs}rs(jYjsjZjsubaubjZ)rs}rs(jYUjZjsjbjqjdj]jf}rs(jh]ji]jj]jk]jn]ujpKijqhjr]rsj`)rs}rs(jYUjcKjZjsjbjqjdjpjf}rs(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjB)rs}rs(jYXC.. Image:: ../../../images/ICE_K2G_connect.png :scale: 50% jZjsjbjqjdjEjf}rs(UscaleK2UuriX(rtos/../../../images/ICE_K2G_connect.pngrsjk]jj]jh]ji]jH}rsU*jssjn]ujpNjqhjr]ubjZ)rs}rs(jYUjZjsjbjqjdj]jf}rs(jh]ji]jj]jk]jn]ujpKnjqhjr]rsj`)rs}rs(jYUjcKjZjsjbjqjdjpjf}rs(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)rs}rs(jYX:**20-pin JTAG Header for Connecting an External Emulator**rsjZjsjbjqjdjjf}rs(jh]ji]jj]jk]jn]ujpKpjqhjr]rsj)rs}rs(jYjsjf}rs(jh]ji]jj]jk]jn]ujZjsjr]rsj{X620-pin JTAG Header for Connecting an External Emulatorrsrs}rs(jYUjZjsubajdjubaubj)rs}rs(jYXUsers have the option of connecting an external at the 20-pin JTAG Header connector (EMU1). The 20-pin JTAG Header is provided on-board for high speed real-time emulation. All JTAG and EMUxx signals are terminated on 20-pin JTAG Header.rsjZjsjbjqjdjjf}rs(jh]ji]jj]jk]jn]ujpKrjqhjr]rsj{XUsers have the option of connecting an external at the 20-pin JTAG Header connector (EMU1). The 20-pin JTAG Header is provided on-board for high speed real-time emulation. All JTAG and EMUxx signals are terminated on 20-pin JTAG Header.rsrs}rs(jYjsjZjsubaubeubj[)rs}rs(jYUjZjEsjbjqjdjejf}rs(jh]ji]jj]jk]rsUid55rsajn]rshPaujpKxjqhjr]rs(jt)rs}rt(jYXPowering Up the EVMrtjZjsjbjqjdjxjf}rt(jh]ji]jj]jk]jn]ujpKxjqhjr]rtj{XPowering Up the EVMrtrt}rt(jYjtjZjsubaubj)rt}rt(jYXPower Supply Specificationsr tjKjZjsjbjqjdjjf}r t(jk]r tUid56r tajj]jh]r tXpower-supply-specificationsrtaji]jn]ujpNjqhjr]rtj{XPower Supply Specificationsrtrt}rt(jYj tjZjtubaubj)rt}rt(jYXThe K2G ICE EVM can be powered from one of two sources. A single +24V / 2.5A DC (60W) external power supply connected to the DC power jack (J6). In addition, the K2G ICE EVM can be powered from the 12V supply pins on the PCIE edge connector. A power ANDing circuit is included in the design which will prevent damage if the +24V is connected while the board is installed on a PCIE backplane. The +24V supply will supply the power for the board in that condition.rtjZjsjbjqjdjjf}rt(jh]ji]jj]jk]jn]ujpK}jqhjr]rtj{XThe K2G ICE EVM can be powered from one of two sources. A single +24V / 2.5A DC (60W) external power supply connected to the DC power jack (J6). In addition, the K2G ICE EVM can be powered from the 12V supply pins on the PCIE edge connector. A power ANDing circuit is included in the design which will prevent damage if the +24V is connected while the board is installed on a PCIE backplane. The +24V supply will supply the power for the board in that condition.rtrt}rt(jYjtjZjtubaubeubeubj[)rt}rt(jYUjZjqjbjqjdjejf}rt(jh]ji]jj]jk]rtUid57rtajn]r thaujpKjqhjr]r!t(jt)r"t}r#t(jYX CCS Setupr$tjZjtjbjqjdjxjf}r%t(jh]ji]jj]jk]jn]ujpKjqhjr]r&tj{X CCS Setupr'tr(t}r)t(jYj$tjZj"tubaubj)r*t}r+t(jYXwThis section describes the setup to connect to 66AK2G02 ICE EVM using Code composer Studio environment and an emulator.r,tjZjtjbjqjdjjf}r-t(jh]ji]jj]jk]jn]ujpKjqhjr]r.tj{XwThis section describes the setup to connect to 66AK2G02 ICE EVM using Code composer Studio environment and an emulator.r/tr0t}r1t(jYj,tjZj*tubaubj)r2t}r3t(jYX6There are two scenarios while connecting to the EVM :r4tjZjtjbjqjdjjf}r5t(jh]ji]jj]jk]jn]ujpKjqhjr]r6tj{X6There are two scenarios while connecting to the EVM :r7tr8t}r9t(jYj4tjZj2tubaubjC)r:t}r;t(jYUjZjtjbjqjdj`jf}rt}r?t(jYX?**Connect to EVM without a SD card boot image to boot the EVM**r@tjZj:tjbjqjdj2jf}rAt(jh]ji]jj]jk]jn]ujpNjqhjr]rBtj)rCt}rDt(jYj@tjZj>tjbjqjdjjf}rEt(jh]ji]jj]jk]jn]ujpKjr]rFtj)rGt}rHt(jYj@tjf}rIt(jh]ji]jj]jk]jn]ujZjCtjr]rJtj{X;Connect to EVM without a SD card boot image to boot the EVMrKtrLt}rMt(jYUjZjGtubajdjubaubaubj/)rNt}rOt(jYX<**Connect to EVM after booting an image from the SD card**. jZj:tjbjqjdj2jf}rPt(jh]ji]jj]jk]jn]ujpNjqhjr]rQtj)rRt}rSt(jYX;**Connect to EVM after booting an image from the SD card**.jZjNtjbjqjdjjf}rTt(jh]ji]jj]jk]jn]ujpKjr]rUt(j)rVt}rWt(jYX:**Connect to EVM after booting an image from the SD card**jf}rXt(jh]ji]jj]jk]jn]ujZjRtjr]rYtj{X6Connect to EVM after booting an image from the SD cardrZtr[t}r\t(jYUjZjVtubajdjubj{X.r]t}r^t(jYX.jZjRtubeubaubeubj)r_t}r`t(jYXKeystone II device support package in CCSv7.1 includes the support for K2G ICE board but CCSv7.0/ CCSv6 users may need to update the device support package as described in the section "Update CCS to Install Keystone II Device Support Package."ratjZjtjbjqjdjjf}rbt(jh]ji]jj]jk]jn]ujpNjqhjr]rctj)rdt}ret(jYjatjZj_tjbjqjdjjf}rft(jh]ji]jj]jk]jn]ujpKjr]rgtj{XKeystone II device support package in CCSv7.1 includes the support for K2G ICE board but CCSv7.0/ CCSv6 users may need to update the device support package as described in the section "Update CCS to Install Keystone II Device Support Package."rhtrit}rjt(jYjatjZjdtubaubaubjZ)rkt}rlt(jYUjZjtjbjqjdj]jf}rmt(jh]ji]jj]jk]jn]ujpKjqhjr]rntj`)rot}rpt(jYUjcKjZjktjbjqjdjpjf}rqt(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj[)rrt}rst(jYUjZjtjbjqjdjejf}rtt(jh]ji]jj]jk]rutU8update-ccs-to-install-keystone-ii-device-support-packagervtajn]rwthaujpKjqhjr]rxt(jt)ryt}rzt(jYX8Update CCS to Install Keystone II Device Support Packager{tjZjrtjbjqjdjxjf}r|t(jh]ji]jj]jk]jn]ujpKjqhjr]r}tj{X8Update CCS to Install Keystone II Device Support Packager~trt}rt(jYj{tjZjytubaubj)rt}rt(jYXAll revisions of the board require this step to be performed in order to get the latest GEL files and the target content for the K2G if you are using CCSv7.0 and earlier. This step will not be required for CCS versions higher than version 7.1. CCSv7.0 or CCSv6.1.3 package contain KeystoneII device support package v1.1.6 which doesn't contain K2GICE specific target files hence we recommend this update.rtjZjrtjbjqjdjjf}rt(jh]ji]jj]jk]jn]ujpKjqhjr]rtj{XAll revisions of the board require this step to be performed in order to get the latest GEL files and the target content for the K2G if you are using CCSv7.0 and earlier. This step will not be required for CCS versions higher than version 7.1. CCSv7.0 or CCSv6.1.3 package contain KeystoneII device support package v1.1.6 which doesn't contain K2GICE specific target files hence we recommend this update.rtrt}rt(jYjtjZjtubaubj)rt}rt(jYX1. All CCS v6.1.3 or CCSv7.0 and earlier version users are required to update the Keystone Device Support package by going into the Help->Check For UpdatesrtjZjrtjbjqjdjjf}rt(jh]ji]jj]jk]jn]ujpKjqhjr]rtj{X1. All CCS v6.1.3 or CCSv7.0 and earlier version users are required to update the Keystone Device Support package by going into the Help->Check For Updatesrtrt}rt(jYjtjZjtubaubjB)rt}rt(jYXE.. Image:: ../../../images/Check_for_Updates.png :scale: 50% jZjrtjbjqjdjEjf}rt(UscaleK2UuriX*rtos/../../../images/Check_for_Updates.pngrtjk]jj]jh]ji]jH}rtU*jtsjn]ujpNjqhjr]ubj)rt}rt(jYX\2. Select Keystone2 device support package. Follow menu options to continue with the update.rtjZjrtjbjqjdjjf}rt(jh]ji]jj]jk]jn]ujpKjqhjr]rtj{X\2. Select Keystone2 device support package. Follow menu options to continue with the update.rtrt}rt(jYjtjZjtubaubj)rt}rt(jYX3. After the update is complete go to Help->Installation details and check that Keystone2 device support package v1.1.9 or later are installed as shown below.rtjZjrtjbjqjdjjf}rt(jh]ji]jj]jk]jn]ujpKjqhjr]rtj{X3. After the update is complete go to Help->Installation details and check that Keystone2 device support package v1.1.9 or later are installed as shown below.rtrt}rt(jYjtjZjtubaubjB)rt}rt(jYXU.. Image:: ../../../images/KeystoneII_device_support_package.png :scale: 50% jZjrtjbjqjdjEjf}rt(UscaleK2UuriX:rtos/../../../images/KeystoneII_device_support_package.pngrtjk]jj]jh]ji]jH}rtU*jtsjn]ujpNjqhjr]ubj)rt}rt(jYXiThe package can be downloaded separately from the link below and manually unzipped into CCS installation.rtjZjrtjbjqjdjjf}rt(jh]ji]jj]jk]jn]ujpNjqhjr]rtj)rt}rt(jYjtjZjtjbjqjdjjf}rt(jh]ji]jj]jk]jn]ujpKjr]rtj{XiThe package can be downloaded separately from the link below and manually unzipped into CCS installation.rtrt}rt(jYjtjZjtubaubaubjC)rt}rt(jYUjZjrtjbjqjdj`jf}rt(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]rtj/)rt}rt(jYXg`Device Support Files `__ jZjtjbjqjdj2jf}rt(jh]ji]jj]jk]jn]ujpNjqhjr]rtj)rt}rt(jYXe`Device Support Files `__rtjZjtjbjqjdjjf}rt(jh]ji]jj]jk]jn]ujpKjr]rtj)rt}rt(jYjtjf}rt(UnameXDevice Support FilesjXJhttps://software-dl.ti.com/ccs/esd/documents/ccs_device_support_files.htmljk]jj]jh]ji]jn]ujZjtjr]rtj{XDevice Support Filesrtrt}rt(jYUjZjtubajdjubaubaubaubj)rt}rt(jYXFor K2G Devices, if using CCS v6.1.2 and Keystone2 device support v1.1.7, 66AK2G02 would not show up in the list of devices when creating the target configuration. This is due to an incompatibility in the XML parser in CCS v6.1.2 with the K2G device xml. In order to work-around this issue, make the change in 66AK2G02.xml as illustrated below in order to have 66AK2G02 display in the device list. This problem does not exist in CCS v6.1.3 onwards as the XML parser has been updated.rtjZjrtjbjqjdjjf}rt(jh]ji]jj]jk]jn]ujpNjqhjr]rtj)rt}rt(jYjtjZjtjbjqjdjjf}rt(jh]ji]jj]jk]jn]ujpKjr]rtj{XFor K2G Devices, if using CCS v6.1.2 and Keystone2 device support v1.1.7, 66AK2G02 would not show up in the list of devices when creating the target configuration. This is due to an incompatibility in the XML parser in CCS v6.1.2 with the K2G device xml. In order to work-around this issue, make the change in 66AK2G02.xml as illustrated below in order to have 66AK2G02 display in the device list. This problem does not exist in CCS v6.1.3 onwards as the XML parser has been updated.rtrt}rt(jYjtjZjtubaubaubj)rt}rt(jYXAC:\\ti\\ccsv6\\ccs\_base\\common\\targetdb\\devices\\66AK2G02.xmlrtjZjrtjbjqjdjjf}rt(jh]ji]jj]jk]jn]ujpKjqhjr]rtj{X9C:\ti\ccsv6\ccs_base\common\targetdb\devices\66AK2G02.xmlrtrt}rt(jYXAC:\\ti\\ccsv6\\ccs\_base\\common\\targetdb\\devices\\66AK2G02.xmljZjtubaubj)rt}rt(jYXLine #1rtjZjrtjbjqjdjjf}rt(jh]ji]jj]jk]jn]ujpKjqhjr]rtj{XLine #1rtrt}rt(jYjtjZjtubaubj)rt}rt(jYX6jZjrtjbjqjdjjf}rt(jjjk]jj]jh]ji]jn]ujpM jqhjr]rtj{X6rtrt}rt(jYUjZjtubaubj)rt}rt(jYXtortjZjrtjbjqjdjjf}rt(jh]ji]jj]jk]jn]ujpKjqhjr]rtj{Xtortrt}rt(jYjtjZjtubaubj)rt}rt(jYX6jZjrtjbjqjdjjf}rt(jjjk]jj]jh]ji]jn]ujpM jqhjr]rtj{X6rtrt}rt(jYUjZjtubaubeubj[)rt}rt(jYUjZjtjbjqjdjejf}rt(jh]ji]jj]jk]ruU%connect-without-an-sd-card-boot-imageruajn]ruhaujpKjqhjr]ru(jt)ru}ru(jYX%Connect without an SD Card Boot ImagerujZjtjbjqjdjxjf}ru(jh]ji]jj]jk]jn]ujpKjqhjr]ruj{X%Connect without an SD Card Boot Imager ur u}r u(jYjujZjuubaubj)r u}r u(jYX&Configuring target configuration filesrujKjZjtjbjqjdjjf}ru(jk]ruUid58ruajj]jh]ruX&configuring-target-configuration-filesruaji]jn]ujpNjqhjr]ruj{X&Configuring target configuration filesruru}ru(jYjujZj uubaubj)ru}ru(jYXuLaunch CCS and create a new target configuration (File->New->Target Configuration file) as shown in the images below.rujZjtjbjqjdjjf}ru(jh]ji]jj]jk]jn]ujpKjqhjr]ruj{XuLaunch CCS and create a new target configuration (File->New->Target Configuration file) as shown in the images below.ruru}ru(jYjujZjuubaubjB)r u}r!u(jYXL.. Image:: ../../../images/CCS_target_configuration.png :scale: 50% jZjtjbjqjdjEjf}r"u(UscaleK2UuriX1rtos/../../../images/CCS_target_configuration.pngr#ujk]jj]jh]ji]jH}r$uU*j#usjn]ujpNjqhjr]ubj)r%u}r&u(jYXtProvide an appropriate name to the configuration. Select Spectrum Digital XDS100 emulator and target as K2G ICE EVM.r'ujZjtjbjqjdjjf}r(u(jh]ji]jj]jk]jn]ujpKjqhjr]r)uj{XtProvide an appropriate name to the configuration. Select Spectrum Digital XDS100 emulator and target as K2G ICE EVM.r*ur+u}r,u(jYj'ujZj%uubaubj)r-u}r.u(jYXIf you don't find the K2GICE target make sure you have installed CCSv7.1 or higher. If using CCSv 7.0 or CCSv6.1.x and earlier, ensure that you have done the software update correctly as shown in the how to section below.r/ujZjtjbjqjdjjf}r0u(jh]ji]jj]jk]jn]ujpNjqhjr]r1uj)r2u}r3u(jYj/ujZj-ujbjqjdjjf}r4u(jh]ji]jj]jk]jn]ujpKjr]r5uj{XIf you don't find the K2GICE target make sure you have installed CCSv7.1 or higher. If using CCSv 7.0 or CCSv6.1.x and earlier, ensure that you have done the software update correctly as shown in the how to section below.r6ur7u}r8u(jYj/ujZj2uubaubaubjB)r9u}r:u(jYXP.. Image:: ../../../images/K2G_ICE_target_configuration.png :scale: 50% jZjtjbjqjdjEjf}r;u(UscaleK2UuriX5rtos/../../../images/K2G_ICE_target_configuration.pngru}r?u(jYXIn advanced settings, make sure that the GEL files are populated correctly. The following GEL files and their corresponding cores are provided below.r@ujZjtjbjqjdjjf}rAu(jh]ji]jj]jk]jn]ujpKjqhjr]rBuj{XIn advanced settings, make sure that the GEL files are populated correctly. The following GEL files and their corresponding cores are provided below.rCurDu}rEu(jYj@ujZj>uubaubjC)rFu}rGu(jYUjZjtjbjqjdj`jf}rHu(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]rIu(j/)rJu}rKu(jYXC66X Core: icek2g.gelrLujZjFujbjqjdj2jf}rMu(jh]ji]jj]jk]jn]ujpNjqhjr]rNuj)rOu}rPu(jYjLujZjJujbjqjdjjf}rQu(jh]ji]jj]jk]jn]ujpKjr]rRuj{XC66X Core: icek2g.gelrSurTu}rUu(jYjLujZjOuubaubaubj/)rVu}rWu(jYXA15 Core: icek2g\_arm.gel jZjFujbjqjdj2jf}rXu(jh]ji]jj]jk]jn]ujpNjqhjr]rYuj)rZu}r[u(jYXA15 Core: icek2g\_arm.geljZjVujbjqjdjjf}r\u(jh]ji]jj]jk]jn]ujpKjr]r]uj{XA15 Core: icek2g_arm.gelr^ur_u}r`u(jYXA15 Core: icek2g\_arm.geljZjZuubaubaubeubj)rau}rbu(jYXConnecting to targetrcujKjZjtjbjqjdjjf}rdu(jk]reuUid59rfuajj]jh]rguXconnecting-to-targetrhuaji]jn]ujpNjqhjr]riuj{XConnecting to targetrjurku}rlu(jYjcujZjauubaubj)rmu}rnu(jYX1. Download Code composer Studio or for CCSv7.0 and earlier, ensure it contains Keystone device support package version 1.1.9 as described in the how to guide "Update CCS to Install Keystone II Device Support Package."roujZjtjbjqjdjjf}rpu(jh]ji]jj]jk]jn]ujpKjqhjr]rquj{X1. Download Code composer Studio or for CCSv7.0 and earlier, ensure it contains Keystone device support package version 1.1.9 as described in the how to guide "Update CCS to Install Keystone II Device Support Package."rrursu}rtu(jYjoujZjmuubaubj)ruu}rvu(jYX2. 66AK2G02 ICE EVM contains boot switches to configure for "No boot/sleep" mode. So configure the boot switches to "No Boot Mode" as described in the "Setting Boot Switches" section.rwujZjtjbjqjdjjf}rxu(jh]ji]jj]jk]jn]ujpKjqhjr]ryuj{X2. 66AK2G02 ICE EVM contains boot switches to configure for "No boot/sleep" mode. So configure the boot switches to "No Boot Mode" as described in the "Setting Boot Switches" section.rzur{u}r|u(jYjwujZjuuubaubj)r}u}r~u(jYXo3. Connect an XDS100 Emulator to the XDS USB port of the ICE EVM as shown in the section "Connecting Emulator."rujZjtjbjqjdjjf}ru(jh]ji]jj]jk]jn]ujpKjqhjr]ruj{Xo3. Connect an XDS100 Emulator to the XDS USB port of the ICE EVM as shown in the section "Connecting Emulator."ruru}ru(jYjujZj}uubaubj)ru}ru(jYX4. Launch CCS and create a new target configuration as discussed in the previous section "Configuring target configuration files."rujZjtjbjqjdjjf}ru(jh]ji]jj]jk]jn]ujpKjqhjr]ruj{X4. Launch CCS and create a new target configuration as discussed in the previous section "Configuring target configuration files."ruru}ru(jYjujZjuubaubj)ru}ru(jYX15. Launch the newly created target configuration.rujZjtjbjqjdjjf}ru(jh]ji]jj]jk]jn]ujpKjqhjr]ruj{X15. Launch the newly created target configuration.ruru}ru(jYjujZjuubaubjB)ru}ru(jYXK.. Image:: ../../../images/K2G_Launch_targetConfig.png :scale: 50% jZjtjbjqjdjEjf}ru(UscaleK2UuriX0rtos/../../../images/K2G_Launch_targetConfig.pngrujk]jj]jh]ji]jH}ruU*jusjn]ujpNjqhjr]ubj)ru}ru(jYXV6. K2G can be a DSP or an ARM master boot device so connect to the C66x or the A15\_0.jZjtjbjqjdjjf}ru(jh]ji]jj]jk]jn]ujpKjqhjr]ruj{XU6. K2G can be a DSP or an ARM master boot device so connect to the C66x or the A15_0.ruru}ru(jYXV6. K2G can be a DSP or an ARM master boot device so connect to the C66x or the A15\_0.jZjuubaubj)ru}ru(jYX **GEL Log**rujZjtjbjqjdjjf}ru(jh]ji]jj]jk]jn]ujpKjqhjr]ruj)ru}ru(jYjujf}ru(jh]ji]jj]jk]jn]ujZjujr]ruj{XGEL Logruru}ru(jYUjZjuubajdjubaubj)ru}ru(jYXA15_0: GEL Output: PLL has been configured (24.0 MHz * 100 / 1 / 4 = 600.0 MHz) A15_0: GEL Output: ARM PLL has been configured with ref clock 24MHz, -sysclkp_period 41.6666 (24.0 MHz * 100 / 1 / 4 = 600.0 MHz) A15_0: GEL Output: Power on all PSC modules and DSP domains... A15_0: GEL Output: Power on PCIE PSC modules and DSP domains... Done. A15_0: GEL Output: UART PLL has been configured (24.0 MHz * 128 / 1 / 8 = 384.0 MHz) A15_0: GEL Output: NSS PLL has been configured (24.0 MHz * 250 / 3 / 2 = 1000.0 MHz) A15_0: GEL Output: ICSS PLL has been configured (24.0 MHz * 250 / 3 / 10 = 200.0 MHz) A15_0: GEL Output: DSS PLL has been configured (24.0 MHz * 198 / 12 / 16 = 24.75 MHz) A15_0: GEL Output: DDR PLL has been configured (24.0 MHz * 250 / 3 / 10 = 200.0 MHz) A15_0: GEL Output: XMC setup complete. A15_0: GEL Output: DDR3 PLL Setup ... A15_0: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 400MHz. A15_0: GEL Output: DDR3A initialization completejZjtjbjqjdjjf}ru(jjjk]jj]jh]ji]jn]ujpM jqhjr]ruj{XA15_0: GEL Output: PLL has been configured (24.0 MHz * 100 / 1 / 4 = 600.0 MHz) A15_0: GEL Output: ARM PLL has been configured with ref clock 24MHz, -sysclkp_period 41.6666 (24.0 MHz * 100 / 1 / 4 = 600.0 MHz) A15_0: GEL Output: Power on all PSC modules and DSP domains... A15_0: GEL Output: Power on PCIE PSC modules and DSP domains... Done. A15_0: GEL Output: UART PLL has been configured (24.0 MHz * 128 / 1 / 8 = 384.0 MHz) A15_0: GEL Output: NSS PLL has been configured (24.0 MHz * 250 / 3 / 2 = 1000.0 MHz) A15_0: GEL Output: ICSS PLL has been configured (24.0 MHz * 250 / 3 / 10 = 200.0 MHz) A15_0: GEL Output: DSS PLL has been configured (24.0 MHz * 198 / 12 / 16 = 24.75 MHz) A15_0: GEL Output: DDR PLL has been configured (24.0 MHz * 250 / 3 / 10 = 200.0 MHz) A15_0: GEL Output: XMC setup complete. A15_0: GEL Output: DDR3 PLL Setup ... A15_0: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 400MHz. A15_0: GEL Output: DDR3A initialization completeruru}ru(jYUjZjuubaubeubj[)ru}ru(jYUjZjtjbjqjdjejf}ru(jh]ji]jj]jk]ruU"connect-with-an-sd-card-boot-imageruajn]ruhUaujpMjqhjr]ru(jt)ru}ru(jYX"Connect with an SD Card Boot ImagerujZjujbjqjdjxjf}ru(jh]ji]jj]jk]jn]ujpMjqhjr]ruj{X"Connect with an SD Card Boot Imageruru}ru(jYjujZjuubaubj)ru}ru(jYXy1. Launch CCS and create a new target configuration (File->New->Target Configuration file) as shown in the images below.rujZjujbjqjdjjf}ru(jh]ji]jj]jk]jn]ujpMjqhjr]ruj{Xy1. Launch CCS and create a new target configuration (File->New->Target Configuration file) as shown in the images below.ruru}ru(jYjujZjuubaubjB)ru}ru(jYXL.. Image:: ../../../images/CCS_target_configuration.png :scale: 50% jZjujbjqjdjEjf}ru(UscaleK2UuriX1rtos/../../../images/CCS_target_configuration.pngrujk]jj]jh]ji]jH}ruU*jusjn]ujpNjqhjr]ubj)ru}ru(jYXqProvide an appropriate name to the configuration. Select Spectrum digital XDS100 emulator and target as 66AK2G02.rujZjujbjqjdjjf}ru(jh]ji]jj]jk]jn]ujpMjqhjr]ruj{XqProvide an appropriate name to the configuration. Select Spectrum digital XDS100 emulator and target as 66AK2G02.ruru}ru(jYjujZjuubaubj)ru}ru(jYXIf you don't find the K2GICE target make sure you have installed CCSv7.1 or higher. If using CCSv 7.0 or CCSv6.1.x and earlier, ensure that you have done the software update correctly as shown in the how to section below.rujZjujbjqjdjjf}ru(jh]ji]jj]jk]jn]ujpNjqhjr]ruj)ru}ru(jYjujZjujbjqjdjjf}ru(jh]ji]jj]jk]jn]ujpMjr]ruj{XIf you don't find the K2GICE target make sure you have installed CCSv7.1 or higher. If using CCSv 7.0 or CCSv6.1.x and earlier, ensure that you have done the software update correctly as shown in the how to section below.ruru}ru(jYjujZjuubaubaubjB)ru}ru(jYX\.. Image:: ../../../images/K2G_GPEVM_Target_configuration_alternate.jpg :scale: 50% jZjujbjqjdjEjf}ru(UscaleK2UuriXArtos/../../../images/K2G_GPEVM_Target_configuration_alternate.jpgrujk]jj]jh]ji]jH}ruU*jusjn]ujpNjqhjr]ubj)ru}ru(jYX@In advanced settings, make sure that no GEL files are populated.rujZjujbjqjdjjf}ru(jh]ji]jj]jk]jn]ujpMjqhjr]ruj{X@In advanced settings, make sure that no GEL files are populated.ruru}ru(jYjujZjuubaubj)ru}ru(jYX2. 66AK2G02 GP EVM contains boot switches to configure for "SD/MMC boot" mode. So configure the boot switches to "SD/MMC Boot" as described in the section "Setting Boot Switches."rujZjujbjqjdjjf}ru(jh]ji]jj]jk]jn]ujpMjqhjr]ruj{X2. 66AK2G02 GP EVM contains boot switches to configure for "SD/MMC boot" mode. So configure the boot switches to "SD/MMC Boot" as described in the section "Setting Boot Switches."ruru}ru(jYjujZjuubaubj)ru}ru(jYXn3. Connect an XDS100 Emulator to the XDS USB port of the GP EVM as shown in the section "Connecting Emulator."rujZjujbjqjdjjf}ru(jh]ji]jj]jk]jn]ujpMjqhjr]ruj{Xn3. Connect an XDS100 Emulator to the XDS USB port of the GP EVM as shown in the section "Connecting Emulator."ruru}rv(jYjujZjuubaubj)rv}rv(jYX4. Launch CCS and create a new target configuration as discussed in the previous section "Configuring target configuration files".rvjZjujbjqjdjjf}rv(jh]ji]jj]jk]jn]ujpMjqhjr]rvj{X4. Launch CCS and create a new target configuration as discussed in the previous section "Configuring target configuration files".rvrv}rv(jYjvjZjvubaubj)r v}r v(jYX15. Launch the newly created target configuration.r vjZjujbjqjdjjf}r v(jh]ji]jj]jk]jn]ujpM jqhjr]r vj{X15. Launch the newly created target configuration.rvrv}rv(jYj vjZj vubaubjB)rv}rv(jYXK.. Image:: ../../../images/K2G_Launch_targetConfig.png :scale: 50% jZjujbjqjdjEjf}rv(UscaleK2UuriX0rtos/../../../images/K2G_Launch_targetConfig.pngrvjk]jj]jh]ji]jH}rvU*jvsjn]ujpNjqhjr]ubj)rv}rv(jYX6. K2G will boot with ARM master boot from the SD card so connect to the A15\_0. There will be no output on the console when you connect to the core.jZjujbjqjdjjf}rv(jh]ji]jj]jk]jn]ujpM&jqhjr]rvj{X6. K2G will boot with ARM master boot from the SD card so connect to the A15_0. There will be no output on the console when you connect to the core.rvrv}rv(jYX6. K2G will boot with ARM master boot from the SD card so connect to the A15\_0. There will be no output on the console when you connect to the core.jZjvubaubj)rv}rv(jYX7. SD card boot image will typically load a secondary bootloader like u-boot that will put the DSP in reset so users will need to follow the instructions in the guide `How to take the C66x DSP out of reset with Linux running on A15 `__jZjujbjqjdjjf}rv(jh]ji]jj]jk]jn]ujpM)jqhjr]r v(j{X7. SD card boot image will typically load a secondary bootloader like u-boot that will put the DSP in reset so users will need to follow the instructions in the guide r!vr"v}r#v(jYX7. SD card boot image will typically load a secondary bootloader like u-boot that will put the DSP in reset so users will need to follow the instructions in the guide jZjvubj)r$v}r%v(jYX`How to take the C66x DSP out of reset with Linux running on A15 `__jf}r&v(UnameX?How to take the C66x DSP out of reset with Linux running on A15jXhttp://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/How_to_Guides.html#taking-the-c66x-out-of-reset-with-linux-running-on-the-arm-a15jk]jj]jh]ji]jn]ujZjvjr]r'vj{X?How to take the C66x DSP out of reset with Linux running on A15r(vr)v}r*v(jYUjZj$vubajdjubeubj)r+v}r,v(jYXRTOS users do not need to follow this step as the Secondary Bootloader (SBL) will put the DSP in idle state and not in reset if there is no code running on the DSP.r-vjZjujbjqjdjjf}r.v(jh]ji]jj]jk]jn]ujpNjqhjr]r/vj)r0v}r1v(jYj-vjZj+vjbjqjdjjf}r2v(jh]ji]jj]jk]jn]ujpM,jr]r3vj{XRTOS users do not need to follow this step as the Secondary Bootloader (SBL) will put the DSP in idle state and not in reset if there is no code running on the DSP.r4vr5v}r6v(jYj-vjZj0vubaubaubeubeubj[)r7v}r8v(jYUjZjqjbjqjdjejf}r9v(jh]ji]jj]jk]r:vUid60r;vajn]rv}r?v(jYXUseful Resources and Supportr@vjZj7vjbjqjdjxjf}rAv(jh]ji]jj]jk]jn]ujpM/jqhjr]rBvj{XUseful Resources and SupportrCvrDv}rEv(jYj@vjZj>vubaubjC)rFv}rGv(jYUjZj7vjbjqjdj`jf}rHv(jGX-jk]jj]jh]ji]jn]ujpM0jqhjr]rIv(j/)rJv}rKv(jYXM`66AK2Gx ICE EVM User Guide `__rLvjZjFvjbjqjdj2jf}rMv(jh]ji]jj]jk]jn]ujpNjqhjr]rNvj)rOv}rPv(jYjLvjZjJvjbjqjdjjf}rQv(jh]ji]jj]jk]jn]ujpM0jr]rRvj)rSv}rTv(jYjLvjf}rUv(UnameX66AK2Gx ICE EVM User GuidejX,http://www.ti.com/lit/ug/spruie3/spruie3.pdfjk]jj]jh]ji]jn]ujZjOvjr]rVvj{X66AK2Gx ICE EVM User GuiderWvrXv}rYv(jYUjZjSvubajdjubaubaubj/)rZv}r[v(jYX?`66AK2Gx Product folder `__r\vjZjFvjbjqjdj2jf}r]v(jh]ji]jj]jk]jn]ujpNjqhjr]r^vj)r_v}r`v(jYj\vjZjZvjbjqjdjjf}rav(jh]ji]jj]jk]jn]ujpM1jr]rbvj)rcv}rdv(jYj\vjf}rev(UnameX66AK2Gx Product folderjX"http://www.ti.com/product/66AK2G12jk]jj]jh]ji]jn]ujZj_vjr]rfvj{X66AK2Gx Product folderrgvrhv}riv(jYUjZjcvubajdjubaubaubj/)rjv}rkv(jYX\`66AK2Gx GP EVM Technical Reference Manual `__jZjFvjbjqjdj2jf}rlv(jh]ji]jj]jk]jn]ujpNjqhjr]rmvj)rnv}rov(jYX\`66AK2Gx GP EVM Technical Reference Manual `__rpvjZjjvjbjqjdjjf}rqv(jh]ji]jj]jk]jn]ujpM2jr]rrvj)rsv}rtv(jYjpvjf}ruv(UnameX)66AK2Gx GP EVM Technical Reference ManualjX,http://www.ti.com/lit/ug/sprui65/sprui65.pdfjk]jj]jh]ji]jn]ujZjnvjr]rvvj{X)66AK2Gx GP EVM Technical Reference Manualrwvrxv}ryv(jYUjZjsvubajdjubaubaubj/)rzv}r{v(jYXB`66AK2Gx ICE EVM Product folder `__r|vjZjFvjbjqjdj2jf}r}v(jh]ji]jj]jk]jn]ujpNjqhjr]r~vj)rv}rv(jYj|vjZjzvjbjqjdjjf}rv(jh]ji]jj]jk]jn]ujpM4jr]rvj)rv}rv(jYj|vjf}rv(UnameX66AK2Gx ICE EVM Product folderjXhttp://www.ti.com/tool/k2gicejk]jj]jh]ji]jn]ujZjvjr]rvj{X66AK2Gx ICE EVM Product folderrvrv}rv(jYUjZjvubajdjubaubaubj/)rv}rv(jYX\`Keystone E2E Support Forum `__ jZjFvjbX_internal padding after source/common/EVM_Hardware_Setup/66AK2G02_ICE_EVM_Hardware_setup.rst.incrvjdj2jf}rv(jh]ji]jj]jk]jn]ujpNjqhjr]rvj)rv}rv(jYX[`Keystone E2E Support Forum `__rvjZjvjbjqjdjjf}rv(jh]ji]jj]jk]jn]ujpM5jr]rvj)rv}rv(jYjvjf}rv(UnameXKeystone E2E Support ForumjX:https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639jk]jj]jh]ji]jn]ujZjvjr]rvj{XKeystone E2E Support Forumrvrv}rv(jYUjZjvubajdjubaubaubeubj)rv}rv(jYXEVMK2E Hardware SetupjZj7vjbjcjdjjf}rv(jjjk]jj]jh]ji]jn]ujpKxjqhjr]rvj{XEVMK2E Hardware Setuprvrv}rv(jYUjZjvubaubj)rv}rv(jYX4====================================================jZj7vjbjcjdjjf}rv(jjjk]jj]jh]ji]jn]ujpKyjqhjr]rvj{X4====================================================rvrv}rv(jYUjZjvubaubeubeubj[)rv}rv(jYUjZjR\jbjX>source/common/EVM_Hardware_Setup/EVMK2E_Hardware_Setup.rst.incrvrv}rvbjdjejf}rv(jh]ji]jj]jk]rvUevmk2e-hardware-setup-guidervajn]rvhaujpKjqhjr]rv(jt)rv}rv(jYXEVMK2E Hardware Setup GuidervjZjvjbjvjdjxjf}rv(jh]ji]jj]jk]jn]ujpKjqhjr]rvj{XEVMK2E Hardware Setup Guidervrv}rv(jYjvjZjvubaubj[)rv}rv(jYUjKjZjvjbjvjdjejf}rv(jh]rvXhardware setuprvaji]jj]jk]rvUhardware-setuprvajn]ujpKjqhjr]rv(jt)rv}rv(jYXHardware SetuprvjZjvjbjvjdjxjf}rv(jh]ji]jj]jk]jn]ujpKjqhjr]rvj{XHardware Setuprvrv}rv(jYjvjZjvubaubj)rv}rv(jYXThe EVM board is sensitive to electrostatic discharges (ESD). Use a grounding strap or other device to prevent damaging the board. Be sure to connect communication cables before applying power to any equipment.rvjZjvjbjvjdjjf}rv(jh]ji]jj]jk]jn]ujpNjqhjr]rvj)rv}rv(jYjvjZjvjbjvjdjjf}rv(jh]ji]jj]jk]jn]ujpKjr]rvj{XThe EVM board is sensitive to electrostatic discharges (ESD). Use a grounding strap or other device to prevent damaging the board. Be sure to connect communication cables before applying power to any equipment.rvrv}rv(jYjvjZjvubaubaubj[)rv}rv(jYUjKjZjvjbjvjdjejf}rv(jh]rvXattach the ethernet cablervaji]jj]jk]rvUattach-the-ethernet-cablervajn]ujpK jqhjr]rv(jt)rv}rv(jYXAttach the Ethernet cablervjZjvjbjvjdjxjf}rv(jh]ji]jj]jk]jn]ujpK jqhjr]rvj{XAttach the Ethernet cablervrv}rv(jYjvjZjvubaubj)rv}rv(jYXUsing the Ethernet cable supplied, connect one end of the cable to the Ethernet Port 0 (At bottom one) on the EVM and the other end to your PC. The below picture shows which Ethernet Port is port 0:rvjZjvjbjvjdjjf}rv(jh]ji]jj]jk]jn]ujpK jqhjr]rvj{XUsing the Ethernet cable supplied, connect one end of the cable to the Ethernet Port 0 (At bottom one) on the EVM and the other end to your PC. The below picture shows which Ethernet Port is port 0:rvrv}rv(jYjvjZjvubaubjB)rv}rv(jYX/.. image:: ../../../images/Evmk2e-image001.jpg jZjvjbjvjdjEjf}rv(UuriX(rtos/../../../images/Evmk2e-image001.jpgrvjk]jj]jh]ji]jH}rvU*jvsjn]ujpKjqhjr]ubeubj[)rv}rv(jYUjKjZjvjbjvjdjejf}rv(jh]rvXconnect the jtag interfacervaji]jj]jk]rvUconnect-the-jtag-interfacervajn]ujpKjqhjr]rv(jt)rv}rv(jYXConnect the JTAG interfacervjZjvjbjvjdjxjf}rv(jh]ji]jj]jk]jn]ujpKjqhjr]rwj{XConnect the JTAG interfacerwrw}rw(jYjvjZjvubaubj)rw}rw(jYXNUse the USB to USB mini-B cable provided. Connect the USB mini-B connector to the USB mini-B interface near to the RST\_PWR1 (Red color) button on the EVM, and the USB connector to your PC. This enables XDS-2xx emulation and is directly useable by CCS. If you are using a different JTAG, you can connect it at MIPI60 connector (EMU1).jZjvjbjvjdjjf}rw(jh]ji]jj]jk]jn]ujpKjqhjr]rwj{XMUse the USB to USB mini-B cable provided. Connect the USB mini-B connector to the USB mini-B interface near to the RST_PWR1 (Red color) button on the EVM, and the USB connector to your PC. This enables XDS-2xx emulation and is directly useable by CCS. If you are using a different JTAG, you can connect it at MIPI60 connector (EMU1).rwr w}r w(jYXNUse the USB to USB mini-B cable provided. Connect the USB mini-B connector to the USB mini-B interface near to the RST\_PWR1 (Red color) button on the EVM, and the USB connector to your PC. This enables XDS-2xx emulation and is directly useable by CCS. If you are using a different JTAG, you can connect it at MIPI60 connector (EMU1).jZjwubaubeubj[)r w}r w(jYUjZjvjbjvjdjejf}r w(jh]ji]jj]jk]rwU k2e-set-the-boot-mode-switch-sw1rwajn]rwjOaujpKjqhjr]rw(jt)rw}rw(jYX K2E Set the boot mode switch SW1rwjZj wjbjvjdjxjf}rw(jh]ji]jj]jk]jn]ujpKjqhjr]rwj{X K2E Set the boot mode switch SW1rwrw}rw(jYjwjZjwubaubj)rw}rw(jYX9K2E SPI Little Endian Boot mode (Default factory setting)rwjZj wjbjvjdjjf}rw(jk]rwUk2e-spi-le-boot-moderwajj]jh]ji]jn]r wj@aujpNjqhjr]r!wj{X9K2E SPI Little Endian Boot mode (Default factory setting)r"wr#w}r$w(jYjwjZjwubaubj)r%w}r&w(jYX@MSB LSB SW1 - 1(OFF) 2(OFF) 3(ON) 4(OFF)jZj wjbjvjdjjf}r'w(jjjk]jj]jh]ji]jn]ujpMc!jqhjr]r(wj{X@MSB LSB SW1 - 1(OFF) 2(OFF) 3(ON) 4(OFF)r)wr*w}r+w(jYUjZj%wubaubjB)r,w}r-w(jYX/.. image:: ../../../images/Evmk2e-image002.jpg jZj wjbjvjdjEjf}r.w(UuriX(rtos/../../../images/Evmk2e-image002.jpgr/wjk]jj]jh]ji]jH}r0wU*j/wsjn]ujpK)jqhjr]ubj)r1w}r2w(jYXCHere a switch on “ON” position should be considered as “1”.r3wjZj wjbjvjdjjf}r4w(jh]ji]jj]jk]jn]ujpNjqhjr]r5wj)r6w}r7w(jYj3wjZj1wjbjvjdjjf}r8w(jh]ji]jj]jk]jn]ujpK*jr]r9wj{XCHere a switch on “ON” position should be considered as “1”.r:wr;w}rw(jYX,K2E No Boot/JTAG DSP Little Endian Boot moder?wjZj wjbjvjdjjf}r@w(jk]rAwUk2e-set-no-boot-moderBwajj]jh]ji]jn]rCwhaujpNjqhjr]rDwj{X,K2E No Boot/JTAG DSP Little Endian Boot moderEwrFw}rGw(jYj?wjZj=wubaubj)rHw}rIw(jYX:MSB LSB SW1 - 1(ON) 2(ON) 3(ON) 4(ON)jZj wjbjvjdjjf}rJw(jjjk]jj]jh]ji]jn]ujpMp!jqhjr]rKwj{X:MSB LSB SW1 - 1(ON) 2(ON) 3(ON) 4(ON)rLwrMw}rNw(jYUjZjHwubaubjB)rOw}rPw(jYX/.. image:: ../../../images/Evmk2e-image003.jpg jZj wjbjvjdjEjf}rQw(UuriX(rtos/../../../images/Evmk2e-image003.jpgrRwjk]jj]jh]ji]jH}rSwU*jRwsjn]ujpK6jqhjr]ubeubj[)rTw}rUw(jYUjKjZjvjbjvjdjejf}rVw(jh]rWwX1attach the serial port cable to the soc uart portrXwaji]jj]jk]rYwU1attach-the-serial-port-cable-to-the-soc-uart-portrZwajn]ujpK8jqhjr]r[w(jt)r\w}r]w(jYX1Attach the serial port cable to the SoC UART portr^wjZjTwjbjvjdjxjf}r_w(jh]ji]jj]jk]jn]ujpK8jqhjr]r`wj{X1Attach the serial port cable to the SoC UART portrawrbw}rcw(jYj^wjZj\wubaubj)rdw}rew(jYXConnect the SoC UART port to PC using the serial cable provided with the EVM. The SoC UART port is the 4-pin white connector COM1 of the EVM.rfwjZjTwjbjvjdjjf}rgw(jh]ji]jj]jk]jn]ujpK:jqhjr]rhwj{XConnect the SoC UART port to PC using the serial cable provided with the EVM. The SoC UART port is the 4-pin white connector COM1 of the EVM.riwrjw}rkw(jYjfwjZjdwubaubj)rlw}rmw(jYX8Start TeraTerm or HyperTerminal and set configuration tornwjZjTwjbjvjdjjf}row(jh]ji]jj]jk]jn]ujpK=jqhjr]rpwj{X8Start TeraTerm or HyperTerminal and set configuration torqwrrw}rsw(jYjnwjZjlwubaubjC)rtw}ruw(jYUjZjTwjbjvjdj`jf}rvw(jGX-jk]jj]jh]ji]jn]ujpK?jqhjr]rww(j/)rxw}ryw(jYX$Baud Rate or Bits per second: 115200rzwjZjtwjbjvjdj2jf}r{w(jh]ji]jj]jk]jn]ujpNjqhjr]r|wj)r}w}r~w(jYjzwjZjxwjbjvjdjjf}rw(jh]ji]jj]jk]jn]ujpK?jr]rwj{X$Baud Rate or Bits per second: 115200rwrw}rw(jYjzwjZj}wubaubaubj/)rw}rw(jYX Data Bits: 8rwjZjtwjbjvjdj2jf}rw(jh]ji]jj]jk]jn]ujpNjqhjr]rwj)rw}rw(jYjwjZjwjbjvjdjjf}rw(jh]ji]jj]jk]jn]ujpK@jr]rwj{X Data Bits: 8rwrw}rw(jYjwjZjwubaubaubj/)rw}rw(jYX Parity: NonerwjZjtwjbjvjdj2jf}rw(jh]ji]jj]jk]jn]ujpNjqhjr]rwj)rw}rw(jYjwjZjwjbjvjdjjf}rw(jh]ji]jj]jk]jn]ujpKAjr]rwj{X Parity: Nonerwrw}rw(jYjwjZjwubaubaubj/)rw}rw(jYX Stop Bits: 1rwjZjtwjbjvjdj2jf}rw(jh]ji]jj]jk]jn]ujpNjqhjr]rwj)rw}rw(jYjwjZjwjbjvjdjjf}rw(jh]ji]jj]jk]jn]ujpKBjr]rwj{X Stop Bits: 1rwrw}rw(jYjwjZjwubaubaubj/)rw}rw(jYXFlow Control: None jZjtwjbjvjdj2jf}rw(jh]ji]jj]jk]jn]ujpNjqhjr]rwj)rw}rw(jYXFlow Control: NonerwjZjwjbjvjdjjf}rw(jh]ji]jj]jk]jn]ujpKCjr]rwj{XFlow Control: Nonerwrw}rw(jYjwjZjwubaubaubeubeubj[)rw}rw(jYUjKjZjvjbjvjdjejf}rw(jh]rwXconnect the power cablerwaji]jj]jk]rwUconnect-the-power-cablerwajn]ujpKFjqhjr]rw(jt)rw}rw(jYXConnect the power cablerwjZjwjbjvjdjxjf}rw(jh]ji]jj]jk]jn]ujpKFjqhjr]rwj{XConnect the power cablerwrw}rw(jYjwjZjwubaubj)rw}rw(jYXConnect the power cable to the EVM power jack on the board. To be ESD safe, plug in the other end of the power cable only after you have connected the power cord to the board. Then turn on the board.rwjZjwjbjvjdjjf}rw(jh]ji]jj]jk]jn]ujpKHjqhjr]rwj{XConnect the power cable to the EVM power jack on the board. To be ESD safe, plug in the other end of the power cable only after you have connected the power cord to the board. Then turn on the board.rwrw}rw(jYjwjZjwubaubeubeubj[)rw}rw(jYUjKjZjvjbjvjdjejf}rw(jh]rwX&dip switch and bootmode configurationsrwaji]jj]jk]rwU&dip-switch-and-bootmode-configurationsrwajn]ujpKMjqhjr]rw(jt)rw}rw(jYX&DIP Switch and Bootmode ConfigurationsrwjZjwjbjvjdjxjf}rw(jh]ji]jj]jk]jn]ujpKMjqhjr]rwj{X&DIP Switch and Bootmode Configurationsrwrw}rw(jYjwjZjwubaubj)rw}rw(jYX)**EVM SW1 switch Bootmode Configuration**rwjZjwjbjvjdjjf}rw(jh]ji]jj]jk]jn]ujpKOjqhjr]rwj)rw}rw(jYjwjf}rw(jh]ji]jj]jk]jn]ujZjwjr]rwj{X%EVM SW1 switch Bootmode Configurationrwrw}rw(jYUjZjwubajdjubaubj)rw}rw(jYXThe table below shows the bootmode combinations for the BMC v1.1.0.x. and value selected from internal flash memory of LM3s2d93.rwjZjwjbjvjdjjf}rw(jh]ji]jj]jk]jn]ujpKQjqhjr]rwj{XThe table below shows the bootmode combinations for the BMC v1.1.0.x. and value selected from internal flash memory of LM3s2d93.rwrw}rw(jYjwjZjwubaubjd$)rw}rw(jYUjZjwjbjvjdjg$jf}rw(jh]ji]jj]jk]jn]ujpNjqhjr]rwjj$)rw}rw(jYUjf}rw(jk]jj]jh]ji]jn]UcolsKujZjwjr]rw(jo$)rw}rw(jYUjf}rw(jk]jj]jh]ji]jn]UcolwidthKujZjwjr]jdjs$ubjo$)rw}rw(jYUjf}rw(jk]jj]jh]ji]jn]UcolwidthKujZjwjr]jdjs$ubjo$)rw}rw(jYUjf}rx(jk]jj]jh]ji]jn]UcolwidthKujZjwjr]jdjs$ubjo$)rx}rx(jYUjf}rx(jk]jj]jh]ji]jn]UcolwidthKujZjwjr]jdjs$ubj$)rx}rx(jYUjf}rx(jh]ji]jj]jk]jn]ujZjwjr]rx(j$)rx}r x(jYUjf}r x(jh]ji]jj]jk]jn]ujZjxjr]r x(j$)r x}r x(jYUjf}rx(jh]ji]jj]jk]jn]ujZjxjr]rxj)rx}rx(jYX **DIP Switch settings Selected**rxjZj xjbjvjdjjf}rx(jh]ji]jj]jk]jn]ujpKUjr]rxj)rx}rx(jYjxjf}rx(jh]ji]jj]jk]jn]ujZjxjr]rxj{XDIP Switch settings Selectedrxrx}rx(jYUjZjxubajdjubaubajdj$ubj$)rx}rx(jYUjf}rx(jh]ji]jj]jk]jn]ujZjxjr]rxj)r x}r!x(jYX **High\_value of that bootmode**jZjxjbjvjdjjf}r"x(jh]ji]jj]jk]jn]ujpKUjr]r#xj)r$x}r%x(jYX **High\_value of that bootmode**jf}r&x(jh]ji]jj]jk]jn]ujZj xjr]r'xj{XHigh_value of that bootmoder(xr)x}r*x(jYUjZj$xubajdjubaubajdj$ubj$)r+x}r,x(jYUjf}r-x(jh]ji]jj]jk]jn]ujZjxjr]r.xj)r/x}r0x(jYX**Low\_value of that bootmode**jZj+xjbjvjdjjf}r1x(jh]ji]jj]jk]jn]ujpKUjr]r2xj)r3x}r4x(jYX**Low\_value of that bootmode**jf}r5x(jh]ji]jj]jk]jn]ujZj/xjr]r6xj{XLow_value of that bootmoder7xr8x}r9x(jYUjZj3xubajdjubaubajdj$ubj$)r:x}r;x(jYUjf}rx}r?x(jYX**Selected bootmode**r@xjZj:xjbjvjdjjf}rAx(jh]ji]jj]jk]jn]ujpKUjr]rBxj)rCx}rDx(jYj@xjf}rEx(jh]ji]jj]jk]jn]ujZj>xjr]rFxj{XSelected bootmoderGxrHx}rIx(jYUjZjCxubajdjubaubajdj$ubejdj$ubj$)rJx}rKx(jYUjf}rLx(jh]ji]jj]jk]jn]ujZjxjr]rMx(j$)rNx}rOx(jYUjf}rPx(jh]ji]jj]jk]jn]ujZjJxjr]rQxj)rRx}rSx(jYX0000rTxjZjNxjbjvjdjjf}rUx(jh]ji]jj]jk]jn]ujpKYjr]rVxj{X0000rWxrXx}rYx(jYjTxjZjRxubaubajdj$ubj$)rZx}r[x(jYUjf}r\x(jh]ji]jj]jk]jn]ujZjJxjr]r]xj)r^x}r_x(jYX 0x00000000r`xjZjZxjbjvjdjjf}rax(jh]ji]jj]jk]jn]ujpKYjr]rbxj{X 0x00000000rcxrdx}rex(jYj`xjZj^xubaubajdj$ubj$)rfx}rgx(jYUjf}rhx(jh]ji]jj]jk]jn]ujZjJxjr]rixj)rjx}rkx(jYX 0x00010067rlxjZjfxjbjvjdjjf}rmx(jh]ji]jj]jk]jn]ujpKYjr]rnxj{X 0x00010067roxrpx}rqx(jYjlxjZjjxubaubajdj$ubj$)rrx}rsx(jYUjf}rtx(jh]ji]jj]jk]jn]ujZjJxjr]ruxj)rvx}rwx(jYXARM NANDrxxjZjrxjbjvjdjjf}ryx(jh]ji]jj]jk]jn]ujpKYjr]rzxj{XARM NANDr{xr|x}r}x(jYjxxjZjvxubaubajdj$ubejdj$ubj$)r~x}rx(jYUjf}rx(jh]ji]jj]jk]jn]ujZjxjr]rx(j$)rx}rx(jYUjf}rx(jh]ji]jj]jk]jn]ujZj~xjr]rxj)rx}rx(jYX0001rxjZjxjbjvjdjjf}rx(jh]ji]jj]jk]jn]ujpK[jr]rxj{X0001rxrx}rx(jYjxjZjxubaubajdj$ubj$)rx}rx(jYUjf}rx(jh]ji]jj]jk]jn]ujZj~xjr]rxj)rx}rx(jYX 0X00000000rxjZjxjbjvjdjjf}rx(jh]ji]jj]jk]jn]ujpK[jr]rxj{X 0X00000000rxrx}rx(jYjxjZjxubaubajdj$ubj$)rx}rx(jYUjf}rx(jh]ji]jj]jk]jn]ujZj~xjr]rxj)rx}rx(jYX 0x00100001rxjZjxjbjvjdjjf}rx(jh]ji]jj]jk]jn]ujpK[jr]rxj{X 0x00100001rxrx}rx(jYjxjZjxubaubajdj$ubj$)rx}rx(jYUjf}rx(jh]ji]jj]jk]jn]ujZj~xjr]rxj)rx}rx(jYX DSP No BootrxjZjxjbjvjdjjf}rx(jh]ji]jj]jk]jn]ujpK[jr]rxj{X DSP No Bootrxrx}rx(jYjxjZjxubaubajdj$ubejdj$ubj$)rx}rx(jYUjf}rx(jh]ji]jj]jk]jn]ujZjxjr]rx(j$)rx}rx(jYUjf}rx(jh]ji]jj]jk]jn]ujZjxjr]rxj)rx}rx(jYX0010rxjZjxjbjvjdjjf}rx(jh]ji]jj]jk]jn]ujpK]jr]rxj{X0010rxrx}rx(jYjxjZjxubaubajdj$ubj$)rx}rx(jYUjf}rx(jh]ji]jj]jk]jn]ujZjxjr]rxj)rx}rx(jYX 0x00000000rxjZjxjbjvjdjjf}rx(jh]ji]jj]jk]jn]ujpK]jr]rxj{X 0x00000000rxrx}rx(jYjxjZjxubaubajdj$ubj$)rx}rx(jYUjf}rx(jh]ji]jj]jk]jn]ujZjxjr]rxj)rx}rx(jYX 0x00008005rxjZjxjbjvjdjjf}rx(jh]ji]jj]jk]jn]ujpK]jr]rxj{X 0x00008005rxrx}rx(jYjxjZjxubaubajdj$ubj$)rx}rx(jYUjf}rx(jh]ji]jj]jk]jn]ujZjxjr]rxj)rx}rx(jYXARM SPIrxjZjxjbjvjdjjf}rx(jh]ji]jj]jk]jn]ujpK]jr]rxj{XARM SPIrxrx}rx(jYjxjZjxubaubajdj$ubejdj$ubj$)rx}rx(jYUjf}rx(jh]ji]jj]jk]jn]ujZjxjr]rx(j$)rx}rx(jYUjf}rx(jh]ji]jj]jk]jn]ujZjxjr]rxj)rx}rx(jYX0011rxjZjxjbjvjdjjf}rx(jh]ji]jj]jk]jn]ujpK_jr]rxj{X0011rxrx}rx(jYjxjZjxubaubajdj$ubj$)rx}rx(jYUjf}rx(jh]ji]jj]jk]jn]ujZjxjr]rxj)rx}rx(jYX 0x00000000rxjZjxjbjvjdjjf}rx(jh]ji]jj]jk]jn]ujpK_jr]rxj{X 0x00000000rxry}ry(jYjxjZjxubaubajdj$ubj$)ry}ry(jYUjf}ry(jh]ji]jj]jk]jn]ujZjxjr]ryj)ry}ry(jYX 0x00100003ryjZjyjbjvjdjjf}r y(jh]ji]jj]jk]jn]ujpK_jr]r yj{X 0x00100003r yr y}r y(jYjyjZjyubaubajdj$ubj$)ry}ry(jYUjf}ry(jh]ji]jj]jk]jn]ujZjxjr]ryj)ry}ry(jYXARM I2C MasterryjZjyjbjvjdjjf}ry(jh]ji]jj]jk]jn]ujpK_jr]ryj{XARM I2C Masterryry}ry(jYjyjZjyubaubajdj$ubejdj$ubj$)ry}ry(jYUjf}ry(jh]ji]jj]jk]jn]ujZjxjr]ry(j$)ry}ry(jYUjf}r y(jh]ji]jj]jk]jn]ujZjyjr]r!yj)r"y}r#y(jYX0100r$yjZjyjbjvjdjjf}r%y(jh]ji]jj]jk]jn]ujpKajr]r&yj{X0100r'yr(y}r)y(jYj$yjZj"yubaubajdj$ubj$)r*y}r+y(jYUjf}r,y(jh]ji]jj]jk]jn]ujZjyjr]r-yj)r.y}r/y(jYX 0x00000000r0yjZj*yjbjvjdjjf}r1y(jh]ji]jj]jk]jn]ujpKajr]r2yj{X 0x00000000r3yr4y}r5y(jYj0yjZj.yubaubajdj$ubj$)r6y}r7y(jYUjf}r8y(jh]ji]jj]jk]jn]ujZjyjr]r9yj)r:y}r;y(jYX 0x0000006Fryj{X 0x0000006Fr?yr@y}rAy(jYjz}r?z(jYX 0x00001061r@zjZj:zjbjvjdjjf}rAz(jh]ji]jj]jk]jn]ujpKljr]rBzj{X 0x00001061rCzrDz}rEz(jYj@zjZj>zubaubajdj$ubj$)rFz}rGz(jYUjf}rHz(jh]ji]jj]jk]jn]ujZjzjr]rIzj)rJz}rKz(jYX"Sleep with Slow PLL and ARM BypassrLzjZjFzjbjvjdjjf}rMz(jh]ji]jj]jk]jn]ujpKljr]rNzj{X"Sleep with Slow PLL and ARM BypassrOzrPz}rQz(jYjLzjZjJzubaubajdj$ubejdj$ubj$)rRz}rSz(jYUjf}rTz(jh]ji]jj]jk]jn]ujZjxjr]rUz(j$)rVz}rWz(jYUjf}rXz(jh]ji]jj]jk]jn]ujZjRzjr]rYzj)rZz}r[z(jYX1010r\zjZjVzjbjvjdjjf}r]z(jh]ji]jj]jk]jn]ujpKojr]r^zj{X1010r_zr`z}raz(jYj\zjZjZzubaubajdj$ubj$)rbz}rcz(jYUjf}rdz(jh]ji]jj]jk]jn]ujZjRzjr]rezj)rfz}rgz(jYX 0x00000000rhzjZjbzjbjvjdjjf}riz(jh]ji]jj]jk]jn]ujpKojr]rjzj{X 0x00000000rkzrlz}rmz(jYjhzjZjfzubaubajdj$ubj$)rnz}roz(jYUjf}rpz(jh]ji]jj]jk]jn]ujZjRzjr]rqzj)rrz}rsz(jYX 0x00008105rtzjZjnzjbjvjdjjf}ruz(jh]ji]jj]jk]jn]ujpKojr]rvzj{X 0x00008105rwzrxz}ryz(jYjtzjZjrzubaubajdj$ubj$)rzz}r{z(jYUjf}r|z(jh]ji]jj]jk]jn]ujZjRzjr]r}zj)r~z}rz(jYX DSP SPI-bootrzjZjzzjbjvjdjjf}rz(jh]ji]jj]jk]jn]ujpKojr]rzj{X DSP SPI-bootrzrz}rz(jYjzjZj~zubaubajdj$ubejdj$ubj$)rz}rz(jYUjf}rz(jh]ji]jj]jk]jn]ujZjxjr]rz(j$)rz}rz(jYUjf}rz(jh]ji]jj]jk]jn]ujZjzjr]rzj)rz}rz(jYX1011rzjZjzjbjvjdjjf}rz(jh]ji]jj]jk]jn]ujpKqjr]rzj{X1011rzrz}rz(jYjzjZjzubaubajdj$ubj$)rz}rz(jYUjf}rz(jh]ji]jj]jk]jn]ujZjzjr]rzj)rz}rz(jYX 0x00000000rzjZjzjbjvjdjjf}rz(jh]ji]jj]jk]jn]ujpKqjr]rzj{X 0x00000000rzrz}rz(jYjzjZjzubaubajdj$ubj$)rz}rz(jYUjf}rz(jh]ji]jj]jk]jn]ujZjzjr]rzj)rz}rz(jYX 0x00100103rzjZjzjbjvjdjjf}rz(jh]ji]jj]jk]jn]ujpKqjr]rzj{X 0x00100103rzrz}rz(jYjzjZjzubaubajdj$ubj$)rz}rz(jYUjf}rz(jh]ji]jj]jk]jn]ujZjzjr]rzj)rz}rz(jYXARM I2C MasterrzjZjzjbjvjdjjf}rz(jh]ji]jj]jk]jn]ujpKqjr]rzj{XARM I2C Masterrzrz}rz(jYjzjZjzubaubajdj$ubejdj$ubj$)rz}rz(jYUjf}rz(jh]ji]jj]jk]jn]ujZjxjr]rz(j$)rz}rz(jYUjf}rz(jh]ji]jj]jk]jn]ujZjzjr]rzj)rz}rz(jYX1100rzjZjzjbjvjdjjf}rz(jh]ji]jj]jk]jn]ujpKsjr]rzj{X1100rzrz}rz(jYjzjZjzubaubajdj$ubj$)rz}rz(jYUjf}rz(jh]ji]jj]jk]jn]ujZjzjr]rzj)rz}rz(jYX 0x00000000rzjZjzjbjvjdjjf}rz(jh]ji]jj]jk]jn]ujpKsjr]rzj{X 0x00000000rzrz}rz(jYjzjZjzubaubajdj$ubj$)rz}rz(jYUjf}rz(jh]ji]jj]jk]jn]ujZjzjr]rzj)rz}rz(jYX 0x0000016FrzjZjzjbjvjdjjf}rz(jh]ji]jj]jk]jn]ujpKsjr]rzj{X 0x0000016Frzrz}rz(jYjzjZjzubaubajdj$ubj$)rz}rz(jYUjf}rz(jh]ji]jj]jk]jn]ujZjzjr]rzj)rz}rz(jYX DSP UART bootrzjZjzjbjvjdjjf}rz(jh]ji]jj]jk]jn]ujpKsjr]rzj{X DSP UART bootrzrz}rz(jYjzjZjzubaubajdj$ubejdj$ubj$)rz}rz(jYUjf}rz(jh]ji]jj]jk]jn]ujZjxjr]rz(j$)rz}rz(jYUjf}rz(jh]ji]jj]jk]jn]ujZjzjr]rzj)rz}rz(jYX1101rzjZjzjbjvjdjjf}rz(jh]ji]jj]jk]jn]ujpKujr]rzj{X1101rzrz}rz(jYjzjZjzubaubajdj$ubj$)rz}rz(jYUjf}r{(jh]ji]jj]jk]jn]ujZjzjr]r{j)r{}r{(jYX 0x00000000r{jZjzjbjvjdjjf}r{(jh]ji]jj]jk]jn]ujpKujr]r{j{X 0x00000000r{r{}r {(jYj{jZj{ubaubajdj$ubj$)r {}r {(jYUjf}r {(jh]ji]jj]jk]jn]ujZjzjr]r {j)r{}r{(jYX 0x0001516Br{jZj {jbjvjdjjf}r{(jh]ji]jj]jk]jn]ujpKujr]r{j{X 0x0001516Br{r{}r{(jYj{jZj{ubaubajdj$ubj$)r{}r{(jYUjf}r{(jh]ji]jj]jk]jn]ujZjzjr]r{j)r{}r{(jYX DSP RBL ENETr{jZj{jbjvjdjjf}r{(jh]ji]jj]jk]jn]ujpKujr]r{j{X DSP RBL ENETr{r {}r!{(jYj{jZj{ubaubajdj$ubejdj$ubj$)r"{}r#{(jYUjf}r${(jh]ji]jj]jk]jn]ujZjxjr]r%{(j$)r&{}r'{(jYUjf}r({(jh]ji]jj]jk]jn]ujZj"{jr]r){j)r*{}r+{(jYX1110r,{jZj&{jbjvjdjjf}r-{(jh]ji]jj]jk]jn]ujpKwjr]r.{j{X1110r/{r0{}r1{(jYj,{jZj*{ubaubajdj$ubj$)r2{}r3{(jYUjf}r4{(jh]ji]jj]jk]jn]ujZj"{jr]r5{j)r6{}r7{(jYX 0x00000000r8{jZj2{jbjvjdjjf}r9{(jh]ji]jj]jk]jn]ujpKwjr]r:{j{X 0x00000000r;{r<{}r={(jYj8{jZj6{ubaubajdj$ubj$)r>{}r?{(jYUjf}r@{(jh]ji]jj]jk]jn]ujZj"{jr]rA{j)rB{}rC{(jYX 0x00003661rD{jZj>{jbjvjdjjf}rE{(jh]ji]jj]jk]jn]ujpKwjr]rF{j{X 0x00003661rG{rH{}rI{(jYjD{jZjB{ubaubajdj$ubj$)rJ{}rK{(jYUjf}rL{(jh]ji]jj]jk]jn]ujZj"{jr]rM{j)rN{}rO{(jYX$Sleep with Slow PLL and Slow ARM PLLrP{jZjJ{jbjvjdjjf}rQ{(jh]ji]jj]jk]jn]ujpKwjr]rR{j{X$Sleep with Slow PLL and Slow ARM PLLrS{rT{}rU{(jYjP{jZjN{ubaubajdj$ubejdj$ubj$)rV{}rW{(jYUjf}rX{(jh]ji]jj]jk]jn]ujZjxjr]rY{(j$)rZ{}r[{(jYUjf}r\{(jh]ji]jj]jk]jn]ujZjV{jr]r]{j)r^{}r_{(jYX1111r`{jZjZ{jbjvjdjjf}ra{(jh]ji]jj]jk]jn]ujpK{jr]rb{j{X1111rc{rd{}re{(jYj`{jZj^{ubaubajdj$ubj$)rf{}rg{(jYUjf}rh{(jh]ji]jj]jk]jn]ujZjV{jr]ri{j)rj{}rk{(jYX 0x00000000rl{jZjf{jbjvjdjjf}rm{(jh]ji]jj]jk]jn]ujpK{jr]rn{j{X 0x00000000ro{rp{}rq{(jYjl{jZjj{ubaubajdj$ubj$)rr{}rs{(jYUjf}rt{(jh]ji]jj]jk]jn]ujZjV{jr]ru{j)rv{}rw{(jYX 0x00100001rx{jZjr{jbjvjdjjf}ry{(jh]ji]jj]jk]jn]ujpK{jr]rz{j{X 0x00100001r{{r|{}r}{(jYjx{jZjv{ubaubajdj$ubj$)r~{}r{(jYUjf}r{(jh]ji]jj]jk]jn]ujZjV{jr]r{j)r{}r{(jYX DSP No-Bootr{jZj~{jbjvjdjjf}r{(jh]ji]jj]jk]jn]ujpK{jr]r{j{X DSP No-Bootr{r{}r{(jYj{jZj{ubaubajdj$ubejdj$ubejdjy%ubejdjz%ubaubjZ)r{}r{(jYUjZjwjbjvjdj]jf}r{(jh]ji]jj]jk]jn]ujpK~jqhjr]r{j`)r{}r{(jYUjcKjZj{jbjvjdjpjf}r{(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubj[)r{}r{(jYUjZjvjbjvjdjejf}r{(jh]ji]jj]jk]r{Uevm-k2e-how-to-guidesr{ajn]r{haujpKjqhjr]r{(jt)r{}r{(jYXEVM K2E How To Guidesr{jZj{jbjvjdjxjf}r{(jh]ji]jj]jk]jn]ujpKjqhjr]r{j{XEVM K2E How To Guidesr{r{}r{(jYj{jZj{ubaubj[)r{}r{(jYUjZj{jbjvjdjejf}r{(jh]ji]jj]jk]r{U+host-driver-for-on-board-mini-usb-connectorr{ajn]r{h3aujpKjqhjr]r{(jt)r{}r{(jYX+Host driver for on-board mini-USB connectorr{jZj{jbjvjdjxjf}r{(jh]ji]jj]jk]jn]ujpKjqhjr]r{j{X+Host driver for on-board mini-USB connectorr{r{}r{(jYj{jZj{ubaubj)r{}r{(jYXVThe K2E EVM has a CP2105 device on-board. A driver must be installed on the host PC in order to be able to communicate with the EVM using the CP2105 mini-USB connector located at the corner edge of the EVM. The driver can be downloaded from `CP2105 driver download `__.jZj{jbjvjdjjf}r{(jh]ji]jj]jk]jn]ujpKjqhjr]r{(j{XThe K2E EVM has a CP2105 device on-board. A driver must be installed on the host PC in order to be able to communicate with the EVM using the CP2105 mini-USB connector located at the corner edge of the EVM. The driver can be downloaded from r{r{}r{(jYXThe K2E EVM has a CP2105 device on-board. A driver must be installed on the host PC in order to be able to communicate with the EVM using the CP2105 mini-USB connector located at the corner edge of the EVM. The driver can be downloaded from jZj{ubj)r{}r{(jYXd`CP2105 driver download `__jf}r{(UnameXCP2105 driver downloadjXGhttp://www.silabs.com/products/mcu/Pages/USBtoUARTBridgeVCPDrivers.aspxjk]jj]jh]ji]jn]ujZj{jr]r{j{XCP2105 driver downloadr{r{}r{(jYUjZj{ubajdjubj{X.r{}r{(jYX.jZj{ubeubj)r{}r{(jYX[Both Linux and Windows host machine drivers can be downloaded from this page. For Linux host machine, please follow the instructions given in the release notes. There are two versions of drivers for Linux kernel version 3.x.x and 2.6.x. Please download appropriate drivers after identifying the correct kernel version of the user’s host machine.r{jZj{jbjvjdjjf}r{(jh]ji]jj]jk]jn]ujpKjqhjr]r{j{X[Both Linux and Windows host machine drivers can be downloaded from this page. For Linux host machine, please follow the instructions given in the release notes. There are two versions of drivers for Linux kernel version 3.x.x and 2.6.x. Please download appropriate drivers after identifying the correct kernel version of the user’s host machine.r{r{}r{(jYj{jZj{ubaubj)r{}r{(jYXpBefore testing the USB connection, make sure that the mini-USB cable is plugged into the port on the base board.r{jZj{jbjvjdjjf}r{(jh]ji]jj]jk]jn]ujpNjqhjr]r{j)r{}r{(jYj{jZj{jbjvjdjjf}r{(jh]ji]jj]jk]jn]ujpKjr]r{j{XpBefore testing the USB connection, make sure that the mini-USB cable is plugged into the port on the base board.r{r{}r{(jYj{jZj{ubaubaubj)r{}r{(jYX After installing the driver and connecting the USB cable, two COM ports should be visible in the list of COM ports available to connect to in the PC Host terminal console. The lower COM port (Enhanced) corresponds to the SoC UART and the higher (Standard) one corresponds to the MCU UART.r{jZj{jbjvjdjjf}r{(jh]ji]jj]jk]jn]ujpKjqhjr]r{j{X After installing the driver and connecting the USB cable, two COM ports should be visible in the list of COM ports available to connect to in the PC Host terminal console. The lower COM port (Enhanced) corresponds to the SoC UART and the higher (Standard) one corresponds to the MCU UART.r{r{}r{(jYj{jZj{ubaubeubj[)r{}r{(jYUjKjZj{jbjvjdjejf}r{(jh]r{Xbmc version check and updater{aji]jj]jk]r{Ubmc-version-check-and-updater{ajn]ujpKjqhjr]r{(jt)r{}r{(jYXBMC Version Check and Updater{jZj{jbjvjdjxjf}r{(jh]ji]jj]jk]jn]ujpKjqhjr]r{j{XBMC Version Check and Updater{r{}r{(jYj{jZj{ubaubj)r{}r{(jYXiBMC, or Board Management Controller, takes care of the power, clocks, resets, bootmodes, etc. of the EVM.r{jZj{jbjvjdjjf}r{(jh]ji]jj]jk]jn]ujpKjqhjr]r{j{XiBMC, or Board Management Controller, takes care of the power, clocks, resets, bootmodes, etc. of the EVM.r{r{}r{(jYj{jZj{ubaubj)r{}r{(jYXYou can check the version by:r{jZj{jbjvjdjjf}r{(jh]ji]jj]jk]jn]ujpKjqhjr]r{j{XYou can check the version by:r{r{}r{(jYj{jZj{ubaubj%)r{}r{(jYUjZj{jbjvjdj(jf}r{(j*U.jk]jj]jh]j+Uji]jn]j,j-ujpKjqhjr]r{(j/)r{}r|(jYXGOpening a hyperterminal or another similar type of console application.jZj{jbjvjdj2jf}r|(jh]ji]jj]jk]jn]ujpNjqhjr]r|j)r|}r|(jYXGOpening a hyperterminal or another similar type of console application.r|jZj{jbjvjdjjf}r|(jh]ji]jj]jk]jn]ujpKjr]r|j{XGOpening a hyperterminal or another similar type of console application.r|r |}r |(jYj|jZj|ubaubaubj/)r |}r |(jYXSet COM Port to higher value. - When you connect to CP2105 mini-USB on the EVM it will provide two COM port connections, one to the SOC UART and one to BMC UART. - The SOC UART will always be the “Enhanced” COM port, for example COM6 (actual COM PORT values will vary.) jZj{jbNjdj2jf}r |(jh]ji]jj]jk]jn]ujpNjqhjr]r|(j)r|}r|(jYXSet COM Port to higher value.r|jZj |jbjvjdjjf}r|(jh]ji]jj]jk]jn]ujpKjr]r|j{XSet COM Port to higher value.r|r|}r|(jYj|jZj|ubaubjC)r|}r|(jYUjf}r|(jGX-jk]jj]jh]ji]jn]ujZj |jr]r|(j/)r|}r|(jYXWhen you connect to CP2105 mini-USB on the EVM it will provide two COM port connections, one to the SOC UART and one to BMC UART.jf}r|(jh]ji]jj]jk]jn]ujZj|jr]r|j)r|}r |(jYXWhen you connect to CP2105 mini-USB on the EVM it will provide two COM port connections, one to the SOC UART and one to BMC UART.r!|jZj|jbjvjdjjf}r"|(jh]ji]jj]jk]jn]ujpKjr]r#|j{XWhen you connect to CP2105 mini-USB on the EVM it will provide two COM port connections, one to the SOC UART and one to BMC UART.r$|r%|}r&|(jYj!|jZj|ubaubajdj2ubj/)r'|}r(|(jYXnThe SOC UART will always be the “Enhanced” COM port, for example COM6 (actual COM PORT values will vary.) jf}r)|(jh]ji]jj]jk]jn]ujZj|jr]r*|j)r+|}r,|(jYXmThe SOC UART will always be the “Enhanced” COM port, for example COM6 (actual COM PORT values will vary.)r-|jZj'|jbjvjdjjf}r.|(jh]ji]jj]jk]jn]ujpKjr]r/|j{XmThe SOC UART will always be the “Enhanced” COM port, for example COM6 (actual COM PORT values will vary.)r0|r1|}r2|(jYj-|jZj+|ubaubajdj2ubejdj`ubeubj/)r3|}r4|(jYXSet COM port properties appropriately: - Baud Rate or Bits per second: 115200 - Data Bits: 8 - Parity: None - Stop Bits: 1 - Flow Control: None jZj{jbNjdj2jf}r5|(jh]ji]jj]jk]jn]ujpNjqhjr]r6|(j)r7|}r8|(jYX&Set COM port properties appropriately:r9|jZj3|jbjvjdjjf}r:|(jh]ji]jj]jk]jn]ujpKjr]r;|j{X&Set COM port properties appropriately:r<|r=|}r>|(jYj9|jZj7|ubaubjC)r?|}r@|(jYUjf}rA|(jGX-jk]jj]jh]ji]jn]ujZj3|jr]rB|(j/)rC|}rD|(jYX$Baud Rate or Bits per second: 115200rE|jf}rF|(jh]ji]jj]jk]jn]ujZj?|jr]rG|j)rH|}rI|(jYjE|jZjC|jbjvjdjjf}rJ|(jh]ji]jj]jk]jn]ujpKjr]rK|j{X$Baud Rate or Bits per second: 115200rL|rM|}rN|(jYjE|jZjH|ubaubajdj2ubj/)rO|}rP|(jYX Data Bits: 8rQ|jf}rR|(jh]ji]jj]jk]jn]ujZj?|jr]rS|j)rT|}rU|(jYjQ|jZjO|jbjvjdjjf}rV|(jh]ji]jj]jk]jn]ujpKjr]rW|j{X Data Bits: 8rX|rY|}rZ|(jYjQ|jZjT|ubaubajdj2ubj/)r[|}r\|(jYX Parity: Noner]|jf}r^|(jh]ji]jj]jk]jn]ujZj?|jr]r_|j)r`|}ra|(jYj]|jZj[|jbjvjdjjf}rb|(jh]ji]jj]jk]jn]ujpKjr]rc|j{X Parity: Nonerd|re|}rf|(jYj]|jZj`|ubaubajdj2ubj/)rg|}rh|(jYX Stop Bits: 1ri|jf}rj|(jh]ji]jj]jk]jn]ujZj?|jr]rk|j)rl|}rm|(jYji|jZjg|jbjvjdjjf}rn|(jh]ji]jj]jk]jn]ujpKjr]ro|j{X Stop Bits: 1rp|rq|}rr|(jYji|jZjl|ubaubajdj2ubj/)rs|}rt|(jYXFlow Control: None jf}ru|(jh]ji]jj]jk]jn]ujZj?|jr]rv|j)rw|}rx|(jYXFlow Control: Nonery|jZjs|jbjvjdjjf}rz|(jh]ji]jj]jk]jn]ujpKjr]r{|j{XFlow Control: Noner||r}|}r~|(jYjy|jZjw|ubaubajdj2ubejdj`ubeubj/)r|}r|(jYX%At BMC prompt type 'ver' (no quotes).r|jZj{jbjvjdj2jf}r|(jh]ji]jj]jk]jn]ujpNjqhjr]r|j)r|}r|(jYj|jZj|jbjvjdjjf}r|(jh]ji]jj]jk]jn]ujpKjr]r|j{X%At BMC prompt type 'ver' (no quotes).r|r|}r|(jYj|jZj|ubaubaubj/)r|}r|(jYXCheck BMC version jZj{jbjvjdj2jf}r|(jh]ji]jj]jk]jn]ujpNjqhjr]r|j)r|}r|(jYXCheck BMC versionr|jZj|jbjvjdjjf}r|(jh]ji]jj]jk]jn]ujpKjr]r|j{XCheck BMC versionr|r|}r|(jYj|jZj|ubaubaubeubjB)r|}r|(jYX/.. image:: ../../../images/Evmk2e-image005.jpg jZj{jbjvjdjEjf}r|(UuriX(rtos/../../../images/Evmk2e-image005.jpgr|jk]jj]jh]ji]jH}r|U*j|sjn]ujpKjqhjr]ubj)r|}r|(jYXIf an in-field update is needed, downloaded the latest version `here `__ (labeled “BMC”) and follow instructions below.jZj{jbjvjdjjf}r|(jh]ji]jj]jk]jn]ujpKjqhjr]r|(j{X?If an in-field update is needed, downloaded the latest version r|r|}r|(jYX?If an in-field update is needed, downloaded the latest version jZj|ubj)r|}r|(jYXg`here `__jf}r|(UnameXherejX\https://www.einfochips.com/index.php/partnerships/texas-instruments/k2e-evm.html#5-resourcesjk]jj]jh]ji]jn]ujZj|jr]r|j{Xherer|r|}r|(jYUjZj|ubajdjubj{X3 (labeled “BMC”) and follow instructions below.r|r|}r|(jYX3 (labeled “BMC”) and follow instructions below.jZj|ubeubj[)r|}r|(jYUjZj{jbjvjdjejf}r|(jh]ji]jj]jk]r|Uprepare-evm-for-in-field-updater|ajn]r|haujpKjqhjr]r|(jt)r|}r|(jYXPrepare EVM for in-field updater|jZj|jbjvjdjxjf}r|(jh]ji]jj]jk]jn]ujpKjqhjr]r|j{XPrepare EVM for in-field updater|r|}r|(jYj|jZj|ubaubj%)r|}r|(jYUjZj|jbjvjdj(jf}r|(j*U.jk]jj]jh]j+Uji]jn]j,j-ujpKjqhjr]r|(j/)r|}r|(jYXRemove power to the EVM.r|jZj|jbjvjdj2jf}r|(jh]ji]jj]jk]jn]ujpNjqhjr]r|j)r|}r|(jYj|jZj|jbjvjdjjf}r|(jh]ji]jj]jk]jn]ujpKjr]r|j{XRemove power to the EVM.r|r|}r|(jYj|jZj|ubaubaubj/)r|}r|(jYX.Set boot mode to "No Boot mode” (see above).r|jZj|jbjvjdj2jf}r|(jh]ji]jj]jk]jn]ujpNjqhjr]r|j)r|}r|(jYj|jZj|jbjvjdjjf}r|(jh]ji]jj]jk]jn]ujpKjr]r|j{X.Set boot mode to "No Boot mode” (see above).r|r|}r|(jYj|jZj|ubaubaubj/)r|}r|(jYXSRemove the MCU\_BOOTSELECT (CN4) jumper (see picture below for location of jumper.)jZj|jbjvjdj2jf}r|(jh]ji]jj]jk]jn]ujpNjqhjr]r|j)r|}r|(jYXSRemove the MCU\_BOOTSELECT (CN4) jumper (see picture below for location of jumper.)jZj|jbjvjdjjf}r|(jh]ji]jj]jk]jn]ujpKjr]r|j{XRRemove the MCU_BOOTSELECT (CN4) jumper (see picture below for location of jumper.)r|r|}r|(jYXSRemove the MCU\_BOOTSELECT (CN4) jumper (see picture below for location of jumper.)jZj|ubaubaubj/)r|}r|(jYXMake sure your - USB cable is connected to CP2105 mini-USB (not XDS200 Emulator USB) or - Connect 4pin UART cable to COM1: MCU UART connector jZj|jbNjdj2jf}r|(jh]ji]jj]jk]jn]ujpNjqhjr]r|(j)r|}r|(jYXMake sure yourr|jZj|jbjvjdjjf}r|(jh]ji]jj]jk]jn]ujpKjr]r|j{XMake sure yourr|r|}r|(jYj|jZj|ubaubjC)r|}r|(jYUjf}r|(jGX-jk]jj]jh]ji]jn]ujZj|jr]r|(j/)r|}r|(jYXFUSB cable is connected to CP2105 mini-USB (not XDS200 Emulator USB) orjf}r|(jh]ji]jj]jk]jn]ujZj|jr]r|j)r|}r|(jYXFUSB cable is connected to CP2105 mini-USB (not XDS200 Emulator USB) orr|jZj|jbjvjdjjf}r|(jh]ji]jj]jk]jn]ujpKjr]r|j{XFUSB cable is connected to CP2105 mini-USB (not XDS200 Emulator USB) orr|r|}r|(jYj|jZj|ubaubajdj2ubj/)r|}r}(jYX4Connect 4pin UART cable to COM1: MCU UART connector jf}r}(jh]ji]jj]jk]jn]ujZj|jr]r}j)r}}r}(jYX3Connect 4pin UART cable to COM1: MCU UART connectorr}jZj|jbjvjdjjf}r}(jh]ji]jj]jk]jn]ujpKjr]r}j{X3Connect 4pin UART cable to COM1: MCU UART connectorr}r }}r }(jYj}jZj}ubaubajdj2ubejdj`ubeubj/)r }}r }(jYXPMake sure no HyperTerminal/Console connected to BMC COM port are open or active.jZj|jbjvjdj2jf}r }(jh]ji]jj]jk]jn]ujpNjqhjr]r}j)r}}r}(jYXPMake sure no HyperTerminal/Console connected to BMC COM port are open or active.r}jZj }jbjvjdjjf}r}(jh]ji]jj]jk]jn]ujpKjr]r}j{XPMake sure no HyperTerminal/Console connected to BMC COM port are open or active.r}r}}r}(jYj}jZj}ubaubaubj/)r}}r}(jYXUse the LM Flash Programmer (available `here `__) to update the firmware, as detailed in the steps below. jZj|jbjvjdj2jf}r}(jh]ji]jj]jk]jn]ujpNjqhjr]r}j)r}}r}(jYXUse the LM Flash Programmer (available `here `__) to update the firmware, as detailed in the steps below.jZj}jbjvjdjjf}r}(jh]ji]jj]jk]jn]ujpKjr]r}(j{X'Use the LM Flash Programmer (available r}r }}r!}(jYX'Use the LM Flash Programmer (available jZj}ubj)r"}}r#}(jYX3`here `__jf}r$}(UnameXherejX(http://www.ti.com/tool/lmflashprogrammerjk]jj]jh]ji]jn]ujZj}jr]r%}j{Xherer&}r'}}r(}(jYUjZj"}ubajdjubj{X9) to update the firmware, as detailed in the steps below.r)}r*}}r+}(jYX9) to update the firmware, as detailed in the steps below.jZj}ubeubaubeubjB)r,}}r-}(jYX/.. image:: ../../../images/Evmk2e-image006.jpg jZj|jbjvjdjEjf}r.}(UuriX(rtos/../../../images/Evmk2e-image006.jpgr/}jk]jj]jh]ji]jH}r0}U*j/}sjn]ujpKjqhjr]ubeubj[)r1}}r2}(jYUjZj{jbjvjdjejf}r3}(jh]ji]jj]jk]r4}Uperform-in-field-updater5}ajn]r6}h_aujpKjqhjr]r7}(jt)r8}}r9}(jYXPerform in-field updater:}jZj1}jbjvjdjxjf}r;}(jh]ji]jj]jk]jn]ujpKjqhjr]r<}j{XPerform in-field updater=}r>}}r?}(jYj:}jZj8}ubaubj%)r@}}rA}(jYUjZj1}jbjvjdj(jf}rB}(j*U.jk]jj]jh]j+Uji]jn]j,j-ujpKjqhjr]rC}(j/)rD}}rE}(jYXApply power to the EVM. No LED's will be illuminated and no LCD backlight or characters will be on because the BMC is waiting for a command rather than executing from Flash.jZj@}jbjvjdj2jf}rF}(jh]ji]jj]jk]jn]ujpNjqhjr]rG}j)rH}}rI}(jYXApply power to the EVM. No LED's will be illuminated and no LCD backlight or characters will be on because the BMC is waiting for a command rather than executing from Flash.rJ}jZjD}jbjvjdjjf}rK}(jh]ji]jj]jk]jn]ujpKjr]rL}j{XApply power to the EVM. No LED's will be illuminated and no LCD backlight or characters will be on because the BMC is waiting for a command rather than executing from Flash.rM}rN}}rO}(jYjJ}jZjH}ubaubaubj/)rP}}rQ}(jYXOpen the LM Flash programmer utility. (Default location Start Menu -> All Programs -> Texas Instruments -> Stellaris -> LM Flash Programmer -> LM Flash Programmer )jZj@}jbjvjdj2jf}rR}(jh]ji]jj]jk]jn]ujpNjqhjr]rS}j)rT}}rU}(jYXOpen the LM Flash programmer utility. (Default location Start Menu -> All Programs -> Texas Instruments -> Stellaris -> LM Flash Programmer -> LM Flash Programmer )rV}jZjP}jbjvjdjjf}rW}(jh]ji]jj]jk]jn]ujpKjr]rX}j{XOpen the LM Flash programmer utility. (Default location Start Menu -> All Programs -> Texas Instruments -> Stellaris -> LM Flash Programmer -> LM Flash Programmer )rY}rZ}}r[}(jYjV}jZjT}ubaubaubj/)r\}}r]}(jYXIn the LM Flash Programmer Utility ‘Configuration’ tab, in the interface section, select ‘Serial (UART)’ from the drop-down box on the left.jZj@}jbjvjdj2jf}r^}(jh]ji]jj]jk]jn]ujpNjqhjr]r_}j)r`}}ra}(jYXIn the LM Flash Programmer Utility ‘Configuration’ tab, in the interface section, select ‘Serial (UART)’ from the drop-down box on the left.rb}jZj\}jbjvjdjjf}rc}(jh]ji]jj]jk]jn]ujpKjr]rd}j{XIn the LM Flash Programmer Utility ‘Configuration’ tab, in the interface section, select ‘Serial (UART)’ from the drop-down box on the left.re}rf}}rg}(jYjb}jZj`}ubaubaubj/)rh}}ri}(jYXySelect the BMC COM Port (the same COM port used to issue the ver command earlier), and set the ‘Baud Rate’ to 115200.jZj@}jbjvjdj2jf}rj}(jh]ji]jj]jk]jn]ujpNjqhjr]rk}j)rl}}rm}(jYXySelect the BMC COM Port (the same COM port used to issue the ver command earlier), and set the ‘Baud Rate’ to 115200.rn}jZjh}jbjvjdjjf}ro}(jh]ji]jj]jk]jn]ujpKjr]rp}j{XySelect the BMC COM Port (the same COM port used to issue the ver command earlier), and set the ‘Baud Rate’ to 115200.rq}rr}}rs}(jYjn}jZjl}ubaubaubj/)rt}}ru}(jYXkSet ‘Transfer Size’ to 60, and make sure ‘Disable Auto Baud Support’ is unchecked. See image below.jZj@}jbjvjdj2jf}rv}(jh]ji]jj]jk]jn]ujpNjqhjr]rw}j)rx}}ry}(jYXkSet ‘Transfer Size’ to 60, and make sure ‘Disable Auto Baud Support’ is unchecked. See image below.rz}jZjt}jbjvjdjjf}r{}(jh]ji]jj]jk]jn]ujpKjr]r|}j{XkSet ‘Transfer Size’ to 60, and make sure ‘Disable Auto Baud Support’ is unchecked. See image below.r}}r~}}r}(jYjz}jZjx}ubaubaubj/)r}}r}(jYXrIn the ‘Program’ tab, Browse to the location of the binary file containing the firmware update, and select it.jZj@}jbjvjdj2jf}r}(jh]ji]jj]jk]jn]ujpNjqhjr]r}j)r}}r}(jYXrIn the ‘Program’ tab, Browse to the location of the binary file containing the firmware update, and select it.r}jZj}jbjvjdjjf}r}(jh]ji]jj]jk]jn]ujpKjr]r}j{XrIn the ‘Program’ tab, Browse to the location of the binary file containing the firmware update, and select it.r}r}}r}(jYj}jZj}ubaubaubj/)r}}r}(jYXGLeave all other options as default, and press the ‘Program’ button.r}jZj@}jbjvjdj2jf}r}(jh]ji]jj]jk]jn]ujpNjqhjr]r}j)r}}r}(jYj}jZj}jbjvjdjjf}r}(jh]ji]jj]jk]jn]ujpKjr]r}j{XGLeave all other options as default, and press the ‘Program’ button.r}r}}r}(jYj}jZj}ubaubaubj/)r}}r}(jYX7After the programming is complete, power off the board.r}jZj@}jbjvjdj2jf}r}(jh]ji]jj]jk]jn]ujpNjqhjr]r}j)r}}r}(jYj}jZj}jbjvjdjjf}r}(jh]ji]jj]jk]jn]ujpKjr]r}j{X7After the programming is complete, power off the board.r}r}}r}(jYj}jZj}ubaubaubj/)r}}r}(jYXReconnect the jumper.r}jZj@}jbjvjdj2jf}r}(jh]ji]jj]jk]jn]ujpNjqhjr]r}j)r}}r}(jYj}jZj}jbjvjdjjf}r}(jh]ji]jj]jk]jn]ujpKjr]r}j{XReconnect the jumper.r}r}}r}(jYj}jZj}ubaubaubj/)r}}r}(jYX4Open the HyperTerminal/Console for the BMC COM port.r}jZj@}jbjvjdj2jf}r}(jh]ji]jj]jk]jn]ujpNjqhjr]r}j)r}}r}(jYj}jZj}jbjvjdjjf}r}(jh]ji]jj]jk]jn]ujpKjr]r}j{X4Open the HyperTerminal/Console for the BMC COM port.r}r}}r}(jYj}jZj}ubaubaubj/)r}}r}(jYXqApply power to the EVM. When BMC completes initialization of board it will show latest version of BMC in Console.jZj@}jbjvjdj2jf}r}(jh]ji]jj]jk]jn]ujpNjqhjr]r}j)r}}r}(jYXqApply power to the EVM. When BMC completes initialization of board it will show latest version of BMC in Console.r}jZj}jbjvjdjjf}r}(jh]ji]jj]jk]jn]ujpKjr]r}j{XqApply power to the EVM. When BMC completes initialization of board it will show latest version of BMC in Console.r}r}}r}(jYj}jZj}ubaubaubj/)r}}r}(jYXKIf step 9 was done after power was applied, just type "ver" at BMC prompt. jZj@}jbjvjdj2jf}r}(jh]ji]jj]jk]jn]ujpNjqhjr]r}j)r}}r}(jYXJIf step 9 was done after power was applied, just type "ver" at BMC prompt.r}jZj}jbjvjdjjf}r}(jh]ji]jj]jk]jn]ujpKjr]r}j{XJIf step 9 was done after power was applied, just type "ver" at BMC prompt.r}r}}r}(jYj}jZj}ubaubaubeubjB)r}}r}(jYX/.. image:: ../../../images/Evmk2e-image007.jpg jZj1}jbjvjdjEjf}r}(UuriX(rtos/../../../images/Evmk2e-image007.jpgr}jk]jj]jh]ji]jH}r}U*j}sjn]ujpKjqhjr]ubeubeubj[)r}}r}(jYUjZj{jbjvjdjejf}r}(jh]ji]jj]jk]r}Uucd-power-management-updater}ajn]r}haujpKjqhjr]r}(jt)r}}r}(jYXUCD Power Management Updater}jZj}jbjvjdjxjf}r}(jh]ji]jj]jk]jn]ujpKjqhjr]r}j{XUCD Power Management Updater}r}}r}(jYj}jZj}ubaubj)r}}r}(jYXThere is one power management module (a.k.a. UCD) located on the EVM. It can be identified by its address: 104(68h). Each module contains non-volatile registers that determine its operation. It may be necessary to update these registers in the field after the board has been shipped.r}jZj}jbjvjdjjf}r}(jh]ji]jj]jk]jn]ujpKjqhjr]r}j{XThere is one power management module (a.k.a. UCD) located on the EVM. It can be identified by its address: 104(68h). Each module contains non-volatile registers that determine its operation. It may be necessary to update these registers in the field after the board has been shipped.r}r}}r}(jYj}jZj}ubaubj)r}}r}(jYX1This update can be performed through the BMC, which can issue commands to the UCD modules to update the register settings. The **Power Management Configuration Update Tool** performs the task of sending commands to the BMC to get the current module versions, and perform updates using configuration files.jZj}jbjvjdjjf}r}(jh]ji]jj]jk]jn]ujpKjqhjr]r}(j{XThis update can be performed through the BMC, which can issue commands to the UCD modules to update the register settings. The r}r}}r}(jYXThis update can be performed through the BMC, which can issue commands to the UCD modules to update the register settings. The jZj}ubj)r}}r}(jYX.**Power Management Configuration Update Tool**jf}r}(jh]ji]jj]jk]jn]ujZj}jr]r}j{X*Power Management Configuration Update Toolr}r}}r}(jYUjZj}ubajdjubj{X performs the task of sending commands to the BMC to get the current module versions, and perform updates using configuration files.r}r}}r~(jYX performs the task of sending commands to the BMC to get the current module versions, and perform updates using configuration files.jZj}ubeubj)r~}r~(jYX^The latest version of the tool is available from `here `__ along with instructions on using the tool, and the latest configuration files (txt files). Please follow the instructions provided to check the current module versions, and update them accordingly.jZj}jbjvjdjjf}r~(jh]ji]jj]jk]jn]ujpKjqhjr]r~(j{X1The latest version of the tool is available from r~r~}r~(jYX1The latest version of the tool is available from jZj~ubj)r~}r ~(jYXg`here `__jf}r ~(UnameXherejX\https://www.einfochips.com/index.php/partnerships/texas-instruments/k2e-evm.html#5-resourcesjk]jj]jh]ji]jn]ujZj~jr]r ~j{Xherer ~r ~}r~(jYUjZj~ubajdjubj{X along with instructions on using the tool, and the latest configuration files (txt files). Please follow the instructions provided to check the current module versions, and update them accordingly.r~r~}r~(jYX along with instructions on using the tool, and the latest configuration files (txt files). Please follow the instructions provided to check the current module versions, and update them accordingly.jZj~ubeubj)r~}r~(jYXPThe DIP switch configuration of the board when running the update is irrelevant.r~jZj}jbjvjdjjf}r~(jh]ji]jj]jk]jn]ujpNjqhjr]r~j)r~}r~(jYj~jZj~jbjvjdjjf}r~(jh]ji]jj]jk]jn]ujpMjr]r~j{XPThe DIP switch configuration of the board when running the update is irrelevant.r~r~}r~(jYj~jZj~ubaubaubj)r~}r~(jYXEVMK2H Hardware SetupjZj}jbjcjdjjf}r ~(jjjk]jj]jh]ji]jn]ujpK|jqhjr]r!~j{XEVMK2H Hardware Setupr"~r#~}r$~(jYUjZj~ubaubj)r%~}r&~(jYX4====================================================jZj}jbjcjdjjf}r'~(jjjk]jj]jh]ji]jn]ujpK}jqhjr]r(~j{X4====================================================r)~r*~}r+~(jYUjZj%~ubaubeubeubeubj[)r,~}r-~(jYUjZjR\jbjX>source/common/EVM_Hardware_Setup/EVMK2H_Hardware_Setup.rst.incr.~r/~}r0~bjdjejf}r1~(jh]ji]jj]jk]r2~Uevmk2h-hardware-setup-guider3~ajn]r4~j-aujpKjqhjr]r5~(jt)r6~}r7~(jYXEVMK2H Hardware Setup Guider8~jZj,~jbj/~jdjxjf}r9~(jh]ji]jj]jk]jn]ujpKjqhjr]r:~j{XEVMK2H Hardware Setup Guider;~r<~}r=~(jYj8~jZj6~ubaubj[)r>~}r?~(jYUjKjZj,~jbj/~jdjejf}r@~(jh]rA~jvaji]jj]jk]rB~Uid61rC~ajn]ujpKjqhjr]rD~(jt)rE~}rF~(jYXHardware SetuprG~jZj>~jbj/~jdjxjf}rH~(jh]ji]jj]jk]jn]ujpKjqhjr]rI~j{XHardware SetuprJ~rK~}rL~(jYjG~jZjE~ubaubj)rM~}rN~(jYXThe EVM board is sensitive to electrostatic discharges (ESD). Use a grounding strap or other device to prevent damaging the board. Be sure to connect communication cables before applying power to any equipment.rO~jZj>~jbj/~jdjjf}rP~(jh]ji]jj]jk]jn]ujpNjqhjr]rQ~j)rR~}rS~(jYjO~jZjM~jbj/~jdjjf}rT~(jh]ji]jj]jk]jn]ujpKjr]rU~j{XThe EVM board is sensitive to electrostatic discharges (ESD). Use a grounding strap or other device to prevent damaging the board. Be sure to connect communication cables before applying power to any equipment.rV~rW~}rX~(jYjO~jZjR~ubaubaubj[)rY~}rZ~(jYUjZj>~jbj/~jdjejf}r[~(jh]ji]jj]jk]r\~U#ftdi-driver-installation-on-pc-hostr]~ajn]r^~haujpK jqhjr]r_~(jt)r`~}ra~(jYX#FTDI Driver Installation on PC Hostrb~jZjY~jbj/~jdjxjf}rc~(jh]ji]jj]jk]jn]ujpK jqhjr]rd~j{X#FTDI Driver Installation on PC Hostre~rf~}rg~(jYjb~jZj`~ubaubj)rh~}ri~(jYXRThe K2 EVM has a FTDI FT2332HL device on board. A driver must be installed on the PC Host in order to be able to communicate with the EVM using the FTDI mini-USB connector located under the mini-USB connector of the emulator daughter card. The driver can be downloaded from here `FTDI Driver `__.jZjY~jbj/~jdjjf}rj~(jh]ji]jj]jk]jn]ujpK jqhjr]rk~(j{XThe K2 EVM has a FTDI FT2332HL device on board. A driver must be installed on the PC Host in order to be able to communicate with the EVM using the FTDI mini-USB connector located under the mini-USB connector of the emulator daughter card. The driver can be downloaded from here rl~rm~}rn~(jYXThe K2 EVM has a FTDI FT2332HL device on board. A driver must be installed on the PC Host in order to be able to communicate with the EVM using the FTDI mini-USB connector located under the mini-USB connector of the emulator daughter card. The driver can be downloaded from here jZjh~ubj)ro~}rp~(jYX:`FTDI Driver `__jf}rq~(UnameX FTDI DriverjX(http://www.ftdichip.com/Drivers/D2XX.htmjk]jj]jh]ji]jn]ujZjh~jr]rr~j{X FTDI Driverrs~rt~}ru~(jYUjZjo~ubajdjubj{X.rv~}rw~(jYX.jZjh~ubeubj)rx~}ry~(jYXBefore testing the usb connection, make sure that the mini-usb cable is plugged into the port on the base board. (and not connected to the daughter card).rz~jZjY~jbj/~jdjjf}r{~(jh]ji]jj]jk]jn]ujpNjqhjr]r|~j)r}~}r~~(jYjz~jZjx~jbj/~jdjjf}r~(jh]ji]jj]jk]jn]ujpKjr]r~j{XBefore testing the usb connection, make sure that the mini-usb cable is plugged into the port on the base board. (and not connected to the daughter card).r~r~}r~(jYjz~jZj}~ubaubaubj)r~}r~(jYX After installing the driver and connecting the USB cable, two COM ports should be visible in the list of COM ports available to connect to in the PC Host terminal console. The lower COM port corresponds to the SoC UART and the higher one corresponds to the MCU UART.r~jZjY~jbj/~jdjjf}r~(jh]ji]jj]jk]jn]ujpKjqhjr]r~j{X After installing the driver and connecting the USB cable, two COM ports should be visible in the list of COM ports available to connect to in the PC Host terminal console. The lower COM port corresponds to the SoC UART and the higher one corresponds to the MCU UART.r~r~}r~(jYj~jZj~ubaubeubj[)r~}r~(jYUjKjZj>~jbj/~jdjejf}r~(jh]r~j{aji]jj]jk]r~Uid62r~ajn]ujpKjqhjr]r~(jt)r~}r~(jYXBMC Version Check and Updater~jZj~jbj/~jdjxjf}r~(jh]ji]jj]jk]jn]ujpKjqhjr]r~j{XBMC Version Check and Updater~r~}r~(jYj~jZj~ubaubj)r~}r~(jYX}Read `BMC\_In-Field\_Update `__ to check BMC version and update if necessary.jZj~jbj/~jdjjf}r~(jh]ji]jj]jk]jn]ujpKjqhjr]r~(j{XRead r~r~}r~(jYXRead jZj~ubj)r~}r~(jYXJ`BMC\_In-Field\_Update `__jf}r~(UnameXBMC_In-Field_UpdatejX.EVMK2H_Hardware_Setup.html#bmc-in-field-updatejk]jj]jh]ji]jn]ujZj~jr]r~j{XBMC_In-Field_Updater~r~}r~(jYUjZj~ubajdjubj{X. to check BMC version and update if necessary.r~r~}r~(jYX. to check BMC version and update if necessary.jZj~ubeubeubj[)r~}r~(jYUjZj>~jbj/~jdjejf}r~(jh]ji]jj]jk]r~U,ucd-power-management-modules-in-field-updater~ajn]r~haujpK"jqhjr]r~(jt)r~}r~(jYX,UCD Power Management Modules In-Field Updater~jZj~jbj/~jdjxjf}r~(jh]ji]jj]jk]jn]ujpK"jqhjr]r~j{X,UCD Power Management Modules In-Field Updater~r~}r~(jYj~jZj~ubaubj)r~}r~(jYX#There are three power management modules (sometimes called the UCDs) located on the EVM. Each module can be identified by it's address: 104(68h), 52(34h), and 78(4Eh). Each module contains non-volatile registers that determine it's operation. It may be necessary to update these registers after the board has been shipped. This update can be performed through the BMC, which can issue commands to the UCD modules to update the register settings. The **Power Management Configuration Update Tool** (bmc\_tool.py) performs the task of sending commands to the BMC to get the current module versions, and perform updates using configuration files. Instructions for executing the update tool (bmc\_tool.py) are available here: :download:`BMC Tool UCD Update Guide <../files/Bmc_tool_ucd_update_guide_v2.pdf>`jZj~jbj/~jdjjf}r~(jh]ji]jj]jk]jn]ujpK$jqhjr]r~(j{XThere are three power management modules (sometimes called the UCDs) located on the EVM. Each module can be identified by it's address: 104(68h), 52(34h), and 78(4Eh). Each module contains non-volatile registers that determine it's operation. It may be necessary to update these registers after the board has been shipped. This update can be performed through the BMC, which can issue commands to the UCD modules to update the register settings. The r~r~}r~(jYXThere are three power management modules (sometimes called the UCDs) located on the EVM. Each module can be identified by it's address: 104(68h), 52(34h), and 78(4Eh). Each module contains non-volatile registers that determine it's operation. It may be necessary to update these registers after the board has been shipped. This update can be performed through the BMC, which can issue commands to the UCD modules to update the register settings. The jZj~ubj)r~}r~(jYX.**Power Management Configuration Update Tool**jf}r~(jh]ji]jj]jk]jn]ujZj~jr]r~j{X*Power Management Configuration Update Toolr~r~}r~(jYUjZj~ubajdjubj{X (bmc_tool.py) performs the task of sending commands to the BMC to get the current module versions, and perform updates using configuration files. Instructions for executing the update tool (bmc_tool.py) are available here: r~r~}r~(jYX (bmc\_tool.py) performs the task of sending commands to the BMC to get the current module versions, and perform updates using configuration files. Instructions for executing the update tool (bmc\_tool.py) are available here: jZj~ubcsphinx.addnodes download_reference r~)r~}r~(jYXQ:download:`BMC Tool UCD Update Guide <../files/Bmc_tool_ucd_update_guide_v2.pdf>`r~jZj~jbj/~jdUdownload_referencer~jf}r~(UreftypeXdownloadr~jjX)../files/Bmc_tool_ucd_update_guide_v2.pdfU refdomainUjk]jj]U refexplicitjh]ji]jn]jjUfilenamer~X Bmc_tool_ucd_update_guide_v2.pdfr~ujpK$jr]r~ji')r~}r~(jYj~jf}r~(jh]ji]r~(jj~ejj]jk]jn]ujZj~jr]r~j{XBMC Tool UCD Update Guider~r~}r~(jYUjZj~ubajdjq'ubaubeubj)r~}r~(jYXThe latest version of the tool is available `here `__. The latest configuration files (txt files) are available `here `__. Please follow the instructions provided to check the current module versions, and update them accordingly.jZj~jbj/~jdjjf}r~(jh]ji]jj]jk]jn]ujpK0jqhjr]r~(j{X,The latest version of the tool is available r~r~}r~(jYX,The latest version of the tool is available jZj~ubj)r~}r~(jYXe`here `__jf}r~(UnameXherejXZhttp://wfcache.advantech.com/www/support/TI-EVM/Rev4_0/BMC/BMC_EVMK2K_1_0_2_6-20160330.zipjk]jj]jh]ji]jn]ujZj~jr]r~j{Xherer~r~}r~(jYUjZj~ubajdjubj{X;. The latest configuration files (txt files) are available r~r~}r~(jYX;. The latest configuration files (txt files) are available jZj~ubj)r~}r~(jYXl`here `__jf}r~(UnameXherejXahttp://wfcache.advantech.com/www/support/TI-EVM/Rev4_0/UCD/UCD_Configuration_Standard_Release.zipjk]jj]jh]ji]jn]ujZj~jr]r~j{Xherer~r~}r~(jYUjZj~ubajdjubj{Xl. Please follow the instructions provided to check the current module versions, and update them accordingly.r~r~}r~(jYXl. Please follow the instructions provided to check the current module versions, and update them accordingly.jZj~ubeubj)r~}r~(jYXPThe DIP switch configuration of the board when running the update is irrelevant.r~jZj~jbj/~jdjjf}r~(jh]ji]jj]jk]jn]ujpNjqhjr]r~j)r~}r~(jYj~jZj~jbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpK7jr]rj{XPThe DIP switch configuration of the board when running the update is irrelevant.rr}r(jYj~jZj~ubaubaubj)r}r(jYXBMC versions 1.0.1.3a and earlier will not work properly with the **Get Versions** feature of the Update Tool. Upgrade to a more recent version of the BMC to use this functionality.rjZj~jbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r (jYjjZjjbj/~jdjjf}r (jh]ji]jj]jk]jn]ujpK9jr]r (j{XBBMC versions 1.0.1.3a and earlier will not work properly with the rr}r(jYXBBMC versions 1.0.1.3a and earlier will not work properly with the jZj ubj)r}r(jYX**Get Versions**jf}r(jh]ji]jj]jk]jn]ujZj jr]rj{X Get Versionsrr}r(jYUjZjubajdjubj{Xc feature of the Update Tool. Upgrade to a more recent version of the BMC to use this functionality.rr}r(jYXc feature of the Update Tool. Upgrade to a more recent version of the BMC to use this functionality.jZj ubeubaubjZ)r}r(jYUjZj~jbj/~jdj]jf}r(jh]ji]jj]jk]jn]ujpK;jqhjr]rj`)r}r (jYUjcKjZjjbj/~jdjpjf}r!(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjZ)r"}r#(jYUjZj~jbj/~jdj]jf}r$(jh]ji]jj]jk]jn]ujpK=jqhjr]r%j`)r&}r'(jYUjcKjZj"jbj/~jdjpjf}r((jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubj[)r)}r*(jYUjKjZj>~jbj/~jdjejf}r+(jh]r,jvaji]jj]jk]r-Uid63r.ajn]ujpK@jqhjr]r/(jt)r0}r1(jYXAttach the Ethernet cabler2jZj)jbj/~jdjxjf}r3(jh]ji]jj]jk]jn]ujpK@jqhjr]r4j{XAttach the Ethernet cabler5r6}r7(jYj2jZj0ubaubj)r8}r9(jYXUsing the Ethernet cable supplied, connect one end of the cable to the Ethernet Port 0 (marked ENET0 on the board) on the EVM and the other end to your PC.r:jZj)jbj/~jdjjf}r;(jh]ji]jj]jk]jn]ujpKBjqhjr]r<j{XUsing the Ethernet cable supplied, connect one end of the cable to the Ethernet Port 0 (marked ENET0 on the board) on the EVM and the other end to your PC.r=r>}r?(jYj:jZj8ubaubj)r@}rA(jYX,This picture shows which Ethernet Port is 0:rBjZj)jbj/~jdjjf}rC(jh]ji]jj]jk]jn]ujpKFjqhjr]rDj{X,This picture shows which Ethernet Port is 0:rErF}rG(jYjBjZj@ubaubjB)rH}rI(jYX).. image:: ../../../images/K2H_ENET0.jpg jZj)jbj/~jdjEjf}rJ(UuriX"rtos/../../../images/K2H_ENET0.jpgrKjk]jj]jh]ji]jH}rLU*jKsjn]ujpKIjqhjr]ubeubj[)rM}rN(jYUjKjZj>~jbj/~jdjejf}rO(jh]rPjvaji]jj]jk]rQUid64rRajn]ujpKKjqhjr]rS(jt)rT}rU(jYXConnect the JTAG interfacerVjZjMjbj/~jdjxjf}rW(jh]ji]jj]jk]jn]ujpKKjqhjr]rXj{XConnect the JTAG interfacerYrZ}r[(jYjVjZjTubaubj)r\}r](jYX#Use the USB to USB mini-B cable provided. Connect the USB mini-B connector to the USB mini-B interface on the XDS-2xx daughter card on the EVM, and the USB connector to your PC. This enables XDS-2xx emulation and is directly useable by CCS. If you are using a different JTAG, connect it now.r^jZjMjbj/~jdjjf}r_(jh]ji]jj]jk]jn]ujpKMjqhjr]r`j{X#Use the USB to USB mini-B cable provided. Connect the USB mini-B connector to the USB mini-B interface on the XDS-2xx daughter card on the EVM, and the USB connector to your PC. This enables XDS-2xx emulation and is directly useable by CCS. If you are using a different JTAG, connect it now.rarb}rc(jYj^jZj\ubaubeubj[)rd}re(jYUjZj>~jbj/~jdjejf}rf(jh]ji]jj]jk]rgU k2h-set-the-boot-mode-switch-sw1rhajn]rij*aujpKTjqhjr]rj(jt)rk}rl(jYX K2H Set the boot mode switch SW1rmjZjdjbj/~jdjxjf}rn(jh]ji]jj]jk]jn]ujpKTjqhjr]roj{X K2H Set the boot mode switch SW1rprq}rr(jYjmjZjkubaubj)rs}rt(jYX,K2H No Boot/JTAG DSP Little Endian Boot moderujZjdjbj/~jdjjf}rv(jk]rwUk2h-set-no-boot-moderxajj]jh]ji]jn]ryh6aujpNjqhjr]rzj{X,K2H No Boot/JTAG DSP Little Endian Boot moder{r|}r}(jYjujZjsubaubj)r~}r(jYX-For **Rev 0B EVM**, the setting is as followsrjZjdjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpKYjqhjr]r(j{XFor rr}r(jYXFor jZj~ubj)r}r(jYX**Rev 0B EVM**jf}r(jh]ji]jj]jk]jn]ujZj~jr]rj{X Rev 0B EVMrr}r(jYUjZjubajdjubj{X, the setting is as followsrr}r(jYX, the setting is as followsjZj~ubeubj)r}r(jYXSW1 - 4(ON) 3(ON) 2(ON) 1(OFF)jZjdjbj/~jdjjf}r(jjjk]jj]jh]ji]jn]ujpM"jqhjr]rj{XSW1 - 4(ON) 3(ON) 2(ON) 1(OFF)rr}r(jYUjZjubaubj)r}r(jYX/For **Rev 1.0 EVM**, the setting is as follows:rjZjdjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpK_jqhjr]r(j{XFor rr}r(jYXFor jZjubj)r}r(jYX**Rev 1.0 EVM**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X Rev 1.0 EVMrr}r(jYUjZjubajdjubj{X, the setting is as follows:rr}r(jYX, the setting is as follows:jZjubeubj)r}r(jYX SW1 - 1(OFF) 2(OFF) 3(OFF) 4(ON)jZjdjbj/~jdjjf}r(jjjk]jj]jh]ji]jn]ujpM"jqhjr]rj{X SW1 - 1(OFF) 2(OFF) 3(OFF) 4(ON)rr}r(jYUjZjubaubjZ)r}r(jYUjZjdjbj/~jdj]jf}r(jh]ji]jj]jk]jn]ujpKejqhjr]rj`)r}r(jYUjcKjZjjbj/~jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r}r(jYXK2H SPI Little Endian Boot moderjZjdjbj/~jdjjf}r(jk]rUk2h-spi-le-boot-moderajj]jh]ji]jn]rhaujpNjqhjr]rj{XK2H SPI Little Endian Boot moderr}r(jYjjZjubaubj)r}r(jYX.For **Rev 0B EVM**, the setting is as follows:rjZjdjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpKjjqhjr]r(j{XFor rr}r(jYXFor jZjubj)r}r(jYX**Rev 0B EVM**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X Rev 0B EVMrr}r(jYUjZjubajdjubj{X, the setting is as follows:rr}r(jYX, the setting is as follows:jZjubeubj)r}r(jYXSW1 - 4(ON) 3(ON) 2(OFF) 1(ON)jZjdjbj/~jdjjf}r(jjjk]jj]jh]ji]jn]ujpM"jqhjr]rj{XSW1 - 4(ON) 3(ON) 2(OFF) 1(ON)rr}r(jYUjZjubaubj)r}r(jYX/For **Rev 1.0 EVM**, the setting is as follows:rjZjdjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpKpjqhjr]r(j{XFor rr}r(jYXFor jZjubj)r}r(jYX**Rev 1.0 EVM**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X Rev 1.0 EVMrr}r(jYUjZjubajdjubj{X, the setting is as follows:rr}r(jYX, the setting is as follows:jZjubeubj)r}r(jYX SW1 - 1(OFF) 2(OFF) 3(ON) 4(OFF)jZjdjbj/~jdjjf}r(jjjk]jj]jh]ji]jn]ujpM"jqhjr]rj{X SW1 - 1(OFF) 2(OFF) 3(ON) 4(OFF)rr}r(jYUjZjubaubeubj[)r}r(jYUjZj>~jbj/~jdjejf}r(jh]ji]jj]jk]rU!ddr-configuration-rev-0b-evm-onlyrajn]rjaujpKwjqhjr]r(jt)r}r(jYX#DDR Configuration (Rev 0B EVM only)rjZjjbj/~jdjxjf}r(jh]ji]jj]jk]jn]ujpKwjqhjr]rj{X#DDR Configuration (Rev 0B EVM only)rr}r(jYjjZjubaubj)r}r(jYXUFor **Rev 0B EVM**, the following procedure is required for proper DDR configuration:jZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpKyjqhjr]r(j{XFor rr}r (jYXFor jZjubj)r }r (jYX**Rev 0B EVM**jf}r (jh]ji]jj]jk]jn]ujZjjr]r j{X Rev 0B EVMrr}r(jYUjZj ubajdjubj{XC, the following procedure is required for proper DDR configuration:rr}r(jYXC, the following procedure is required for proper DDR configuration:jZjubeubjC)r}r(jYUjZjjbj/~jdj`jf}r(jGX-jk]jj]jh]ji]jn]ujpK|jqhjr]r(j/)r}r(jYXIConnect the MCU UART port to PC using the serial cable provided with the EVM. The MCU UART port is the 4-pin white connector farthest from the edge of the EVM. Alternatively it is also possible to connect a mini-USB cable to the FTDI mini-USB connector of the EVM. This will provide access to both the SoC and the MCU UART ports.jZjjbj/~jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXIConnect the MCU UART port to PC using the serial cable provided with the EVM. The MCU UART port is the 4-pin white connector farthest from the edge of the EVM. Alternatively it is also possible to connect a mini-USB cable to the FTDI mini-USB connector of the EVM. This will provide access to both the SoC and the MCU UART ports.rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpK|jr]r j{XIConnect the MCU UART port to PC using the serial cable provided with the EVM. The MCU UART port is the 4-pin white connector farthest from the edge of the EVM. Alternatively it is also possible to connect a mini-USB cable to the FTDI mini-USB connector of the EVM. This will provide access to both the SoC and the MCU UART ports.r!r"}r#(jYjjZjubaubaubj/)r$}r%(jYXrStart Tera Term or Hyper terminal and set to 115200 board rate, 8-bit data, 1-bit stop and no parity/flow control.jZjjbj/~jdj2jf}r&(jh]ji]jj]jk]jn]ujpNjqhjr]r'j)r(}r)(jYXrStart Tera Term or Hyper terminal and set to 115200 board rate, 8-bit data, 1-bit stop and no parity/flow control.r*jZj$jbj/~jdjjf}r+(jh]ji]jj]jk]jn]ujpKjr]r,j{XrStart Tera Term or Hyper terminal and set to 115200 board rate, 8-bit data, 1-bit stop and no parity/flow control.r-r.}r/(jYj*jZj(ubaubaubj/)r0}r1(jYXPower on the EVM. MCU UART console will show user prompt once MCU boot up is complete. Type the following commands at the console to setup DDR3A. Ethernet requires DDR3A and will not work with DDR3B which is default in Rev 0B EVMs. jZjjbj/~jdj2jf}r2(jh]ji]jj]jk]jn]ujpNjqhjr]r3j)r4}r5(jYXPower on the EVM. MCU UART console will show user prompt once MCU boot up is complete. Type the following commands at the console to setup DDR3A. Ethernet requires DDR3A and will not work with DDR3B which is default in Rev 0B EVMs.r6jZj0jbj/~jdjjf}r7(jh]ji]jj]jk]jn]ujpKjr]r8j{XPower on the EVM. MCU UART console will show user prompt once MCU boot up is complete. Type the following commands at the console to setup DDR3A. Ethernet requires DDR3A and will not work with DDR3B which is default in Rev 0B EVMs.r9r:}r;(jYj6jZj4ubaubaubeubj)r<}r=(jYX BMC> setboot 100001 BMC> fullrstjZjjbj/~jdjjf}r>(jjjk]jj]jh]ji]jn]ujpM"jqhjr]r?j{X BMC> setboot 100001 BMC> fullrstr@rA}rB(jYUjZj<ubaubeubj[)rC}rD(jYUjKjZj>~jbj/~jdjejf}rE(jh]rFjXwaji]jj]jk]rGUid65rHajn]ujpKjqhjr]rI(jt)rJ}rK(jYX1Attach the serial port cable to the SoC UART portrLjZjCjbj/~jdjxjf}rM(jh]ji]jj]jk]jn]ujpKjqhjr]rNj{X1Attach the serial port cable to the SoC UART portrOrP}rQ(jYjLjZjJubaubj)rR}rS(jYXConnect the SoC UART port to PC using the serial cable provided with the EVM. The SoC UART port is the 4-pin white connector closest to the edge of the EVM.rTjZjCjbj/~jdjjf}rU(jh]ji]jj]jk]jn]ujpKjqhjr]rVj{XConnect the SoC UART port to PC using the serial cable provided with the EVM. The SoC UART port is the 4-pin white connector closest to the edge of the EVM.rWrX}rY(jYjTjZjRubaubj)rZ}r[(jYXrStart Tera Term or Hyper terminal and set to 115200 board rate, 8-bit data, 1-bit stop and no parity/flow control.r\jZjCjbj/~jdjjf}r](jh]ji]jj]jk]jn]ujpKjqhjr]r^j{XrStart Tera Term or Hyper terminal and set to 115200 board rate, 8-bit data, 1-bit stop and no parity/flow control.r_r`}ra(jYj\jZjZubaubeubj[)rb}rc(jYUjKjZj>~jbj/~jdjejf}rd(jh]rejwaji]jj]jk]rfUid66rgajn]ujpKjqhjr]rh(jt)ri}rj(jYXConnect the power cablerkjZjbjbj/~jdjxjf}rl(jh]ji]jj]jk]jn]ujpKjqhjr]rmj{XConnect the power cablernro}rp(jYjkjZjiubaubj)rq}rr(jYXConnect the power cable to the EVM power jack on the board. To be ESD safe, plug in the other end of the power cable only after you have connected the power cord to the board. Then turn on the board.rsjZjbjbj/~jdjjf}rt(jh]ji]jj]jk]jn]ujpKjqhjr]ruj{XConnect the power cable to the EVM power jack on the board. To be ESD safe, plug in the other end of the power cable only after you have connected the power cord to the board. Then turn on the board.rvrw}rx(jYjsjZjqubaubeubeubj[)ry}rz(jYUjZj,~jbj/~jdjejf}r{(jh]ji]jj]jk]r|Ubmc-in-field-updater}ajn]r~haujpKjqhjr]r(jt)r}r(jYXBMC In-Field UpdaterjZjyjbj/~jdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XBMC In-Field Updaterr}r(jYjjZjubaubj)r}r(jYXiBMC, or Board Management Controller, takes care of the power, clocks, resets, bootmodes, etc. of the EVM.rjZjyjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XiBMC, or Board Management Controller, takes care of the power, clocks, resets, bootmodes, etc. of the EVM.rr}r(jYjjZjubaubj)r}r(jYXFor Rev1.0 EVMs an in-field update may be necessary as a very small quantity were delivered with an old revision of the BMC. If your EVM is using version 1.0.1.3 then it should be updated to version 1.0.1.3a. The update corrects the way that the boot mode pins are interpreted.rjZjyjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XFor Rev1.0 EVMs an in-field update may be necessary as a very small quantity were delivered with an old revision of the BMC. If your EVM is using version 1.0.1.3 then it should be updated to version 1.0.1.3a. The update corrects the way that the boot mode pins are interpreted.rr}r(jYjjZjubaubj)r}r(jYXYou can check the version by:rjZjyjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XYou can check the version by:rr}r(jYjjZjubaubj)r}r(jYXN**1. Opening a hyperterminal or another similar type of console application.**rjZjyjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XJ1. Opening a hyperterminal or another similar type of console application.rr}r(jYUjZjubajdjubaubj)r}r(jYX#**2. Set COM Port to higher value**rjZjyjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X2. Set COM Port to higher valuerr}r(jYUjZjubajdjubaubjC)r}r(jYUjZjyjbj/~jdj`jf}r(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]r(j/)r}r(jYX}When you connect to FTDI mini-USB on the EVM it will provide 2 COM port connections, one to the SOC UART and one to BMC UART.jZjjbj/~jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYX}When you connect to FTDI mini-USB on the EVM it will provide 2 COM port connections, one to the SOC UART and one to BMC UART.r€jZjjbj/~jdjjf}rÀ(jh]ji]jj]jk]jn]ujpKjr]rĀj{X}When you connect to FTDI mini-USB on the EVM it will provide 2 COM port connections, one to the SOC UART and one to BMC UART.rŀrƀ}rǀ(jYj€jZjubaubaubj/)rȀ}rɀ(jYXThe SOC UART will always be the lowest value COM port, for example COM5, and the BMC UART will always be the higher value COM port, for example COM6. (Actual COM PORT values will vary). jZjjbj/~jdj2jf}rʀ(jh]ji]jj]jk]jn]ujpNjqhjr]rˀj)r̀}r̀(jYXThe SOC UART will always be the lowest value COM port, for example COM5, and the BMC UART will always be the higher value COM port, for example COM6. (Actual COM PORT values will vary).r΀jZjȀjbj/~jdjjf}rπ(jh]ji]jj]jk]jn]ujpKjr]rЀj{XThe SOC UART will always be the lowest value COM port, for example COM5, and the BMC UART will always be the higher value COM port, for example COM6. (Actual COM PORT values will vary).rрrҀ}rӀ(jYj΀jZj̀ubaubaubeubj)rԀ}rՀ(jYX,**3. Set COM port properties appopriately:**rրjZjyjbj/~jdjjf}r׀(jh]ji]jj]jk]jn]ujpKjqhjr]r؀j)rـ}rڀ(jYjրjf}rۀ(jh]ji]jj]jk]jn]ujZjԀjr]r܀j{X(3. Set COM port properties appopriately:r݀rހ}r߀(jYUjZjـubajdjubaubjC)r}r(jYUjZjyjbj/~jdj`jf}r(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]r(j/)r}r(jYX$Baud Rate or Bits per second: 115200rjZjjbj/~jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X$Baud Rate or Bits per second: 115200rr}r(jYjjZjubaubaubj/)r}r(jYX Data Bits: 8rjZjjbj/~jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X Data Bits: 8rr}r(jYjjZjubaubaubj/)r}r(jYX Parity: NonerjZjjbj/~jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X Parity: Nonerr}r(jYjjZjubaubaubj/)r}r (jYX Stop Bits: 1r jZjjbj/~jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r }r(jYj jZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X Stop Bits: 1rr}r(jYj jZj ubaubaubj/)r}r(jYXFlow Control: None jZjjbj/~jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXFlow Control: NonerjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XFlow Control: Nonerr}r(jYjjZjubaubaubeubj)r }r!(jYX,**4. At BMC prompt typer 'ver' (no quotes)**r"jZjyjbj/~jdjjf}r#(jh]ji]jj]jk]jn]ujpKjqhjr]r$j)r%}r&(jYj"jf}r'(jh]ji]jj]jk]jn]ujZj jr]r(j{X(4. At BMC prompt typer 'ver' (no quotes)r)r*}r+(jYUjZj%ubajdjubaubj)r,}r-(jYX**5. Check BMC Version**r.jZjyjbj/~jdjjf}r/(jh]ji]jj]jk]jn]ujpKjqhjr]r0j)r1}r2(jYj.jf}r3(jh]ji]jj]jk]jn]ujZj,jr]r4j{X5. Check BMC Versionr5r6}r7(jYUjZj1ubajdjubaubjZ)r8}r9(jYUjZjyjbj/~jdj]jf}r:(jh]ji]jj]jk]jn]ujpKjqhjr]r;j`)r<}r=(jYUjcKjZj8jbj/~jdjpjf}r>(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjB)r?}r@(jYX3.. image:: ../../../images/Bmc_ver_screenshot.JPG jZjyjbj/~jdjEjf}rA(UuriX+rtos/../../../images/Bmc_ver_screenshot.JPGrBjk]jj]jh]ji]jH}rCU*jBsjn]ujpKjqhjr]ubjZ)rD}rE(jYUjZjyjbj/~jdj]jf}rF(jh]ji]jj]jk]jn]ujpKjqhjr]rG(j`)rH}rI(jYUjcKjZjDjbj/~jdjpjf}rJ(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)rK}rL(jYUjcKjZjDjbj/~jdjpjf}rM(jh]ji]jj]jk]jn]ujpKjqhjr]ubeubj)rN}rO(jYXIf an in-field update is needed, downloaded the latest version `here `__ (labeled **Board Management Controller Binaries (BMC)**) and continue with the following steps.jZjyjbj/~jdjjf}rP(jh]ji]jj]jk]jn]ujpKjqhjr]rQ(j{X?If an in-field update is needed, downloaded the latest version rRrS}rT(jYX?If an in-field update is needed, downloaded the latest version jZjNubj)rU}rV(jYXB`here `__jf}rW(UnameXherejX7http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspxjk]jj]jh]ji]jn]ujZjNjr]rXj{XhererYrZ}r[(jYUjZjUubajdjubj{X (labeled r\r]}r^(jYX (labeled jZjNubj)r_}r`(jYX.**Board Management Controller Binaries (BMC)**jf}ra(jh]ji]jj]jk]jn]ujZjNjr]rbj{X*Board Management Controller Binaries (BMC)rcrd}re(jYUjZj_ubajdjubj{X() and continue with the following steps.rfrg}rh(jYX() and continue with the following steps.jZjNubeubjZ)ri}rj(jYUjZjyjbj/~jdj]jf}rk(jh]ji]jj]jk]jn]ujpKjqhjr]rlj`)rm}rn(jYUjcKjZjijbj/~jdjpjf}ro(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)rp}rq(jYX$**Prepare EVM for in-field update:**rrjZjyjbj/~jdjjf}rs(jh]ji]jj]jk]jn]ujpKjqhjr]rtj)ru}rv(jYjrjf}rw(jh]ji]jj]jk]jn]ujZjpjr]rxj{X Prepare EVM for in-field update:ryrz}r{(jYUjZjuubajdjubaubj%)r|}r}(jYUjZjyjbj/~jdj(jf}r~(j*U.jk]jj]jh]j+Uji]jn]j,j-ujpKjqhjr]r(j/)r}r(jYXRemove power to the EVM.rjZj|jbj/~jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XRemove power to the EVM.rr}r(jYjjZjubaubaubj/)r}r(jYX;Set boot mode to "No Boot mode" ( See NoBootLittleEndian_ )rjZj|jbj/~jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]r(j{X&Set boot mode to "No Boot mode" ( See rr}r(jYX&Set boot mode to "No Boot mode" ( See jZjubj)r}r(jYXNoBootLittleEndian_rjf}r(jk]rUid88rajj]jh]ji]jn]UrefidUid87rujZjjr]rj{XNoBootLittleEndian_rr}r(jYUjZjubajdjubj{X )rr}r(jYX )jZjubeubaubj/)r}r(jYXRemove the MCU\_BOOTSELECT (CN9) jumper (see picture below for location of jumper: Referred as "**G: MCU Reset Jumper for BMC field update**\ ").jZj|jbj/~jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXRemove the MCU\_BOOTSELECT (CN9) jumper (see picture below for location of jumper: Referred as "**G: MCU Reset Jumper for BMC field update**\ ").jZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]r(j{X_Remove the MCU_BOOTSELECT (CN9) jumper (see picture below for location of jumper: Referred as "rr}r(jYX`Remove the MCU\_BOOTSELECT (CN9) jumper (see picture below for location of jumper: Referred as "jZjubj)r}r(jYX,**G: MCU Reset Jumper for BMC field update**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X(G: MCU Reset Jumper for BMC field updaterr}r(jYUjZjubajdjubj{X").rr}r(jYX\ ").jZjubeubaubj/)r}r(jYXMake sure your USB cable is connected to FTDI mini-USB (not XDS200 Emulator USB) OR connect 4pin UART cable to COM1: MCU UART connector.jZj|jbj/~jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXMake sure your USB cable is connected to FTDI mini-USB (not XDS200 Emulator USB) OR connect 4pin UART cable to COM1: MCU UART connector.rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rÁj{XMake sure your USB cable is connected to FTDI mini-USB (not XDS200 Emulator USB) OR connect 4pin UART cable to COM1: MCU UART connector.rārŁ}rƁ(jYjjZjubaubaubj/)rǁ}rȁ(jYXPMake sure no HyperTerminal/Console connected to BMC COM port are open or active.jZj|jbj/~jdj2jf}rɁ(jh]ji]jj]jk]jn]ujpNjqhjr]rʁj)rˁ}ŕ(jYXPMake sure no HyperTerminal/Console connected to BMC COM port are open or active.ŕjZjǁjbj/~jdjjf}r΁(jh]ji]jj]jk]jn]ujpKjr]rρj{XPMake sure no HyperTerminal/Console connected to BMC COM port are open or active.rЁrс}rҁ(jYj́jZjˁubaubaubj/)rӁ}rԁ(jYXUse the LM Flash Programmer (available `here `__) to update the firmware, as detailed in the steps below. jZj|jbj/~jdj2jf}rՁ(jh]ji]jj]jk]jn]ujpNjqhjr]rցj)rׁ}r؁(jYXUse the LM Flash Programmer (available `here `__) to update the firmware, as detailed in the steps below.jZjӁjbj/~jdjjf}rف(jh]ji]jj]jk]jn]ujpKjr]rځ(j{X'Use the LM Flash Programmer (available rہr܁}r݁(jYX'Use the LM Flash Programmer (available jZjׁubj)rށ}r߁(jYX3`here `__jf}r(UnameXherejX(http://www.ti.com/tool/lmflashprogrammerjk]jj]jh]ji]jn]ujZjׁjr]rj{Xhererr}r(jYUjZjށubajdjubj{X9) to update the firmware, as detailed in the steps below.rr}r(jYX9) to update the firmware, as detailed in the steps below.jZjׁubeubaubeubjZ)r}r(jYUjZjyjbj/~jdj]jf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj`)r}r(jYUjcKjZjjbj/~jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r}r(jYX**Perform in-field update:**rjZjyjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XPerform in-field update:rr}r(jYUjZjubajdjubaubj%)r}r(jYUjZjyjbj/~jdj(jf}r(j*U.jk]jj]jh]j+Uji]jn]j,j-ujpKjqhjr]r(j/)r}r(jYXApply power to the EVM. No LED's will be illuminated and no LCD backlight or characters will be on because the BMC is waiting for a command rather than executing from Flash.jZjjbj/~jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXApply power to the EVM. No LED's will be illuminated and no LCD backlight or characters will be on because the BMC is waiting for a command rather than executing from Flash.rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XApply power to the EVM. No LED's will be illuminated and no LCD backlight or characters will be on because the BMC is waiting for a command rather than executing from Flash.rr }r (jYjjZjubaubaubj/)r }r (jYXOpen the LM Flash programmer utility. (Default location Start Menu -> All Programs -> Texas Instruments -> Stellaris -> LM Flash Programmer -> LM Flash Programmer )jZjjbj/~jdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXOpen the LM Flash programmer utility. (Default location Start Menu -> All Programs -> Texas Instruments -> Stellaris -> LM Flash Programmer -> LM Flash Programmer )rjZj jbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XOpen the LM Flash programmer utility. (Default location Start Menu -> All Programs -> Texas Instruments -> Stellaris -> LM Flash Programmer -> LM Flash Programmer )rr}r(jYjjZjubaubaubj/)r}r(jYXIn the LM Flash Programmer Utility ‘Configuration’ tab, in the interface section, select ‘Serial (UART)’ from the drop-down box on the left.jZjjbj/~jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXIn the LM Flash Programmer Utility ‘Configuration’ tab, in the interface section, select ‘Serial (UART)’ from the drop-down box on the left.rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XIn the LM Flash Programmer Utility ‘Configuration’ tab, in the interface section, select ‘Serial (UART)’ from the drop-down box on the left.r r!}r"(jYjjZjubaubaubj/)r#}r$(jYXySelect the BMC COM Port (the same COM port used to issue the ver command earlier), and set the ‘Baud Rate’ to 115200.jZjjbj/~jdj2jf}r%(jh]ji]jj]jk]jn]ujpNjqhjr]r&j)r'}r((jYXySelect the BMC COM Port (the same COM port used to issue the ver command earlier), and set the ‘Baud Rate’ to 115200.r)jZj#jbj/~jdjjf}r*(jh]ji]jj]jk]jn]ujpKjr]r+j{XySelect the BMC COM Port (the same COM port used to issue the ver command earlier), and set the ‘Baud Rate’ to 115200.r,r-}r.(jYj)jZj'ubaubaubj/)r/}r0(jYXSet ‘Transfer Size’ to 60, and make sure ‘Disable Auto Baud Support’ is unchecked. .. image:: ../../../images/LMflashProg_Config.png jZjjbNjdj2jf}r1(jh]ji]jj]jk]jn]ujpNjqhjr]r2(j)r3}r4(jYXZSet ‘Transfer Size’ to 60, and make sure ‘Disable Auto Baud Support’ is unchecked.r5jZj/jbj/~jdjjf}r6(jh]ji]jj]jk]jn]ujpKjr]r7j{XZSet ‘Transfer Size’ to 60, and make sure ‘Disable Auto Baud Support’ is unchecked.r8r9}r:(jYj5jZj3ubaubjB)r;}r<(jYX3.. image:: ../../../images/LMflashProg_Config.png jf}r=(UuriX+rtos/../../../images/LMflashProg_Config.pngr>jk]jj]jh]ji]jH}r?U*j>sjn]ujZj/jr]jdjEubeubj/)r@}rA(jYXrIn the ‘Program’ tab, Browse to the location of the binary file containing the firmware update, and select it.jZjjbj/~jdj2jf}rB(jh]ji]jj]jk]jn]ujpNjqhjr]rCj)rD}rE(jYXrIn the ‘Program’ tab, Browse to the location of the binary file containing the firmware update, and select it.rFjZj@jbj/~jdjjf}rG(jh]ji]jj]jk]jn]ujpKjr]rHj{XrIn the ‘Program’ tab, Browse to the location of the binary file containing the firmware update, and select it.rIrJ}rK(jYjFjZjDubaubaubj/)rL}rM(jYXGLeave all other options as default, and press the ‘Program’ button.rNjZjjbj/~jdj2jf}rO(jh]ji]jj]jk]jn]ujpNjqhjr]rPj)rQ}rR(jYjNjZjLjbj/~jdjjf}rS(jh]ji]jj]jk]jn]ujpKjr]rTj{XGLeave all other options as default, and press the ‘Program’ button.rUrV}rW(jYjNjZjQubaubaubj/)rX}rY(jYX7After the programming is complete, power off the board.rZjZjjbj/~jdj2jf}r[(jh]ji]jj]jk]jn]ujpNjqhjr]r\j)r]}r^(jYjZjZjXjbj/~jdjjf}r_(jh]ji]jj]jk]jn]ujpKjr]r`j{X7After the programming is complete, power off the board.rarb}rc(jYjZjZj]ubaubaubj/)rd}re(jYXReconnect the jumper.rfjZjjbj/~jdj2jf}rg(jh]ji]jj]jk]jn]ujpNjqhjr]rhj)ri}rj(jYjfjZjdjbj/~jdjjf}rk(jh]ji]jj]jk]jn]ujpKjr]rlj{XReconnect the jumper.rmrn}ro(jYjfjZjiubaubaubj/)rp}rq(jYX4Open the HyperTerminal/Console for the BMC COM port.rrjZjjbj/~jdj2jf}rs(jh]ji]jj]jk]jn]ujpNjqhjr]rtj)ru}rv(jYjrjZjpjbj/~jdjjf}rw(jh]ji]jj]jk]jn]ujpKjr]rxj{X4Open the HyperTerminal/Console for the BMC COM port.ryrz}r{(jYjrjZjuubaubaubj/)r|}r}(jYXqApply power to the EVM. When BMC completes initialization of board it will show latest version of BMC in Console.jZjjbj/~jdj2jf}r~(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXqApply power to the EVM. When BMC completes initialization of board it will show latest version of BMC in Console.rjZj|jbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XqApply power to the EVM. When BMC completes initialization of board it will show latest version of BMC in Console.rr}r(jYjjZjubaubaubj/)r}r(jYXKIf step 9 was done after power was applied, just type "ver" at BMC prompt. jZjjbj/~jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXJIf step 9 was done after power was applied, just type "ver" at BMC prompt.rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XJIf step 9 was done after power was applied, just type "ver" at BMC prompt.rr}r(jYjjZjubaubaubeubjB)r}r(jYX%.. image:: ../../../images/K2EVM.jpg jZjyjbj/~jdjEjf}r(UuriXrtos/../../../images/K2EVM.jpgrjk]jj]jh]ji]jH}rU*jsjn]ujpMjqhjr]ubeubj[)r}r(jYUjKjZj,~jbj/~jdjejf}r(jh]rjwaji]jj]jk]rUid67rajn]ujpMjqhjr]r(jt)r}r(jYX&DIP Switch and Bootmode ConfigurationsrjZjjbj/~jdjxjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{X&DIP Switch and Bootmode Configurationsrr}r(jYjjZjubaubj)r}r(jYX.. _BootModeConfiguration:jKjZjjbj/~jdjjf}r(jk]jj]jh]ji]jn]jUbootmodeconfigurationrujpMK#jqhjr]ubj[)r}r(jYUjKjZjjbj/~j}rhDjsjdjejf}r(jh]ji]jj]jk]r(U-rev-1-0-evm-sw1-switch-bootmode-configurationrjejn]r(j?hDeujpMjqhj}rjjsjr]r(jt)r}r(jYX-Rev 1.0 EVM SW1 switch Bootmode ConfigurationrjZjjbj/~jdjxjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{X-Rev 1.0 EVM SW1 switch Bootmode Configurationrr}r(jYjjZjubaubjZ)r}r(jYUjZjjbj/~jdj]jf}r(jh]ji]jj]jk]jn]ujpM jqhjr]rj`)r}r‚(jYXFThe table below shows the bootmode combinations for the BMC v1.0.1.3a.rÂjcKjZjjbj/~jdjpjf}rĂ(jh]ji]jj]jk]jn]ujpM jqhjr]rłj{XFThe table below shows the bootmode combinations for the BMC v1.0.1.3a.rƂrǂ}rȂ(jYjÂjZjubaubaubjd$)rɂ}rʂ(jYUjZjjbj/~jdjg$jf}r˂(jh]ji]jj]jk]jn]ujpNjqhjr]r̂jj$)r͂}r΂(jYUjf}rς(jk]jj]jh]ji]jn]UcolsKujZjɂjr]rЂ(jo$)rт}r҂(jYUjf}rӂ(jk]jj]jh]ji]jn]UcolwidthKujZj͂jr]jdjs$ubjo$)rԂ}rՂ(jYUjf}rւ(jk]jj]jh]ji]jn]UcolwidthKujZj͂jr]jdjs$ubjz$)rׂ}r؂(jYUjf}rق(jh]ji]jj]jk]jn]ujZj͂jr]rڂj$)rۂ}r܂(jYUjf}r݂(jh]ji]jj]jk]jn]ujZjׂjr]rނ(j$)r߂}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjۂjr]rj)r}r(jYXDIP Switch (p1, p2, p3, p4)rjZj߂jbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpM jr]rj{XDIP Switch (p1, p2, p3, p4)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjۂjr]rj)r}r(jYXBootmoderjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpM jr]rj{XBootmoderr}r(jYjjZjubaubajdj$ubejdj$ubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj͂jr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX0000rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{X0000rr }r (jYjjZjubaubajdj$ubj$)r }r (jYUjf}r (jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXARM NANDrjZj jbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XARM NANDrr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r (jYX0001r!jZjjbj/~jdjjf}r"(jh]ji]jj]jk]jn]ujpMjr]r#j{X0001r$r%}r&(jYj!jZjubaubajdj$ubj$)r'}r((jYUjf}r)(jh]ji]jj]jk]jn]ujZjjr]r*j)r+}r,(jYX DSP no-bootr-jZj'jbj/~jdjjf}r.(jh]ji]jj]jk]jn]ujpMjr]r/j{X DSP no-bootr0r1}r2(jYj-jZj+ubaubajdj$ubejdj$ubj$)r3}r4(jYUjf}r5(jh]ji]jj]jk]jn]ujZjjr]r6(j$)r7}r8(jYUjf}r9(jh]ji]jj]jk]jn]ujZj3jr]r:j)r;}r<(jYX0010r=jZj7jbj/~jdjjf}r>(jh]ji]jj]jk]jn]ujpMjr]r?j{X0010r@rA}rB(jYj=jZj;ubaubajdj$ubj$)rC}rD(jYUjf}rE(jh]ji]jj]jk]jn]ujZj3jr]rFj)rG}rH(jYXARM SPIrIjZjCjbj/~jdjjf}rJ(jh]ji]jj]jk]jn]ujpMjr]rKj{XARM SPIrLrM}rN(jYjIjZjGubaubajdj$ubejdj$ubj$)rO}rP(jYUjf}rQ(jh]ji]jj]jk]jn]ujZjjr]rR(j$)rS}rT(jYUjf}rU(jh]ji]jj]jk]jn]ujZjOjr]rVj)rW}rX(jYX0011rYjZjSjbj/~jdjjf}rZ(jh]ji]jj]jk]jn]ujpMjr]r[j{X0011r\r]}r^(jYjYjZjWubaubajdj$ubj$)r_}r`(jYUjf}ra(jh]ji]jj]jk]jn]ujZjOjr]rbj)rc}rd(jYXARM I2CrejZj_jbj/~jdjjf}rf(jh]ji]jj]jk]jn]ujpMjr]rgj{XARM I2Crhri}rj(jYjejZjcubaubajdj$ubejdj$ubj$)rk}rl(jYUjf}rm(jh]ji]jj]jk]jn]ujZjjr]rn(j$)ro}rp(jYUjf}rq(jh]ji]jj]jk]jn]ujZjkjr]rrj)rs}rt(jYX0100rujZjojbj/~jdjjf}rv(jh]ji]jj]jk]jn]ujpMjr]rwj{X0100rxry}rz(jYjujZjsubaubajdj$ubj$)r{}r|(jYUjf}r}(jh]ji]jj]jk]jn]ujZjkjr]r~j)r}r(jYXARM UARTrjZj{jbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XARM UARTrr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX0101rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{X0101rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXReservedrjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XReservedrr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX0110rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{X0110rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXReservedrjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XReservedrr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rƒ(j$)rÃ}ră(jYUjf}rŃ(jh]ji]jj]jk]jn]ujZjjr]rƃj)rǃ}rȃ(jYX0111rɃjZjÃjbj/~jdjjf}rʃ(jh]ji]jj]jk]jn]ujpMjr]r˃j{X0111r̃r̓}r΃(jYjɃjZjǃubaubajdj$ubj$)rσ}rЃ(jYUjf}rу(jh]ji]jj]jk]jn]ujZjjr]r҃j)rӃ}rԃ(jYXReservedrՃjZjσjbj/~jdjjf}rփ(jh]ji]jj]jk]jn]ujpMjr]r׃j{XReservedr؃rك}rڃ(jYjՃjZjӃubaubajdj$ubejdj$ubj$)rۃ}r܃(jYUjf}r݃(jh]ji]jj]jk]jn]ujZjjr]rރ(j$)r߃}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjۃjr]rj)r}r(jYX1000rjZj߃jbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{X1000rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjۃjr]rj)r}r(jYXReservedrjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XReservedrr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX1001rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpM!jr]rj{X1001rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r (jh]ji]jj]jk]jn]ujZjjr]r j)r }r (jYXReserved\ :sup:`[1]`jZjjbj/~jdjjf}r (jh]ji]jj]jk]jn]ujpM!jr]r(j{XReservedrr}r(jYX Reserved\ jZj ubcdocutils.nodes superscript r)r}r(jYX :sup:`[1]`jf}r(jh]ji]jj]jk]jn]ujZj jr]rj{X[1]rr}r(jYUjZjubajdU superscriptrubeubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r (jYUjf}r!(jh]ji]jj]jk]jn]ujZjjr]r"j)r#}r$(jYX1010r%jZjjbj/~jdjjf}r&(jh]ji]jj]jk]jn]ujpM#jr]r'j{X1010r(r)}r*(jYj%jZj#ubaubajdj$ubj$)r+}r,(jYUjf}r-(jh]ji]jj]jk]jn]ujZjjr]r.j)r/}r0(jYXReservedr1jZj+jbj/~jdjjf}r2(jh]ji]jj]jk]jn]ujpM#jr]r3j{XReservedr4r5}r6(jYj1jZj/ubaubajdj$ubejdj$ubj$)r7}r8(jYUjf}r9(jh]ji]jj]jk]jn]ujZjjr]r:(j$)r;}r<(jYUjf}r=(jh]ji]jj]jk]jn]ujZj7jr]r>j)r?}r@(jYX1011rAjZj;jbj/~jdjjf}rB(jh]ji]jj]jk]jn]ujpM%jr]rCj{X1011rDrE}rF(jYjAjZj?ubaubajdj$ubj$)rG}rH(jYUjf}rI(jh]ji]jj]jk]jn]ujZj7jr]rJj)rK}rL(jYXReservedrMjZjGjbj/~jdjjf}rN(jh]ji]jj]jk]jn]ujpM%jr]rOj{XReservedrPrQ}rR(jYjMjZjKubaubajdj$ubejdj$ubj$)rS}rT(jYUjf}rU(jh]ji]jj]jk]jn]ujZjjr]rV(j$)rW}rX(jYUjf}rY(jh]ji]jj]jk]jn]ujZjSjr]rZj)r[}r\(jYX1100r]jZjWjbj/~jdjjf}r^(jh]ji]jj]jk]jn]ujpM'jr]r_j{X1100r`ra}rb(jYj]jZj[ubaubajdj$ubj$)rc}rd(jYUjf}re(jh]ji]jj]jk]jn]ujZjSjr]rfj)rg}rh(jYXReservedrijZjcjbj/~jdjjf}rj(jh]ji]jj]jk]jn]ujpM'jr]rkj{XReservedrlrm}rn(jYjijZjgubaubajdj$ubejdj$ubj$)ro}rp(jYUjf}rq(jh]ji]jj]jk]jn]ujZjjr]rr(j$)rs}rt(jYUjf}ru(jh]ji]jj]jk]jn]ujZjojr]rvj)rw}rx(jYX1101ryjZjsjbj/~jdjjf}rz(jh]ji]jj]jk]jn]ujpM)jr]r{j{X1101r|r}}r~(jYjyjZjwubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjojr]rj)r}r(jYXReservedrjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpM)jr]rj{XReservedrr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX1110rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpM+jr]rj{X1110rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXReservedrjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpM+jr]rj{XReservedrr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX1111rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpM-jr]rj{X1111rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXReservedrjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpM-jr]rj{XReservedrr}r„(jYjjZjubaubajdj$ubejdj$ubejdjy%ubejdjz%ubaubj)rÄ}rĄ(jYXg:sup:`[1]`\ In revision BMC v1.0.1.4 this is 10 MHz SPI NOR. This will not continue in future versions.jZjjbj/~jdjjf}rń(jh]ji]jj]jk]jn]ujpM0jqhjr]rƄ(j)rDŽ}rȄ(jYX :sup:`[1]`jf}rɄ(jh]ji]jj]jk]jn]ujZjÄjr]rʄj{X[1]r˄r̄}r̈́(jYUjZjDŽubajdjubj{X[In revision BMC v1.0.1.4 this is 10 MHz SPI NOR. This will not continue in future versions.r΄rτ}rЄ(jYX]\ In revision BMC v1.0.1.4 this is 10 MHz SPI NOR. This will not continue in future versions.jZjÄubeubeubj[)rф}r҄(jYUjZjjbj/~jdjejf}rӄ(jh]ji]jj]jk]rԄUchanging-the-bootmoderՄajn]rքhaujpM4jqhjr]rׄ(jt)r؄}rل(jYXChanging the BootmoderڄjZjфjbj/~jdjxjf}rۄ(jh]ji]jj]jk]jn]ujpM4jqhjr]r܄j{XChanging the Bootmoder݄rބ}r߄(jYjڄjZj؄ubaubj)r}r(jYXIn BMC v1.0.1.x the only way to use a bootmode that is not supported by the DIP switch combinations is to use the 'setboot' and 'fullrst' commands. To set the bootmode use the setboot command, which takes a 32 bit value in hex as its only argument:rjZjфjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpM6jqhjr]rj{XIn BMC v1.0.1.x the only way to use a bootmode that is not supported by the DIP switch combinations is to use the 'setboot' and 'fullrst' commands. To set the bootmode use the setboot command, which takes a 32 bit value in hex as its only argument:rr}r(jYjjZjubaubj)r}r(jYXsetboot 00110CE7jZjфjbj/~jdjjf}r(jjjk]jj]jh]ji]jn]ujpM#jqhjr]rj{Xsetboot 00110CE7rr}r(jYUjZjubaubj)r}r(jYX@Then use the fullrst command to boot the SoC into this bootmode:rjZjфjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpM?jqhjr]rj{X@Then use the fullrst command to boot the SoC into this bootmode:rr}r(jYjjZjubaubj)r}r(jYXfullrstjZjфjbj/~jdjjf}r(jjjk]jj]jh]ji]jn]ujpM#jqhjr]rj{Xfullrstrr}r(jYUjZjubaubj)r}r(jYX\This process is volatile, and will have to be repeated every time the board is power cycled.rjZjфjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMEjqhjr]rj{X\This process is volatile, and will have to be repeated every time the board is power cycled.rr}r(jYjjZjubaubj)r}r(jYXIn BMC v1.0.2.x the setboot command has been removed. It has been replaced with the bootmode command, which performs various functions depending on the way in which the command is used. The command works with 16 bootmodes, which are representative of the various DIP switch combinations; the bootmodes are numbered 0 - 15. Bootmodes 8 - 15 are User-Defined, and may be altered and stored using the command (explained below). Each bootmode consists of a title, a high value, and a low value. The high value is currently not used. The low value is a 32 bit value in hex, and is the same as the value previously used by setboot. The bits of low value (and the setboot argument) are shown in the table below).rjZjфjbj/~jdjjf}r (jh]ji]jj]jk]jn]ujpMHjqhjr]r j{XIn BMC v1.0.2.x the setboot command has been removed. It has been replaced with the bootmode command, which performs various functions depending on the way in which the command is used. The command works with 16 bootmodes, which are representative of the various DIP switch combinations; the bootmodes are numbered 0 - 15. Bootmodes 8 - 15 are User-Defined, and may be altered and stored using the command (explained below). Each bootmode consists of a title, a high value, and a low value. The high value is currently not used. The low value is a 32 bit value in hex, and is the same as the value previously used by setboot. The bits of low value (and the setboot argument) are shown in the table below).r r }r (jYjjZjubaubjd$)r}r(jYUjZjфjbj/~jdjg$jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rjj$)r}r(jYUjf}r(jk]jj]jh]ji]jn]UcolsKujZjjr]r(jo$)r}r(jYUjf}r(jk]jj]jh]ji]jn]UcolwidthKujZjjr]jdjs$ubjo$)r}r(jYUjf}r(jk]jj]jh]ji]jn]UcolwidthKujZjjr]jdjs$ubjo$)r}r(jYUjf}r(jk]jj]jh]ji]jn]UcolwidthKujZjjr]jdjs$ubjo$)r}r (jYUjf}r!(jk]jj]jh]ji]jn]UcolwidthKujZjjr]jdjs$ubjo$)r"}r#(jYUjf}r$(jk]jj]jh]ji]jn]UcolwidthK@ujZjjr]jdjs$ubjz$)r%}r&(jYUjf}r'(jh]ji]jj]jk]jn]ujZjjr]r(j$)r)}r*(jYUjf}r+(jh]ji]jj]jk]jn]ujZj%jr]r,(j$)r-}r.(jYUjf}r/(jh]ji]jj]jk]jn]ujZj)jr]r0j)r1}r2(jYXBitr3jZj-jbj/~jdjjf}r4(jh]ji]jj]jk]jn]ujpMUjr]r5j{XBitr6r7}r8(jYj3jZj1ubaubajdj$ubj$)r9}r:(jYUjf}r;(jh]ji]jj]jk]jn]ujZj)jr]r<j)r=}r>(jYX Devstat Bitr?jZj9jbj/~jdjjf}r@(jh]ji]jj]jk]jn]ujpMUjr]rAj{X Devstat BitrBrC}rD(jYj?jZj=ubaubajdj$ubj$)rE}rF(jYUjf}rG(jh]ji]jj]jk]jn]ujZj)jr]rHj)rI}rJ(jYXConfig Pin FunctionrKjZjEjbj/~jdjjf}rL(jh]ji]jj]jk]jn]ujpMUjr]rMj{XConfig Pin FunctionrNrO}rP(jYjKjZjIubaubajdj$ubj$)rQ}rR(jYUjf}rS(jh]ji]jj]jk]jn]ujZj)jr]rTj)rU}rV(jYXNormal Pin FunctionrWjZjQjbj/~jdjjf}rX(jh]ji]jj]jk]jn]ujpMUjr]rYj{XNormal Pin FunctionrZr[}r\(jYjWjZjUubaubajdj$ubj$)r]}r^(jYUjf}r_(jh]ji]jj]jk]jn]ujZj)jr]r`j)ra}rb(jYXCommentsrcjZj]jbj/~jdjjf}rd(jh]ji]jj]jk]jn]ujpMUjr]rej{XCommentsrfrg}rh(jYjcjZjaubaubajdj$ubejdj$ubajdj$ubj$)ri}rj(jYUjf}rk(jh]ji]jj]jk]jn]ujZjjr]rl(j$)rm}rn(jYUjf}ro(jh]ji]jj]jk]jn]ujZjijr]rp(j$)rq}rr(jYUjf}rs(jh]ji]jj]jk]jn]ujZjmjr]rtj)ru}rv(jYX31rwjZjqjbj/~jdjjf}rx(jh]ji]jj]jk]jn]ujpMWjr]ryj{X31rzr{}r|(jYjwjZjuubaubajdj$ubj$)r}}r~(jYUjf}r(jh]ji]jj]jk]jn]ujZjmjr]jdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjmjr]jdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjmjr]jdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjmjr]rj)r}r(jYXReservedrjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMWjr]rj{XReservedrr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjijr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX30rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMYjr]rj{X30rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]jdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]jdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]jdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXReservedrjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMYjr]rj{XReservedrr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjijr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX29rjZjjbj/~jdjjf}r…(jh]ji]jj]jk]jn]ujpM[jr]rÅj{X29rąrŅ}rƅ(jYjjZjubaubajdj$ubj$)rDž}rȅ(jYUjf}rɅ(jh]ji]jj]jk]jn]ujZjjr]jdj$ubj$)rʅ}r˅(jYUjf}r̅(jh]ji]jj]jk]jn]ujZjjr]jdj$ubj$)rͅ}r΅(jYUjf}rυ(jh]ji]jj]jk]jn]ujZjjr]jdj$ubj$)rЅ}rх(jYUjf}r҅(jh]ji]jj]jk]jn]ujZjjr]rӅj)rԅ}rՅ(jYXReservedrօjZjЅjbj/~jdjjf}rׅ(jh]ji]jj]jk]jn]ujpM[jr]r؅j{XReservedrمrڅ}rۅ(jYjօjZjԅubaubajdj$ubejdj$ubj$)r܅}r݅(jYUjf}rޅ(jh]ji]jj]jk]jn]ujZjijr]r߅(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj܅jr]rj)r}r(jYX28rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpM]jr]rj{X28rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj܅jr]jdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj܅jr]jdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj܅jr]jdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj܅jr]rj)r}r(jYXReservedrjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpM]jr]rj{XReservedrr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjijr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r }r (jYX27r jZjjbj/~jdjjf}r (jh]ji]jj]jk]jn]ujpM_jr]r j{X27rr}r(jYj jZj ubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]jdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]jdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]jdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXReservedr jZjjbj/~jdjjf}r!(jh]ji]jj]jk]jn]ujpM_jr]r"j{XReservedr#r$}r%(jYj jZjubaubajdj$ubejdj$ubj$)r&}r'(jYUjf}r((jh]ji]jj]jk]jn]ujZjijr]r)(j$)r*}r+(jYUjf}r,(jh]ji]jj]jk]jn]ujZj&jr]r-j)r.}r/(jYX26r0jZj*jbj/~jdjjf}r1(jh]ji]jj]jk]jn]ujpMajr]r2j{X26r3r4}r5(jYj0jZj.ubaubajdj$ubj$)r6}r7(jYUjf}r8(jh]ji]jj]jk]jn]ujZj&jr]jdj$ubj$)r9}r:(jYUjf}r;(jh]ji]jj]jk]jn]ujZj&jr]jdj$ubj$)r<}r=(jYUjf}r>(jh]ji]jj]jk]jn]ujZj&jr]jdj$ubj$)r?}r@(jYUjf}rA(jh]ji]jj]jk]jn]ujZj&jr]rBj)rC}rD(jYXReservedrEjZj?jbj/~jdjjf}rF(jh]ji]jj]jk]jn]ujpMajr]rGj{XReservedrHrI}rJ(jYjEjZjCubaubajdj$ubejdj$ubj$)rK}rL(jYUjf}rM(jh]ji]jj]jk]jn]ujZjijr]rN(j$)rO}rP(jYUjf}rQ(jh]ji]jj]jk]jn]ujZjKjr]rRj)rS}rT(jYX25rUjZjOjbj/~jdjjf}rV(jh]ji]jj]jk]jn]ujpMcjr]rWj{X25rXrY}rZ(jYjUjZjSubaubajdj$ubj$)r[}r\(jYUjf}r](jh]ji]jj]jk]jn]ujZjKjr]jdj$ubj$)r^}r_(jYUjf}r`(jh]ji]jj]jk]jn]ujZjKjr]raj)rb}rc(jYXPACLKSELrdjZj^jbj/~jdjjf}re(jh]ji]jj]jk]jn]ujpMcjr]rfj{XPACLKSELrgrh}ri(jYjdjZjbubaubajdj$ubj$)rj}rk(jYUjf}rl(jh]ji]jj]jk]jn]ujZjKjr]rmj)rn}ro(jYXPACLKSELrpjZjjjbj/~jdjjf}rq(jh]ji]jj]jk]jn]ujpMcjr]rrj{XPACLKSELrsrt}ru(jYjpjZjnubaubajdj$ubj$)rv}rw(jYUjf}rx(jh]ji]jj]jk]jn]ujZjKjr]jdj$ubejdj$ubj$)ry}rz(jYUjf}r{(jh]ji]jj]jk]jn]ujZjijr]r|(j$)r}}r~(jYUjf}r(jh]ji]jj]jk]jn]ujZjyjr]rj)r}r(jYX24rjZj}jbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMejr]rj{X24rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjyjr]jdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjyjr]rj)r}r(jYX CORECLKSELrjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMejr]rj{X CORECLKSELrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjyjr]rj)r}r(jYX CORECLKSELrjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMejr]rj{X CORECLKSELrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjyjr]jdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjijr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX23rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMgjr]rj{X23rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]jdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]jdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]jdj$ubj$)r}r(jYUjf}r†(jh]ji]jj]jk]jn]ujZjjr]rÆj)rĆ}rņ(jYXReservedrƆjZjjbj/~jdjjf}rdž(jh]ji]jj]jk]jn]ujpMgjr]rȆj{XReservedrɆrʆ}rˆ(jYjƆjZjĆubaubajdj$ubejdj$ubj$)r̆}r͆(jYUjf}rΆ(jh]ji]jj]jk]jn]ujZjijr]rφ(j$)rІ}rц(jYUjf}r҆(jh]ji]jj]jk]jn]ujZj̆jr]rӆj)rԆ}rՆ(jYX22rֆjZjІjbj/~jdjjf}r׆(jh]ji]jj]jk]jn]ujpMijr]r؆j{X22rنrچ}rۆ(jYjֆjZjԆubaubajdj$ubj$)r܆}r݆(jYUjf}rކ(jh]ji]jj]jk]jn]ujZj̆jr]jdj$ubj$)r߆}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj̆jr]rj)r}r(jYX AVSIFSEL1rjZj߆jbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMijr]rj{X AVSIFSEL1rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj̆jr]rj)r}r(jYXTIMI1rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMijr]rj{XTIMI1rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj̆jr]rj)r}r(jYX<Reserved: EVM forces these bits to strap values during resetrjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMijr]rj{X<Reserved: EVM forces these bits to strap values during resetrr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjijr]r(j$)r}r(jYUjf}r (jh]ji]jj]jk]jn]ujZjjr]r j)r }r (jYX21r jZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMkjr]rj{X21rr}r(jYj jZj ubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]jdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX AVSIFSEL0rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMkjr]rj{X AVSIFSEL0rr }r!(jYjjZjubaubajdj$ubj$)r"}r#(jYUjf}r$(jh]ji]jj]jk]jn]ujZjjr]r%j)r&}r'(jYXTIMI0r(jZj"jbj/~jdjjf}r)(jh]ji]jj]jk]jn]ujpMkjr]r*j{XTIMI0r+r,}r-(jYj(jZj&ubaubajdj$ubj$)r.}r/(jYUjf}r0(jh]ji]jj]jk]jn]ujZjjr]r1j)r2}r3(jYX<Reserved: EVM forces these bits to strap values during resetr4jZj.jbj/~jdjjf}r5(jh]ji]jj]jk]jn]ujpMkjr]r6j{X<Reserved: EVM forces these bits to strap values during resetr7r8}r9(jYj4jZj2ubaubajdj$ubejdj$ubj$)r:}r;(jYUjf}r<(jh]ji]jj]jk]jn]ujZjijr]r=(j$)r>}r?(jYUjf}r@(jh]ji]jj]jk]jn]ujZj:jr]rAj)rB}rC(jYX20rDjZj>jbj/~jdjjf}rE(jh]ji]jj]jk]jn]ujpMmjr]rFj{X20rGrH}rI(jYjDjZjBubaubajdj$ubj$)rJ}rK(jYUjf}rL(jh]ji]jj]jk]jn]ujZj:jr]jdj$ubj$)rM}rN(jYUjf}rO(jh]ji]jj]jk]jn]ujZj:jr]rPj)rQ}rR(jYXDDR3\_REMAP\_ENjZjMjbj/~jdjjf}rS(jh]ji]jj]jk]jn]ujpMmjr]rTj{X DDR3_REMAP_ENrUrV}rW(jYXDDR3\_REMAP\_ENjZjQubaubajdj$ubj$)rX}rY(jYUjf}rZ(jh]ji]jj]jk]jn]ujZj:jr]r[j)r\}r](jYXGPIO16r^jZjXjbj/~jdjjf}r_(jh]ji]jj]jk]jn]ujpMmjr]r`j{XGPIO16rarb}rc(jYj^jZj\ubaubajdj$ubj$)rd}re(jYUjf}rf(jh]ji]jj]jk]jn]ujZj:jr]jdj$ubejdj$ubj$)rg}rh(jYUjf}ri(jh]ji]jj]jk]jn]ujZjijr]rj(j$)rk}rl(jYUjf}rm(jh]ji]jj]jk]jn]ujZjgjr]rnj)ro}rp(jYX19rqjZjkjbj/~jdjjf}rr(jh]ji]jj]jk]jn]ujpMojr]rsj{X19rtru}rv(jYjqjZjoubaubajdj$ubj$)rw}rx(jYUjf}ry(jh]ji]jj]jk]jn]ujZjgjr]jdj$ubj$)rz}r{(jYUjf}r|(jh]ji]jj]jk]jn]ujZjgjr]r}j)r~}r(jYX ARM\_LENDIANjZjzjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMojr]rj{X ARM_LENDIANrr}r(jYX ARM\_LENDIANjZj~ubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjgjr]rj)r}r(jYXGPIO15rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMojr]rj{XGPIO15rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjgjr]rj)r}r(jYX*0 = little, 1 = is not supported; do in SWrjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMojr]rj{X*0 = little, 1 = is not supported; do in SWrr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjijr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX18rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMqjr]rj{X18rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]jdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX MAINPLLODSELrjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMqjr]rj{X MAINPLLODSELrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXCORESEL3r‡jZjjbj/~jdjjf}rÇ(jh]ji]jj]jk]jn]ujpMqjr]rćj{XCORESEL3rŇrƇ}rLJ(jYj‡jZjubaubajdj$ubj$)rȇ}rɇ(jYUjf}rʇ(jh]ji]jj]jk]jn]ujZjjr]jdj$ubejdj$ubj$)rˇ}ṙ(jYUjf}r͇(jh]ji]jj]jk]jn]ujZjijr]r·(j$)rχ}rЇ(jYUjf}rч(jh]ji]jj]jk]jn]ujZjˇjr]r҇j)rӇ}rԇ(jYX17rՇjZjχjbj/~jdjjf}rև(jh]ji]jj]jk]jn]ujpMsjr]rׇj{X17r؇rه}rڇ(jYjՇjZjӇubaubajdj$ubj$)rۇ}r܇(jYUjf}r݇(jh]ji]jj]jk]jn]ujZjˇjr]jdj$ubj$)rއ}r߇(jYUjf}r(jh]ji]jj]jk]jn]ujZjˇjr]rj)r}r(jYX ARMAVSSHAREDrjZjއjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMsjr]rj{X ARMAVSSHAREDrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjˇjr]rj)r}r(jYXCORESEL2rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMsjr]rj{XCORESEL2rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjˇjr]jdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjijr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX16rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMujr]rj{X16rr}r(jYjjZjubaubajdj$ubj$)r }r (jYUjf}r (jh]ji]jj]jk]jn]ujZjjr]r j)r }r(jYX16rjZj jbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMujr]rj{X16rr}r(jYjjZj ubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX BOOTMODE15rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMujr]rj{X BOOTMODE15rr}r (jYjjZjubaubajdj$ubj$)r!}r"(jYUjf}r#(jh]ji]jj]jk]jn]ujZjjr]r$j)r%}r&(jYXCORESEL2r'jZj!jbj/~jdjjf}r((jh]ji]jj]jk]jn]ujpMujr]r)j{XCORESEL2r*r+}r,(jYj'jZj%ubaubajdj$ubj$)r-}r.(jYUjf}r/(jh]ji]jj]jk]jn]ujZjjr]jdj$ubejdj$ubj$)r0}r1(jYUjf}r2(jh]ji]jj]jk]jn]ujZjijr]r3(j$)r4}r5(jYUjf}r6(jh]ji]jj]jk]jn]ujZj0jr]r7j)r8}r9(jYX15r:jZj4jbj/~jdjjf}r;(jh]ji]jj]jk]jn]ujpMwjr]r<j{X15r=r>}r?(jYj:jZj8ubaubajdj$ubj$)r@}rA(jYUjf}rB(jh]ji]jj]jk]jn]ujZj0jr]rCj)rD}rE(jYX15rFjZj@jbj/~jdjjf}rG(jh]ji]jj]jk]jn]ujpMwjr]rHj{X15rIrJ}rK(jYjFjZjDubaubajdj$ubj$)rL}rM(jYUjf}rN(jh]ji]jj]jk]jn]ujZj0jr]rOj)rP}rQ(jYX BOOTMODE14rRjZjLjbj/~jdjjf}rS(jh]ji]jj]jk]jn]ujpMwjr]rTj{X BOOTMODE14rUrV}rW(jYjRjZjPubaubajdj$ubj$)rX}rY(jYUjf}rZ(jh]ji]jj]jk]jn]ujZj0jr]r[j)r\}r](jYXCORESEL1r^jZjXjbj/~jdjjf}r_(jh]ji]jj]jk]jn]ujpMwjr]r`j{XCORESEL1rarb}rc(jYj^jZj\ubaubajdj$ubj$)rd}re(jYUjf}rf(jh]ji]jj]jk]jn]ujZj0jr]rgj)rh}ri(jYXElementrjjZjdjbj/~jdjjf}rk(jh]ji]jj]jk]jn]ujpMwjr]rlj{XElementrmrn}ro(jYjjjZjhubaubajdj$ubejdj$ubj$)rp}rq(jYUjf}rr(jh]ji]jj]jk]jn]ujZjijr]rs(j$)rt}ru(jYUjf}rv(jh]ji]jj]jk]jn]ujZjpjr]rwj)rx}ry(jYX14rzjZjtjbj/~jdjjf}r{(jh]ji]jj]jk]jn]ujpMyjr]r|j{X14r}r~}r(jYjzjZjxubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjpjr]rj)r}r(jYX14rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMyjr]rj{X14rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjpjr]rj)r}r(jYX BOOTMODE13rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMyjr]rj{X BOOTMODE13rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjpjr]rj)r}r(jYXCORESEL0rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMyjr]rj{XCORESEL0rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjpjr]jdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjijr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX13rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpM{jr]rj{X13rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX13rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpM{jr]rj{X13rr}rˆ(jYjjZjubaubajdj$ubj$)rÈ}rĈ(jYUjf}rň(jh]ji]jj]jk]jn]ujZjjr]rƈj)rLj}rȈ(jYX BOOTMODE12rɈjZjÈjbj/~jdjjf}rʈ(jh]ji]jj]jk]jn]ujpM{jr]rˈj{X BOOTMODE12r̈r͈}rΈ(jYjɈjZjLjubaubajdj$ubj$)rψ}rЈ(jYUjf}rш(jh]ji]jj]jk]jn]ujZjjr]r҈j)rӈ}rԈ(jYXGPIO13rՈjZjψjbj/~jdjjf}rֈ(jh]ji]jj]jk]jn]ujpM{jr]r׈j{XGPIO13r؈rو}rڈ(jYjՈjZjӈubaubajdj$ubj$)rۈ}r܈(jYUjf}r݈(jh]ji]jj]jk]jn]ujZjjr]jdj$ubejdj$ubj$)rވ}r߈(jYUjf}r(jh]ji]jj]jk]jn]ujZjijr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjވjr]rj)r}r(jYX12rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpM}jr]rj{X12rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjވjr]rj)r}r(jYX12rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpM}jr]rj{X12rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjވjr]rj)r}r(jYX BOOTMODE11rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpM}jr]rj{X BOOTMODE11rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjވjr]r j)r }r (jYXGPIO12r jZjjbj/~jdjjf}r (jh]ji]jj]jk]jn]ujpM}jr]rj{XGPIO12rr}r(jYj jZj ubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjވjr]jdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjijr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX11rjZjjbj/~jdjjf}r (jh]ji]jj]jk]jn]ujpMjr]r!j{X11r"r#}r$(jYjjZjubaubajdj$ubj$)r%}r&(jYUjf}r'(jh]ji]jj]jk]jn]ujZjjr]r(j)r)}r*(jYX11r+jZj%jbj/~jdjjf}r,(jh]ji]jj]jk]jn]ujpMjr]r-j{X11r.r/}r0(jYj+jZj)ubaubajdj$ubj$)r1}r2(jYUjf}r3(jh]ji]jj]jk]jn]ujZjjr]r4j)r5}r6(jYX BOOTMODE10r7jZj1jbj/~jdjjf}r8(jh]ji]jj]jk]jn]ujpMjr]r9j{X BOOTMODE10r:r;}r<(jYj7jZj5ubaubajdj$ubj$)r=}r>(jYUjf}r?(jh]ji]jj]jk]jn]ujZjjr]r@j)rA}rB(jYXGPIO11rCjZj=jbj/~jdjjf}rD(jh]ji]jj]jk]jn]ujpMjr]rEj{XGPIO11rFrG}rH(jYjCjZjAubaubajdj$ubj$)rI}rJ(jYUjf}rK(jh]ji]jj]jk]jn]ujZjjr]jdj$ubejdj$ubj$)rL}rM(jYUjf}rN(jh]ji]jj]jk]jn]ujZjijr]rO(j$)rP}rQ(jYUjf}rR(jh]ji]jj]jk]jn]ujZjLjr]rSj)rT}rU(jYX10rVjZjPjbj/~jdjjf}rW(jh]ji]jj]jk]jn]ujpMjr]rXj{X10rYrZ}r[(jYjVjZjTubaubajdj$ubj$)r\}r](jYUjf}r^(jh]ji]jj]jk]jn]ujZjLjr]r_j)r`}ra(jYX10rbjZj\jbj/~jdjjf}rc(jh]ji]jj]jk]jn]ujpMjr]rdj{X10rerf}rg(jYjbjZj`ubaubajdj$ubj$)rh}ri(jYUjf}rj(jh]ji]jj]jk]jn]ujZjLjr]rkj)rl}rm(jYX BOOTMODE9rnjZjhjbj/~jdjjf}ro(jh]ji]jj]jk]jn]ujpMjr]rpj{X BOOTMODE9rqrr}rs(jYjnjZjlubaubajdj$ubj$)rt}ru(jYUjf}rv(jh]ji]jj]jk]jn]ujZjLjr]rwj)rx}ry(jYXGPIO10rzjZjtjbj/~jdjjf}r{(jh]ji]jj]jk]jn]ujpMjr]r|j{XGPIO10r}r~}r(jYjzjZjxubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjLjr]jdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjijr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX9jZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{X9r}r(jYX9jZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX9jZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{X9r}r(jYX9jZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX BOOTMODE8rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{X BOOTMODE8rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXGPIO9rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XGPIO9rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]jdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjijr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX8jZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{X8r‰}rÉ(jYX8jZjubaubajdj$ubj$)rĉ}rʼn(jYUjf}rƉ(jh]ji]jj]jk]jn]ujZjjr]rljj)rȉ}rɉ(jYX8jZjĉjbj/~jdjjf}rʉ(jh]ji]jj]jk]jn]ujpMjr]rˉj{X8r̉}r͉(jYX8jZjȉubaubajdj$ubj$)rΉ}rω(jYUjf}rЉ(jh]ji]jj]jk]jn]ujZjjr]rщj)r҉}rӉ(jYX BOOTMODE7rԉjZjΉjbj/~jdjjf}rՉ(jh]ji]jj]jk]jn]ujpMjr]r։j{X BOOTMODE7r׉r؉}rى(jYjԉjZj҉ubaubajdj$ubj$)rډ}rۉ(jYUjf}r܉(jh]ji]jj]jk]jn]ujZjjr]r݉j)rމ}r߉(jYXGPIO8rjZjډjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XGPIO8rr}r(jYjjZjމubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]jdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjijr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX7jZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{X7r}r(jYX7jZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX7jZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{X7r}r(jYX7jZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX BOOTMODE6rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]r j{X BOOTMODE6r r }r (jYjjZjubaubajdj$ubj$)r }r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXGPIO7rjZj jbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XGPIO7rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]jdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjijr]r(j$)r }r!(jYUjf}r"(jh]ji]jj]jk]jn]ujZjjr]r#j)r$}r%(jYX6jZj jbj/~jdjjf}r&(jh]ji]jj]jk]jn]ujpMjr]r'j{X6r(}r)(jYX6jZj$ubaubajdj$ubj$)r*}r+(jYUjf}r,(jh]ji]jj]jk]jn]ujZjjr]r-j)r.}r/(jYX6jZj*jbj/~jdjjf}r0(jh]ji]jj]jk]jn]ujpMjr]r1j{X6r2}r3(jYX6jZj.ubaubajdj$ubj$)r4}r5(jYUjf}r6(jh]ji]jj]jk]jn]ujZjjr]r7j)r8}r9(jYX BOOTMODE5r:jZj4jbj/~jdjjf}r;(jh]ji]jj]jk]jn]ujpMjr]r<j{X BOOTMODE5r=r>}r?(jYj:jZj8ubaubajdj$ubj$)r@}rA(jYUjf}rB(jh]ji]jj]jk]jn]ujZjjr]rCj)rD}rE(jYXGPIO6rFjZj@jbj/~jdjjf}rG(jh]ji]jj]jk]jn]ujpMjr]rHj{XGPIO6rIrJ}rK(jYjFjZjDubaubajdj$ubj$)rL}rM(jYUjf}rN(jh]ji]jj]jk]jn]ujZjjr]jdj$ubejdj$ubj$)rO}rP(jYUjf}rQ(jh]ji]jj]jk]jn]ujZjijr]rR(j$)rS}rT(jYUjf}rU(jh]ji]jj]jk]jn]ujZjOjr]rVj)rW}rX(jYX5jZjSjbj/~jdjjf}rY(jh]ji]jj]jk]jn]ujpMjr]rZj{X5r[}r\(jYX5jZjWubaubajdj$ubj$)r]}r^(jYUjf}r_(jh]ji]jj]jk]jn]ujZjOjr]r`j)ra}rb(jYX5jZj]jbj/~jdjjf}rc(jh]ji]jj]jk]jn]ujpMjr]rdj{X5re}rf(jYX5jZjaubaubajdj$ubj$)rg}rh(jYUjf}ri(jh]ji]jj]jk]jn]ujZjOjr]rjj)rk}rl(jYX BOOTMODE4rmjZjgjbj/~jdjjf}rn(jh]ji]jj]jk]jn]ujpMjr]roj{X BOOTMODE4rprq}rr(jYjmjZjkubaubajdj$ubj$)rs}rt(jYUjf}ru(jh]ji]jj]jk]jn]ujZjOjr]rvj)rw}rx(jYXGPIO5ryjZjsjbj/~jdjjf}rz(jh]ji]jj]jk]jn]ujpMjr]r{j{XGPIO5r|r}}r~(jYjyjZjwubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjOjr]jdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjijr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX4jZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{X4r}r(jYX4jZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX4jZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{X4r}r(jYX4jZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX BOOTMODE3rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{X BOOTMODE3rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXGPIO4rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XGPIO4rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]jdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjijr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX3jZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{X3r}rŠ(jYX3jZjubaubajdj$ubj$)rÊ}rĊ(jYUjf}rŊ(jh]ji]jj]jk]jn]ujZjjr]rƊj)rNJ}rȊ(jYX3jZjÊjbj/~jdjjf}rɊ(jh]ji]jj]jk]jn]ujpMjr]rʊj{X3rˊ}r̊(jYX3jZjNJubaubajdj$ubj$)r͊}rΊ(jYUjf}rϊ(jh]ji]jj]jk]jn]ujZjjr]rЊj)rъ}rҊ(jYX BOOTMODE2rӊjZj͊jbj/~jdjjf}rԊ(jh]ji]jj]jk]jn]ujpMjr]rՊj{X BOOTMODE2r֊r׊}r؊(jYjӊjZjъubaubajdj$ubj$)rي}rڊ(jYUjf}rۊ(jh]ji]jj]jk]jn]ujZjjr]r܊j)r݊}rފ(jYXGPIO3rߊjZjيjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XGPIO3rr}r(jYjߊjZj݊ubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]jdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjijr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX2jZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{X2r}r(jYX2jZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX2jZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{X2r}r(jYX2jZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX BOOTMODE1rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{X BOOTMODE1r r }r (jYjjZjubaubajdj$ubj$)r }r (jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXGPIO2rjZj jbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XGPIO2rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]jdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjijr]r(j$)r}r (jYUjf}r!(jh]ji]jj]jk]jn]ujZjjr]r"j)r#}r$(jYX1jZjjbj/~jdjjf}r%(jh]ji]jj]jk]jn]ujpMjr]r&j{X1r'}r((jYX1jZj#ubaubajdj$ubj$)r)}r*(jYUjf}r+(jh]ji]jj]jk]jn]ujZjjr]r,j)r-}r.(jYX1jZj)jbj/~jdjjf}r/(jh]ji]jj]jk]jn]ujpMjr]r0j{X1r1}r2(jYX1jZj-ubaubajdj$ubj$)r3}r4(jYUjf}r5(jh]ji]jj]jk]jn]ujZjjr]r6j)r7}r8(jYX BOOTMODE0r9jZj3jbj/~jdjjf}r:(jh]ji]jj]jk]jn]ujpMjr]r;j{X BOOTMODE0r<r=}r>(jYj9jZj7ubaubajdj$ubj$)r?}r@(jYUjf}rA(jh]ji]jj]jk]jn]ujZjjr]rBj)rC}rD(jYXGPIO1rEjZj?jbj/~jdjjf}rF(jh]ji]jj]jk]jn]ujpMjr]rGj{XGPIO1rHrI}rJ(jYjEjZjCubaubajdj$ubj$)rK}rL(jYUjf}rM(jh]ji]jj]jk]jn]ujZjjr]jdj$ubejdj$ubj$)rN}rO(jYUjf}rP(jh]ji]jj]jk]jn]ujZjijr]rQ(j$)rR}rS(jYUjf}rT(jh]ji]jj]jk]jn]ujZjNjr]rUj)rV}rW(jYX0jZjRjbj/~jdjjf}rX(jh]ji]jj]jk]jn]ujpMjr]rYj{X0rZ}r[(jYX0jZjVubaubajdj$ubj$)r\}r](jYUjf}r^(jh]ji]jj]jk]jn]ujZjNjr]r_j)r`}ra(jYX0jZj\jbj/~jdjjf}rb(jh]ji]jj]jk]jn]ujpMjr]rcj{X0rd}re(jYX0jZj`ubaubajdj$ubj$)rf}rg(jYUjf}rh(jh]ji]jj]jk]jn]ujZjNjr]rij)rj}rk(jYXLENDIANrljZjfjbj/~jdjjf}rm(jh]ji]jj]jk]jn]ujpMjr]rnj{XLENDIANrorp}rq(jYjljZjjubaubajdj$ubj$)rr}rs(jYUjf}rt(jh]ji]jj]jk]jn]ujZjNjr]ruj)rv}rw(jYXGPIO0rxjZjrjbj/~jdjjf}ry(jh]ji]jj]jk]jn]ujpMjr]rzj{XGPIO0r{r|}r}(jYjxjZjvubaubajdj$ubj$)r~}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjNjr]jdj$ubejdj$ubejdjy%ubejdjz%ubaubj)r}r(jYX6There are 5 different formats to the bootmode command:rjZjфjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{X6There are 5 different formats to the bootmode command:rr}r(jYjjZjubaubj)r}r(jYXbootmodejZjфjbj/~jdjjf}r(jjjk]jj]jh]ji]jn]ujpM#jqhjr]rj{Xbootmoderr}r(jYUjZjubaubj)r}r(jYXUWhen the command is entered with no arguments the current bootmode will be displayed.rjZjфjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{XUWhen the command is entered with no arguments the current bootmode will be displayed.rr}r(jYjjZjubaubj)r}r(jYX bootmode alljZjфjbj/~jdjjf}r(jjjk]jj]jh]ji]jn]ujpM#jqhjr]rj{X bootmode allrr}r(jYUjZjubaubj)r}r(jYXSThis format will display all 16 bootmodes and mark the currently selected bootmode.rjZjфjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{XSThis format will display all 16 bootmodes and mark the currently selected bootmode.rr}r(jYjjZjubaubj)r}r(jYX bootmode #xjZjфjbj/~jdjjf}r(jjjk]jj]jh]ji]jn]ujpM#jqhjr]rj{X bootmode #xrr}r(jYUjZjubaubj)r}r(jYXFThis will change the currently selected bootmode to the bootmode represented by x. For example, if the board is booted with DIP switch setting 1(OFF) 2(OFF) 3(OFF) 4(ON) then the bootmode would be 1 - DSP NO-BOOT. If 'bootmode #2' is entered, the bootmode represented by DIP switch setting 1(OFF) 2(OFF) 3(ON) 4(OFF) would become the current bootmode (ARM SPI-NOR BOOT). If the 'reboot' command is given, the SoC will be rebooted using this new bootmode. This format is volatile, meaning once power is removed, the bootmode at the next power up will be determined by the DIP switch.rjZjфjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{XFThis will change the currently selected bootmode to the bootmode represented by x. For example, if the board is booted with DIP switch setting 1(OFF) 2(OFF) 3(OFF) 4(ON) then the bootmode would be 1 - DSP NO-BOOT. If 'bootmode #2' is entered, the bootmode represented by DIP switch setting 1(OFF) 2(OFF) 3(ON) 4(OFF) would become the current bootmode (ARM SPI-NOR BOOT). If the 'reboot' command is given, the SoC will be rebooted using this new bootmode. This format is volatile, meaning once power is removed, the bootmode at the next power up will be determined by the DIP switch.rr}r(jYjjZjubaubj)r}r(jYX bootmode readjZjфjbj/~jdjjf}r(jjjk]jj]jh]ji]jn]ujpM#jqhjr]rj{X bootmode readrr}r(jYUjZjubaubj)r}r(jYXThis format reads the current value of the DIP switch, and changes the current bootmode to this value. For example, if the board is booted with DIP switch setting 1(OFF) 2(OFF) 3(OFF) 4(ON) then the bootmode would be 1 - DSP NO-BOOT. If the DIP switch is changed to 1(OFF) 2(OFF) 3(ON) 4(OFF) and then the command 'bootmode read' is given, the board will change to bootmode 2 - ARM SPI-NOR BOOT. If the 'reboot command is then given, the SoC will be rebooted using this new bootmode.rjZjфjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{XThis format reads the current value of the DIP switch, and changes the current bootmode to this value. For example, if the board is booted with DIP switch setting 1(OFF) 2(OFF) 3(OFF) 4(ON) then the bootmode would be 1 - DSP NO-BOOT. If the DIP switch is changed to 1(OFF) 2(OFF) 3(ON) 4(OFF) and then the command 'bootmode read' is given, the board will change to bootmode 2 - ARM SPI-NOR BOOT. If the 'reboot command is then given, the SoC will be rebooted using this new bootmode.r‹rË}rċ(jYjjZjubaubj)rŋ}rƋ(jYX%bootmode [#]x hi_value lo_value titlejZjфjbj/~jdjjf}rNj(jjjk]jj]jh]ji]jn]ujpM $jqhjr]rȋj{X%bootmode [#]x hi_value lo_value titlerɋrʋ}rˋ(jYUjZjŋubaubj)r̋}r͋(jYXkThis bootmode is used to alter User-Defined bootmodes (bootmodes 8 - 15). x is the index of the bootmode to be set, as such its appropriate value range is 8 - 15, any other value will return an error. hi\_value is not currently used, and should always be set to 0. lo\_value is a 32 bit hex value whose bits are representative of the table above. title is a given string that is displayed by the bootmode command to help better understand what the bootmode does, it has no purpose within the actual booting of the board. The option '#' is used to determine whether the bootmode will be saved. If # is used, the bootmode will be saved to flash, meaning the new value is tied to the DIP switch, and will remain even if power is removed from the board. If # is not given, then the change will be lost as soon as power is removed. Some examples with descriptions are given below:jZjфjbj/~jdjjf}r΋(jh]ji]jj]jk]jn]ujpMjqhjr]rϋj{XiThis bootmode is used to alter User-Defined bootmodes (bootmodes 8 - 15). x is the index of the bootmode to be set, as such its appropriate value range is 8 - 15, any other value will return an error. hi_value is not currently used, and should always be set to 0. lo_value is a 32 bit hex value whose bits are representative of the table above. title is a given string that is displayed by the bootmode command to help better understand what the bootmode does, it has no purpose within the actual booting of the board. The option '#' is used to determine whether the bootmode will be saved. If # is used, the bootmode will be saved to flash, meaning the new value is tied to the DIP switch, and will remain even if power is removed from the board. If # is not given, then the change will be lost as soon as power is removed. Some examples with descriptions are given below:rЋrы}rҋ(jYXkThis bootmode is used to alter User-Defined bootmodes (bootmodes 8 - 15). x is the index of the bootmode to be set, as such its appropriate value range is 8 - 15, any other value will return an error. hi\_value is not currently used, and should always be set to 0. lo\_value is a 32 bit hex value whose bits are representative of the table above. title is a given string that is displayed by the bootmode command to help better understand what the bootmode does, it has no purpose within the actual booting of the board. The option '#' is used to determine whether the bootmode will be saved. If # is used, the bootmode will be saved to flash, meaning the new value is tied to the DIP switch, and will remain even if power is removed from the board. If # is not given, then the change will be lost as soon as power is removed. Some examples with descriptions are given below:jZj̋ubaubj)rӋ}rԋ(jYXbootmode 8 0 112005 ARM_SPIjZjфjbj/~jdjjf}rՋ(jjjk]jj]jh]ji]jn]ujpM$jqhjr]r֋j{Xbootmode 8 0 112005 ARM_SPIr׋r؋}rً(jYUjZjӋubaubj)rڋ}rۋ(jYXKbootmode 8 will be set to 112005 and given the title ARM\_SPI. To boot into this bootmode, the command 'bootmode #8' followed by 'reboot' would be given (or changing the DIP switch to 1(ON) 2(OFF) 3(OFF) 4(OFF) without removing power, then entering 'bootmode read' followed by 'reboot'). Once power is removed, this change is lost.jZjфjbj/~jdjjf}r܋(jh]ji]jj]jk]jn]ujpMjqhjr]r݋j{XJbootmode 8 will be set to 112005 and given the title ARM_SPI. To boot into this bootmode, the command 'bootmode #8' followed by 'reboot' would be given (or changing the DIP switch to 1(ON) 2(OFF) 3(OFF) 4(OFF) without removing power, then entering 'bootmode read' followed by 'reboot'). Once power is removed, this change is lost.rދrߋ}r(jYXKbootmode 8 will be set to 112005 and given the title ARM\_SPI. To boot into this bootmode, the command 'bootmode #8' followed by 'reboot' would be given (or changing the DIP switch to 1(ON) 2(OFF) 3(OFF) 4(OFF) without removing power, then entering 'bootmode read' followed by 'reboot'). Once power is removed, this change is lost.jZjڋubaubj)r}r(jYX!bootmode #10 0 12cba1 RANDOM_BOOTjZjфjbj/~jdjjf}r(jjjk]jj]jh]ji]jn]ujpM'$jqhjr]rj{X!bootmode #10 0 12cba1 RANDOM_BOOTrr}r(jYUjZjubaubj)r}r(jYXbootmode 10 will be set to 12cba1 and given the title RANDOM\_BOOT. This is now the permanent value of bootmode 10; the change will persist even if power is removed.jZjфjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{Xbootmode 10 will be set to 12cba1 and given the title RANDOM_BOOT. This is now the permanent value of bootmode 10; the change will persist even if power is removed.rr}r(jYXbootmode 10 will be set to 12cba1 and given the title RANDOM\_BOOT. This is now the permanent value of bootmode 10; the change will persist even if power is removed.jZjubaubeubeubj[)r}r(jYUjZj,~jbj/~jdjejf}r(jh]ji]jj]jk]rUconnect-to-evmk2h-using-ccsrajn]rh)aujpMjqhjr]r(jt)r}r(jYXConnect to EVMK2H using CCSrjZjjbj/~jdjxjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{XConnect to EVMK2H using CCSrr}r(jYjjZjubaubj)r}r(jYX&**Step 1:** Configure the EVM hardwarerjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]r(j)r}r(jYX **Step 1:**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XStep 1:rr}r (jYUjZjubajdjubj{X Configure the EVM hardwarer r }r (jYX Configure the EVM hardwarejZjubeubjC)r }r(jYUjZjjbj/~jdj`jf}r(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]r(j/)r}r(jYXZSetup the EVM to DSP no boot using SW1 as described in the section BootModeConfiguration_ jZj jbj/~jdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXYSetup the EVM to DSP no boot using SW1 as described in the section BootModeConfiguration_jZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjr]r(j{XCSetup the EVM to DSP no boot using SW1 as described in the section rr}r(jYXCSetup the EVM to DSP no boot using SW1 as described in the section jZjubj)r}r(jYXBootModeConfiguration_jKjZjjdjjf}r(UnameXBootModeConfigurationjk]jj]jh]ji]jn]jjujr]rj{XBootModeConfigurationr r!}r"(jYUjZjubaubeubaubj/)r#}r$(jYXzConnect mini USB cable to the XDS2xx MIPI adapter card marked J1 or connect external emulator to the MIPI connector on J3 jZj jbj/~jdj2jf}r%(jh]ji]jj]jk]jn]ujpNjqhjr]r&j)r'}r((jYXyConnect mini USB cable to the XDS2xx MIPI adapter card marked J1 or connect external emulator to the MIPI connector on J3r)jZj#jbj/~jdjjf}r*(jh]ji]jj]jk]jn]ujpMjr]r+j{XyConnect mini USB cable to the XDS2xx MIPI adapter card marked J1 or connect external emulator to the MIPI connector on J3r,r-}r.(jYj)jZj'ubaubaubeubj)r/}r0(jYXzFor newer versions of CCS, a XDS200 firmware update is recommended which user can perform using instruction on the articler1jZjjbj/~jdjjf}r2(jh]ji]jj]jk]jn]ujpNjqhjr]r3j)r4}r5(jYj1jZj/jbj/~jdjjf}r6(jh]ji]jj]jk]jn]ujpMjr]r7j{XzFor newer versions of CCS, a XDS200 firmware update is recommended which user can perform using instruction on the articler8r9}r:(jYj1jZj4ubaubaubj)r;}r<(jYXbelow:r=jZjjbj/~jdjjf}r>(jh]ji]jj]jk]jn]ujpMjqhjr]r?j{Xbelow:r@rA}rB(jYj=jZj;ubaubjC)rC}rD(jYUjZjjbj/~jdj`jf}rE(jGX-jk]jj]jh]ji]jn]ujpMjqhjr]rFj/)rG}rH(jYXq`Updating XDS2xx Firmware `__ jZjCjbj/~jdj2jf}rI(jh]ji]jj]jk]jn]ujpNjqhjr]rJj)rK}rL(jYXp`Updating XDS2xx Firmware `__rMjZjGjbj/~jdjjf}rN(jh]ji]jj]jk]jn]ujpMjr]rOj)rP}rQ(jYjMjf}rR(UnameXUpdating XDS2xx FirmwarejXQhttp://dev.ti.com/tirex/explore/node?node=AADzJ8Y-La4f7Bi5Ga0TcA__FUz-xrs__LATESTjk]jj]jh]ji]jn]ujZjKjr]rSj{XUpdating XDS2xx FirmwarerTrU}rV(jYUjZjPubajdjubaubaubaubj)rW}rX(jYXnFor newer versions of CCS, a XDS200 firmware update is recommended which user can perform using instruction onrYjZjjbj/~jdjjf}rZ(jh]ji]jj]jk]jn]ujpNjqhjr]r[j)r\}r](jYjYjZjWjbj/~jdjjf}r^(jh]ji]jj]jk]jn]ujpMjr]r_j{XnFor newer versions of CCS, a XDS200 firmware update is recommended which user can perform using instruction onr`ra}rb(jYjYjZj\ubaubaubj)rc}rd(jYXw`Updating\_the\_XDS200\_firmware __`rejZjjbj/~jdjjf}rf(jh]ji]jj]jk]jn]ujpMjqhjr]rgcdocutils.nodes title_reference rh)ri}rj(jYXw`Updating\_the\_XDS200\_firmware __`jf}rk(jh]ji]jj]jk]jn]ujZjcjr]rlj{XrUpdating_the_XDS200_firmware __rmrn}ro(jYUjZjiubajdUtitle_referencerpubaubj)rq}rr(jYX+**Step 2:** Create CCS Target configurationrsjZjjbj/~jdjjf}rt(jh]ji]jj]jk]jn]ujpMjqhjr]ru(j)rv}rw(jYX **Step 2:**jf}rx(jh]ji]jj]jk]jn]ujZjqjr]ryj{XStep 2:rzr{}r|(jYUjZjvubajdjubj{X Create CCS Target configurationr}r~}r(jYX Create CCS Target configurationjZjqubeubj)r}r(jYXVLaunch CCS on your host machine. Select View Tab and select the "Target configuration"rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{XVLaunch CCS on your host machine. Select View Tab and select the "Target configuration"rr}r(jYjjZjubaubjB)r}r(jYX0.. image:: ../../../images/New_TargetConfig.png jZjjbj/~jdjEjf}r(UuriX)rtos/../../../images/New_TargetConfig.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpMjqhjr]ubjZ)r}r(jYUjZjjbj/~jdj]jf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj`)r}r(jYUjcKjZjjbj/~jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r}r(jYXCreate New Target configuration in CCS by selecting appropriate emulator. For Default on board emulator select "Texas instruments XDS2xx Debug Probe" and select the target device as 66AK2H12.rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{XCreate New Target configuration in CCS by selecting appropriate emulator. For Default on board emulator select "Texas instruments XDS2xx Debug Probe" and select the target device as 66AK2H12.rr}r(jYjjZjubaubjB)r}r(jYX0.. image:: ../../../images/K2H_TargetConfig.png jZjjbj/~jdjEjf}r(UuriX)rtos/../../../images/K2H_TargetConfig.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpMjqhjr]ubj)r}r(jYX}Go to the Advanced Tab where you will see all the cores on the SOC listed. In order to initialize the clocks and external DDR memory on the device, users are required to use a initialization Gel scripts. To populate the Gel Select A15\_0 and then hit Browse and locate the GEL in the CCS installation under the following path: CCS\_INSTALL/ccs\_base/emulation/boards/xtcievmk2x/geljZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{XzGo to the Advanced Tab where you will see all the cores on the SOC listed. In order to initialize the clocks and external DDR memory on the device, users are required to use a initialization Gel scripts. To populate the Gel Select A15_0 and then hit Browse and locate the GEL in the CCS installation under the following path: CCS_INSTALL/ccs_base/emulation/boards/xtcievmk2x/gelrr}r(jYX}Go to the Advanced Tab where you will see all the cores on the SOC listed. In order to initialize the clocks and external DDR memory on the device, users are required to use a initialization Gel scripts. To populate the Gel Select A15\_0 and then hit Browse and locate the GEL in the CCS installation under the following path: CCS\_INSTALL/ccs\_base/emulation/boards/xtcievmk2x/geljZjubaubjB)r}r(jYX'.. image:: ../../../images/ARM_GEL.png jZjjbj/~jdjEjf}r(UuriX rtos/../../../images/ARM_GEL.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpMjqhjr]ubj)r}r(jYXiDSP developers, can also select C66x\_0 and populate the DSP GEL file that is found in the same location.jZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{XhDSP developers, can also select C66x_0 and populate the DSP GEL file that is found in the same location.rr}r(jYXiDSP developers, can also select C66x\_0 and populate the DSP GEL file that is found in the same location.jZjubaubjB)r}r(jYX'.. image:: ../../../images/DSP_GEL.png jZjjbj/~jdjEjf}r(UuriX rtos/../../../images/DSP_GEL.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpMjqhjr]ubj)r}r(jYXoGoing back to the Basic Tab, Save the configuration. For additional sanity check, you can also test connection.rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{XoGoing back to the Basic Tab, Save the configuration. For additional sanity check, you can also test connection.rr}r(jYjjZjubaubjZ)r}rŒ(jYUjZjjbj/~jdj]jf}rÌ(jh]ji]jj]jk]jn]ujpMjqhjr]rČj`)rŌ}rƌ(jYUjcKjZjjbj/~jdjpjf}rnj(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)rȌ}rɌ(jYX **Step 3:** Connect to the coresrʌjZjjbj/~jdjjf}rˌ(jh]ji]jj]jk]jn]ujpMjqhjr]ř(j)r͌}rΌ(jYX **Step 3:**jf}rό(jh]ji]jj]jk]jn]ujZjȌjr]rЌj{XStep 3:rьrҌ}rӌ(jYUjZj͌ubajdjubj{X Connect to the coresrԌrՌ}r֌(jYX Connect to the coresjZjȌubeubj)r׌}r،(jYXRight click on the target configuration and Select "Launch Target configuration". Wait for CCS debug View to launch and display the eight C66x cores and 4 A15 cores.rٌjZjjbj/~jdjjf}rڌ(jh]ji]jj]jk]jn]ujpMjqhjr]rیj{XRight click on the target configuration and Select "Launch Target configuration". Wait for CCS debug View to launch and display the eight C66x cores and 4 A15 cores.r܌r݌}rތ(jYjٌjZj׌ubaubjB)rߌ}r(jYX3.. image:: ../../../images/Launch_TargetConfig.png jZjjbj/~jdjEjf}r(UuriX,rtos/../../../images/Launch_TargetConfig.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpM"jqhjr]ubjB)r}r(jYX+.. image:: ../../../images/Connect_A15.png jZjjbj/~jdjEjf}r(UuriX$rtos/../../../images/Connect_A15.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpM$jqhjr]ubj)r}r(jYXStart by connecting to A15\_0 and C66x\_0. when you connect to the cores, you will see the GEL script logs in the console window, which indicates that device clocks, PSC and external DDR memory has been initialized. The GEL log from target connect is provided below for reference.jZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpM%jqhjr]rj{XStart by connecting to A15_0 and C66x_0. when you connect to the cores, you will see the GEL script logs in the console window, which indicates that device clocks, PSC and external DDR memory has been initialized. The GEL log from target connect is provided below for reference.rr}r(jYXStart by connecting to A15\_0 and C66x\_0. when you connect to the cores, you will see the GEL script logs in the console window, which indicates that device clocks, PSC and external DDR memory has been initialized. The GEL log from target connect is provided below for reference.jZjubaubj)r}r(jYX]arm_A15_0: GEL Output: Disabling MMU arm_A15_0: GEL Output: Disabling Caches arm_A15_0: GEL Output: Invalidate Instruction Caches arm_A15_0: GEL Output: Enabling non-secure access to cp10 and cp11 arm_A15_0: GEL Output: Enabled non-secure access to cp10 and cp11 arm_A15_0: GEL Output: Enabling SMP bit in ACTLR arm_A15_0: GEL Output: Enabled SMP bit in ACTLR arm_A15_0: GEL Output: Entering NonSecure Mode arm_A15_0: GEL Output: Entered NonSecure Mode arm_A15_0: GEL Output: Disabling MMU arm_A15_0: GEL Output: Disabling Caches arm_A15_0: GEL Output: Invalidate Instruction Caches arm_A15_0: GEL Output:jZjjbj/~jdjjf}r(jjjk]jj]jh]ji]jn]ujpMt$jqhjr]rj{X]arm_A15_0: GEL Output: Disabling MMU arm_A15_0: GEL Output: Disabling Caches arm_A15_0: GEL Output: Invalidate Instruction Caches arm_A15_0: GEL Output: Enabling non-secure access to cp10 and cp11 arm_A15_0: GEL Output: Enabled non-secure access to cp10 and cp11 arm_A15_0: GEL Output: Enabling SMP bit in ACTLR arm_A15_0: GEL Output: Enabled SMP bit in ACTLR arm_A15_0: GEL Output: Entering NonSecure Mode arm_A15_0: GEL Output: Entered NonSecure Mode arm_A15_0: GEL Output: Disabling MMU arm_A15_0: GEL Output: Disabling Caches arm_A15_0: GEL Output: Invalidate Instruction Caches arm_A15_0: GEL Output:rr}r(jYUjZjubaubj)r}r(jYXConnecting Target...rjZjjbj/~jdjjf}r(jh]ji]jj]jk]jn]ujpM;jqhjr]rj{XConnecting Target...rr}r(jYjjZjubaubj)r}r(jYXarm_A15_0: GEL Output: Disabling MMU arm_A15_0: GEL Output: Disabling Caches arm_A15_0: GEL Output: Invalidate Instruction Caches arm_A15_0: GEL Output: Enabling non-secure access to cp10 and cp11 arm_A15_0: GEL Output: Enabled non-secure access to cp10 and cp11 arm_A15_0: GEL Output: Enabling SMP bit in ACTLR arm_A15_0: GEL Output: Enabled SMP bit in ACTLR arm_A15_0: GEL Output: Entering NonSecure Mode arm_A15_0: GEL Output: Entered NonSecure Mode arm_A15_0: GEL Output: Disabling MMU arm_A15_0: GEL Output: Disabling Caches arm_A15_0: GEL Output: Invalidate Instruction Caches arm_A15_0: GEL Output: TCI6638K2K GEL file Ver is 1.89999998 arm_A15_0: GEL Output: Disabling MMU arm_A15_0: GEL Output: Disabling Caches arm_A15_0: GEL Output: Invalidate Instruction Caches arm_A15_0: GEL Output: Enabling non-secure access to cp10 and cp11 arm_A15_0: GEL Output: Enabled non-secure access to cp10 and cp11 arm_A15_0: GEL Output: Enabling SMP bit in ACTLR arm_A15_0: GEL Output: Enabled SMP bit in ACTLR arm_A15_0: GEL Output: Entering NonSecure Mode arm_A15_0: GEL Output: Entered NonSecure Mode arm_A15_0: GEL Output: Disabling MMU arm_A15_0: GEL Output: Disabling Caches arm_A15_0: GEL Output: Invalidate Instruction Caches arm_A15_0: GEL Output: Detected PLL bypass disabled: SECCTL[BYPASS] = 0x00000000 arm_A15_0: GEL Output: (3a) PLLCTL = 0x00000040 arm_A15_0: GEL Output: (3b) PLLCTL = 0x00000040 arm_A15_0: GEL Output: (3c) Delay... arm_A15_0: GEL Output: (4)PLLM[PLLM] = 0x0000000F arm_A15_0: GEL Output: MAINPLLCTL0 = 0x07000000 arm_A15_0: GEL Output: (5) MAINPLLCTL0 = 0x07000000 arm_A15_0: GEL Output: (5) MAINPLLCTL1 = 0x00000040 arm_A15_0: GEL Output: (6) MAINPLLCTL0 = 0x07000000 arm_A15_0: GEL Output: (7) SECCTL = 0x00090000 arm_A15_0: GEL Output: (8a) Delay... arm_A15_0: GEL Output: PLL1_DIV3 = 0x00008002 arm_A15_0: GEL Output: PLL1_DIV4 = 0x00008004 arm_A15_0: GEL Output: PLL1_DIV7 = 0x00000000 arm_A15_0: GEL Output: (8d/e) Delay... arm_A15_0: GEL Output: (10) Delay... arm_A15_0: GEL Output: (12) Delay... arm_A15_0: GEL Output: (13) SECCTL = 0x00090000 arm_A15_0: GEL Output: (Delay... arm_A15_0: GEL Output: (Delay... arm_A15_0: GEL Output: (14) PLLCTL = 0x00000041 arm_A15_0: GEL Output: PLL has been configured (CLKIN * PLLM / PLLD / PLLOD = PLLOUT): arm_A15_0: GEL Output: PLL has been configured (122.879997 MHz * 16 / 1 / 2 = 983.039978 MHz) arm_A15_0: GEL Output: Switching on ARM Core 0 arm_A15_0: GEL Output: Switching on ARM Core 1 arm_A15_0: GEL Output: Switching on ARM Core 2 arm_A15_0: GEL Output: Switching on ARM Core 3 arm_A15_0: GEL Output: ARM PLL has been configured (125.0 MHz * 16 / 2 = 1000.0 MHz) arm_A15_0: GEL Output: DISABLESTAT ---> 0x00000000 arm_A15_0: GEL Output: Power on all PSC modules and DSP domains... arm_A15_0: GEL Output: Power on all PSC modules and DSP domains... Done. arm_A15_0: GEL Output: WARNING: SYSCLK is the input to the PA PLL. arm_A15_0: GEL Output: Completed PA PLL Setup arm_A15_0: GEL Output: PAPLLCTL0 - before: 0x0x09080500 after: 0x0x09080500 arm_A15_0: GEL Output: PAPLLCTL1 - before: 0x0x00002040 after: 0x0x00002040 arm_A15_0: GEL Output: DDR begin arm_A15_0: GEL Output: XMC setup complete. arm_A15_0: GEL Output: DDR3 PLL (PLL2) Setup ... arm_A15_0: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 666 MHz. arm_A15_0: GEL Output: DDR3A initialization complete arm_A15_0: GEL Output: DDR3 PLL Setup ... arm_A15_0: GEL Output: DDR3 PLL Setup complete, DDR3B clock now running at 800MHz. arm_A15_0: GEL Output: DDR3B initialization complete arm_A15_0: GEL Output: DDR done arm_A15_0: GEL Output: Entering A15 non secure mode .. arm_A15_0: GEL Output: Disabling MMU arm_A15_0: GEL Output: Disabling Caches arm_A15_0: GEL Output: Invalidate Instruction Caches arm_A15_0: GEL Output: Enabling non-secure access to cp10 and cp11 arm_A15_0: GEL Output: Enabled non-secure access to cp10 and cp11 arm_A15_0: GEL Output: Enabling SMP bit in ACTLR arm_A15_0: GEL Output: Enabled SMP bit in ACTLR arm_A15_0: GEL Output: Entering NonSecure Mode arm_A15_0: GEL Output: Entered NonSecure Mode arm_A15_0: GEL Output: Disabling MMU arm_A15_0: GEL Output: Disabling Caches arm_A15_0: GEL Output: Invalidate Instruction Caches arm_A15_0: GEL Output: A15 non secure mode enteredjZjjbj/~jdjjf}r(jjjk]jj]jh]ji]jn]ujpM$jqhjr]rj{Xarm_A15_0: GEL Output: Disabling MMU arm_A15_0: GEL Output: Disabling Caches arm_A15_0: GEL Output: Invalidate Instruction Caches arm_A15_0: GEL Output: Enabling non-secure access to cp10 and cp11 arm_A15_0: GEL Output: Enabled non-secure access to cp10 and cp11 arm_A15_0: GEL Output: Enabling SMP bit in ACTLR arm_A15_0: GEL Output: Enabled SMP bit in ACTLR arm_A15_0: GEL Output: Entering NonSecure Mode arm_A15_0: GEL Output: Entered NonSecure Mode arm_A15_0: GEL Output: Disabling MMU arm_A15_0: GEL Output: Disabling Caches arm_A15_0: GEL Output: Invalidate Instruction Caches arm_A15_0: GEL Output: TCI6638K2K GEL file Ver is 1.89999998 arm_A15_0: GEL Output: Disabling MMU arm_A15_0: GEL Output: Disabling Caches arm_A15_0: GEL Output: Invalidate Instruction Caches arm_A15_0: GEL Output: Enabling non-secure access to cp10 and cp11 arm_A15_0: GEL Output: Enabled non-secure access to cp10 and cp11 arm_A15_0: GEL Output: Enabling SMP bit in ACTLR arm_A15_0: GEL Output: Enabled SMP bit in ACTLR arm_A15_0: GEL Output: Entering NonSecure Mode arm_A15_0: GEL Output: Entered NonSecure Mode arm_A15_0: GEL Output: Disabling MMU arm_A15_0: GEL Output: Disabling Caches arm_A15_0: GEL Output: Invalidate Instruction Caches arm_A15_0: GEL Output: Detected PLL bypass disabled: SECCTL[BYPASS] = 0x00000000 arm_A15_0: GEL Output: (3a) PLLCTL = 0x00000040 arm_A15_0: GEL Output: (3b) PLLCTL = 0x00000040 arm_A15_0: GEL Output: (3c) Delay... arm_A15_0: GEL Output: (4)PLLM[PLLM] = 0x0000000F arm_A15_0: GEL Output: MAINPLLCTL0 = 0x07000000 arm_A15_0: GEL Output: (5) MAINPLLCTL0 = 0x07000000 arm_A15_0: GEL Output: (5) MAINPLLCTL1 = 0x00000040 arm_A15_0: GEL Output: (6) MAINPLLCTL0 = 0x07000000 arm_A15_0: GEL Output: (7) SECCTL = 0x00090000 arm_A15_0: GEL Output: (8a) Delay... arm_A15_0: GEL Output: PLL1_DIV3 = 0x00008002 arm_A15_0: GEL Output: PLL1_DIV4 = 0x00008004 arm_A15_0: GEL Output: PLL1_DIV7 = 0x00000000 arm_A15_0: GEL Output: (8d/e) Delay... arm_A15_0: GEL Output: (10) Delay... arm_A15_0: GEL Output: (12) Delay... arm_A15_0: GEL Output: (13) SECCTL = 0x00090000 arm_A15_0: GEL Output: (Delay... arm_A15_0: GEL Output: (Delay... arm_A15_0: GEL Output: (14) PLLCTL = 0x00000041 arm_A15_0: GEL Output: PLL has been configured (CLKIN * PLLM / PLLD / PLLOD = PLLOUT): arm_A15_0: GEL Output: PLL has been configured (122.879997 MHz * 16 / 1 / 2 = 983.039978 MHz) arm_A15_0: GEL Output: Switching on ARM Core 0 arm_A15_0: GEL Output: Switching on ARM Core 1 arm_A15_0: GEL Output: Switching on ARM Core 2 arm_A15_0: GEL Output: Switching on ARM Core 3 arm_A15_0: GEL Output: ARM PLL has been configured (125.0 MHz * 16 / 2 = 1000.0 MHz) arm_A15_0: GEL Output: DISABLESTAT ---> 0x00000000 arm_A15_0: GEL Output: Power on all PSC modules and DSP domains... arm_A15_0: GEL Output: Power on all PSC modules and DSP domains... Done. arm_A15_0: GEL Output: WARNING: SYSCLK is the input to the PA PLL. arm_A15_0: GEL Output: Completed PA PLL Setup arm_A15_0: GEL Output: PAPLLCTL0 - before: 0x0x09080500 after: 0x0x09080500 arm_A15_0: GEL Output: PAPLLCTL1 - before: 0x0x00002040 after: 0x0x00002040 arm_A15_0: GEL Output: DDR begin arm_A15_0: GEL Output: XMC setup complete. arm_A15_0: GEL Output: DDR3 PLL (PLL2) Setup ... arm_A15_0: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 666 MHz. arm_A15_0: GEL Output: DDR3A initialization complete arm_A15_0: GEL Output: DDR3 PLL Setup ... arm_A15_0: GEL Output: DDR3 PLL Setup complete, DDR3B clock now running at 800MHz. arm_A15_0: GEL Output: DDR3B initialization complete arm_A15_0: GEL Output: DDR done arm_A15_0: GEL Output: Entering A15 non secure mode .. arm_A15_0: GEL Output: Disabling MMU arm_A15_0: GEL Output: Disabling Caches arm_A15_0: GEL Output: Invalidate Instruction Caches arm_A15_0: GEL Output: Enabling non-secure access to cp10 and cp11 arm_A15_0: GEL Output: Enabled non-secure access to cp10 and cp11 arm_A15_0: GEL Output: Enabling SMP bit in ACTLR arm_A15_0: GEL Output: Enabled SMP bit in ACTLR arm_A15_0: GEL Output: Entering NonSecure Mode arm_A15_0: GEL Output: Entered NonSecure Mode arm_A15_0: GEL Output: Disabling MMU arm_A15_0: GEL Output: Disabling Caches arm_A15_0: GEL Output: Invalidate Instruction Caches arm_A15_0: GEL Output: A15 non secure mode enteredrr}r(jYUjZjubaubj)r}r(jYX^Users can now load and run code on the cores by using Run -> Load Program. Happy Debugging !!rjZjjbj/~jdjjf}r (jh]ji]jj]jk]jn]ujpMjqhjr]r j{X^Users can now load and run code on the cores by using Run -> Load Program. Happy Debugging !!r r }r (jYjjZjubaubj)r}r(jYXTMDSEVM6657L EVM Hardware SetupjZjjbjcjdjjf}r(jjjk]jj]jh]ji]jn]ujpKjqhjr]rj{XTMDSEVM6657L EVM Hardware Setuprr}r(jYUjZjubaubj)r}r(jYX4====================================================jZjjbjcjdjjf}r(jjjk]jj]jh]ji]jn]ujpKjqhjr]rj{X4====================================================rr}r(jYUjZjubaubeubeubj[)r}r(jYUjZjR\jbjXHsource/common/EVM_Hardware_Setup/TMDSEVM6657L_EVM_Hardware_Setup.rst.incrr}r bjdjejf}r!(jh]ji]jj]jk]r"U%tmdsevm6657l-evm-hardware-setup-guider#ajn]r$haujpKjqhjr]r%(jt)r&}r'(jYX%TMDSEVM6657L EVM Hardware Setup Guider(jZjjbjjdjxjf}r)(jh]ji]jj]jk]jn]ujpKjqhjr]r*j{X%TMDSEVM6657L EVM Hardware Setup Guider+r,}r-(jYj(jZj&ubaubj)r.}r/(jYXThis page will walk you through setting up your `TMDSEVM6657L `__ Evaluation Module (EVM). These guidelines also apply to the L and LE EVM models.jZjjbjjdjjf}r0(jh]ji]jj]jk]jn]ujpKjqhjr]r1(j{X0This page will walk you through setting up your r2r3}r4(jYX0This page will walk you through setting up your jZj.ubj)r5}r6(jYX5`TMDSEVM6657L `__jf}r7(UnameX TMDSEVM6657LjX"http://www.ti.com/tool/TMDSEVM6657jk]jj]jh]ji]jn]ujZj.jr]r8j{X TMDSEVM6657Lr9r:}r;(jYUjZj5ubajdjubj{XQ Evaluation Module (EVM). These guidelines also apply to the L and LE EVM models.r<r=}r>(jYXQ Evaluation Module (EVM). These guidelines also apply to the L and LE EVM models.jZj.ubeubj)r?}r@(jYXcSome of the steps in this section have been updated from those used in the EVM *Quick Start Guide*.rAjZjjbjjdjjf}rB(jh]ji]jj]jk]jn]ujpNjqhjr]rCj)rD}rE(jYjAjZj?jbjjdjjf}rF(jh]ji]jj]jk]jn]ujpK jr]rG(j{XOSome of the steps in this section have been updated from those used in the EVM rHrI}rJ(jYXOSome of the steps in this section have been updated from those used in the EVM jZjDubj')rK}rL(jYX*Quick Start Guide*jf}rM(jh]ji]jj]jk]jn]ujZjDjr]rNj{XQuick Start GuiderOrP}rQ(jYUjZjKubajdj'ubj{X.rR}rS(jYX.jZjDubeubaubj[)rT}rU(jYUjKjZjjbjjdjejf}rV(jh]rWXhardware setup overviewrXaji]jj]jk]rYUhardware-setup-overviewrZajn]ujpKjqhjr]r[(jt)r\}r](jYXHardware Setup Overviewr^jZjTjbjjdjxjf}r_(jh]ji]jj]jk]jn]ujpKjqhjr]r`j{XHardware Setup Overviewrarb}rc(jYj^jZj\ubaubj)rd}re(jYXcThe picture below shows the TMDXEVM6657L EVM and the locations of relevant switches and connectors.rfjZjTjbjjdjjf}rg(jh]ji]jj]jk]jn]ujpKjqhjr]rhj{XcThe picture below shows the TMDXEVM6657L EVM and the locations of relevant switches and connectors.rirj}rk(jYjfjZjdubaubjB)rl}rm(jYX-.. image:: ../images/TMDSEVM6657L-image.jpg jZjTjbjjdjEjf}rn(UuriX%rtos/../images/TMDSEVM6657L-image.jpgrojk]jj]jh]ji]jH}rpU*josjn]ujpKjqhjr]ubeubj[)rq}rr(jYUjKjZjjbjjdjejf}rs(jh]rtXhardware setup stepsruaji]jj]jk]rvUhardware-setup-stepsrwajn]ujpKjqhjr]rx(jt)ry}rz(jYXHardware Setup Stepsr{jZjqjbjjdjxjf}r|(jh]ji]jj]jk]jn]ujpKjqhjr]r}j{XHardware Setup Stepsr~r}r(jYj{jZjyubaubj)r}r(jYXThe EVM board is sensitive to electrostatic discharges (ESD). Use a grounding strap or other device to prevent damaging the board. Be sure to connect communication cables before applying power to any equipment.rjZjqjbjjdjjf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XThe EVM board is sensitive to electrostatic discharges (ESD). Use a grounding strap or other device to prevent damaging the board. Be sure to connect communication cables before applying power to any equipment.rr}r(jYjjZjubaubaubjZ)r}r(jYUjZjqjbjjdj]jf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj`)r}r(jYUjcKjZjjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r}r(jYX**1. Attach the Ethernet cable** Using the Ethernet cable supplied, connect one end of the cable to the Ethernet port on the EVM and the other end to your PC.jZjqjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r(j)r}r(jYX **1. Attach the Ethernet cable**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X1. Attach the Ethernet cablerr}r(jYUjZjubajdjubj{X~ Using the Ethernet cable supplied, connect one end of the cable to the Ethernet port on the EVM and the other end to your PC.rr}r(jYX~ Using the Ethernet cable supplied, connect one end of the cable to the Ethernet port on the EVM and the other end to your PC.jZjubeubj)r}r(jYX'**2. Connect the JTAG interface** Use the USB to USB mini-B cable provided. Connect the USB mini-B connector to the USB mini-B interface on the EVM and the USB connector to your PC. This enables XDS-100 emulation and is directly useable by CCS. If you are using a different JTAG, connect it now.jZjqjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK!jqhjr]r(j)r}r(jYX!**2. Connect the JTAG interface**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X2. Connect the JTAG interfacerr}r(jYUjZjubajdjubj{X Use the USB to USB mini-B cable provided. Connect the USB mini-B connector to the USB mini-B interface on the EVM and the USB connector to your PC. This enables XDS-100 emulation and is directly useable by CCS. If you are using a different JTAG, connect it now.rr}r(jYX Use the USB to USB mini-B cable provided. Connect the USB mini-B connector to the USB mini-B interface on the EVM and the USB connector to your PC. This enables XDS-100 emulation and is directly useable by CCS. If you are using a different JTAG, connect it now.jZjubeubj)r}r(jYX**3. Verify Endian mode in the SW3 settings** The Endian mode should be set to Little Endian. SW3 also contains the boot device settings.jZjqjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK'jqhjr]r(j)r}r(jYX-**3. Verify Endian mode in the SW3 settings**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X)3. Verify Endian mode in the SW3 settingsrr}r(jYUjZjubajdjubj{X\ The Endian mode should be set to Little Endian. SW3 also contains the boot device settings.rr}r(jYX\ The Endian mode should be set to Little Endian. SW3 also contains the boot device settings.jZjubeubjB)r}r(jYX4.. image:: ../images/TMD6657LSW3.png :scale: 60% jZjqjbjjdjEjf}r(UscaleK(jh]ji]jj]jk]jn]ujpKUjqhjr]r?j)r@}rA(jYj=jf}rB(jh]ji]jj]jk]jn]ujZj;jr]rCj{X7. Connect the power cablerDrE}rF(jYUjZj@ubajdjubaubj)rG}rH(jYXConnect the power cable to the EVM power jack on the board. To be ESD safe, plug in the other end of the power cable only after you have connected the power cord to the board. Then turn on the board.rIjZjqjbjjdjjf}rJ(jh]ji]jj]jk]jn]ujpKWjqhjr]rKj{XConnect the power cable to the EVM power jack on the board. To be ESD safe, plug in the other end of the power cable only after you have connected the power cord to the board. Then turn on the board.rLrM}rN(jYjIjZjGubaubjZ)rO}rP(jYUjZjqjbjjdj]jf}rQ(jh]ji]jj]jk]jn]ujpK[jqhjr]rRj`)rS}rT(jYUjcKjZjOjbjjdjpjf}rU(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubj[)rV}rW(jYUjKjZjjbjjdjejf}rX(jh]rYXboot mode dip switch settingsrZaji]jj]jk]r[Uboot-mode-dip-switch-settingsr\ajn]ujpK^jqhjr]r](jt)r^}r_(jYXBoot Mode Dip Switch Settingsr`jZjVjbjjdjxjf}ra(jh]ji]jj]jk]jn]ujpK^jqhjr]rbj{XBoot Mode Dip Switch Settingsrcrd}re(jYj`jZj^ubaubj)rf}rg(jYXmThe EVM supports booting image from various devices (EEPROM, NAND or NOR) via IBL (at I2C address 0x51), I2C EEPROM (at I2C address 0x50), and ROM Boot modes (such as Ethernet, SRIO, PCIe, SPI etc.) which address the boot source directly from the ROM code. Below is the table showing the boot mode dip switch settings for different boot mode that the EVM supports:rhjZjVjbjjdjjf}ri(jh]ji]jj]jk]jn]ujpK`jqhjr]rjj{XmThe EVM supports booting image from various devices (EEPROM, NAND or NOR) via IBL (at I2C address 0x51), I2C EEPROM (at I2C address 0x50), and ROM Boot modes (such as Ethernet, SRIO, PCIe, SPI etc.) which address the boot source directly from the ROM code. Below is the table showing the boot mode dip switch settings for different boot mode that the EVM supports:rkrl}rm(jYjhjZjfubaubjd$)rn}ro(jYUjZjVjbjjdjg$jf}rp(jh]ji]jj]jk]jn]ujpNjqhjr]rqjj$)rr}rs(jYUjf}rt(jk]jj]jh]ji]jn]UcolsKujZjnjr]ru(jo$)rv}rw(jYUjf}rx(jk]jj]jh]ji]jn]UcolwidthKujZjrjr]jdjs$ubjo$)ry}rz(jYUjf}r{(jk]jj]jh]ji]jn]UcolwidthKujZjrjr]jdjs$ubjo$)r|}r}(jYUjf}r~(jk]jj]jh]ji]jn]UcolwidthKujZjrjr]jdjs$ubjz$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjrjr]rj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX Boot ModerjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKhjr]rj{X Boot Moderr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j)r}r(jYXDIP SW3rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKhjr]rj{XDIP SW3rr}r(jYjjZjubaubj)r}r(jYX(Pin1, 2, 3, 4, 5, 6, 7, 8)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjjr]rj{X(Pin1, 2, 3, 4, 5, 6, 7, 8)rr}r(jYjjZjubaubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j)r}r(jYXDIP SW5rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKhjr]rj{XDIP SW5rr}r(jYjjZjubaubj)r}r(jYX(Pin1, 2, 3, 4, 5, 6, 7, 8)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjjr]rj{X(Pin1, 2, 3, 4, 5, 6, 7, 8)rr}r(jYjjZjubaubejdj$ubejdj$ubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjrjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rŽ(j$)rÎ}rĎ(jYUjf}rŎ(jh]ji]jj]jk]jn]ujZjjr]rƎj)rǎ}rȎ(jYX"IBL NOR boot on image 0 (default)rɎjZjÎjbjjdjjf}rʎ(jh]ji]jj]jk]jn]ujpKmjr]rˎj{X"IBL NOR boot on image 0 (default)r̎r͎}rΎ(jYjɎjZjǎubaubajdj$ubj$)rώ}rЎ(jYUjf}rю(jh]ji]jj]jk]jn]ujZjjr]rҎj)rӎ}rԎ(jYX1(off, off, on, off, on, on, on, on)\ :sup:`1,2,3`jZjώjbjjdjjf}rՎ(jh]ji]jj]jk]jn]ujpKmjr]r֎(j{X#(off, off, on, off, on, on, on, on)r׎r؎}rَ(jYX%(off, off, on, off, on, on, on, on)\ jZjӎubj)rڎ}rێ(jYX :sup:`1,2,3`jf}r܎(jh]ji]jj]jk]jn]ujZjӎjr]rݎj{X1,2,3rގrߎ}r(jYUjZjڎubajdjubeubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX+(on, on, on, off, on, on, on, on)\ :sup:`4`jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKmjr]r(j{X!(on, on, on, off, on, on, on, on)rr}r(jYX#(on, on, on, off, on, on, on, on)\ jZjubj)r}r(jYX:sup:`4`jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X4r}r(jYUjZjubajdjubeubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXIBL NAND boot on image 0rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKqjr]rj{XIBL NAND boot on image 0rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX$(off, off, on, off, on, off, on, on)rjZjjbjjdjjf}r (jh]ji]jj]jk]jn]ujpKqjr]r j{X$(off, off, on, off, on, off, on, on)r r }r (jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX!(on, on, on, off, on, on, on, on)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKqjr]rj{X!(on, on, on, off, on, on, on, on)rr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r (jh]ji]jj]jk]jn]ujZjjr]r!j)r"}r#(jYXIBL NAND boot on image 1r$jZjjbjjdjjf}r%(jh]ji]jj]jk]jn]ujpKtjr]r&j{XIBL NAND boot on image 1r'r(}r)(jYj$jZj"ubaubajdj$ubj$)r*}r+(jYUjf}r,(jh]ji]jj]jk]jn]ujZjjr]r-j)r.}r/(jYX%(off, off, on, off, off, off, on, on)r0jZj*jbjjdjjf}r1(jh]ji]jj]jk]jn]ujpKtjr]r2j{X%(off, off, on, off, off, off, on, on)r3r4}r5(jYj0jZj.ubaubajdj$ubj$)r6}r7(jYUjf}r8(jh]ji]jj]jk]jn]ujZjjr]r9j)r:}r;(jYX!(on, on, on, off, on, on, on, on)r<jZj6jbjjdjjf}r=(jh]ji]jj]jk]jn]ujpKtjr]r>j{X!(on, on, on, off, on, on, on, on)r?r@}rA(jYj<jZj:ubaubajdj$ubejdj$ubj$)rB}rC(jYUjf}rD(jh]ji]jj]jk]jn]ujZjjr]rE(j$)rF}rG(jYUjf}rH(jh]ji]jj]jk]jn]ujZjBjr]rIj)rJ}rK(jYX IBL TFTP bootrLjZjFjbjjdjjf}rM(jh]ji]jj]jk]jn]ujpKwjr]rNj{X IBL TFTP bootrOrP}rQ(jYjLjZjJubaubajdj$ubj$)rR}rS(jYUjf}rT(jh]ji]jj]jk]jn]ujZjBjr]rUj)rV}rW(jYX$(off, off, on, off, on, on, off, on)rXjZjRjbjjdjjf}rY(jh]ji]jj]jk]jn]ujpKwjr]rZj{X$(off, off, on, off, on, on, off, on)r[r\}r](jYjXjZjVubaubajdj$ubj$)r^}r_(jYUjf}r`(jh]ji]jj]jk]jn]ujZjBjr]raj)rb}rc(jYX!(on, on, on, off, on, on, on, on)rdjZj^jbjjdjjf}re(jh]ji]jj]jk]jn]ujpKwjr]rfj{X!(on, on, on, off, on, on, on, on)rgrh}ri(jYjdjZjbubaubajdj$ubejdj$ubj$)rj}rk(jYUjf}rl(jh]ji]jj]jk]jn]ujZjjr]rm(j$)rn}ro(jYUjf}rp(jh]ji]jj]jk]jn]ujZjjjr]rqj)rr}rs(jYX I2C POST bootrtjZjnjbjjdjjf}ru(jh]ji]jj]jk]jn]ujpKzjr]rvj{X I2C POST bootrwrx}ry(jYjtjZjrubaubajdj$ubj$)rz}r{(jYUjf}r|(jh]ji]jj]jk]jn]ujZjjjr]r}j)r~}r(jYX#(off, off, on, off, on, on, on, on)rjZjzjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKzjr]rj{X#(off, off, on, off, on, on, on, on)rr}r(jYjjZj~ubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjjr]rj)r}r(jYX (on, on, on, on, on, on, on, on)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKzjr]rj{X (on, on, on, on, on, on, on, on)rr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXROM SPI Boot\ :sup:`8`jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK}jr]r(j{X ROM SPI Bootrr}r(jYXROM SPI Boot\ jZjubj)r}r(jYX:sup:`8`jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X8r}r(jYUjZjubajdjubeubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX#(off, on, off, off, on, on, on, on)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK}jr]rj{X#(off, on, off, off, on, on, on, on)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX!(on, on, off, on, on, on, on, on)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK}jr]rj{X!(on, on, off, on, on, on, on, on)rr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)rÏ}rď(jYUjf}rŏ(jh]ji]jj]jk]jn]ujZjjr]rƏj)rǏ}rȏ(jYXROM SRIO Boot\ :sup:`5`jZjÏjbjjdjjf}rɏ(jh]ji]jj]jk]jn]ujpKjr]rʏ(j{X ROM SRIO Bootrˏȑ}r͏(jYXROM SRIO Boot\ jZjǏubj)rΏ}rϏ(jYX:sup:`5`jf}rЏ(jh]ji]jj]jk]jn]ujZjǏjr]rяj{X5rҏ}rӏ(jYUjZjΏubajdjubeubajdj$ubj$)rԏ}rՏ(jYUjf}r֏(jh]ji]jj]jk]jn]ujZjjr]r׏j)r؏}rُ(jYX#(off, off, on, on, on, on, off, on)rڏjZjԏjbjjdjjf}rۏ(jh]ji]jj]jk]jn]ujpKjr]r܏j{X#(off, off, on, on, on, on, off, on)rݏrޏ}rߏ(jYjڏjZj؏ubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX#(off, on, on, off, off, on, on, on)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X#(off, on, on, off, off, on, on, on)rr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXROM Ethernet Boot\ :sup:`6`jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]r(j{XROM Ethernet Bootrr}r(jYXROM Ethernet Boot\ jZjubj)r}r(jYX:sup:`6`jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X6r}r(jYUjZjubajdjubeubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX#(off, on, off, on, on, on, on, off)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]r j{X#(off, on, off, on, on, on, on, off)r r }r (jYjjZjubaubajdj$ubj$)r }r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX#(on, off, on, off, off, on, on, on)rjZj jbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X#(on, off, on, off, off, on, on, on)rr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r j)r!}r"(jYXROM PCIE Boot\ :sup:`7`jZjjbjjdjjf}r#(jh]ji]jj]jk]jn]ujpKjr]r$(j{X ROM PCIE Bootr%r&}r'(jYXROM PCIE Boot\ jZj!ubj)r(}r)(jYX:sup:`7`jf}r*(jh]ji]jj]jk]jn]ujZj!jr]r+j{X7r,}r-(jYUjZj(ubajdjubeubajdj$ubj$)r.}r/(jYUjf}r0(jh]ji]jj]jk]jn]ujZjjr]r1j)r2}r3(jYX"(off, on, on, off, on, on, on, on)r4jZj.jbjjdjjf}r5(jh]ji]jj]jk]jn]ujpKjr]r6j{X"(off, on, on, off, on, on, on, on)r7r8}r9(jYj4jZj2ubaubajdj$ubj$)r:}r;(jYUjf}r<(jh]ji]jj]jk]jn]ujZjjr]r=j)r>}r?(jYX"(on, on, on, off, off, on, on, on)r@jZj:jbjjdjjf}rA(jh]ji]jj]jk]jn]ujpKjr]rBj{X"(on, on, on, off, off, on, on, on)rCrD}rE(jYj@jZj>ubaubajdj$ubejdj$ubj$)rF}rG(jYUjf}rH(jh]ji]jj]jk]jn]ujZjjr]rI(j$)rJ}rK(jYUjf}rL(jh]ji]jj]jk]jn]ujZjFjr]rMj)rN}rO(jYXNo bootrPjZjJjbjjdjjf}rQ(jh]ji]jj]jk]jn]ujpKjr]rRj{XNo bootrSrT}rU(jYjPjZjNubaubajdj$ubj$)rV}rW(jYUjf}rX(jh]ji]jj]jk]jn]ujZjFjr]rYj)rZ}r[(jYX!(off, on, on, on, on, on, on, on)r\jZjVjbjjdjjf}r](jh]ji]jj]jk]jn]ujpKjr]r^j{X!(off, on, on, on, on, on, on, on)r_r`}ra(jYj\jZjZubaubajdj$ubj$)rb}rc(jYUjf}rd(jh]ji]jj]jk]jn]ujZjFjr]rej)rf}rg(jYX (on, on, on, on, on, on, on, on)rhjZjbjbjjdjjf}ri(jh]ji]jj]jk]jn]ujpKjr]rjj{X (on, on, on, on, on, on, on, on)rkrl}rm(jYjhjZjfubaubajdj$ubejdj$ubejdjy%ubejdjz%ubaubjZ)rn}ro(jYUjZjVjbjjdj]jf}rp(jh]ji]jj]jk]jn]ujpKjqhjr]rqj`)rr}rs(jYX@**Note:** C6657 currently does not support Image 1 for NOR boot.jcKjZjnjbjjdjpjf}rt(jh]ji]jj]jk]jn]ujpKjqhjr]ru(j)rv}rw(jYX **Note:**jf}rx(jh]ji]jj]jk]jn]ujZjrjr]ryj{XNote:rzr{}r|(jYUjZjvubajdjubj{X7 C6657 currently does not support Image 1 for NOR boot.r}r~}r(jYX7 C6657 currently does not support Image 1 for NOR boot.jZjrubeubaubjZ)r}r(jYUjZjVjbjjdj]jf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r(j`)r}r(jYUjcKjZjjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)r}r(jYUjcKjZjjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubeubj)r}r(jYX**Footnotes:**rjZjVjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X Footnotes:rr}r(jYUjZjubajdjubaubjZ)r}r(jYUjZjVjbjjdj]jf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r(j`)r}r(jYXR1. Pin 1 of SW3 is the endian pin, by default, it is set to off (Little Endian)rjcKjZjjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XR1. Pin 1 of SW3 is the endian pin, by default, it is set to off (Little Endian)rr}r(jYjjZjubaubj`)r}r(jYUjcKjZjjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubeubjZ)r}r(jYUjZjVjbjjdj]jf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r(j`)r}r(jYX`2. Pin 2-4 of SW3 are the boot mode pins, by default it is set to I2C boot mode (off, on, off)rjcKjZjjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X`2. Pin 2-4 of SW3 are the boot mode pins, by default it is set to I2C boot mode (off, on, off)rr}r(jYjjZjubaubj`)r}r(jYUjcKjZjjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubeubjZ)r}r(jYUjZjVjbjjdj]jf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r(j`)r}r(jYX3. Pin 5-8 of SW3 and pin 1-2 of SW5 are the boot parameter index pins for I2C boot (paramter index 0/1 for NOR boot image 0/1, parameter index 2/3 for NAND boot image 0/1, parameter index 4 for TFTP boot). By default, image 0 is programmed to offset byte address 0x0 on NOR, and 0x20000 (block 1 start address) on NAND, image 1 is programmed to offset byte address 0x4000000 on NAND.rjcKjZjjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X3. Pin 5-8 of SW3 and pin 1-2 of SW5 are the boot parameter index pins for I2C boot (paramter index 0/1 for NOR boot image 0/1, parameter index 2/3 for NAND boot image 0/1, parameter index 4 for TFTP boot). By default, image 0 is programmed to offset byte address 0x0 on NOR, and 0x20000 (block 1 start address) on NAND, image 1 is programmed to offset byte address 0x4000000 on NAND.rr}r(jYjjZjubaubj`)r}r(jYUjcKjZjjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubeubjZ)rÐ}rĐ(jYUjZjVjbjjdj]jf}rŐ(jh]ji]jj]jk]jn]ujpKjqhjr]rƐ(j`)rǐ}rȐ(jYXQ4. Pin 4 of SW5 is the I2C address pin (off: 0x51, on: 0x50)  for I2C boot moderɐjcKjZjÐjbjjdjpjf}rʐ(jh]ji]jj]jk]jn]ujpKjqhjr]rːj{XQ4. Pin 4 of SW5 is the I2C address pin (off: 0x51, on: 0x50)  for I2C boot moder̐r͐}rΐ(jYjɐjZjǐubaubj`)rϐ}rА(jYUjcKjZjÐjbjjdjpjf}rѐ(jh]ji]jj]jk]jn]ujpKjqhjr]ubeubjZ)rҐ}rӐ(jYUjZjVjbjjdj]jf}rԐ(jh]ji]jj]jk]jn]ujpKjqhjr]rՐ(j`)r֐}rא(jYX5. This will set the board to boot from SRIO boot mode, with reference clock at 250 MHz, data rate at 3.125 GBs, and lane setup 4-1x ports and DSP System PLL at 100 MHz.rؐjcKjZjҐjbjjdjpjf}rِ(jh]ji]jj]jk]jn]ujpKjqhjr]rڐj{X5. This will set the board to boot from SRIO boot mode, with reference clock at 250 MHz, data rate at 3.125 GBs, and lane setup 4-1x ports and DSP System PLL at 100 MHz.rېrܐ}rݐ(jYjؐjZj֐ubaubj`)rސ}rߐ(jYUjcKjZjҐjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubeubjZ)r}r(jYUjZjVjbjjdj]jf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r(j`)r}r(jYXy6. This will set the board to boot from Ethernet boot mode, with SerDes clock multiplier x 4, core PLL clock at 100 MHz.rjcKjZjjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{Xy6. This will set the board to boot from Ethernet boot mode, with SerDes clock multiplier x 4, core PLL clock at 100 MHz.rr}r(jYjjZjubaubj`)r}r(jYUjcKjZjjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubeubjZ)r}r(jYUjZjVjbjjdj]jf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r(j`)r}r(jYXr7. This will set the board to boot form PCIE boot mode, with PCIE in end point mode and DSP System PLL at 100 MHz.rjcKjZjjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{Xr7. This will set the board to boot form PCIE boot mode, with PCIE in end point mode and DSP System PLL at 100 MHz.rr}r(jYjjZjubaubj`)r}r(jYUjcKjZjjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubeubjZ)r}r(jYUjZjVjbjjdj]jf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r(j`)r}r(jYX8. This will set the board to boot from SPI NOR via the ROM code, with boot-table contents expected in the NOR. 24bit addressing has been set.rjcKjZjjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X8. This will set the board to boot from SPI NOR via the ROM code, with boot-table contents expected in the NOR. 24bit addressing has been set.rr }r (jYjjZjubaubj`)r }r (jYUjcKjZjjbjjdjpjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]ubeubj)r}r(jYX^Please refer to *Technical\_Reference\_Manual* for the boot mode switch settings on the board.jZjVjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r(j{XPlease refer to rr}r(jYXPlease refer to jZjubj')r}r(jYX*Technical\_Reference\_Manual*jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XTechnical_Reference_Manualrr}r(jYUjZjubajdj'ubj{X0 for the boot mode switch settings on the board.rr}r(jYX0 for the boot mode switch settings on the board.jZjubeubj)r}r (jYXTMDXEVM6670L EVM Hardware SetupjZjVjbjcjdjjf}r!(jjjk]jj]jh]ji]jn]ujpKjqhjr]r"j{XTMDXEVM6670L EVM Hardware Setupr#r$}r%(jYUjZjubaubj)r&}r'(jYX4====================================================jZjVjbjcjdjjf}r((jjjk]jj]jh]ji]jn]ujpKjqhjr]r)j{X4====================================================r*r+}r,(jYUjZj&ubaubeubeubj[)r-}r.(jYUjZjR\jbjXHsource/common/EVM_Hardware_Setup/TMDXEVM6670L_EVM_Hardware_Setup.rst.incr/r0}r1bjdjejf}r2(jh]ji]jj]jk]r3Utmdxevm6670l-evm-hardware-setupr4ajn]r5hsaujpKjqhjr]r6(jt)r7}r8(jYXTMDXEVM6670L EVM Hardware Setupr9jZj-jbj0jdjxjf}r:(jh]ji]jj]jk]jn]ujpKjqhjr]r;j{XTMDXEVM6670L EVM Hardware Setupr<r=}r>(jYj9jZj7ubaubj)r?}r@(jYXThis page will walk you through setting up your `TMDSEVM6670L `__ Evaluation Module (EVM). These guidelines also apply to the LE and LXE EVM models.jZj-jbj0jdjjf}rA(jh]ji]jj]jk]jn]ujpKjqhjr]rB(j{X0This page will walk you through setting up your rCrD}rE(jYX0This page will walk you through setting up your jZj?ubj)rF}rG(jYX5`TMDSEVM6670L `__jf}rH(UnameX TMDSEVM6670LjX"http://www.ti.com/tool/tmdsevm6670jk]jj]jh]ji]jn]ujZj?jr]rIj{X TMDSEVM6670LrJrK}rL(jYUjZjFubajdjubj{XS Evaluation Module (EVM). These guidelines also apply to the LE and LXE EVM models.rMrN}rO(jYXS Evaluation Module (EVM). These guidelines also apply to the LE and LXE EVM models.jZj?ubeubj)rP}rQ(jYXcSome of the steps in this section have been updated from those used in the EVM *Quick Start Guide*.rRjZj-jbj0jdjjf}rS(jh]ji]jj]jk]jn]ujpNjqhjr]rTj)rU}rV(jYjRjZjPjbj0jdjjf}rW(jh]ji]jj]jk]jn]ujpK jr]rX(j{XOSome of the steps in this section have been updated from those used in the EVM rYrZ}r[(jYXOSome of the steps in this section have been updated from those used in the EVM jZjUubj')r\}r](jYX*Quick Start Guide*jf}r^(jh]ji]jj]jk]jn]ujZjUjr]r_j{XQuick Start Guider`ra}rb(jYUjZj\ubajdj'ubj{X.rc}rd(jYX.jZjUubeubaubj[)re}rf(jYUjKjZj-jbj0jdjejf}rg(jh]rhjXaji]jj]jk]riUid68rjajn]ujpK jqhjr]rk(jt)rl}rm(jYXHardware Setup OverviewrnjZjejbj0jdjxjf}ro(jh]ji]jj]jk]jn]ujpK jqhjr]rpj{XHardware Setup Overviewrqrr}rs(jYjnjZjlubaubj)rt}ru(jYXcThe picture below shows the TMDXEVM6670L EVM and the locations of relevant switches and connectors.rvjZjejbj0jdjjf}rw(jh]ji]jj]jk]jn]ujpKjqhjr]rxj{XcThe picture below shows the TMDXEVM6670L EVM and the locations of relevant switches and connectors.ryrz}r{(jYjvjZjtubaubjB)r|}r}(jYX#.. image:: ../images/TMD6670L.jpg jZjejbj0jdjEjf}r~(UuriXrtos/../images/TMD6670L.jpgrjk]jj]jh]ji]jH}rU*jsjn]ujpKjqhjr]ubeubj[)r}r(jYUjKjZj-jbj0jdjejf}r(jh]rjuaji]jj]jk]rUid69rajn]ujpKjqhjr]r(jt)r}r(jYXHardware Setup StepsrjZjjbj0jdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XHardware Setup Stepsrr}r(jYjjZjubaubj)r}r(jYXThe EVM board is sensitive to electrostatic discharges (ESD). Use a grounding strap or other device to prevent damaging the board. Be sure to connect communication cables before applying power to any equipment.rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XThe EVM board is sensitive to electrostatic discharges (ESD). Use a grounding strap or other device to prevent damaging the board. Be sure to connect communication cables before applying power to any equipment.rr}r(jYjjZjubaubaubjZ)r}r(jYUjZjjbj0jdj]jf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r(j`)r}r(jYUjcKjZjjbj0jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)r}r(jYX **1. Attach the Ethernet cable**rjcKjZjjbj0jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X1. Attach the Ethernet cablerr}r(jYUjZjubajdjubaubj`)r}r(jYX}Using the Ethernet cable supplied, connect one end of the cable to the Ethernet port on the EVM and the other end to your PC.rjcKjZjjbj0jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X}Using the Ethernet cable supplied, connect one end of the cable to the Ethernet port on the EVM and the other end to your PC.rr}r(jYjjZjubaubeubjZ)r}r(jYUjZjjbj0jdj]jf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r(j`)r}r(jYUjcKjZjjbj0jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)r}r(jYX!**2. Connect the JTAG interface**rjcKjZjjbj0jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r‘j)rÑ}rđ(jYjjf}rő(jh]ji]jj]jk]jn]ujZjjr]rƑj{X2. Connect the JTAG interfacerǑrȑ}rɑ(jYUjZjÑubajdjubaubj`)rʑ}rˑ(jYXUse the USB to USB mini-B cable provided. Connect the USB mini-B connector to the USB mini-B interface on the EVM and the USB connector to your PC. This enables XDS-100 emulation and is directly useable by CCS. If you are using a different JTAG, connect it now.ȓjcKjZjjbj0jdjpjf}r͑(jh]ji]jj]jk]jn]ujpK jqhjr]rΑj{XUse the USB to USB mini-B cable provided. Connect the USB mini-B connector to the USB mini-B interface on the EVM and the USB connector to your PC. This enables XDS-100 emulation and is directly useable by CCS. If you are using a different JTAG, connect it now.rϑrБ}rё(jYj̑jZjʑubaubeubjZ)rґ}rӑ(jYUjZjjbj0jdj]jf}rԑ(jh]ji]jj]jk]jn]ujpK"jqhjr]rՑ(j`)r֑}rב(jYUjcKjZjґjbj0jdjpjf}rؑ(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)rّ}rڑ(jYX-**3. Verify Endian mode in the SW3 settings**rۑjcKjZjґjbj0jdjpjf}rܑ(jh]ji]jj]jk]jn]ujpK#jqhjr]rݑj)rޑ}rߑ(jYjۑjf}r(jh]ji]jj]jk]jn]ujZjّjr]rj{X)3. Verify Endian mode in the SW3 settingsrr}r(jYUjZjޑubajdjubaubj`)r}r(jYX[The Endian mode should be set to Little Endian. SW3 also contains the boot device settings.rjcKjZjґjbj0jdjpjf}r(jh]ji]jj]jk]jn]ujpK$jqhjr]rj{X[The Endian mode should be set to Little Endian. SW3 also contains the boot device settings.rr}r(jYjjZjubaubeubjB)r}r(jYX4.. image:: ../images/TMD6678LSW3.png :scale: 40% jZjjbj0jdjEjf}r(UscaleK(UuriXrtos/../images/TMD6678LSW3.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpNjqhjr]ubjZ)r}r(jYUjZjjbj0jdj]jf}r(jh]ji]jj]jk]jn]ujpK)jqhjr]r(j`)r}r(jYUjcKjZjjbj0jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)r}r(jYX1**4. Verify boot mode in the SW3 - SW6 settings**rjcKjZjjbj0jdjpjf}r(jh]ji]jj]jk]jn]ujpK*jqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X-4. Verify boot mode in the SW3 - SW6 settingsrr}r(jYUjZjubajdjubaubj`)r}r(jYXaThe boot mode settings below enable NOR boot by loading the boot loader from EEPROM address 0x51.rjcKjZjjbj0jdjpjf}r(jh]ji]jj]jk]jn]ujpK+jqhjr]r j{XaThe boot mode settings below enable NOR boot by loading the boot loader from EEPROM address 0x51.r r }r (jYjjZjubaubeubjB)r }r(jYX6.. image:: ../images/TMD6678LSW3-6.png :scale: 40% jZjjbj0jdjEjf}r(UscaleK(UuriX rtos/../images/TMD6678LSW3-6.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpNjqhjr]ubjZ)r}r(jYUjZjjbj0jdj]jf}r(jh]ji]jj]jk]jn]ujpK0jqhjr]r(j`)r}r(jYUjcKjZjjbj0jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)r}r(jYX1**5. Set User Switch 2 for the demo application**rjcKjZjjbj0jdjpjf}r(jh]ji]jj]jk]jn]ujpK1jqhjr]rj)r}r(jYjjf}r (jh]ji]jj]jk]jn]ujZjjr]r!j{X-5. Set User Switch 2 for the demo applicationr"r#}r$(jYUjZjubajdjubaubj`)r%}r&(jYXThe application needs an IP address. It can use either a static IP address (pre-configured) or it can request one using DHCP. This is controlled by setting User Switch 2 to ON for DHCP and OFF for Static. See SW9.r'jcKjZjjbj0jdjpjf}r((jh]ji]jj]jk]jn]ujpK2jqhjr]r)j{XThe application needs an IP address. It can use either a static IP address (pre-configured) or it can request one using DHCP. This is controlled by setting User Switch 2 to ON for DHCP and OFF for Static. See SW9.r*r+}r,(jYj'jZj%ubaubeubjB)r-}r.(jYX%.. image:: ../images/TMD6670LSW9.png jZjjbj0jdjEjf}r/(UuriXrtos/../images/TMD6670LSW9.pngr0jk]jj]jh]ji]jH}r1U*j0sjn]ujpK5jqhjr]ubjZ)r2}r3(jYUjZjjbj0jdj]jf}r4(jh]ji]jj]jk]jn]ujpK6jqhjr]r5(j`)r6}r7(jYUjcKjZj2jbj0jdjpjf}r8(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)r9}r:(jYX#**6. Attach the serial port cable**r;jcKjZj2jbj0jdjpjf}r<(jh]ji]jj]jk]jn]ujpK7jqhjr]r=j)r>}r?(jYj;jf}r@(jh]ji]jj]jk]jn]ujZj9jr]rAj{X6. Attach the serial port cablerBrC}rD(jYUjZj>ubajdjubaubj`)rE}rF(jYX"This EVM can use either a USB serial port or the standard DB-9 (use the cable shipped with the platform). By default the shunts which control this on the platforms are set to use the USB by default. We recommend changing them to use the DB-9 as there are no known issues with this approach.rGjcKjZj2jbj0jdjpjf}rH(jh]ji]jj]jk]jn]ujpK8jqhjr]rIj{X"This EVM can use either a USB serial port or the standard DB-9 (use the cable shipped with the platform). By default the shunts which control this on the platforms are set to use the USB by default. We recommend changing them to use the DB-9 as there are no known issues with this approach.rJrK}rL(jYjGjZjEubaubeubjZ)rM}rN(jYUjZjjbj0jdj]jf}rO(jh]ji]jj]jk]jn]ujpK:jqhjr]rPj`)rQ}rR(jYX0To change the shunts refer to the picture below.rSjcKjZjMjbj0jdjpjf}rT(jh]ji]jj]jk]jn]ujpK:jqhjr]rUj{X0To change the shunts refer to the picture below.rVrW}rX(jYjSjZjQubaubaubjB)rY}rZ(jYX(.. image:: ../images/TMD6670LShunts.jpg jZjjbj0jdjEjf}r[(UuriX!rtos/../images/TMD6670LShunts.jpgr\jk]jj]jh]ji]jH}r]U*j\sjn]ujpK=jqhjr]ubj)r^}r_(jYXIf the USB serial port output does not work, ensure that the cable is connected directly to a USB port on the PC/laptop rather than going through an extender or USB hub.r`jZjjbj0jdjjf}ra(jh]ji]jj]jk]jn]ujpNjqhjr]rbj)rc}rd(jYj`jZj^jbj0jdjjf}re(jh]ji]jj]jk]jn]ujpK>jr]rfj{XIf the USB serial port output does not work, ensure that the cable is connected directly to a USB port on the PC/laptop rather than going through an extender or USB hub.rgrh}ri(jYj`jZjcubaubaubjZ)rj}rk(jYUjZjjbj0jdj]jf}rl(jh]ji]jj]jk]jn]ujpK@jqhjr]rm(j`)rn}ro(jYUjcKjZjjjbj0jdjpjf}rp(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)rq}rr(jYX**7. Connect the power cable**rsjcKjZjjjbj0jdjpjf}rt(jh]ji]jj]jk]jn]ujpKAjqhjr]ruj)rv}rw(jYjsjf}rx(jh]ji]jj]jk]jn]ujZjqjr]ryj{X7. Connect the power cablerzr{}r|(jYUjZjvubajdjubaubj`)r}}r~(jYXConnect the power cable to the EVM power jack on the board. To be ESD safe, plug in the other end of the power cable only after you have connected the power cord to the board. Then turn on the board.rjcKjZjjjbj0jdjpjf}r(jh]ji]jj]jk]jn]ujpKBjqhjr]rj{XConnect the power cable to the EVM power jack on the board. To be ESD safe, plug in the other end of the power cable only after you have connected the power cord to the board. Then turn on the board.rr}r(jYjjZj}ubaubeubjZ)r}r(jYUjZjjbj0jdj]jf}r(jh]ji]jj]jk]jn]ujpKDjqhjr]rj`)r}r(jYUjcKjZjjbj0jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubj[)r}r(jYUjKjZj-jbj0jdjejf}r(jh]rjZaji]jj]jk]rUid70rajn]ujpKGjqhjr]r(jt)r}r(jYXBoot Mode Dip Switch SettingsrjZjjbj0jdjxjf}r(jh]ji]jj]jk]jn]ujpKGjqhjr]rj{XBoot Mode Dip Switch Settingsrr}r(jYjjZjubaubj)r}r(jYXThe EVM supports booting image from various devices (EEPROM, NAND or NOR) via IBL, it also supports ROM Boot modes, such as Ethernet, SRIO, PCIe, etc. Below is the table showing the boot mode dip switch settings for different boot mode that the EVM supports:rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKIjqhjr]rj{XThe EVM supports booting image from various devices (EEPROM, NAND or NOR) via IBL, it also supports ROM Boot modes, such as Ethernet, SRIO, PCIe, etc. Below is the table showing the boot mode dip switch settings for different boot mode that the EVM supports:rr}r(jYjjZjubaubjd$)r}r(jYUjZjjbj0jdjg$jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rjj$)r}r(jYUjf}r(jk]jj]jh]ji]jn]UcolsKujZjjr]r(jo$)r}r(jYUjf}r(jk]jj]jh]ji]jn]UcolwidthKujZjjr]jdjs$ubjo$)r}r(jYUjf}r(jk]jj]jh]ji]jn]UcolwidthKujZjjr]jdjs$ubjo$)r}r(jYUjf}r(jk]jj]jh]ji]jn]UcolwidthKujZjjr]jdjs$ubjo$)r}r(jYUjf}r(jk]jj]jh]ji]jn]UcolwidthKujZjjr]jdjs$ubjo$)r}r(jYUjf}r(jk]jj]jh]ji]jn]UcolwidthKujZjjr]jdjs$ubjz$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r’}rÒ(jYUjf}rĒ(jh]ji]jj]jk]jn]ujZjjr]rŒj)rƒ}rǒ(jYX Boot ModerȒjZj’jbj0jdjjf}rɒ(jh]ji]jj]jk]jn]ujpKOjr]rʒj{X Boot Moder˒r̒}r͒(jYjȒjZjƒubaubajdj$ubj$)rΒ}rϒ(jYUjf}rВ(jh]ji]jj]jk]jn]ujZjjr]rђ(j)rҒ}rӒ(jYXDIP SW3rԒjZjΒjbj0jdjjf}rՒ(jh]ji]jj]jk]jn]ujpKOjr]r֒j{XDIP SW3rגrؒ}rْ(jYjԒjZjҒubaubj)rڒ}rے(jYX(Pin1, 2, 3, 4)rܒjZjΒjbj0jdjjf}rݒ(jh]ji]jj]jk]jn]ujpKQjr]rޒj{X(Pin1, 2, 3, 4)rߒr}r(jYjܒjZjڒubaubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j)r}r(jYXDIP SW4rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKOjr]rj{XDIP SW4rr}r(jYjjZjubaubj)r}r(jYX(Pin1, 2, 3, 4)rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKQjr]rj{X(Pin1, 2, 3, 4)rr}r(jYjjZjubaubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j)r}r(jYXDIP SW5rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKOjr]rj{XDIP SW5rr}r(jYjjZjubaubj)r}r(jYX(Pin1, 2, 3, 4)rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKQjr]rj{X(Pin1, 2, 3, 4)rr}r (jYjjZjubaubejdj$ubj$)r }r (jYUjf}r (jh]ji]jj]jk]jn]ujZjjr]r (j)r}r(jYXDIP SW6rjZj jbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKOjr]rj{XDIP SW6rr}r(jYjjZjubaubj)r}r(jYX(Pin1, 2, 3, 4)rjZj jbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKQjr]rj{X(Pin1, 2, 3, 4)rr}r(jYjjZjubaubejdj$ubejdj$ubajdj$ubj$)r}r(jYUjf}r (jh]ji]jj]jk]jn]ujZjjr]r!(j$)r"}r#(jYUjf}r$(jh]ji]jj]jk]jn]ujZjjr]r%(j$)r&}r'(jYUjf}r((jh]ji]jj]jk]jn]ujZj"jr]r)j)r*}r+(jYX!IBL NOR boot on image 0 (default)r,jZj&jbj0jdjjf}r-(jh]ji]jj]jk]jn]ujpKTjr]r.j{X!IBL NOR boot on image 0 (default)r/r0}r1(jYj,jZj*ubaubajdj$ubj$)r2}r3(jYUjf}r4(jh]ji]jj]jk]jn]ujZj"jr]r5j)r6}r7(jYX (off, off, on, off)\ :sup:`1, 2`jZj2jbj0jdjjf}r8(jh]ji]jj]jk]jn]ujpKTjr]r9(j{X(off, off, on, off)r:r;}r<(jYX(off, off, on, off)\ jZj6ubj)r=}r>(jYX :sup:`1, 2`jf}r?(jh]ji]jj]jk]jn]ujZj6jr]r@j{X1, 2rArB}rC(jYUjZj=ubajdjubeubajdj$ubj$)rD}rE(jYUjf}rF(jh]ji]jj]jk]jn]ujZj"jr]rGj)rH}rI(jYX(on, on, on, on)\ :sup:`3`jZjDjbj0jdjjf}rJ(jh]ji]jj]jk]jn]ujpKTjr]rK(j{X(on, on, on, on)rLrM}rN(jYX(on, on, on, on)\ jZjHubj)rO}rP(jYX:sup:`3`jf}rQ(jh]ji]jj]jk]jn]ujZjHjr]rRj{X3rS}rT(jYUjZjOubajdjubeubajdj$ubj$)rU}rV(jYUjf}rW(jh]ji]jj]jk]jn]ujZj"jr]rXj)rY}rZ(jYX(on, on, on, off)\ :sup:`4`jZjUjbj0jdjjf}r[(jh]ji]jj]jk]jn]ujpKTjr]r\(j{X(on, on, on, off)r]r^}r_(jYX(on, on, on, off)\ jZjYubj)r`}ra(jYX:sup:`4`jf}rb(jh]ji]jj]jk]jn]ujZjYjr]rcj{X4rd}re(jYUjZj`ubajdjubeubajdj$ubj$)rf}rg(jYUjf}rh(jh]ji]jj]jk]jn]ujZj"jr]rij)rj}rk(jYX(on, on, on, on)rljZjfjbj0jdjjf}rm(jh]ji]jj]jk]jn]ujpKTjr]rnj{X(on, on, on, on)rorp}rq(jYjljZjjubaubajdj$ubejdj$ubj$)rr}rs(jYUjf}rt(jh]ji]jj]jk]jn]ujZjjr]ru(j$)rv}rw(jYUjf}rx(jh]ji]jj]jk]jn]ujZjrjr]ryj)rz}r{(jYXIBL NOR boot on image 1r|jZjvjbj0jdjjf}r}(jh]ji]jj]jk]jn]ujpKXjr]r~j{XIBL NOR boot on image 1rr}r(jYj|jZjzubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjrjr]rj)r}r(jYX(off, off, on, off)rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKXjr]rj{X(off, off, on, off)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjrjr]rj)r}r(jYX(off, on, on, on)rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKXjr]rj{X(off, on, on, on)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjrjr]rj)r}r(jYX(on, on, on, off)rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKXjr]rj{X(on, on, on, off)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjrjr]rj)r}r(jYX(on, on, on, on)rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKXjr]rj{X(on, on, on, on)rr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXIBL NAND boot on image 0rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpK[jr]rj{XIBL NAND boot on image 0rr}r(jYjjZjubaubajdj$ubj$)r“}rÓ(jYUjf}rē(jh]ji]jj]jk]jn]ujZjjr]rœj)rƓ}rǓ(jYX(off, off, on, off)rȓjZj“jbj0jdjjf}rɓ(jh]ji]jj]jk]jn]ujpK[jr]rʓj{X(off, off, on, off)r˓r̓}r͓(jYjȓjZjƓubaubajdj$ubj$)rΓ}rϓ(jYUjf}rГ(jh]ji]jj]jk]jn]ujZjjr]rѓj)rғ}rӓ(jYX(on, off, on, on)rԓjZjΓjbj0jdjjf}rՓ(jh]ji]jj]jk]jn]ujpK[jr]r֓j{X(on, off, on, on)rדrؓ}rٓ(jYjԓjZjғubaubajdj$ubj$)rړ}rۓ(jYUjf}rܓ(jh]ji]jj]jk]jn]ujZjjr]rݓj)rޓ}rߓ(jYX(on, on, on, off)rjZjړjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpK[jr]rj{X(on, on, on, off)rr}r(jYjjZjޓubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX(on, on, on, on)rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpK[jr]rj{X(on, on, on, on)rr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXIBL NAND boot on image 1rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpK^jr]rj{XIBL NAND boot on image 1rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX(off, off, on, off)rjZjjbj0jdjjf}r (jh]ji]jj]jk]jn]ujpK^jr]r j{X(off, off, on, off)r r }r (jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX(off, off, on, on)rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpK^jr]rj{X(off, off, on, on)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX(on, on, on, off)r jZjjbj0jdjjf}r!(jh]ji]jj]jk]jn]ujpK^jr]r"j{X(on, on, on, off)r#r$}r%(jYj jZjubaubajdj$ubj$)r&}r'(jYUjf}r((jh]ji]jj]jk]jn]ujZjjr]r)j)r*}r+(jYX(on, on, on, on)r,jZj&jbj0jdjjf}r-(jh]ji]jj]jk]jn]ujpK^jr]r.j{X(on, on, on, on)r/r0}r1(jYj,jZj*ubaubajdj$ubejdj$ubj$)r2}r3(jYUjf}r4(jh]ji]jj]jk]jn]ujZjjr]r5(j$)r6}r7(jYUjf}r8(jh]ji]jj]jk]jn]ujZj2jr]r9j)r:}r;(jYX IBL TFTP bootr<jZj6jbj0jdjjf}r=(jh]ji]jj]jk]jn]ujpKajr]r>j{X IBL TFTP bootr?r@}rA(jYj<jZj:ubaubajdj$ubj$)rB}rC(jYUjf}rD(jh]ji]jj]jk]jn]ujZj2jr]rEj)rF}rG(jYX(off, off, on, off)rHjZjBjbj0jdjjf}rI(jh]ji]jj]jk]jn]ujpKajr]rJj{X(off, off, on, off)rKrL}rM(jYjHjZjFubaubajdj$ubj$)rN}rO(jYUjf}rP(jh]ji]jj]jk]jn]ujZj2jr]rQj)rR}rS(jYX(on, on, off, on)rTjZjNjbj0jdjjf}rU(jh]ji]jj]jk]jn]ujpKajr]rVj{X(on, on, off, on)rWrX}rY(jYjTjZjRubaubajdj$ubj$)rZ}r[(jYUjf}r\(jh]ji]jj]jk]jn]ujZj2jr]r]j)r^}r_(jYX(on, on, on, off)r`jZjZjbj0jdjjf}ra(jh]ji]jj]jk]jn]ujpKajr]rbj{X(on, on, on, off)rcrd}re(jYj`jZj^ubaubajdj$ubj$)rf}rg(jYUjf}rh(jh]ji]jj]jk]jn]ujZj2jr]rij)rj}rk(jYX(on, on, on, on)rljZjfjbj0jdjjf}rm(jh]ji]jj]jk]jn]ujpKajr]rnj{X(on, on, on, on)rorp}rq(jYjljZjjubaubajdj$ubejdj$ubj$)rr}rs(jYUjf}rt(jh]ji]jj]jk]jn]ujZjjr]ru(j$)rv}rw(jYUjf}rx(jh]ji]jj]jk]jn]ujZjrjr]ryj)rz}r{(jYX I2C POST bootr|jZjvjbj0jdjjf}r}(jh]ji]jj]jk]jn]ujpKdjr]r~j{X I2C POST bootrr}r(jYj|jZjzubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjrjr]rj)r}r(jYX(off, off, on, off)rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKdjr]rj{X(off, off, on, off)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjrjr]rj)r}r(jYX(on, on, on, on)rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKdjr]rj{X(on, on, on, on)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjrjr]rj)r}r(jYX(on, on, on, on)rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKdjr]rj{X(on, on, on, on)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjrjr]rj)r}r(jYX(on, on, on, on)rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKdjr]rj{X(on, on, on, on)rr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXROM SPI Boot\ :sup:`8`jZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKgjr]r(j{X ROM SPI Bootrr}r(jYXROM SPI Boot\ jZjubj)r}r”(jYX:sup:`8`jf}rÔ(jh]ji]jj]jk]jn]ujZjjr]rĔj{X8rŔ}rƔ(jYUjZjubajdjubeubajdj$ubj$)rǔ}rȔ(jYUjf}rɔ(jh]ji]jj]jk]jn]ujZjjr]rʔj)r˔}r̔(jYX(off, on, off, off)r͔jZjǔjbj0jdjjf}rΔ(jh]ji]jj]jk]jn]ujpKgjr]rϔj{X(off, on, off, off)rДrє}rҔ(jYj͔jZj˔ubaubajdj$ubj$)rӔ}rԔ(jYUjf}rՔ(jh]ji]jj]jk]jn]ujZjjr]r֔j)rה}rؔ(jYX(on, on, on, on)rٔjZjӔjbj0jdjjf}rڔ(jh]ji]jj]jk]jn]ujpKgjr]r۔j{X(on, on, on, on)rܔrݔ}rޔ(jYjٔjZjהubaubajdj$ubj$)rߔ}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX(on, on, off, on)rjZjߔjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKgjr]rj{X(on, on, off, on)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX(off, on, on, on)rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKgjr]rj{X(off, on, on, on)rr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXROM SRIO Boot\ :sup:`5`jZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKjjr]r(j{X ROM SRIO Bootrr}r(jYXROM SRIO Boot\ jZjubj)r}r(jYX:sup:`5`jf}r(jh]ji]jj]jk]jn]ujZjjr]r j{X5r }r (jYUjZjubajdjubeubajdj$ubj$)r }r (jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX(off, off, on, on)rjZj jbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKjjr]rj{X(off, off, on, on)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX(on, on, on, off)rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKjjr]r j{X(on, on, on, off)r!r"}r#(jYjjZjubaubajdj$ubj$)r$}r%(jYUjf}r&(jh]ji]jj]jk]jn]ujZjjr]r'j)r(}r)(jYX(on, off, on, off)r*jZj$jbj0jdjjf}r+(jh]ji]jj]jk]jn]ujpKjjr]r,j{X(on, off, on, off)r-r.}r/(jYj*jZj(ubaubajdj$ubj$)r0}r1(jYUjf}r2(jh]ji]jj]jk]jn]ujZjjr]r3j)r4}r5(jYX(off, off, on, on)r6jZj0jbj0jdjjf}r7(jh]ji]jj]jk]jn]ujpKjjr]r8j{X(off, off, on, on)r9r:}r;(jYj6jZj4ubaubajdj$ubejdj$ubj$)r<}r=(jYUjf}r>(jh]ji]jj]jk]jn]ujZjjr]r?(j$)r@}rA(jYUjf}rB(jh]ji]jj]jk]jn]ujZj<jr]rCj)rD}rE(jYXROM Ethernet Boot\ :sup:`6`jZj@jbj0jdjjf}rF(jh]ji]jj]jk]jn]ujpKmjr]rG(j{XROM Ethernet BootrHrI}rJ(jYXROM Ethernet Boot\ jZjDubj)rK}rL(jYX:sup:`6`jf}rM(jh]ji]jj]jk]jn]ujZjDjr]rNj{X6rO}rP(jYUjZjKubajdjubeubajdj$ubj$)rQ}rR(jYUjf}rS(jh]ji]jj]jk]jn]ujZj<jr]rTj)rU}rV(jYX(off, on, off, on)rWjZjQjbj0jdjjf}rX(jh]ji]jj]jk]jn]ujpKmjr]rYj{X(off, on, off, on)rZr[}r\(jYjWjZjUubaubajdj$ubj$)r]}r^(jYUjf}r_(jh]ji]jj]jk]jn]ujZj<jr]r`j)ra}rb(jYX(on, on, on, off)rcjZj]jbj0jdjjf}rd(jh]ji]jj]jk]jn]ujpKmjr]rej{X(on, on, on, off)rfrg}rh(jYjcjZjaubaubajdj$ubj$)ri}rj(jYUjf}rk(jh]ji]jj]jk]jn]ujZj<jr]rlj)rm}rn(jYX(on, off, on, off)rojZjijbj0jdjjf}rp(jh]ji]jj]jk]jn]ujpKmjr]rqj{X(on, off, on, off)rrrs}rt(jYjojZjmubaubajdj$ubj$)ru}rv(jYUjf}rw(jh]ji]jj]jk]jn]ujZj<jr]rxj)ry}rz(jYX(off, off, on, on)r{jZjujbj0jdjjf}r|(jh]ji]jj]jk]jn]ujpKmjr]r}j{X(off, off, on, on)r~r}r(jYj{jZjyubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXROM PCIE Boot\ :sup:`7`jZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKpjr]r(j{X ROM PCIE Bootrr}r(jYXROM PCIE Boot\ jZjubj)r}r(jYX:sup:`7`jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X7r}r(jYUjZjubajdjubeubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX(off, on, on, off)rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKpjr]rj{X(off, on, on, off)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX(on, on, on, on)rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKpjr]rj{X(on, on, on, on)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX(on, on, on, off)rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKpjr]rj{X(on, on, on, off)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX(off, on, on, on)rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKpjr]r•j{X(off, on, on, on)rÕrĕ}rŕ(jYjjZjubaubajdj$ubejdj$ubj$)rƕ}rǕ(jYUjf}rȕ(jh]ji]jj]jk]jn]ujZjjr]rɕ(j$)rʕ}r˕(jYUjf}r̕(jh]ji]jj]jk]jn]ujZjƕjr]r͕j)rΕ}rϕ(jYXNo bootrЕjZjʕjbj0jdjjf}rѕ(jh]ji]jj]jk]jn]ujpKsjr]rҕj{XNo bootrӕrԕ}rՕ(jYjЕjZjΕubaubajdj$ubj$)r֕}rו(jYUjf}rؕ(jh]ji]jj]jk]jn]ujZjƕjr]rٕj)rڕ}rە(jYX(off, on, on, on)rܕjZj֕jbj0jdjjf}rݕ(jh]ji]jj]jk]jn]ujpKsjr]rޕj{X(off, on, on, on)rߕr}r(jYjܕjZjڕubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjƕjr]rj)r}r(jYX(on, on, on, on)rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKsjr]rj{X(on, on, on, on)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjƕjr]rj)r}r(jYX(on, on, on, on)rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKsjr]rj{X(on, on, on, on)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjƕjr]rj)r}r(jYX(on, on, on, on)rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKsjr]rj{X(on, on, on, on)rr}r(jYjjZjubaubajdj$ubejdj$ubejdjy%ubejdjz%ubaubjZ)r}r(jYUjZjjbj0jdj]jf}r(jh]ji]jj]jk]jn]ujpKwjqhjr]r j`)r }r (jYUjcKjZjjbj0jdjpjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r }r(jYX**Footnotes:**rjZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKyjqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZj jr]rj{X Footnotes:rr}r(jYUjZjubajdjubaubjZ)r}r(jYUjZjjbj0jdj]jf}r(jh]ji]jj]jk]jn]ujpK{jqhjr]r(j`)r}r(jYXR1. Pin 1 of SW3 is the endian pin, by default, it is set to off (Little Endian)rjcKjZjjbj0jdjpjf}r (jh]ji]jj]jk]jn]ujpK{jqhjr]r!j{XR1. Pin 1 of SW3 is the endian pin, by default, it is set to off (Little Endian)r"r#}r$(jYjjZjubaubj`)r%}r&(jYUjcKjZjjbj0jdjpjf}r'(jh]ji]jj]jk]jn]ujpKjqhjr]ubeubjZ)r(}r)(jYUjZjjbj0jdj]jf}r*(jh]ji]jj]jk]jn]ujpK~jqhjr]r+(j`)r,}r-(jYX`2. Pin 2-4 of SW3 are the boot mode pins, by default it is set to I2C boot mode (off, on, off)r.jcKjZj(jbj0jdjpjf}r/(jh]ji]jj]jk]jn]ujpK~jqhjr]r0j{X`2. Pin 2-4 of SW3 are the boot mode pins, by default it is set to I2C boot mode (off, on, off)r1r2}r3(jYj.jZj,ubaubj`)r4}r5(jYUjcKjZj(jbj0jdjpjf}r6(jh]ji]jj]jk]jn]ujpKjqhjr]ubeubjZ)r7}r8(jYUjZjjbj0jdj]jf}r9(jh]ji]jj]jk]jn]ujpKjqhjr]r:(j`)r;}r<(jYX3. Pin 1-4 of SW4 and pin 1-2 of SW5 are the boot parameter index pins for I2C boot (paramter index 0/1 for NOR boot image 0/1, parameter index 2/3 for NAND boot image 0/1, parameter index 4 for TFTP boot). By default, image 0 is programmed to offset byte address 0x0 on NOR, and 0x4000 (block 1 start address) on NAND, image 1 is programmed to offset byte address 0xA00000 on NOR, and 0x2000000 on NAND.r=jcKjZj7jbj0jdjpjf}r>(jh]ji]jj]jk]jn]ujpKjqhjr]r?j{X3. Pin 1-4 of SW4 and pin 1-2 of SW5 are the boot parameter index pins for I2C boot (paramter index 0/1 for NOR boot image 0/1, parameter index 2/3 for NAND boot image 0/1, parameter index 4 for TFTP boot). By default, image 0 is programmed to offset byte address 0x0 on NOR, and 0x4000 (block 1 start address) on NAND, image 1 is programmed to offset byte address 0xA00000 on NOR, and 0x2000000 on NAND.r@rA}rB(jYj=jZj;ubaubj`)rC}rD(jYUjcKjZj7jbj0jdjpjf}rE(jh]ji]jj]jk]jn]ujpKjqhjr]ubeubjZ)rF}rG(jYUjZjjbj0jdj]jf}rH(jh]ji]jj]jk]jn]ujpKjqhjr]rI(j`)rJ}rK(jYXQ4. Pin 4 of SW5 is the I2C address pin (off: 0x51, on: 0x50)  for I2C boot moderLjcKjZjFjbj0jdjpjf}rM(jh]ji]jj]jk]jn]ujpKjqhjr]rNj{XQ4. Pin 4 of SW5 is the I2C address pin (off: 0x51, on: 0x50)  for I2C boot moderOrP}rQ(jYjLjZjJubaubj`)rR}rS(jYUjcKjZjFjbj0jdjpjf}rT(jh]ji]jj]jk]jn]ujpKjqhjr]ubeubjZ)rU}rV(jYUjZjjbj0jdj]jf}rW(jh]ji]jj]jk]jn]ujpKjqhjr]rX(j`)rY}rZ(jYX5. This will set the board to boot from SRIO boot mode, with reference clock at 250 MHz, data rate at 3.125 GBs, and lane setup 4-1x ports and DSP System PLL at 122.88 MHz.r[jcKjZjUjbj0jdjpjf}r\(jh]ji]jj]jk]jn]ujpKjqhjr]r]j{X5. This will set the board to boot from SRIO boot mode, with reference clock at 250 MHz, data rate at 3.125 GBs, and lane setup 4-1x ports and DSP System PLL at 122.88 MHz.r^r_}r`(jYj[jZjYubaubj`)ra}rb(jYUjcKjZjUjbj0jdjpjf}rc(jh]ji]jj]jk]jn]ujpKjqhjr]ubeubjZ)rd}re(jYUjZjjbj0jdj]jf}rf(jh]ji]jj]jk]jn]ujpKjqhjr]rg(j`)rh}ri(jYX6. This will set the board to boot from Ethernet boot mode, with SerDes clock multiplier x 5, DSP System PLL clock at 122.88 MHz.rjjcKjZjdjbj0jdjpjf}rk(jh]ji]jj]jk]jn]ujpKjqhjr]rlj{X6. This will set the board to boot from Ethernet boot mode, with SerDes clock multiplier x 5, DSP System PLL clock at 122.88 MHz.rmrn}ro(jYjjjZjhubaubj`)rp}rq(jYUjcKjZjdjbj0jdjpjf}rr(jh]ji]jj]jk]jn]ujpKjqhjr]ubeubjZ)rs}rt(jYUjZjjbj0jdj]jf}ru(jh]ji]jj]jk]jn]ujpKjqhjr]rv(j`)rw}rx(jYXr7. This will set the board to boot form PCIE boot mode, with PCIE in end point mode and DSP System PLL at 100 MHz.ryjcKjZjsjbj0jdjpjf}rz(jh]ji]jj]jk]jn]ujpKjqhjr]r{j{Xr7. This will set the board to boot form PCIE boot mode, with PCIE in end point mode and DSP System PLL at 100 MHz.r|r}}r~(jYjyjZjwubaubj`)r}r(jYUjcKjZjsjbj0jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubeubjZ)r}r(jYUjZjjbj0jdj]jf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r(j`)r}r(jYX8. This will set the board to boot from SPI NOR via the ROM code, with boot-table contents expected in the NOR. 24bit addressing has been set.rjcKjZjjbj0jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X8. This will set the board to boot from SPI NOR via the ROM code, with boot-table contents expected in the NOR. 24bit addressing has been set.rr}r(jYjjZjubaubj`)r}r(jYUjcKjZjjbj0jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)r}r(jYUjcKjZjjbj0jdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubeubj)r}r(jYXPlease refer to `Technical\_Reference\_Manual `__ for the boot mode switch settings on the board.jZjjbj0jdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r(j{XPlease refer to rr}r(jYXPlease refer to jZjubj)r}r(jYXY`Technical\_Reference\_Manual `__jf}r(UnameXTechnical_Reference_ManualjX6http://www.advantech.com/Support/TI-EVM/6670le_sd.aspxjk]jj]jh]ji]jn]ujZjjr]rj{XTechnical_Reference_Manualrr}r(jYUjZjubajdjubj{X0 for the boot mode switch settings on the board.rr}r(jYX0 for the boot mode switch settings on the board.jZjubeubj)r}r(jYXTMDXEVM6678L EVM Hardware SetupjZjjbjcjdjjf}r(jjjk]jj]jh]ji]jn]ujpKjqhjr]rj{XTMDXEVM6678L EVM Hardware Setuprr}r(jYUjZjubaubj)r}r(jYX4====================================================jZjjbjcjdjjf}r(jjjk]jj]jh]ji]jn]ujpKjqhjr]rj{X4====================================================rr}r(jYUjZjubaubeubeubj[)r}r(jYUjZjR\jbjXHsource/common/EVM_Hardware_Setup/TMDXEVM6678L_EVM_Hardware_Setup.rst.incrr}rbjdjejf}r(jh]ji]jj]jk]rU%tmdxevm6678l-evm-hardware-setup-guiderajn]rhaujpKjqhjr]r(jt)r}r(jYX%TMDXEVM6678L EVM Hardware Setup GuiderjZjjbjjdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X%TMDXEVM6678L EVM Hardware Setup Guider–rÖ}rĖ(jYjjZjubaubjZ)rŖ}rƖ(jYUjZjjbjjdj]jf}rǖ(jh]ji]jj]jk]jn]ujpKjqhjr]rȖj`)rɖ}rʖ(jYUjcKjZjŖjbjjdjpjf}r˖(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r̖}r͖(jYXThis page will walk you through setting up your `TMDXEVM6678L `__ Evaluation Module (EVM). These guidelines also apply to the LE and LXE EVM models.jZjjbjjdjjf}rΖ(jh]ji]jj]jk]jn]ujpKjqhjr]rϖ(j{X0This page will walk you through setting up your rЖrі}rҖ(jYX0This page will walk you through setting up your jZj̖ubj)rӖ}rԖ(jYX5`TMDXEVM6678L `__jf}rՖ(UnameX TMDXEVM6678LjX"http://www.ti.com/tool/TMDSEVM6678jk]jj]jh]ji]jn]ujZj̖jr]r֖j{X TMDXEVM6678Lrזrؖ}rٖ(jYUjZjӖubajdjubj{XS Evaluation Module (EVM). These guidelines also apply to the LE and LXE EVM models.rږrۖ}rܖ(jYXS Evaluation Module (EVM). These guidelines also apply to the LE and LXE EVM models.jZj̖ubeubj)rݖ}rޖ(jYXcSome of the steps in this section have been updated from those used in the EVM *Quick Start Guide*.rߖjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjߖjZjݖjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK jr]r(j{XOSome of the steps in this section have been updated from those used in the EVM rr}r(jYXOSome of the steps in this section have been updated from those used in the EVM jZjubj')r}r(jYX*Quick Start Guide*jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XQuick Start Guiderr}r(jYUjZjubajdj'ubj{X.r}r(jYX.jZjubeubaubj[)r}r(jYUjKjZjjbjjdjejf}r(jh]rXhardware setup overviewraji]jj]jk]rUid71rajn]ujpK jqhjr]r(jt)r}r(jYXHardware Setup OverviewrjZjjbjjdjxjf}r(jh]ji]jj]jk]jn]ujpK jqhjr]rj{XHardware Setup Overviewrr}r(jYjjZjubaubj)r}r(jYXcThe picture below shows the TMDXEVM6678L EVM and the locations of relevant switches and connectors.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XcThe picture below shows the TMDXEVM6678L EVM and the locations of relevant switches and connectors.rr}r (jYjjZjubaubjB)r }r (jYX<.. image:: ../images/TMDXEVM6678L-image.jpg :scale: 60 % jZjjbjjdjEjf}r (UscaleKj{XWarningr?r@}rA(jYUjZj;ubajdjubj{X: The EVM board is sensitive to electrostatic discharges (ESD). Use a grounding strap or other device to prevent damaging the board. Be sure to connect communication cables before applying power to any equipment.rBrC}rD(jYX: The EVM board is sensitive to electrostatic discharges (ESD). Use a grounding strap or other device to prevent damaging the board. Be sure to connect communication cables before applying power to any equipment.jZj7ubeubjZ)rE}rF(jYUjZj'jbjjdj]jf}rG(jh]ji]jj]jk]jn]ujpK#jqhjr]rH(j`)rI}rJ(jYUjcKjZjEjbjjdjpjf}rK(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)rL}rM(jYX **1. Attach the Ethernet cable**rNjcKjZjEjbjjdjpjf}rO(jh]ji]jj]jk]jn]ujpK$jqhjr]rPj)rQ}rR(jYjNjf}rS(jh]ji]jj]jk]jn]ujZjLjr]rTj{X1. Attach the Ethernet cablerUrV}rW(jYUjZjQubajdjubaubeubj)rX}rY(jYX}Using the Ethernet cable supplied, connect one end of the cable to the Ethernet port on the EVM and the other end to your PC.rZjZj'jbjjdjjf}r[(jh]ji]jj]jk]jn]ujpK&jqhjr]r\j{X}Using the Ethernet cable supplied, connect one end of the cable to the Ethernet port on the EVM and the other end to your PC.r]r^}r_(jYjZjZjXubaubjZ)r`}ra(jYUjZj'jbjjdj]jf}rb(jh]ji]jj]jk]jn]ujpK)jqhjr]rc(j`)rd}re(jYUjcKjZj`jbjjdjpjf}rf(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)rg}rh(jYX!**2. Connect the JTAG interface**rijcKjZj`jbjjdjpjf}rj(jh]ji]jj]jk]jn]ujpK*jqhjr]rkj)rl}rm(jYjijf}rn(jh]ji]jj]jk]jn]ujZjgjr]roj{X2. Connect the JTAG interfacerprq}rr(jYUjZjlubajdjubaubeubj)rs}rt(jYXUse the USB to USB mini-B cable provided. Connect the USB mini-B connector to the USB mini-B interface on the EVM and the USB connector to your PC. This enables XDS-100 emulation and is directly useable by CCS. If you are using a different JTAG, connect it now.rujZj'jbjjdjjf}rv(jh]ji]jj]jk]jn]ujpK,jqhjr]rwj{XUse the USB to USB mini-B cable provided. Connect the USB mini-B connector to the USB mini-B interface on the EVM and the USB connector to your PC. This enables XDS-100 emulation and is directly useable by CCS. If you are using a different JTAG, connect it now.rxry}rz(jYjujZjsubaubjZ)r{}r|(jYUjZj'jbjjdj]jf}r}(jh]ji]jj]jk]jn]ujpK1jqhjr]r~(j`)r}r(jYUjcKjZj{jbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)r}r(jYX-**3. Verify Endian mode in the SW3 settings**rjcKjZj{jbjjdjpjf}r(jh]ji]jj]jk]jn]ujpK2jqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X)3. Verify Endian mode in the SW3 settingsrr}r(jYUjZjubajdjubaubeubj)r}r(jYX[The Endian mode should be set to Little Endian. SW3 also contains the boot device settings.rjZj'jbjjdjjf}r(jh]ji]jj]jk]jn]ujpK4jqhjr]rj{X[The Endian mode should be set to Little Endian. SW3 also contains the boot device settings.rr}r(jYjjZjubaubjZ)r}r(jYUjZj'jbjjdj]jf}r(jh]ji]jj]jk]jn]ujpK7jqhjr]rj`)r}r(jYUjcKjZjjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjB)r}r(jYX6.. image:: ../images/TMD6678LSW3.png :scale: 40 % jZj'jbjjdjEjf}r(UscaleK(UuriXrtos/../images/TMD6678LSW3.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpNjqhjr]ubjZ)r}r(jYUjZj'jbjjdj]jf}r(jh]ji]jj]jk]jn]ujpK=jqhjr]r(j`)r}r(jYUjcKjZjjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)r}r(jYX1**4. Verify boot mode in the SW3 - SW6 settings**rjcKjZjjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpK>jqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X-4. Verify boot mode in the SW3 - SW6 settingsrr}r(jYUjZjubajdjubaubeubj)r}r(jYXaThe boot mode settings below enable NOR boot by loading the boot loader from EEPROM address 0x51.rjZj'jbjjdjjf}r(jh]ji]jj]jk]jn]ujpK@jqhjr]rj{XaThe boot mode settings below enable NOR boot by loading the boot loader from EEPROM address 0x51.rr}r(jYjjZjubaubjB)r}r(jYX7.. image:: ../images/TMD6678LSW3-6.png :scale: 40 % jZj'jbjjdjEjf}r(UscaleK(UuriX rtos/../images/TMD6678LSW3-6.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpNjqhjr]ubjZ)r—}r×(jYUjZj'jbjjdj]jf}rė(jh]ji]jj]jk]jn]ujpKFjqhjr]rŗ(j`)rƗ}rǗ(jYUjcKjZj—jbjjdjpjf}rȗ(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)rɗ}rʗ(jYX/**5. Set User Switch for the demo application**r˗jcKjZj—jbjjdjpjf}r̗(jh]ji]jj]jk]jn]ujpKGjqhjr]r͗j)rΗ}rϗ(jYj˗jf}rЗ(jh]ji]jj]jk]jn]ujZjɗjr]rїj{X+5. Set User Switch for the demo applicationrҗrӗ}rԗ(jYUjZjΗubajdjubaubeubj)r՗}r֗(jYXThe application needs an IP address. It can use either a static IP address (pre-configured) or it can request one using DHCP. This is controlled by setting dip switch 2 of SW9.rחjZj'jbjjdjjf}rؗ(jh]ji]jj]jk]jn]ujpKIjqhjr]rٗj{XThe application needs an IP address. It can use either a static IP address (pre-configured) or it can request one using DHCP. This is controlled by setting dip switch 2 of SW9.rڗrۗ}rܗ(jYjחjZj՗ubaubjZ)rݗ}rޗ(jYUjZj'jbjjdj]jf}rߗ(jh]ji]jj]jk]jn]ujpKMjqhjr]r(j`)r}r(jYXUser Switch 2 ON : DHCPrjcKjZjݗjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKMjqhjr]rj{XUser Switch 2 ON : DHCPrr}r(jYjjZjubaubj`)r}r(jYXUser Switch 2 OFF: Static IPrjcKjZjݗjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKNjqhjr]rj{XUser Switch 2 OFF: Static IPrr}r(jYjjZjubaubeubjB)r}r(jYX5.. image:: ../images/TMD6678LSW9.png :scale: 50 % jZj'jbjjdjEjf}r(UscaleK2UuriXrtos/../images/TMD6678LSW9.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpNjqhjr]ubjZ)r}r(jYUjZj'jbjjdj]jf}r(jh]ji]jj]jk]jn]ujpKSjqhjr]r(j`)r}r(jYUjcKjZjjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)r}r(jYX#**6. Attach the serial port cable**rjcKjZjjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKTjqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X6. Attach the serial port cablerr}r(jYUjZjubajdjubaubeubj)r }r (jYX"This EVM can use either a USB serial port or the standard DB-9 (use the cable shipped with the platform). By default the shunts which control this on the platforms are set to use the USB by default. We recommend changing them to use the DB-9 as there are no known issues with this approach.r jZj'jbjjdjjf}r (jh]ji]jj]jk]jn]ujpKVjqhjr]r j{X"This EVM can use either a USB serial port or the standard DB-9 (use the cable shipped with the platform). By default the shunts which control this on the platforms are set to use the USB by default. We recommend changing them to use the DB-9 as there are no known issues with this approach.rr}r(jYj jZj ubaubjB)r}r(jYX-.. image:: ../images/TMDXEVM6678L-shunts.jpg jZj'jbjjdjEjf}r(UuriX&rtos/../images/TMDXEVM6678L-shunts.jpgrjk]jj]jh]ji]jH}rU*jsjn]ujpK]jqhjr]ubj)r}r(jYXIf the USB serial port output does not work, ensure that the cable is connected directly to a USB port on the PC/laptop rather than going through an extender or USB hub.rjZj'jbjjdjjf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK^jr]rj{XIf the USB serial port output does not work, ensure that the cable is connected directly to a USB port on the PC/laptop rather than going through an extender or USB hub.rr }r!(jYjjZjubaubaubj)r"}r#(jYX\For the shunts on the alpha/beta Lite EVM, please refer to the picture below for the settingr$jZj'jbjjdjjf}r%(jh]ji]jj]jk]jn]ujpNjqhjr]r&j)r'}r((jYj$jZj"jbjjdjjf}r)(jh]ji]jj]jk]jn]ujpK`jr]r*j{X\For the shunts on the alpha/beta Lite EVM, please refer to the picture below for the settingr+r,}r-(jYj$jZj'ubaubaubjB)r.}r/(jYX(.. image:: ../images/TMD6678LShunts.jpg jZj'jbjjdjEjf}r0(UuriX!rtos/../images/TMD6678LShunts.jpgr1jk]jj]jh]ji]jH}r2U*j1sjn]ujpKbjqhjr]ubjZ)r3}r4(jYUjZj'jbjjdj]jf}r5(jh]ji]jj]jk]jn]ujpKcjqhjr]r6(j`)r7}r8(jYUjcKjZj3jbjjdjpjf}r9(jh]ji]jj]jk]jn]ujpKjqhjr]ubj`)r:}r;(jYX**7. Connect the power cable**r<jcKjZj3jbjjdjpjf}r=(jh]ji]jj]jk]jn]ujpKdjqhjr]r>j)r?}r@(jYj<jf}rA(jh]ji]jj]jk]jn]ujZj:jr]rBj{X7. Connect the power cablerCrD}rE(jYUjZj?ubajdjubaubeubj)rF}rG(jYXConnect the power cable to the EVM power jack on the board. To be ESD safe, plug in the other end of the power cable only after you have connected the power cord to the board. Then turn on the board.rHjZj'jbjjdjjf}rI(jh]ji]jj]jk]jn]ujpKfjqhjr]rJj{XConnect the power cable to the EVM power jack on the board. To be ESD safe, plug in the other end of the power cable only after you have connected the power cord to the board. Then turn on the board.rKrL}rM(jYjHjZjFubaubjZ)rN}rO(jYUjZj'jbjjdj]jf}rP(jh]ji]jj]jk]jn]ujpKjjqhjr]rQj`)rR}rS(jYUjcKjZjNjbjjdjpjf}rT(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubj[)rU}rV(jYUjKjZjjbjjdjejf}rW(jh]rXXboot mode dip switch settingsrYaji]jj]jk]rZUid73r[ajn]ujpKmjqhjr]r\(jt)r]}r^(jYXBoot Mode Dip Switch Settingsr_jZjUjbjjdjxjf}r`(jh]ji]jj]jk]jn]ujpKmjqhjr]raj{XBoot Mode Dip Switch Settingsrbrc}rd(jYj_jZj]ubaubj)re}rf(jYXmThe EVM supports booting image from various devices (EEPROM, NAND or NOR) via IBL (at I2C address 0x51), I2C EEPROM (at I2C address 0x50), and ROM Boot modes (such as Ethernet, SRIO, PCIe, SPI etc.) which address the boot source directly from the ROM code. Below is the table showing the boot mode dip switch settings for different boot mode that the EVM supports:rgjZjUjbjjdjjf}rh(jh]ji]jj]jk]jn]ujpKojqhjr]rij{XmThe EVM supports booting image from various devices (EEPROM, NAND or NOR) via IBL (at I2C address 0x51), I2C EEPROM (at I2C address 0x50), and ROM Boot modes (such as Ethernet, SRIO, PCIe, SPI etc.) which address the boot source directly from the ROM code. Below is the table showing the boot mode dip switch settings for different boot mode that the EVM supports:rjrk}rl(jYjgjZjeubaubjd$)rm}rn(jYUjZjUjbjjdjg$jf}ro(jh]ji]jj]jk]jn]ujpNjqhjr]rpjj$)rq}rr(jYUjf}rs(jk]jj]jh]ji]jn]UcolsKujZjmjr]rt(jo$)ru}rv(jYUjf}rw(jk]jj]jh]ji]jn]UcolwidthKujZjqjr]jdjs$ubjo$)rx}ry(jYUjf}rz(jk]jj]jh]ji]jn]UcolwidthKujZjqjr]jdjs$ubjo$)r{}r|(jYUjf}r}(jk]jj]jh]ji]jn]UcolwidthKujZjqjr]jdjs$ubjo$)r~}r(jYUjf}r(jk]jj]jh]ji]jn]UcolwidthKujZjqjr]jdjs$ubjo$)r}r(jYUjf}r(jk]jj]jh]ji]jn]UcolwidthKujZjqjr]jdjs$ubjz$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjqjr]rj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX Boot ModerjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKwjr]rj{X Boot Moderr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j)r}r(jYXDIP SW3rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKwjr]rj{XDIP SW3rr}r(jYjjZjubaubj)r}r(jYX(Pin1, 2, 3, 4)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKyjr]rj{X(Pin1, 2, 3, 4)rr}r(jYjjZjubaubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j)r}r(jYXDIP SW4rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKwjr]rj{XDIP SW4rr}r(jYjjZjubaubj)r}r(jYX(Pin1, 2, 3, 4)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKyjr]rj{X(Pin1, 2, 3, 4)rr}r(jYjjZjubaubejdj$ubj$)r}r(jYUjf}r˜(jh]ji]jj]jk]jn]ujZjjr]rØ(j)rĘ}rŘ(jYXDIP SW5rƘjZjjbjjdjjf}rǘ(jh]ji]jj]jk]jn]ujpKwjr]rȘj{XDIP SW5rɘrʘ}r˘(jYjƘjZjĘubaubj)r̘}r͘(jYX(Pin1, 2, 3, 4)rΘjZjjbjjdjjf}rϘ(jh]ji]jj]jk]jn]ujpKyjr]rИj{X(Pin1, 2, 3, 4)rјrҘ}rӘ(jYjΘjZj̘ubaubejdj$ubj$)rԘ}r՘(jYUjf}r֘(jh]ji]jj]jk]jn]ujZjjr]rט(j)rؘ}r٘(jYXDIP SW6rژjZjԘjbjjdjjf}rۘ(jh]ji]jj]jk]jn]ujpKwjr]rܘj{XDIP SW6rݘrޘ}rߘ(jYjژjZjؘubaubj)r}r(jYX(Pin1, 2, 3, 4)rjZjԘjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKyjr]rj{X(Pin1, 2, 3, 4)rr}r(jYjjZjubaubejdj$ubejdj$ubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjqjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX"IBL NOR boot on image 0 (default)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK|jr]rj{X"IBL NOR boot on image 0 (default)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX (off, off, on, off)\ :sup:`1, 2`jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK|jr]r(j{X(off, off, on, off)rr}r(jYX(off, off, on, off)\ jZjubj)r}r(jYX :sup:`1, 2`jf}r (jh]ji]jj]jk]jn]ujZjjr]r j{X1, 2r r }r (jYUjZjubajdjubeubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX(on, on, on, on)\ :sup:`3`jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK|jr]r(j{X(on, on, on, on)rr}r(jYX(on, on, on, on)\ jZjubj)r}r(jYX:sup:`3`jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X3r}r(jYUjZjubajdjubeubajdj$ubj$)r}r (jYUjf}r!(jh]ji]jj]jk]jn]ujZjjr]r"j)r#}r$(jYX(on, on, on, off)\ :sup:`4`jZjjbjjdjjf}r%(jh]ji]jj]jk]jn]ujpK|jr]r&(j{X(on, on, on, off)r'r(}r)(jYX(on, on, on, off)\ jZj#ubj)r*}r+(jYX:sup:`4`jf}r,(jh]ji]jj]jk]jn]ujZj#jr]r-j{X4r.}r/(jYUjZj*ubajdjubeubajdj$ubj$)r0}r1(jYUjf}r2(jh]ji]jj]jk]jn]ujZjjr]r3j)r4}r5(jYX(on, on, on, on)r6jZj0jbjjdjjf}r7(jh]ji]jj]jk]jn]ujpK|jr]r8j{X(on, on, on, on)r9r:}r;(jYj6jZj4ubaubajdj$ubejdj$ubj$)r<}r=(jYUjf}r>(jh]ji]jj]jk]jn]ujZjjr]r?(j$)r@}rA(jYUjf}rB(jh]ji]jj]jk]jn]ujZj<jr]rCj)rD}rE(jYXIBL NOR boot on image 1rFjZj@jbjjdjjf}rG(jh]ji]jj]jk]jn]ujpKjr]rHj{XIBL NOR boot on image 1rIrJ}rK(jYjFjZjDubaubajdj$ubj$)rL}rM(jYUjf}rN(jh]ji]jj]jk]jn]ujZj<jr]rOj)rP}rQ(jYX(off, off, on, off)rRjZjLjbjjdjjf}rS(jh]ji]jj]jk]jn]ujpKjr]rTj{X(off, off, on, off)rUrV}rW(jYjRjZjPubaubajdj$ubj$)rX}rY(jYUjf}rZ(jh]ji]jj]jk]jn]ujZj<jr]r[j)r\}r](jYX(off, on, on, on)r^jZjXjbjjdjjf}r_(jh]ji]jj]jk]jn]ujpKjr]r`j{X(off, on, on, on)rarb}rc(jYj^jZj\ubaubajdj$ubj$)rd}re(jYUjf}rf(jh]ji]jj]jk]jn]ujZj<jr]rgj)rh}ri(jYX(on, on, on, off)rjjZjdjbjjdjjf}rk(jh]ji]jj]jk]jn]ujpKjr]rlj{X(on, on, on, off)rmrn}ro(jYjjjZjhubaubajdj$ubj$)rp}rq(jYUjf}rr(jh]ji]jj]jk]jn]ujZj<jr]rsj)rt}ru(jYX(on, on, on, on)rvjZjpjbjjdjjf}rw(jh]ji]jj]jk]jn]ujpKjr]rxj{X(on, on, on, on)ryrz}r{(jYjvjZjtubaubajdj$ubejdj$ubj$)r|}r}(jYUjf}r~(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj|jr]rj)r}r(jYXIBL NAND boot on image 0rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XIBL NAND boot on image 0rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj|jr]rj)r}r(jYX(off, off, on, off)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X(off, off, on, off)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj|jr]rj)r}r(jYX(on, off, on, on)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X(on, off, on, on)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj|jr]rj)r}r(jYX(on, on, on, off)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X(on, on, on, off)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj|jr]rj)r}r(jYX(on, on, on, on)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X(on, on, on, on)rr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r™(jh]ji]jj]jk]jn]ujZjjr]rÙj)rę}rř(jYXIBL NAND boot on image 1rƙjZjjbjjdjjf}rǙ(jh]ji]jj]jk]jn]ujpKjr]rșj{XIBL NAND boot on image 1rərʙ}r˙(jYjƙjZjęubaubajdj$ubj$)r̙}r͙(jYUjf}rΙ(jh]ji]jj]jk]jn]ujZjjr]rϙj)rЙ}rљ(jYX(off, off, on, off)rҙjZj̙jbjjdjjf}rә(jh]ji]jj]jk]jn]ujpKjr]rԙj{X(off, off, on, off)rՙr֙}rי(jYjҙjZjЙubaubajdj$ubj$)rؙ}rٙ(jYUjf}rڙ(jh]ji]jj]jk]jn]ujZjjr]rۙj)rܙ}rݙ(jYX(off, off, on, on)rޙjZjؙjbjjdjjf}rߙ(jh]ji]jj]jk]jn]ujpKjr]rj{X(off, off, on, on)rr}r(jYjޙjZjܙubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX(on, on, on, off)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X(on, on, on, off)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX(on, on, on, on)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X(on, on, on, on)rr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX IBL TFTP bootrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X IBL TFTP bootr r }r (jYjjZjubaubajdj$ubj$)r }r (jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX(off, off, on, off)rjZj jbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X(off, off, on, off)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX(on, on, off, on)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]r j{X(on, on, off, on)r!r"}r#(jYjjZjubaubajdj$ubj$)r$}r%(jYUjf}r&(jh]ji]jj]jk]jn]ujZjjr]r'j)r(}r)(jYX(on, on, on, off)r*jZj$jbjjdjjf}r+(jh]ji]jj]jk]jn]ujpKjr]r,j{X(on, on, on, off)r-r.}r/(jYj*jZj(ubaubajdj$ubj$)r0}r1(jYUjf}r2(jh]ji]jj]jk]jn]ujZjjr]r3j)r4}r5(jYX(on, on, on, on)r6jZj0jbjjdjjf}r7(jh]ji]jj]jk]jn]ujpKjr]r8j{X(on, on, on, on)r9r:}r;(jYj6jZj4ubaubajdj$ubejdj$ubj$)r<}r=(jYUjf}r>(jh]ji]jj]jk]jn]ujZjjr]r?(j$)r@}rA(jYUjf}rB(jh]ji]jj]jk]jn]ujZj<jr]rCj)rD}rE(jYX I2C POST bootrFjZj@jbjjdjjf}rG(jh]ji]jj]jk]jn]ujpKjr]rHj{X I2C POST bootrIrJ}rK(jYjFjZjDubaubajdj$ubj$)rL}rM(jYUjf}rN(jh]ji]jj]jk]jn]ujZj<jr]rOj)rP}rQ(jYX(off, off, on, off)rRjZjLjbjjdjjf}rS(jh]ji]jj]jk]jn]ujpKjr]rTj{X(off, off, on, off)rUrV}rW(jYjRjZjPubaubajdj$ubj$)rX}rY(jYUjf}rZ(jh]ji]jj]jk]jn]ujZj<jr]r[j)r\}r](jYX(on, on, on, on)r^jZjXjbjjdjjf}r_(jh]ji]jj]jk]jn]ujpKjr]r`j{X(on, on, on, on)rarb}rc(jYj^jZj\ubaubajdj$ubj$)rd}re(jYUjf}rf(jh]ji]jj]jk]jn]ujZj<jr]rgj)rh}ri(jYX(on, on, on, on)rjjZjdjbjjdjjf}rk(jh]ji]jj]jk]jn]ujpKjr]rlj{X(on, on, on, on)rmrn}ro(jYjjjZjhubaubajdj$ubj$)rp}rq(jYUjf}rr(jh]ji]jj]jk]jn]ujZj<jr]rsj)rt}ru(jYX(on, on, on, on)rvjZjpjbjjdjjf}rw(jh]ji]jj]jk]jn]ujpKjr]rxj{X(on, on, on, on)ryrz}r{(jYjvjZjtubaubajdj$ubejdj$ubj$)r|}r}(jYUjf}r~(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj|jr]rj)r}r(jYXROM SPI Boot\ :sup:`8`jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]r(j{X ROM SPI Bootrr}r(jYXROM SPI Boot\ jZjubj)r}r(jYX:sup:`8`jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X8r}r(jYUjZjubajdjubeubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj|jr]rj)r}r(jYX(off, on, off, off)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X(off, on, off, off)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj|jr]rj)r}r(jYX(on, on, on, on)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X(on, on, on, on)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj|jr]rj)r}r(jYX(on, on, off, on)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X(on, on, off, on)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj|jr]rj)r}r(jYX(on, on, on, on)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X(on, on, on, on)rr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}rš(jYUjf}rÚ(jh]ji]jj]jk]jn]ujZjjr]rĚ(j$)rŚ}rƚ(jYUjf}rǚ(jh]ji]jj]jk]jn]ujZjjr]rȚj)rɚ}rʚ(jYXROM SRIO Boot\ :sup:`5`jZjŚjbjjdjjf}r˚(jh]ji]jj]jk]jn]ujpKjr]r̚(j{X ROM SRIO Bootr͚rΚ}rϚ(jYXROM SRIO Boot\ jZjɚubj)rК}rњ(jYX:sup:`5`jf}rҚ(jh]ji]jj]jk]jn]ujZjɚjr]rӚj{X5rԚ}r՚(jYUjZjКubajdjubeubajdj$ubj$)r֚}rך(jYUjf}rؚ(jh]ji]jj]jk]jn]ujZjjr]rٚj)rښ}rۚ(jYX(off, off, on, on)rܚjZj֚jbjjdjjf}rݚ(jh]ji]jj]jk]jn]ujpKjr]rޚj{X(off, off, on, on)rߚr}r(jYjܚjZjښubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX(on, on, on, off)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X(on, on, on, off)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX(on, off, on, off)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X(on, off, on, off)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX(off, on, on, on)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X(off, on, on, on)rr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r (j$)r }r (jYUjf}r (jh]ji]jj]jk]jn]ujZjjr]r j)r}r(jYXROM Ethernet Boot\ :sup:`6`jZj jbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]r(j{XROM Ethernet Bootrr}r(jYXROM Ethernet Boot\ jZjubj)r}r(jYX:sup:`6`jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X6r}r(jYUjZjubajdjubeubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r (jYX(off, on, off, on)r!jZjjbjjdjjf}r"(jh]ji]jj]jk]jn]ujpKjr]r#j{X(off, on, off, on)r$r%}r&(jYj!jZjubaubajdj$ubj$)r'}r((jYUjf}r)(jh]ji]jj]jk]jn]ujZjjr]r*j)r+}r,(jYX(on, on, on, off)r-jZj'jbjjdjjf}r.(jh]ji]jj]jk]jn]ujpKjr]r/j{X(on, on, on, off)r0r1}r2(jYj-jZj+ubaubajdj$ubj$)r3}r4(jYUjf}r5(jh]ji]jj]jk]jn]ujZjjr]r6j)r7}r8(jYX(on, on, off, off)r9jZj3jbjjdjjf}r:(jh]ji]jj]jk]jn]ujpKjr]r;j{X(on, on, off, off)r<r=}r>(jYj9jZj7ubaubajdj$ubj$)r?}r@(jYUjf}rA(jh]ji]jj]jk]jn]ujZjjr]rBj)rC}rD(jYX(off, on, on, on)rEjZj?jbjjdjjf}rF(jh]ji]jj]jk]jn]ujpKjr]rGj{X(off, on, on, on)rHrI}rJ(jYjEjZjCubaubajdj$ubejdj$ubj$)rK}rL(jYUjf}rM(jh]ji]jj]jk]jn]ujZjjr]rN(j$)rO}rP(jYUjf}rQ(jh]ji]jj]jk]jn]ujZjKjr]rRj)rS}rT(jYXROM PCIE Boot\ :sup:`7`jZjOjbjjdjjf}rU(jh]ji]jj]jk]jn]ujpKjr]rV(j{X ROM PCIE BootrWrX}rY(jYXROM PCIE Boot\ jZjSubj)rZ}r[(jYX:sup:`7`jf}r\(jh]ji]jj]jk]jn]ujZjSjr]r]j{X7r^}r_(jYUjZjZubajdjubeubajdj$ubj$)r`}ra(jYUjf}rb(jh]ji]jj]jk]jn]ujZjKjr]rcj)rd}re(jYX(off, on, on, off)rfjZj`jbjjdjjf}rg(jh]ji]jj]jk]jn]ujpKjr]rhj{X(off, on, on, off)rirj}rk(jYjfjZjdubaubajdj$ubj$)rl}rm(jYUjf}rn(jh]ji]jj]jk]jn]ujZjKjr]roj)rp}rq(jYX(on, on, on, on)rrjZjljbjjdjjf}rs(jh]ji]jj]jk]jn]ujpKjr]rtj{X(on, on, on, on)rurv}rw(jYjrjZjpubaubajdj$ubj$)rx}ry(jYUjf}rz(jh]ji]jj]jk]jn]ujZjKjr]r{j)r|}r}(jYX(on, on, on, off)r~jZjxjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X(on, on, on, off)rr}r(jYj~jZj|ubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjKjr]rj)r}r(jYX(off, on, on, on)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X(off, on, on, on)rr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXNo bootrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XNo bootrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX(off, on, on, on)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X(off, on, on, on)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX(on, on, on, on)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X(on, on, on, on)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX(on, on, on, on)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X(on, on, on, on)rr›}rÛ(jYjjZjubaubajdj$ubj$)rě}rś(jYUjf}rƛ(jh]ji]jj]jk]jn]ujZjjr]rǛj)rț}rɛ(jYX(on, on, on, on)rʛjZjějbjjdjjf}r˛(jh]ji]jj]jk]jn]ujpKjr]r̛j{X(on, on, on, on)r͛rΛ}rϛ(jYjʛjZjțubaubajdj$ubejdj$ubejdjy%ubejdjz%ubaubjZ)rЛ}rћ(jYUjZjUjbjjdj]jf}rқ(jh]ji]jj]jk]jn]ujpKjqhjr]rӛj`)rԛ}r՛(jYUjcKjZjЛjbjjdjpjf}r֛(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjZ)rכ}r؛(jYUjZjUjbjjdj]jf}rٛ(jh]ji]jj]jk]jn]ujpKjqhjr]rڛj`)rۛ}rܛ(jYX**Footnotes:**rݛjcKjZjכjbjjdjpjf}rޛ(jh]ji]jj]jk]jn]ujpKjqhjr]rߛj)r}r(jYjݛjf}r(jh]ji]jj]jk]jn]ujZjۛjr]rj{X Footnotes:rr}r(jYUjZjubajdjubaubaubj)r}r(jYXR1. Pin 1 of SW3 is the endian pin, by default, it is set to off (Little Endian)rjZjUjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XR1. Pin 1 of SW3 is the endian pin, by default, it is set to off (Little Endian)rr}r(jYjjZjubaubj)r}r(jYX`2. Pin 2-4 of SW3 are the boot mode pins, by default it is set to I2C boot mode (off, on, off)rjZjUjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X`2. Pin 2-4 of SW3 are the boot mode pins, by default it is set to I2C boot mode (off, on, off)rr}r(jYjjZjubaubj)r}r(jYX3. Pin 1-4 of SW4 and pin 1-2 of SW5 are the boot parameter index pins for I2C boot (paramter index 0/1 for NOR boot image 0/1, parameter index 2/3 for NAND boot image 0/1, parameter index 4 for TFTP boot). By default, image 0 is programmed to offset byte address 0x0 on NOR, and 0x4000 (block 1 start address) on NAND, image 1 is programmed to offset byte address 0xA00000 on NOR, and 0x2000000 on NAND.rjZjUjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X3. Pin 1-4 of SW4 and pin 1-2 of SW5 are the boot parameter index pins for I2C boot (paramter index 0/1 for NOR boot image 0/1, parameter index 2/3 for NAND boot image 0/1, parameter index 4 for TFTP boot). By default, image 0 is programmed to offset byte address 0x0 on NOR, and 0x4000 (block 1 start address) on NAND, image 1 is programmed to offset byte address 0xA00000 on NOR, and 0x2000000 on NAND.rr}r(jYjjZjubaubj)r}r(jYXQ4. Pin 4 of SW5 is the I2C address pin (off: 0x51, on: 0x50)  for I2C boot moderjZjUjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XQ4. Pin 4 of SW5 is the I2C address pin (off: 0x51, on: 0x50)  for I2C boot moderr}r(jYjjZjubaubj)r}r(jYX5. This will set the board to boot from SRIO boot mode, with reference clock at 312.5 MHz, data rate at 3.125 GBs, and lane setup 4-1x ports and DSP System PLL at 100 MHz.r jZjUjbjjdjjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r j{X5. This will set the board to boot from SRIO boot mode, with reference clock at 312.5 MHz, data rate at 3.125 GBs, and lane setup 4-1x ports and DSP System PLL at 100 MHz.r r }r(jYj jZjubaubj)r}r(jYXy6. This will set the board to boot from Ethernet boot mode, with SerDes clock multiplier x 4, core PLL clock at 100 MHz.rjZjUjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{Xy6. This will set the board to boot from Ethernet boot mode, with SerDes clock multiplier x 4, core PLL clock at 100 MHz.rr}r(jYjjZjubaubj)r}r(jYXr7. This will set the board to boot form PCIE boot mode, with PCIE in end point mode and DSP System PLL at 100 MHz.rjZjUjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{Xr7. This will set the board to boot form PCIE boot mode, with PCIE in end point mode and DSP System PLL at 100 MHz.rr}r(jYjjZjubaubj)r}r (jYX8. This will set the board to boot from SPI NOR via the ROM code, with boot-table contents expected in the NOR. 24bit addressing has been set.r!jZjUjbjjdjjf}r"(jh]ji]jj]jk]jn]ujpKjqhjr]r#j{X8. This will set the board to boot from SPI NOR via the ROM code, with boot-table contents expected in the NOR. 24bit addressing has been set.r$r%}r&(jYj!jZjubaubjZ)r'}r((jYUjZjUjbjjdj]jf}r)(jh]ji]jj]jk]jn]ujpKjqhjr]r*j`)r+}r,(jYUjcKjZj'jbjjdjpjf}r-(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r.}r/(jYXPlease refer to `Technical Reference Manual `__ for the boot mode switch settings on the board.jZjUjbjjdjjf}r0(jh]ji]jj]jk]jn]ujpKjqhjr]r1(j{XPlease refer to r2r3}r4(jYXPlease refer to jZj.ubj)r5}r6(jYXW`Technical Reference Manual `__jf}r7(UnameXTechnical Reference ManualjX6http://www.advantech.com/Support/TI-EVM/6678le_sd.aspxjk]jj]jh]ji]jn]ujZj.jr]r8j{XTechnical Reference Manualr9r:}r;(jYUjZj5ubajdjubj{X0 for the boot mode switch settings on the board.r<r=}r>(jYX0 for the boot mode switch settings on the board.jZj.ubeubj)r?}r@(jYX#OMAP-L138/C6748 LCDK Hardware SetupjZjUjbjcjdjjf}rA(jjjk]jj]jh]ji]jn]ujpKjqhjr]rBj{X#OMAP-L138/C6748 LCDK Hardware SetuprCrD}rE(jYUjZj?ubaubj)rF}rG(jYX4====================================================jZjUjbjcjdjjf}rH(jjjk]jj]jh]ji]jn]ujpKjqhjr]rIj{X4====================================================rJrK}rL(jYUjZjFubaubeubeubj[)rM}rN(jYUjZjR\jbjXKsource/common/EVM_Hardware_Setup/OMAPL138-C6748_LCDK_Hardware_Setup.rst.incrOrP}rQbjdjejf}rR(jh]ji]jj]jk]rSU#omap-l138-c6748-lcdk-hardware-setuprTajn]rUjaujpKjqhjr]rV(jt)rW}rX(jYX#OMAP-L138/C6748 LCDK Hardware SetuprYjZjMjbjPjdjxjf}rZ(jh]ji]jj]jk]jn]ujpKjqhjr]r[j{X#OMAP-L138/C6748 LCDK Hardware Setupr\r]}r^(jYjYjZjWubaubj[)r_}r`(jYUjKjZjMjbjPjdjejf}ra(jh]rbXoverviewrcaji]jj]jk]rdUid74reajn]ujpKjqhjr]rf(jt)rg}rh(jYXOverviewrijZj_jbjPjdjxjf}rj(jh]ji]jj]jk]jn]ujpKjqhjr]rkj{XOverviewrlrm}rn(jYjijZjgubaubj)ro}rp(jYX The OMAP-L138/C6748 low-cost development kit (LCDK) enables fast and easy software and hardware development of everyday applications that require real-time signal processing and control functional, including industrial control, medical diagnostics and communications.rqjZj_jbjPjdjjf}rr(jh]ji]jj]jk]jn]ujpKjqhjr]rsj{X The OMAP-L138/C6748 low-cost development kit (LCDK) enables fast and easy software and hardware development of everyday applications that require real-time signal processing and control functional, including industrial control, medical diagnostics and communications.rtru}rv(jYjqjZjoubaubj[)rw}rx(jYUjKjZj_jbjPjdjejf}ry(jh]rzjaji]jj]jk]r{Uid75r|ajn]ujpK jqhjr]r}(jt)r~}r(jYXHardwarerjZjwjbjPjdjxjf}r(jh]ji]jj]jk]jn]ujpK jqhjr]rj{XHardwarerr}r(jYjjZj~ubaubj)r}r(jYXInformation on the LCDK hardware, including DIP switches, LEDs, and user bottons, can be found in the LCDK User's Guide at the following link.rjZjwjbjPjdjjf}r(jh]ji]jj]jk]jn]ujpK jqhjr]rj{XInformation on the LCDK hardware, including DIP switches, LEDs, and user bottons, can be found in the LCDK User's Guide at the following link.rr}r(jYjjZjubaubj)r}r(jYXh`OMAP-L138/C6748 Low-Cost Development Kit User's Guide `__rjZjwjbjPjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj)r}r(jYjjf}r(UnameX5OMAP-L138/C6748 Low-Cost Development Kit User's GuidejX,http://www.ti.com/lit/ug/spruil2/spruil2.pdfjk]jj]jh]ji]jn]ujZjjr]rj{X5OMAP-L138/C6748 Low-Cost Development Kit User's Guiderr}r(jYUjZjubajdjubaubeubj[)r}r(jYUjZj_jbjPjdjejf}r(jh]ji]jj]jk]rUpowering-the-lcdkrajn]rjaujpKjqhjr]r(jt)r}r(jYXPowering the LCDKrjZjjbjPjdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XPowering the LCDKrr}r(jYjjZjubaubj)r}r(jYXGThe board can be powered with 5V input through the J1 barrel connector.rjZjjbjPjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XGThe board can be powered with 5V input through the J1 barrel connector.rr}r(jYjjZjubaubeubj[)r}r(jYUjKjZj_jbjPjdjejf}r(jh]rXuart connectionraji]jj]jk]rUid76rajn]ujpKjqhjr]r(jt)r}r(jYXUART ConnectionrjZjjbjPjdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XUART Connectionrr}r(jYjjZjubaubj)r}rœ(jYXConnect a mini-USB cable between UART port (J3) of the EVM and the host PC. Open a serial console (e.g. Tera Term) on the host PC and configure the serial port as follows.rÜjZjjbjPjdjjf}rĜ(jh]ji]jj]jk]jn]ujpKjqhjr]rŜj{XConnect a mini-USB cable between UART port (J3) of the EVM and the host PC. Open a serial console (e.g. Tera Term) on the host PC and configure the serial port as follows.rƜrǜ}rȜ(jYjÜjZjubaubj=)rɜ}rʜ(jYUjZjjbNjdj@jf}r˜(jh]ji]jj]jk]jn]ujpNjqhjr]r̜jC)r͜}rΜ(jYUjf}rϜ(jGX-jk]jj]jh]ji]jn]ujZjɜjr]rМ(j/)rќ}rҜ(jYXBaud rate - 115200rӜjf}rԜ(jh]ji]jj]jk]jn]ujZj͜jr]r՜j)r֜}rל(jYjӜjZjќjbjPjdjjf}r؜(jh]ji]jj]jk]jn]ujpKjr]rٜj{XBaud rate - 115200rڜrۜ}rܜ(jYjӜjZj֜ubaubajdj2ubj/)rݜ}rޜ(jYXData length - 8 bitrߜjf}r(jh]ji]jj]jk]jn]ujZj͜jr]rj)r}r(jYjߜjZjݜjbjPjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XData length - 8 bitrr}r(jYjߜjZjubaubajdj2ubj/)r}r(jYX Parity - Nonerjf}r(jh]ji]jj]jk]jn]ujZj͜jr]rj)r}r(jYjjZjjbjPjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X Parity - Nonerr}r(jYjjZjubaubajdj2ubj/)r}r(jYX Stop bits - 1rjf}r(jh]ji]jj]jk]jn]ujZj͜jr]rj)r}r(jYjjZjjbjPjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X Stop bits - 1rr}r(jYjjZjubaubajdj2ubj/)r}r(jYXFlow control - None jf}r(jh]ji]jj]jk]jn]ujZj͜jr]rj)r}r(jYXFlow control - NonerjZjjbjPjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]r j{XFlow control - Noner r }r (jYjjZjubaubajdj2ubejdj`ubaubeubeubj[)r }r(jYUjZjMjbjPjdjejf}r(jh]ji]jj]jk]rUlinux-quick-start-guiderajn]rhSaujpK jqhjr]r(jt)r}r(jYXLinux Quick Start GuiderjZj jbjPjdjxjf}r(jh]ji]jj]jk]jn]ujpK jqhjr]rj{XLinux Quick Start Guiderr}r(jYjjZjubaubj)r}r(jYX[The quick start guide for booting Linux on the Arm core can be found at the following link.rjZj jbjPjdjjf}r(jh]ji]jj]jk]jn]ujpK"jqhjr]r j{X[The quick start guide for booting Linux on the Arm core can be found at the following link.r!r"}r#(jYjjZjubaubj)r$}r%(jYXs`OMAP-L138 DSP+ARM9™ Development Kit (LCDK) Quick Start Guide `__r&jZj jbjPjdjjf}r'(jh]ji]jj]jk]jn]ujpK$jqhjr]r(j)r)}r*(jYj&jf}r+(UnameX>OMAP-L138 DSP+ARM9™ Development Kit (LCDK) Quick Start GuidejX.http://www.ti.com/lit/ml/sprw268a/sprw268a.pdfjk]jj]jh]ji]jn]ujZj$jr]r,j{X>OMAP-L138 DSP+ARM9™ Development Kit (LCDK) Quick Start Guider-r.}r/(jYUjZj)ubajdjubaubeubj[)r0}r1(jYUjZjMjbjPjdjejf}r2(jh]ji]jj]jk]r3U+connecting-the-lcdk-to-code-composer-studior4ajn]r5haujpK'jqhjr]r6(jt)r7}r8(jYX+Connecting the LCDK to Code Composer Studior9jZj0jbjPjdjxjf}r:(jh]ji]jj]jk]jn]ujpK'jqhjr]r;j{X+Connecting the LCDK to Code Composer Studior<r=}r>(jYj9jZj7ubaubj)r?}r@(jYXwThe following section describes how to connect to the LCDK and load code via CCS for application development and debug.rAjZj0jbjPjdjjf}rB(jh]ji]jj]jk]jn]ujpK)jqhjr]rCj{XwThe following section describes how to connect to the LCDK and load code via CCS for application development and debug.rDrE}rF(jYjAjZj?ubaubj[)rG}rH(jYUjKjZj0jbjPjdjejf}rI(jh]rJXhardware setuprKaji]jj]jk]rLUid77rMajn]ujpK,jqhjr]rN(jt)rO}rP(jYXHardware SetuprQjZjGjbjPjdjxjf}rR(jh]ji]jj]jk]jn]ujpK,jqhjr]rSj{XHardware SetuprTrU}rV(jYjQjZjOubaubjC)rW}rX(jYUjZjGjbjPjdj`jf}rY(jGX-jk]jj]jh]ji]jn]ujpK.jqhjr]rZ(j/)r[}r\(jYXSSet the SW1 DIP switches to UART boot mode as shown in the `DIP Switches`_ section.r]jZjWjbjPjdj2jf}r^(jh]ji]jj]jk]jn]ujpNjqhjr]r_j)r`}ra(jYj]jZj[jbjPjdjjf}rb(jh]ji]jj]jk]jn]ujpK.jr]rc(j{X;Set the SW1 DIP switches to UART boot mode as shown in the rdre}rf(jYX;Set the SW1 DIP switches to UART boot mode as shown in the jZj`ubj)rg}rh(jYX`DIP Switches`_rijf}rj(jk]rkUid90rlajj]jh]ji]jn]UrefidUid89rmujZj`jr]rnj{X`DIP Switches`_rorp}rq(jYUjZjgubajdjubj{X section.rrrs}rt(jYX section.jZj`ubeubaubj/)ru}rv(jYX.Connect an external emulator to the J6 header.rwjZjWjbjPjdj2jf}rx(jh]ji]jj]jk]jn]ujpNjqhjr]ryj)rz}r{(jYjwjZjujbjPjdjjf}r|(jh]ji]jj]jk]jn]ujpK/jr]r}j{X.Connect an external emulator to the J6 header.r~r}r(jYjwjZjzubaubaubj/)r}r(jYX1Power on the LCDK using the J1 barrel connector. jZjWjbjPjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYX0Power on the LCDK using the J1 barrel connector.rjZjjbjPjdjjf}r(jh]ji]jj]jk]jn]ujpK0jr]rj{X0Power on the LCDK using the J1 barrel connector.rr}r(jYjjZjubaubaubeubeubj[)r}r(jYUjZj0jbjPjdjejf}r(jh]ji]jj]jk]rUsoftware-setuprajn]rhaujpK3jqhjr]r(jt)r}r(jYXSoftware SetuprjZjjbjPjdjxjf}r(jh]ji]jj]jk]jn]ujpK3jqhjr]rj{XSoftware Setuprr}r(jYjjZjubaubjC)r}r(jYUjZjjbjPjdj`jf}r(jGX-jk]jj]jh]ji]jn]ujpK5jqhjr]rj/)r}r(jYXJCode Composer Studio IDE - `Download `__ jZjjbjPjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXICode Composer Studio IDE - `Download `__jZjjbjPjdjjf}r(jh]ji]jj]jk]jn]ujpK5jr]r(j{XCode Composer Studio IDE - rr}r(jYXCode Composer Studio IDE - jZjubj)r}r(jYX.`Download `__jf}r(UnameXDownloadjXhttp://www.ti.com/tool/CCSTUDIOjk]jj]jh]ji]jn]ujZjjr]rj{XDownloadrr}r(jYUjZjubajdjubeubaubaubj)r}r(jYXCCS versions 9.0 and later are 64-bit applications. Due to this, 32-bit emulators like the Spectrum Digital XDS510USB emulator are not supported with CCS versions 9.0 and later.rjZjjbjPjdjjf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbjPjdjjf}r(jh]ji]jj]jk]jn]ujpK7jr]rj{XCCS versions 9.0 and later are 64-bit applications. Due to this, 32-bit emulators like the Spectrum Digital XDS510USB emulator are not supported with CCS versions 9.0 and later.rr}r(jYjjZjubaubaubjC)r}r(jYUjZjjbjPjdj`jf}r(jGX-jk]jj]jh]ji]jn]ujpK9jqhjr]rj/)r}rÝ(jYXfProcessor SDK RTOS for OMAP-L138/C6748 - `Download `__ jZjjbjPjdj2jf}rĝ(jh]ji]jj]jk]jn]ujpNjqhjr]rŝj)rƝ}rǝ(jYXeProcessor SDK RTOS for OMAP-L138/C6748 - `Download `__jZjjbjPjdjjf}rȝ(jh]ji]jj]jk]jn]ujpK9jr]rɝ(j{X)Processor SDK RTOS for OMAP-L138/C6748 - rʝr˝}r̝(jYX)Processor SDK RTOS for OMAP-L138/C6748 - jZjƝubj)r͝}rΝ(jYX<`Download `__jf}rϝ(UnameXDownloadjX-http://www.ti.com/tool/PROCESSOR-SDK-OMAPL138jk]jj]jh]ji]jn]ujZjƝjr]rНj{XDownloadrѝrҝ}rӝ(jYUjZj͝ubajdjubeubaubaubj)rԝ}r՝(jYXPlease check the `Processor SDK Release Notes `__ for the recommended CCS version.r֝jZjjbjPjdjjf}rם(jh]ji]jj]jk]jn]ujpNjqhjr]r؝j)rٝ}rڝ(jYj֝jZjԝjbjPjdjjf}r۝(jh]ji]jj]jk]jn]ujpK;jr]rܝ(j{XPlease check the rݝrޝ}rߝ(jYXPlease check the jZjٝubj)r}r(jYX`Processor SDK Release Notes `__jf}r(UnameXProcessor SDK Release NotesjXkhttp://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_release_specific.html#release-notesjk]jj]jh]ji]jn]ujZjٝjr]rj{XProcessor SDK Release Notesrr}r(jYUjZjubajdjubj{X! for the recommended CCS version.rr}r(jYX! for the recommended CCS version.jZjٝubeubaubjC)r}r(jYUjZjjbjPjdj`jf}r(jGX-jk]jj]jh]ji]jn]ujpK=jqhjr]r(j/)r}r(jYXSetup the software environment as described in the "Download and install software" section of the `Processor SDK RTOS Getting Started Guide `__ jZjjbjPjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXSetup the software environment as described in the "Download and install software" section of the `Processor SDK RTOS Getting Started Guide `__jZjjbjPjdjjf}r(jh]ji]jj]jk]jn]ujpK=jr]r(j{XbSetup the software environment as described in the "Download and install software" section of the rr}r(jYXbSetup the software environment as described in the "Download and install software" section of the jZjubj)r}r(jYX`Processor SDK RTOS Getting Started Guide `__jf}r(UnameX(Processor SDK RTOS Getting Started GuidejXshttp://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_overview.html#download-and-install-softwarejk]jj]jh]ji]jn]ujZjjr]rj{X(Processor SDK RTOS Getting Started Guiderr}r(jYUjZjubajdjubeubaubj/)r}r(jYXBuild an example. Below are some suggested examples to get started with. - `No OS (Bare Metal) Example `__ - `TI-RTOS Kernel Example `__ - `GPIO LED Blink Example `__ jZjjbjPjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]r(j)r}r(jYXHBuild an example. Below are some suggested examples to get started with.rjZjjbjPjdjjf}r(jh]ji]jj]jk]jn]ujpK?jr]rj{XHBuild an example. Below are some suggested examples to get started with.r r }r (jYjjZjubaubj=)r }r (jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rjC)r}r(jYUjf}r(jGX-jk]jj]jh]ji]jn]ujZj jr]r(j/)r}r(jYX`No OS (Bare Metal) Example `__ jf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX`No OS (Bare Metal) Example `__rjZjjbjPjdjjf}r(jh]ji]jj]jk]jn]ujpKAjr]rj)r}r(jYjjf}r(UnameXNo OS (Bare Metal) ExamplejX`http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_examples_demos.html#id53jk]jj]jh]ji]jn]ujZjjr]r j{XNo OS (Bare Metal) Exampler!r"}r#(jYUjZjubajdjubaubajdj2ubj/)r$}r%(jYX`TI-RTOS Kernel Example `__ jf}r&(jh]ji]jj]jk]jn]ujZjjr]r'j)r(}r)(jYX`TI-RTOS Kernel Example `__r*jZj$jbjPjdjjf}r+(jh]ji]jj]jk]jn]ujpKCjr]r,j)r-}r.(jYj*jf}r/(UnameXTI-RTOS Kernel ExamplejXehttp://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_examples_demos.html#dsp-c674xjk]jj]jh]ji]jn]ujZj(jr]r0j{XTI-RTOS Kernel Exampler1r2}r3(jYUjZj-ubajdjubaubajdj2ubj/)r4}r5(jYXz`GPIO LED Blink Example `__ jf}r6(jh]ji]jj]jk]jn]ujZjjr]r7j)r8}r9(jYXy`GPIO LED Blink Example `__r:jZj4jbjPjdjjf}r;(jh]ji]jj]jk]jn]ujpKEjr]r<j)r=}r>(jYj:jf}r?(UnameXGPIO LED Blink ExamplejX\http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_device_drv.html#id22jk]jj]jh]ji]jn]ujZj8jr]r@j{XGPIO LED Blink ExamplerArB}rC(jYUjZj=ubajdjubaubajdj2ubejdj`ubajdj@ubeubeubeubj[)rD}rE(jYUjZj0jbjPjdjejf}rF(jh]ji]jj]jk]rGU$creating-a-target-configuration-filerHajn]rIhMaujpKHjqhjr]rJ(jt)rK}rL(jYX$Creating a Target Configuration FilerMjZjDjbjPjdjxjf}rN(jh]ji]jj]jk]jn]ujpKHjqhjr]rOj{X$Creating a Target Configuration FilerPrQ}rR(jYjMjZjKubaubjC)rS}rT(jYUjZjDjbjPjdj`jf}rU(jGX-jk]jj]jh]ji]jn]ujpKJjqhjr]rV(j/)rW}rX(jYX3In CCS, navigate to View -> Target Configurations. jZjSjbjPjdj2jf}rY(jh]ji]jj]jk]jn]ujpNjqhjr]rZj)r[}r\(jYX2In CCS, navigate to View -> Target Configurations.r]jZjWjbjPjdjjf}r^(jh]ji]jj]jk]jn]ujpKJjr]r_j{X2In CCS, navigate to View -> Target Configurations.r`ra}rb(jYj]jZj[ubaubaubj/)rc}rd(jYXXIn the Target Configurations window, right-click and select "New Target Configuration." jZjSjbjPjdj2jf}re(jh]ji]jj]jk]jn]ujpNjqhjr]rfj)rg}rh(jYXWIn the Target Configurations window, right-click and select "New Target Configuration."rijZjcjbjPjdjjf}rj(jh]ji]jj]jk]jn]ujpKLjr]rkj{XWIn the Target Configurations window, right-click and select "New Target Configuration."rlrm}rn(jYjijZjgubaubaubj/)ro}rp(jYX/For Connection, select your external emulator. jZjSjbjPjdj2jf}rq(jh]ji]jj]jk]jn]ujpNjqhjr]rrj)rs}rt(jYX.For Connection, select your external emulator.rujZjojbjPjdjjf}rv(jh]ji]jj]jk]jn]ujpKNjr]rwj{X.For Connection, select your external emulator.rxry}rz(jYjujZjsubaubaubj/)r{}r|(jYXgFor Board or Device, select LCDKC6748 or LCDKOMAPL138 as shown in the following image, and click Save. jZjSjbjPjdj2jf}r}(jh]ji]jj]jk]jn]ujpNjqhjr]r~j)r}r(jYXfFor Board or Device, select LCDKC6748 or LCDKOMAPL138 as shown in the following image, and click Save.rjZj{jbjPjdjjf}r(jh]ji]jj]jk]jn]ujpKPjr]rj{XfFor Board or Device, select LCDKC6748 or LCDKOMAPL138 as shown in the following image, and click Save.rr}r(jYjjZjubaubaubeubjB)r}r(jYX+.. Image:: ../images/lcdk_targetConfig.png jZjDjbjPjdjEjf}r(UuriX$rtos/../images/lcdk_targetConfig.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpKSjqhjr]ubjZ)r}r(jYUjZjDjbjPjdj]jf}r(jh]ji]jj]jk]jn]ujpKTjqhjr]rj`)r}r(jYUjcKjZjjbjPjdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubjC)r}r(jYUjZjDjbjPjdj`jf}r(jGX-jk]jj]jh]ji]jn]ujpKVjqhjr]rj/)r}r(jYXxNavigate to the Advanced tab and ensure the GEL file is loaded for the ARM9_0 core (OMAP-L138) or C674X_0 core (C6748). jZjjbjPjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXwNavigate to the Advanced tab and ensure the GEL file is loaded for the ARM9_0 core (OMAP-L138) or C674X_0 core (C6748).rjZjjbjPjdjjf}r(jh]ji]jj]jk]jn]ujpKVjr]rj{XwNavigate to the Advanced tab and ensure the GEL file is loaded for the ARM9_0 core (OMAP-L138) or C674X_0 core (C6748).rr}r(jYjjZjubaubaubaubj)r}r(jYX**OMAP-L138 LCDK GEL File:**rjZjDjbjPjdjjf}r(jh]ji]jj]jk]jn]ujpKXjqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XOMAP-L138 LCDK GEL File:rr}r(jYUjZjubajdjubaubjB)r}r(jYX@.. Image:: ../images/lcdk_omapl138_gel.png :scale: 100% jZjDjbjPjdjEjf}r(UscaleKdUuriX$rtos/../images/lcdk_omapl138_gel.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpNjqhjr]ubj)r}r(jYX**C6748 LCDK GEL File:**rjZjDjbjPjdjjf}r(jh]ji]jj]jk]jn]ujpK]jqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XC6748 LCDK GEL File:rr}r(jYUjZjubajdjubaubjB)r}r(jYX>.. Image:: ../images/lcdk_c6748_gel.png :scale: 100% jZjDjbjPjdjEjf}rž(UscaleKdUuriX!rtos/../images/lcdk_c6748_gel.pngrÞjk]jj]jh]ji]jH}rĞU*jÞsjn]ujpNjqhjr]ubeubj[)rŞ}rƞ(jYUjZj0jbjPjdjejf}rǞ(jh]ji]jj]jk]rȞU0connecting-to-target-and-loading-running-programrɞajn]rʞhaujpKdjqhjr]r˞(jt)r̞}r͞(jYX0Connecting to Target and Loading/Running ProgramrΞjZjŞjbjPjdjxjf}rϞ(jh]ji]jj]jk]jn]ujpKdjqhjr]rОj{X0Connecting to Target and Loading/Running ProgramrўrҞ}rӞ(jYjΞjZj̞ubaubj)rԞ}r՞(jYX**Connecting to Target**r֞jZjŞjbjPjdjjf}rמ(jh]ji]jj]jk]jn]ujpKfjqhjr]r؞j)rٞ}rڞ(jYj֞jf}r۞(jh]ji]jj]jk]jn]ujZjԞjr]rܞj{XConnecting to Targetrݞrޞ}rߞ(jYUjZjٞubajdjubaubjC)r}r(jYUjZjŞjbjPjdj`jf}r(jGX-jk]jj]jh]ji]jn]ujpKhjqhjr]r(j/)r}r(jYX6In CCS, navigate to the Target Configurations window. jZjjbjPjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYX5In CCS, navigate to the Target Configurations window.rjZjjbjPjdjjf}r(jh]ji]jj]jk]jn]ujpKhjr]rj{X5In CCS, navigate to the Target Configurations window.rr}r(jYjjZjubaubaubj/)r}r(jYXbRight-click on the newly created target configuration and select "Launch Selected Configuration." jZjjbjPjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXaRight-click on the newly created target configuration and select "Launch Selected Configuration."rjZjjbjPjdjjf}r(jh]ji]jj]jk]jn]ujpKjjr]rj{XaRight-click on the newly created target configuration and select "Launch Selected Configuration."rr}r(jYjjZjubaubaubj/)r}r(jYXeRight-click on the ARM9_0 core for OMAP-L138 or C674X_0 core for C6748, and click "Connect Target." jZjjbjPjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXcRight-click on the ARM9_0 core for OMAP-L138 or C674X_0 core for C6748, and click "Connect Target."rjZjjbjPjdjjf}r(jh]ji]jj]jk]jn]ujpKljr]rj{XcRight-click on the ARM9_0 core for OMAP-L138 or C674X_0 core for C6748, and click "Connect Target."rr}r(jYjjZjubaubaubeubj)r}r (jYX@The following GEL outputs should appear in the CCS Console view.r jZjŞjbjPjdjjf}r (jh]ji]jj]jk]jn]ujpKojqhjr]r j{X@The following GEL outputs should appear in the CCS Console view.r r}r(jYj jZjubaubj)r}r(jYX**OMAP-L138 LCDK:** ::jZjŞjbjPjdjjf}r(jh]ji]jj]jk]jn]ujpKqjqhjr]rj)r}r(jYX**OMAP-L138 LCDK:**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XOMAP-L138 LCDK:rr}r(jYUjZjubajdjubaubj)r}r(jYXARM9_0: Output: Target Connected. ARM9_0: Output: --------------------------------------------- ARM9_0: Output: Memory Map Cleared. ARM9_0: Output: --------------------------------------------- ARM9_0: Output: Memory Map Setup Complete. ARM9_0: Output: --------------------------------------------- ARM9_0: Output: PSC Enable Complete. ARM9_0: Output: --------------------------------------------- ARM9_0: Output: PLL0 init done for Core:300MHz, EMIFA:25MHz ARM9_0: Output: DDR initialization is in progress.... ARM9_0: Output: PLL1 init done for DDR:150MHz ARM9_0: Output: Using DDR2 settings ARM9_0: Output: DDR2 init for 150 MHz is done ARM9_0: Output: --------------------------------------------- ARM9_0: Output: DSP Wake Complete. ARM9_0: Output: ---------------------------------------------jZjŞjbjPjdjjf}r(jjjk]jj]jh]ji]jn]ujpMr'jqhjr]rj{XARM9_0: Output: Target Connected. ARM9_0: Output: --------------------------------------------- ARM9_0: Output: Memory Map Cleared. ARM9_0: Output: --------------------------------------------- ARM9_0: Output: Memory Map Setup Complete. ARM9_0: Output: --------------------------------------------- ARM9_0: Output: PSC Enable Complete. ARM9_0: Output: --------------------------------------------- ARM9_0: Output: PLL0 init done for Core:300MHz, EMIFA:25MHz ARM9_0: Output: DDR initialization is in progress.... ARM9_0: Output: PLL1 init done for DDR:150MHz ARM9_0: Output: Using DDR2 settings ARM9_0: Output: DDR2 init for 150 MHz is done ARM9_0: Output: --------------------------------------------- ARM9_0: Output: DSP Wake Complete. ARM9_0: Output: ---------------------------------------------rr }r!(jYUjZjubaubj)r"}r#(jYX**C6748 LCDK:** ::jZjŞjbjPjdjjf}r$(jh]ji]jj]jk]jn]ujpKjqhjr]r%j)r&}r'(jYX**C6748 LCDK:**jf}r((jh]ji]jj]jk]jn]ujZj"jr]r)j{X C6748 LCDK:r*r+}r,(jYUjZj&ubajdjubaubj)r-}r.(jYX-C674X_0: Output: Target Connected. C674X_0: Output: --------------------------------------------- C674X_0: Output: Memory Map Cleared. C674X_0: Output: --------------------------------------------- C674X_0: Output: Memory Map Setup Complete. C674X_0: Output: --------------------------------------------- C674X_0: Output: PSC Enable Complete. C674X_0: Output: --------------------------------------------- C674X_0: Output: PLL0 init done for Core:300MHz, EMIFA:25MHz C674X_0: Output: DDR initialization is in progress.... C674X_0: Output: PLL1 init done for DDR:150MHz C674X_0: Output: Using DDR2 settings C674X_0: Output: DDR2 init for 150 MHz is done C674X_0: Output: ---------------------------------------------jZjŞjbjPjdjjf}r/(jjjk]jj]jh]ji]jn]ujpM'jqhjr]r0j{X-C674X_0: Output: Target Connected. C674X_0: Output: --------------------------------------------- C674X_0: Output: Memory Map Cleared. C674X_0: Output: --------------------------------------------- C674X_0: Output: Memory Map Setup Complete. C674X_0: Output: --------------------------------------------- C674X_0: Output: PSC Enable Complete. C674X_0: Output: --------------------------------------------- C674X_0: Output: PLL0 init done for Core:300MHz, EMIFA:25MHz C674X_0: Output: DDR initialization is in progress.... C674X_0: Output: PLL1 init done for DDR:150MHz C674X_0: Output: Using DDR2 settings C674X_0: Output: DDR2 init for 150 MHz is done C674X_0: Output: ---------------------------------------------r1r2}r3(jYUjZj-ubaubjZ)r4}r5(jYUjZjŞjbjPjdj]jf}r6(jh]ji]jj]jk]jn]ujpKjqhjr]r7j`)r8}r9(jYUjcKjZj4jbjPjdjpjf}r:(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r;}r<(jYX**Loading Program**r=jZjŞjbjPjdjjf}r>(jh]ji]jj]jk]jn]ujpKjqhjr]r?j)r@}rA(jYj=jf}rB(jh]ji]jj]jk]jn]ujZj;jr]rCj{XLoading ProgramrDrE}rF(jYUjZj@ubajdjubaubjC)rG}rH(jYUjZjŞjbjPjdj`jf}rI(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]rJ(j/)rK}rL(jYX,Select the desired core (ARM9_0 or C674X_0).rMjZjGjbjPjdj2jf}rN(jh]ji]jj]jk]jn]ujpNjqhjr]rOj)rP}rQ(jYjMjZjKjbjPjdjjf}rR(jh]ji]jj]jk]jn]ujpKjr]rSj{X,Select the desired core (ARM9_0 or C674X_0).rTrU}rV(jYjMjZjPubaubaubj/)rW}rX(jYX(Go to “Run -> Load -> Load Program.”rYjZjGjbjPjdj2jf}rZ(jh]ji]jj]jk]jn]ujpNjqhjr]r[j)r\}r](jYjYjZjWjbjPjdjjf}r^(jh]ji]jj]jk]jn]ujpKjr]r_j{X(Go to “Run -> Load -> Load Program.”r`ra}rb(jYjYjZj\ubaubaubj/)rc}rd(jYXsClick “Browse” to choose a prebuilt .out or click “Browse project..” to choose a .out from an open project.rejZjGjbjPjdj2jf}rf(jh]ji]jj]jk]jn]ujpNjqhjr]rgj)rh}ri(jYjejZjcjbjPjdjjf}rj(jh]ji]jj]jk]jn]ujpKjr]rkj{XsClick “Browse” to choose a prebuilt .out or click “Browse project..” to choose a .out from an open project.rlrm}rn(jYjejZjhubaubaubj/)ro}rp(jYX&Select the desired .out and click OK. jZjGjbjPjdj2jf}rq(jh]ji]jj]jk]jn]ujpNjqhjr]rrj)rs}rt(jYX%Select the desired .out and click OK.rujZjojbjPjdjjf}rv(jh]ji]jj]jk]jn]ujpKjr]rwj{X%Select the desired .out and click OK.rxry}rz(jYjujZjsubaubaubeubj)r{}r|(jYX**Running Program**r}jZjŞjbjPjdjjf}r~(jh]ji]jj]jk]jn]ujpKjqhjr]rj)r}r(jYj}jf}r(jh]ji]jj]jk]jn]ujZj{jr]rj{XRunning Programrr}r(jYUjZjubajdjubaubjC)r}r(jYUjZjŞjbjPjdj`jf}r(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]rj/)r}r(jYXGo to “Run -> Resume” jZjjbXbinternal padding after source/common/EVM_Hardware_Setup/OMAPL138-C6748_LCDK_Hardware_Setup.rst.incrjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXGo to “Run -> Resume”rjZjjbjPjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XGo to “Run -> Resume”rr}r(jYjjZjubaubaubaubj)r}r(jYXOMAP-L137 EVM Hardware SetupjZjŞjbjcjdjjf}r(jjjk]jj]jh]ji]jn]ujpKjqhjr]rj{XOMAP-L137 EVM Hardware Setuprr}r(jYUjZjubaubj)r}r(jYX4====================================================jZjŞjbjcjdjjf}r(jjjk]jj]jh]ji]jn]ujpKjqhjr]rj{X4====================================================rr}r(jYUjZjubaubeubeubeubj[)r}r(jYUjZjR\jbjXDsource/common/EVM_Hardware_Setup/OMAPL137_EVM_Hardware_Setup.rst.incrr}rbjdjejf}r(jh]ji]jj]jk]rU(omap-l137-c6747-evm-hardware-setup-guiderajn]rh!aujpKjqhjr]r(jt)r}r(jYX(OMAP-L137/C6747 EVM Hardware Setup GuiderjZjjbjjdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X(OMAP-L137/C6747 EVM Hardware Setup Guiderr}r(jYjjZjubaubj[)r}r(jYUjZjjbjjdjejf}r(jh]ji]jj]jk]rUsetting-up-the-hardwarerajn]rhaujpKjqhjr]r(jt)r}r(jYXSetting up the HardwarerjZjjbjjdjxjf}rŸ(jh]ji]jj]jk]jn]ujpKjqhjr]rßj{XSetting up the Hardwarerğrş}rƟ(jYjjZjubaubj)rǟ}rȟ(jYXSFollow the steps below to setup the hardware and enable communication with the EVM.rɟjZjjbjjdjjf}rʟ(jh]ji]jj]jk]jn]ujpKjqhjr]r˟j{XSFollow the steps below to setup the hardware and enable communication with the EVM.r̟r͟}rΟ(jYjɟjZjǟubaubj)rϟ}rП(jYXThe EVM is sensitive to static discharges. Use a grounding strap or other device to prevent damaging the board. Be sure to connect communication cables before applying power to any equipment.rџjZjjbjjdjjf}rҟ(jh]ji]jj]jk]jn]ujpNjqhjr]rӟj)rԟ}r՟(jYjџjZjϟjbjjdjjf}r֟(jh]ji]jj]jk]jn]ujpK jr]rןj{XThe EVM is sensitive to static discharges. Use a grounding strap or other device to prevent damaging the board. Be sure to connect communication cables before applying power to any equipment.r؟rٟ}rڟ(jYjџjZjԟubaubaubjC)r۟}rܟ(jYUjZjjbjjdj`jf}rݟ(jGX-jk]jj]jh]ji]jn]ujpK jqhjr]rޟj/)rߟ}r(jYXiVerify that the EVM board's SW2 (Boot) switch is correctly set. The setting to boot from SPI0 Flash are: jZj۟jbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXhVerify that the EVM board's SW2 (Boot) switch is correctly set. The setting to boot from SPI0 Flash are:rjZjߟjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK jr]rj{XhVerify that the EVM board's SW2 (Boot) switch is correctly set. The setting to boot from SPI0 Flash are:rr}r(jYjjZjubaubaubaubjd$)r}r(jYUjZjjbjjdjg$jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rjj$)r}r(jYUjf}r(jk]jj]jh]ji]jn]UcolsKujZjjr]r(jo$)r}r(jYUjf}r(jk]jj]jh]ji]jn]UcolwidthKujZjjr]jdjs$ubjo$)r}r(jYUjf}r(jk]jj]jh]ji]jn]UcolwidthKujZjjr]jdjs$ubjo$)r}r(jYUjf}r(jk]jj]jh]ji]jn]UcolwidthKujZjjr]jdjs$ubjo$)r}r(jYUjf}r(jk]jj]jh]ji]jn]UcolwidthKujZjjr]jdjs$ubjo$)r}r(jYUjf}r(jk]jj]jh]ji]jn]UcolwidthKujZjjr]jdjs$ubjo$)r}r(jYUjf}r(jk]jj]jh]ji]jn]UcolwidthKujZjjr]jdjs$ubjz$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj$)r }r (jYUjf}r (jh]ji]jj]jk]jn]ujZjjr]r (j$)r }r(jYUjf}r(jh]ji]jj]jk]jn]ujZj jr]rj)r}r(jYX **Pin #**rjZj jbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XPin #rr}r(jYUjZjubajdjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj jr]r j)r!}r"(jYX7jZjjbjjdjjf}r#(jh]ji]jj]jk]jn]ujpKjr]r$j{X7r%}r&(jYX7jZj!ubaubajdj$ubj$)r'}r((jYUjf}r)(jh]ji]jj]jk]jn]ujZj jr]r*j)r+}r,(jYX2jZj'jbjjdjjf}r-(jh]ji]jj]jk]jn]ujpKjr]r.j{X2r/}r0(jYX2jZj+ubaubajdj$ubj$)r1}r2(jYUjf}r3(jh]ji]jj]jk]jn]ujZj jr]r4j)r5}r6(jYX1jZj1jbjjdjjf}r7(jh]ji]jj]jk]jn]ujpKjr]r8j{X1r9}r:(jYX1jZj5ubaubajdj$ubj$)r;}r<(jYUjf}r=(jh]ji]jj]jk]jn]ujZj jr]r>j)r?}r@(jYX0jZj;jbjjdjjf}rA(jh]ji]jj]jk]jn]ujpKjr]rBj{X0rC}rD(jYX0jZj?ubaubajdj$ubj$)rE}rF(jYUjf}rG(jh]ji]jj]jk]jn]ujZj jr]rHj)rI}rJ(jYX3jZjEjbjjdjjf}rK(jh]ji]jj]jk]jn]ujpKjr]rLj{X3rM}rN(jYX3jZjIubaubajdj$ubejdj$ubajdj$ubj$)rO}rP(jYUjf}rQ(jh]ji]jj]jk]jn]ujZjjr]rRj$)rS}rT(jYUjf}rU(jh]ji]jj]jk]jn]ujZjOjr]rV(j$)rW}rX(jYUjf}rY(jh]ji]jj]jk]jn]ujZjSjr]rZj)r[}r\(jYX **Position**r]jZjWjbjjdjjf}r^(jh]ji]jj]jk]jn]ujpKjr]r_j)r`}ra(jYj]jf}rb(jh]ji]jj]jk]jn]ujZj[jr]rcj{XPositionrdre}rf(jYUjZj`ubajdjubaubajdj$ubj$)rg}rh(jYUjf}ri(jh]ji]jj]jk]jn]ujZjSjr]rjj)rk}rl(jYX0jZjgjbjjdjjf}rm(jh]ji]jj]jk]jn]ujpKjr]rnj{X0ro}rp(jYX0jZjkubaubajdj$ubj$)rq}rr(jYUjf}rs(jh]ji]jj]jk]jn]ujZjSjr]rtj)ru}rv(jYX1jZjqjbjjdjjf}rw(jh]ji]jj]jk]jn]ujpKjr]rxj{X1ry}rz(jYX1jZjuubaubajdj$ubj$)r{}r|(jYUjf}r}(jh]ji]jj]jk]jn]ujZjSjr]r~j)r}r(jYX0jZj{jbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X0r}r(jYX0jZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjSjr]rj)r}r(jYX1jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X1r}r(jYX1jZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjSjr]rj)r}r(jYXXjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XXr}r(jYXXjZjubaubajdj$ubejdj$ubajdjy%ubejdjz%ubaubj)r}r(jYXAll boot switch modes can be found in the EVM Technical Reference Manual at the link provided under the Additional Resources section.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XAll boot switch modes can be found in the EVM Technical Reference Manual at the link provided under the Additional Resources section.rr}r(jYjjZjubaubaubjC)r}r(jYUjZjjbjjdj`jf}r(jGX-jk]jj]jh]ji]jn]ujpKjqhjr]r(j/)r}r(jYXIf you want to use networking, connect the Ethernet cable to one of the Ethernet ports on the EVM board and to an Ethernet network port. jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXIf you want to use networking, connect the Ethernet cable to one of the Ethernet ports on the EVM board and to an Ethernet network port.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XIf you want to use networking, connect the Ethernet cable to one of the Ethernet ports on the EVM board and to an Ethernet network port.rr}r(jYjjZjubaubaubj/)r}r(jYXConnect the USB cable provided in the kit to the on-board emulation USB port on the board (EMBED USB). Connect the other end to a computer with CCS installed. jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXConnect the USB cable provided in the kit to the on-board emulation USB port on the board (EMBED USB). Connect the other end to a computer with CCS installed.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XConnect the USB cable provided in the kit to the on-board emulation USB port on the board (EMBED USB). Connect the other end to a computer with CCS installed.rr}r(jYjjZjubaubaubj/)r}r (jYXIf you plan to use UART port for a console window, connect the RS-232 null modem cable to the EVM UART port and to the COM port of your host workstation. jZjjbjjdj2jf}rà(jh]ji]jj]jk]jn]ujpNjqhjr]rĠj)rŠ}rƠ(jYXIf you plan to use UART port for a console window, connect the RS-232 null modem cable to the EVM UART port and to the COM port of your host workstation.rǠjZjjbjjdjjf}rȠ(jh]ji]jj]jk]jn]ujpKjr]rɠj{XIf you plan to use UART port for a console window, connect the RS-232 null modem cable to the EVM UART port and to the COM port of your host workstation.rʠrˠ}r̠(jYjǠjZjŠubaubaubj/)r͠}rΠ(jYXConnect the power cable to the EVM power jack on the board. To be ESD safe, plug in the other end of the power cable only after you have connected the power cord to the board. jZjjbjjdj2jf}rϠ(jh]ji]jj]jk]jn]ujpNjqhjr]rРj)rѠ}rҠ(jYXConnect the power cable to the EVM power jack on the board. To be ESD safe, plug in the other end of the power cable only after you have connected the power cord to the board.rӠjZj͠jbjjdjjf}rԠ(jh]ji]jj]jk]jn]ujpK#jr]rՠj{XConnect the power cable to the EVM power jack on the board. To be ESD safe, plug in the other end of the power cable only after you have connected the power cord to the board.r֠rנ}rؠ(jYjӠjZjѠubaubaubeubeubj[)r٠}rڠ(jYUjZjjbjjdjejf}r۠(jh]ji]jj]jk]rܠUconnecting-to-a-console-windowrݠajn]rޠhlaujpK(jqhjr]rߠ(jt)r}r(jYXConnecting to a Console WindowrjZj٠jbjjdjxjf}r(jh]ji]jj]jk]jn]ujpK(jqhjr]rj{XConnecting to a Console Windowrr}r(jYjjZjubaubj)r}r(jYXqYou can open a console window that allows you to watch boot and serial console messages by following these steps:rjZj٠jbjjdjjf}r(jh]ji]jj]jk]jn]ujpK*jqhjr]rj{XqYou can open a console window that allows you to watch boot and serial console messages by following these steps:rr}r(jYjjZjubaubj%)r}r(jYUjZj٠jbjjdj(jf}r(j*U.jk]jj]jh]j+Uji]jn]j,j-ujpK-jqhjr]r(j/)r}r(jYXiConnect a serial cable between the serial port on the EVM and the serial port (for example COM1) on a PC.jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXiConnect a serial cable between the serial port on the EVM and the serial port (for example COM1) on a PC.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK-jr]rj{XiConnect a serial cable between the serial port on the EVM and the serial port (for example COM1) on a PC.rr}r(jYjjZjubaubaubj/)r}r(jYX@Run a terminal session (such as Minicom on Linux or TeraTerm on Windows) on the workstation and configure it to connect to that serial port with the following characteristics: - Bits per Second: 115200 - Data Bits: 8 - Parity: None - Stop Bits: 1 - Flow Control: None - Transmit delay: 0 msec/char, 100 msec/line jZjjbNjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]r(j)r}r(jYXRun a terminal session (such as Minicom on Linux or TeraTerm on Windows) on the workstation and configure it to connect to that serial port with the following characteristics:rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK/jr]rj{XRun a terminal session (such as Minicom on Linux or TeraTerm on Windows) on the workstation and configure it to connect to that serial port with the following characteristics:r r }r (jYjjZjubaubjC)r }r (jYUjf}r(jGX-jk]jj]jh]ji]jn]ujZjjr]r(j/)r}r(jYXBits per Second: 115200rjf}r(jh]ji]jj]jk]jn]ujZj jr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK3jr]rj{XBits per Second: 115200rr}r(jYjjZjubaubajdj2ubj/)r}r(jYX Data Bits: 8rjf}r(jh]ji]jj]jk]jn]ujZj jr]r j)r!}r"(jYjjZjjbjjdjjf}r#(jh]ji]jj]jk]jn]ujpK4jr]r$j{X Data Bits: 8r%r&}r'(jYjjZj!ubaubajdj2ubj/)r(}r)(jYX Parity: Noner*jf}r+(jh]ji]jj]jk]jn]ujZj jr]r,j)r-}r.(jYj*jZj(jbjjdjjf}r/(jh]ji]jj]jk]jn]ujpK5jr]r0j{X Parity: Noner1r2}r3(jYj*jZj-ubaubajdj2ubj/)r4}r5(jYX Stop Bits: 1r6jf}r7(jh]ji]jj]jk]jn]ujZj jr]r8j)r9}r:(jYj6jZj4jbjjdjjf}r;(jh]ji]jj]jk]jn]ujpK6jr]r<j{X Stop Bits: 1r=r>}r?(jYj6jZj9ubaubajdj2ubj/)r@}rA(jYXFlow Control: NonerBjf}rC(jh]ji]jj]jk]jn]ujZj jr]rDj)rE}rF(jYjBjZj@jbjjdjjf}rG(jh]ji]jj]jk]jn]ujpK7jr]rHj{XFlow Control: NonerIrJ}rK(jYjBjZjEubaubajdj2ubj/)rL}rM(jYX+Transmit delay: 0 msec/char, 100 msec/line jf}rN(jh]ji]jj]jk]jn]ujZj jr]rOj)rP}rQ(jYX*Transmit delay: 0 msec/char, 100 msec/linerRjZjLjbjjdjjf}rS(jh]ji]jj]jk]jn]ujpK8jr]rTj{X*Transmit delay: 0 msec/char, 100 msec/linerUrV}rW(jYjRjZjPubaubajdj2ubejdj`ubeubeubj)rX}rY(jYX **For Linux**rZjZj٠jbjjdjjf}r[(jh]ji]jj]jk]jn]ujpK:jqhjr]r\j)r]}r^(jYjZjf}r_(jh]ji]jj]jk]jn]ujZjXjr]r`j{X For Linuxrarb}rc(jYUjZj]ubajdjubaubj%)rd}re(jYUjZj٠jbjjdj(jf}rf(j*U.jdKjk]jj]jh]j+Uji]jn]j,j-ujpKTarget Configuration File.rjZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKIjr]rj{X3Open CCS and select New->Target Configuration File.rr}r(jYjjZjubaubaubj/)r}r(jYX#Specify a file name or use default.rjZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKJjr]rj{X#Specify a file name or use default.r¡rá}rġ(jYjjZjubaubaubj/)rš}rơ(jYXSelect "Spectrum Digital XDS510USB Emulator" as Connection. **If using CCS 9.0 or later, you will need an external emulator as noted above.** jZjjbjjdj2jf}rǡ(jh]ji]jj]jk]jn]ujpNjqhjr]rȡj)rɡ}rʡ(jYXSelect "Spectrum Digital XDS510USB Emulator" as Connection. **If using CCS 9.0 or later, you will need an external emulator as noted above.**jZjšjbjjdjjf}rˡ(jh]ji]jj]jk]jn]ujpKKjr]r̡(j{X<Select "Spectrum Digital XDS510USB Emulator" as Connection. r͡rΡ}rϡ(jYX<Select "Spectrum Digital XDS510USB Emulator" as Connection. jZjɡubj)rС}rѡ(jYXQ**If using CCS 9.0 or later, you will need an external emulator as noted above.**jf}rҡ(jh]ji]jj]jk]jn]ujZjɡjr]rӡj{XMIf using CCS 9.0 or later, you will need an external emulator as noted above.rԡrա}r֡(jYUjZjСubajdjubeubaubeubjB)rס}rء(jYX0.. Image:: ../images/OMAPL137_targetConfig.png jZjjbjjdjEjf}r١(UuriX(rtos/../images/OMAPL137_targetConfig.pngrڡjk]jj]jh]ji]jH}rۡU*jڡsjn]ujpKOjqhjr]ubjC)rܡ}rݡ(jYUjZjjbjjdj`jf}rޡ(jGX-jk]jj]jh]ji]jn]ujpKPjqhjr]rߡj/)r}r(jYX0Check "OMAPL137" or "C6747" as Device and save. jZjܡjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYX/Check "OMAPL137" or "C6747" as Device and save.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKPjr]rj{X/Check "OMAPL137" or "C6747" as Device and save.rr}r(jYjjZjubaubaubaubcdocutils.nodes tip r)r}r(jYXyIf you don't see "OMAPL137", ensure that you have installed CCS and selected Single Core DSP devices in the installation.rjZjjbjjdUtiprjf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKRjr]rj{XyIf you don't see "OMAPL137", ensure that you have installed CCS and selected Single Core DSP devices in the installation.rr}r(jYjjZjubaubaubjC)r}r(jYUjZjjbjjdj`jf}r(jGX-jk]jj]jh]ji]jn]ujpKTjqhjr]r(j/)r}r(jYXlOpen Target Configuration view in CCS by selecting "Window -> Show View -> Target Configurations" from menu.jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXlOpen Target Configuration view in CCS by selecting "Window -> Show View -> Target Configurations" from menu.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKTjr]rj{XlOpen Target Configuration view in CCS by selecting "Window -> Show View -> Target Configurations" from menu.rr}r (jYjjZjubaubaubj/)r }r (jYXLSelect newly created configuration, right-click on it and set it as default.jZjjbjjdj2jf}r (jh]ji]jj]jk]jn]ujpNjqhjr]r j)r}r(jYXLSelect newly created configuration, right-click on it and set it as default.rjZj jbjjdjjf}r(jh]ji]jj]jk]jn]ujpKVjr]rj{XLSelect newly created configuration, right-click on it and set it as default.rr}r(jYjjZjubaubaubj/)r}r(jYX#Launch Target configuration file jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYX Launch Target configuration filerjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKXjr]rj{X Launch Target configuration filerr }r!(jYjjZjubaubaubeubeubj[)r"}r#(jYUjZjtjbjjdjejf}r$(jh]ji]jj]jk]r%U#connect-target-and-load-run-programr&ajn]r'jKaujpK]jqhjr]r((jt)r)}r*(jYX#Connect Target and Load/Run Programr+jZj"jbjjdjxjf}r,(jh]ji]jj]jk]jn]ujpK]jqhjr]r-j{X#Connect Target and Load/Run Programr.r/}r0(jYj+jZj)ubaubjC)r1}r2(jYUjZj"jbjjdj`jf}r3(jGX-jk]jj]jh]ji]jn]ujpK_jqhjr]r4j/)r5}r6(jYXConnecting Target - Select "View -> Debug" from menu to start a debug session. - CCS will switch to Debug perspective with devices DSP and ARM. - Select device to connect and then go to "Run -> Connect Target" from menu. jZj1jbNjdj2jf}r7(jh]ji]jj]jk]jn]ujpNjqhjr]r8(j)r9}r:(jYXConnecting Targetr;jZj5jbjjdjjf}r<(jh]ji]jj]jk]jn]ujpK_jr]r=j{XConnecting Targetr>r?}r@(jYj;jZj9ubaubjC)rA}rB(jYUjf}rC(jGX-jk]jj]jh]ji]jn]ujZj5jr]rD(j/)rE}rF(jYX:Select "View -> Debug" from menu to start a debug session.rGjf}rH(jh]ji]jj]jk]jn]ujZjAjr]rIj)rJ}rK(jYjGjZjEjbjjdjjf}rL(jh]ji]jj]jk]jn]ujpKajr]rMj{X:Select "View -> Debug" from menu to start a debug session.rNrO}rP(jYjGjZjJubaubajdj2ubj/)rQ}rR(jYX>CCS will switch to Debug perspective with devices DSP and ARM.rSjf}rT(jh]ji]jj]jk]jn]ujZjAjr]rUj)rV}rW(jYjSjZjQjbjjdjjf}rX(jh]ji]jj]jk]jn]ujpKbjr]rYj{X>CCS will switch to Debug perspective with devices DSP and ARM.rZr[}r\(jYjSjZjVubaubajdj2ubj/)r]}r^(jYXKSelect device to connect and then go to "Run -> Connect Target" from menu. jf}r_(jh]ji]jj]jk]jn]ujZjAjr]r`j)ra}rb(jYXJSelect device to connect and then go to "Run -> Connect Target" from menu.rcjZj]jbjjdjjf}rd(jh]ji]jj]jk]jn]ujpKcjr]rej{XJSelect device to connect and then go to "Run -> Connect Target" from menu.rfrg}rh(jYjcjZjaubaubajdj2ubejdj`ubeubaubj)ri}rj(jYXOMAPL137 is a DSP boot master device. Hence to connect to the ARM, you need to connect the DSP first (even if you do not load anything to DSP), then connect ARM (Reason: DSP’s GEL file enables and wakes up the ARM).rkjZj"jbjjdjjf}rl(jh]ji]jj]jk]jn]ujpNjqhjr]rmj)rn}ro(jYjkjZjijbjjdjjf}rp(jh]ji]jj]jk]jn]ujpKfjr]rqj{XOMAPL137 is a DSP boot master device. Hence to connect to the ARM, you need to connect the DSP first (even if you do not load anything to DSP), then connect ARM (Reason: DSP’s GEL file enables and wakes up the ARM).rrrs}rt(jYjkjZjnubaubaubjC)ru}rv(jYUjZj"jbjjdj`jf}rw(jGX-jk]jj]jh]ji]jn]ujpKhjqhjr]rx(j/)ry}rz(jYX Loading Program - Choose desired device (DSP or ARM). - Go to "Run -> Load -> Load Program" from menu. - Click “Browse” to choose a prebuilt \*.out or click “Browse project..” to choose \*.out of the open projects. - Choose desired \*.out and click OK. jZjujbNjdj2jf}r{(jh]ji]jj]jk]jn]ujpNjqhjr]r|(j)r}}r~(jYXLoading ProgramrjZjyjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKhjr]rj{XLoading Programrr}r(jYjjZj}ubaubjC)r}r(jYUjf}r(jGX-jk]jj]jh]ji]jn]ujZjyjr]r(j/)r}r(jYX#Choose desired device (DSP or ARM).rjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjjr]rj{X#Choose desired device (DSP or ARM).rr}r(jYjjZjubaubajdj2ubj/)r}r(jYX.Go to "Run -> Load -> Load Program" from menu.rjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKkjr]rj{X.Go to "Run -> Load -> Load Program" from menu.rr}r(jYjjZjubaubajdj2ubj/)r}r(jYXuClick “Browse” to choose a prebuilt \*.out or click “Browse project..” to choose \*.out of the open projects.rjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKljr]rj{XsClick “Browse” to choose a prebuilt *.out or click “Browse project..” to choose *.out of the open projects.rr}r(jYXuClick “Browse” to choose a prebuilt \*.out or click “Browse project..” to choose \*.out of the open projects.jZjubaubajdj2ubj/)r}r(jYX%Choose desired \*.out and click OK. jf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX#Choose desired \*.out and click OK.jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKmjr]rj{X"Choose desired *.out and click OK.rr}r(jYX#Choose desired \*.out and click OK.jZjubaubajdj2ubejdj`ubeubj/)r}r(jYX*Running Program - Go to "Run -> Resume" jZjujbNjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]r(j)r}r(jYXRunning ProgramrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKpjr]rj{XRunning Programrr¢}râ(jYjjZjubaubjC)rĢ}rŢ(jYUjf}rƢ(jGX-jk]jj]jh]ji]jn]ujZjjr]rǢj/)rȢ}rɢ(jYXGo to "Run -> Resume" jf}rʢ(jh]ji]jj]jk]jn]ujZjĢjr]rˢj)r̢}r͢(jYXGo to "Run -> Resume"r΢jZjȢjbjjdjjf}rϢ(jh]ji]jj]jk]jn]ujpKrjr]rТj{XGo to "Run -> Resume"rѢrҢ}rӢ(jYj΢jZj̢ubaubajdj2ubajdj`ubeubeubeubj[)rԢ}rբ(jYUjZjtjbjjdjejf}r֢(jh]ji]jj]jk]rעUadditional-referencesrآajn]r٢hyaujpKujqhjr]rڢ(jt)rۢ}rܢ(jYXAdditional ReferencesrݢjZjԢjbjjdjxjf}rޢ(jh]ji]jj]jk]jn]ujpKujqhjr]rߢj{XAdditional Referencesrr}r(jYjݢjZjۢubaubj)r}r(jYXYEVM Design and Support Files: http://support.spectrumdigital.com/boards/evmomapl137/revg/rjZjԢjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKvjqhjr]r(j{XEVM Design and Support Files: rr}r(jYXEVM Design and Support Files: jZjubj)r}r(jYX;http://support.spectrumdigital.com/boards/evmomapl137/revg/rjf}r(Urefurijjk]jj]jh]ji]jn]ujZjjr]rj{X;http://support.spectrumdigital.com/boards/evmomapl137/revg/rr}r(jYUjZjubajdjubeubj)r}r(jYXAM335x ICE EVM Hardware SetupjZjԢjbjcjdjjf}r(jjjk]jj]jh]ji]jn]ujpKjqhjr]rj{XAM335x ICE EVM Hardware Setuprr}r(jYUjZjubaubj)r}r(jYX4====================================================jZjԢjbjcjdjjf}r(jjjk]jj]jh]ji]jn]ujpKjqhjr]rj{X4====================================================rr}r(jYUjZjubaubeubeubeubj[)r}r(jYUjZjR\jbjXBsource/common/EVM_Hardware_Setup/ICE_AM335x_Hardware_Setup.rst.incrr}rbjdjejf}r(jh]ji]jj]jk]rUam335x-ice-evm-hardware-setuprajn]r hFaujpKjqhjr]r (jt)r }r (jYXAM335x ICE EVM Hardware Setupr jZjjbjjdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XAM335x ICE EVM Hardware Setuprr}r(jYj jZj ubaubj[)r}r(jYUjKjZjjbjjdjejf}r(jh]rX descriptionraji]jj]jk]rUid79rajn]ujpKjqhjr]r(jt)r}r(jYX DescriptionrjZjjbjjdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X Descriptionr r!}r"(jYjjZjubaubj)r#}r$(jYXThe low-cost ICE EVM can be used for evaluation and development of industrial communication type applications. It has been equipped with a TI AM3359 processor and a defined set of features to allow the user to experience specifically industrial communication solutions using serial or Ethernet based interfaces. It is not intended as a generic development platform as some of the features and interfaces supplied by the AM335x are not accessible from the ICE board. Using standard interfaces, the ICE board may interface to other processors or systems and act as a communication gateway in this case. In addition it can directly operate as a standard remote I/O system or simple sensor connected to an industrial communication network. The embedded emulation logic allows emulation and debug using standard development tools such as TI’s Code Composer Studio by just using the supplied USB cable.r%jZjjbjjdjjf}r&(jh]ji]jj]jk]jn]ujpKjqhjr]r'j{XThe low-cost ICE EVM can be used for evaluation and development of industrial communication type applications. It has been equipped with a TI AM3359 processor and a defined set of features to allow the user to experience specifically industrial communication solutions using serial or Ethernet based interfaces. It is not intended as a generic development platform as some of the features and interfaces supplied by the AM335x are not accessible from the ICE board. Using standard interfaces, the ICE board may interface to other processors or systems and act as a communication gateway in this case. In addition it can directly operate as a standard remote I/O system or simple sensor connected to an industrial communication network. The embedded emulation logic allows emulation and debug using standard development tools such as TI’s Code Composer Studio by just using the supplied USB cable.r(r)}r*(jYj%jZj#ubaubeubj[)r+}r,(jYUjKjZjjbjjdjejf}r-(jh]r.Xevm layout and key componentsr/aji]jj]jk]r0Uid80r1ajn]ujpKjqhjr]r2(jt)r3}r4(jYXEVM Layout and Key Componentsr5jZj+jbjjdjxjf}r6(jh]ji]jj]jk]jn]ujpKjqhjr]r7j{XEVM Layout and Key Componentsr8r9}r:(jYj5jZj3ubaubjB)r;}r<(jYXA.. Image:: ../../../images/ICE_V2_marked.png :scale: 50% jZj+jbjjdjEjf}r=(UscaleK2UuriX&rtos/../../../images/ICE_V2_marked.pngr>jk]jj]jh]ji]jH}r?U*j>sjn]ujpNjqhjr]ubeubj[)r@}rA(jYUjKjZjjbjjdjejf}rB(jh]rCXquick start guiderDaji]jj]jk]rEUid81rFajn]ujpKjqhjr]rG(jt)rH}rI(jYXQuick Start GuiderJjZj@jbjjdjxjf}rK(jh]ji]jj]jk]jn]ujpKjqhjr]rLj{XQuick Start GuiderMrN}rO(jYjJjZjHubaubj)rP}rQ(jYX9This section details how to quickly setup the AM3359 ICE.rRjZj@jbjjdjjf}rS(jh]ji]jj]jk]jn]ujpKjqhjr]rTj{X9This section details how to quickly setup the AM3359 ICE.rUrV}rW(jYjRjZjPubaubj)rX}rY(jYXR1. Unbox the board and identify the various components and connectors shown above.rZjZj@jbjjdjjf}r[(jh]ji]jj]jk]jn]ujpK!jqhjr]r\j{XR1. Unbox the board and identify the various components and connectors shown above.r]r^}r_(jYjZjZjXubaubj)r`}ra(jYX^2. Connect the power cable to the power jack on the board and plug it into an AC power source.rbjZj@jbjjdjjf}rc(jh]ji]jj]jk]jn]ujpK$jqhjr]rdj{X^2. Connect the power cable to the power jack on the board and plug it into an AC power source.rerf}rg(jYjbjZj`ubaubjB)rh}ri(jYX>.. Image:: ../../../images/ICE335924V.png :scale: 50% jZj@jbjjdjEjf}rj(UscaleK2UuriX#rtos/../../../images/ICE335924V.pngrkjk]jj]jh]ji]jH}rlU*jksjn]ujpNjqhjr]ubj)rm}rn(jYXlOnce powered on, the POWER ON LED (D16) and Industrial Output LEDs (D6-D10, D12, D14, and D15) will turn on.rojZj@jbjjdjjf}rp(jh]ji]jj]jk]jn]ujpK*jqhjr]rqj{XlOnce powered on, the POWER ON LED (D16) and Industrial Output LEDs (D6-D10, D12, D14, and D15) will turn on.rrrs}rt(jYjojZjmubaubj)ru}rv(jYX-When powering the AM335x ICE, always use the supplied power supply (CUI/V-Infinity Part Number EMSA240075) or equivalent model having output voltage of +24VDC and output current max 0.75 Amps and that complies with applicable regional safety standards such as (by example) UL, CSA, VDE, CCC, PSE, etc.rwjZj@jbjjdjjf}rx(jh]ji]jj]jk]jn]ujpNjqhjr]ryj)rz}r{(jYjwjZjujbjjdjjf}r|(jh]ji]jj]jk]jn]ujpK.jr]r}j{X-When powering the AM335x ICE, always use the supplied power supply (CUI/V-Infinity Part Number EMSA240075) or equivalent model having output voltage of +24VDC and output current max 0.75 Amps and that complies with applicable regional safety standards such as (by example) UL, CSA, VDE, CCC, PSE, etc.r~r}r(jYjwjZjzubaubaubj)r}r(jYX3. Connect the microUSB cable to the USB JTAG/Console port on the ICE board and connect to the USB on the host. Connect an Ethernet cable to ETH0 if network connectivity is required.rjZj@jbjjdjjf}r(jh]ji]jj]jk]jn]ujpK0jqhjr]rj{X3. Connect the microUSB cable to the USB JTAG/Console port on the ICE board and connect to the USB on the host. Connect an Ethernet cable to ETH0 if network connectivity is required.rr}r(jYjjZjubaubjB)r}r(jYX>.. Image:: ../../../images/ICE3359USB.png :scale: 50% jZj@jbjjdjEjf}r(UscaleK2UuriX#rtos/../../../images/ICE3359USB.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpNjqhjr]ubj)r}r(jYXNThe serial port will not show up on the host PC until the board is powered on.rjZj@jbjjdjjf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK6jr]rj{XNThe serial port will not show up on the host PC until the board is powered on.rr}r(jYjjZjubaubaubj)r}r(jYX4. Users can now connect to UART and the on-board XDS100v2 emulator from the host machine. For UART port connections, set the serial terminal software baud rate to 115200 to view the log messages. Connecting to the target using the on-board emulator is discussed in the section below.rjZj@jbjjdjjf}r(jh]ji]jj]jk]jn]ujpK8jqhjr]rj{X4. Users can now connect to UART and the on-board XDS100v2 emulator from the host machine. For UART port connections, set the serial terminal software baud rate to 115200 to view the log messages. Connecting to the target using the on-board emulator is discussed in the section below.rr}r(jYjjZjubaubjB)r}r(jYXB.. Image:: ../../../images/Serial_connect.jpg :scale: 50% jZj@jbjjdjEjf}r(UscaleK2UuriX'rtos/../../../images/Serial_connect.jpgrjk]jj]jh]ji]jH}rU*jsjn]ujpNjqhjr]ubjB)r}r(jYX<.. Image:: ../../../images/Baudrate.jpg :scale: 50% jZj@jbjjdjEjf}r(UscaleK2UuriX!rtos/../../../images/Baudrate.jpgrjk]jj]jh]ji]jH}rU*jsjn]ujpNjqhjr]ubeubj[)r}r(jYUjKjZjjbjjdjejf}r(jh]rXboot configurationraji]jj]jk]rUboot-configurationrajn]ujpKEjqhjr]r(jt)r}r(jYXBoot ConfigurationrjZjjbjjdjxjf}r(jh]ji]jj]jk]jn]ujpKEjqhjr]rj{XBoot Configurationrr}r(jYjjZjubaubj)r}r(jYXmThe various boot configurations are discussed in the `Hardware User Guide. `__jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKGjqhjr]r(j{X5The various boot configurations are discussed in the rr}r£(jYX5The various boot configurations are discussed in the jZjubj)rã}rģ(jYX8`Hardware User Guide. `__jf}rţ(UnameXHardware User Guide.jXhttp://www.ti.com/lit/spruip3jk]jj]jh]ji]jn]ujZjjr]rƣj{XHardware User Guide.rǣrȣ}rɣ(jYUjZjãubajdjubeubjZ)rʣ}rˣ(jYUjZjjbjjdj]jf}ṛ(jh]ji]jj]jk]jn]ujpKJjqhjr]rͣj`)rΣ}rϣ(jYUjcKjZjʣjbjjdjpjf}rУ(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubj[)rѣ}rң(jYUjZjjbjjdjejf}rӣ(jh]ji]jj]jk]rԣU1connecting-the-am3359-ice-to-code-composer-studiorգajn]r֣haujpKMjqhjr]rף(jt)rأ}r٣(jYX1Connecting the AM3359 ICE to Code Composer StudiorڣjZjѣjbjjdjxjf}rۣ(jh]ji]jj]jk]jn]ujpKMjqhjr]rܣj{X1Connecting the AM3359 ICE to Code Composer Studiorݣrޣ}rߣ(jYjڣjZjأubaubj)r}r(jYX1. Download Code Composer Studio and the AM335x Sitara Device Support package as described in the `Processor SDK RTOS Getting Started Guide. `__jZjѣjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKOjqhjr]r(j{Xb1. Download Code Composer Studio and the AM335x Sitara Device Support package as described in the rr}r(jYXb1. Download Code Composer Studio and the AM335x Sitara Device Support package as described in the jZjubj)r}r(jYX`Processor SDK RTOS Getting Started Guide. `__jf}r(UnameX)Processor SDK RTOS Getting Started Guide.jXjhttp://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_overview.html#code-composer-studiojk]jj]jh]ji]jn]ujZjjr]rj{X)Processor SDK RTOS Getting Started Guide.rr}r(jYUjZjubajdjubeubj)r}r(jYXF2. Connect the AM3359 ICE as described above in the Quick Start Guide.rjZjѣjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKSjqhjr]rj{XF2. Connect the AM3359 ICE as described above in the Quick Start Guide.rr}r(jYjjZjubaubj)r}r(jYX3. Launch CCS and create a new target configuration file (File->New->Target Configuration File) as shown below. Select the Texas Instruments XDS100v2 USB Debug Probe and the ICE\_AM3359 as shown below.jZjѣjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKVjqhjr]rj{X3. Launch CCS and create a new target configuration file (File->New->Target Configuration File) as shown below. Select the Texas Instruments XDS100v2 USB Debug Probe and the ICE_AM3359 as shown below.rr}r(jYX3. Launch CCS and create a new target configuration file (File->New->Target Configuration File) as shown below. Select the Texas Instruments XDS100v2 USB Debug Probe and the ICE\_AM3359 as shown below.jZjubaubj)r}r(jYXIf the ICE\_AM3359 target is not listed, make sure the latest Sitara Device Support package is installed by going to Help->Check for Updates.rjZjѣjbjjdjjf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK[jr]rj{XIf the ICE_AM3359 target is not listed, make sure the latest Sitara Device Support package is installed by going to Help->Check for Updates.rr}r(jYXIf the ICE\_AM3359 target is not listed, make sure the latest Sitara Device Support package is installed by going to Help->Check for Updates.jZjubaubaubjB)r }r (jYXG.. Image:: ../../../images/ICE3359TargetConfig.png :scale: 50% jZjѣjbjjdjEjf}r (UscaleK2UuriX,rtos/../../../images/ICE3359TargetConfig.pngr jk]jj]jh]ji]jH}r U*j sjn]ujpNjqhjr]ubj)r}r(jYX4. Click Save to save the target configuration. Then press Test Connection to test the connection. If successful, a message should be seen similar to the one below.rjZjѣjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK`jqhjr]rj{X4. Click Save to save the target configuration. Then press Test Connection to test the connection. If successful, a message should be seen similar to the one below.rr}r(jYjjZjubaubjB)r}r(jYX?.. Image:: ../../../images/ICE3359Test.png :scale: 50% jZjѣjbjjdjEjf}r(UscaleK2UuriX$rtos/../../../images/ICE3359Test.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpNjqhjr]ubj)r}r(jYXD5. Launch the target configuration and connect to the ARM Cortex-A8.rjZjѣjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKgjqhjr]rj{XD5. Launch the target configuration and connect to the ARM Cortex-A8.r r!}r"(jYjjZjubaubj)r#}r$(jYX:The complete GEL log from the Cortex A8 is provided below.r%jZjѣjbjjdjjf}r&(jh]ji]jj]jk]jn]ujpKjjqhjr]r'j{X:The complete GEL log from the Cortex A8 is provided below.r(r)}r*(jYj%jZj#ubaubj)r+}r,(jYXCortxA8: Output: **** AM3359_ICE Initialization is in progress .......... CortxA8: Output: **** AM335x ALL PLL Config for OPP == OPP100 is in progress ......... CortxA8: Output: Input Clock Read from SYSBOOT[15:14]: 24MHz CortxA8: Output: **** Going to Bypass... CortxA8: Output: **** Bypassed, changing values... CortxA8: Output: **** Locking ARM PLL CortxA8: Output: **** Core Bypassed CortxA8: Output: **** Now locking Core... CortxA8: Output: **** Core locked CortxA8: Output: **** DDR DPLL Bypassed CortxA8: Output: **** DDR DPLL Locked CortxA8: Output: **** PER DPLL Bypassed CortxA8: Output: **** PER DPLL Locked CortxA8: Output: **** DISP PLL Config is in progress .......... CortxA8: Output: **** DISP PLL Config is DONE .......... CortxA8: Output: **** AM335x ALL ADPLL Config for OPP == OPP100 is Done ......... CortxA8: Output: **** AM335x DDR3 EMIF and PHY configuration is in progress... CortxA8: Output: EMIF PRCM is in progress ....... CortxA8: Output: EMIF PRCM Done CortxA8: Output: DDR PHY Configuration in progress CortxA8: Output: Waiting for VTP Ready ....... CortxA8: Output: VTP is Ready! CortxA8: Output: DDR PHY CMD0 Register configuration is in progress ....... CortxA8: Output: DDR PHY CMD1 Register configuration is in progress ....... CortxA8: Output: DDR PHY CMD2 Register configuration is in progress ....... CortxA8: Output: DDR PHY DATA0 Register configuration is in progress ....... CortxA8: Output: DDR PHY DATA1 Register configuration is in progress ....... CortxA8: Output: Setting IO control registers....... CortxA8: Output: EMIF Timing register configuration is in progress ....... CortxA8: Output: EMIF Timing register configuration is done ....... CortxA8: Output: PHY is READY!! CortxA8: Output: DDR PHY Configuration done CortxA8: GEL Output: Turning on EDMA... CortxA8: GEL Output: EDMA is turned on... CortxA8: Output: **** AM3359_ICE Initialization is Done ******************jZjѣjbjjdjjf}r-(jjjk]jj]jh]ji]jn]ujpM(jqhjr]r.j{XCortxA8: Output: **** AM3359_ICE Initialization is in progress .......... CortxA8: Output: **** AM335x ALL PLL Config for OPP == OPP100 is in progress ......... CortxA8: Output: Input Clock Read from SYSBOOT[15:14]: 24MHz CortxA8: Output: **** Going to Bypass... CortxA8: Output: **** Bypassed, changing values... CortxA8: Output: **** Locking ARM PLL CortxA8: Output: **** Core Bypassed CortxA8: Output: **** Now locking Core... CortxA8: Output: **** Core locked CortxA8: Output: **** DDR DPLL Bypassed CortxA8: Output: **** DDR DPLL Locked CortxA8: Output: **** PER DPLL Bypassed CortxA8: Output: **** PER DPLL Locked CortxA8: Output: **** DISP PLL Config is in progress .......... CortxA8: Output: **** DISP PLL Config is DONE .......... CortxA8: Output: **** AM335x ALL ADPLL Config for OPP == OPP100 is Done ......... CortxA8: Output: **** AM335x DDR3 EMIF and PHY configuration is in progress... CortxA8: Output: EMIF PRCM is in progress ....... CortxA8: Output: EMIF PRCM Done CortxA8: Output: DDR PHY Configuration in progress CortxA8: Output: Waiting for VTP Ready ....... CortxA8: Output: VTP is Ready! CortxA8: Output: DDR PHY CMD0 Register configuration is in progress ....... CortxA8: Output: DDR PHY CMD1 Register configuration is in progress ....... CortxA8: Output: DDR PHY CMD2 Register configuration is in progress ....... CortxA8: Output: DDR PHY DATA0 Register configuration is in progress ....... CortxA8: Output: DDR PHY DATA1 Register configuration is in progress ....... CortxA8: Output: Setting IO control registers....... CortxA8: Output: EMIF Timing register configuration is in progress ....... CortxA8: Output: EMIF Timing register configuration is done ....... CortxA8: Output: PHY is READY!! CortxA8: Output: DDR PHY Configuration done CortxA8: GEL Output: Turning on EDMA... CortxA8: GEL Output: EDMA is turned on... CortxA8: Output: **** AM3359_ICE Initialization is Done ******************r/r0}r1(jYUjZj+ubaubjZ)r2}r3(jYUjZjѣjbjjdj]jf}r4(jh]ji]jj]jk]jn]ujpKjqhjr]r5j`)r6}r7(jYUjcKjZj2jbjjdjpjf}r8(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubj[)r9}r:(jYUjKjZjjbjjdjejf}r;(jh]r<Xrunning board diagnosticsr=aji]jj]jk]r>Urunning-board-diagnosticsr?ajn]ujpKjqhjr]r@(jt)rA}rB(jYXRunning Board DiagnosticsrCjZj9jbjjdjxjf}rD(jh]ji]jj]jk]jn]ujpKjqhjr]rEj{XRunning Board DiagnosticsrFrG}rH(jYjCjZjAubaubj)rI}rJ(jYXThe Processor SDK RTOS Diagnostic package is designed to be a set of baremetal tests to run on a given board to provide data path continuity testing on peripherals.rKjZj9jbjjdjjf}rL(jh]ji]jj]jk]jn]ujpKjqhjr]rMj{XThe Processor SDK RTOS Diagnostic package is designed to be a set of baremetal tests to run on a given board to provide data path continuity testing on peripherals.rNrO}rP(jYjKjZjIubaubj)rQ}rR(jYXTo run diagnostics on the AM335x ICE, follow the procedure given in the `RTOS Software Developer Guide `__jZj9jbjjdjjf}rS(jh]ji]jj]jk]jn]ujpKjqhjr]rT(j{XHTo run diagnostics on the AM335x ICE, follow the procedure given in the rUrV}rW(jYXHTo run diagnostics on the AM335x ICE, follow the procedure given in the jZjQubj)rX}rY(jYX`RTOS Software Developer Guide `__jf}rZ(UnameXRTOS Software Developer GuidejXrhttp://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_board.html#running-the-diagnostic-examplesjk]jj]jh]ji]jn]ujZjQjr]r[j{XRTOS Software Developer Guider\r]}r^(jYUjZjXubajdjubeubj)r_}r`(jYXAMIC110 ICE EVM Hardware SetupjZj9jbjcjdjjf}ra(jjjk]jj]jh]ji]jn]ujpKjqhjr]rbj{XAMIC110 ICE EVM Hardware Setuprcrd}re(jYUjZj_ubaubj)rf}rg(jYX4====================================================jZj9jbjcjdjjf}rh(jjjk]jj]jh]ji]jn]ujpKjqhjr]rij{X4====================================================rjrk}rl(jYUjZjfubaubeubeubj[)rm}rn(jYUjZjR\jbjXGsource/common/EVM_Hardware_Setup/ICE_AMIC110_EVM_Hardware_Setup.rst.incrorp}rqbjdjejf}rr(jh]ji]jj]jk]rsUamic110-ice-evm-hardware-setuprtajn]ruhoaujpKjqhjr]rv(jt)rw}rx(jYXAMIC110 ICE EVM Hardware SetupryjZjmjbjpjdjxjf}rz(jh]ji]jj]jk]jn]ujpKjqhjr]r{j{XAMIC110 ICE EVM Hardware Setupr|r}}r~(jYjyjZjwubaubj[)r}r(jYUjKjZjmjbjpjdjejf}r(jh]rX descriptionraji]jj]jk]rUid82rajn]ujpKjqhjr]r(jt)r}r(jYX DescriptionrjZjjbjpjdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X Descriptionrr}r(jYjjZjubaubj)r}r(jYXThe AMIC110 ICE is a high-performance, low-power platform that enables users to evaluate and develop industrial communications applications for the Sitara AMIC110 ARM Cortex-A8 processor SoC from Texas Instruments.™rjZjjbjpjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XThe AMIC110 ICE is a high-performance, low-power platform that enables users to evaluate and develop industrial communications applications for the Sitara AMIC110 ARM Cortex-A8 processor SoC from Texas Instruments.™rr}r(jYjjZjubaubeubj[)r}r(jYUjKjZjmjbjpjdjejf}r(jh]rXevm layout and key componentsraji]jj]jk]rUid83rajn]ujpK jqhjr]r(jt)r}r(jYXEVM Layout and Key ComponentsrjZjjbjpjdjxjf}r(jh]ji]jj]jk]jn]ujpK jqhjr]rj{XEVM Layout and Key Componentsrr}r(jYjjZjubaubjB)r}r(jYXG.. Image:: ../../../images/ICEAMIC110TopLayout.PNG :scale: 50% jZjjbjpjdjEjf}r(UscaleK2UuriX,rtos/../../../images/ICEAMIC110TopLayout.PNGrjk]jj]jh]ji]jH}rU*jsjn]ujpNjqhjr]ubjB)r}r(jYXJ.. Image:: ../../../images/ICEAMIC110BottomLayout.PNG :scale: 50% jZjjbjpjdjEjf}r(UscaleK2UuriX/rtos/../../../images/ICEAMIC110BottomLayout.PNGrjk]jj]jh]ji]jH}rU*jsjn]ujpNjqhjr]ubeubj[)r}r(jYUjKjZjmjbjpjdjejf}r(jh]rjDaji]jj]jk]rUid84rajn]ujpKjqhjr]r(jt)r}r(jYXQuick Start GuiderjZjjbjpjdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XQuick Start Guiderr}r(jYjjZjubaubj)r}r(jYXeThis quick start guide can be found in the `Hardware User's Guide `_.jZjjbjpjdjjf}r¤(jh]ji]jj]jk]jn]ujpKjqhjr]rä(j{X+This quick start guide can be found in the rĤrŤ}rƤ(jYX+This quick start guide can be found in the jZjubj)rǤ}rȤ(jYX9`Hardware User's Guide `_jf}rɤ(UnameXHardware User's GuidejXhttp://www.ti.com/lit/spruie6arʤjk]jj]jh]ji]jn]ujZjjr]rˤj{XHardware User's Guider̤rͤ}rΤ(jYUjZjǤubajdjubj)rϤ}rФ(jYX! jKjZjjdjjf}rѤ(Urefurijʤjk]rҤUhardware-user-s-guiderӤajj]jh]ji]jn]rԤjNaujr]ubj{X.rդ}r֤(jYX.jZjubeubj)rפ}rؤ(jYXR1. Unbox the board and identify the various components and connectors shown above.r٤jZjjbjpjdjjf}rڤ(jh]ji]jj]jk]jn]ujpKjqhjr]rۤj{XR1. Unbox the board and identify the various components and connectors shown above.rܤrݤ}rޤ(jYj٤jZjפubaubj)rߤ}r(jYX2. To download a bootable image into the onboard SPI Flash, connect a 20-pin JTAG emulator to J1 on the ICE board. For example, the XDS110 or the XDS200 emulators may be used for this purpose and can be purchased from the TI store: `XDS200 `__ and `XDS110 `__.jZjjbjpjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r(j{X2. To download a bootable image into the onboard SPI Flash, connect a 20-pin JTAG emulator to J1 on the ICE board. For example, the XDS110 or the XDS200 emulators may be used for this purpose and can be purchased from the TI store: rr}r(jYX2. To download a bootable image into the onboard SPI Flash, connect a 20-pin JTAG emulator to J1 on the ICE board. For example, the XDS110 or the XDS200 emulators may be used for this purpose and can be purchased from the TI store: jZjߤubj)r}r(jYXP`XDS200 `__jf}r(UnameXXDS200jXChttps://store.ti.com/TMDSEMU200-U-XDS200-USB-Debug-Probe-P4281.aspxjk]jj]jh]ji]jn]ujZjߤjr]rj{XXDS200rr}r(jYUjZjubajdjubj{X and rr}r(jYX and jZjߤubj)r}r(jYXR`XDS110 `__jf}r(UnameXXDS110jXEhttps://store.ti.com/TMDSEMU110-U-XDS110-JTAG-Debug-Probe-P51766.aspxjk]jj]jh]ji]jn]ujZjߤjr]rj{XXDS110rr}r(jYUjZjubajdjubj{X.r}r(jYX.jZjߤubeubjB)r}r(jYXB.. Image:: ../../../images/ICEAMIC110JTAG.PNG :scale: 50% jZjjbjpjdjEjf}r(UscaleK2UuriX'rtos/../../../images/ICEAMIC110JTAG.PNGrjk]jj]jh]ji]jH}rU*jsjn]ujpNjqhjr]ubj)r}r(jYX3. Connect the pin header connector of the included TTL-232R-3V3 serial cable to J3 on the ICE board. Ensure that pin 1 of the serial cable (black wire, marked with a triangle) is connected to pin 1 of J3, which is indicated by a dot on the silk screen. Connect the USB connector of the serial cable to a PC host port. The datasheet for this cable can found at http://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_TTL-232R_CABLES.pdfjZjjbjpjdjjf}r(jh]ji]jj]jk]jn]ujpK&jqhjr]r(j{Xi3. Connect the pin header connector of the included TTL-232R-3V3 serial cable to J3 on the ICE board. Ensure that pin 1 of the serial cable (black wire, marked with a triangle) is connected to pin 1 of J3, which is indicated by a dot on the silk screen. Connect the USB connector of the serial cable to a PC host port. The datasheet for this cable can found at rr}r(jYXi3. Connect the pin header connector of the included TTL-232R-3V3 serial cable to J3 on the ICE board. Ensure that pin 1 of the serial cable (black wire, marked with a triangle) is connected to pin 1 of J3, which is indicated by a dot on the silk screen. Connect the USB connector of the serial cable to a PC host port. The datasheet for this cable can found at jZjubj)r}r(jYXRhttp://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_TTL-232R_CABLES.pdfrjf}r(Urefurijjk]jj]jh]ji]jn]ujZjjr]r j{XRhttp://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_TTL-232R_CABLES.pdfr r }r (jYUjZjubajdjubeubjB)r }r(jYXA.. Image:: ../../../images/ICEAMIC110TTL.PNG :scale: 50% jZjjbjpjdjEjf}r(UscaleK2UuriX&rtos/../../../images/ICEAMIC110TTL.PNGrjk]jj]jh]ji]jH}rU*jsjn]ujpNjqhjr]ubj)r}r(jYX.4. Connect a CAT5 Ethernet cable from a PC running TwinCAT software to ECAT IN/PHY1 (J6) of the ICE board. If you have multiple ICE boards in a chain, please connect another CAT5 Ethernet cable from ECAT OUT/PHY2 (J7) to PHY1 of the next ICE board. PHY2 of the last ICE board in the chain is left open.rjZjjbjpjdjjf}r(jh]ji]jj]jk]jn]ujpK,jqhjr]rj{X.4. Connect a CAT5 Ethernet cable from a PC running TwinCAT software to ECAT IN/PHY1 (J6) of the ICE board. If you have multiple ICE boards in a chain, please connect another CAT5 Ethernet cable from ECAT OUT/PHY2 (J7) to PHY1 of the next ICE board. PHY2 of the last ICE board in the chain is left open.rr}r(jYjjZjubaubjB)r}r(jYXF.. Image:: ../../../images/ICEAMIC110ETHERNET.PNG :scale: 50% jZjjbjpjdjEjf}r(UscaleK2UuriX+rtos/../../../images/ICEAMIC110ETHERNET.PNGrjk]jj]jh]ji]jH}rU*jsjn]ujpNjqhjr]ubj)r}r (jYX5. Connect the recommended power supply (CUI Inc. SMI18-5-V-P5, procurable at: http://www.digikey.com/product-detail/en/cui-inc/SMI18-5-V-P5/102-3571-ND/5415042) or equivalent (Output voltage/current: 5 Volts DC +/- 10% @ 1.2 Amps; Output connector: 2.1-mm ID, 5.5-mm OD barrel plug, center positive) power supply to J8 on the ICE board. Apply power to the power supply to power up the ICE board. Do not hot plug the 5-V supply into the ICE board.jZjjbjpjdjjf}r!(jh]ji]jj]jk]jn]ujpK2jqhjr]r"(j{XO5. Connect the recommended power supply (CUI Inc. SMI18-5-V-P5, procurable at: r#r$}r%(jYXO5. Connect the recommended power supply (CUI Inc. SMI18-5-V-P5, procurable at: jZjubj)r&}r'(jYXQhttp://www.digikey.com/product-detail/en/cui-inc/SMI18-5-V-P5/102-3571-ND/5415042r(jf}r)(Urefurij(jk]jj]jh]ji]jn]ujZjjr]r*j{XQhttp://www.digikey.com/product-detail/en/cui-inc/SMI18-5-V-P5/102-3571-ND/5415042r+r,}r-(jYUjZj&ubajdjubj{X) or equivalent (Output voltage/current: 5 Volts DC +/- 10% @ 1.2 Amps; Output connector: 2.1-mm ID, 5.5-mm OD barrel plug, center positive) power supply to J8 on the ICE board. Apply power to the power supply to power up the ICE board. Do not hot plug the 5-V supply into the ICE board.r.r/}r0(jYX) or equivalent (Output voltage/current: 5 Volts DC +/- 10% @ 1.2 Amps; Output connector: 2.1-mm ID, 5.5-mm OD barrel plug, center positive) power supply to J8 on the ICE board. Apply power to the power supply to power up the ICE board. Do not hot plug the 5-V supply into the ICE board.jZjubeubjB)r1}r2(jYX@.. Image:: ../../../images/ICEAMIC1105V.PNG :scale: 50% jZjjbjpjdjEjf}r3(UscaleK2UuriX%rtos/../../../images/ICEAMIC1105V.PNGr4jk]jj]jh]ji]jH}r5U*j4sjn]ujpNjqhjr]ubj)r6}r7(jYXOOnce the ICE board is powered on, the ON LED (D15) and LED4 (D19) will turn on.r8jZjjbjpjdjjf}r9(jh]ji]jj]jk]jn]ujpK8jqhjr]r:j{XOOnce the ICE board is powered on, the ON LED (D15) and LED4 (D19) will turn on.r;r<}r=(jYj8jZj6ubaubj)r>}r?(jYXz6. The AMIC110 ICE can now be connected to from the host machine via UART. The serial port should be setup as shown below.r@jZjjbjpjdjjf}rA(jh]ji]jj]jk]jn]ujpK;jqhjr]rBj{Xz6. The AMIC110 ICE can now be connected to from the host machine via UART. The serial port should be setup as shown below.rCrD}rE(jYj@jZj>ubaubjB)rF}rG(jYX<.. Image:: ../../../images/Baudrate.jpg :scale: 50% jZjjbjpjdjEjf}rH(UscaleK2UuriX!rtos/../../../images/Baudrate.jpgrIjk]jj]jh]ji]jH}rJU*jIsjn]ujpNjqhjr]ubeubj[)rK}rL(jYUjKjZjmjbjpjdjejf}rM(jh]rNjaji]jj]jk]rOUid85rPajn]ujpKBjqhjr]rQ(jt)rR}rS(jYXBoot ConfigurationrTjZjKjbjpjdjxjf}rU(jh]ji]jj]jk]jn]ujpKBjqhjr]rVj{XBoot ConfigurationrWrX}rY(jYjTjZjRubaubj)rZ}r[(jYXmThe various boot configurations are discussed in the `Hardware User Guide. `__jZjKjbjpjdjjf}r\(jh]ji]jj]jk]jn]ujpKDjqhjr]r](j{X5The various boot configurations are discussed in the r^r_}r`(jYX5The various boot configurations are discussed in the jZjZubj)ra}rb(jYX8`Hardware User Guide. `__jf}rc(UnameXHardware User Guide.jXhttp://www.ti.com/lit/spruip3jk]jj]jh]ji]jn]ujZjZjr]rdj{XHardware User Guide.rerf}rg(jYUjZjaubajdjubeubeubj[)rh}ri(jYUjZjmjbjpjdjejf}rj(jh]ji]jj]jk]rkU2connecting-the-amic110-ice-to-code-composer-studiorlajn]rmh%aujpKHjqhjr]rn(jt)ro}rp(jYX2Connecting the AMIC110 ICE to Code Composer StudiorqjZjhjbjpjdjxjf}rr(jh]ji]jj]jk]jn]ujpKHjqhjr]rsj{X2Connecting the AMIC110 ICE to Code Composer Studiortru}rv(jYjqjZjoubaubj)rw}rx(jYX 1. Download Code Composer Studio and the AMIC110 Sitara Device Support package as described in the `Processor SDK RTOS Getting Started Guide `_.jZjhjbjpjdjjf}ry(jh]ji]jj]jk]jn]ujpKJjqhjr]rz(j{Xc1. Download Code Composer Studio and the AMIC110 Sitara Device Support package as described in the r{r|}r}(jYXc1. Download Code Composer Studio and the AMIC110 Sitara Device Support package as described in the jZjwubj)r~}r(jYX`Processor SDK RTOS Getting Started Guide `_jf}r(UnameX(Processor SDK RTOS Getting Started GuidejXxhttp://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/Overview.html#processor-sdk-rtos-getting-started-guiderjk]jj]jh]ji]jn]ujZjwjr]rj{X(Processor SDK RTOS Getting Started Guiderr}r(jYUjZj~ubajdjubj)r}r(jYX{ jKjZjwjdjjf}r(Urefurijjk]rU(processor-sdk-rtos-getting-started-guiderajj]jh]ji]jn]rhaujr]ubj{X.r}r(jYX.jZjwubeubj)r}r(jYXA2. Connect the AMIC110 ICE as described in the Quick Start Guide.rjZjhjbjpjdjjf}r(jh]ji]jj]jk]jn]ujpKMjqhjr]rj{XA2. Connect the AMIC110 ICE as described in the Quick Start Guide.rr}r(jYjjZjubaubj)r}r(jYX3. Launch CCS and create a new target configuration file (File->New->Target Configuration File) as shown below. Select the appropriate emulator and the ICE\_AMIC110 as the target as shown below.jZjhjbjpjdjjf}r(jh]ji]jj]jk]jn]ujpKPjqhjr]rj{X3. Launch CCS and create a new target configuration file (File->New->Target Configuration File) as shown below. Select the appropriate emulator and the ICE_AMIC110 as the target as shown below.rr}r(jYX3. Launch CCS and create a new target configuration file (File->New->Target Configuration File) as shown below. Select the appropriate emulator and the ICE\_AMIC110 as the target as shown below.jZjubaubj)r}r(jYXuIf the ICE\_AMIC110 target is not listed, make sure the Sitara Device Support package v1.3.6 or greater is installed.rjZjhjbjpjdjjf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbjpjdjjf}r(jh]ji]jj]jk]jn]ujpKTjr]rj{XtIf the ICE_AMIC110 target is not listed, make sure the Sitara Device Support package v1.3.6 or greater is installed.rr}r(jYXuIf the ICE\_AMIC110 target is not listed, make sure the Sitara Device Support package v1.3.6 or greater is installed.jZjubaubaubjB)r}r(jYXJ.. Image:: ../../../images/ICEAMIC110TargetConfig.PNG :scale: 50% jZjhjbjpjdjEjf}r(UscaleK2UuriX/rtos/../../../images/ICEAMIC110TargetConfig.PNGrjk]jj]jh]ji]jH}rU*jsjn]ujpNjqhjr]ubj)r}r(jYX4. Click Save to save the target configuration. Then press Test Connection to test the connection. If successful, a message should be seen similar to the one below.rjZjhjbjpjdjjf}r(jh]ji]jj]jk]jn]ujpKYjqhjr]rj{X4. Click Save to save the target configuration. Then press Test Connection to test the connection. If successful, a message should be seen similar to the one below.rr}r(jYjjZjubaubjB)r}r(jYXB.. Image:: ../../../images/ICEAMIC110Test.PNG :scale: 50% jZjhjbjpjdjEjf}r(UscaleK2UuriX'rtos/../../../images/ICEAMIC110Test.PNGrjk]jj]jh]ji]jH}rU*jsjn]ujpNjqhjr]ubj)r}r(jYXD5. Launch the target configuration and connect to the ARM Cortex-A8.rjZjhjbjpjdjjf}r(jh]ji]jj]jk]jn]ujpK_jqhjr]rj{XD5. Launch the target configuration and connect to the ARM Cortex-A8.rr}r¥(jYjjZjubaubj)rå}rĥ(jYX:The complete GEL log from the Cortex A8 is provided below.rťjZjhjbjpjdjjf}rƥ(jh]ji]jj]jk]jn]ujpKbjqhjr]rǥj{X:The complete GEL log from the Cortex A8 is provided below.rȥrɥ}rʥ(jYjťjZjåubaubj)r˥}r̥(jYXCortxA8: Output: **** AMIC110_ICE & BoosterPack Initialization is in progress ...... CortxA8: Output: **** AMIC110 & Booster Pack ALL PLL Config for OPP == OPP100 is in progress ........ CortxA8: Output: Input Clock Read from SYSBOOT[15:14]: 25MHz CortxA8: Output: **** Going to Bypass... CortxA8: Output: **** Bypassed, changing values... CortxA8: Output: **** Locking ARM PLL CortxA8: Output: **** Core Bypassed CortxA8: Output: **** Now locking Core... CortxA8: Output: **** Core locked CortxA8: Output: **** DDR DPLL Bypassed CortxA8: Output: **** DDR DPLL Locked CortxA8: Output: **** PER DPLL Bypassed CortxA8: Output: **** PER DPLL Locked CortxA8: Output: **** DISP PLL Config is in progress .......... CortxA8: Output: **** DISP PLL Config is DONE .......... CortxA8: Output: **** AMIC110 BoosterPack ALL ADPLL Config for 25 MHz OPP == OPP100 25MHz is Done ......... CortxA8: Output: **** AMIC110 DDR3 EMIF and PHY configuration is in progress... CortxA8: Output: EMIF PRCM is in progress ....... CortxA8: Output: EMIF PRCM Done CortxA8: Output: DDR PHY Configuration in progress CortxA8: Output: Waiting for VTP Ready ....... CortxA8: Output: VTP is Ready! CortxA8: Output: DDR PHY CMD0 Register configuration is in progress ....... CortxA8: Output: DDR PHY CMD1 Register configuration is in progress ....... CortxA8: Output: DDR PHY CMD2 Register configuration is in progress ....... CortxA8: Output: DDR PHY DATA0 Register configuration is in progress ....... CortxA8: Output: DDR PHY DATA1 Register configuration is in progress ....... CortxA8: Output: Setting IO control registers....... CortxA8: Output: EMIF Timing register configuration is in progress ....... CortxA8: Output: EMIF Timing register configuration is done ....... CortxA8: Output: PHY is READY!! CortxA8: Output: DDR PHY Configuration done CortxA8: GEL Output: Turning on EDMA... CortxA8: GEL Output: EDMA is turned on... CortxA8: Output: **** AMIC110_ICE Initialization is Done ******************jZjhjbjpjdjjf}rͥ(jjjk]jj]jh]ji]jn]ujpM,)jqhjr]rΥj{XCortxA8: Output: **** AMIC110_ICE & BoosterPack Initialization is in progress ...... CortxA8: Output: **** AMIC110 & Booster Pack ALL PLL Config for OPP == OPP100 is in progress ........ CortxA8: Output: Input Clock Read from SYSBOOT[15:14]: 25MHz CortxA8: Output: **** Going to Bypass... CortxA8: Output: **** Bypassed, changing values... CortxA8: Output: **** Locking ARM PLL CortxA8: Output: **** Core Bypassed CortxA8: Output: **** Now locking Core... CortxA8: Output: **** Core locked CortxA8: Output: **** DDR DPLL Bypassed CortxA8: Output: **** DDR DPLL Locked CortxA8: Output: **** PER DPLL Bypassed CortxA8: Output: **** PER DPLL Locked CortxA8: Output: **** DISP PLL Config is in progress .......... CortxA8: Output: **** DISP PLL Config is DONE .......... CortxA8: Output: **** AMIC110 BoosterPack ALL ADPLL Config for 25 MHz OPP == OPP100 25MHz is Done ......... CortxA8: Output: **** AMIC110 DDR3 EMIF and PHY configuration is in progress... CortxA8: Output: EMIF PRCM is in progress ....... CortxA8: Output: EMIF PRCM Done CortxA8: Output: DDR PHY Configuration in progress CortxA8: Output: Waiting for VTP Ready ....... CortxA8: Output: VTP is Ready! CortxA8: Output: DDR PHY CMD0 Register configuration is in progress ....... CortxA8: Output: DDR PHY CMD1 Register configuration is in progress ....... CortxA8: Output: DDR PHY CMD2 Register configuration is in progress ....... CortxA8: Output: DDR PHY DATA0 Register configuration is in progress ....... CortxA8: Output: DDR PHY DATA1 Register configuration is in progress ....... CortxA8: Output: Setting IO control registers....... CortxA8: Output: EMIF Timing register configuration is in progress ....... CortxA8: Output: EMIF Timing register configuration is done ....... CortxA8: Output: PHY is READY!! CortxA8: Output: DDR PHY Configuration done CortxA8: GEL Output: Turning on EDMA... CortxA8: GEL Output: EDMA is turned on... CortxA8: Output: **** AMIC110_ICE Initialization is Done ******************rϥrХ}rѥ(jYUjZj˥ubaubeubj[)rҥ}rӥ(jYUjKjZjmjbjpjdjejf}rԥ(jh]rեj=aji]jj]jk]r֥Uid86rץajn]ujpKjqhjr]rإ(jt)r٥}rڥ(jYXRunning Board DiagnosticsrۥjZjҥjbjpjdjxjf}rܥ(jh]ji]jj]jk]jn]ujpKjqhjr]rݥj{XRunning Board Diagnosticsrޥrߥ}r(jYjۥjZj٥ubaubj)r}r(jYXThe Processor SDK RTOS Diagnostic package is designed to be a set of baremetal tests to run on a given board to provide data path continuity testing on peripherals.rjZjҥjbjpjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XThe Processor SDK RTOS Diagnostic package is designed to be a set of baremetal tests to run on a given board to provide data path continuity testing on peripherals.rr}r(jYjjZjubaubj)r}r(jYXTo run diagnostics on the AMIC110 ICE, follow the procedure given in the `RTOS Software Developer Guide `__jZjҥjbjpjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r(j{XITo run diagnostics on the AMIC110 ICE, follow the procedure given in the rr}r(jYXITo run diagnostics on the AMIC110 ICE, follow the procedure given in the jZjubj)r}r(jYX`RTOS Software Developer Guide `__jf}r(UnameXRTOS Software Developer GuidejX^http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_board.html#diagnosticsjk]jj]jh]ji]jn]ujZjjr]rj{XRTOS Software Developer Guiderr}r(jYUjZjubajdjubeubeubeubj[)r}r(jYUjZjR\jbjcjdjejf}r(jh]ji]jj]jk]rUak2g-audio-dc-addonrajn]rjaujpKjqhjr]r(jt)r}r(jYX66AK2G Audio DC AddOnrjZjjbjcjdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X66AK2G Audio DC AddOnrr}r(jYjjZjubaubj)r}r(jYXUPlease refer to `K2G Audio DC AddOn `__jZjjbjcjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r (j{XPlease refer to r r }r (jYXPlease refer to jZjubj)r }r(jYXE`K2G Audio DC AddOn `__jf}r(UnameXK2G Audio DC AddOnjX,index_examples_demos.html#k2g-audio-dc-addonjk]jj]jh]ji]jn]ujZjjr]rj{XK2G Audio DC AddOnrr}r(jYUjZj ubajdjubeubeubeubjbjXCsource/common/EVM_Hardware_Setup/TMDX654_EVM_Hardware_Setup.rst.incrr}rbjdjejf}r(jh]ji]jj]jk]rU am65x-evmrajn]rhdaujpKjqhjr]r(jt)r}r(jYX AM65x EVMrjZjP\jbjjdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r j{X AM65x EVMr!r"}r#(jYjjZjubaubjN\j[)r$}r%(jYUjZjP\jbjjdjejf}r&(jh]ji]jj]jk]r'U1minimum-hardware-setup-required-to-connect-to-evmr(ajn]r)hQaujpKjqhjr]r*(jt)r+}r,(jYX1Minimum Hardware Setup Required to Connect to EVMr-jZj$jbjjdjxjf}r.(jh]ji]jj]jk]jn]ujpKjqhjr]r/j{X1Minimum Hardware Setup Required to Connect to EVMr0r1}r2(jYj-jZj+ubaubj=)r3}r4(jYUjZj$jbNjdj@jf}r5(jh]ji]jj]jk]jn]ujpNjqhjr]r6j%)r7}r8(jYUjf}r9(j*U.jk]jj]jh]j+Uji]jn]j,j-ujZj3jr]r:(j/)r;}r<(jYXTConnect micro USB cable to J23 and connect USB to Host PC on which CCS is installed.r=jf}r>(jh]ji]jj]jk]jn]ujZj7jr]r?j)r@}rA(jYj=jZj;jbjjdjjf}rB(jh]ji]jj]jk]jn]ujpKjr]rCj{XTConnect micro USB cable to J23 and connect USB to Host PC on which CCS is installed.rDrE}rF(jYj=jZj@ubaubajdj2ubj/)rG}rH(jYX2Connect micro USB cable to J42 for UART serial IO.rIjf}rJ(jh]ji]jj]jk]jn]ujZj7jr]rKj)rL}rM(jYjIjZjGjbjjdjjf}rN(jh]ji]jj]jk]jn]ujpKjr]rOj{X2Connect micro USB cable to J42 for UART serial IO.rPrQ}rR(jYjIjZjLubaubajdj2ubj/)rS}rT(jYXYSet boot switches to "Sleep Boot" or "SD Boot" as described in the BOOT Switches section.rUjf}rV(jh]ji]jj]jk]jn]ujZj7jr]rWj)rX}rY(jYjUjZjSjbjjdjjf}rZ(jh]ji]jj]jk]jn]ujpKjr]r[j{XYSet boot switches to "Sleep Boot" or "SD Boot" as described in the BOOT Switches section.r\r]}r^(jYjUjZjXubaubajdj2ubj/)r_}r`(jYX1Connect power supply to DC jack and power on EVM.rajf}rb(jh]ji]jj]jk]jn]ujZj7jr]rcj)rd}re(jYjajZj_jbjjdjjf}rf(jh]ji]jj]jk]jn]ujpKjr]rgj{X1Connect power supply to DC jack and power on EVM.rhri}rj(jYjajZjdubaubajdj2ubj/)rk}rl(jYX-Set switches and jumpers as indicated below. jf}rm(jh]ji]jj]jk]jn]ujZj7jr]rnj)ro}rp(jYX,Set switches and jumpers as indicated below.rqjZjkjbjjdjjf}rr(jh]ji]jj]jk]jn]ujpKjr]rsj{X,Set switches and jumpers as indicated below.rtru}rv(jYjqjZjoubaubajdj2ubejdj(ubaubj )rw}rx(jYUjZj$jbNjdj3 jf}ry(jh]ji]jj]jk]jn]ujpNjqhjr]rz(j )r{}r|(jYXD**Boot Settings** * SW2 - All switches OFF * SW3 - All switches OFF jZjwjbjjdj jf}r}(jh]ji]jj]jk]jn]ujpKjr]r~(j )r}r(jYX**Boot Settings**rjZj{jbjjdj jf}r(jh]ji]jj]jk]jn]ujpKjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X Boot Settingsrr}r(jYUjZjubajdjubaubj )r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj{jr]rjC)r}r(jYUjf}r(jGX*jk]jj]jh]ji]jn]ujZjjr]r(j/)r}r(jYXSW2 - All switches OFFrjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XSW2 - All switches OFFrr}r(jYjjZjubaubajdj2ubj/)r}r(jYXSW3 - All switches OFF jf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXSW3 - All switches OFFrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XSW3 - All switches OFFrr}r(jYjjZjubaubajdj2ubejdj`ubajdj2 ubeubj )r}r(jYXw**Jumpers** * J4 – Short all the pins * JP37 – Short pins 1 & 2 * J43 - Short pins 1 & 2 * J8 – Short pins 1 & 2 jZjwjbjjdj jf}r(jh]ji]jj]jk]jn]ujpKjqhjr]r(j )r}r(jYX **Jumpers**rjZjjbjjdj jf}r(jh]ji]jj]jk]jn]ujpKjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XJumpersrr}r(jYUjZjubajdjubaubj )r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rjC)r}r(jYUjf}r(jGX*jk]jj]jh]ji]jn]ujZjjr]r¦(j/)ræ}rĦ(jYXJ4 – Short all the pinsrŦjf}rƦ(jh]ji]jj]jk]jn]ujZjjr]rǦj)rȦ}rɦ(jYjŦjZjæjbjjdjjf}rʦ(jh]ji]jj]jk]jn]ujpKjr]r˦j{XJ4 – Short all the pinsr̦rͦ}rΦ(jYjŦjZjȦubaubajdj2ubj/)rϦ}rЦ(jYXJP37 – Short pins 1 & 2rѦjf}rҦ(jh]ji]jj]jk]jn]ujZjjr]rӦj)rԦ}rզ(jYjѦjZjϦjbjjdjjf}r֦(jh]ji]jj]jk]jn]ujpKjr]rצj{XJP37 – Short pins 1 & 2rئr٦}rڦ(jYjѦjZjԦubaubajdj2ubj/)rۦ}rܦ(jYXJ43 - Short pins 1 & 2rݦjf}rަ(jh]ji]jj]jk]jn]ujZjjr]rߦj)r}r(jYjݦjZjۦjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XJ43 - Short pins 1 & 2rr}r(jYjݦjZjubaubajdj2ubj/)r}r(jYXJ8 – Short pins 1 & 2 jf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXJ8 – Short pins 1 & 2rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XJ8 – Short pins 1 & 2rr}r(jYjjZjubaubajdj2ubejdj`ubajdj2 ubeubeubeubj[)r}r(jYUjZjP\jbjjdjejf}r(jh]ji]jj]jk]rUam65x-debug-software-setuprajn]rhnaujpKjqhjr]r(jt)r}r(jYXAM65x Debug Software SetuprjZjjbjjdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XAM65x Debug Software Setuprr}r(jYjjZjubaubj)r}r(jYXCThe following software packages are required to setup the AM65x EVMrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XCThe following software packages are required to setup the AM65x EVMrr}r (jYjjZjubaubjC)r }r (jYUjZjjbjjdj`jf}r (jGX-jk]jj]jh]ji]jn]ujpKjqhjr]r (j/)r}r(jYX%Code Composer Studio IDE Environment jZj jbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYX$Code Composer Studio IDE EnvironmentrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X$Code Composer Studio IDE Environmentrr}r(jYjjZjubaubaubj/)r}r(jYXProcessor SDK RTOS for AM65xx jZj jbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXProcessor SDK RTOS for AM65xxr jZjjbjjdjjf}r!(jh]ji]jj]jk]jn]ujpKjr]r"j{XProcessor SDK RTOS for AM65xxr#r$}r%(jYj jZjubaubaubeubj[)r&}r'(jYUjZjjbjjdjejf}r((jh]ji]jj]jk]r)Uccs-host-setupr*ajn]r+haujpKjqhjr]r,(jt)r-}r.(jYXCCS Host Setupr/jZj&jbjjdjxjf}r0(jh]ji]jj]jk]jn]ujpKjqhjr]r1j{XCCS Host Setupr2r3}r4(jYj/jZj-ubaubj)r5}r6(jYX]1. Download CCS from the following link: http://processors.wiki.ti.com/index.php/Download_CCSjZj&jbjjdjjf}r7(jh]ji]jj]jk]jn]ujpKjqhjr]r8(j{X)1. Download CCS from the following link: r9r:}r;(jYX)1. Download CCS from the following link: jZj5ubj)r<}r=(jYX4http://processors.wiki.ti.com/index.php/Download_CCSr>jf}r?(Urefurij>jk]jj]jh]ji]jn]ujZj5jr]r@j{X4http://processors.wiki.ti.com/index.php/Download_CCSrArB}rC(jYUjZj<ubajdjubeubj)rD}rE(jYXCheck the `Processor SDK Release Notes `_ for the recommended CCS version.rFjZj&jbjjdjjf}rG(jh]ji]jj]jk]jn]ujpNjqhjr]rHj)rI}rJ(jYjFjZjDjbjjdjjf}rK(jh]ji]jj]jk]jn]ujpKjr]rL(j{X Check the rMrN}rO(jYX Check the jZjIubj)rP}rQ(jYX`Processor SDK Release Notes `_jf}rR(UnameXProcessor SDK Release NotesjXkhttp://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_release_specific.html#release-notesrSjk]jj]jh]ji]jn]ujZjIjr]rTj{XProcessor SDK Release NotesrUrV}rW(jYUjZjPubajdjubj)rX}rY(jYXn jKjZjIjdjjf}rZ(UrefurijSjk]r[Uprocessor-sdk-release-notesr\ajj]jh]ji]jn]r]haujr]ubj{X! for the recommended CCS version.r^r_}r`(jYX! for the recommended CCS version.jZjIubeubaubj)ra}rb(jYX9Ensure that at least "Sitara AMx Processors" is selected:rcjZj&jbjjdjjf}rd(jh]ji]jj]jk]jn]ujpKjqhjr]rej{X9Ensure that at least "Sitara AMx Processors" is selected:rfrg}rh(jYjcjZjaubaubj=)ri}rj(jYUjZj&jbNjdj@jf}rk(jh]ji]jj]jk]jn]ujpNjqhjr]rljB)rm}rn(jYXN.. image:: ../../../images/TMDX654_EVM_Hardware_Setup/AM65x_CCS_Install.png jf}ro(UuriXErtos/../../../images/TMDX654_EVM_Hardware_Setup/AM65x_CCS_Install.pngrpjk]jj]jh]ji]jH}rqU*jpsjn]ujZjijr]jdjEubaubj[)rr}rs(jYUjZj&jbjjdjejf}rt(jh]ji]jj]jk]ruU?install-the-latest-emulation-package-and-device-support-packagervajn]rwhaujpKjqhjr]rx(jt)ry}rz(jYX?Install the latest Emulation Package and Device Support Packager{jZjrjbjjdjxjf}r|(jh]ji]jj]jk]jn]ujpKjqhjr]r}j{X?Install the latest Emulation Package and Device Support Packager~r}r(jYj{jZjyubaubj)r}r(jYXv1. In CCS, navigate to Help -> Check for Updates and select "Sitara device support" and "TI Emulators" and click Next.rjZjrjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{Xv1. In CCS, navigate to Help -> Check for Updates and select "Sitara device support" and "TI Emulators" and click Next.rr}r(jYjjZjubaubj=)r}r(jYUjZjrjbNjdj@jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rjB)r}r(jYXP.. image:: ../../../images/TMDX654_EVM_Hardware_Setup/CCS_Check_for_Updates.PNG jf}r(UuriXIrtos/../../../images/TMDX654_EVM_Hardware_Setup/CCS_Check_for_Updates.PNGrjk]jj]jh]ji]jH}rU*jsjn]ujZjjr]jdjEubaubj)r}r(jYXx2. Click "Next" again, select "I accept the terms of the license agreements" and click Finish to begin the installation.rjZjrjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{Xx2. Click "Next" again, select "I accept the terms of the license agreements" and click Finish to begin the installation.rr}r(jYjjZjubaubj=)r}r(jYUjZjrjbNjdj@jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rjB)r}r(jYXP.. image:: ../../../images/TMDX654_EVM_Hardware_Setup/CCS_Updating_Software.png jf}r(UuriXIrtos/../../../images/TMDX654_EVM_Hardware_Setup/CCS_Updating_Software.pngrjk]jj]jh]ji]jH}rU*jsjn]ujZjjr]jdjEubaubj)r}r(jYX3. You may be prompted to restart CCS for the updates to take effect. Click "Restart Now" when prompted to complete the installation.rjZjrjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X3. You may be prompted to restart CCS for the updates to take effect. Click "Restart Now" when prompted to complete the installation.rr}r(jYjjZjubaubj)r}r(jYX**Disable Automatic Updates**rjZjrjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XDisable Automatic Updatesrr}r(jYUjZjubajdjubaubj)r}r(jYXTo disable automatic updates in CCS, navigate to Windows -> Preferences -> Install/Update -> Automatic Updates, and uncheck "Automatically find new updates and notify me."rjZjrjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XTo disable automatic updates in CCS, navigate to Windows -> Preferences -> Install/Update -> Automatic Updates, and uncheck "Automatically find new updates and notify me."rr}r(jYjjZjubaubj)r}r(jYXxThis is a precautionary step to avoid automatic updates overwriting files updated through TI Emulation Updates for AM65xrjZjrjbjjdjjf}r§(jh]ji]jj]jk]jn]ujpKjqhjr]rçj{XxThis is a precautionary step to avoid automatic updates overwriting files updated through TI Emulation Updates for AM65xrħrŧ}rƧ(jYjjZjubaubeubeubj[)rǧ}rȧ(jYUjZjjbjjdjejf}rɧ(jh]ji]jj]jk]rʧUbasic-ccs-setupr˧ajn]ŗj;aujpKjqhjr]rͧ(jt)rΧ}rϧ(jYXBasic CCS SetuprЧjZjǧjbjjdjxjf}rѧ(jh]ji]jj]jk]jn]ujpKjqhjr]rҧj{XBasic CCS Setuprӧrԧ}rէ(jYjЧjZjΧubaubj)r֧}rק(jYXThe Basic CCS setup is similar to earlier Sitara devices which involves creation of target configuration and connecting to cores using the GEL files. This step is suitable for new board bring up and getting hello world going on the AM65x cores.rاjZjǧjbjjdjjf}r٧(jh]ji]jj]jk]jn]ujpKjqhjr]rڧj{XThe Basic CCS setup is similar to earlier Sitara devices which involves creation of target configuration and connecting to cores using the GEL files. This step is suitable for new board bring up and getting hello world going on the AM65x cores.rۧrܧ}rݧ(jYjاjZj֧ubaubj)rާ}rߧ(jYX%Users can use this setup for benchmarking code on cores, test basic pin functionality or to run diagnostics. However, multi-core application developers requiring resource management, power management or security services will require the advanced CCS setup in addition to the basic core setup.rjZjǧjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X%Users can use this setup for benchmarking code on cores, test basic pin functionality or to run diagnostics. However, multi-core application developers requiring resource management, power management or security services will require the advanced CCS setup in addition to the basic core setup.rr}r(jYjjZjާubaubj)r}r(jYXWe recommend that you follow the steps in basic setup and then migrate to the advanced SOC CCS setup for application development.rjZjǧjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XWe recommend that you follow the steps in basic setup and then migrate to the advanced SOC CCS setup for application development.rr}r(jYjjZjubaubj[)r}r(jYUjZjǧjbjjdjejf}r(jh]ji]jj]jk]rU!creating-the-target-configurationrajn]rh(aujpKjqhjr]r(jt)r}r(jYX!Creating the Target ConfigurationrjZjjbjjdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{X!Creating the Target Configurationrr}r(jYjjZjubaubj%)r}r(jYUjZjjbjjdj(jf}r(j*U.jk]jj]jh]j+Uji]jn]j,j-ujpKjqhjr]r(j/)r}r(jYX_In CCS, open the Target Configurations window by navigating to View -> Target Configurations. jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYX]In CCS, open the Target Configurations window by navigating to View -> Target Configurations.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]r j{X]In CCS, open the Target Configurations window by navigating to View -> Target Configurations.r r }r (jYjjZjubaubaubj/)r }r(jYXNIn Target Configurations, right click and select "New Target Configuration." jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXLIn Target Configurations, right click and select "New Target Configuration."rjZj jbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XLIn Target Configurations, right click and select "New Target Configuration."rr}r(jYjjZjubaubaubj/)r}r(jYXQPopulate the Target Configuration File name, set the location, and click Finish. jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXPPopulate the Target Configuration File name, set the location, and click Finish.rjZjjbjjdjjf}r (jh]ji]jj]jk]jn]ujpKjr]r!j{XPPopulate the Target Configuration File name, set the location, and click Finish.r"r#}r$(jYjjZjubaubaubeubj=)r%}r&(jYUjZjjbNjdj@jf}r'(jh]ji]jj]jk]jn]ujpNjqhjr]r(jB)r)}r*(jYXV.. image:: ../../../images/TMDX654_EVM_Hardware_Setup/AM65x_Target_Configuration.png jf}r+(UuriXNrtos/../../../images/TMDX654_EVM_Hardware_Setup/AM65x_Target_Configuration.pngr,jk]jj]jh]ji]jH}r-U*j,sjn]ujZj%jr]jdjEubaubj%)r.}r/(jYUjZjjbjjdj(jf}r0(j*U.jdKjk]jj]jh]j+Uji]jn]j,j-ujpKjqhjr]r1j/)r2}r3(jYXpSelect "Texas Instruments XDS110 USB Debug Probe" for the Connection and "GPEVM_AM65x" for the Board or Device. jZj.jbjjdj2jf}r4(jh]ji]jj]jk]jn]ujpNjqhjr]r5j)r6}r7(jYXoSelect "Texas Instruments XDS110 USB Debug Probe" for the Connection and "GPEVM_AM65x" for the Board or Device.r8jZj2jbjjdjjf}r9(jh]ji]jj]jk]jn]ujpKjr]r:j{XoSelect "Texas Instruments XDS110 USB Debug Probe" for the Connection and "GPEVM_AM65x" for the Board or Device.r;r<}r=(jYj8jZj6ubaubaubaubj=)r>}r?(jYUjZjjbNjdj@jf}r@(jh]ji]jj]jk]jn]ujpNjqhjr]rAjB)rB}rC(jYXW.. image:: ../../../images/TMDX654_EVM_Hardware_Setup/AM65x_Target_Configuration2.png jf}rD(UuriXOrtos/../../../images/TMDX654_EVM_Hardware_Setup/AM65x_Target_Configuration2.pngrEjk]jj]jh]ji]jH}rFU*jEsjn]ujZj>jr]jdjEubaubj)rG}rH(jYXThe GEL files are automatically populated in the Target Configuration when selecting an EVM instead of an SOC. The SOC option is generally used for custom board bring up or secondary boot debugging.rIjZjjbjjdjjf}rJ(jh]ji]jj]jk]jn]ujpNjqhjr]rKj)rL}rM(jYjIjZjGjbjjdjjf}rN(jh]ji]jj]jk]jn]ujpMjr]rOj{XThe GEL files are automatically populated in the Target Configuration when selecting an EVM instead of an SOC. The SOC option is generally used for custom board bring up or secondary boot debugging.rPrQ}rR(jYjIjZjLubaubaubj%)rS}rT(jYUjZjjbjjdj(jf}rU(j*U.jdKjk]jj]jh]j+Uji]jn]j,j-ujpMjqhjr]rVj/)rW}rX(jYXNavigate to the "Advanced" tab to ensure the GEL files are populated in the "initialization script" field for the various cores. jZjSjbjjdj2jf}rY(jh]ji]jj]jk]jn]ujpNjqhjr]rZj)r[}r\(jYXNavigate to the "Advanced" tab to ensure the GEL files are populated in the "initialization script" field for the various cores.r]jZjWjbjjdjjf}r^(jh]ji]jj]jk]jn]ujpMjr]r_j{XNavigate to the "Advanced" tab to ensure the GEL files are populated in the "initialization script" field for the various cores.r`ra}rb(jYj]jZj[ubaubaubaubj=)rc}rd(jYUjZjjbNjdj@jf}re(jh]ji]jj]jk]jn]ujpNjqhjr]rfjB)rg}rh(jYXV.. image:: ../../../images/TMDX654_EVM_Hardware_Setup/AM65x_Target_Configuration3.png jf}ri(UuriXOrtos/../../../images/TMDX654_EVM_Hardware_Setup/AM65x_Target_Configuration3.pngrjjk]jj]jh]ji]jH}rkU*jjsjn]ujZjcjr]jdjEubaubj)rl}rm(jYXThe initialization script for the Cortex M3 will setup the MCU domain and Main domain PLL clocks, PSC registers, and bring the R5 and Cortex A53 cores out of reset.rnjZjjbjjdjjf}ro(jh]ji]jj]jk]jn]ujpM jqhjr]rpj{XThe initialization script for the Cortex M3 will setup the MCU domain and Main domain PLL clocks, PSC registers, and bring the R5 and Cortex A53 cores out of reset.rqrr}rs(jYjnjZjlubaubj)rt}ru(jYXThe initialization script for the Cortex A53 and Cortex R5 will perform a similar step to setup the DDR clocks and initialize DDR from the cores if required.rvjZjjbjjdjjf}rw(jh]ji]jj]jk]jn]ujpM jqhjr]rxj{XThe initialization script for the Cortex A53 and Cortex R5 will perform a similar step to setup the DDR clocks and initialize DDR from the cores if required.ryrz}r{(jYjvjZjtubaubj%)r|}r}(jYUjZjjbjjdj(jf}r~(j*U.jdKjk]jj]jh]j+Uji]jn]j,j-ujpMjqhjr]rj/)r}r(jYXSave the Target Configuration. jZj|jbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXSave the Target Configuration.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XSave the Target Configuration.rr}r(jYjjZjubaubaubaubj=)r}r(jYUjZjjbNjdj@jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rjB)r}r(jYXW.. image:: ../../../images/TMDX654_EVM_Hardware_Setup/AM65x_Target_Configuration4.png jf}r(UuriXOrtos/../../../images/TMDX654_EVM_Hardware_Setup/AM65x_Target_Configuration4.pngrjk]jj]jh]ji]jH}rU*jsjn]ujZjjr]jdjEubaubeubj[)r}r(jYUjZjǧjbjjdjejf}r(jh]ji]jj]jk]rU connecting-to-the-cores-on-am65xrajn]rhaujpMjqhjr]r(jt)r}r(jYX Connecting to the Cores on AM65xrjZjjbjjdjxjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{X Connecting to the Cores on AM65xrr}r(jYjjZjubaubj)r}r(jYX1. **Launch Target Configuration** In CCS Editor View, go to View -> Target Configuration, and right click on the configuration that was created in the previous section and select "Launch Selected Configuration."jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]r(j{X1. rr}r(jYX1. jZjubj)r}r(jYX**Launch Target Configuration**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XLaunch Target Configurationrr}r(jYUjZjubajdjubj{X In CCS Editor View, go to View -> Target Configuration, and right click on the configuration that was created in the previous section and select "Launch Selected Configuration."rr}r(jYX In CCS Editor View, go to View -> Target Configuration, and right click on the configuration that was created in the previous section and select "Launch Selected Configuration."jZjubeubj%)r}r(jYUjZjjbjjdj(jf}r(j*U.jdKjk]jj]jh]j+Uji]jn]j,j-ujpMjqhjr]rj/)r}r(jYX**Connect to DMSC_Cortex_M3** jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYX**Connect to DMSC_Cortex_M3**rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj)r¨}rè(jYjjf}rĨ(jh]ji]jj]jk]jn]ujZjjr]rŨj{XConnect to DMSC_Cortex_M3rƨrǨ}rȨ(jYUjZj¨ubajdjubaubaubaubj)rɨ}rʨ(jYXWhen connecting to the M3 core for the first time, you may be prompted with a firmware update. Please click "Update" to update the emulator firmware.r˨jZjjbjjdjjf}r̨(jh]ji]jj]jk]jn]ujpNjqhjr]rͨj)rΨ}rϨ(jYj˨jZjɨjbjjdjjf}rШ(jh]ji]jj]jk]jn]ujpMjr]rѨj{XWhen connecting to the M3 core for the first time, you may be prompted with a firmware update. Please click "Update" to update the emulator firmware.rҨrӨ}rԨ(jYj˨jZjΨubaubaubjB)rը}r֨(jYXJ.. image:: ../../../images/TMDX654_EVM_Hardware_Setup/AM65x_FW_Update.png jZjjbjjdjEjf}rר(UuriXCrtos/../../../images/TMDX654_EVM_Hardware_Setup/AM65x_FW_Update.pngrبjk]jj]jh]ji]jH}r٨U*jبsjn]ujpM jqhjr]ubj)rڨ}rۨ(jYX1On AM65x DMSC_Cortex_M3 is the boot master and is the first core that wakes up and starts the R5F ROM. Upon launching the target configuration, **connect to DMSC_Cortex_M3 first**, as this will automatically perform the PSC and PLL initialization. The following GEL output will appear in the CCS Console::rܨjZjjbjjdjjf}rݨ(jh]ji]jj]jk]jn]ujpM!jqhjr]rި(j{XOn AM65x DMSC_Cortex_M3 is the boot master and is the first core that wakes up and starts the R5F ROM. Upon launching the target configuration, rߨr}r(jYXOn AM65x DMSC_Cortex_M3 is the boot master and is the first core that wakes up and starts the R5F ROM. Upon launching the target configuration, jZjڨubj)r}r(jYX#**connect to DMSC_Cortex_M3 first**jf}r(jh]ji]jj]jk]jn]ujZjڨjr]rj{Xconnect to DMSC_Cortex_M3 firstrr}r(jYUjZjubajdjubj{X}, as this will automatically perform the PSC and PLL initialization. The following GEL output will appear in the CCS Console:rr}r(jYX}, as this will automatically perform the PSC and PLL initialization. The following GEL output will appear in the CCS Console:jZjڨubeubj)r}r(jYXDMSC_Cortex_M3_0: GEL Output: Configuring AM65xEVM... DMSC_Cortex_M3_0: GEL Output: Init value actual value: 0x00000888 DMSC_Cortex_M3_0: GEL Output: Register value: 0x00000888 DMSC_Cortex_M3_0: GEL Output: ATCM is on DMSC_Cortex_M3_0: GEL Output: ATCM configured. DMSC_Cortex_M3_0: GEL Output: Assuming execution from M3 DMSC_Cortex_M3_0: GEL Output: This script sets the first address translation region to [0x8000_0000, 0x0000_0000]. DMSC_Cortex_M3_0: GEL Output: It also sets the second address translation region to [0x6000_0000, 0x4000_0000]. DMSC_Cortex_M3_0: GEL Output: Setting all PLLs in progress. This may take some time. DMSC_Cortex_M3_0: GEL Output: 0 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 10 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 20 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 30 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 40 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 50 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 60 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 70 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 80 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 90 Percent Complete... DMSC_Cortex_M3_0: GEL Output: Setting all PLLs done! DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains in progress... DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP_COMMON DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP2MCU DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP2MAIN_INFRA DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DEBUG2DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP_GPIO DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU2MAIN_INFRA DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU2MAIN DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU2WKUP DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN2MCU DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_COMMON DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_TEST DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_MCAN_0 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_MCAN_1 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_OSPI_0 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_OSPI_1 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_HYPERBUS DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_DEBUG DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_R5_0 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_R5_1 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_INFRA DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_TEST DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_PBIST DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CC_TOP DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_CLUSTER_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_CLUSTER_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_2 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_3 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_DEBUG DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DSS DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MMC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CAL DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SAUL DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_COMMON DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_NB DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_2 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPU DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_DATA DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_CFG DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains done!jZjjbjjdjjf}r(jjjk]jj]jh]ji]jn]ujpMjqhjr]rj{XDMSC_Cortex_M3_0: GEL Output: Configuring AM65xEVM... DMSC_Cortex_M3_0: GEL Output: Init value actual value: 0x00000888 DMSC_Cortex_M3_0: GEL Output: Register value: 0x00000888 DMSC_Cortex_M3_0: GEL Output: ATCM is on DMSC_Cortex_M3_0: GEL Output: ATCM configured. DMSC_Cortex_M3_0: GEL Output: Assuming execution from M3 DMSC_Cortex_M3_0: GEL Output: This script sets the first address translation region to [0x8000_0000, 0x0000_0000]. DMSC_Cortex_M3_0: GEL Output: It also sets the second address translation region to [0x6000_0000, 0x4000_0000]. DMSC_Cortex_M3_0: GEL Output: Setting all PLLs in progress. This may take some time. DMSC_Cortex_M3_0: GEL Output: 0 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 10 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 20 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 30 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 40 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 50 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 60 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 70 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 80 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 90 Percent Complete... DMSC_Cortex_M3_0: GEL Output: Setting all PLLs done! DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains in progress... DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP_COMMON DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP2MCU DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP2MAIN_INFRA DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DEBUG2DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP_GPIO DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU2MAIN_INFRA DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU2MAIN DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU2WKUP DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN2MCU DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_COMMON DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_TEST DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_MCAN_0 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_MCAN_1 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_OSPI_0 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_OSPI_1 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_HYPERBUS DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_DEBUG DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_R5_0 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_R5_1 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_INFRA DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_TEST DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_PBIST DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CC_TOP DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_CLUSTER_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_CLUSTER_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_2 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_3 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_DEBUG DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DSS DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MMC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CAL DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SAUL DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_COMMON DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_NB DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_2 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPU DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_DATA DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_CFG DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains done!rr}r(jYUjZjubaubjZ)r}r(jYUjZjjbjjdj]jf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj`)r}r(jYUjcKjZjjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r}r(jYX3. **Connect to Cortex A53 or Cortex R5F** Users must now connect to either the Cortex A53 (CortexA53_0_0) or Cortex R5 (MCU_PULSAR_Cortex_R5_0). The following GEL output will appear in the CCS console when connecting to the Cortex A53::jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]r(j{X3. rr}r(jYX3. jZjubj)r}r(jYX'**Connect to Cortex A53 or Cortex R5F**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X#Connect to Cortex A53 or Cortex R5Frr}r(jYUjZjubajdjubj{X Users must now connect to either the Cortex A53 (CortexA53_0_0) or Cortex R5 (MCU_PULSAR_Cortex_R5_0). The following GEL output will appear in the CCS console when connecting to the Cortex A53:rr }r (jYX Users must now connect to either the Cortex A53 (CortexA53_0_0) or Cortex R5 (MCU_PULSAR_Cortex_R5_0). The following GEL output will appear in the CCS console when connecting to the Cortex A53:jZjubeubj)r }r (jYX CortexA53_0_0: GEL Output: VTT Regulator Enabled CortexA53_0_0: GEL Output: PHY Init complete CortexA53_0_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000000F CortexA53_0_0: GEL Output: Waiting for DRAM Init to complete... CortexA53_0_0: GEL Output: DRAM Init complete CortexA53_0_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F CortexA53_0_0: GEL Output: Waiting for write leveling to complete CortexA53_0_0: GEL Output: Write leveling complete CortexA53_0_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000003F CortexA53_0_0: GEL Output: checking status per byte... CortexA53_0_0: GEL Output: DDRSS_DDRPHY_DX0GSR0 = 0x00932420 CortexA53_0_0: GEL Output: DDRSS_DDRPHY_DX1GSR0 = 0x009224A0 CortexA53_0_0: GEL Output: DDRSS_DDRPHY_DX2GSR0 = 0x00992620 CortexA53_0_0: GEL Output: DDRSS_DDRPHY_DX3GSR0 = 0x009825A0 CortexA53_0_0: GEL Output: Waiting for Read DQS training to complete CortexA53_0_0: GEL Output: Read DQS training complete CortexA53_0_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000007F CortexA53_0_0: GEL Output: checking status per byte... CortexA53_0_0: GEL Output: DDRSS_DDRPHY_DX0RSR0 = 0x00000000 CortexA53_0_0: GEL Output: DDRSS_DDRPHY_DX1RSR0 = 0x00000000 CortexA53_0_0: GEL Output: DDRSS_DDRPHY_DX2RSR0 = 0x00000000 CortexA53_0_0: GEL Output: DDRSS_DDRPHY_DX3RSR0 = 0x00000000 CortexA53_0_0: GEL Output: Waiting for Write leveling adjustment to complete CortexA53_0_0: GEL Output: Write leveling adjustment complete CortexA53_0_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800000FF CortexA53_0_0: GEL Output: Waiting for Read deskew to complete CortexA53_0_0: GEL Output: Read deskew complete CortexA53_0_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800001FF CortexA53_0_0: GEL Output: Waiting for Write deskew to complete CortexA53_0_0: GEL Output: Write deskew complete CortexA53_0_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800003FF CortexA53_0_0: GEL Output: Waiting for Read Eye training to complete CortexA53_0_0: GEL Output: Read Eye training complete CortexA53_0_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800007FF CortexA53_0_0: GEL Output: Waiting for Write Eye training to complete CortexA53_0_0: GEL Output: Write Eye training complete CortexA53_0_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x80000FFF CortexA53_0_0: GEL Output: Waiting for VREF training to complete CortexA53_0_0: GEL Output: VREF training complete CortexA53_0_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x80004FFF CortexA53_0_0: GEL Output: ==== DDR4 Initialization has PASSED!!!! ====jZjjbjjdjjf}r (jjjk]jj]jh]ji]jn]ujpMjqhjr]rj{X CortexA53_0_0: GEL Output: VTT Regulator Enabled CortexA53_0_0: GEL Output: PHY Init complete CortexA53_0_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000000F CortexA53_0_0: GEL Output: Waiting for DRAM Init to complete... CortexA53_0_0: GEL Output: DRAM Init complete CortexA53_0_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F CortexA53_0_0: GEL Output: Waiting for write leveling to complete CortexA53_0_0: GEL Output: Write leveling complete CortexA53_0_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000003F CortexA53_0_0: GEL Output: checking status per byte... CortexA53_0_0: GEL Output: DDRSS_DDRPHY_DX0GSR0 = 0x00932420 CortexA53_0_0: GEL Output: DDRSS_DDRPHY_DX1GSR0 = 0x009224A0 CortexA53_0_0: GEL Output: DDRSS_DDRPHY_DX2GSR0 = 0x00992620 CortexA53_0_0: GEL Output: DDRSS_DDRPHY_DX3GSR0 = 0x009825A0 CortexA53_0_0: GEL Output: Waiting for Read DQS training to complete CortexA53_0_0: GEL Output: Read DQS training complete CortexA53_0_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000007F CortexA53_0_0: GEL Output: checking status per byte... CortexA53_0_0: GEL Output: DDRSS_DDRPHY_DX0RSR0 = 0x00000000 CortexA53_0_0: GEL Output: DDRSS_DDRPHY_DX1RSR0 = 0x00000000 CortexA53_0_0: GEL Output: DDRSS_DDRPHY_DX2RSR0 = 0x00000000 CortexA53_0_0: GEL Output: DDRSS_DDRPHY_DX3RSR0 = 0x00000000 CortexA53_0_0: GEL Output: Waiting for Write leveling adjustment to complete CortexA53_0_0: GEL Output: Write leveling adjustment complete CortexA53_0_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800000FF CortexA53_0_0: GEL Output: Waiting for Read deskew to complete CortexA53_0_0: GEL Output: Read deskew complete CortexA53_0_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800001FF CortexA53_0_0: GEL Output: Waiting for Write deskew to complete CortexA53_0_0: GEL Output: Write deskew complete CortexA53_0_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800003FF CortexA53_0_0: GEL Output: Waiting for Read Eye training to complete CortexA53_0_0: GEL Output: Read Eye training complete CortexA53_0_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800007FF CortexA53_0_0: GEL Output: Waiting for Write Eye training to complete CortexA53_0_0: GEL Output: Write Eye training complete CortexA53_0_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x80000FFF CortexA53_0_0: GEL Output: Waiting for VREF training to complete CortexA53_0_0: GEL Output: VREF training complete CortexA53_0_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x80004FFF CortexA53_0_0: GEL Output: ==== DDR4 Initialization has PASSED!!!! ====rr}r(jYUjZj ubaubjZ)r}r(jYUjZjjbjjdj]jf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj`)r}r(jYUjcKjZjjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r}r(jYXaThe same GEL output will be shown if connecting to the Cortex R5 first instead of the Cortex A53.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{XaThe same GEL output will be shown if connecting to the Cortex R5 first instead of the Cortex A53.rr}r (jYjjZjubaubj%)r!}r"(jYUjZjjbjjdj(jf}r#(j*U.jdKjk]jj]jh]j+Uji]jn]j,j-ujpMjqhjr]r$j/)r%}r&(jYXThe EVM is now completely initialized to load and run code on the cores and access the full device address range. User level software is responsible to configure the pin multiplexing and peripheral configuration. jZj!jbjjdj2jf}r'(jh]ji]jj]jk]jn]ujpNjqhjr]r(j)r)}r*(jYXThe EVM is now completely initialized to load and run code on the cores and access the full device address range. User level software is responsible to configure the pin multiplexing and peripheral configuration.r+jZj%jbjjdjjf}r,(jh]ji]jj]jk]jn]ujpMjr]r-j{XThe EVM is now completely initialized to load and run code on the cores and access the full device address range. User level software is responsible to configure the pin multiplexing and peripheral configuration.r.r/}r0(jYj+jZj)ubaubaubaubjZ)r1}r2(jYUjZjjbjjdj]jf}r3(jh]ji]jj]jk]jn]ujpMjqhjr]r4j`)r5}r6(jYUjcKjZj1jbjjdjpjf}r7(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubeubj[)r8}r9(jYUjKjZjjbjjdjejf}r:(jh]ji]jj]jk]r;jajn]r<h.aujpMjqhjr]r=(jt)r>}r?(jYX2Advanced AM65x Debug Setup with DMSC Firmware Loadr@jZj8jbjjdjxjf}rA(jh]ji]jj]jk]jn]ujpMjqhjr]rBj{X2Advanced AM65x Debug Setup with DMSC Firmware LoadrCrD}rE(jYj@jZj>ubaubj)rF}rG(jYX**Description**rHjZj8jbjjdjjf}rI(jh]ji]jj]jk]jn]ujpMjqhjr]rJj)rK}rL(jYjHjf}rM(jh]ji]jj]jk]jn]ujZjFjr]rNj{X DescriptionrOrP}rQ(jYUjZjKubajdjubaubj)rR}rS(jYXAM65x EVM users testing basic functionality like R5F and A53 bring up and DDR configuration can use the basic setup described in the previous section for setting up the EVM. However, advanced application level debug that uses resource management for UDMAs, interrupt setup, power management to setup clock modules, or wakeup/power of slave cores will require loading of SYSFW (DMSC Firmware) on the M3 core so that the application can make API calls to leverage its services.rTjZj8jbjjdjjf}rU(jh]ji]jj]jk]jn]ujpMjqhjr]rVj{XAM65x EVM users testing basic functionality like R5F and A53 bring up and DDR configuration can use the basic setup described in the previous section for setting up the EVM. However, advanced application level debug that uses resource management for UDMAs, interrupt setup, power management to setup clock modules, or wakeup/power of slave cores will require loading of SYSFW (DMSC Firmware) on the M3 core so that the application can make API calls to leverage its services.rWrX}rY(jYjTjZjRubaubj)rZ}r[(jYX;To load the SYSFW firmware, the DMSC ROM expects R5F secondary bootloader/application to provide board configuration message to initialize the cores and SOC services. The R5F application provided in SciClient uses a default board configuration message to the SYSFW and sets up the device for application debugging.r\jZj8jbjjdjjf}r](jh]ji]jj]jk]jn]ujpMjqhjr]r^j{X;To load the SYSFW firmware, the DMSC ROM expects R5F secondary bootloader/application to provide board configuration message to initialize the cores and SOC services. The R5F application provided in SciClient uses a default board configuration message to the SYSFW and sets up the device for application debugging.r_r`}ra(jYj\jZjZubaubj)rb}rc(jYX^For more details, refer to the Initialization Chapter in the TRM and the SciClient User guide.rdjZj8jbjjdjjf}re(jh]ji]jj]jk]jn]ujpMjqhjr]rfj{X^For more details, refer to the Initialization Chapter in the TRM and the SciClient User guide.rgrh}ri(jYjdjZjbubaubj)rj}rk(jYX"**Additional Software Dependency**rljZj8jbjjdjjf}rm(jh]ji]jj]jk]jn]ujpMjqhjr]rnj)ro}rp(jYjljf}rq(jh]ji]jj]jk]jn]ujZjjjr]rrj{XAdditional Software Dependencyrsrt}ru(jYUjZjoubajdjubaubj=)rv}rw(jYUjZj8jbNjdj@jf}rx(jh]ji]jj]jk]jn]ujpNjqhjr]ryjC)rz}r{(jYUjf}r|(jGX*jk]jj]jh]ji]jn]ujZjvjr]r}j/)r~}r(jYXProcessor SDK RTOS for AM65x jf}r(jh]ji]jj]jk]jn]ujZjzjr]rj)r}r(jYXProcessor SDK RTOS for AM65xrjZj~jbjjdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XProcessor SDK RTOS for AM65xrr}r(jYjjZjubaubajdj2ubajdj`ubaubj)r}r(jYX~Users are required to install Processor SDK RTOS to obtain the SciClient component package before proceeding to the Next Step.rjZj8jbjjdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{X~Users are required to install Processor SDK RTOS to obtain the SciClient component package before proceeding to the Next Step.rr}r(jYjjZjubaubj)r}r(jYXAfter installing Processor SDK RTOS, users should locate the latest R5F CCS init app, SYSFW binary, and the debug server script within the following directory:rjZj8jbjjdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{XAfter installing Processor SDK RTOS, users should locate the latest R5F CCS init app, SYSFW binary, and the debug server script within the following directory:rr}r(jYjjZjubaubj)r}r(jYX?${PDK_INSTALL_PATH}/packages/ti/drv/sciclient/tools/ccsLoadDmscrjZj8jbjjdjjf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj{X?${PDK_INSTALL_PATH}/packages/ti/drv/sciclient/tools/ccsLoadDmscrr}r(jYjjZjubaubj)r}r(jYXAThe following files are provided as part for the SciClient tools:rjZj8jbjjdjjf}r(jh]ji]jj]jk]jn]ujpM jqhjr]rj{XAThe following files are provided as part for the SciClient tools:rr}r(jYjjZjubaubj=)r}r(jYUjZj8jbjjdj@jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]r(jC)r}r(jYUjf}r(jGX*jk]jj]jh]ji]jn]ujZjjr]rj/)r}r(jYXtlaunch_am65xx.js: CCS Debug Server script to perform on target connect and load DMSC firmware and R5F CCS Init app. jf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXslaunch_am65xx.js: CCS Debug Server script to perform on target connect and load DMSC firmware and R5F CCS Init app.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpM jr]rj{Xslaunch_am65xx.js: CCS Debug Server script to perform on target connect and load DMSC firmware and R5F CCS Init app.rr}r(jYjjZjubaubajdj2ubajdj`ubj)r}r(jYXN**Location:**: ${PDK_INSTALL_PATH}/packages/ti/drv/sciclient/tools/ccsLoadDmscjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpMjr]r(j)r©}ré(jYX **Location:**jf}rĩ(jh]ji]jj]jk]jn]ujZjjr]rũj{X Location:rƩrǩ}rȩ(jYUjZj©ubajdjubj{XA: ${PDK_INSTALL_PATH}/packages/ti/drv/sciclient/tools/ccsLoadDmscrɩrʩ}r˩(jYXA: ${PDK_INSTALL_PATH}/packages/ti/drv/sciclient/tools/ccsLoadDmscjZjubeubjC)r̩}rͩ(jYUjf}rΩ(jGX*jk]jj]jh]ji]jn]ujZjjr]rϩj/)rЩ}rѩ(jYXSsciclient_ccs_init_mcu1_0_release.xer5f: R5F Application with default board config jf}rҩ(jh]ji]jj]jk]jn]ujZj̩jr]rөj)rԩ}rթ(jYXRsciclient_ccs_init_mcu1_0_release.xer5f: R5F Application with default board configr֩jZjЩjbjjdjjf}rש(jh]ji]jj]jk]jn]ujpMjr]rةj{XRsciclient_ccs_init_mcu1_0_release.xer5f: R5F Application with default board configr٩rک}r۩(jYj֩jZjԩubaubajdj2ubajdj`ubj)rܩ}rݩ(jYXU**Location:**: ${PDK_INSTALL_PATH}/packages/ti/drv/sciclient/tools/ccsLoadDmsc/am65xxjZjjbjjdjjf}rީ(jh]ji]jj]jk]jn]ujpMjr]rߩ(j)r}r(jYX **Location:**jf}r(jh]ji]jj]jk]jn]ujZjܩjr]rj{X Location:rr}r(jYUjZjubajdjubj{XH: ${PDK_INSTALL_PATH}/packages/ti/drv/sciclient/tools/ccsLoadDmsc/am65xxrr}r(jYXH: ${PDK_INSTALL_PATH}/packages/ti/drv/sciclient/tools/ccsLoadDmsc/am65xxjZjܩubeubjC)r}r(jYUjf}r(jGX*jk]jj]jh]ji]jn]ujZjjr]rj/)r}r(jYXCti-sci-firmware-am6x-gp.bin: TISCI SYSFW binary loaded on the DMSC jf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXBti-sci-firmware-am6x-gp.bin: TISCI SYSFW binary loaded on the DMSCrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpMjr]rj{XBti-sci-firmware-am6x-gp.bin: TISCI SYSFW binary loaded on the DMSCrr}r(jYjjZjubaubajdj2ubajdj`ubj)r}r(jYXC**Location:**: ${PDK_INSTALL_PATH}/packages/ti/drv/sciclient/src/V0jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpMjr]r(j)r}r(jYX **Location:**jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X Location:rr}r(jYUjZjubajdjubj{X6: ${PDK_INSTALL_PATH}/packages/ti/drv/sciclient/src/V0rr}r(jYX6: ${PDK_INSTALL_PATH}/packages/ti/drv/sciclient/src/V0jZjubeubeubj)r}r (jYX AM65x Advanced Debug Script Flowr jZj8jbjjdjjf}r (jh]ji]jj]jk]jn]ujpMjqhjr]r j{X AM65x Advanced Debug Script Flowr r}r(jYj jZjubaubjB)r}r(jYXN.. image:: ../../../images/TMDX654_EVM_Hardware_Setup/AM65x_Advanced_Flow.png jZj8jbjjdjEjf}r(UuriXGrtos/../../../images/TMDX654_EVM_Hardware_Setup/AM65x_Advanced_Flow.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpMjqhjr]ubjZ)r}r(jYUjZj8jbjjdj]jf}r(jh]ji]jj]jk]jn]ujpMjqhjr]rj`)r}r(jYUjcKjZjjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj[)r}r(jYUjZj8jbjjdjejf}r(jh]ji]jj]jk]rURcreating-debug-configuration-to-integrate-ccs-gel-and-dmsc-firmware-initializationr ajn]r!haujpM jqhjr]r"(jt)r#}r$(jYXRCreating Debug Configuration to Integrate CCS GEL and DMSC Firmware Initializationr%jZjjbjjdjxjf}r&(jh]ji]jj]jk]jn]ujpM jqhjr]r'j{XRCreating Debug Configuration to Integrate CCS GEL and DMSC Firmware Initializationr(r)}r*(jYj%jZj#ubaubj)r+}r,(jYXWith the intent to maintain the same CCS target connect flow as existing devices, we provide a Debug Server Script (DSS) that users can link to in their target configuration to allow for loading SYSFW firmware on the DMSC as part of the target connect process.r-jZjjbjjdjjf}r.(jh]ji]jj]jk]jn]ujpM"jqhjr]r/j{XWith the intent to maintain the same CCS target connect flow as existing devices, we provide a Debug Server Script (DSS) that users can link to in their target configuration to allow for loading SYSFW firmware on the DMSC as part of the target connect process.r0r1}r2(jYj-jZj+ubaubj)r3}r4(jYXThe DSS script allows users to perform all of the initialization using a single click. When the script is run, the following actions happens sequentially:r5jZjjbjjdjjf}r6(jh]ji]jj]jk]jn]ujpM$jqhjr]r7j{XThe DSS script allows users to perform all of the initialization using a single click. When the script is run, the following actions happens sequentially:r8r9}r:(jYj5jZj3ubaubj%)r;}r<(jYUjZjjbjjdj(jf}r=(j*U.jk]jj]jh]j+Uji]jn]j,j-ujpM&jqhjr]r>(j/)r?}r@(jYX3Running On Target Connect M3 existing GEL scripts. jZj;jbjjdj2jf}rA(jh]ji]jj]jk]jn]ujpNjqhjr]rBj)rC}rD(jYX2Running On Target Connect M3 existing GEL scripts.rEjZj?jbjjdjjf}rF(jh]ji]jj]jk]jn]ujpM&jr]rGj{X2Running On Target Connect M3 existing GEL scripts.rHrI}rJ(jYjEjZjCubaubaubj/)rK}rL(jYX5Loading the DMSC firmware ``*``.bin file to DMSC M3. jZj;jbjjdj2jf}rM(jh]ji]jj]jk]jn]ujpNjqhjr]rNj)rO}rP(jYX4Loading the DMSC firmware ``*``.bin file to DMSC M3.jZjKjbjjdjjf}rQ(jh]ji]jj]jk]jn]ujpM(jr]rR(j{XLoading the DMSC firmware rSrT}rU(jYXLoading the DMSC firmware jZjOubji')rV}rW(jYX``*``jf}rX(jh]ji]jj]jk]jn]ujZjOjr]rYj{X*rZ}r[(jYUjZjVubajdjq'ubj{X.bin file to DMSC M3.r\r]}r^(jYX.bin file to DMSC M3.jZjOubeubaubj/)r_}r`(jYXMRun the R5F Init code which performs the board configuration initialization. jZj;jbjjdj2jf}ra(jh]ji]jj]jk]jn]ujpNjqhjr]rbj)rc}rd(jYXLRun the R5F Init code which performs the board configuration initialization.rejZj_jbjjdjjf}rf(jh]ji]jj]jk]jn]ujpM*jr]rgj{XLRun the R5F Init code which performs the board configuration initialization.rhri}rj(jYjejZjcubaubaubeubj)rk}rl(jYXAt the end of the setup, the R5F and A53 are in a clean state to load code and debug the application with the SYSFW loaded on the M3 core.rmjZjjbjjdjjf}rn(jh]ji]jj]jk]jn]ujpM,jqhjr]roj{XAt the end of the setup, the R5F and A53 are in a clean state to load code and debug the application with the SYSFW loaded on the M3 core.rprq}rr(jYjmjZjkubaubj)rs}rt(jYXB**Steps to Link and Run the DSS Script for DMSC Firmware Loading**rujZjjbjjdjjf}rv(jh]ji]jj]jk]jn]ujpM.jqhjr]rwj)rx}ry(jYjujf}rz(jh]ji]jj]jk]jn]ujZjsjr]r{j{X>Steps to Link and Run the DSS Script for DMSC Firmware Loadingr|r}}r~(jYUjZjxubajdjubaubj%)r}r(jYUjZjjbjjdj(jf}r(j*U.jk]jj]jh]j+Uji]jn]j,j-ujpM0jqhjr]rj/)r}r(jYXUpdate the file "pdk/packages/ti/drv/sciclient/tools/ccsLoadDmsc/launch_am65xx.js" for the following variable to your PC location: jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXUpdate the file "pdk/packages/ti/drv/sciclient/tools/ccsLoadDmsc/launch_am65xx.js" for the following variable to your PC location:rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpM0jr]rj{XUpdate the file "pdk/packages/ti/drv/sciclient/tools/ccsLoadDmsc/launch_am65xx.js" for the following variable to your PC location:rr}r(jYjjZjubaubaubaubj=)r}r(jYUjZjjbNjdj@jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]r(j)r}r(jYX // // Set this to 1 to allow loading the GEL files directly from the ccxml file. disableGelLoad = 1; if (disableGelLoad == 0) { //Path to GEL files gelFilePath = "C:/ti/ccsv8/ccs_base/emulation/gel/AM65xEVM"; } // Path to the directory in which this file would be residing. CCS expects // absolute paths to load the binaries. thisJsFileDirectory = "pdk/packages/ti/drv/sciclient/tools/ccsLoadDmsc"; //jZjjbjjdjjf}r(jjXcjjjk]jj]jh]j }rUhl_linesr]r(KK esji]jn]ujpM2jr]rj{X // // Set this to 1 to allow loading the GEL files directly from the ccxml file. disableGelLoad = 1; if (disableGelLoad == 0) { //Path to GEL files gelFilePath = "C:/ti/ccsv8/ccs_base/emulation/gel/AM65xEVM"; } // Path to the directory in which this file would be residing. CCS expects // absolute paths to load the binaries. thisJsFileDirectory = "pdk/packages/ti/drv/sciclient/tools/ccsLoadDmsc"; //rr}r(jYUjZjubaubjC)r}r(jYUjf}r(jGX*jk]jj]jh]ji]jn]ujZjjr]r(j/)r}r(jYX[Set disableGelLoad =1 if GEL files is linked to the cores in the target configuration file.rjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpMCjr]rj{X[Set disableGelLoad =1 if GEL files is linked to the cores in the target configuration file.rr}r(jYjjZjubaubajdj2ubj/)r}r(jYXjThe variable "gelFilePath" doesn't need to be updated if CCS is installed in the default C:/ti/ directory.rjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpMDjr]rj{XjThe variable "gelFilePath" doesn't need to be updated if CCS is installed in the default C:/ti/ directory.rr}r(jYjjZjubaubajdj2ubj/)r}r(jYX^The variable "thisJsFileDirectory" needs to be updated to point to the PDK install directory. jf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX]The variable "thisJsFileDirectory" needs to be updated to point to the PDK install directory.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpMEjr]rj{X]The variable "thisJsFileDirectory" needs to be updated to point to the PDK install directory.rªrê}rĪ(jYjjZjubaubajdj2ubejdj`ubeubj%)rŪ}rƪ(jYUjZjjbjjdj(jf}rǪ(j*U.jdKjk]jj]jh]j+Uji]jn]j,j-ujpMGjqhjr]rȪj/)rɪ}rʪ(jYXEConnect the Javascript to the CCXML file with the steps shown below. jZjŪjbjjdj2jf}r˪(jh]ji]jj]jk]jn]ujpNjqhjr]r̪j)rͪ}rΪ(jYXDConnect the Javascript to the CCXML file with the steps shown below.rϪjZjɪjbjjdjjf}rЪ(jh]ji]jj]jk]jn]ujpMGjr]rѪj{XDConnect the Javascript to the CCXML file with the steps shown below.rҪrӪ}rԪ(jYjϪjZjͪubaubaubaubj)rժ}r֪(jYXPThis step needs to be repeated if you switch workspaces or clean your workspace.rתjZjjbjjdjjf}rت(jh]ji]jj]jk]jn]ujpNjqhjr]r٪j)rڪ}r۪(jYjתjZjժjbjjdjjf}rܪ(jh]ji]jj]jk]jn]ujpMIjr]rݪj{XPThis step needs to be repeated if you switch workspaces or clean your workspace.rުrߪ}r(jYjתjZjڪubaubaubj)r}r(jYXtIn the debug view after completing the basic CCS setup, Click on Debug Configurations from the button as show below:rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpMKjqhjr]rj{XtIn the debug view after completing the basic CCS setup, Click on Debug Configurations from the button as show below:rr}r(jYjjZjubaubjB)r}r(jYXK.. image:: ../../../images/TMDX654_EVM_Hardware_Setup/CCS_Debug_Config.png jZjjbjjdjEjf}r(UuriXDrtos/../../../images/TMDX654_EVM_Hardware_Setup/CCS_Debug_Config.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpMNjqhjr]ubj)r}r(jYXSelect the CCXML file from the left-hand side and populate the path to the launch_am65xx.js file in the "Initialization Script" free form field and click on "Apply".rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpMOjqhjr]rj{XSelect the CCXML file from the left-hand side and populate the path to the launch_am65xx.js file in the "Initialization Script" free form field and click on "Apply".rr}r(jYjjZjubaubjB)r}r(jYXH.. image:: ../../../images/TMDX654_EVM_Hardware_Setup/CCS_Debug_XML.png jZjjbjjdjEjf}r(UuriXArtos/../../../images/TMDX654_EVM_Hardware_Setup/CCS_Debug_XML.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpMRjqhjr]ubj)r}r(jYXZOnce you Launch the CCXML file, the java script will automatically run and connect to R5F.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpMSjqhjr]rj{XZOnce you Launch the CCXML file, the java script will automatically run and connect to R5F.rr}r(jYjjZjubaubj)r}r(jYX>**Steps to re-run the script once ccxml is already launched:**rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpMUjqhjr]rj)r}r (jYjjf}r (jh]ji]jj]jk]jn]ujZjjr]r j{X:Steps to re-run the script once ccxml is already launched:r r }r(jYUjZjubajdjubaubj)r}r(jYX<In the CCS window, navigate to "View → Scripting Console."rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpMWjqhjr]rj{X<In the CCS window, navigate to "View → Scripting Console."rr}r(jYjjZjubaubj)r}r(jYX$In the CCS Scripting Console, type::rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpMYjqhjr]rj{X#In the CCS Scripting Console, type:rr}r(jYX#In the CCS Scripting Console, type:jZjubaubj)r}r (jYX*> load ("\\launch_am65xx.js");jZjjbjjdjjf}r!(jjjk]jj]jh]ji]jn]ujpMjqhjr]r"j{X*> load ("\\launch_am65xx.js");r#r$}r%(jYUjZjubaubj)r&}r'(jYX?This would give the following output on the scripting console::r(jZjjbjjdjjf}r)(jh]ji]jj]jk]jn]ujpM]jqhjr]r*j{X>This would give the following output on the scripting console:r+r,}r-(jYX>This would give the following output on the scripting console:jZj&ubaubj)r.}r/(jYX js:> load("C:\\Users\\User\\Documents\\PDK\\pdk\\packages\\ti\\drv\\sciclient\\tools\\ccsLoadDmsc\\launch_am65xx.js") Connecting to DMSC_Cortex_M3_0! Loading DMSC Firmware... DMSC Firmware Load Done... DMSC Firmware run starting now... Connecting to MCU Cortex_R5_0!jZjjbjjdjjf}r0(jjjk]jj]jh]ji]jn]ujpMjqhjr]r1j{X js:> load("C:\\Users\\User\\Documents\\PDK\\pdk\\packages\\ti\\drv\\sciclient\\tools\\ccsLoadDmsc\\launch_am65xx.js") Connecting to DMSC_Cortex_M3_0! Loading DMSC Firmware... DMSC Firmware Load Done... DMSC Firmware run starting now... Connecting to MCU Cortex_R5_0!r2r3}r4(jYUjZj.ubaubj)r5}r6(jYXGEL Output Log::r7jZjjbjjdjjf}r8(jh]ji]jj]jk]jn]ujpMfjqhjr]r9j{XGEL Output Log:r:r;}r<(jYXGEL Output Log:jZj5ubaubj)r=}r>(jYX&DMSC_Cortex_M3_0: GEL Output: Configuring AM65xEVM... DMSC_Cortex_M3_0: GEL Output: Init value actual value: 0x00000888 DMSC_Cortex_M3_0: GEL Output: Register value: 0x00000888 DMSC_Cortex_M3_0: GEL Output: ATCM is on DMSC_Cortex_M3_0: GEL Output: ATCM configured. DMSC_Cortex_M3_0: GEL Output: Assuming execution from M3 DMSC_Cortex_M3_0: GEL Output: This script sets the first address translation region to [0x8000_0000, 0x0000_0000]. DMSC_Cortex_M3_0: GEL Output: It also sets the second address translation region to [0x6000_0000, 0x4000_0000]. DMSC_Cortex_M3_0: GEL Output: Setting all PLLs in progress. This may take some time. DMSC_Cortex_M3_0: GEL Output: 0 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 10 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 20 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 30 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 40 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 50 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 60 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 70 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 80 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 90 Percent Complete... DMSC_Cortex_M3_0: GEL Output: Setting all PLLs done! DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains in progress... DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP_COMMON DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP2MCU DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP2MAIN_INFRA DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DEBUG2DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP_GPIO DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU2MAIN_INFRA DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU2MAIN DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU2WKUP DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN2MCU DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_COMMON DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_TEST DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_MCAN_0 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_MCAN_1 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_OSPI_0 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_OSPI_1 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_HYPERBUS DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_DEBUG DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_R5_0 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_R5_1 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_INFRA DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_TEST DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_PBIST DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CC_TOP DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_CLUSTER_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_CLUSTER_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_2 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_3 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_DEBUG DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DSS DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MMC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CAL DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SAUL DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_COMMON DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_NB DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_2 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPU DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_DATA DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_CFG DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains done! MCU_PULSAR_Cortex_R5_0: GEL Output: VTT Regulator Enabled MCU_PULSAR_Cortex_R5_0: GEL Output: PHY Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000000F MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for DRAM Init to complete... MCU_PULSAR_Cortex_R5_0: GEL Output: DRAM Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for write leveling to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write leveling complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000003F MCU_PULSAR_Cortex_R5_0: GEL Output: checking status per byte... MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX0GSR0 = 0x00A728A0 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX1GSR0 = 0x00AA2920 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX2GSR0 = 0x00AB2920 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX3GSR0 = 0x00AA2A20 MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Read DQS training to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Read DQS training complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000007F MCU_PULSAR_Cortex_R5_0: GEL Output: checking status per byte... MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX0RSR0 = 0x00000000 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX1RSR0 = 0x00000000 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX2RSR0 = 0x00000000 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX3RSR0 = 0x00000000 MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Write leveling adjustment to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write leveling adjustment complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800000FF MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Read deskew to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Read deskew complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800001FF MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Write deskew to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write deskew complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800003FF MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Read Eye training to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Read Eye training complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800007FF MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Write Eye training to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write Eye training complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x80000FFF MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for VREF training to complete MCU_PULSAR_Cortex_R5_0: GEL Output: VREF training complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x80004FFF MCU_PULSAR_Cortex_R5_0: GEL Output: ==== DDR4 Initialization has PASSED!!!! ====jZjjbjjdjjf}r?(jjjk]jj]jh]ji]jn]ujpMjqhjr]r@j{X&DMSC_Cortex_M3_0: GEL Output: Configuring AM65xEVM... DMSC_Cortex_M3_0: GEL Output: Init value actual value: 0x00000888 DMSC_Cortex_M3_0: GEL Output: Register value: 0x00000888 DMSC_Cortex_M3_0: GEL Output: ATCM is on DMSC_Cortex_M3_0: GEL Output: ATCM configured. DMSC_Cortex_M3_0: GEL Output: Assuming execution from M3 DMSC_Cortex_M3_0: GEL Output: This script sets the first address translation region to [0x8000_0000, 0x0000_0000]. DMSC_Cortex_M3_0: GEL Output: It also sets the second address translation region to [0x6000_0000, 0x4000_0000]. DMSC_Cortex_M3_0: GEL Output: Setting all PLLs in progress. This may take some time. DMSC_Cortex_M3_0: GEL Output: 0 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 10 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 20 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 30 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 40 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 50 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 60 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 70 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 80 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 90 Percent Complete... DMSC_Cortex_M3_0: GEL Output: Setting all PLLs done! DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains in progress... DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP_COMMON DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP2MCU DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP2MAIN_INFRA DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DEBUG2DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP_GPIO DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU2MAIN_INFRA DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU2MAIN DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU2WKUP DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN2MCU DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_COMMON DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_TEST DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_MCAN_0 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_MCAN_1 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_OSPI_0 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_OSPI_1 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_HYPERBUS DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_DEBUG DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_R5_0 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_R5_1 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_INFRA DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_TEST DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_PBIST DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CC_TOP DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_CLUSTER_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_CLUSTER_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_2 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_3 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_DEBUG DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DSS DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MMC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CAL DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SAUL DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_COMMON DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_NB DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_2 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPU DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_DATA DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_CFG DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains done! MCU_PULSAR_Cortex_R5_0: GEL Output: VTT Regulator Enabled MCU_PULSAR_Cortex_R5_0: GEL Output: PHY Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000000F MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for DRAM Init to complete... MCU_PULSAR_Cortex_R5_0: GEL Output: DRAM Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for write leveling to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write leveling complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000003F MCU_PULSAR_Cortex_R5_0: GEL Output: checking status per byte... MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX0GSR0 = 0x00A728A0 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX1GSR0 = 0x00AA2920 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX2GSR0 = 0x00AB2920 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX3GSR0 = 0x00AA2A20 MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Read DQS training to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Read DQS training complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000007F MCU_PULSAR_Cortex_R5_0: GEL Output: checking status per byte... MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX0RSR0 = 0x00000000 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX1RSR0 = 0x00000000 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX2RSR0 = 0x00000000 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX3RSR0 = 0x00000000 MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Write leveling adjustment to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write leveling adjustment complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800000FF MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Read deskew to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Read deskew complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800001FF MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Write deskew to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write deskew complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800003FF MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Read Eye training to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Read Eye training complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800007FF MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Write Eye training to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write Eye training complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x80000FFF MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for VREF training to complete MCU_PULSAR_Cortex_R5_0: GEL Output: VREF training complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x80004FFF MCU_PULSAR_Cortex_R5_0: GEL Output: ==== DDR4 Initialization has PASSED!!!! ====rArB}rC(jYUjZj=ubaubjZ)rD}rE(jYUjZjjbjjdj]jf}rF(jh]ji]jj]jk]jn]ujpM+jqhjr]rGj`)rH}rI(jYUjcKjZjDjbjjdjpjf}rJ(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubeubj[)rK}rL(jYUjZj8jbjjdjejf}rM(jh]ji]jj]jk]rNUadditional-notes-for-gel-usersrOajn]rPhaujpM.jqhjr]rQ(jt)rR}rS(jYXAdditional Notes for GEL UsersrTjZjKjbjjdjxjf}rU(jh]ji]jj]jk]jn]ujpM.jqhjr]rVj{XAdditional Notes for GEL UsersrWrX}rY(jYjTjZjRubaubj)rZ}r[(jYX#**R5F in Split Mode Configuration**r\jZjKjbjjdjjf}r](jh]ji]jj]jk]jn]ujpM0jqhjr]r^j)r_}r`(jYj\jf}ra(jh]ji]jj]jk]jn]ujZjZjr]rbj{XR5F in Split Mode Configurationrcrd}re(jYUjZj_ubajdjubaubj)rf}rg(jYXAM65x EVM ships with the dual Cortex R5F configured in lockstep mode. The AM65x EVM GEL file provides a GEL function "Change_MCUSS_to_SplitMode" that can be added to OnTargetConnect or invoked from the DMSC_Cortex_M3 to set the dual R5F in split mode.rhjZjKjbjjdjjf}ri(jh]ji]jj]jk]jn]ujpM2jqhjr]rjj{XAM65x EVM ships with the dual Cortex R5F configured in lockstep mode. The AM65x EVM GEL file provides a GEL function "Change_MCUSS_to_SplitMode" that can be added to OnTargetConnect or invoked from the DMSC_Cortex_M3 to set the dual R5F in split mode.rkrl}rm(jYjhjZjfubaubj)rn}ro(jYX%**Configuring PRU-ICSS in Sync Mode**rpjZjKjbjjdjjf}rq(jh]ji]jj]jk]jn]ujpM5jqhjr]rrj)rs}rt(jYjpjf}ru(jh]ji]jj]jk]jn]ujZjnjr]rvj{X!Configuring PRU-ICSS in Sync Moderwrx}ry(jYUjZjsubajdjubaubj)rz}r{(jYXThe PRU-ICSS subsystem can be configured to SYNC mode (250 Mhz) using the GEL function "PRU_ICSSG_SyncMode_250MHz" from Cortex A53 or R5Fr|jZjKjbjjdjjf}r}(jh]ji]jj]jk]jn]ujpM7jqhjr]r~j{XThe PRU-ICSS subsystem can be configured to SYNC mode (250 Mhz) using the GEL function "PRU_ICSSG_SyncMode_250MHz" from Cortex A53 or R5Frr}r(jYj|jZjzubaubj)r}r(jYXAM572x GP EVM Hardware SetupjZjKjbjcjdjjf}r(jjjk]jj]jh]ji]jn]ujpKhjqhjr]rj{XAM572x GP EVM Hardware Setuprr}r(jYUjZjubaubj)r}r(jYX4====================================================jZjKjbjcjdjjf}r(jjjk]jj]jh]ji]jn]ujpKijqhjr]rj{X4====================================================rr}r(jYUjZjubaubj)r}r(jYXDhttp://processors.wiki.ti.com/index.php/AM572x_GP_EVM_Hardware_SetupjZjKjbjr\jdjjf}r(jjjk]jj]jh]ji]jn]ujpKjqhjr]rj{XDhttp://processors.wiki.ti.com/index.php/AM572x_GP_EVM_Hardware_Setuprr}r(jYUjZjubaubeubeubeubeubjbjjdjejf}r(jh]rjraji]jj]jk]rUevm-layout-and-key-componentsrajn]ujpKjqhjr]r(jt)r}r(jYXEVM Layout and Key ComponentsrjZjN\jbjjdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XEVM Layout and Key Componentsrr}r(jYjjZjubaubj)r}r(jYXXRefer to the image below which highlights the key components available on the AM65x EVM.rjZjN\jbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XXRefer to the image below which highlights the key components available on the AM65x EVM.rr}r(jYjjZjubaubjB)r}r(jYXM.. image:: ../../../images/TMDX654_EVM_Hardware_Setup/AM65x_IDK_Diagram.png jZjN\jbjjdjEjf}r(UuriXErtos/../../../images/TMDX654_EVM_Hardware_Setup/AM65x_IDK_Diagram.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpK jqhjr]ubj)r}r(jYXThe complete feature set for the AM65x EVM is described in AM65x EVM User Manual. This section only provides description of components that are required to complete basic EVM setup for debugging code using an emulator and Code Composer Studio.rjZjN\jbjjdjjf}r(jh]ji]jj]jk]jn]ujpK jqhjr]rj{XThe complete feature set for the AM65x EVM is described in AM65x EVM User Manual. This section only provides description of components that are required to complete basic EVM setup for debugging code using an emulator and Code Composer Studio.rr}r(jYjjZjubaubj[)r}r(jYUjKjZjN\jbjjdjejf}r(jh]rjsaji]jj]jk]rU%supported-jtag-debug-probes-emulatorsrajn]ujpKjqhjr]r(jt)r}r(jYX'Supported JTAG Debug Probes (Emulators)r«jZjjbjjdjxjf}rë(jh]ji]jj]jk]jn]ujpKjqhjr]rīj{X'Supported JTAG Debug Probes (Emulators)rūrƫ}rǫ(jYj«jZjubaubj)rȫ}rɫ(jYXThe AM65x EVM includes a cTI20 JTAG connector for external emulators and a micro USB connector for the on-board XDS110 emulator.rʫjZjjbjjdjjf}r˫(jh]ji]jj]jk]jn]ujpKjqhjr]r̫j{XThe AM65x EVM includes a cTI20 JTAG connector for external emulators and a micro USB connector for the on-board XDS110 emulator.rͫrΫ}rϫ(jYjʫjZjȫubaubj)rЫ}rѫ(jYXXFor XDS110 connect a USB cable to the micro USB connector J23 on the front of the board.rҫjZjjbjjdjjf}rӫ(jh]ji]jj]jk]jn]ujpKjqhjr]rԫj{XXFor XDS110 connect a USB cable to the micro USB connector J23 on the front of the board.rիr֫}r׫(jYjҫjZjЫubaubj)rث}r٫(jYXEFor external XDS200, connect the emulator to the cTI20 pin connector.rګjZjjbjjdjjf}r۫(jh]ji]jj]jk]jn]ujpKjqhjr]rܫj{XEFor external XDS200, connect the emulator to the cTI20 pin connector.rݫrޫ}r߫(jYjګjZjثubaubj)r}r(jYXoFor Lauterbach or emulators with MIPI60 or TI14 pin connector, an adapter must be used to connect the emulator.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XoFor Lauterbach or emulators with MIPI60 or TI14 pin connector, an adapter must be used to connect the emulator.rr}r(jYjjZjubaubj)r}r(jYXwDo not connect an XDS560 emulator to the J16 application board connector. This may damage the EVM and the emulator pod.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XwDo not connect an XDS560 emulator to the J16 application board connector. This may damage the EVM and the emulator pod.rr}r(jYjjZjubaubaubjB)r}r(jYXc.. image:: ../../../images/TMDX654_EVM_Hardware_Setup/AM65x_JTAG.png :width: 600px jZjjbjjdjEjf}r(jh]UuriX>rtos/../../../images/TMDX654_EVM_Hardware_Setup/AM65x_JTAG.pngrjk]jj]UwidthX600pxji]jH}rU*jsjn]ujpNjqhjr]ubjZ)r}r(jYUjZjjbjjdj]jf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj`)r}r(jYUjcKjZjjbjjdjpjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]ubaubj)r}r(jYX If you are using an external emulator pod, you must select which connector sources the clock. The AM65x EVM can support the MIPI60 or cTI20 connector. The JTAG select jumper must be set correctly to specify the clock source as either the MIPI60 or the cTI20 connector.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK!jqhjr]rj{X If you are using an external emulator pod, you must select which connector sources the clock. The AM65x EVM can support the MIPI60 or cTI20 connector. The JTAG select jumper must be set correctly to specify the clock source as either the MIPI60 or the cTI20 connector.rr}r(jYjjZjubaubjB)r}r (jYXN.. image:: ../../../images/TMDX654_EVM_Hardware_Setup/AM65x_Clock_Select.png jZjjbjjdjEjf}r (UuriXFrtos/../../../images/TMDX654_EVM_Hardware_Setup/AM65x_Clock_Select.pngr jk]jj]jh]ji]jH}r U*j sjn]ujpK%jqhjr]ubeubj[)r }r(jYUjZjN\jbjjdjejf}r(jh]ji]jj]jk]rUbootmode-switchesrajn]rhuaujpK'jqhjr]r(jt)r}r(jYXBOOTMODE SwitchesrjZj jbjjdjxjf}r(jh]ji]jj]jk]jn]ujpK'jqhjr]rj{XBOOTMODE Switchesrr}r(jYjjZjubaubjB)r}r(jYXK.. image:: ../../../images/TMDX654_EVM_Hardware_Setup/AM65x_Boot_Modes.png jZj jbjjdjEjf}r(UuriXDrtos/../../../images/TMDX654_EVM_Hardware_Setup/AM65x_Boot_Modes.pngrjk]jj]jh]ji]jH}r U*jsjn]ujpK*jqhjr]ubj)r!}r"(jYX**MCU BOOTMODE shown:**r#jZj jbjjdjjf}r$(jh]ji]jj]jk]jn]ujpK+jqhjr]r%j)r&}r'(jYj#jf}r((jh]ji]jj]jk]jn]ujZj!jr]r)j{XMCU BOOTMODE shown:r*r+}r,(jYUjZj&ubajdjubaubj)r-}r.(jYX(MCUBOOTMODE[8:0] – **0000** 10 **011**r/jZj jbjjdjjf}r0(jh]ji]jj]jk]jn]ujpK-jqhjr]r1(j{XMCUBOOTMODE[8:0] – r2r3}r4(jYXMCUBOOTMODE[8:0] – jZj-ubj)r5}r6(jYX**0000**jf}r7(jh]ji]jj]jk]jn]ujZj-jr]r8j{X0000r9r:}r;(jYUjZj5ubajdjubj{X 10 r<r=}r>(jYX 10 jZj-ubj)r?}r@(jYX**011**jf}rA(jh]ji]jj]jk]jn]ujZj-jr]rBj{X011rCrD}rE(jYUjZj?ubajdjubeubj)rF}rG(jYX(Values in bold are fixed with resistors.rHjZj jbjjdjjf}rI(jh]ji]jj]jk]jn]ujpK/jqhjr]rJj{X(Values in bold are fixed with resistors.rKrL}rM(jYjHjZjFubaubj)rN}rO(jYX**BOOTMODE shown:**rPjZj jbjjdjjf}rQ(jh]ji]jj]jk]jn]ujpK1jqhjr]rRj)rS}rT(jYjPjf}rU(jh]ji]jj]jk]jn]ujZjNjr]rVj{XBOOTMODE shown:rWrX}rY(jYUjZjSubajdjubaubj)rZ}r[(jYX$BOOTMODE[18:0] - 1111111000011110000r\jZj jbjjdjjf}r](jh]ji]jj]jk]jn]ujpK3jqhjr]r^j{X$BOOTMODE[18:0] - 1111111000011110000r_r`}ra(jYj\jZjZubaubj[)rb}rc(jYUjZj jbjjdjejf}rd(jh]ji]jj]jk]reUrecommended-boot-moderfajn]rghaujpK9jqhjr]rh(jt)ri}rj(jYXRecommended Boot ModerkjZjbjbjjdjxjf}rl(jh]ji]jj]jk]jn]ujpK9jqhjr]rmj{XRecommended Boot Modernro}rp(jYjkjZjiubaubj)rq}rr(jYXOBOOTMODE[18:0] = 000000000 0000000000 MCUBOOTMODE[8:0]= 000000011 (SLEEP BOOT)rsjZjbjbjjdjjf}rt(jh]ji]jj]jk]jn]ujpK:jqhjr]ruj{XOBOOTMODE[18:0] = 000000000 0000000000 MCUBOOTMODE[8:0]= 000000011 (SLEEP BOOT)rvrw}rx(jYjsjZjqubaubj )ry}rz(jYUjZjbjbNjdj3 jf}r{(jh]ji]jj]jk]jn]ujpNjqhjr]r|j )r}}r~(jYXH**Boot Settings** * SW2 – All switches OFF * SW3 – All switches OFF jZjyjbjjdj jf}r(jh]ji]jj]jk]jn]ujpK>jr]r(j )r}r(jYX**Boot Settings**rjZj}jbjjdj jf}r(jh]ji]jj]jk]jn]ujpK>jr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X Boot Settingsrr}r(jYUjZjubajdjubaubj )r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj}jr]rjC)r}r(jYUjf}r(jGX*jk]jj]jh]ji]jn]ujZjjr]r(j/)r}r(jYXSW2 – All switches OFFrjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK=jr]rj{XSW2 – All switches OFFrr}r(jYjjZjubaubajdj2ubj/)r}r(jYXSW3 – All switches OFF jf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXSW3 – All switches OFFrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK>jr]rj{XSW3 – All switches OFFrr}r(jYjjZjubaubajdj2ubejdj`ubajdj2 ubeubaubj)r}r(jYXOBOOTMODE[18:0] = 000000100 0000000110 MCUBOOTMODE[8:0]= 000000011 (SD BOOT)rjZjbjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK@jqhjr]rj{XOBOOTMODE[18:0] = 000000100 0000000110 MCUBOOTMODE[8:0]= 000000011 (SD BOOT)rr}r(jYjjZjubaubjB)r}r(jYXN.. image:: ../../../images/TMDX654_EVM_Hardware_Setup/AM65x_Boot_Switches.png jZjbjbjjdjEjf}r(UuriXGrtos/../../../images/TMDX654_EVM_Hardware_Setup/AM65x_Boot_Switches.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpKCjqhjr]ubj)r}r(jYXJFor full details on supported boot modes, please refer to the table below.rjZjbjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKDjqhjr]rj{XJFor full details on supported boot modes, please refer to the table below.rr}r(jYjjZjubaubjd$)r¬}rì(jYUjZjbjbjjdjg$jf}rĬ(jh]ji]jj]jk]jn]ujpNjqhjr]rŬjj$)rƬ}rǬ(jYUjf}rȬ(jk]jj]jh]ji]jn]UcolsKujZj¬jr]rɬ(jo$)rʬ}rˬ(jYUjf}r̬(jk]jj]jh]ji]jn]UcolwidthKujZjƬjr]jdjs$ubjo$)rͬ}rά(jYUjf}rϬ(jk]jj]jh]ji]jn]UcolwidthKujZjƬjr]jdjs$ubjo$)rЬ}rѬ(jYUjf}rҬ(jk]jj]jh]ji]jn]UcolwidthKujZjƬjr]jdjs$ubjo$)rӬ}rԬ(jYUjf}rլ(jk]jj]jh]ji]jn]UcolwidthKujZjƬjr]jdjs$ubjo$)r֬}r׬(jYUjf}rج(jk]jj]jh]ji]jn]UcolwidthKCujZjƬjr]jdjs$ubjz$)r٬}rڬ(jYUjf}r۬(jh]ji]jj]jk]jn]ujZjƬjr]rܬj$)rݬ}rެ(jYUjf}r߬(jh]ji]jj]jk]jn]ujZj٬jr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjݬjr]rj)r}r(jYXSW3.4rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKGjr]rj{XSW3.4rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjݬjr]rj)r}r(jYXSW3.3rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKGjr]rj{XSW3.3rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjݬjr]rj)r}r(jYXSW3.2rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKGjr]rj{XSW3.2rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjݬjr]rj)r }r (jYXSW3.1r jZjjbjjdjjf}r (jh]ji]jj]jk]jn]ujpKGjr]r j{XSW3.1rr}r(jYj jZj ubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjݬjr]rj)r}r(jYXPrimary Boot Device SelectedrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKGjr]rj{XPrimary Boot Device Selectedrr}r(jYjjZjubaubajdj$ubejdj$ubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjƬjr]r (j$)r!}r"(jYUjf}r#(jh]ji]jj]jk]jn]ujZjjr]r$(j$)r%}r&(jYUjf}r'(jh]ji]jj]jk]jn]ujZj!jr]r(j)r)}r*(jYXOFFr+jZj%jbjjdjjf}r,(jh]ji]jj]jk]jn]ujpKIjr]r-j{XOFFr.r/}r0(jYj+jZj)ubaubajdj$ubj$)r1}r2(jYUjf}r3(jh]ji]jj]jk]jn]ujZj!jr]r4j)r5}r6(jYXOFFr7jZj1jbjjdjjf}r8(jh]ji]jj]jk]jn]ujpKIjr]r9j{XOFFr:r;}r<(jYj7jZj5ubaubajdj$ubj$)r=}r>(jYUjf}r?(jh]ji]jj]jk]jn]ujZj!jr]r@j)rA}rB(jYXOFFrCjZj=jbjjdjjf}rD(jh]ji]jj]jk]jn]ujpKIjr]rEj{XOFFrFrG}rH(jYjCjZjAubaubajdj$ubj$)rI}rJ(jYUjf}rK(jh]ji]jj]jk]jn]ujZj!jr]rLj)rM}rN(jYXOFFrOjZjIjbjjdjjf}rP(jh]ji]jj]jk]jn]ujpKIjr]rQj{XOFFrRrS}rT(jYjOjZjMubaubajdj$ubj$)rU}rV(jYUjf}rW(jh]ji]jj]jk]jn]ujZj!jr]rXj)rY}rZ(jYXSleep (No boot - debug mode)r[jZjUjbjjdjjf}r\(jh]ji]jj]jk]jn]ujpKIjr]r]j{XSleep (No boot - debug mode)r^r_}r`(jYj[jZjYubaubajdj$ubejdj$ubj$)ra}rb(jYUjf}rc(jh]ji]jj]jk]jn]ujZjjr]rd(j$)re}rf(jYUjf}rg(jh]ji]jj]jk]jn]ujZjajr]rhj)ri}rj(jYXOFFrkjZjejbjjdjjf}rl(jh]ji]jj]jk]jn]ujpKKjr]rmj{XOFFrnro}rp(jYjkjZjiubaubajdj$ubj$)rq}rr(jYUjf}rs(jh]ji]jj]jk]jn]ujZjajr]rtj)ru}rv(jYXOFFrwjZjqjbjjdjjf}rx(jh]ji]jj]jk]jn]ujpKKjr]ryj{XOFFrzr{}r|(jYjwjZjuubaubajdj$ubj$)r}}r~(jYUjf}r(jh]ji]jj]jk]jn]ujZjajr]rj)r}r(jYXOFFrjZj}jbjjdjjf}r(jh]ji]jj]jk]jn]ujpKKjr]rj{XOFFrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjajr]rj)r}r(jYXONrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKKjr]rj{XONrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjajr]rj)r}r(jYXOSPIrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKKjr]rj{XOSPIrr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXOFFrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKMjr]rj{XOFFrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXOFFrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKMjr]rj{XOFFrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r­(jYXONríjZjjbjjdjjf}rĭ(jh]ji]jj]jk]jn]ujpKMjr]rŭj{XONrƭrǭ}rȭ(jYjíjZjubaubajdj$ubj$)rɭ}rʭ(jYUjf}r˭(jh]ji]jj]jk]jn]ujZjjr]r̭j)rͭ}rέ(jYXOFFrϭjZjɭjbjjdjjf}rЭ(jh]ji]jj]jk]jn]ujpKMjr]rѭj{XOFFrҭrӭ}rԭ(jYjϭjZjͭubaubajdj$ubj$)rխ}r֭(jYUjf}r׭(jh]ji]jj]jk]jn]ujZjjr]rحj)r٭}rڭ(jYXQSPIrۭjZjխjbjjdjjf}rܭ(jh]ji]jj]jk]jn]ujpKMjr]rݭj{XQSPIrޭr߭}r(jYjۭjZj٭ubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXOFFrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKOjr]rj{XOFFrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXOFFrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKOjr]rj{XOFFrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXONrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKOjr]rj{XONrr}r(jYjjZjubaubajdj$ubj$)r }r (jYUjf}r (jh]ji]jj]jk]jn]ujZjjr]r j)r }r(jYXONrjZj jbjjdjjf}r(jh]ji]jj]jk]jn]ujpKOjr]rj{XONrr}r(jYjjZj ubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX HyperflashrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKOjr]rj{X Hyperflashrr}r (jYjjZjubaubajdj$ubejdj$ubj$)r!}r"(jYUjf}r#(jh]ji]jj]jk]jn]ujZjjr]r$(j$)r%}r&(jYUjf}r'(jh]ji]jj]jk]jn]ujZj!jr]r(j)r)}r*(jYXOFFr+jZj%jbjjdjjf}r,(jh]ji]jj]jk]jn]ujpKQjr]r-j{XOFFr.r/}r0(jYj+jZj)ubaubajdj$ubj$)r1}r2(jYUjf}r3(jh]ji]jj]jk]jn]ujZj!jr]r4j)r5}r6(jYXONr7jZj1jbjjdjjf}r8(jh]ji]jj]jk]jn]ujpKQjr]r9j{XONr:r;}r<(jYj7jZj5ubaubajdj$ubj$)r=}r>(jYUjf}r?(jh]ji]jj]jk]jn]ujZj!jr]r@j)rA}rB(jYXOFFrCjZj=jbjjdjjf}rD(jh]ji]jj]jk]jn]ujpKQjr]rEj{XOFFrFrG}rH(jYjCjZjAubaubajdj$ubj$)rI}rJ(jYUjf}rK(jh]ji]jj]jk]jn]ujZj!jr]rLj)rM}rN(jYXOFFrOjZjIjbjjdjjf}rP(jh]ji]jj]jk]jn]ujpKQjr]rQj{XOFFrRrS}rT(jYjOjZjMubaubajdj$ubj$)rU}rV(jYUjf}rW(jh]ji]jj]jk]jn]ujZj!jr]rXj)rY}rZ(jYX,SPI (on QSPI/OSPI port 0 in legacy SPI mode)r[jZjUjbjjdjjf}r\(jh]ji]jj]jk]jn]ujpKQjr]r]j{X,SPI (on QSPI/OSPI port 0 in legacy SPI mode)r^r_}r`(jYj[jZjYubaubajdj$ubejdj$ubj$)ra}rb(jYUjf}rc(jh]ji]jj]jk]jn]ujZjjr]rd(j$)re}rf(jYUjf}rg(jh]ji]jj]jk]jn]ujZjajr]rhj)ri}rj(jYXOFFrkjZjejbjjdjjf}rl(jh]ji]jj]jk]jn]ujpKSjr]rmj{XOFFrnro}rp(jYjkjZjiubaubajdj$ubj$)rq}rr(jYUjf}rs(jh]ji]jj]jk]jn]ujZjajr]rtj)ru}rv(jYXONrwjZjqjbjjdjjf}rx(jh]ji]jj]jk]jn]ujpKSjr]ryj{XONrzr{}r|(jYjwjZjuubaubajdj$ubj$)r}}r~(jYUjf}r(jh]ji]jj]jk]jn]ujZjajr]rj)r}r(jYXOFFrjZj}jbjjdjjf}r(jh]ji]jj]jk]jn]ujpKSjr]rj{XOFFrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjajr]rj)r}r(jYXONrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKSjr]rj{XONrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjajr]rj)r}r(jYXI2CrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKSjr]rj{XI2Crr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXOFFrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKUjr]rj{XOFFrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXONrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKUjr]rj{XONrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r®(jYXONrîjZjjbjjdjjf}rĮ(jh]ji]jj]jk]jn]ujpKUjr]rŮj{XONrƮrǮ}rȮ(jYjîjZjubaubajdj$ubj$)rɮ}rʮ(jYUjf}rˮ(jh]ji]jj]jk]jn]ujZjjr]r̮j)rͮ}rή(jYXOFFrϮjZjɮjbjjdjjf}rЮ(jh]ji]jj]jk]jn]ujpKUjr]rѮj{XOFFrҮrӮ}rԮ(jYjϮjZjͮubaubajdj$ubj$)rծ}r֮(jYUjf}r׮(jh]ji]jj]jk]jn]ujZjjr]rخj)rٮ}rڮ(jYX.MMC/SD card, eMMC boot from UDA or file systemrۮjZjծjbjjdjjf}rܮ(jh]ji]jj]jk]jn]ujpKUjr]rݮj{X.MMC/SD card, eMMC boot from UDA or file systemrޮr߮}r(jYjۮjZjٮubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXOFFrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKWjr]rj{XOFFrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXONrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKWjr]rj{XONrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXONrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKWjr]rj{XONrr}r(jYjjZjubaubajdj$ubj$)r }r (jYUjf}r (jh]ji]jj]jk]jn]ujZjjr]r j)r }r(jYXONrjZj jbjjdjjf}r(jh]ji]jj]jk]jn]ujpKWjr]rj{XONrr}r(jYjjZj ubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXEthernetrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKWjr]rj{XEthernetrr}r (jYjjZjubaubajdj$ubejdj$ubj$)r!}r"(jYUjf}r#(jh]ji]jj]jk]jn]ujZjjr]r$(j$)r%}r&(jYUjf}r'(jh]ji]jj]jk]jn]ujZj!jr]r(j)r)}r*(jYXONr+jZj%jbjjdjjf}r,(jh]ji]jj]jk]jn]ujpKYjr]r-j{XONr.r/}r0(jYj+jZj)ubaubajdj$ubj$)r1}r2(jYUjf}r3(jh]ji]jj]jk]jn]ujZj!jr]r4j)r5}r6(jYXOFFr7jZj1jbjjdjjf}r8(jh]ji]jj]jk]jn]ujpKYjr]r9j{XOFFr:r;}r<(jYj7jZj5ubaubajdj$ubj$)r=}r>(jYUjf}r?(jh]ji]jj]jk]jn]ujZj!jr]r@j)rA}rB(jYXOFFrCjZj=jbjjdjjf}rD(jh]ji]jj]jk]jn]ujpKYjr]rEj{XOFFrFrG}rH(jYjCjZjAubaubajdj$ubj$)rI}rJ(jYUjf}rK(jh]ji]jj]jk]jn]ujZj!jr]rLj)rM}rN(jYXOFFrOjZjIjbjjdjjf}rP(jh]ji]jj]jk]jn]ujpKYjr]rQj{XOFFrRrS}rT(jYjOjZjMubaubajdj$ubj$)rU}rV(jYUjf}rW(jh]ji]jj]jk]jn]ujZj!jr]rXj)rY}rZ(jYXUSBr[jZjUjbjjdjjf}r\(jh]ji]jj]jk]jn]ujpKYjr]r]j{XUSBr^r_}r`(jYj[jZjYubaubajdj$ubejdj$ubj$)ra}rb(jYUjf}rc(jh]ji]jj]jk]jn]ujZjjr]rd(j$)re}rf(jYUjf}rg(jh]ji]jj]jk]jn]ujZjajr]rhj)ri}rj(jYXONrkjZjejbjjdjjf}rl(jh]ji]jj]jk]jn]ujpK[jr]rmj{XONrnro}rp(jYjkjZjiubaubajdj$ubj$)rq}rr(jYUjf}rs(jh]ji]jj]jk]jn]ujZjajr]rtj)ru}rv(jYXOFFrwjZjqjbjjdjjf}rx(jh]ji]jj]jk]jn]ujpK[jr]ryj{XOFFrzr{}r|(jYjwjZjuubaubajdj$ubj$)r}}r~(jYUjf}r(jh]ji]jj]jk]jn]ujZjajr]rj)r}r(jYXOFFrjZj}jbjjdjjf}r(jh]ji]jj]jk]jn]ujpK[jr]rj{XOFFrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjajr]rj)r}r(jYXONrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK[jr]rj{XONrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjajr]rj)r}r(jYXPCIerjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK[jr]rj{XPCIerr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXONrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK]jr]rj{XONrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXOFFrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK]jr]rj{XOFFrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r¯(jYXONrïjZjjbjjdjjf}rį(jh]ji]jj]jk]jn]ujpK]jr]růj{XONrƯrǯ}rȯ(jYjïjZjubaubajdj$ubj$)rɯ}rʯ(jYUjf}r˯(jh]ji]jj]jk]jn]ujZjjr]r̯j)rͯ}rί(jYXOFFrϯjZjɯjbjjdjjf}rЯ(jh]ji]jj]jk]jn]ujpK]jr]rѯj{XOFFrүrӯ}rԯ(jYjϯjZjͯubaubajdj$ubj$)rկ}r֯(jYUjf}rׯ(jh]ji]jj]jk]jn]ujZjjr]rدj)rٯ}rگ(jYXUARTrۯjZjկjbjjdjjf}rܯ(jh]ji]jj]jk]jn]ujpK]jr]rݯj{XUARTrޯr߯}r(jYjۯjZjٯubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXONrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK_jr]rj{XONrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXOFFrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK_jr]rj{XOFFrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXONrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK_jr]rj{XONrr}r(jYjjZjubaubajdj$ubj$)r }r (jYUjf}r (jh]ji]jj]jk]jn]ujZjjr]r j)r }r(jYXONrjZj jbjjdjjf}r(jh]ji]jj]jk]jn]ujpK_jr]rj{XONrr}r(jYjjZj ubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXReservedrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK_jr]rj{XReservedrr}r (jYjjZjubaubajdj$ubejdj$ubj$)r!}r"(jYUjf}r#(jh]ji]jj]jk]jn]ujZjjr]r$(j$)r%}r&(jYUjf}r'(jh]ji]jj]jk]jn]ujZj!jr]r(j)r)}r*(jYXONr+jZj%jbjjdjjf}r,(jh]ji]jj]jk]jn]ujpKajr]r-j{XONr.r/}r0(jYj+jZj)ubaubajdj$ubj$)r1}r2(jYUjf}r3(jh]ji]jj]jk]jn]ujZj!jr]r4j)r5}r6(jYXONr7jZj1jbjjdjjf}r8(jh]ji]jj]jk]jn]ujpKajr]r9j{XONr:r;}r<(jYj7jZj5ubaubajdj$ubj$)r=}r>(jYUjf}r?(jh]ji]jj]jk]jn]ujZj!jr]r@j)rA}rB(jYXOFFrCjZj=jbjjdjjf}rD(jh]ji]jj]jk]jn]ujpKajr]rEj{XOFFrFrG}rH(jYjCjZjAubaubajdj$ubj$)rI}rJ(jYUjf}rK(jh]ji]jj]jk]jn]ujZj!jr]rLj)rM}rN(jYXOFFrOjZjIjbjjdjjf}rP(jh]ji]jj]jk]jn]ujpKajr]rQj{XOFFrRrS}rT(jYjOjZjMubaubajdj$ubj$)rU}rV(jYUjf}rW(jh]ji]jj]jk]jn]ujZj!jr]rXj)rY}rZ(jYXGPMC XIPr[jZjUjbjjdjjf}r\(jh]ji]jj]jk]jn]ujpKajr]r]j{XGPMC XIPr^r_}r`(jYj[jZjYubaubajdj$ubejdj$ubj$)ra}rb(jYUjf}rc(jh]ji]jj]jk]jn]ujZjjr]rd(j$)re}rf(jYUjf}rg(jh]ji]jj]jk]jn]ujZjajr]rhj)ri}rj(jYXONrkjZjejbjjdjjf}rl(jh]ji]jj]jk]jn]ujpKcjr]rmj{XONrnro}rp(jYjkjZjiubaubajdj$ubj$)rq}rr(jYUjf}rs(jh]ji]jj]jk]jn]ujZjajr]rtj)ru}rv(jYXONrwjZjqjbjjdjjf}rx(jh]ji]jj]jk]jn]ujpKcjr]ryj{XONrzr{}r|(jYjwjZjuubaubajdj$ubj$)r}}r~(jYUjf}r(jh]ji]jj]jk]jn]ujZjajr]rj)r}r(jYXOFFrjZj}jbjjdjjf}r(jh]ji]jj]jk]jn]ujpKcjr]rj{XOFFrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjajr]rj)r}r(jYXONrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKcjr]rj{XONrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjajr]rj)r}r(jYXBeMMC boot from boot partition (with auto-fall back to file system)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKcjr]rj{XBeMMC boot from boot partition (with auto-fall back to file system)rr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXONrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKejr]rj{XONrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXONrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKejr]rj{XONrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r°(jYXONrðjZjjbjjdjjf}rİ(jh]ji]jj]jk]jn]ujpKejr]rŰj{XONrưrǰ}rȰ(jYjðjZjubaubajdj$ubj$)rɰ}rʰ(jYUjf}r˰(jh]ji]jj]jk]jn]ujZjjr]r̰j)rͰ}rΰ(jYXOFFrϰjZjɰjbjjdjjf}rа(jh]ji]jj]jk]jn]ujpKejr]rѰj{XOFFrҰrӰ}r԰(jYjϰjZjͰubaubajdj$ubj$)rհ}rְ(jYUjf}rװ(jh]ji]jj]jk]jn]ujZjjr]rذj)rٰ}rڰ(jYXReserved (acts as no boot)r۰jZjհjbjjdjjf}rܰ(jh]ji]jj]jk]jn]ujpKejr]rݰj{XReserved (acts as no boot)rްr߰}r(jYj۰jZjٰubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXONrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKgjr]rj{XONrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXONrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKgjr]rj{XONrr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXONrjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKgjr]rj{XONrr}r(jYjjZjubaubajdj$ubj$)r }r (jYUjf}r (jh]ji]jj]jk]jn]ujZjjr]r j)r }r(jYXONrjZj jbjjdjjf}r(jh]ji]jj]jk]jn]ujpKgjr]rj{XONrr}r(jYjjZj ubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYXReserved (acts as no boot)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKgjr]rj{XReserved (acts as no boot)rr}r (jYjjZjubaubajdj$ubejdj$ubejdjy%ubejdjz%ubaubj)r!}r"(jYXfOn the AM65x EVM, ensure that the PLL configuration is set to 25 MHz (see bolded line in table below).r#jZjbjbjjdjjf}r$(jh]ji]jj]jk]jn]ujpNjqhjr]r%j)r&}r'(jYj#jZj!jbjjdjjf}r((jh]ji]jj]jk]jn]ujpKjjr]r)j{XfOn the AM65x EVM, ensure that the PLL configuration is set to 25 MHz (see bolded line in table below).r*r+}r,(jYj#jZj&ubaubaubjd$)r-}r.(jYUjZjbjbjjdjg$jf}r/(jh]ji]jj]jk]jn]ujpNjqhjr]r0jj$)r1}r2(jYUjf}r3(jk]jj]jh]ji]jn]UcolsKujZj-jr]r4(jo$)r5}r6(jYUjf}r7(jk]jj]jh]ji]jn]UcolwidthKujZj1jr]jdjs$ubjo$)r8}r9(jYUjf}r:(jk]jj]jh]ji]jn]UcolwidthKujZj1jr]jdjs$ubjo$)r;}r<(jYUjf}r=(jk]jj]jh]ji]jn]UcolwidthKujZj1jr]jdjs$ubjo$)r>}r?(jYUjf}r@(jk]jj]jh]ji]jn]UcolwidthK/ujZj1jr]jdjs$ubjz$)rA}rB(jYUjf}rC(jh]ji]jj]jk]jn]ujZj1jr]rDj$)rE}rF(jYUjf}rG(jh]ji]jj]jk]jn]ujZjAjr]rH(j$)rI}rJ(jYUjf}rK(jh]ji]jj]jk]jn]ujZjEjr]rLj)rM}rN(jYXBit 2rOjZjIjbjjdjjf}rP(jh]ji]jj]jk]jn]ujpKmjr]rQj{XBit 2rRrS}rT(jYjOjZjMubaubajdj$ubj$)rU}rV(jYUjf}rW(jh]ji]jj]jk]jn]ujZjEjr]rXj)rY}rZ(jYXBit 1r[jZjUjbjjdjjf}r\(jh]ji]jj]jk]jn]ujpKmjr]r]j{XBit 1r^r_}r`(jYj[jZjYubaubajdj$ubj$)ra}rb(jYUjf}rc(jh]ji]jj]jk]jn]ujZjEjr]rdj)re}rf(jYXBit 0rgjZjajbjjdjjf}rh(jh]ji]jj]jk]jn]ujpKmjr]rij{XBit 0rjrk}rl(jYjgjZjeubaubajdj$ubj$)rm}rn(jYUjf}ro(jh]ji]jj]jk]jn]ujZjEjr]rpj)rq}rr(jYXPLL REF CLK (MHz)rsjZjmjbjjdjjf}rt(jh]ji]jj]jk]jn]ujpKmjr]ruj{XPLL REF CLK (MHz)rvrw}rx(jYjsjZjqubaubajdj$ubejdj$ubajdj$ubj$)ry}rz(jYUjf}r{(jh]ji]jj]jk]jn]ujZj1jr]r|(j$)r}}r~(jYUjf}r(jh]ji]jj]jk]jn]ujZjyjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj}jr]rj)r}r(jYX0jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKojr]rj{X0r}r(jYX0jZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj}jr]rj)r}r(jYX0jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKojr]rj{X0r}r(jYX0jZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj}jr]rj)r}r(jYX0jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKojr]rj{X0r}r(jYX0jZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj}jr]rj)r}r(jYXSleep (No boot - debug mode)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKojr]rj{XSleep (No boot - debug mode)rr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjyjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX0jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKqjr]rj{X0r}r(jYX0jZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX0jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKqjr]rj{X0r}r±(jYX0jZjubaubajdj$ubj$)rñ}rı(jYUjf}rű(jh]ji]jj]jk]jn]ujZjjr]rƱj)rDZ}rȱ(jYX1jZjñjbjjdjjf}rɱ(jh]ji]jj]jk]jn]ujpKqjr]rʱj{X1r˱}ṟ(jYX1jZjDZubaubajdj$ubj$)rͱ}rα(jYUjf}rϱ(jh]ji]jj]jk]jn]ujZjjr]rбj)rѱ}rұ(jYX20rӱjZjͱjbjjdjjf}rԱ(jh]ji]jj]jk]jn]ujpKqjr]rձj{X20rֱrױ}rر(jYjӱjZjѱubaubajdj$ubejdj$ubj$)rٱ}rڱ(jYUjf}r۱(jh]ji]jj]jk]jn]ujZjyjr]rܱ(j$)rݱ}rޱ(jYUjf}r߱(jh]ji]jj]jk]jn]ujZjٱjr]rj)r}r(jYX0jZjݱjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKsjr]rj{X0r}r(jYX0jZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjٱjr]rj)r}r(jYX1jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKsjr]rj{X1r}r(jYX1jZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjٱjr]rj)r}r(jYX0jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKsjr]rj{X0r}r(jYX0jZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjٱjr]rj)r}r(jYX24rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKsjr]rj{X24rr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r (jh]ji]jj]jk]jn]ujZjyjr]r (j$)r }r (jYUjf}r (jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX**0**rjZj jbjjdjjf}r(jh]ji]jj]jk]jn]ujpKujr]rj)r}r(jYjjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X0r}r(jYUjZjubajdjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX**1**r jZjjbjjdjjf}r!(jh]ji]jj]jk]jn]ujpKujr]r"j)r#}r$(jYj jf}r%(jh]ji]jj]jk]jn]ujZjjr]r&j{X1r'}r((jYUjZj#ubajdjubaubajdj$ubj$)r)}r*(jYUjf}r+(jh]ji]jj]jk]jn]ujZjjr]r,j)r-}r.(jYX**1**r/jZj)jbjjdjjf}r0(jh]ji]jj]jk]jn]ujpKujr]r1j)r2}r3(jYj/jf}r4(jh]ji]jj]jk]jn]ujZj-jr]r5j{X1r6}r7(jYUjZj2ubajdjubaubajdj$ubj$)r8}r9(jYUjf}r:(jh]ji]jj]jk]jn]ujZjjr]r;j)r<}r=(jYX**25**r>jZj8jbjjdjjf}r?(jh]ji]jj]jk]jn]ujpKujr]r@j)rA}rB(jYj>jf}rC(jh]ji]jj]jk]jn]ujZj<jr]rDj{X25rErF}rG(jYUjZjAubajdjubaubajdj$ubejdj$ubj$)rH}rI(jYUjf}rJ(jh]ji]jj]jk]jn]ujZjyjr]rK(j$)rL}rM(jYUjf}rN(jh]ji]jj]jk]jn]ujZjHjr]rOj)rP}rQ(jYX1jZjLjbjjdjjf}rR(jh]ji]jj]jk]jn]ujpKwjr]rSj{X1rT}rU(jYX1jZjPubaubajdj$ubj$)rV}rW(jYUjf}rX(jh]ji]jj]jk]jn]ujZjHjr]rYj)rZ}r[(jYX0jZjVjbjjdjjf}r\(jh]ji]jj]jk]jn]ujpKwjr]r]j{X0r^}r_(jYX0jZjZubaubajdj$ubj$)r`}ra(jYUjf}rb(jh]ji]jj]jk]jn]ujZjHjr]rcj)rd}re(jYX0jZj`jbjjdjjf}rf(jh]ji]jj]jk]jn]ujpKwjr]rgj{X0rh}ri(jYX0jZjdubaubajdj$ubj$)rj}rk(jYUjf}rl(jh]ji]jj]jk]jn]ujZjHjr]rmj)rn}ro(jYX26rpjZjjjbjjdjjf}rq(jh]ji]jj]jk]jn]ujpKwjr]rrj{X26rsrt}ru(jYjpjZjnubaubajdj$ubejdj$ubj$)rv}rw(jYUjf}rx(jh]ji]jj]jk]jn]ujZjyjr]ry(j$)rz}r{(jYUjf}r|(jh]ji]jj]jk]jn]ujZjvjr]r}j)r~}r(jYX1jZjzjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKyjr]rj{X1r}r(jYX1jZj~ubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjvjr]rj)r}r(jYX0jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKyjr]rj{X0r}r(jYX0jZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjvjr]rj)r}r(jYX1jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKyjr]rj{X1r}r(jYX1jZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjvjr]rj)r}r(jYX27rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKyjr]rj{X27rr}r(jYjjZjubaubajdj$ubejdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjyjr]r(j$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX1jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK{jr]rj{X1r}r(jYX1jZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX1jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK{jr]rj{X1r}r(jYX1jZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj)r}r(jYX0jZjjbjjdjjf}r²(jh]ji]jj]jk]jn]ujpK{jr]ròj{X0rIJ}rŲ(jYX0jZjubaubajdj$ubj$)rƲ}rDz(jYUjf}rȲ(jh]ji]jj]jk]jn]ujZjjr]rɲj)rʲ}r˲(jYXReservedr̲jZjƲjbjjdjjf}rͲ(jh]ji]jj]jk]jn]ujpK{jr]rβj{XReservedrϲrв}rѲ(jYj̲jZjʲubaubajdj$ubejdj$ubj$)rҲ}rӲ(jYUjf}rԲ(jh]ji]jj]jk]jn]ujZjyjr]rղ(j$)rֲ}rײ(jYUjf}rز(jh]ji]jj]jk]jn]ujZjҲjr]rٲj)rڲ}r۲(jYX1jZjֲjbjjdjjf}rܲ(jh]ji]jj]jk]jn]ujpK}jr]rݲj{X1r޲}r߲(jYX1jZjڲubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjҲjr]rj)r}r(jYX1jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK}jr]rj{X1r}r(jYX1jZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjҲjr]rj)r}r(jYX1jZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK}jr]rj{X1r}r(jYX1jZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjҲjr]rj)r}r(jYX-No PLL Configuration Done (slow speed backup)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpK}jr]rj{X-No PLL Configuration Done (slow speed backup)rr}r(jYjjZjubaubajdj$ubejdj$ubejdjy%ubejdjz%ubaubeubeubjL\j[)r}r(jYUjZjN\jbjjdjejf}r(jh]ji]jj]jk]rUpowering-the-evmrajn]rjHaujpKjqhjr]r(jt)r}r(jYXPowering the EVMr jZjjbjjdjxjf}r (jh]ji]jj]jk]jn]ujpKjqhjr]r j{XPowering the EVMr r }r(jYj jZjubaubjd$)r}r(jYUjZjjbjjdjg$jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rjj$)r}r(jYUjf}r(jk]jj]jh]ji]jn]UcolsKujZjjr]r(jo$)r}r(jYUjf}r(jk]jj]jh]ji]jn]UcolwidthK+ujZjjr]jdjs$ubjo$)r}r(jYUjf}r(jk]jj]jh]ji]jn]UcolwidthKujZjjr]jdjs$ubjo$)r}r(jYUjf}r(jk]jj]jh]ji]jn]UcolwidthKujZjjr]jdjs$ubjz$)r }r!(jYUjf}r"(jh]ji]jj]jk]jn]ujZjjr]r#j$)r$}r%(jYUjf}r&(jh]ji]jj]jk]jn]ujZj jr]r'(j$)r(}r)(jYUjf}r*(jh]ji]jj]jk]jn]ujZj$jr]r+j)r,}r-(jYX Connectorr.jZj(jbjjdjjf}r/(jh]ji]jj]jk]jn]ujpKjr]r0j{X Connectorr1r2}r3(jYj.jZj,ubaubajdj$ubj$)r4}r5(jYUjf}r6(jh]ji]jj]jk]jn]ujZj$jr]r7j)r8}r9(jYXSpecificationsr:jZj4jbjjdjjf}r;(jh]ji]jj]jk]jn]ujpKjr]r<j{XSpecificationsr=r>}r?(jYj:jZj8ubaubajdj$ubj$)r@}rA(jYUjf}rB(jh]ji]jj]jk]jn]ujZj$jr]rCj)rD}rE(jYXExamplerFjZj@jbjjdjjf}rG(jh]ji]jj]jk]jn]ujpKjr]rHj{XExamplerIrJ}rK(jYjFjZjDubaubajdj$ubejdj$ubajdj$ubj$)rL}rM(jYUjf}rN(jh]ji]jj]jk]jn]ujZjjr]rO(j$)rP}rQ(jYUjf}rR(jh]ji]jj]jk]jn]ujZjLjr]rS(j$)rT}rU(jYUjf}rV(jh]ji]jj]jk]jn]ujZjPjr]rWj)rX}rY(jYXPower DIN, 4-pinrZjZjTjbjjdjjf}r[(jh]ji]jj]jk]jn]ujpKjr]r\j{XPower DIN, 4-pinr]r^}r_(jYjZjZjXubaubajdj$ubj$)r`}ra(jYUjf}rb(jh]ji]jj]jk]jn]ujZjPjr]rcj)rd}re(jYX24VDC, 5A Output (Max)rfjZj`jbjjdjjf}rg(jh]ji]jj]jk]jn]ujpKjr]rhj{X24VDC, 5A Output (Max)rirj}rk(jYjfjZjdubaubajdj$ubj$)rl}rm(jYUjf}rn(jh]ji]jj]jk]jn]ujZjPjr]roj)rp}rq(jYXCUI Inc.SDI120-24-U-P51rrjZjljbjjdjjf}rs(jh]ji]jj]jk]jn]ujpKjr]rtj{XCUI Inc.SDI120-24-U-P51rurv}rw(jYjrjZjpubaubajdj$ubejdj$ubj$)rx}ry(jYUjf}rz(jh]ji]jj]jk]jn]ujZjLjr]r{(j$)r|}r}(jYUjf}r~(jh]ji]jj]jk]jn]ujZjxjr]rj)r}r(jYX)Barrel Plug, 2.5mm I.D x 5.5mm O.D x 9.55rjZj|jbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X)Barrel Plug, 2.5mm I.D x 5.5mm O.D x 9.55rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjxjr]rj)r}r(jYX-12-24VDC, positive center, 2.71A Output (Max)rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X-12-24VDC, positive center, 2.71A Output (Max)rr}r(jYjjZjubaubajdj$ubj$)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjxjr]rj)r}r(jYXCUI Inc. SDI65-24UD-P6rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XCUI Inc. SDI65-24UD-P6rr}r(jYjjZjubaubajdj$ubejdj$ubejdjy%ubejdjz%ubaubj)r}r(jYX{The DIN connector power supply is recommended to provide enough power for applications that make use of the PCIe interface.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X{The DIN connector power supply is recommended to provide enough power for applications that make use of the PCIe interface.rr}r(jYjjZjubaubaubeubeubjbjjdjejf}r(jh]rjaji]jj]jk]rUuart-connectionrajn]ujpKjqhjr]r(jt)r}r(jYXUART ConnectionrjZjL\jbjjdjxjf}r(jh]ji]jj]jk]jn]ujpKjqhjr]rj{XUART Connectionrr}r(jYjjZjubaubj%)r}r(jYUjZjL\jbjjdj(jf}r(j*U.jk]jj]jh]j+Uji]jn]j,j-ujpKjqhjr]r(j/)r}r(jYXJConnect a micro USB cable between UART port (J42) of the EVM and host PC. jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r³(jYXIConnect a micro USB cable between UART port (J42) of the EVM and host PC.rójZjjbjjdjjf}rij(jh]ji]jj]jk]jn]ujpKjr]rųj{XIConnect a micro USB cable between UART port (J42) of the EVM and host PC.rƳrdz}rȳ(jYjójZjubaubaubj/)rɳ}rʳ(jYXOpen a serial console (e.g. Tera Term) on host PC, connect to COM port on which SOC UART0 port is connected. Four COM ports should appear in the serial console application. Connect to the first COM port in the list. jZjjbjjdj2jf}r˳(jh]ji]jj]jk]jn]ujpNjqhjr]r̳j)rͳ}rγ(jYXOpen a serial console (e.g. Tera Term) on host PC, connect to COM port on which SOC UART0 port is connected. Four COM ports should appear in the serial console application. Connect to the first COM port in the list.rϳjZjɳjbjjdjjf}rг(jh]ji]jj]jk]jn]ujpKjr]rѳj{XOpen a serial console (e.g. Tera Term) on host PC, connect to COM port on which SOC UART0 port is connected. Four COM ports should appear in the serial console application. Connect to the first COM port in the list.rҳrӳ}rԳ(jYjϳjZjͳubaubaubeubj=)rճ}rֳ(jYUjZjL\jbNjdj@jf}r׳(jh]ji]jj]jk]jn]ujpNjqhjr]rسjC)rٳ}rڳ(jYUjf}r۳(jGX*jk]jj]jh]ji]jn]ujZjճjr]rܳ(j/)rݳ}r޳(jYX!First COM port – SoC MAIN UART0r߳jf}r(jh]ji]jj]jk]jn]ujZjٳjr]rj)r}r(jYj߳jZjݳjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{X!First COM port – SoC MAIN UART0rr}r(jYj߳jZjubaubajdj2ubj/)r}r(jYXSecond COM port – MCU UARTrjf}r(jh]ji]jj]jk]jn]ujZjٳjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XSecond COM port – MCU UARTrr}r(jYjjZjubaubajdj2ubj/)r}r(jYXThird COM port – Wakeup UARTrjf}r(jh]ji]jj]jk]jn]ujZjٳjr]rj)r}r(jYjjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XThird COM port – Wakeup UARTrr}r(jYjjZjubaubajdj2ubj/)r}r(jYX#Fourth COM port – SoC MAIN UART1 jf}r(jh]ji]jj]jk]jn]ujZjٳjr]rj)r}r(jYX"Fourth COM port – SoC MAIN UART1rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]r j{X"Fourth COM port – SoC MAIN UART1r r }r (jYjjZjubaubajdj2ubejdj`ubaubjB)r }r(jYXJ.. image:: ../../../images/TMDX654_EVM_Hardware_Setup/AM65x_Tera_Term.png jZjL\jbjjdjEjf}r(UuriXCrtos/../../../images/TMDX654_EVM_Hardware_Setup/AM65x_Tera_Term.pngrjk]jj]jh]ji]jH}rU*jsjn]ujpKjqhjr]ubj%)r}r(jYUjZjL\jbjjdj(jf}r(j*U.jdKjk]jj]jh]j+Uji]jn]j,j-ujpKjqhjr]rj/)r}r(jYXOpen a serial console (e.g Tera Term) on host PC, connect to COM port on which EVM UART port is connected and set the following configuration. jZjjbjjdj2jf}r(jh]ji]jj]jk]jn]ujpNjqhjr]rj)r}r(jYXOpen a serial console (e.g Tera Term) on host PC, connect to COM port on which EVM UART port is connected and set the following configuration.rjZjjbjjdjjf}r(jh]ji]jj]jk]jn]ujpKjr]rj{XOpen a serial console (e.g Tera Term) on host PC, connect to COM port on which EVM UART port is connected and set the following configuration.rr }r!(jYjjZjubaubaubaubj=)r"}r#(jYUjZjL\jbNjdj@jf}r$(jh]ji]jj]jk]jn]ujpNjqhjr]r%jC)r&}r'(jYUjf}r((jGX*jk]jj]jh]ji]jn]ujZj"jr]r)(j/)r*}r+(jYXBaud rate - 115200r,jf}r-(jh]ji]jj]jk]jn]ujZj&jr]r.j)r/}r0(jYj,jZj*jbjjdjjf}r1(jh]ji]jj]jk]jn]ujpKjr]r2j{XBaud rate - 115200r3r4}r5(jYj,jZj/ubaubajdj2ubj/)r6}r7(jYXData length - 8 bitr8jf}r9(jh]ji]jj]jk]jn]ujZj&jr]r:j)r;}r<(jYj8jZj6jbjjdjjf}r=(jh]ji]jj]jk]jn]ujpKjr]r>j{XData length - 8 bitr?r@}rA(jYj8jZj;ubaubajdj2ubj/)rB}rC(jYX Parity - NonerDjf}rE(jh]ji]jj]jk]jn]ujZj&jr]rFj)rG}rH(jYjDjZjBjbjjdjjf}rI(jh]ji]jj]jk]jn]ujpKjr]rJj{X Parity - NonerKrL}rM(jYjDjZjGubaubajdj2ubj/)rN}rO(jYX Stop bits - 1rPjf}rQ(jh]ji]jj]jk]jn]ujZj&jr]rRj)rS}rT(jYjPjZjNjbjjdjjf}rU(jh]ji]jj]jk]jn]ujpKjr]rVj{X Stop bits - 1rWrX}rY(jYjPjZjSubaubajdj2ubj/)rZ}r[(jYXFlow control - None jf}r\(jh]ji]jj]jk]jn]ujZj&jr]r]j)r^}r_(jYXFlow control - Noner`jZjZjbjjdjjf}ra(jh]ji]jj]jk]jn]ujpKjr]rbj{XFlow control - Nonercrd}re(jYj`jZj^ubaubajdj2ubejdj`ubaubeubjbjjdj jf}rf(jh]UlevelKjk]jj]Usourcejcji]jn]UlineKbUtypej ujpKjqhjr]rgj)rh}ri(jYX:Enumerated list start value not ordinal-1: "3" (ordinal 3)jf}rj(jh]ji]jj]jk]jn]ujZjJ\jr]rkj{X:Enumerated list start value not ordinal-1: "3" (ordinal 3)rlrm}rn(jYUjZjhubajdjubaubjV)ro}rp(jYUjZjjbjjdj jf}rq(jh]UlevelKjk]jj]Usourcejcji]jn]UlineKbUtypej ujpKjqhjr]rrj)rs}rt(jYX:Enumerated list start value not ordinal-1: "4" (ordinal 4)jf}ru(jh]ji]jj]jk]jn]ujZjojr]rvj{X:Enumerated list start value not ordinal-1: "4" (ordinal 4)rwrx}ry(jYUjZjsubajdjubaubjV)rz}r{(jYUjZjjbjjdj jf}r|(jh]UlevelKjk]jj]Usourcejcji]jn]UlineKbUtypej ujpMjqhjr]r}j)r~}r(jYX:Enumerated list start value not ordinal-1: "5" (ordinal 5)jf}r(jh]ji]jj]jk]jn]ujZjzjr]rj{X:Enumerated list start value not ordinal-1: "5" (ordinal 5)rr}r(jYUjZj~ubajdjubaubjV)r}r(jYUjZjjbjjdj jf}r(jh]UlevelKjk]jj]Usourcejcji]jn]UlineKbUtypej ujpMjqhjr]rj)r}r(jYX:Enumerated list start value not ordinal-1: "6" (ordinal 6)jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X:Enumerated list start value not ordinal-1: "6" (ordinal 6)rr}r(jYUjZjubajdjubaubjV)r}r(jYUjZjjbjjdj jf}r(jh]UlevelKjk]jj]Usourcejcji]jn]UlineKbUtypej ujpMjqhjr]rj)r}r(jYX:Enumerated list start value not ordinal-1: "2" (ordinal 2)jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X:Enumerated list start value not ordinal-1: "2" (ordinal 2)rr}r(jYUjZjubajdjubaubjV)r}r(jYUjZjjbjjdj jf}r(jh]UlevelKjk]jj]Usourcejcji]jn]UlineKbUtypej ujpMjqhjr]rj)r}r(jYX:Enumerated list start value not ordinal-1: "4" (ordinal 4)jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X:Enumerated list start value not ordinal-1: "4" (ordinal 4)rr}r(jYUjZjubajdjubaubjV)r}r(jYUjZjjbjjdj jf}r(jh]UlevelKjk]jj]Usourcejcji]jn]UlineKbUtypej ujpMGjqhjr]rj)r}r(jYX:Enumerated list start value not ordinal-1: "2" (ordinal 2)jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X:Enumerated list start value not ordinal-1: "2" (ordinal 2)rr}r(jYUjZjubajdjubaubjV)r}r(jYUjf}r(jh]UlevelKjk]jj]rj>caUsourcejcji]jn]UlineKbUtypej ujZj9cjr]rj)r}r(jYX.Duplicate explicit target name: "description".jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X.Duplicate explicit target name: "description".rr}r(jYUjZjubajdjubajdj ubjV)r}r(jYUjf}r(jh]UlevelKjk]jj]rjQcaUsourcejcji]jn]UlineKbUtypej ujZjLcjr]rj)r´}rô(jYX@Duplicate explicit target name: "evm-layout-and-key-components".jf}rĴ(jh]ji]jj]jk]jn]ujZjjr]rŴj{X@Duplicate explicit target name: "evm-layout-and-key-components".rƴrǴ}rȴ(jYUjZj´ubajdjubajdj ubjV)rɴ}rʴ(jYUjf}r˴(jh]UlevelKjk]jj]r̴jfaUsourcejcji]jn]UlineKbUtypej ujZjfjr]rʹj)rδ}rϴ(jYX.Duplicate explicit target name: "description".jf}rд(jh]ji]jj]jk]jn]ujZjɴjr]rѴj{X.Duplicate explicit target name: "description".rҴrӴ}rԴ(jYUjZjδubajdjubajdj ubjV)rմ}rִ(jYUjf}r״(jh]UlevelKjk]jj]rشjhaUsourcejcji]jn]UlineKbUtypej ujZjgjr]rٴj)rڴ}r۴(jYX@Duplicate explicit target name: "evm-layout-and-key-components".jf}rܴ(jh]ji]jj]jk]jn]ujZjմjr]rݴj{X@Duplicate explicit target name: "evm-layout-and-key-components".r޴rߴ}r(jYUjZjڴubajdjubajdj ubjV)r}r(jYUjf}r(jh]UlevelKjk]jj]rjhaUsourcejcji]jn]UlineKbUtypej ujZjhjr]rj)r}r(jYXLDuplicate explicit target name: "jtag-debug-probes-aka-emulators-supported".jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XLDuplicate explicit target name: "jtag-debug-probes-aka-emulators-supported".rr}r(jYUjZjubajdjubajdj ubjV)r}r(jYUjf}r(jh]UlevelKjk]jj]rjVhaUsourcejcji]jn]UlineKbUtypej ujZjQhjr]rj)r}r(jYX4Duplicate explicit target name: "minimal-evm-setup".jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X4Duplicate explicit target name: "minimal-evm-setup".rr}r(jYUjZjubajdjubajdj ubjV)r}r(jYUjf}r(jh]UlevelKjk]jj]rjfhaUsourcejcji]jn]UlineKbUtypej ujZj`hjr]rj)r}r(jYX8Duplicate explicit target name: "setting-boot-switches".jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X8Duplicate explicit target name: "setting-boot-switches".rr}r(jYUjZjubajdjubajdj ubjV)r}r(jYUjf}r(jh]UlevelKjk]jj]rjjaUsourcejcji]jn]UlineKbUtypej ujZjjjr]r j)r }r (jYX6Duplicate explicit target name: "connecting-emulator".jf}r (jh]ji]jj]jk]jn]ujZjjr]r j{X6Duplicate explicit target name: "connecting-emulator".rr}r(jYUjZj ubajdjubajdj ubjV)r}r(jYUjf}r(jh]UlevelKjk]jj]rjkaUsourcejcji]jn]UlineKbUtypej ujZjkjr]rj)r}r(jYX6Duplicate explicit target name: "powering-up-the-evm".jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X6Duplicate explicit target name: "powering-up-the-evm".rr}r(jYUjZjubajdjubajdj ubjV)r}r(jYUjf}r(jh]UlevelKjk]jj]r jkaUsourcejcji]jn]UlineKbUtypej ujZjkjr]r!j)r"}r#(jYX>Duplicate explicit target name: "power-supply-specifications".jf}r$(jh]ji]jj]jk]jn]ujZjjr]r%j{X>Duplicate explicit target name: "power-supply-specifications".r&r'}r((jYUjZj"ubajdjubajdj ubjV)r)}r*(jYUjf}r+(jh]UlevelKjk]jj]r,jkaUsourcejcji]jn]UlineKbUtypej ujZjkjr]r-j)r.}r/(jYX,Duplicate explicit target name: "ccs-setup".jf}r0(jh]ji]jj]jk]jn]ujZj)jr]r1j{X,Duplicate explicit target name: "ccs-setup".r2r3}r4(jYUjZj.ubajdjubajdj ubjV)r5}r6(jYUjf}r7(jh]UlevelKjk]jj]r8jmaUsourcejcji]jn]UlineKbUtypej ujZjmjr]r9j)r:}r;(jYXGDuplicate explicit target name: "connect-without-a-sd-card-boot-image".jf}r<(jh]ji]jj]jk]jn]ujZj5jr]r=j{XGDuplicate explicit target name: "connect-without-a-sd-card-boot-image".r>r?}r@(jYUjZj:ubajdjubajdj ubjV)rA}rB(jYUjf}rC(jh]UlevelKjk]jj]rDjmaUsourcejcji]jn]UlineKbUtypej ujZjmjr]rEj)rF}rG(jYXIDuplicate explicit target name: "configuring-target-configuration-files".jf}rH(jh]ji]jj]jk]jn]ujZjAjr]rIj{XIDuplicate explicit target name: "configuring-target-configuration-files".rJrK}rL(jYUjZjFubajdjubajdj ubjV)rM}rN(jYUjf}rO(jh]UlevelKjk]jj]rPjmmaUsourcejcji]jn]UlineKbUtypej ujZjhmjr]rQj)rR}rS(jYX7Duplicate explicit target name: "connecting-to-target".jf}rT(jh]ji]jj]jk]jn]ujZjMjr]rUj{X7Duplicate explicit target name: "connecting-to-target".rVrW}rX(jYUjZjRubajdjubajdj ubjV)rY}rZ(jYUjZjqjbjqjdj jf}r[(jh]UlevelKjk]jj]r\jqaUsourcejqji]jn]UlineKUtypej ujpKjqhjr]r]j)r^}r_(jYX.Duplicate implicit target name: "description".jf}r`(jh]ji]jj]jk]jn]ujZjYjr]raj{X.Duplicate implicit target name: "description".rbrc}rd(jYUjZj^ubajdjubaubjV)re}rf(jYUjZjrjbjqjdj jf}rg(jh]UlevelKjk]jj]rhjraUsourcejqji]jn]UlineK0Utypej ujpK0jqhjr]rij)rj}rk(jYX@Duplicate implicit target name: "evm layout and key components".jf}rl(jh]ji]jj]jk]jn]ujZjejr]rmj{X@Duplicate implicit target name: "evm layout and key components".rnro}rp(jYUjZjjubajdjubaubjV)rq}rr(jYUjZj sjbjqjdj jf}rs(jh]UlevelKjk]jj]rtjsaUsourcejqji]jn]UlineK9Utypej ujpK9jqhjr]ruj)rv}rw(jYXJDuplicate implicit target name: "supported jtag debug probes (emulators)".jf}rx(jh]ji]jj]jk]jn]ujZjqjr]ryj{XJDuplicate implicit target name: "supported jtag debug probes (emulators)".rzr{}r|(jYUjZjvubajdjubaubjV)r}}r~(jYUjf}r(jh]UlevelKjk]jj]rj taUsourcejcji]jn]UlineKbUtypej ujZjtjr]rj)r}r(jYX>Duplicate explicit target name: "power-supply-specifications".jf}r(jh]ji]jj]jk]jn]ujZj}jr]rj{X>Duplicate explicit target name: "power-supply-specifications".rr}r(jYUjZjubajdjubajdj ubjV)r}r(jYUjf}r(jh]UlevelKjk]jj]rjuaUsourcejcji]jn]UlineKbUtypej ujZj ujr]rj)r}r(jYXIDuplicate explicit target name: "configuring-target-configuration-files".jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XIDuplicate explicit target name: "configuring-target-configuration-files".rr}r(jYUjZjubajdjubajdj ubjV)r}r(jYUjf}r(jh]UlevelKjk]jj]rjfuaUsourcejcji]jn]UlineKbUtypej ujZjaujr]rj)r}r(jYX7Duplicate explicit target name: "connecting-to-target".jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X7Duplicate explicit target name: "connecting-to-target".rr}r(jYUjZjubajdjubajdj ubjV)r}r(jYUjZj>~jbj/~jdj jf}r(jh]UlevelKjk]jj]rjC~aUsourcej/~ji]jn]UlineKUtypej ujpKjqhjr]rj)r}r(jYX1Duplicate implicit target name: "hardware setup".jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X1Duplicate implicit target name: "hardware setup".rr}r(jYUjZjubajdjubaubjV)r}r(jYUjZj~jbj/~jdj jf}r(jh]UlevelKjk]jj]rj~aUsourcej/~ji]jn]UlineKUtypej ujpKjqhjr]rj)r}r(jYX?Duplicate implicit target name: "bmc version check and update".jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X?Duplicate implicit target name: "bmc version check and update".rr}r(jYUjZjubajdjubaubjV)r}r(jYUjZj)jbj/~jdj jf}r(jh]UlevelKjk]jj]rj.aUsourcej/~ji]jn]UlineK@Utypej ujpK@jqhjr]rj)r}r(jYX<Duplicate implicit target name: "attach the ethernet cable".jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X<Duplicate implicit target name: "attach the ethernet cable".rµrõ}rĵ(jYUjZjubajdjubaubjV)rŵ}rƵ(jYUjZjMjbj/~jdj jf}rǵ(jh]UlevelKjk]jj]rȵjRaUsourcej/~ji]jn]UlineKKUtypej ujpKKjqhjr]rɵj)rʵ}r˵(jYX=Duplicate implicit target name: "connect the jtag interface".jf}r̵(jh]ji]jj]jk]jn]ujZjŵjr]r͵j{X=Duplicate implicit target name: "connect the jtag interface".rεrϵ}rе(jYUjZjʵubajdjubaubjV)rѵ}rҵ(jYUjZjCjbj/~jdj jf}rӵ(jh]UlevelKjk]jj]rԵjHaUsourcej/~ji]jn]UlineKUtypej ujpKjqhjr]rյj)rֵ}r׵(jYXTDuplicate implicit target name: "attach the serial port cable to the soc uart port".jf}rص(jh]ji]jj]jk]jn]ujZjѵjr]rٵj{XTDuplicate implicit target name: "attach the serial port cable to the soc uart port".rڵr۵}rܵ(jYUjZjֵubajdjubaubjV)rݵ}r޵(jYUjZjbjbj/~jdj jf}rߵ(jh]UlevelKjk]jj]rjgaUsourcej/~ji]jn]UlineKUtypej ujpKjqhjr]rj)r}r(jYX:Duplicate implicit target name: "connect the power cable".jf}r(jh]ji]jj]jk]jn]ujZjݵjr]rj{X:Duplicate implicit target name: "connect the power cable".rr}r(jYUjZjubajdjubaubjV)r}r(jYUjZjjbj/~jdj jf}r(jh]UlevelKjk]jj]rjaUsourcej/~ji]jn]UlineMUtypej ujpMjqhjr]rj)r}r(jYXIDuplicate implicit target name: "dip switch and bootmode configurations".jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XIDuplicate implicit target name: "dip switch and bootmode configurations".rr}r(jYUjZjubajdjubaubjV)r}r(jYUjZjjbj/~jdj jf}r(jh]UlevelKjk]jj]Usourcej/~ji]jn]UlineMUtypej ujpMjqhjr]rj)r}r(jYX?Explicit markup ends without a blank line; unexpected unindent.jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X?Explicit markup ends without a blank line; unexpected unindent.rr}r(jYUjZjubajdjubaubjV)r}r(jYUjZjjbj/~jdj jf}r(jh]UlevelKjk]jj]Usourcej/~ji]jn]UlineMUtypej ujpMjqhjr]rj)r}r(jYX?Explicit markup ends without a blank line; unexpected unindent.jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X?Explicit markup ends without a blank line; unexpected unindent.rr }r (jYUjZjubajdjubaubjV)r }r (jYUjZjejbj0jdj jf}r (jh]UlevelKjk]jj]rjjaUsourcej0ji]jn]UlineK Utypej ujpK jqhjr]rj)r}r(jYX:Duplicate implicit target name: "hardware setup overview".jf}r(jh]ji]jj]jk]jn]ujZj jr]rj{X:Duplicate implicit target name: "hardware setup overview".rr}r(jYUjZjubajdjubaubjV)r}r(jYUjZjjbj0jdj jf}r(jh]UlevelKjk]jj]rjaUsourcej0ji]jn]UlineKUtypej ujpKjqhjr]rj)r}r(jYX7Duplicate implicit target name: "hardware setup steps".jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{X7Duplicate implicit target name: "hardware setup steps".r r!}r"(jYUjZjubajdjubaubjV)r#}r$(jYUjZjjbj0jdj jf}r%(jh]UlevelKjk]jj]r&jaUsourcej0ji]jn]UlineKGUtypej ujpKGjqhjr]r'j)r(}r)(jYX@Duplicate implicit target name: "boot mode dip switch settings".jf}r*(jh]ji]jj]jk]jn]ujZj#jr]r+j{X@Duplicate implicit target name: "boot mode dip switch settings".r,r-}r.(jYUjZj(ubajdjubaubjV)r/}r0(jYUjZjjbjjdj jf}r1(jh]UlevelKjk]jj]r2jaUsourcejji]jn]UlineK Utypej ujpK jqhjr]r3j)r4}r5(jYX:Duplicate implicit target name: "hardware setup overview".jf}r6(jh]ji]jj]jk]jn]ujZj/jr]r7j{X:Duplicate implicit target name: "hardware setup overview".r8r9}r:(jYUjZj4ubajdjubaubjV)r;}r<(jYUjZj'jbjjdj jf}r=(jh]UlevelKjk]jj]r>j-aUsourcejji]jn]UlineKUtypej ujpKjqhjr]r?j)r@}rA(jYX7Duplicate implicit target name: "hardware setup steps".jf}rB(jh]ji]jj]jk]jn]ujZj;jr]rCj{X7Duplicate implicit target name: "hardware setup steps".rDrE}rF(jYUjZj@ubajdjubaubjV)rG}rH(jYUjZjUjbjjdj jf}rI(jh]UlevelKjk]jj]rJj[aUsourcejji]jn]UlineKmUtypej ujpKmjqhjr]rKj)rL}rM(jYX@Duplicate implicit target name: "boot mode dip switch settings".jf}rN(jh]ji]jj]jk]jn]ujZjGjr]rOj{X@Duplicate implicit target name: "boot mode dip switch settings".rPrQ}rR(jYUjZjLubajdjubaubjV)rS}rT(jYUjZj_jbjPjdj jf}rU(jh]UlevelKjk]jj]rVjeaUsourcejPji]jn]UlineKUtypej ujpKjqhjr]rWj)rX}rY(jYX+Duplicate implicit target name: "overview".jf}rZ(jh]ji]jj]jk]jn]ujZjSjr]r[j{X+Duplicate implicit target name: "overview".r\r]}r^(jYUjZjXubajdjubaubjV)r_}r`(jYUjZjwjbjPjdj jf}ra(jh]UlevelKjk]jj]rbj|aUsourcejPji]jn]UlineK Utypej ujpK jqhjr]rcj)rd}re(jYX+Duplicate implicit target name: "hardware".jf}rf(jh]ji]jj]jk]jn]ujZj_jr]rgj{X+Duplicate implicit target name: "hardware".rhri}rj(jYUjZjdubajdjubaubjV)rk}rl(jYUjZjjbjPjdj jf}rm(jh]UlevelKjk]jj]rnjaUsourcejPji]jn]UlineKUtypej ujpKjqhjr]roj)rp}rq(jYX2Duplicate implicit target name: "uart connection".jf}rr(jh]ji]jj]jk]jn]ujZjkjr]rsj{X2Duplicate implicit target name: "uart connection".rtru}rv(jYUjZjpubajdjubaubjV)rw}rx(jYUjZjGjbjPjdj jf}ry(jh]UlevelKjk]jj]rzjMaUsourcejPji]jn]UlineK,Utypej ujpK,jqhjr]r{j)r|}r}(jYX1Duplicate implicit target name: "hardware setup".jf}r~(jh]ji]jj]jk]jn]ujZjwjr]rj{X1Duplicate implicit target name: "hardware setup".rr}r(jYUjZj|ubajdjubaubjV)r}r(jYUjZjŞjbjPjdj jf}r(jh]UlevelKjk]jj]UsourcejPji]jn]UlineKrUtypej ujpKrjqhjr]rj)r}r(jYXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rr}r(jYUjZjubajdjubaubjV)r}r(jYUjZjŞjbjPjdj jf}r(jh]UlevelKjk]jj]UsourcejPji]jn]UlineKUtypej ujpKjqhjr]rj)r}r(jYXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rr}r(jYUjZjubajdjubaubjV)r}r(jYUjf}r(jh]UlevelKjk]jj]Usourcejji]jn]UlineKUtypej ujr]r(j)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XTitle underline too short.rr}r(jYUjZjubajdjubj)r}r(jYXOOMAP-L137/C6747 EVM Hardware Setup Guide ======================================jf}r(jjjk]jj]jh]ji]jn]ujZjjr]rj{XOOMAP-L137/C6747 EVM Hardware Setup Guide ======================================rr}r(jYUjZjubajdjubejdj ubjV)r}r(jYUjZjjbjjdj jf}r(jh]UlevelKjk]jj]Usourcejji]jn]UlineKUtypej ujpKjqhjr]r(j)r}r(jYXTitle underline too short.jf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XTitle underline too short.rr}r(jYUjZjubajdjubj)r}r(jYXOOMAP-L137/C6747 EVM Hardware Setup Guide ======================================jf}r(jjjk]jj]jh]ji]jn]ujZjjr]rj{XOOMAP-L137/C6747 EVM Hardware Setup Guide ======================================rr}r(jYUjZjubajdjubeubjV)r}r(jYUjZj٠jbjjdj jf}r(jh]UlevelKjk]jj]Usourcejcji]jn]UlineKbUtypej ujpK`__. | +--------------------------------+--------------------------------------------------------------------------------------------------+jf}r5(jjjk]jj]jh]ji]jn]ujZj(jr]r6j{X+--------------------------------+--------------------------------------------------------------------------------------------------+ | .. Image:: ../../images/E2e.jpg | For technical support please post your questions at `http://e2e.ti.com `__. | +--------------------------------+--------------------------------------------------------------------------------------------------+r7r8}r9(jYUjZj3ubajdjubeubeUcurrent_sourcer:NU decorationr;NUautofootnote_startr<KUnameidsr=}r>(hj'hjbhjh jh j,>h j7h Nh jbhjoEhj`hjNhjU>hjOhjEhjhjthjFhj hj:hjuhjUhj%hjGlhjefhjhj!h jxh!jh"jNh#Nh$j[!h%jlh&jh'jXh(jh)jh*jQDh+Nh,jh-j h.jh/j?h0j?h1j#Jh2jJh3j{h4Nh5jsh6jxh7jh8jh9jh:jlKh;jbhj^h?j}+h@jMhAj/hBjO$hCjhDjhENhFjhGj@hHjOhIjFhJjqchKj%hLjEhMjHhNjW=hOjhPjshQj(hRjMhSjhTjHhUjuhVj>hWjdhXjMhYjNThZj%h[j\h\jMh]jjh^Nh_j5}h`jhaj,hbjQ2hcNhdjhej>Lhfj<hgjT7hhNhij.chjjMhkj\hljݠhmj hnjhojthpjkhqjNUhrjhsj4htjhujhvjhwjVphxjhyjآhzj=!h{jh|jh}j^Nh~NhjnhjɞhjDhjEhjxOhjphj!hj\hjhjhNhjBhjhjhjhj67hjfhjՄhj4hj@hjhjRMhj-hjhNhNhNhj&hjThj^hjvDhj&Jhj@hj}hj"hj*hjmhj}hjNhjhjhjlhj]~hNhj]hjhjrJhj hj^ahNhj*hjhj hj1hjvhjrThj_hjգhj{hjhj[Ihj8hj4Fhj("hje)hjNhNhjhj?OhjJhj8hNhj!hj#hj}hjThj~hNhNhjBwhj1hjhjhNhjDhNhj>hj{hj,qhjhjvhjThj hjhjOhjhj&$hj*hj!hjhj-hjhjhjW8hjhjShj~ahj|hj/IhjhjBhjhjBEhjvthjhNhj0hjhj>hj;vhNhNhjxhjhj6$hj7hjhjV\hj qjjjjDjjk2jj#2jj{AjjGjj"jjTjNj j$j j!j jzj jmj j*TjjjNjjjj1jjpjjjNjj[jjjj@jj_hjjajjv\jjjj jNjj>Njjj jlej!Nj"j0j#jnj$j"Nj%jmj&j58j'Nj(jXsj)jqj*jhj+Nj,jEj-j3~j.jr+j/jNj0jaj1jv>j2jDj3jEj4jj5j"j6j>j7jEoj8j6nj9jj:jbj;j˧j<jpj=jPj>j!j?jj@jwjAjKIjBj jCj=#jDjojEjn?jFj>jGNjHjjIj>jJj jKj&jLjOjMNjNjӤjOjwjPjSjQjIsujr]r?(j`jjR\ejYUU transformerr@NU footnote_refsrA}rBUrefnamesrC}rD(Xconnectingemulator]rE(jmjneX crash dump]rF(jOFjHeXbootmodeconfiguration]rGjaXsettingbootswitches]rH(jmjzneX#debugging mmu faults and exceptions]rI(j?j@eX,linux and android - disabling error recovery]rJjHaX2advanced am65x debug setup with dmsc firmware load]rKjaXnobootlittleendianrL]rMj)rN}rO(jYjjf}rP(UnameXNoBootLittleEndianjk]jj]jh]UrefnamerQjLji]jn]ujZjjr]rRj{XNoBootLittleEndianrSrT}rU(jYUjZjNubajdjubaX(linux and android – disabling watchdog]rV(jDjHeX&linux and android - remote core traces]rWj"AaX dip switchesrX]rYj)rZ}r[(jYjijf}r\(UnameX DIP Switchesjk]jj]jh]jQjXji]jn]ujZj`jr]r]j{X DIP Switchesr^r_}r`(jYUjZjZubajdjubaX5linux and android - disabling remoteproc auto-suspend]rajHaXconfiguringtargetconfigfile]rb(jmjneXlinux and android - remoteproc]rc(j@jEeuUsymbol_footnotesrd]reUautofootnote_refsrf]rgUsymbol_footnote_refsrh]riU citationsrj]rkjqhU current_linerlNUtransform_messagesrm]rn(jV)ro}rp(jYUjf}rq(jh]UlevelKjk]rrjajj]rsjaUsourcej/~ji]jn]UlineKUtypej ujr]rtj)ru}rv(jYUjf}rw(jh]ji]jj]jk]jn]ujZjojr]rxj{X*Unknown target name: "nobootlittleendian".ryrz}r{(jYUjZjuubajdjubajdj ubjV)r|}r}(jYUjf}r~(jh]UlevelKjk]rjmajj]rjlaUsourcejPji]jn]UlineK.Utypej ujr]rj)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZj|jr]rj{X$Unknown target name: "dip switches".rr}r(jYUjZjubajdjubajdj ubjV)r}r(jYUjf}r(jh]UlevelKjk]jj]Usourcejji]jn]UlineMUtypej ujr]rj)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XCHyperlink target "run-apps-from-ddr-on-r5-cores" is not referenced.rr}r(jYUjZjubajdjubajdj ubjV)r}r(jYUjf}r(jh]UlevelKjk]jj]Usourcejji]jn]UlineMUtypej ujr]rj)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XAHyperlink target "run-bios-app-from-ddr-on-r5" is not referenced.rr}r(jYUjZjubajdjubajdj ubjV)r}r(jYUjf}r(jh]UlevelKjk]jj]Usourcejji]jn]UlineMUtypej ujr]rj)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XFHyperlink target "run-baremetal-app-from-ddr-on-r5" is not referenced.rr}r(jYUjZjubajdjubajdj ubjV)r}r(jYUjf}r(jh]UlevelKjk]jj]Usourcejcji]jn]UlineM=Utypej ujr]rj)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XHHyperlink target "processor-sdk-rtos-setup-ccs-label" is not referenced.rr}r(jYUjZjubajdjubajdj ubjV)r}r(jYUjf}r(jh]UlevelKjk]jj]Usourcejcji]jn]UlineMUtypej ujr]rj)r}r(jYUjf}r(jh]ji]jj]jk]jn]ujZjjr]rj{XUHyperlink target "processor-sdk-rtos-install-in-custom-path-label" is not referenced.rr}r(jYUjZjubajdjubajdj ubeUreporterrNUid_startrK[U autofootnotesr·]r÷U citation_refsrķ}rŷUindirect_targetsrƷ]rǷUsettingsrȷ(cdocutils.frontend Values rɷorʷ}r˷(Ufootnote_backlinksr̷KUrecord_dependenciesrͷNU rfc_base_urlrηUhttps://tools.ietf.org/html/rϷU tracebackrзUpep_referencesrѷNUstrip_commentsrҷNU toc_backlinksrӷj$U language_coderԷUenrշU datestamprַNU report_levelr׷KU _destinationrطNU halt_levelrٷKU strip_classesrڷNjxNUerror_encoding_error_handlerr۷UbackslashreplacerܷUdebugrݷNUembed_stylesheetr޷Uoutput_encoding_error_handlerr߷UstrictrU sectnum_xformrKUdump_transformsrNU docinfo_xformrKUwarning_streamrNUpep_file_url_templaterUpep-%04drUexit_status_levelrKUconfigrNUstrict_visitorrNUcloak_email_addressesrUtrim_footnote_reference_spacerUenvrNUdump_pseudo_xmlrNUexpose_internalsrNUsectsubtitle_xformrU source_linkrNUrfc_referencesrNUoutput_encodingrUutf-8rU source_urlrNUinput_encodingrU utf-8-sigrU_disable_configrNU id_prefixrUU tab_widthrKUerror_encodingrUUTF-8rU_sourcerjcUgettext_compactrU generatorrNUdump_internalsrNU smart_quotesrU pep_base_urlrU https://www.python.org/dev/peps/rUsyntax_highlightrUlongrUinput_encoding_error_handlerrjUauto_id_prefixrUidrUdoctitle_xformrUstrip_elements_with_classesr NU _config_filesr ]Ufile_insertion_enabledr U raw_enabledr KU dump_settingsr NubUsymbol_footnote_startrKUidsr}r(jNUjJUjmmjhmjmjmjmjmjkjkjkjkj7j7jjjfhj`hjVhjQhjhjhj!j^jefj`fjjjݠj٠jtjmj_j_jEjEjjjjjjjO$jJ$jTjTjjj}jyjjjxjsjjjj joEjkEj?j9jjj5}j1}jjjvDjrDj!jjDjDjjj"NjNj'j'jjjajaj}jyjjjjj67j17j{j{j jjs^jn^j{jwj&j&j6nj1nj:j6j jjhjdjjj("j#"jk2jf2jjj j jkjgj"j"jDjDj j jMjLj\jVjW8jR8j/IjjBEj>Ejzjvjjj~ajyajNjNj6$j1$jjjj j]j]j*j&jsjsjMjMjjjjjjj_hj`hjmjmjpjpj<j6j!j!jӤjϤj>j >jojojpjpjQ2jL2jjjjP\jBjBj>j>j/j/j1j1j@j<j>Lj:Ljv\jo\jjjjj<j8j[jUjjjjjjjMjGjej_j|jwj$jjjjGljBlj[!jW!jBj>jHjDj˧jǧjOjKjW=jR=j#jjMjIjQDjMDj>j>jjjT7jO7jg^jb^j jj j jjj1j+jץjҥjjjV\jR\jnjnjr+jm+jjjjjjj\jXjjjmjij0j,jbjbjjjOjOjj jOjOjjjyjsjGjGj}j}jjj!jz!jjjjj1j1jjjJjJjfjfjEjEj1j-j,j,jjj~j~jvjrjjN\j\jXj7j3j%j%j4j-jvjvj-j)jfjbjZwjTwjbjbj?Oj;Oj4j0jfjfjhjgj>cj9cjQcjLcjF]jA]jbj}bjmj`j\j\jjj"j!j@j@jFj Fjjj jj"j"jjjbjbjvtjrtjjjwjwj=#j8#jRMjNMjl_jg_jJjJjEjAjj j>Nj:NjrJjnJj,>j(>j%j%jUjjjj;`j6`j#JjLIjkjkjjjwjwj}+jx+jnjjj{j{jujtj.cj*cjآjԢjqcjlcjHjCjEjEjrTjnTj=!j9!jEjEjVpjQpjxjtjjjxjtjjj8j\jpjpj(j$jjL\j?j?jwjwjj8jHjCjRjMjFjBj@jAjC~j>~j;vj7vj.j)j~j~jEoj@oj*Tj&TjjjjjejW]jR]jvNjqNj*j*j^jZjljgj%j%je)j`)jjjOjKjNjNj,qj'qj{AjwAjjjգjѣjjj]j]jDjDjDjDjPjPj qjqj^Njjjjjj jjajajjj-j'jgjbj]~jY~jBwj=wjujujuj ujfujaujXsjTsjsjsj tjtjtjtjqjqjrjrjsj sjIsjEsj"j"jՄjфj!j!jjjjjjjlKjhKjjjxOjtOjjjjjjCWj?Jj9JjjYjjjv>jr>jMjMj`j`jjjjjSjSj&JjLIjvjvj?jEjjjjjXjTj&$j"$j j jlejgejNjNjdj`j j jTjTj3~j,~j`>jZ>jjjjj58j08jjjSjSjU>jQ>jjj`_j[_jNjNj>j>jjj:jj9j5j&jj%j!jjsjj jjfjjjjjTjMj]j]j'_j"_jjjljhj4Fj0Fj-j-j>j>j^j^jljhjjj^ajYajjjjjmj|jjj[IjTIj\j\jjjjjjjFj@jNTjJTjjojNjjPjKjn?jj?jwj wj!j!jNjjMjIjvjjujqjjjjjjjjjjjjjɞjŞjTjTj>j>j*j*jjjjj&j"jqjqj#2j2jvjvjjj8j8jjj j jMjMj|j|j0j,j{j{jvjvj[jWjjjwjqjjjKIjjZjTj^j]jjj@j@uUsubstitution_namesr}rjdjqjf}r(jh]jk]jj]Usourcejcji]jn]uU footnotesr]rUrefidsr}r(jj]rjjaj]rjajKI]rjHIaj_h]rj\haj#J]rjRIaj]rjaj]rjaj]rjajm]r j mauub.