€cdocutils.nodes document q)q}q(U nametypesq}q(XMdo-i-need-to-do-any-post-processing-on-pdk-files-generated-by-pin-mux-utilityqˆXgeneral supportqNX0what-documentation-exists-for-processor-sdk-rtosqˆXHhow-can-i-optimize-the-build-time-when-rebuilding-the-processor-sdk-rtosq ˆXc++ build verificationq NX2step-5-generate-and-run-peripheral-driver-examplesq ˆXFhow-can-i-run-ti-rtos-on-secondary-arm-cores-on-multi-core-arm-devicesq ˆX,where-do-i-post-questions-on-generic-ti-rtosq ˆXwwhat-is-the-difference-between-soc-specific-driver-library-and-the-soc-independent-generic-core-specific-driver-libraryqˆXawhat-are-the-typical-flows-for-a-new-user-to-setup-the-processor-sdk-rtos-development-environmentqˆX#where-can-i-locate-ipc-faq-documentqˆX-how-do-i-resolve-edma-instance-usage-conflictqˆX1how-can-i-create-a-sd-card-for-processor-sdk-rtosqˆX edma libraryqNXstep-3-build-environment-setupqˆX^why-did-i-encounter-a-build-issue-while-rebuilding-dsplib-imglib-or-mathlib-with-c6000-cgt-8.xqˆX?processor sdk rtos porting guide for am571x/am570x speed gradesqˆX%mcsdk to processor sdk rtos migrationqˆXKcan-i-use-ndk-software-stack-on-all-devices-supported-in-processor-sdk-rtosqˆXLcan-i-install-multiple-versions-of-the-processor-sdk-rtos-in-the-same-folderqˆXGhow-do-i-find-out-if-a-driver-is-supported-in-the-package-for-my-deviceqˆX release notesqˆXnetworking supportqNXrunning the applicationqNX'step-1-basic-hardware-sdk-and-ide-setupqˆXsteps to buildqNXQhow-to-i-test-my-evm-functionality-can-i-use-the-same-tests-on-my-custom-platformq ˆXchip support library (csl)q!NX0how-can-i-modify-pll-settings-in-board-librariesq"ˆX<how-can-i-restore-the-firmware-on-my-evm-to-factory-settingsq#ˆX&how-do-i-debug-ti-rtos-and-driver-codeq$ˆXZdoes-processor-sdk-rtos-release-support-all-device-part-numbers-in-supported-device-familyq%ˆXdsp-optimized librariesq&NX_why-am-i-not-able-to-connect-to-the-dsp-core-in-ccs-when-linux-is-booted-on-keystone-ii-devicesq'ˆXqin-a-ti-sgmii-to-fpga-phy-port-connection-data-corruption-is-observed-on-egress-direction-what-could-be-the-causeq(ˆX4are-there-any-bare-metal-examples-in-the-pdk-packageq)ˆXawhy-does-the-performance-of-the-dsp-libraries-not-match-with-the-performance-in-the-documentationq*ˆXhhow-do-i-start-writing-my-ti-rtos-application-code-is-there-any-documentation-that-describes-the-processq+ˆXZhow-to-create-arm-baremetal-ccs-project-that-link-to-pdk-driver-libraries-using-gnu-linkerq,ˆX,step-6-exploring-other-components-in-the-sdkq-ˆX#how-do-i-build-and-run-ipc-examplesq.ˆXFhow-do-i-find-out-which-csl-header-and-source-files-apply-to-my-deviceq/ˆX•what-filesystem-support-if-provided-by-processor-sdk-rtos-can-i-use-ubifs-ramfs-or-fatfs-with-ti-rtos-when-using-external-non-volatile-memory-devicesq0ˆXam57x emif toolsq1ˆX#inter-processor communication (ipc)q2NXlis-processor-sdk-rtos-replacing-mcsdk-how-do-i-migrate-from-mcsdk-to-processor-sdk-rtos-for-keystone-devicesq3ˆXkeystonei ddr initializationq4ˆXplatform_supportedq5ˆX<where-do-i-locate-flashing-and-boot-utilities-in-the-packageq6ˆX&keystone-i-and-ii-devices-sgmiimdiophyq7ˆXGwhat-interrupt-latency-foot-print-etc.-can-i-expect-while-using-ti-rtosq8ˆX7how-do-i-download-earlier-version-of-processor-sdk-rtosq9ˆXti rtosq:NXfilesystem supportq;NX$is-unicode-string-supported-in-fatfsq<ˆX>is-there-any-training-content-available-for-processor-sdk-rtosq=ˆX board supportq>NX)ccs-7.1-platform-cant-be-verified-warningq?ˆXGwhy-my-sd-card-stopped-booting-with-the-latest-processor-sdk-bootloaderq@ˆXNi-am-a-current-sitara-starterware-user.-should-i-migrate-to-processor-sdk-rtosqAˆX$am335x/am11x emif configurationtoolsqBˆXgcan-i-read-core-specific-registers-on-multi-core-devices-supported-in-processor-sdk-rtos-using-csl-codeqCˆXdevice driversqDNX1step-2-run-the-out-of-box-examples-or-diagnosticsqEˆXkeystone ii ddr guideqFˆXhost and target setupqGNXZhow-do-i-program-the-phy-through-mdio-interface-i-find-that-ti-init_mdio-function-is-emptyqHˆX@what-are-the-advantages-of-using-the-processor-sdk-rtos-softwareqIˆXRhow-to-setup-sgmii-interface-to-a-phy-or-to-another-sgmii-port-without-using-a-phyqJˆXam437x ddr configuration guideqKˆXkeystone ii ddr debug guideqLˆXewhen-load-a-rtos-example-to-dsp2-the-code-stuck-at-timer.c-before-go-main-but-the-same-worked-on-dsp1qMˆX3where-do-i-find-the-documentation-for-the-ndk-stackqNˆXstep-4-rebuilding-the-sdkqOˆXwhy-do-i-get-a-undefined-reference-to-ti_sysbios_rts_gnu_reentsupport_checkifcorrectlibrary-error-when-compiling-my-applicationqPˆX4how-can-i-run-ti-rtos-ipc-examples-on-am57xx-devicesqQˆXsecondary bootloaderqRNXtraining and documentationqSNX*can-i-run-processor-sdk-rtos-on-beagleboneqTˆX%how-do-i-verify-c++-build-environmentqUˆX6what-is-the-system-memory-map-used-by-the-sdk-examplesqVˆXuseful resourcesqWNXrhow-do-i-setup-the-build-environment-with-custom-processor-sdk-rtos-and-ccs-installation-paths-on-the-host-machineqXˆXChow-do-i-make-a-feature-request-or-file-bugs-for-processor-sdk-rtosqYˆX build setupqZNXplatforms supportedq[NXjwhat-board-initialization-is-required-in-the-application-after-booting-using-the-secondary-boot-loader-sblq\ˆX|can-you-provide-an-example-of-modifying-a-board-library-to-use-a-different-peripheral-instance-as-compared-to-the-evm-designq]ˆXVhow-do-i-know-the-list-of-known-issues-and-bugs-resolved-in-processor-sdk-rtos-releaseq^ˆX§when-i-use-ccs-7.1-for-processor-sdk-rtos-4.0-projects-i-saw-a-warning-platform-name-ti.platforms.xxxxxx-could-not-be-verified.-your-project-may-not-build-as-expected.q_ˆX4where-can-i-find-example-projects-for-device-driversq`ˆX diagnosticsqaNX@what-steps-are-involved-when-creating-a-new-custom-board-libraryqbˆuUsubstitution_defsqc}qdUparse_messagesqe]qf(cdocutils.nodes system_message qg)qh}qi(U rawsourceqjUUparentqkcdocutils.nodes section ql)qm}qn(hjUhkhUsourceqoXH/home/gtbldadm/nightlybuilds/processor-sdk-doc/source/rtos/index_faq.rstqpUtagnameqqUsectionqrU attributesqs}qt(Udupnamesqu]Uclassesqv]Ubackrefsqw]Uidsqx]qyUhost-and-target-setupqzaUnamesq{]q|hGauUlineq}K®Udocumentq~hUchildrenq]q€(cdocutils.nodes title q)q‚}qƒ(hjXHost and Target Setupq„hkhmhohphqUtitleq…hs}q†(hu]hv]hw]hx]h{]uh}K®h~hh]q‡cdocutils.nodes Text qˆXHost and Target Setupq‰…qŠ}q‹(hjh„hkh‚ubaubcdocutils.nodes rubric qŒ)q}qŽ(hjXsHow do I setup the build environment with custom Processor SDK RTOS and CCS Installation paths on the host machine?qhkhmhohphqUrubricqhs}q‘(hx]q’Urhow-do-i-setup-the-build-environment-with-custom-processor-sdk-rtos-and-ccs-installation-paths-on-the-host-machineq“ahw]hu]hv]h{]q”hXauh}Nh~hh]q•hˆXsHow do I setup the build environment with custom Processor SDK RTOS and CCS Installation paths on the host machine?q–…q—}q˜(hjhhkhubaubcdocutils.nodes paragraph q™)qš}q›(hjXśThe steps to set up CCS and Processor SDK RTOS when the SDK or the IDE is installed in a location other than the default location are described below: `Processor SDK RTOS Setup with CCS `__hkhmhohphqU paragraphqœhs}q(hu]hv]hw]hx]h{]uh}K“h~hh]qž(hˆX—The steps to set up CCS and Processor SDK RTOS when the SDK or the IDE is installed in a location other than the default location are described below: qŸ…q }q”(hjX—The steps to set up CCS and Processor SDK RTOS when the SDK or the IDE is installed in a location other than the default location are described below: hkhšubcdocutils.nodes reference q¢)q£}q¤(hjXc`Processor SDK RTOS Setup with CCS `__hs}q„(UnameX!Processor SDK RTOS Setup with CCSUrefuriq¦X;How_to_Guides.html#setup-ccs-for-evm-and-processor-sdk-rtoshx]hw]hu]hv]h{]uhkhšh]q§hˆX!Processor SDK RTOS Setup with CCSq؅q©}qŖ(hjUhkh£ubahqU referenceq«ubeubh™)q¬}q­(hjXČ**A common gotcha while setting up the build environment is compatibility with CCS version. Please refer to `Release Notes `__ for the recommended version of CCS**q®hkhmhohphqhœhs}qÆ(hu]hv]hw]hx]h{]uh}Køh~hh]q°cdocutils.nodes strong q±)q²}q³(hjh®hs}q“(hu]hv]hw]hx]h{]uhkh¬h]qµhˆXÄA common gotcha while setting up the build environment is compatibility with CCS version. Please refer to `Release Notes `__ for the recommended version of CCSq¶…q·}qø(hjUhkh²ubahqUstrongq¹ubaubhŒ)qŗ}q»(hjXMCan I install multiple versions of the Processor SDK RTOS in the same folder?q¼hkhmhohphqhhs}q½(hx]q¾ULcan-i-install-multiple-versions-of-the-processor-sdk-rtos-in-the-same-folderqæahw]hu]hv]h{]qĄhauh}Nh~hh]qĮhˆXMCan I install multiple versions of the Processor SDK RTOS in the same folder?qĀ…qĆ}qÄ(hjh¼hkhŗubaubh™)qÅ}qĘ(hjX”Typically, the version numbers of most components (PDK, Processor SDK, BIOS, XDC, etc.) will be updated in the newer release. However there are components like DSPLIB, IMGLIB, etc. and EDMA drivers that may remain the same. The safe option would be to install the most current Processor SDK in a custom location. You can have multiple versions of the SDK for different devices on your machine and install all of them in custom folders. For example, if you have a project with AM335x and AM437x that requires you to download the Processor SDK RTOS for those device, we recommend that you install them under different directories say C:\\ti\\PRSDK_AM3x and C:\\ti\\PRSDK_AM4xhkhmhohphqhœhs}qĒ(hu]hv]hw]hx]h{]uh}KĮh~hh]qČhˆXTypically, the version numbers of most components (PDK, Processor SDK, BIOS, XDC, etc.) will be updated in the newer release. However there are components like DSPLIB, IMGLIB, etc. and EDMA drivers that may remain the same. The safe option would be to install the most current Processor SDK in a custom location. You can have multiple versions of the SDK for different devices on your machine and install all of them in custom folders. For example, if you have a project with AM335x and AM437x that requires you to download the Processor SDK RTOS for those device, we recommend that you install them under different directories say C:\ti\PRSDK_AM3x and C:\ti\PRSDK_AM4xqɅqŹ}qĖ(hjX”Typically, the version numbers of most components (PDK, Processor SDK, BIOS, XDC, etc.) will be updated in the newer release. However there are components like DSPLIB, IMGLIB, etc. and EDMA drivers that may remain the same. The safe option would be to install the most current Processor SDK in a custom location. You can have multiple versions of the SDK for different devices on your machine and install all of them in custom folders. For example, if you have a project with AM335x and AM437x that requires you to download the Processor SDK RTOS for those device, we recommend that you install them under different directories say C:\\ti\\PRSDK_AM3x and C:\\ti\\PRSDK_AM4xhkhÅubaubcdocutils.nodes note qĢ)qĶ}qĪ(hjX When you install the SDK in a custom location, there are few additional steps to follow: - CCS auto-detects components only in C:\\ti path. So you will need to add the custom path to discovery as described in `Setup CCS `__. - Assuming CCS is installed in the default path, the process to set the custom SDK path while building the SDK is provided in `Install in Custom Path `hkhmhoNhqUnoteqĻhs}qŠ(hu]hv]hw]hx]h{]uh}Nh~hh]qŃ(h™)qŅ}qÓ(hjXXWhen you install the SDK in a custom location, there are few additional steps to follow:qŌhkhĶhohphqhœhs}qÕ(hu]hv]hw]hx]h{]uh}KĶh]qÖhˆXXWhen you install the SDK in a custom location, there are few additional steps to follow:qׅqŲ}qŁ(hjhŌhkhŅubaubcdocutils.nodes bullet_list qŚ)qŪ}qÜ(hjUhs}qŻ(UbulletqŽX-hx]hw]hu]hv]h{]uhkhĶh]qß(cdocutils.nodes list_item qą)qį}qā(hjXĀCCS auto-detects components only in C:\\ti path. So you will need to add the custom path to discovery as described in `Setup CCS `__.hs}qć(hu]hv]hw]hx]h{]uhkhŪh]qäh™)qå}qę(hjXĀCCS auto-detects components only in C:\\ti path. So you will need to add the custom path to discovery as described in `Setup CCS `__.hkhįhohphqhœhs}qē(hu]hv]hw]hx]h{]uh}KŠh]qč(hˆXuCCS auto-detects components only in C:\ti path. So you will need to add the custom path to discovery as described in q酁qź}qė(hjXvCCS auto-detects components only in C:\\ti path. So you will need to add the custom path to discovery as described in hkhåubh¢)qģ}qķ(hjXK`Setup CCS `__hs}qī(UnameX Setup CCSh¦X;How_to_Guides.html#setup-ccs-for-evm-and-processor-sdk-rtoshx]hw]hu]hv]h{]uhkhåh]qļhˆX Setup CCSqš…qń}qņ(hjUhkhģubahqh«ubhˆX.…qó}qō(hjX.hkhåubeubahqU list_itemqõubhą)qö}q÷(hjXŻAssuming CCS is installed in the default path, the process to set the custom SDK path while building the SDK is provided in `Install in Custom Path `hs}qų(hu]hv]hw]hx]h{]uhkhŪh]qłh™)qś}qū(hjXŻAssuming CCS is installed in the default path, the process to set the custom SDK path while building the SDK is provided in `Install in Custom Path `hkhöhohphqhœhs}qü(hu]hv]hw]hx]h{]uh}KÓh]qż(hˆX|Assuming CCS is installed in the default path, the process to set the custom SDK path while building the SDK is provided in qž…q’}r(hjX|Assuming CCS is installed in the default path, the process to set the custom SDK path while building the SDK is provided in hkhśubcdocutils.nodes title_reference r)r}r(hjXa`Install in Custom Path `hs}r(hu]hv]hw]hx]h{]uhkhśh]rhˆX_Install in Custom Path r…r}r(hjUhkjubahqUtitle_referencer ubeubahqhõubehqU bullet_listr ubeubhŒ)r }r (hjXbWhat are the typical flows for a new user to setup the Processor SDK RTOS development environment?r hkhmhohphqhhs}r(hx]rUawhat-are-the-typical-flows-for-a-new-user-to-setup-the-processor-sdk-rtos-development-environmentrahw]hu]hv]h{]rhauh}Nh~hh]rhˆXbWhat are the typical flows for a new user to setup the Processor SDK RTOS development environment?r…r}r(hjj hkj ubaubh™)r}r(hjXEThe typical Processor SDK RTOS setup steps have been described below:rhkhmhohphqhœhs}r(hu]hv]hw]hx]h{]uh}KŪh~hh]rhˆXEThe typical Processor SDK RTOS setup steps have been described below:r…r}r(hjjhkjubaubhŒ)r}r(hjX*Step 1: Basic Hardware, SDK, and IDE Setupr hkhmhohphqhhs}r!(hx]r"U'step-1-basic-hardware-sdk-and-ide-setupr#ahw]hu]hv]h{]r$hauh}Nh~hh]r%hˆX*Step 1: Basic Hardware, SDK, and IDE Setupr&…r'}r((hjj hkjubaubh™)r)}r*(hjXSetup the software and hardware as described in the :ref:`Getting Started Guide ` At this stage, you should have the CCS IDE environment, the Processor SDK RTOS installed and be able to connect to your target using an emulator.hkhmhohphqhœhs}r+(hu]hv]hw]hx]h{]uh}Kąh~hh]r,(hˆX4Setup the software and hardware as described in the r-…r.}r/(hjX4Setup the software and hardware as described in the hkj)ubcsphinx.addnodes pending_xref r0)r1}r2(hjXM:ref:`Getting Started Guide `r3hkj)hohphqU pending_xrefr4hs}r5(UreftypeXrefUrefwarnr6ˆU reftargetr7X.processor-sdk-rtos-getting-started-guide-labelU refdomainXstdr8hx]hw]U refexplicitˆhu]hv]h{]Urefdocr9Xrtos/index_faqr:uh}Kąh]r;cdocutils.nodes inline r<)r=}r>(hjj3hs}r?(hu]hv]r@(UxrefrAj8Xstd-refrBehw]hx]h{]uhkj1h]rChˆXGetting Started GuiderD…rE}rF(hjUhkj=ubahqUinlinerGubaubhˆX’ At this stage, you should have the CCS IDE environment, the Processor SDK RTOS installed and be able to connect to your target using an emulator.rH…rI}rJ(hjX’ At this stage, you should have the CCS IDE environment, the Processor SDK RTOS installed and be able to connect to your target using an emulator.hkj)ubeubhĢ)rK}rL(hjX If you have installed CCS and/or the Processor SDK RTOS in a custom location, you need to manually add the SDK install path to CCS as described here `CCS_and_SDK_installed_in_different_directories `__hkhmhohphqhĻhs}rM(hu]hv]hw]hx]h{]uh}Nh~hh]rNh™)rO}rP(hjX If you have installed CCS and/or the Processor SDK RTOS in a custom location, you need to manually add the SDK install path to CCS as described here `CCS_and_SDK_installed_in_different_directories `__hkjKhohphqhœhs}rQ(hu]hv]hw]hx]h{]uh}Kēh]rR(hˆX•If you have installed CCS and/or the Processor SDK RTOS in a custom location, you need to manually add the SDK install path to CCS as described here rS…rT}rU(hjX•If you have installed CCS and/or the Processor SDK RTOS in a custom location, you need to manually add the SDK install path to CCS as described here hkjOubh¢)rV}rW(hjXv`CCS_and_SDK_installed_in_different_directories `__hs}rX(UnameX.CCS_and_SDK_installed_in_different_directoriesh¦XAHow_to_Guides.html#ccs-and-sdk-installed-in-different-directorieshx]hw]hu]hv]h{]uhkjOh]rYhˆX.CCS_and_SDK_installed_in_different_directoriesrZ…r[}r\(hjUhkjVubahqh«ubeubaubhŒ)r]}r^(hjX2Step 2: Run the Out-of-Box Examples or Diagnosticsr_hkhmhohphqhhs}r`(hx]raU1step-2-run-the-out-of-box-examples-or-diagnosticsrbahw]hu]hv]h{]rchEauh}Nh~hh]rdhˆX2Step 2: Run the Out-of-Box Examples or Diagnosticsre…rf}rg(hjj_hkj]ubaubh™)rh}ri(hjXThe SDK and CCS ships with some pre-built out-of-box demonstrations/examples that can be flashed on to the EVM, copied over to an SD card, or loaded over emulator so that you can bring up and test the EVM hardware. The steps to flash and run the out-of-box examples are described here:rjhkhmhohphqhœhs}rk(hu]hv]hw]hx]h{]uh}Kļh~hh]rlhˆXThe SDK and CCS ships with some pre-built out-of-box demonstrations/examples that can be flashed on to the EVM, copied over to an SD card, or loaded over emulator so that you can bring up and test the EVM hardware. The steps to flash and run the out-of-box examples are described here:rm…rn}ro(hjjjhkjhubaubhŚ)rp}rq(hjUhkhmhohphqj hs}rr(hŽX-hx]hw]hu]hv]h{]uh}Kõh~hh]rshą)rt}ru(hjXe`Running_examples.2Fdemonstrations `__ hkjphohphqhõhs}rv(hu]hv]hw]hx]h{]uh}Nh~hh]rwh™)rx}ry(hjXd`Running_examples.2Fdemonstrations `__rzhkjthohphqhœhs}r{(hu]hv]hw]hx]h{]uh}Kõh]r|h¢)r}}r~(hjjzhs}r(UnameX!Running_examples.2Fdemonstrationsh¦X<Examples_and_Demonstrations.html#examples-and-demonstrationshx]hw]hu]hv]h{]uhkjxh]r€hˆX!Running_examples.2Fdemonstrationsr…r‚}rƒ(hjUhkj}ubahqh«ubaubaubaubhŒ)r„}r…(hjXStep 3: Build Environment Setupr†hkhmhohphqhhs}r‡(hx]rˆUstep-3-build-environment-setupr‰ahw]hu]hv]h{]rŠhauh}Nh~hh]r‹hˆXStep 3: Build Environment SetuprŒ…r}rŽ(hjj†hkj„ubaubh™)r}r(hjX!Processor SDK RTOS provides a script to set up the Windows and Linux environment with the component and compiler PATHs. Running the script and rebuilding the Processor SDK from the root directory is described in the wiki article `Setup build Environment `.hkhmhohphqhœhs}r‘(hu]hv]hw]hx]h{]uh}Kśh~hh]r’(hˆXåProcessor SDK RTOS provides a script to set up the Windows and Linux environment with the component and compiler PATHs. Running the script and rebuilding the Processor SDK from the root directory is described in the wiki article r“…r”}r•(hjXåProcessor SDK RTOS provides a script to set up the Windows and Linux environment with the component and compiler PATHs. Running the script and rebuilding the Processor SDK from the root directory is described in the wiki article hkjubj)r–}r—(hjX;`Setup build Environment `hs}r˜(hu]hv]hw]hx]h{]uhkjh]r™hˆX9Setup build Environment rš…r›}rœ(hjUhkj–ubahqj ubhˆX.…r}rž(hjX.hkjubeubhĢ)rŸ}r (hjXV- The script assumes that CCS and Processor SDK RTOS are installed in the default location. If you have installed CCS and/or the Processor SDK RTOS in a custom location, then modify the setup file to the custom path. Please setup the environment using the steps described in the wiki article `Processor SDK RTOS Install in Custom Path `__ - After the script executes, it prints all the PATH macros set for the different variables. Be sure that the compiler and component paths have been setup correctly.hkhmhoNhqhĻhs}r”(hu]hv]hw]hx]h{]uh}Nh~hh]r¢hŚ)r£}r¤(hjUhs}r„(hŽX-hx]hw]hu]hv]h{]uhkjŸh]r¦(hą)r§}rØ(hjX˜The script assumes that CCS and Processor SDK RTOS are installed in the default location. If you have installed CCS and/or the Processor SDK RTOS in a custom location, then modify the setup file to the custom path. Please setup the environment using the steps described in the wiki article `Processor SDK RTOS Install in Custom Path `__hs}r©(hu]hv]hw]hx]h{]uhkj£h]rŖh™)r«}r¬(hjX˜The script assumes that CCS and Processor SDK RTOS are installed in the default location. If you have installed CCS and/or the Processor SDK RTOS in a custom location, then modify the setup file to the custom path. Please setup the environment using the steps described in the wiki article `Processor SDK RTOS Install in Custom Path `__hkj§hohphqhœhs}r­(hu]hv]hw]hx]h{]uh}Mh]r®(hˆX"The script assumes that CCS and Processor SDK RTOS are installed in the default location. If you have installed CCS and/or the Processor SDK RTOS in a custom location, then modify the setup file to the custom path. Please setup the environment using the steps described in the wiki article rÆ…r°}r±(hjX"The script assumes that CCS and Processor SDK RTOS are installed in the default location. If you have installed CCS and/or the Processor SDK RTOS in a custom location, then modify the setup file to the custom path. Please setup the environment using the steps described in the wiki article hkj«ubh¢)r²}r³(hjXv`Processor SDK RTOS Install in Custom Path `__hs}r“(UnameX)Processor SDK RTOS Install in Custom Pathh¦XFHow_to_Guides.html#update-environment-when-installing-to-a-custom-pathhx]hw]hu]hv]h{]uhkj«h]rµhˆX)Processor SDK RTOS Install in Custom Pathr¶…r·}rø(hjUhkj²ubahqh«ubeubahqhõubhą)r¹}rŗ(hjX¢After the script executes, it prints all the PATH macros set for the different variables. Be sure that the compiler and component paths have been setup correctly.hs}r»(hu]hv]hw]hx]h{]uhkj£h]r¼h™)r½}r¾(hjX¢After the script executes, it prints all the PATH macros set for the different variables. Be sure that the compiler and component paths have been setup correctly.ræhkj¹hohphqhœhs}rĄ(hu]hv]hw]hx]h{]uh}Mh]rĮhˆX¢After the script executes, it prints all the PATH macros set for the different variables. Be sure that the compiler and component paths have been setup correctly.rĀ…rĆ}rÄ(hjjæhkj½ubaubahqhõubehqj ubaubhŒ)rÅ}rĘ(hjXStep 4: Rebuilding the SDKrĒhkhmhohphqhhs}rČ(hx]rÉUstep-4-rebuilding-the-sdkrŹahw]hu]hv]h{]rĖhOauh}Nh~hh]rĢhˆXStep 4: Rebuilding the SDKrĶ…rĪ}rĻ(hjjĒhkjÅubaubh™)rŠ}rŃ(hjXQThe critical device-specific components of the Processor SDK RTOS can be rebuilt from the top-level make file provided in the root directory processor_sdk_rtos_x_xx_xx_xx. Invoking the build and available options from top-level make files is described in the wiki article `Rebuilding SDK Components `__.hkhmhohphqhœhs}rŅ(hu]hv]hw]hx]h{]uh}Mh~hh]rÓ(hˆXThe critical device-specific components of the Processor SDK RTOS can be rebuilt from the top-level make file provided in the root directory processor_sdk_rtos_x_xx_xx_xx. Invoking the build and available options from top-level make files is described in the wiki article rŌ…rÕ}rÖ(hjXThe critical device-specific components of the Processor SDK RTOS can be rebuilt from the top-level make file provided in the root directory processor_sdk_rtos_x_xx_xx_xx. Invoking the build and available options from top-level make files is described in the wiki article hkjŠubh¢)r×}rŲ(hjX@`Rebuilding SDK Components `__hs}rŁ(UnameXRebuilding SDK Componentsh¦X Overview.html#top-level-makefilehx]hw]hu]hv]h{]uhkjŠh]rŚhˆXRebuilding SDK ComponentsrŪ…rÜ}rŻ(hjUhkj×ubahqh«ubhˆX.…rŽ}rß(hjX.hkjŠubeubhĢ)rą}rį(hjX„The SDK offers command line build for all the components. CCS projects are only supported for DSP libraries and PDK driver examples.hkhmhohphqhĻhs}rā(hu]hv]hw]hx]h{]uh}Nh~hh]rćh™)rä}rå(hjX„The SDK offers command line build for all the components. CCS projects are only supported for DSP libraries and PDK driver examples.ręhkjąhohphqhœhs}rē(hu]hv]hw]hx]h{]uh}Mh]rčhˆX„The SDK offers command line build for all the components. CCS projects are only supported for DSP libraries and PDK driver examples.r酁rź}rė(hjjęhkjäubaubaubcdocutils.nodes line_block rģ)rķ}rī(hjUhkhmhohphqU line_blockrļhs}rš(hu]hv]hw]hx]h{]uh}Mh~hh]rńcdocutils.nodes line rņ)ró}rō(hjUUindentrõKhkjķhohphqh}hs}rö(hu]hv]hw]hx]h{]uh}Kh~hh]ubaubhŒ)r÷}rų(hjX3Step 5: Generate and Run Peripheral Driver Examplesrłhkhmhohphqhhs}rś(hx]rūU2step-5-generate-and-run-peripheral-driver-examplesrüahw]hu]hv]h{]rżh auh}Nh~hh]ržhˆX3Step 5: Generate and Run Peripheral Driver Examplesr’…r}r(hjjłhkj÷ubaubh™)r}r(hjXThe PDK component in Processor SDK RTOS provides drivers for different IPs on the SOC and provides unit tests and examples for the drivers to test them on a specific board/hardware. These examples do not ship with pre-generated CCS projects and require users to generate a project create script to generate the CCS project for the unit tests. The procedure to generate the CCS projects for a given SOC is described in this article `PDK_Example_and_Test_Project_Creation `__.hkhmhohphqhœhs}r(hu]hv]hw]hx]h{]uh}Mh~hh]r(hˆXÆThe PDK component in Processor SDK RTOS provides drivers for different IPs on the SOC and provides unit tests and examples for the drivers to test them on a specific board/hardware. These examples do not ship with pre-generated CCS projects and require users to generate a project create script to generate the CCS project for the unit tests. The procedure to generate the CCS projects for a given SOC is described in this article r…r}r(hjXÆThe PDK component in Processor SDK RTOS provides drivers for different IPs on the SOC and provides unit tests and examples for the drivers to test them on a specific board/hardware. These examples do not ship with pre-generated CCS projects and require users to generate a project create script to generate the CCS project for the unit tests. The procedure to generate the CCS projects for a given SOC is described in this article hkjubh¢)r }r (hjXd`PDK_Example_and_Test_Project_Creation `__hs}r (UnameX%PDK_Example_and_Test_Project_Creationh¦X8How_to_Guides.html#pdk-example-and-test-project-creationhx]hw]hu]hv]h{]uhkjh]r hˆX%PDK_Example_and_Test_Project_Creationr …r}r(hjUhkj ubahqh«ubhˆX.…r}r(hjX.hkjubeubhŒ)r}r(hjX-Step 6: Exploring Other Components in the SDKrhkhmhohphqhhs}r(hx]rU,step-6-exploring-other-components-in-the-sdkrahw]hu]hv]h{]rh-auh}Nh~hh]rhˆX-Step 6: Exploring Other Components in the SDKr…r}r(hjjhkjubaubh™)r}r(hjX+The SDK package includes several other components that allow application developers to develop software for multi-core devices. This includes an inter-processor communication component known as (IPC). For SOCs that contain an C66x DSP, the SDK provides several optimized DSP libraries (DSPLIB, MATHLIB and IMGLIB). These components also ship with pre-built examples that can be built using build steps described in their documentation that is linked at the top level `Software Developer Guide `__.hkhmhohphqhœhs}r(hu]hv]hw]hx]h{]uh}M*h~hh]r (hˆXÓThe SDK package includes several other components that allow application developers to develop software for multi-core devices. This includes an inter-processor communication component known as (IPC). For SOCs that contain an C66x DSP, the SDK provides several optimized DSP libraries (DSPLIB, MATHLIB and IMGLIB). These components also ship with pre-built examples that can be built using build steps described in their documentation that is linked at the top level r!…r"}r#(hjXÓThe SDK package includes several other components that allow application developers to develop software for multi-core devices. This includes an inter-processor communication component known as (IPC). For SOCs that contain an C66x DSP, the SDK provides several optimized DSP libraries (DSPLIB, MATHLIB and IMGLIB). These components also ship with pre-built examples that can be built using build steps described in their documentation that is linked at the top level hkjubh¢)r$}r%(hjXW`Software Developer Guide `__hs}r&(UnameXSoftware Developer Guideh¦X8index.html#processor-sdk-rtos-software-developer-s-guidehx]hw]hu]hv]h{]uhkjh]r'hˆXSoftware Developer Guider(…r)}r*(hjUhkj$ubahqh«ubhˆX.…r+}r,(hjX.hkjubeubjģ)r-}r.(hjUhkhmhohphqjļhs}r/(hu]hv]hw]hx]h{]uh}M3h~hh]r0jņ)r1}r2(hjUjõKhkj-hohphqh}hs}r3(hu]hv]hw]hx]h{]uh}Kh~hh]ubaubhŒ)r4}r5(hjXKHow can I optimize the build time when rebuilding the Processor SDK RTOSĀ ?r6hkhmhohphqhhs}r7(hx]r8UHhow-can-i-optimize-the-build-time-when-rebuilding-the-processor-sdk-rtosr9ahw]hu]hv]h{]r:h auh}Nh~hh]r;hˆXKHow can I optimize the build time when rebuilding the Processor SDK RTOSĀ ?r<…r=}r>(hjj6hkj4ubaubh™)r?}r@(hjXÅProcessor SDK RTOS top level build will rebuild IPC, all components inside the PDK package for all supported cores and evaluation platforms. Building all components can cause long build times. If you wish to only rebuild a section of the package, the build times can be significantly optimized if you invoke make for specific components in the SDK instead of making all components. Also, for the PDK users can invoke the build using the following syntaxrAhkhmhohphqhœhs}rB(hu]hv]hw]hx]h{]uh}M9h~hh]rChˆXÅProcessor SDK RTOS top level build will rebuild IPC, all components inside the PDK package for all supported cores and evaluation platforms. Building all components can cause long build times. If you wish to only rebuild a section of the package, the build times can be significantly optimized if you invoke make for specific components in the SDK instead of making all components. Also, for the PDK users can invoke the build using the following syntaxrD…rE}rF(hjjAhkj?ubaubcdocutils.nodes literal_block rG)rH}rI(hjXCmake LIMIT_BOARDS="" LIMIT_SOCS="" LIMIT_CORES=""hkhmhohphqU literal_blockrJhs}rK(U xml:spacerLUpreserverMhx]hw]hu]hv]h{]uh}MCh~hh]rNhˆXCmake LIMIT_BOARDS="" LIMIT_SOCS="" LIMIT_CORES=""rO…rP}rQ(hjUhkjHubaubh™)rR}rS(hjX@**SOC** can be am335x, am437x, am571x, am572x, k2g,k2h,k2e, etc.rThkhmhohphqhœhs}rU(hu]hv]hw]hx]h{]uh}MEh~hh]rV(h±)rW}rX(hjX**SOC**hs}rY(hu]hv]hw]hx]h{]uhkjRh]rZhˆXSOCr[…r\}r](hjUhkjWubahqh¹ubhˆX9 can be am335x, am437x, am571x, am572x, k2g,k2h,k2e, etc.r^…r_}r`(hjX9 can be am335x, am437x, am571x, am572x, k2g,k2h,k2e, etc.hkjRubeubh™)ra}rb(hjXX**CORE** can be ā€œa15_0ā€, ā€œc66xā€, or ā€œipu1_0ā€, for a15, c66, m4 respectively.hkhmhohphqhœhs}rc(hu]hv]hw]hx]h{]uh}MGh~hh]rd(h±)re}rf(hjX**CORE**hs}rg(hu]hv]hw]hx]h{]uhkjah]rhhˆXCOREri…rj}rk(hjUhkjeubahqh¹ubhˆXP can be ā€œa15_0ā€, ā€œc66xā€, or ā€œipu1_0ā€, for a15, c66, m4 respectively.rl…rm}rn(hjXP can be ā€œa15_0ā€, ā€œc66xā€, or ā€œipu1_0ā€, for a15, c66, m4 respectively.hkjaubeubh™)ro}rp(hjXI**BOARD** can be any evaluation hardware platform that your SOC supports.hkhmhohphqhœhs}rq(hu]hv]hw]hx]h{]uh}MJh~hh]rr(h±)rs}rt(hjX **BOARD**hs}ru(hu]hv]hw]hx]h{]uhkjoh]rvhˆXBOARDrw…rx}ry(hjUhkjsubahqh¹ubhˆX@ can be any evaluation hardware platform that your SOC supports.rz…r{}r|(hjX@ can be any evaluation hardware platform that your SOC supports.hkjoubeubjG)r}}r~(hjXSFor Example: make LIMIT_BOARDS="evmK2G iceK2G" LIMIT_SOCS="k2g" LIMIT_CORES="a15_0"hkhmhohphqjJhs}r(jLjMhx]hw]hu]hv]h{]uh}MOh~hh]r€hˆXSFor Example: make LIMIT_BOARDS="evmK2G iceK2G" LIMIT_SOCS="k2g" LIMIT_CORES="a15_0"r…r‚}rƒ(hjUhkj}ubaubjģ)r„}r…(hjUhkhmhohphqjļhs}r†(hu]hv]hw]hx]h{]uh}MQh~hh]r‡jņ)rˆ}r‰(hjUjõKhkj„hohphqh}hs}rŠ(hu]hv]hw]hx]h{]uh}Kh~hh]ubaubhŒ)r‹}rŒ(hjX`Why am I not able to connect to the DSP core in CCS when Linux is booted on KeyStone II devices?rhkhmhohphqhhs}rŽ(hx]rU_why-am-i-not-able-to-connect-to-the-dsp-core-in-ccs-when-linux-is-booted-on-keystone-ii-devicesrahw]hu]hv]h{]r‘h'auh}Nh~hh]r’hˆX`Why am I not able to connect to the DSP core in CCS when Linux is booted on KeyStone II devices?r“…r”}r•(hjjhkj‹ubaubh™)r–}r—(hjXHThe U-boot code that is booted before booting Linux puts the DSP core in reset. In order to connect to the DSP, you need to run a GEL script in CCS as described in this article `Taking_the_C66x_Out_Of_Reset_with_Linux_Running_on_the_ARM_A15 `__.hkhmhohphqhœhs}r˜(hu]hv]hw]hx]h{]uh}MWh~hh]r™(hˆX±The U-boot code that is booted before booting Linux puts the DSP core in reset. In order to connect to the DSP, you need to run a GEL script in CCS as described in this article rš…r›}rœ(hjX±The U-boot code that is booted before booting Linux puts the DSP core in reset. In order to connect to the DSP, you need to run a GEL script in CCS as described in this article hkj–ubh¢)r}rž(hjX–`Taking_the_C66x_Out_Of_Reset_with_Linux_Running_on_the_ARM_A15 `__hs}rŸ(UnameX>Taking_the_C66x_Out_Of_Reset_with_Linux_Running_on_the_ARM_A15h¦XQHow_to_Guides.html#taking-the-c66x-out-of-reset-with-linux-running-on-the-arm-a15hx]hw]hu]hv]h{]uhkj–h]r hˆX>Taking_the_C66x_Out_Of_Reset_with_Linux_Running_on_the_ARM_A15r”…r¢}r£(hjUhkjubahqh«ubhˆX.…r¤}r„(hjX.hkj–ubeubhŒ)r¦}r§(hjX2How can I create a SD card for Processor SDK RTOS?rØhkhmhohphqhhs}r©(hx]rŖU1how-can-i-create-a-sd-card-for-processor-sdk-rtosr«ahw]hu]hv]h{]r¬hauh}Nh~hh]r­hˆX2How can I create a SD card for Processor SDK RTOS?r®…rÆ}r°(hjjØhkj¦ubaubh™)r±}r²(hjX©Many of the TI-supported EVMs ship with an SD card with Linux Booting as part of the EVM out-of-box experience. Users are required to create a separate SD card if they want to boot their EVM with Processor SDK RTOS out-of-box demonstrations or run board diagnostics. The procedure to create an SD differs depending on whether you are doing this on a Windows or Linux host machine, as described in the two articles shown here:r³hkhmhohphqhœhs}r“(hu]hv]hw]hx]h{]uh}M_h~hh]rµhˆX©Many of the TI-supported EVMs ship with an SD card with Linux Booting as part of the EVM out-of-box experience. Users are required to create a separate SD card if they want to boot their EVM with Processor SDK RTOS out-of-box demonstrations or run board diagnostics. The procedure to create an SD differs depending on whether you are doing this on a Windows or Linux host machine, as described in the two articles shown here:r¶…r·}rø(hjj³hkj±ubaubhŚ)r¹}rŗ(hjUhkhmhohphqj hs}r»(hŽX-hx]hw]hu]hv]h{]uh}Mgh~hh]r¼(hą)r½}r¾(hjXe`Create an SD card on Windows Host (AMx, K2G only) `__ hkj¹hohphqhõhs}ræ(hu]hv]hw]hx]h{]uh}Nh~hh]rĄh™)rĮ}rĀ(hjXd`Create an SD card on Windows Host (AMx, K2G only) `__rĆhkj½hohphqhœhs}rÄ(hu]hv]hw]hx]h{]uh}Mgh]rÅh¢)rĘ}rĒ(hjjĆhs}rČ(UnameX1Create an SD card on Windows Host (AMx, K2G only)h¦X,Overview.html#windows-sd-card-creation-guidehx]hw]hu]hv]h{]uhkjĮh]rÉhˆX1Create an SD card on Windows Host (AMx, K2G only)rŹ…rĖ}rĢ(hjUhkjĘubahqh«ubaubaubhą)rĶ}rĪ(hjXa`Create an SD card on Linux Host (AMx, K2G only) `__ hkj¹hohphqhõhs}rĻ(hu]hv]hw]hx]h{]uh}Nh~hh]rŠh™)rŃ}rŅ(hjX``Create an SD card on Linux Host (AMx, K2G only) `__rÓhkjĶhohphqhœhs}rŌ(hu]hv]hw]hx]h{]uh}Mih]rÕh¢)rÖ}r×(hjjÓhs}rŲ(UnameX/Create an SD card on Linux Host (AMx, K2G only)h¦X*Overview.html#linux-sd-card-creation-guidehx]hw]hu]hv]h{]uhkjŃh]rŁhˆX/Create an SD card on Linux Host (AMx, K2G only)rŚ…rŪ}rÜ(hjUhkjÖubahqh«ubaubaubeubhŒ)rŻ}rŽ(hjX=How can I restore the firmware on my EVM to factory settings?rßhkhmhohphqhhs}rą(hx]rįU`__ provided in Processor SDK Linux.hkhmhohphqhœhs}rź(hu]hv]hw]hx]h{]uh}Moh~hh]rė(hˆX¬Most of the Sitara EVMs ship with a bootable SD card that boots Linux. To restore the EVM to factory settings, simply reflash the SD card with the bootable image using the rģ…rķ}rī(hjX¬Most of the Sitara EVMs ship with a bootable SD card that boots Linux. To restore the EVM to factory settings, simply reflash the SD card with the bootable image using the hkjčubh¢)rļ}rš(hjXo`SD Card Creation Script `__hs}rń(UnameXSD Card Creation Scripth¦XQhttp://processors.wiki.ti.com/index.php/Processor_SDK_Linux_create_SD_card_scripthx]hw]hu]hv]h{]uhkjčh]rņhˆXSD Card Creation Scriptró…rō}rõ(hjUhkjļubahqh«ubhˆX! provided in Processor SDK Linux.rö…r÷}rų(hjX! provided in Processor SDK Linux.hkjčubeubh™)rł}rś(hjXźFor KeyStone Devices, the Processor SDK RTOS provides a `Program EVM Script `__ with default binaries that reflash images on EEPROM, SPI, and/or NAND (depending on the EVM platform used).hkhmhohphqhœhs}rū(hu]hv]hw]hx]h{]uh}Muh~hh]rü(hˆX8For KeyStone Devices, the Processor SDK RTOS provides a rż…rž}r’(hjX8For KeyStone Devices, the Processor SDK RTOS provides a hkjłubh¢)r}r(hjXF`Program EVM Script `__hs}r(UnameXProgram EVM Scripth¦X-How_to_Guides.html#default-binaries-and-setuphx]hw]hu]hv]h{]uhkjłh]rhˆXProgram EVM Scriptr…r}r(hjUhkjubahqh«ubhˆXl with default binaries that reflash images on EEPROM, SPI, and/or NAND (depending on the EVM platform used).r…r}r (hjXl with default binaries that reflash images on EEPROM, SPI, and/or NAND (depending on the EVM platform used).hkjłubeubhŒ)r }r (hjX+Can I run Processor SDK RTOS on BeagleBone?r hkhmhohphqhhs}r (hx]rU*can-i-run-processor-sdk-rtos-on-beaglebonerahw]hu]hv]h{]rhTauh}Nh~hh]rhˆX+Can I run Processor SDK RTOS on BeagleBone?r…r}r(hjj hkj ubaubh™)r}r(hjX„Yes, Processor SDK RTOS software can be used to develop and run code on BeagleBone platform. In order to test Processor SDK RTOS software on BeagleBone, you will need to connect a JTAG to the BeagleBone. With the default configuration of the board, we have observed that connecting a JTAG causes a reset. Users need to follow the procedure provided here to prevent a reset from occurring.rhkhmhohphqhœhs}r(hu]hv]hw]hx]h{]uh}M}h~hh]rhˆX„Yes, Processor SDK RTOS software can be used to develop and run code on BeagleBone platform. In order to test Processor SDK RTOS software on BeagleBone, you will need to connect a JTAG to the BeagleBone. With the default configuration of the board, we have observed that connecting a JTAG causes a reset. Users need to follow the procedure provided here to prevent a reset from occurring.r…r}r(hjjhkjubaubhŚ)r}r(hjUhkhmhohphqj hs}r(hŽX-hx]hw]hu]hv]h{]uh}M„h~hh]r hą)r!}r"(hjX•`Preventing a Reset When Connecting a JTAG on BeagleBone `__ hkjhohphqhõhs}r#(hu]hv]hw]hx]h{]uh}Nh~hh]r$h™)r%}r&(hjX”`Preventing a Reset When Connecting a JTAG on BeagleBone `__r'hkj!hohphqhœhs}r((hu]hv]hw]hx]h{]uh}M„h]r)h¢)r*}r+(hjj'hs}r,(UnameX7Preventing a Reset When Connecting a JTAG on BeagleBoneh¦XVhttp://elinux.org/Beagleboard:BeagleBone#Board_Reset_on_JTAG_Connect.28A3.2CA4.2CA5.29hx]hw]hu]hv]h{]uhkj%h]r-hˆX7Preventing a Reset When Connecting a JTAG on BeagleBoner.…r/}r0(hjUhkj*ubahqh«ubaubaubaubjģ)r1}r2(hjUhkhmhohphqjļhs}r3(hu]hv]hw]hx]h{]uh}M‡h~hh]r4jņ)r5}r6(hjUjõKhkj1hohphqh}hs}r7(hu]hv]hw]hx]h{]uh}Kh~hh]ubaubeubhohphqUsystem_messager8hs}r9(hu]UlevelKhx]hw]Usourcehphv]h{]UlineMUtypeUWARNINGr:uh}Mh~hh]r;h™)r<}r=(hjX?Explicit markup ends without a blank line; unexpected unindent.hs}r>(hu]hv]hw]hx]h{]uhkhhh]r?hˆX?Explicit markup ends without a blank line; unexpected unindent.r@…rA}rB(hjUhkj<ubahqhœubaubhg)rC}rD(hjUhkhmhohphqj8hs}rE(hu]UlevelKhx]hw]Usourcehphv]h{]UlineMQUtypej:uh}MPh~hh]rFh™)rG}rH(hjX=Literal block ends without a blank line; unexpected unindent.hs}rI(hu]hv]hw]hx]h{]uhkjCh]rJhˆX=Literal block ends without a blank line; unexpected unindent.rK…rL}rM(hjUhkjGubahqhœubaubhg)rN}rO(hjUhkhl)rP}rQ(hjUhkhhohphqhrhs}rR(hu]hv]hw]hx]rSU board-supportrTah{]rUh>auh}Mkh~hh]rV(h)rW}rX(hjX Board SupportrYhkjPhohphqh…hs}rZ(hu]hv]hw]hx]h{]uh}Mkh~hh]r[hˆX Board Supportr\…r]}r^(hjjYhkjWubaubhŒ)r_}r`(hjXAWhat steps are involved when creating a new custom board library?rahkjPhohphqhhs}rb(hx]rcU@what-steps-are-involved-when-creating-a-new-custom-board-libraryrdahw]hu]hv]h{]rehbauh}Nh~hh]rfhˆXAWhat steps are involved when creating a new custom board library?rg…rh}ri(hjjahkj_ubaubh™)rj}rk(hjXThe board library consolidates all the board-specific information so that all the modifications made when moving to a new custom platform using the SOC can be made in the source of this library. The following steps are involved in creating custom board library:rlhkjPhohphqhœhs}rm(hu]hv]hw]hx]h{]uh}Mqh~hh]rnhˆXThe board library consolidates all the board-specific information so that all the modifications made when moving to a new custom platform using the SOC can be made in the source of this library. The following steps are involved in creating custom board library:ro…rp}rq(hjjlhkjjubaubhŚ)rr}rs(hjUhkjPhohphqj hs}rt(hŽX-hx]hw]hu]hv]h{]uh}Mvh~hh]ru(hą)rv}rw(hjX°**Modify SOC Clock Settings** The core clocks and module clocks used on the custom board library may vary based on the power requirements and external components used on the boards. TI provides `Clock Tree Tools `__ to simulate the device clocks. We recommend that you test the settings in CCS by creating a GEL file with the modified settings before modifying the source in the board library. hkjrhohphqhõhs}rx(hu]hv]hw]hx]h{]uh}Nh~hh]ryh™)rz}r{(hjXÆ**Modify SOC Clock Settings** The core clocks and module clocks used on the custom board library may vary based on the power requirements and external components used on the boards. TI provides `Clock Tree Tools `__ to simulate the device clocks. We recommend that you test the settings in CCS by creating a GEL file with the modified settings before modifying the source in the board library.hkjvhohphqhœhs}r|(hu]hv]hw]hx]h{]uh}Mvh]r}(h±)r~}r(hjX**Modify SOC Clock Settings**hs}r€(hu]hv]hw]hx]h{]uhkjzh]rhˆXModify SOC Clock Settingsr‚…rƒ}r„(hjUhkj~ubahqh¹ubhˆX„ The core clocks and module clocks used on the custom board library may vary based on the power requirements and external components used on the boards. TI provides r……r†}r‡(hjX„ The core clocks and module clocks used on the custom board library may vary based on the power requirements and external components used on the boards. TI provides hkjzubh¢)rˆ}r‰(hjX;`Clock Tree Tools `__hs}rŠ(UnameXClock Tree Toolsh¦X$http://www.ti.com/tool/CLOCKTREETOOLhx]hw]hu]hv]h{]uhkjzh]r‹hˆXClock Tree ToolsrŒ…r}rŽ(hjUhkjˆubahqh«ubhˆX² to simulate the device clocks. We recommend that you test the settings in CCS by creating a GEL file with the modified settings before modifying the source in the board library.r…r}r‘(hjX² to simulate the device clocks. We recommend that you test the settings in CCS by creating a GEL file with the modified settings before modifying the source in the board library.hkjzubeubaubhą)r’}r“(hjX¶**Modify SOC DDR:** The board library has the correct DDR initialization sequence to initialize the DDR memory on your board. You may need to make changes to the AC timings, hardware leveling, and DDR PHY configuration, some or all of which may be different than the TI supported platforms. We recommend that you test the settings in CCS by creating a GEL file with the modified settings before modifying the source in the board library. hkjrhohphqhõhs}r”(hu]hv]hw]hx]h{]uh}Nh~hh]r•h™)r–}r—(hjXµ**Modify SOC DDR:** The board library has the correct DDR initialization sequence to initialize the DDR memory on your board. You may need to make changes to the AC timings, hardware leveling, and DDR PHY configuration, some or all of which may be different than the TI supported platforms. We recommend that you test the settings in CCS by creating a GEL file with the modified settings before modifying the source in the board library.hkj’hohphqhœhs}r˜(hu]hv]hw]hx]h{]uh}M~h]r™(h±)rš}r›(hjX**Modify SOC DDR:**hs}rœ(hu]hv]hw]hx]h{]uhkj–h]rhˆXModify SOC DDR:rž…rŸ}r (hjUhkjšubahqh¹ubhˆX¢ The board library has the correct DDR initialization sequence to initialize the DDR memory on your board. You may need to make changes to the AC timings, hardware leveling, and DDR PHY configuration, some or all of which may be different than the TI supported platforms. We recommend that you test the settings in CCS by creating a GEL file with the modified settings before modifying the source in the board library.r”…r¢}r£(hjX¢ The board library has the correct DDR initialization sequence to initialize the DDR memory on your board. You may need to make changes to the AC timings, hardware leveling, and DDR PHY configuration, some or all of which may be different than the TI supported platforms. We recommend that you test the settings in CCS by creating a GEL file with the modified settings before modifying the source in the board library.hkj–ubeubaubeubh™)r¤}r„(hjX&**Useful DDR Configuration Resources**r¦hkjPhohphqhœhs}r§(hu]hv]hw]hx]h{]uh}M†h~hh]rØh±)r©}rŖ(hjj¦hs}r«(hu]hv]hw]hx]h{]uhkj¤h]r¬hˆX"Useful DDR Configuration Resourcesr­…r®}rÆ(hjUhkj©ubahqh¹ubaubcdocutils.nodes table r°)r±}r²(hjUhkjPhohphqUtabler³hs}r“(hu]hv]hw]hx]h{]uh}Nh~hh]rµcdocutils.nodes tgroup r¶)r·}rø(hjUhs}r¹(hx]hw]hu]hv]h{]UcolsKuhkj±h]rŗ(cdocutils.nodes colspec r»)r¼}r½(hjUhs}r¾(hx]hw]hu]hv]h{]UcolwidthK‚uhkj·h]hqUcolspecræubj»)rĄ}rĮ(hjUhs}rĀ(hx]hw]hu]hv]h{]UcolwidthKFuhkj·h]hqjæubcdocutils.nodes thead rĆ)rÄ}rÅ(hjUhs}rĘ(hu]hv]hw]hx]h{]uhkj·h]rĒcdocutils.nodes row rČ)rÉ}rŹ(hjUhs}rĖ(hu]hv]hw]hx]h{]uhkjÄh]rĢ(cdocutils.nodes entry rĶ)rĪ}rĻ(hjUhs}rŠ(hu]hv]hw]hx]h{]uhkjÉh]rŃh™)rŅ}rÓ(hjXSitara Resources:rŌhkjĪhohphqhœhs}rÕ(hu]hv]hw]hx]h{]uh}M‰h]rÖhˆXSitara Resources:r×…rŲ}rŁ(hjjŌhkjŅubaubahqUentryrŚubjĶ)rŪ}rÜ(hjUhs}rŻ(hu]hv]hw]hx]h{]uhkjÉh]rŽh™)rß}rą(hjXKeystone Resources:rįhkjŪhohphqhœhs}rā(hu]hv]hw]hx]h{]uh}M‰h]rćhˆXKeystone Resources:r䅁rå}rę(hjjįhkjßubaubahqjŚubehqUrowrēubahqUtheadrčubcdocutils.nodes tbody ré)rź}rė(hjUhs}rģ(hu]hv]hw]hx]h{]uhkj·h]rķ(jČ)rī}rļ(hjUhs}rš(hu]hv]hw]hx]h{]uhkjźh]rń(jĶ)rņ}ró(hjUhs}rō(hu]hv]hw]hx]h{]uhkjīh]rõh™)rö}r÷(hjX7`AM57x EMIF Tools `_rųhkjņhohphqhœhs}rł(hu]hv]hw]hx]h{]uh}M‹h]rś(h¢)rū}rü(hjjųhs}rż(UnameXAM57x EMIF Toolsh¦X!http://www.ti.com/lit/pdf/sprac36ržhx]hw]hu]hv]h{]uhkjöh]r’hˆXAM57x EMIF Toolsr…r}r(hjUhkjūubahqh«ubcdocutils.nodes target r)r}r(hjX$ U referencedrKhkjöhqUtargetrhs}r(Urefurijžhx]r Uam57x-emif-toolsr ahw]hu]hv]h{]r h1auh]ubeubahqjŚubjĶ)r }r (hjUhs}r(hu]hv]hw]hx]h{]uhkjīh]rh™)r}r(hjX<`KeyStone II DDR Guide `_rhkj hohphqhœhs}r(hu]hv]hw]hx]h{]uh}M‹h]r(h¢)r}r(hjjhs}r(UnameXKeyStone II DDR Guideh¦X!http://www.ti.com/lit/pdf/sprabx7rhx]hw]hu]hv]h{]uhkjh]rhˆXKeyStone II DDR Guider…r}r(hjUhkjubahqh«ubj)r}r(hjX$ jKhkjhqjhs}r(Urefurijhx]r Ukeystone-ii-ddr-guider!ahw]hu]hv]h{]r"hFauh]ubeubahqjŚubehqjēubjČ)r#}r$(hjUhs}r%(hu]hv]hw]hx]h{]uhkjźh]r&(jĶ)r'}r((hjUhs}r)(hu]hv]hw]hx]h{]uhkj#h]r*h™)r+}r,(hjXz`AM437x DDR Configuration Guide `_r-hkj'hohphqhœhs}r.(hu]hv]hw]hx]h{]uh}Mh]r/(h¢)r0}r1(hjj-hs}r2(UnameXAM437x DDR Configuration Guideh¦XVhttp://processors.wiki.ti.com/index.php/AM437x_DDR_Configuration_and_Programming_Guider3hx]hw]hu]hv]h{]uhkj+h]r4hˆXAM437x DDR Configuration Guider5…r6}r7(hjUhkj0ubahqh«ubj)r8}r9(hjXY jKhkj+hqjhs}r:(Urefurij3hx]r;Uam437x-ddr-configuration-guider<ahw]hu]hv]h{]r=hKauh]ubeubahqjŚubjĶ)r>}r?(hjUhs}r@(hu]hv]hw]hx]h{]uhkj#h]rAh™)rB}rC(hjXB`KeyStone II DDR Debug Guide `_rDhkj>hohphqhœhs}rE(hu]hv]hw]hx]h{]uh}Mh]rF(h¢)rG}rH(hjjDhs}rI(UnameXKeyStone II DDR Debug Guideh¦X!http://www.ti.com/lit/pdf/sprac04rJhx]hw]hu]hv]h{]uhkjBh]rKhˆXKeyStone II DDR Debug GuiderL…rM}rN(hjUhkjGubahqh«ubj)rO}rP(hjX$ jKhkjBhqjhs}rQ(UrefurijJhx]rRUkeystone-ii-ddr-debug-guiderSahw]hu]hv]h{]rThLauh]ubeubahqjŚubehqjēubjČ)rU}rV(hjUhs}rW(hu]hv]hw]hx]h{]uhkjźh]rX(jĶ)rY}rZ(hjUhs}r[(hu]hv]hw]hx]h{]uhkjUh]r\h™)r]}r^(hjXp`AM335x/AM11x EMIF ConfigurationTools `_r_hkjYhohphqhœhs}r`(hu]hv]hw]hx]h{]uh}Mh]ra(h¢)rb}rc(hjj_hs}rd(UnameX$AM335x/AM11x EMIF ConfigurationToolsh¦XFhttp://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tipsrehx]hw]hu]hv]h{]uhkj]h]rfhˆX$AM335x/AM11x EMIF ConfigurationToolsrg…rh}ri(hjUhkjbubahqh«ubj)rj}rk(hjXI jKhkj]hqjhs}rl(Urefurijehx]rmU$am335x-am11x-emif-configurationtoolsrnahw]hu]hv]h{]rohBauh]ubeubahqjŚubjĶ)rp}rq(hjUhs}rr(hu]hv]hw]hx]h{]uhkjUh]rsh™)rt}ru(hjXC`KeyStoneI DDR Initialization `_rvhkjphohphqhœhs}rw(hu]hv]hw]hx]h{]uh}Mh]rx(h¢)ry}rz(hjjvhs}r{(UnameXKeyStoneI DDR Initializationh¦X!http://www.ti.com/lit/pdf/sprabl2r|hx]hw]hu]hv]h{]uhkjth]r}hˆXKeyStoneI DDR Initializationr~…r}r€(hjUhkjyubahqh«ubj)r}r‚(hjX$ jKhkjthqjhs}rƒ(Urefurij|hx]r„Ukeystonei-ddr-initializationr…ahw]hu]hv]h{]r†h4auh]ubeubahqjŚubehqjēubehqUtbodyr‡ubehqUtgrouprˆubaubhŚ)r‰}rŠ(hjUhkjPhohphqj hs}r‹(hŽX-hx]hw]hu]hv]h{]uh}M’h~hh]rŒ(hą)r}rŽ(hjX°**Modify SoC Pin Mux Settings.** The Pin Mux configuration for a particular platform is obtained by creating a .pinmux project for the device using the `TI Pin Mux Tools `__ available on ti.com. The output of the tool can be plugged into the board library to modify the default configuration. The default baseline Pin Mux project (boardname.pinmux) is included in the board library for reference. hkj‰hohphqhõhs}r(hu]hv]hw]hx]h{]uh}Nh~hh]rh™)r‘}r’(hjXÆ**Modify SoC Pin Mux Settings.** The Pin Mux configuration for a particular platform is obtained by creating a .pinmux project for the device using the `TI Pin Mux Tools `__ available on ti.com. The output of the tool can be plugged into the board library to modify the default configuration. The default baseline Pin Mux project (boardname.pinmux) is included in the board library for reference.hkjhohphqhœhs}r“(hu]hv]hw]hx]h{]uh}M’h]r”(h±)r•}r–(hjX **Modify SoC Pin Mux Settings.**hs}r—(hu]hv]hw]hx]h{]uhkj‘h]r˜hˆXModify SoC Pin Mux Settings.r™…rš}r›(hjUhkj•ubahqh¹ubhˆXx The Pin Mux configuration for a particular platform is obtained by creating a .pinmux project for the device using the rœ…r}rž(hjXx The Pin Mux configuration for a particular platform is obtained by creating a .pinmux project for the device using the hkj‘ubh¢)rŸ}r (hjX8`TI Pin Mux Tools `__hs}r”(UnameXTI Pin Mux Toolsh¦X!http://www.ti.com/tool/PINMUXTOOLhx]hw]hu]hv]h{]uhkj‘h]r¢hˆXTI Pin Mux Toolsr£…r¤}r„(hjUhkjŸubahqh«ubhˆXß available on ti.com. The output of the tool can be plugged into the board library to modify the default configuration. The default baseline Pin Mux project (boardname.pinmux) is included in the board library for reference.r¦…r§}rØ(hjXß available on ti.com. The output of the tool can be plugged into the board library to modify the default configuration. The default baseline Pin Mux project (boardname.pinmux) is included in the board library for reference.hkj‘ubeubaubhą)r©}rŖ(hjX"**Modify IO Instance and Configuration to Match Use Case:** If your custom board uses an IO instance different from the TI-supported board, the instance needs to be modified in the Pin Mux setup as well as in the board_cfg.h file in pdk_xx_Xx_xx_xx/packages/ti/board/src// hkj‰hohphqhõhs}r«(hu]hv]hw]hx]h{]uh}Nh~hh]r¬h™)r­}r®(hjX!**Modify IO Instance and Configuration to Match Use Case:** If your custom board uses an IO instance different from the TI-supported board, the instance needs to be modified in the Pin Mux setup as well as in the board_cfg.h file in pdk_xx_Xx_xx_xx/packages/ti/board/src//hkj©hohphqhœhs}rÆ(hu]hv]hw]hx]h{]uh}Mšh]r°(h±)r±}r²(hjX;**Modify IO Instance and Configuration to Match Use Case:**hs}r³(hu]hv]hw]hx]h{]uhkj­h]r“hˆX7Modify IO Instance and Configuration to Match Use Case:rµ…r¶}r·(hjUhkj±ubahqh¹ubhˆXę If your custom board uses an IO instance different from the TI-supported board, the instance needs to be modified in the Pin Mux setup as well as in the board_cfg.h file in pdk_xx_Xx_xx_xx/packages/ti/board/src//rø…r¹}rŗ(hjXę If your custom board uses an IO instance different from the TI-supported board, the instance needs to be modified in the Pin Mux setup as well as in the board_cfg.h file in pdk_xx_Xx_xx_xx/packages/ti/board/src//hkj­ubeubaubhą)r»}r¼(hjX**Modify Files Corresponding to External Board Components:** The custom board may have external components (flash devices, Ethernet PHY, etc.) that are different from the components populated on the TI-supported EVM. These components and their support files need to be added to the pdk_xx_Xx_xx_xx/packages/ti/board/src//device path and linked as part of the board library build. hkj‰hohphqhõhs}r½(hu]hv]hw]hx]h{]uh}Nh~hh]r¾h™)ræ}rĄ(hjXŒ**Modify Files Corresponding to External Board Components:** The custom board may have external components (flash devices, Ethernet PHY, etc.) that are different from the components populated on the TI-supported EVM. These components and their support files need to be added to the pdk_xx_Xx_xx_xx/packages/ti/board/src//device path and linked as part of the board library build.hkj»hohphqhœhs}rĮ(hu]hv]hw]hx]h{]uh}M h]rĀ(h±)rĆ}rÄ(hjX<**Modify Files Corresponding to External Board Components:**hs}rÅ(hu]hv]hw]hx]h{]uhkjæh]rĘhˆX8Modify Files Corresponding to External Board Components:rĒ…rČ}rÉ(hjUhkjĆubahqh¹ubhˆXP The custom board may have external components (flash devices, Ethernet PHY, etc.) that are different from the components populated on the TI-supported EVM. These components and their support files need to be added to the pdk_xx_Xx_xx_xx/packages/ti/board/src//device path and linked as part of the board library build.rŹ…rĖ}rĢ(hjXP The custom board may have external components (flash devices, Ethernet PHY, etc.) that are different from the components populated on the TI-supported EVM. These components and their support files need to be added to the pdk_xx_Xx_xx_xx/packages/ti/board/src//device path and linked as part of the board library build.hkjæubeubaubeubh™)rĶ}rĪ(hjX‹The above steps have been explained in detail in **Section 9** of the **`Application Development Using Processor SDK RTOS Training `__**. The slides talk about the different aspects of porting Processor SDK 3.0 to your custom platform, including incorporating custom Pin Mux, clocking, peripheral instance, etc.hkjPhohphqhœhs}rĻ(hu]hv]hw]hx]h{]uh}MØh~hh]rŠ(hˆX1The above steps have been explained in detail in rŃ…rŅ}rÓ(hjX1The above steps have been explained in detail in hkjĶubh±)rŌ}rÕ(hjX **Section 9**hs}rÖ(hu]hv]hw]hx]h{]uhkjĶh]r×hˆX Section 9rŲ…rŁ}rŚ(hjUhkjŌubahqh¹ubhˆX of the rŪ…rÜ}rŻ(hjX of the hkjĶubh±)rŽ}rß(hjX–**`Application Development Using Processor SDK RTOS Training `__**hs}rą(hu]hv]hw]hx]h{]uhkjĶh]rįhˆX’`Application Development Using Processor SDK RTOS Training `__rā…rć}rä(hjUhkjŽubahqh¹ubhˆXÆ. The slides talk about the different aspects of porting Processor SDK 3.0 to your custom platform, including incorporating custom Pin Mux, clocking, peripheral instance, etc.r允rę}rē(hjXÆ. The slides talk about the different aspects of porting Processor SDK 3.0 to your custom platform, including incorporating custom Pin Mux, clocking, peripheral instance, etc.hkjĶubeubh™)rč}ré(hjXżAdding custom board to the PDK directory structure and build setup is described in the article `Adding_Custom_Board_Library_Target_to_Processor_SDK_RTOS_makefiles `__hkjPhohphqhœhs}rź(hu]hv]hw]hx]h{]uh}MÆh~hh]rė(hˆX_Adding custom board to the PDK directory structure and build setup is described in the article rģ…rķ}rī(hjX_Adding custom board to the PDK directory structure and build setup is described in the article hkjčubh¢)rļ}rš(hjXž`Adding_Custom_Board_Library_Target_to_Processor_SDK_RTOS_makefiles `__hs}rń(UnameXBAdding_Custom_Board_Library_Target_to_Processor_SDK_RTOS_makefilesh¦XUHow_to_Guides.html#adding-custom-board-library-target-to-processor-sdk-rtos-makefileshx]hw]hu]hv]h{]uhkjčh]rņhˆXBAdding_Custom_Board_Library_Target_to_Processor_SDK_RTOS_makefilesró…rō}rõ(hjUhkjļubahqh«ubeubhĢ)rö}r÷(hjXRTI evaluation platforms for Sitara Processors usually have board information stored in an EEPROM which checks for revision number and board name which is used to configure the board. When creating a custom platform if you don`t intend to use an EEPROM then we recommend removing code corresponding to Board_getIDInfo in your board libraryhkjPhohphqhĻhs}rų(hu]hv]hw]hx]h{]uh}Nh~hh]rłh™)rś}rū(hjXRTI evaluation platforms for Sitara Processors usually have board information stored in an EEPROM which checks for revision number and board name which is used to configure the board. When creating a custom platform if you don`t intend to use an EEPROM then we recommend removing code corresponding to Board_getIDInfo in your board libraryrühkjöhohphqhœhs}rż(hu]hv]hw]hx]h{]uh}M“h]ržhˆXRTI evaluation platforms for Sitara Processors usually have board information stored in an EEPROM which checks for revision number and board name which is used to configure the board. When creating a custom platform if you don`t intend to use an EEPROM then we recommend removing code corresponding to Board_getIDInfo in your board libraryr’…r}r(hjjühkjśubaubaubjģ)r}r(hjUhkjPhohphqjļhs}r(hu]hv]hw]hx]h{]uh}M¹h~hh]rjņ)r}r(hjUjõKhkjhohphqh}hs}r(hu]hv]hw]hx]h{]uh}Kh~hh]ubaubhŒ)r }r (hjXNDo I need to do any post processing on PDK files generated by Pin Mux Utility?r hkjPhohphqhhs}r (hx]r UMdo-i-need-to-do-any-post-processing-on-pdk-files-generated-by-pin-mux-utilityrahw]hu]hv]h{]rhauh}Nh~hh]rhˆXNDo I need to do any post processing on PDK files generated by Pin Mux Utility?r…r}r(hjj hkj ubaubh™)r}r(hjXśThe Pin Mux utility is designed to automate the integration of a custom-designed SOC pin map into the board library software. For AM335x, AM437x, and K2G devices, the PDK files generated by the utility can be integrated into the board library without any manual edits to the files. For AM57x users, there are system design-level considerations that require the user to manually select IO delay modes for specific peripherals, which may require manual intervention before integrating with the board library.rhkjPhohphqhœhs}r(hu]hv]hw]hx]h{]uh}Mæh~hh]rhˆXśThe Pin Mux utility is designed to automate the integration of a custom-designed SOC pin map into the board library software. For AM335x, AM437x, and K2G devices, the PDK files generated by the utility can be integrated into the board library without any manual edits to the files. For AM57x users, there are system design-level considerations that require the user to manually select IO delay modes for specific peripherals, which may require manual intervention before integrating with the board library.r…r}r(hjjhkjubaubh™)r}r(hjX+An example for modifying the Pin Mux in the board library to modify the UART instance on AM335x is provided in the wiki article `Processor SDK RTOS Customization `__.hkjPhohphqhœhs}r(hu]hv]hw]hx]h{]uh}MČh~hh]r(hˆX€An example for modifying the Pin Mux in the board library to modify the UART instance on AM335x is provided in the wiki article r …r!}r"(hjX€An example for modifying the Pin Mux in the board library to modify the UART instance on AM335x is provided in the wiki article hkjubh¢)r#}r$(hjXŖ`Processor SDK RTOS Customization `__hs}r%(UnameX Processor SDK RTOS Customizationh¦Xƒhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_Customization:_Modifying_Board_library_to_change_UART_instance_on_AM335xhx]hw]hu]hv]h{]uhkjh]r&hˆX Processor SDK RTOS Customizationr'…r(}r)(hjUhkj#ubahqh«ubhˆX.…r*}r+(hjX.hkjubeubh™)r,}r-(hjX**For More Information:** Refer to `Application Development Using Processor SDK RTOS Training `__ and `Application Notes on AM57xx Pin Multiplexing Utilities `__.hkjPhohphqhœhs}r.(hu]hv]hw]hx]h{]uh}MĶh~hh]r/(h±)r0}r1(hjX**For More Information:**hs}r2(hu]hv]hw]hx]h{]uhkj,h]r3hˆXFor More Information:r4…r5}r6(hjUhkj0ubahqh¹ubhˆX Refer to r7…r8}r9(hjX Refer to hkj,ubh¢)r:}r;(hjX’`Application Development Using Processor SDK RTOS Training `__hs}r<(UnameX9Application Development Using Processor SDK RTOS Trainingh¦XRhttp://training.ti.com/application-development-using-processor-sdk-rtos/index.htmlhx]hw]hu]hv]h{]uhkj,h]r=hˆX9Application Development Using Processor SDK RTOS Trainingr>…r?}r@(hjUhkj:ubahqh«ubhˆX and rA…rB}rC(hjX and hkj,ubh¢)rD}rE(hjX^`Application Notes on AM57xx Pin Multiplexing Utilities `__hs}rF(UnameX6Application Notes on AM57xx Pin Multiplexing Utilitiesh¦X!http://www.ti.com/lit/pdf/sprac44hx]hw]hu]hv]h{]uhkj,h]rGhˆX6Application Notes on AM57xx Pin Multiplexing UtilitiesrH…rI}rJ(hjUhkjDubahqh«ubhˆX.…rK}rL(hjX.hkj,ubeubhŒ)rM}rN(hjX1How can I modify PLL settings in board libraries?rOhkjPhohphqhhs}rP(hx]rQU0how-can-i-modify-pll-settings-in-board-librariesrRahw]hu]hv]h{]rSh"auh}Nh~hh]rThˆX1How can I modify PLL settings in board libraries?rU…rV}rW(hjjOhkjMubaubh™)rX}rY(hjXÉThe SOC board library in the PDK configures the SOC PLL and module clock settings to the nominal settings required to be used with the TI evaluation platform. If you want to use different clock settings due to power consideration, or if you are using a variant of the device that needs to be clocked differently, you can enter the PLL and clock settings in the board library. All of the PLL and module clock settings are consolidated in the following files:rZhkjPhohphqhœhs}r[(hu]hv]hw]hx]h{]uh}MÖh~hh]r\hˆXÉThe SOC board library in the PDK configures the SOC PLL and module clock settings to the nominal settings required to be used with the TI evaluation platform. If you want to use different clock settings due to power consideration, or if you are using a variant of the device that needs to be clocked differently, you can enter the PLL and clock settings in the board library. All of the PLL and module clock settings are consolidated in the following files:r]…r^}r_(hjjZhkjXubaubhŚ)r`}ra(hjUhkjPhohphqj hs}rb(hŽX-hx]hw]hu]hv]h{]uh}MŽh~hh]rc(hą)rd}re(hjX‡.c: Contains calls related to all board-level initialization. refers to the evaluation platform (For example, evmam335x)hkj`hohphqhõhs}rf(hu]hv]hw]hx]h{]uh}Nh~hh]rgh™)rh}ri(hjX‡.c: Contains calls related to all board-level initialization. refers to the evaluation platform (For example, evmam335x)rjhkjdhohphqhœhs}rk(hu]hv]hw]hx]h{]uh}MŽh]rlhˆX‡.c: Contains calls related to all board-level initialization. refers to the evaluation platform (For example, evmam335x)rm…rn}ro(hjjjhkjhubaubaubhą)rp}rq(hjXr_pll.c: Defines the Board_PLLInit() function that configures the dividers and multipliers for the clock tree.hkj`hohphqhõhs}rr(hu]hv]hw]hx]h{]uh}Nh~hh]rsh™)rt}ru(hjXr_pll.c: Defines the Board_PLLInit() function that configures the dividers and multipliers for the clock tree.rvhkjphohphqhœhs}rw(hu]hv]hw]hx]h{]uh}Mąh]rxhˆXr_pll.c: Defines the Board_PLLInit() function that configures the dividers and multipliers for the clock tree.ry…rz}r{(hjjvhkjtubaubaubhą)r|}r}(hjX‚_clock.c: Defines clock dividers, scalars, and multipliers for individual board modules initialized using the board library. hkj`hohphqhõhs}r~(hu]hv]hw]hx]h{]uh}Nh~hh]rh™)r€}r(hjX_clock.c: Defines clock dividers, scalars, and multipliers for individual board modules initialized using the board library.r‚hkj|hohphqhœhs}rƒ(hu]hv]hw]hx]h{]uh}Māh]r„hˆX_clock.c: Defines clock dividers, scalars, and multipliers for individual board modules initialized using the board library.r……r†}r‡(hjj‚hkj€ubaubaubeubhŒ)rˆ}r‰(hjX}Can you provide an example of modifying a board library to use a different peripheral instance as compared to the EVM design?rŠhkjPhohphqhhs}r‹(hx]rŒU|can-you-provide-an-example-of-modifying-a-board-library-to-use-a-different-peripheral-instance-as-compared-to-the-evm-designrahw]hu]hv]h{]rŽh]auh}Nh~hh]rhˆX}Can you provide an example of modifying a board library to use a different peripheral instance as compared to the EVM design?r…r‘}r’(hjjŠhkjˆubaubh™)r“}r”(hjXĻA good example of the steps involved in modifying a peripheral instance is provided in the application note "`Processor SDK RTOS Customization: Modifying UART Instance `__"hkjPhohphqhœhs}r•(hu]hv]hw]hx]h{]uh}Méh~hh]r–(hˆXmA good example of the steps involved in modifying a peripheral instance is provided in the application note "r—…r˜}r™(hjXmA good example of the steps involved in modifying a peripheral instance is provided in the application note "hkj“ubh¢)rš}r›(hjXa`Processor SDK RTOS Customization: Modifying UART Instance `__hs}rœ(UnameX9Processor SDK RTOS Customization: Modifying UART Instanceh¦X!http://www.ti.com/lit/pdf/sprac32hx]hw]hu]hv]h{]uhkj“h]rhˆX9Processor SDK RTOS Customization: Modifying UART Instancerž…rŸ}r (hjUhkjšubahqh«ubhˆX"…r”}r¢(hjX"hkj“ubeubjģ)r£}r¤(hjUhkjPhohphqjļhs}r„(hu]hv]hw]hx]h{]uh}Mīh~hh]r¦jņ)r§}rØ(hjUjõKhkj£hohphqh}hs}r©(hu]hv]hw]hx]h{]uh}Kh~hh]ubaubeubhohphqj8hs}rŖ(hu]UlevelKhx]hw]Usourcehphv]h{]UlineM¹Utypej:uh}Møh~hh]r«h™)r¬}r­(hjX?Explicit markup ends without a blank line; unexpected unindent.hs}r®(hu]hv]hw]hx]h{]uhkjNh]rÆhˆX?Explicit markup ends without a blank line; unexpected unindent.r°…r±}r²(hjUhkj¬ubahqhœubaubhg)r³}r“(hjUhkhl)rµ}r¶(hjUhkhhohphqhrhs}r·(hu]hv]hw]hx]røU diagnosticsr¹ah{]rŗhaauh}M/h~hh]r»(h)r¼}r½(hjX Diagnosticsr¾hkjµhohphqh…hs}ræ(hu]hv]hw]hx]h{]uh}M/h~hh]rĄhˆX DiagnosticsrĮ…rĀ}rĆ(hjj¾hkj¼ubaubhŒ)rÄ}rÅ(hjXSHow to I test my EVM functionality? Can I use the same tests on my custom platform?rĘhkjµhohphqhhs}rĒ(hx]rČUQhow-to-i-test-my-evm-functionality-can-i-use-the-same-tests-on-my-custom-platformrÉahw]hu]hv]h{]rŹh auh}Nh~hh]rĖhˆXSHow to I test my EVM functionality? Can I use the same tests on my custom platform?rĢ…rĶ}rĪ(hjjĘhkjÄubaubh™)rĻ}rŠ(hjX”The Processor SDK RTOS provides unit tests to test interfaces on the EVM as part of diagnostics package that can be found in the package in the path pdk__x_x_x\\packages\\ti\\board\\diag. It also provides a framework to run each of these tests through a command line serial interface. Users can either load the tests using an emulator or they can load them over an SD card to test the EVM functionality.hkjµhohphqhœhs}rŃ(hu]hv]hw]hx]h{]uh}M5h~hh]rŅhˆXThe Processor SDK RTOS provides unit tests to test interfaces on the EVM as part of diagnostics package that can be found in the package in the path pdk__x_x_x\packages\ti\board\diag. It also provides a framework to run each of these tests through a command line serial interface. Users can either load the tests using an emulator or they can load them over an SD card to test the EVM functionality.rÓ…rŌ}rÕ(hjX”The Processor SDK RTOS provides unit tests to test interfaces on the EVM as part of diagnostics package that can be found in the package in the path pdk__x_x_x\\packages\\ti\\board\\diag. It also provides a framework to run each of these tests through a command line serial interface. Users can either load the tests using an emulator or they can load them over an SD card to test the EVM functionality.hkjĻubaubh™)rÖ}r×(hjX·These tests, like all other examples in the SDK, rely on the board library to perform the SOC and board initialization. So if you have modified the board library to account for the components on your custom hardware, then you should be able to re-use the diagnostic tests while bringing up your custom hardware. Users will link to the new board library and rebuild the diagnostics package to leverage these examples on the custom hardware.rŲhkjµhohphqhœhs}rŁ(hu]hv]hw]hx]h{]uh}M<h~hh]rŚhˆX·These tests, like all other examples in the SDK, rely on the board library to perform the SOC and board initialization. So if you have modified the board library to account for the components on your custom hardware, then you should be able to re-use the diagnostic tests while bringing up your custom hardware. Users will link to the new board library and rebuild the diagnostics package to leverage these examples on the custom hardware.rŪ…rÜ}rŻ(hjjŲhkjÖubaubh™)rŽ}rß(hjX-**How to test Keystone II serdes interface?**rąhkjµhohphqhœhs}rį(hu]hv]hw]hx]h{]uh}MDh~hh]rāh±)rć}rä(hjjąhs}rå(hu]hv]hw]hx]h{]uhkjŽh]ręhˆX)How to test Keystone II serdes interface?rē…rč}ré(hjUhkjćubahqh¹ubaubh™)rź}rė(hjXÉFor Keystone II Serdes, there is also a Serdes diagnostics package which can be found in the path pdk_k2hk/k2e_x_x_x\\packages\\ti\\diag\\serdes_diag. The tests run on C66x and cover BER, EYE and PRBS.hkjµhohphqhœhs}rģ(hu]hv]hw]hx]h{]uh}MFh~hh]rķhˆXÅFor Keystone II Serdes, there is also a Serdes diagnostics package which can be found in the path pdk_k2hk/k2e_x_x_x\packages\ti\diag\serdes_diag. The tests run on C66x and cover BER, EYE and PRBS.rī…rļ}rš(hjXÉFor Keystone II Serdes, there is also a Serdes diagnostics package which can be found in the path pdk_k2hk/k2e_x_x_x\\packages\\ti\\diag\\serdes_diag. The tests run on C66x and cover BER, EYE and PRBS.hkjźubaubh™)rń}rņ(hjX”For common Keystone I/II Serdes debug, please refer to `SERDES Link Commissioning on KeyStone I and II Devices `__"hkjµhohphqhœhs}ró(hu]hv]hw]hx]h{]uh}MIh~hh]rō(hˆX7For common Keystone I/II Serdes debug, please refer to rõ…rö}r÷(hjX7For common Keystone I/II Serdes debug, please refer to hkjńubh¢)rų}rł(hjXi`SERDES Link Commissioning on KeyStone I and II Devices `__hs}rś(UnameX6SERDES Link Commissioning on KeyStone I and II Devicesh¦X,http://www.ti.com/lit/an/sprac37/sprac37.pdfhx]hw]hu]hv]h{]uhkjńh]rūhˆX6SERDES Link Commissioning on KeyStone I and II Devicesrü…rż}rž(hjUhkjųubahqh«ubhˆX"…r’}r(hjX"hkjńubeubcdocutils.nodes block_quote r)r}r(hjUhkjµhohphqU block_quoterhs}r(hu]hv]hw]hx]h{]uh}Nh~hh]rjģ)r}r(hjUhs}r (hu]hv]hw]hx]h{]uhkjh]r jņ)r }r (hjUjõKhkjhohphqh}hs}r (hu]hv]hw]hx]h{]uh}Kh]ubahqjļubaubeubhohphqj8hs}r(hu]UlevelKhx]hw]Usourcehphv]h{]UlineMKUtypeUERRORruh}MJh~hh]rh™)r}r(hjXUnexpected indentation.hs}r(hu]hv]hw]hx]h{]uhkj³h]rhˆXUnexpected indentation.r…r}r(hjUhkjubahqhœubaubhg)r}r(hjUhkhl)r}r(hjUhkhl)r}r(hjUhkhhohphqhrhs}r(hu]hv]hw]hx]rUti-rtosr ah{]r!h:auh}Mhh~hh]r"(h)r#}r$(hjXTI RTOSr%hkjhohphqh…hs}r&(hu]hv]hw]hx]h{]uh}Mhh~hh]r'hˆXTI RTOSr(…r)}r*(hjj%hkj#ubaubjeubhohphqhrhs}r+(hu]hv]hw]hx]r,Uuseful-resourcesr-ah{]r.hWauh}Mkh~hh]r/(h)r0}r1(hjXUseful Resourcesr2hkjhohphqh…hs}r3(hu]hv]hw]hx]h{]uh}Mkh~hh]r4hˆXUseful Resourcesr5…r6}r7(hjj2hkj0ubaubhŚ)r8}r9(hjUhkjhohphqj hs}r:(hŽX-hx]hw]hu]hv]h{]uh}Mmh~hh]r;(hą)r<}r=(hjXG`SYSBIOS FAQ `__hkj8hohphqhõhs}r>(hu]hv]hw]hx]h{]uh}Nh~hh]r?h™)r@}rA(hjXG`SYSBIOS FAQ `__rBhkj<hohphqhœhs}rC(hu]hv]hw]hx]h{]uh}Mmh]rDh¢)rE}rF(hjjBhs}rG(UnameX SYSBIOS FAQh¦X5http://processors.wiki.ti.com/index.php/SYS/BIOS_FAQshx]hw]hu]hv]h{]uhkj@h]rHhˆX SYSBIOS FAQrI…rJ}rK(hjUhkjEubahqh«ubaubaubhą)rL}rM(hjX…`Processor_SDK_RTOS:_TI_RTOS_Tips_And_Tricks `__rNhkj8hohphqhõhs}rO(hu]hv]hw]hx]h{]uh}Nh~hh]rPh™)rQ}rR(hjjNhkjLhohphqhœhs}rS(hu]hv]hw]hx]h{]uh}Moh]rTh¢)rU}rV(hjjNhs}rW(UnameX+Processor_SDK_RTOS:_TI_RTOS_Tips_And_Tricksh¦XShttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS:_TI_RTOS_Tips_And_Trickshx]hw]hu]hv]h{]uhkjQh]rXhˆX+Processor_SDK_RTOS:_TI_RTOS_Tips_And_TricksrY…rZ}r[(hjUhkjUubahqh«ubaubaubhą)r\}r](hjXG`TI RTOS Worskshop `__hkj8hohphqhõhs}r^(hu]hv]hw]hx]h{]uh}Nh~hh]r_h™)r`}ra(hjXG`TI RTOS Worskshop `__rbhkj\hohphqhœhs}rc(hu]hv]hw]hx]h{]uh}Mph]rdh¢)re}rf(hjjbhs}rg(UnameXTI RTOS Worskshoph¦X/https://training.ti.com/ti-rtos-workshop-serieshx]hw]hu]hv]h{]uhkj`h]rhhˆXTI RTOS Worskshopri…rj}rk(hjUhkjeubahqh«ubaubaubhą)rl}rm(hjXf`SYS/BIOS_with_GCC_(CortexA) `__ hkj8hohphqhõhs}rn(hu]hv]hw]hx]h{]uh}Nh~hh]roh™)rp}rq(hjXe`SYS/BIOS_with_GCC_(CortexA) `__rrhkjlhohphqhœhs}rs(hu]hv]hw]hx]h{]uh}Mrh]rth¢)ru}rv(hjjrhs}rw(UnameXSYS/BIOS_with_GCC_(CortexA)h¦XChttp://processors.wiki.ti.com/index.php/SYS/BIOS_with_GCC_(CortexA)hx]hw]hu]hv]h{]uhkjph]rxhˆXSYS/BIOS_with_GCC_(CortexA)ry…rz}r{(hjUhkjuubahqh«ubaubaubeubjģ)r|}r}(hjUhkjhohphqjļhs}r~(hu]hv]hw]hx]h{]uh}Mth~hh]rjņ)r€}r(hjUjõKhkj|hohphqh}hs}r‚(hu]hv]hw]hx]h{]uh}Kh~hh]ubaubhŒ)rƒ}r„(hjXjHow do I start writing my TI RTOS application code? Is there any documentation that describes the process?r…hkjhohphqhhs}r†(hx]r‡Uhhow-do-i-start-writing-my-ti-rtos-application-code-is-there-any-documentation-that-describes-the-processrˆahw]hu]hv]h{]r‰h+auh}Nh~hh]rŠhˆXjHow do I start writing my TI RTOS application code? Is there any documentation that describes the process?r‹…rŒ}r(hjj…hkjƒubaubh™)rŽ}r(hjX‡The typical recommendation is to start a TI RTOS project using the predefined templates provided as part of CCS installation and then add custom configuration on top of it. CCS allows users to create a TI RTOS project with Minimum, Typical, and a set of generic examples, as you can see from wiki `Processor SDK RTOS TI RTOS Getting Started Examples `__.hkjhohphqhœhs}r(hu]hv]hw]hx]h{]uh}Myh~hh]r‘(hˆX)The typical recommendation is to start a TI RTOS project using the predefined templates provided as part of CCS installation and then add custom configuration on top of it. CCS allows users to create a TI RTOS project with Minimum, Typical, and a set of generic examples, as you can see from wiki r’…r“}r”(hjX)The typical recommendation is to start a TI RTOS project using the predefined templates provided as part of CCS installation and then add custom configuration on top of it. CCS allows users to create a TI RTOS project with Minimum, Typical, and a set of generic examples, as you can see from wiki hkjŽubh¢)r•}r–(hjX]`Processor SDK RTOS TI RTOS Getting Started Examples `__hs}r—(UnameX3Processor SDK RTOS TI RTOS Getting Started Examplesh¦X#Release_Specific.html#release-noteshx]hw]hu]hv]h{]uhkjŽh]r˜hˆX3Processor SDK RTOS TI RTOS Getting Started Examplesr™…rš}r›(hjUhkj•ubahqh«ubhˆX.…rœ}r(hjX.hkjŽubeubh™)rž}rŸ(hjXųOther than that, there is an TI RTOS workshop that addresses different features and use cases of TI RTOS with CCS: `Introduction to the TI-RTOS Kernel Workshop `__hkjhohphqhœhs}r (hu]hv]hw]hx]h{]uh}M€h~hh]r”(hˆXsOther than that, there is an TI RTOS workshop that addresses different features and use cases of TI RTOS with CCS: r¢…r£}r¤(hjXsOther than that, there is an TI RTOS workshop that addresses different features and use cases of TI RTOS with CCS: hkjžubh¢)r„}r¦(hjX…`Introduction to the TI-RTOS Kernel Workshop `__hs}r§(UnameX+Introduction to the TI-RTOS Kernel Workshoph¦XShttp://processors.wiki.ti.com/index.php/Introduction_to_the_TI-RTOS_Kernel_Workshophx]hw]hu]hv]h{]uhkjžh]rØhˆX+Introduction to the TI-RTOS Kernel Workshopr©…rŖ}r«(hjUhkj„ubahqh«ubeubh™)r¬}r­(hjX‡The TI RTOS component also ships with user documentation that provides information on configuring TI RTOS through scripts APIs and also using the graphical XGCONF tool. Full online API and module documentation is available here: `TI RTOS API Documentation `__hkjhohphqhœhs}r®(hu]hv]hw]hx]h{]uh}M…h~hh]rÆ(hˆXåThe TI RTOS component also ships with user documentation that provides information on configuring TI RTOS through scripts APIs and also using the graphical XGCONF tool. Full online API and module documentation is available here: r°…r±}r²(hjXåThe TI RTOS component also ships with user documentation that provides information on configuring TI RTOS through scripts APIs and also using the graphical XGCONF tool. Full online API and module documentation is available here: hkj¬ubh¢)r³}r“(hjX¢`TI RTOS API Documentation `__hs}rµ(UnameXTI RTOS API Documentationh¦X‚http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/sysbios/6_46_00_23/exports/bios_6_46_00_23/docs/cdoc/index.htmlhx]hw]hu]hv]h{]uhkj¬h]r¶hˆXTI RTOS API Documentationr·…rø}r¹(hjUhkj³ubahqh«ubeubhŒ)rŗ}r»(hjXJWhat interrupt latency, foot print, etc. can I expect while using TI RTOS?r¼hkjhohphqhhs}r½(hx]r¾UFwhat-interrupt-latency-foot-print-etc-can-i-expect-while-using-ti-rtosræahw]hu]hv]h{]rĄh8auh}Nh~hh]rĮhˆXJWhat interrupt latency, foot print, etc. can I expect while using TI RTOS?rĀ…rĆ}rÄ(hjj¼hkjŗubaubh™)rÅ}rĘ(hjXuPerformance and size benchmarks are available for every released SYS/BIOS kernel in the TI RTOS package and are shipped as part of the standard product documentation. In addition to the benchmark numbers themselves, .pdf files provide a detailed description of how the benchmarks were implemented. For example, whether they were implemented in internal or external memory..rĒhkjhohphqhœhs}rČ(hu]hv]hw]hx]h{]uh}Mh~hh]rÉhˆXuPerformance and size benchmarks are available for every released SYS/BIOS kernel in the TI RTOS package and are shipped as part of the standard product documentation. In addition to the benchmark numbers themselves, .pdf files provide a detailed description of how the benchmarks were implemented. For example, whether they were implemented in internal or external memory..rŹ…rĖ}rĢ(hjjĒhkjÅubaubh™)rĶ}rĪ(hjXŽIf you do not have access to a release, you can access the release notes (and thereby the benchmarks) online by clicking on the following link and going to the download link for the TI RTOS version that is part of the SDK.rĻhkjhohphqhœhs}rŠ(hu]hv]hw]hx]h{]uh}M–h~hh]rŃhˆXŽIf you do not have access to a release, you can access the release notes (and thereby the benchmarks) online by clicking on the following link and going to the download link for the TI RTOS version that is part of the SDK.rŅ…rÓ}rŌ(hjjĻhkjĶubaubhŚ)rÕ}rÖ(hjUhkjhohphqj hs}r×(hŽX-hx]hw]hu]hv]h{]uh}M›h~hh]rŲhą)rŁ}rŚ(hjXs`SYS/BIOS Releases `__ hkjÕhohphqhõhs}rŪ(hu]hv]hw]hx]h{]uh}Nh~hh]rÜh™)rŻ}rŽ(hjXr`SYS/BIOS Releases `__rßhkjŁhohphqhœhs}rą(hu]hv]hw]hx]h{]uh}M›h]rįh¢)rā}rć(hjjßhs}rä(UnameXSYS/BIOS Releasesh¦XZhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/bios/sysbios/index.htmlhx]hw]hu]hv]h{]uhkjŻh]råhˆXSYS/BIOS Releasesrꅁrē}rč(hjUhkjāubahqh«ubaubaubaubh™)ré}rź(hjXģThis link enables you to access any TI RTOS products and their associated release notes. The release notes may be browsed directly. There is no need to download the whole product. You will need to have a my.ti login to access this site.rėhkjhohphqhœhs}rģ(hu]hv]hw]hx]h{]uh}Mžh~hh]rķhˆXģThis link enables you to access any TI RTOS products and their associated release notes. The release notes may be browsed directly. There is no need to download the whole product. You will need to have a my.ti login to access this site.rī…rļ}rš(hjjėhkjéubaubh™)rń}rņ(hjX™Within the SDK package, TI-RTOS Benchmark Documentation can be found under directory path *bios_6_xx_xx_xx\\packages\\ti\\sysbios\\benchmarks\\doc-files*hkjhohphqhœhs}ró(hu]hv]hw]hx]h{]uh}M£h~hh]rō(hˆXZWithin the SDK package, TI-RTOS Benchmark Documentation can be found under directory path rõ…rö}r÷(hjXZWithin the SDK package, TI-RTOS Benchmark Documentation can be found under directory path hkjńubcdocutils.nodes emphasis rų)rł}rś(hjX?*bios_6_xx_xx_xx\\packages\\ti\\sysbios\\benchmarks\\doc-files*hs}rū(hu]hv]hw]hx]h{]uhkjńh]rühˆX8bios_6_xx_xx_xx\packages\ti\sysbios\benchmarks\doc-filesrż…rž}r’(hjUhkjłubahqUemphasisrubeubhŒ)r}r(hjX'How do I debug TI-RTOS and driver code?rhkjhohphqhhs}r(hx]rU&how-do-i-debug-ti-rtos-and-driver-coderahw]hu]hv]h{]rh$auh}Nh~hh]rhˆX'How do I debug TI-RTOS and driver code?r …r }r (hjjhkjubaubh™)r }r (hjX…In order to single step through code, the driver libraries and the TI RTOS libraries should be built with complete symbol definition.rhkjhohphqhœhs}r(hu]hv]hw]hx]h{]uh}MŖh~hh]rhˆX…In order to single step through code, the driver libraries and the TI RTOS libraries should be built with complete symbol definition.r…r}r(hjjhkj ubaubh™)r}r(hjXėFor building a debug-able version of TI RTOS, please refer to the following article: `Making_a_debug-able_Custom_SYSBIOS_Library `__hkjhohphqhœhs}r(hu]hv]hw]hx]h{]uh}M­h~hh]r(hˆXUFor building a debug-able version of TI RTOS, please refer to the following article: r…r}r(hjXUFor building a debug-able version of TI RTOS, please refer to the following article: hkjubh¢)r}r(hjX–`Making_a_debug-able_Custom_SYSBIOS_Library `__hs}r(UnameX*Making_a_debug-able_Custom_SYSBIOS_Libraryh¦Xehttp://processors.wiki.ti.com/index.php/SYS/BIOS_FAQs#1_Making_a_debug-able_Custom_SYS.2FBIOS_Libraryhx]hw]hu]hv]h{]uhkjh]rhˆX*Making_a_debug-able_Custom_SYSBIOS_Libraryr…r }r!(hjUhkjubahqh«ubeubh™)r"}r#(hjXProcessor SDK RTOS drivers are already built with full symbol definition. So you should be able to single step into the drivers in the CCS IDE environment. **Note**: You may need to add the source of the SYS/BIOS and the drivers in the source search path in CCS.hkjhohphqhœhs}r$(hu]hv]hw]hx]h{]uh}M±h~hh]r%(hˆXœProcessor SDK RTOS drivers are already built with full symbol definition. So you should be able to single step into the drivers in the CCS IDE environment. r&…r'}r((hjXœProcessor SDK RTOS drivers are already built with full symbol definition. So you should be able to single step into the drivers in the CCS IDE environment. hkj"ubh±)r)}r*(hjX**Note**hs}r+(hu]hv]hw]hx]h{]uhkj"h]r,hˆXNoter-…r.}r/(hjUhkj)ubahqh¹ubhˆXb: You may need to add the source of the SYS/BIOS and the drivers in the source search path in CCS.r0…r1}r2(hjXb: You may need to add the source of the SYS/BIOS and the drivers in the source search path in CCS.hkj"ubeubh™)r3}r4(hjXąAdvanced debug of TI RTOS applications using system analyzer and ROV object viewer is described in the `TI RTOS SYSTEM Anlayzer wiki `__.hkjhohphqhœhs}r5(hu]hv]hw]hx]h{]uh}M¶h~hh]r6(hˆXgAdvanced debug of TI RTOS applications using system analyzer and ROV object viewer is described in the r7…r8}r9(hjXgAdvanced debug of TI RTOS applications using system analyzer and ROV object viewer is described in the hkj3ubh¢)r:}r;(hjXx`TI RTOS SYSTEM Anlayzer wiki `__hs}r<(UnameXTI RTOS SYSTEM Anlayzer wikih¦XUhttp://processors.wiki.ti.com/index.php/How_is_SYS/BIOS_related_to_System_Analyzer%3Fhx]hw]hu]hv]h{]uhkj3h]r=hˆXTI RTOS SYSTEM Anlayzer wikir>…r?}r@(hjUhkj:ubahqh«ubhˆX.…rA}rB(hjX.hkj3ubeubjģ)rC}rD(hjUhkjhohphqjļhs}rE(hu]hv]hw]hx]h{]uh}Mŗh~hh]rFjņ)rG}rH(hjUjõKhkjChohphqh}hs}rI(hu]hv]hw]hx]h{]uh}Kh~hh]ubaubhŒ)rJ}rK(hjXFHow can I run TI RTOS on secondary ARM cores on multi-core ARM devicesrLhkjhohphqhhs}rM(hx]rNUFhow-can-i-run-ti-rtos-on-secondary-arm-cores-on-multi-core-arm-devicesrOahw]hu]hv]h{]rPh auh}Nh~hh]rQhˆXFHow can I run TI RTOS on secondary ARM cores on multi-core ARM devicesrR…rS}rT(hjjLhkjJubaubh™)rU}rV(hjX^Processor SDK RTOS supports multiple device that have multi-core ARM like AM572x and Keystone2 devices. In order to run TI RTOS application on the secondary ARM core in non-SMP mode, application developers need to add correct coreID to the configuration to their BIOS configuration to allow the hardware interrupts to be routed to the secondary core.rWhkjhohphqhœhs}rX(hu]hv]hw]hx]h{]uh}MĄh~hh]rYhˆX^Processor SDK RTOS supports multiple device that have multi-core ARM like AM572x and Keystone2 devices. In order to run TI RTOS application on the secondary ARM core in non-SMP mode, application developers need to add correct coreID to the configuration to their BIOS configuration to allow the hardware interrupts to be routed to the secondary core.rZ…r[}r\(hjjWhkjUubaubh™)r]}r^(hjXFor example on AM572x which has 2 A15 cores, to run the TI RTOS example on secondary ARM core, application users need to addĀ :r_hkjhohphqhœhs}r`(hu]hv]hw]hx]h{]uh}MĘh~hh]rahˆXFor example on AM572x which has 2 A15 cores, to run the TI RTOS example on secondary ARM core, application users need to addĀ :rb…rc}rd(hjj_hkj]ubaubjG)re}rf(hjXKvar Core = xdc.useModule('ti.sysbios.family.arm.ducati.Core'); Core.id = 1;hkjhohphqjJhs}rg(jLjMhx]hw]hu]hv]h{]uh}MĖh~hh]rhhˆXKvar Core = xdc.useModule('ti.sysbios.family.arm.ducati.Core'); Core.id = 1;ri…rj}rk(hjUhkjeubaubjģ)rl}rm(hjUhkjhohphqjļhs}rn(hu]hv]hw]hx]h{]uh}MĪh~hh]rojņ)rp}rq(hjUjõKhkjlhohphqh}hs}rr(hu]hv]hw]hx]h{]uh}Kh~hh]ubaubhŒ)rs}rt(hjX…Why do I get a "undefined reference to \`ti_sysbios_rts_gnu_ReentSupport_checkIfCorrectLibrary'" error when compiling my application?hkjhohphqhhs}ru(hx]rvUwhy-do-i-get-a-undefined-reference-to-ti-sysbios-rts-gnu-reentsupport-checkifcorrectlibrary-error-when-compiling-my-applicationrwahw]hu]hv]h{]rxhPauh}Nh~hh]ryhˆX„Why do I get a "undefined reference to `ti_sysbios_rts_gnu_ReentSupport_checkIfCorrectLibrary'" error when compiling my application?rz…r{}r|(hjX…Why do I get a "undefined reference to \`ti_sysbios_rts_gnu_ReentSupport_checkIfCorrectLibrary'" error when compiling my application?hkjsubaubh™)r}}r~(hjXJYou may have encountered this error when building an application for ARM using makefile and not using CCS. You will need to link in the proper C runtime library from SYS/BIOS. Double check the makefile(s) and make sure that you are using libc, libgcc, libm, etc. from the SYS/BIOS package and not from your toolchain (GCC Linaro).rhkjhohphqhœhs}r€(hu]hv]hw]hx]h{]uh}MÕh~hh]rhˆXJYou may have encountered this error when building an application for ARM using makefile and not using CCS. You will need to link in the proper C runtime library from SYS/BIOS. Double check the makefile(s) and make sure that you are using libc, libgcc, libm, etc. from the SYS/BIOS package and not from your toolchain (GCC Linaro).r‚…rƒ}r„(hjjhkj}ubaubh™)r…}r†(hjXpFor additional information, refer to: `What do I need to do to make the C runtime library re-entrant when building SYS/BIOS applications for Cortex-A GNU targets `__hkjhohphqhœhs}r‡(hu]hv]hw]hx]h{]uh}MŪh~hh]rˆ(hˆX&For additional information, refer to: r‰…rŠ}r‹(hjX&For additional information, refer to: hkj…ubh¢)rŒ}r(hjXJ`What do I need to do to make the C runtime library re-entrant when building SYS/BIOS applications for Cortex-A GNU targets `__hs}rŽ(UnameXzWhat do I need to do to make the C runtime library re-entrant when building SYS/BIOS applications for Cortex-A GNU targetsh¦XÉhttp://processors.wiki.ti.com/index.php/SYS/BIOS_with_GCC_(CortexA)#What_do_I_need_to_do_to_make_the_C_runtime_library_re-entrant_when_building_SYS.2FBIOS_applications_for_Cortex-A_GNU_targets.C2.A0.3Fhx]hw]hu]hv]h{]uhkj…h]rhˆXzWhat do I need to do to make the C runtime library re-entrant when building SYS/BIOS applications for Cortex-A GNU targetsr…r‘}r’(hjUhkjŒubahqh«ubeubhŒ)r“}r”(hjX-Where do I post questions on generic TI RTOS?r•hkjhohphqhhs}r–(hx]r—U,where-do-i-post-questions-on-generic-ti-rtosr˜ahw]hu]hv]h{]r™h auh}Nh~hh]ršhˆX-Where do I post questions on generic TI RTOS?r›…rœ}r(hjj•hkj“ubaubh™)rž}rŸ(hjXĪWe recommend that all TI RTOS users review the list of TI RTOS frequently asked questions on the `TI RTOS FAQ `__ page prior to posting the questions on the E2E forum. If the question is not specific to the Processor SDK RTOS drivers, but relates to configuration of a specific module inside TI RTOS, then please post the questions on the `TI RTOS E2E Forum `__.hkjhohphqhœhs}r (hu]hv]hw]hx]h{]uh}Mćh~hh]r”(hˆXaWe recommend that all TI RTOS users review the list of TI RTOS frequently asked questions on the r¢…r£}r¤(hjXaWe recommend that all TI RTOS users review the list of TI RTOS frequently asked questions on the hkjžubh¢)r„}r¦(hjXG`TI RTOS FAQ `__hs}r§(UnameX TI RTOS FAQh¦X5http://processors.wiki.ti.com/index.php/SYS/BIOS_FAQshx]hw]hu]hv]h{]uhkjžh]rØhˆX TI RTOS FAQr©…rŖ}r«(hjUhkj„ubahqh«ubhˆXā page prior to posting the questions on the E2E forum. If the question is not specific to the Processor SDK RTOS drivers, but relates to configuration of a specific module inside TI RTOS, then please post the questions on the r¬…r­}r®(hjXā page prior to posting the questions on the E2E forum. If the question is not specific to the Processor SDK RTOS drivers, but relates to configuration of a specific module inside TI RTOS, then please post the questions on the hkjžubh¢)rÆ}r°(hjXC`TI RTOS E2E Forum `__hs}r±(UnameXTI RTOS E2E Forumh¦X+https://e2e.ti.com/support/embedded/tirtos/hx]hw]hu]hv]h{]uhkjžh]r²hˆXTI RTOS E2E Forumr³…r“}rµ(hjUhkjÆubahqh«ubhˆX.…r¶}r·(hjX.hkjžubeubhŒ)rø}r¹(hjXjWhen load a RTOS example to DSP2, the code stuck at timer.c before go main(), but the same worked on DSP1?rŗhkjhohphqhhs}r»(hx]r¼Uewhen-load-a-rtos-example-to-dsp2-the-code-stuck-at-timer-c-before-go-main-but-the-same-worked-on-dsp1r½ahw]hu]hv]h{]r¾hMauh}Nh~hh]ræhˆXjWhen load a RTOS example to DSP2, the code stuck at timer.c before go main(), but the same worked on DSP1?rĄ…rĮ}rĀ(hjjŗhkjøubaubh™)rĆ}rÄ(hjXxBy default, BIOS uses GPtimer5 to source the clock ticks in the BIOS clock module. The GEL is created with the assumption that the DSP1 developers will use GPtimer5 and DSP2 users will use GPtimer6 to source clock module. This means that DSP2 developers will need to add configuration script to change the clock source to GPtimer6. Try to add the following in your DSP2.cfgĀ :rÅhkjhohphqhœhs}rĘ(hu]hv]hw]hx]h{]uh}Mļh~hh]rĒhˆXxBy default, BIOS uses GPtimer5 to source the clock ticks in the BIOS clock module. The GEL is created with the assumption that the DSP1 developers will use GPtimer5 and DSP2 users will use GPtimer6 to source clock module. This means that DSP2 developers will need to add configuration script to change the clock source to GPtimer6. Try to add the following in your DSP2.cfgĀ :rČ…rÉ}rŹ(hjjÅhkjĆubaubjG)rĖ}rĢ(hjXivar Clock = xdc.useModule('ti.sysbios.knl.Clock'); Clock.timerId = 5; /* Change BIOS clock to GPTimer6 */hkjhohphqjJhs}rĶ(jLjMhx]hw]hu]hv]h{]uh}Mųh~hh]rĪhˆXivar Clock = xdc.useModule('ti.sysbios.knl.Clock'); Clock.timerId = 5; /* Change BIOS clock to GPTimer6 */rĻ…rŠ}rŃ(hjUhkjĖubaubjģ)rŅ}rÓ(hjUhkjhohphqjļhs}rŌ(hu]hv]hw]hx]h{]uh}Mūh~hh]rÕjņ)rÖ}r×(hjUjõKhkjŅhohphqh}hs}rŲ(hu]hv]hw]hx]h{]uh}Kh~hh]ubaubeubhohphqj8hs}rŁ(hu]UlevelKhx]hw]Usourcehphv]h{]UlineMuUtypej:uh}Mth~hh]rŚh™)rŪ}rÜ(hjX%Line block ends without a blank line.hs}rŻ(hu]hv]hw]hx]h{]uhkjh]rŽhˆX%Line block ends without a blank line.rß…rą}rį(hjUhkjŪubahqhœubaubhg)rā}rć(hjUhkhl)rä}rå(hjUhkhl)rę}rē(hjUhkhhohphqhrhs}rč(hu]hv]hw]hx]réUc-build-verificationrźah{]rėh auh}MŌh~hh]rģ(h)rķ}rī(hjXC++ Build Verificationrļhkjęhohphqh…hs}rš(hu]hv]hw]hx]h{]uh}MŌh~hh]rńhˆXC++ Build Verificationrņ…ró}rō(hjjļhkjķubaubhŒ)rõ}rö(hjX&How do I verify C++ build environment?r÷hkjęhohphqhhs}rų(hx]rłU#how-do-i-verify-c-build-environmentrśahw]hu]hv]h{]rūhUauh}Nh~hh]rühˆX&How do I verify C++ build environment?rż…rž}r’(hjj÷hkjõubaubh™)r}r(hjX½Cpptest application verifies C++ Build environment on the Processor SDK package. It is located under the path $(PDK_INSTALL_PATH)/ti/osal/test This is a simple application with a print message. The application includes top level header files of all components in the PDK package and is built in C++ build environment. The header files are included dynamically for AM57xx and K2G platforms and statically included for AM335x and AM437x platforms.rhkjęhohphqhœhs}r(hu]hv]hw]hx]h{]uh}MŁh~hh]rhˆX½Cpptest application verifies C++ Build environment on the Processor SDK package. It is located under the path $(PDK_INSTALL_PATH)/ti/osal/test This is a simple application with a print message. The application includes top level header files of all components in the PDK package and is built in C++ build environment. The header files are included dynamically for AM57xx and K2G platforms and statically included for AM335x and AM437x platforms.r…r}r(hjjhkjubaubj)r}r (hjX.. _platform_supported:hkjęhohphqjhs}r (hx]hw]hu]hv]h{]Urefidr Uplatform-supportedr uh}Mąh~hh]ubhl)r }r(hjUhkjęhohpUexpect_referenced_by_namer}rh5jshqhrhs}r(hu]hv]hw]hx]r(Uplatforms-supportedrj eh{]r(h[h5euh}Mćh~hUexpect_referenced_by_idr}rj jsh]r(h)r}r(hjXPlatforms Supportedrhkj hohphqh…hs}r(hu]hv]hw]hx]h{]uh}Mćh~hh]rhˆXPlatforms Supportedr…r}r(hjjhkjubaubj°)r }r!(hjUhkj hohphqj³hs}r"(hu]hv]hw]hx]h{]uh}Nh~hh]r#j¶)r$}r%(hjUhs}r&(hx]hw]hu]hv]h{]UcolsKuhkj h]r'(j»)r(}r)(hjUhs}r*(hx]hw]hu]hv]h{]UcolwidthKuhkj$h]hqjæubj»)r+}r,(hjUhs}r-(hx]hw]hu]hv]h{]UcolwidthKuhkj$h]hqjæubj»)r.}r/(hjUhs}r0(hx]hw]hu]hv]h{]UcolwidthKuhkj$h]hqjæubj»)r1}r2(hjUhs}r3(hx]hw]hu]hv]h{]UcolwidthKuhkj$h]hqjæubj»)r4}r5(hjUhs}r6(hx]hw]hu]hv]h{]UcolwidthKuhkj$h]hqjæubj»)r7}r8(hjUhs}r9(hx]hw]hu]hv]h{]UcolwidthKuhkj$h]hqjæubj»)r:}r;(hjUhs}r<(hx]hw]hu]hv]h{]UcolwidthKuhkj$h]hqjæubjĆ)r=}r>(hjUhs}r?(hu]hv]hw]hx]h{]uhkj$h]r@(jČ)rA}rB(hjUhs}rC(hu]hv]hw]hx]h{]uhkj=h]rD(jĶ)rE}rF(hjUhs}rG(hx]hw]hu]hv]UmorerowsKh{]uhkjAh]rHh™)rI}rJ(hjXSOCrKhkjEhohphqhœhs}rL(hu]hv]hw]hx]h{]uh}Męh]rMhˆXSOCrN…rO}rP(hjjKhkjIubaubahqjŚubjĶ)rQ}rR(hjUhs}rS(hx]hw]hu]hv]UmorerowsKh{]uhkjAh]rTh™)rU}rV(hjX BOARD NAMESrWhkjQhohphqhœhs}rX(hu]hv]hw]hx]h{]uh}Męh]rYhˆX BOARD NAMESrZ…r[}r\(hjjWhkjUubaubahqjŚubjĶ)r]}r^(hjUhs}r_(hx]UmorecolsKhw]hu]hv]h{]uhkjAh]r`h™)ra}rb(hjXCORErchkj]hohphqhœhs}rd(hu]hv]hw]hx]h{]uh}Męh]rehˆXCORErf…rg}rh(hjjchkjaubaubahqjŚubehqjēubjČ)ri}rj(hjUhs}rk(hu]hv]hw]hx]h{]uhkj=h]rl(jĶ)rm}rn(hjUhs}ro(hu]hv]hw]hx]h{]uhkjih]rph™)rq}rr(hjXa8hostrshkjmhohphqhœhs}rt(hu]hv]hw]hx]h{]uh}Mčh]ruhˆXa8hostrv…rw}rx(hjjshkjqubaubahqjŚubjĶ)ry}rz(hjUhs}r{(hu]hv]hw]hx]h{]uhkjih]r|h™)r}}r~(hjXa9hostrhkjyhohphqhœhs}r€(hu]hv]hw]hx]h{]uh}Mčh]rhˆXa9hostr‚…rƒ}r„(hjjhkj}ubaubahqjŚubjĶ)r…}r†(hjUhs}r‡(hu]hv]hw]hx]h{]uhkjih]rˆh™)r‰}rŠ(hjXa15_0r‹hkj…hohphqhœhs}rŒ(hu]hv]hw]hx]h{]uh}Mčh]rhˆXa15_0rŽ…r}r(hjj‹hkj‰ubaubahqjŚubjĶ)r‘}r’(hjUhs}r“(hu]hv]hw]hx]h{]uhkjih]r”h™)r•}r–(hjXc66xr—hkj‘hohphqhœhs}r˜(hu]hv]hw]hx]h{]uh}Mčh]r™hˆXc66xrš…r›}rœ(hjj—hkj•ubaubahqjŚubjĶ)r}rž(hjUhs}rŸ(hu]hv]hw]hx]h{]uhkjih]r h™)r”}r¢(hjXipu1_0r£hkjhohphqhœhs}r¤(hu]hv]hw]hx]h{]uh}Mčh]r„hˆXipu1_0r¦…r§}rØ(hjj£hkj”ubaubahqjŚubehqjēubehqjčubjé)r©}rŖ(hjUhs}r«(hu]hv]hw]hx]h{]uhkj$h]r¬(jČ)r­}r®(hjUhs}rÆ(hu]hv]hw]hx]h{]uhkj©h]r°(jĶ)r±}r²(hjUhs}r³(hx]hw]hu]hv]UmorerowsKh{]uhkj­h]r“h™)rµ}r¶(hjXAM335xr·hkj±hohphqhœhs}rø(hu]hv]hw]hx]h{]uh}Mźh]r¹hˆXAM335xrŗ…r»}r¼(hjj·hkjµubaubahqjŚubjĶ)r½}r¾(hjUhs}ræ(hu]hv]hw]hx]h{]uhkj­h]rĄh™)rĮ}rĀ(hjX evmAM335xrĆhkj½hohphqhœhs}rÄ(hu]hv]hw]hx]h{]uh}Mźh]rÅhˆX evmAM335xrĘ…rĒ}rČ(hjjĆhkjĮubaubahqjŚubjĶ)rÉ}rŹ(hjUhs}rĖ(hu]hv]hw]hx]h{]uhkj­h]rĢh™)rĶ}rĪ(hjXXhkjÉhohphqhœhs}rĻ(hu]hv]hw]hx]h{]uh}Mźh]rŠhˆXX…rŃ}rŅ(hjXXhkjĶubaubahqjŚubjĶ)rÓ}rŌ(hjUhs}rÕ(hu]hv]hw]hx]h{]uhkj­h]hqjŚubjĶ)rÖ}r×(hjUhs}rŲ(hu]hv]hw]hx]h{]uhkj­h]hqjŚubjĶ)rŁ}rŚ(hjUhs}rŪ(hu]hv]hw]hx]h{]uhkj­h]hqjŚubjĶ)rÜ}rŻ(hjUhs}rŽ(hu]hv]hw]hx]h{]uhkj­h]hqjŚubehqjēubjČ)rß}rą(hjUhs}rį(hu]hv]hw]hx]h{]uhkj©h]rā(jĶ)rć}rä(hjUhs}rå(hu]hv]hw]hx]h{]uhkjßh]ręh™)rē}rč(hjX icev2AM335xréhkjćhohphqhœhs}rź(hu]hv]hw]hx]h{]uh}Mģh]rėhˆX icev2AM335xrģ…rķ}rī(hjjéhkjēubaubahqjŚubjĶ)rļ}rš(hjUhs}rń(hu]hv]hw]hx]h{]uhkjßh]rņh™)ró}rō(hjXXhkjļhohphqhœhs}rõ(hu]hv]hw]hx]h{]uh}Mģh]röhˆXX…r÷}rų(hjXXhkjóubaubahqjŚubjĶ)rł}rś(hjUhs}rū(hu]hv]hw]hx]h{]uhkjßh]hqjŚubjĶ)rü}rż(hjUhs}rž(hu]hv]hw]hx]h{]uhkjßh]hqjŚubjĶ)r’}r (hjUhs}r (hu]hv]hw]hx]h{]uhkjßh]hqjŚubjĶ)r }r (hjUhs}r (hu]hv]hw]hx]h{]uhkjßh]hqjŚubehqjēubjČ)r }r (hjUhs}r (hu]hv]hw]hx]h{]uhkj©h]r (jĶ)r }r (hjUhs}r (hu]hv]hw]hx]h{]uhkj h]r h™)r }r (hjX iceAMIC110r hkj hohphqhœhs}r (hu]hv]hw]hx]h{]uh}Mīh]r hˆX iceAMIC110r …r }r (hjj hkj ubaubahqjŚubjĶ)r }r (hjUhs}r (hu]hv]hw]hx]h{]uhkj h]r h™)r }r (hjXXhkj hohphqhœhs}r (hu]hv]hw]hx]h{]uh}Mīh]r hˆXX…r }r (hjXXhkj ubaubahqjŚubjĶ)r }r (hjUhs}r! (hu]hv]hw]hx]h{]uhkj h]hqjŚubjĶ)r" }r# (hjUhs}r$ (hu]hv]hw]hx]h{]uhkj h]hqjŚubjĶ)r% }r& (hjUhs}r' (hu]hv]hw]hx]h{]uhkj h]hqjŚubjĶ)r( }r) (hjUhs}r* (hu]hv]hw]hx]h{]uhkj h]hqjŚubehqjēubjČ)r+ }r, (hjUhs}r- (hu]hv]hw]hx]h{]uhkj©h]r. (jĶ)r/ }r0 (hjUhs}r1 (hu]hv]hw]hx]h{]uhkj+ h]r2 h™)r3 }r4 (hjXskAM335xr5 hkj/ hohphqhœhs}r6 (hu]hv]hw]hx]h{]uh}Mšh]r7 hˆXskAM335xr8 …r9 }r: (hjj5 hkj3 ubaubahqjŚubjĶ)r; }r< (hjUhs}r= (hu]hv]hw]hx]h{]uhkj+ h]r> h™)r? }r@ (hjXXhkj; hohphqhœhs}rA (hu]hv]hw]hx]h{]uh}Mšh]rB hˆXX…rC }rD (hjXXhkj? ubaubahqjŚubjĶ)rE }rF (hjUhs}rG (hu]hv]hw]hx]h{]uhkj+ h]hqjŚubjĶ)rH }rI (hjUhs}rJ (hu]hv]hw]hx]h{]uhkj+ h]hqjŚubjĶ)rK }rL (hjUhs}rM (hu]hv]hw]hx]h{]uhkj+ h]hqjŚubjĶ)rN }rO (hjUhs}rP (hu]hv]hw]hx]h{]uhkj+ h]hqjŚubehqjēubjČ)rQ }rR (hjUhs}rS (hu]hv]hw]hx]h{]uhkj©h]rT (jĶ)rU }rV (hjUhs}rW (hu]hv]hw]hx]h{]uhkjQ h]rX h™)rY }rZ (hjX bbbAM335xr[ hkjU hohphqhœhs}r\ (hu]hv]hw]hx]h{]uh}Mņh]r] hˆX bbbAM335xr^ …r_ }r` (hjj[ hkjY ubaubahqjŚubjĶ)ra }rb (hjUhs}rc (hu]hv]hw]hx]h{]uhkjQ h]rd h™)re }rf (hjXXhkja hohphqhœhs}rg (hu]hv]hw]hx]h{]uh}Mņh]rh hˆXX…ri }rj (hjXXhkje ubaubahqjŚubjĶ)rk }rl (hjUhs}rm (hu]hv]hw]hx]h{]uhkjQ h]hqjŚubjĶ)rn }ro (hjUhs}rp (hu]hv]hw]hx]h{]uhkjQ h]hqjŚubjĶ)rq }rr (hjUhs}rs (hu]hv]hw]hx]h{]uhkjQ h]hqjŚubjĶ)rt }ru (hjUhs}rv (hu]hv]hw]hx]h{]uhkjQ h]hqjŚubehqjēubjČ)rw }rx (hjUhs}ry (hu]hv]hw]hx]h{]uhkj©h]rz (jĶ)r{ }r| (hjUhs}r} (hx]hw]hu]hv]UmorerowsKh{]uhkjw h]r~ h™)r }r€ (hjXAM437xr hkj{ hohphqhœhs}r‚ (hu]hv]hw]hx]h{]uh}Mōh]rƒ hˆXAM437xr„ …r… }r† (hjj hkj ubaubahqjŚubjĶ)r‡ }rˆ (hjUhs}r‰ (hu]hv]hw]hx]h{]uhkjw h]rŠ h™)r‹ }rŒ (hjX evmAM437xr hkj‡ hohphqhœhs}rŽ (hu]hv]hw]hx]h{]uh}Mōh]r hˆX evmAM437xr …r‘ }r’ (hjj hkj‹ ubaubahqjŚubjĶ)r“ }r” (hjUhs}r• (hu]hv]hw]hx]h{]uhkjw h]hqjŚubjĶ)r– }r— (hjUhs}r˜ (hu]hv]hw]hx]h{]uhkjw h]r™ h™)rš }r› (hjXXhkj– hohphqhœhs}rœ (hu]hv]hw]hx]h{]uh}Mōh]r hˆXX…rž }rŸ (hjXXhkjš ubaubahqjŚubjĶ)r  }r” (hjUhs}r¢ (hu]hv]hw]hx]h{]uhkjw h]hqjŚubjĶ)r£ }r¤ (hjUhs}r„ (hu]hv]hw]hx]h{]uhkjw h]hqjŚubjĶ)r¦ }r§ (hjUhs}rØ (hu]hv]hw]hx]h{]uhkjw h]hqjŚubehqjēubjČ)r© }rŖ (hjUhs}r« (hu]hv]hw]hx]h{]uhkj©h]r¬ (jĶ)r­ }r® (hjUhs}rÆ (hu]hv]hw]hx]h{]uhkj© h]r° h™)r± }r² (hjX idkAM437xr³ hkj­ hohphqhœhs}r“ (hu]hv]hw]hx]h{]uh}Möh]rµ hˆX idkAM437xr¶ …r· }rø (hjj³ hkj± ubaubahqjŚubjĶ)r¹ }rŗ (hjUhs}r» (hu]hv]hw]hx]h{]uhkj© h]hqjŚubjĶ)r¼ }r½ (hjUhs}r¾ (hu]hv]hw]hx]h{]uhkj© h]ræ h™)rĄ }rĮ (hjXXhkj¼ hohphqhœhs}rĀ (hu]hv]hw]hx]h{]uh}Möh]rĆ hˆXX…rÄ }rÅ (hjXXhkjĄ ubaubahqjŚubjĶ)rĘ }rĒ (hjUhs}rČ (hu]hv]hw]hx]h{]uhkj© h]hqjŚubjĶ)rÉ }rŹ (hjUhs}rĖ (hu]hv]hw]hx]h{]uhkj© h]hqjŚubjĶ)rĢ }rĶ (hjUhs}rĪ (hu]hv]hw]hx]h{]uhkj© h]hqjŚubehqjēubjČ)rĻ }rŠ (hjUhs}rŃ (hu]hv]hw]hx]h{]uhkj©h]rŅ (jĶ)rÓ }rŌ (hjUhs}rÕ (hu]hv]hw]hx]h{]uhkjĻ h]rÖ h™)r× }rŲ (hjXskAM437xrŁ hkjÓ hohphqhœhs}rŚ (hu]hv]hw]hx]h{]uh}Mųh]rŪ hˆXskAM437xrÜ …rŻ }rŽ (hjjŁ hkj× ubaubahqjŚubjĶ)rß }rą (hjUhs}rį (hu]hv]hw]hx]h{]uhkjĻ h]hqjŚubjĶ)rā }rć (hjUhs}rä (hu]hv]hw]hx]h{]uhkjĻ h]rå h™)rę }rē (hjXXhkjā hohphqhœhs}rč (hu]hv]hw]hx]h{]uh}Mųh]ré hˆXX…rź }rė (hjXXhkję ubaubahqjŚubjĶ)rģ }rķ (hjUhs}rī (hu]hv]hw]hx]h{]uhkjĻ h]hqjŚubjĶ)rļ }rš (hjUhs}rń (hu]hv]hw]hx]h{]uhkjĻ h]hqjŚubjĶ)rņ }ró (hjUhs}rō (hu]hv]hw]hx]h{]uhkjĻ h]hqjŚubehqjēubjČ)rõ }rö (hjUhs}r÷ (hu]hv]hw]hx]h{]uhkj©h]rų (jĶ)rł }rś (hjUhs}rū (hx]hw]hu]hv]UmorerowsKh{]uhkjõ h]rü h™)rż }rž (hjXAM57xxr’ hkjł hohphqhœhs}r (hu]hv]hw]hx]h{]uh}Mśh]r hˆXAM57xxr …r }r (hjj’ hkjż ubaubahqjŚubjĶ)r }r (hjUhs}r (hu]hv]hw]hx]h{]uhkjõ h]r h™)r }r (hjX idkAM571xr hkj hohphqhœhs}r (hu]hv]hw]hx]h{]uh}Mśh]r hˆX idkAM571xr …r }r (hjj hkj ubaubahqjŚubjĶ)r }r (hjUhs}r (hu]hv]hw]hx]h{]uhkjõ h]hqjŚubjĶ)r }r (hjUhs}r (hu]hv]hw]hx]h{]uhkjõ h]hqjŚubjĶ)r }r (hjUhs}r (hu]hv]hw]hx]h{]uhkjõ h]r h™)r }r (hjXXhkj hohphqhœhs}r (hu]hv]hw]hx]h{]uh}Mśh]r hˆXX…r }r (hjXXhkj ubaubahqjŚubjĶ)r! }r" (hjUhs}r# (hu]hv]hw]hx]h{]uhkjõ h]r$ h™)r% }r& (hjXXhkj! hohphqhœhs}r' (hu]hv]hw]hx]h{]uh}Mśh]r( hˆXX…r) }r* (hjXXhkj% ubaubahqjŚubjĶ)r+ }r, (hjUhs}r- (hu]hv]hw]hx]h{]uhkjõ h]r. h™)r/ }r0 (hjXXhkj+ hohphqhœhs}r1 (hu]hv]hw]hx]h{]uh}Mśh]r2 hˆXX…r3 }r4 (hjXXhkj/ ubaubahqjŚubehqjēubjČ)r5 }r6 (hjUhs}r7 (hu]hv]hw]hx]h{]uhkj©h]r8 (jĶ)r9 }r: (hjUhs}r; (hu]hv]hw]hx]h{]uhkj5 h]r< h™)r= }r> (hjX idkAM572xr? hkj9 hohphqhœhs}r@ (hu]hv]hw]hx]h{]uh}Müh]rA hˆX idkAM572xrB …rC }rD (hjj? hkj= ubaubahqjŚubjĶ)rE }rF (hjUhs}rG (hu]hv]hw]hx]h{]uhkj5 h]hqjŚubjĶ)rH }rI (hjUhs}rJ (hu]hv]hw]hx]h{]uhkj5 h]hqjŚubjĶ)rK }rL (hjUhs}rM (hu]hv]hw]hx]h{]uhkj5 h]rN h™)rO }rP (hjXXhkjK hohphqhœhs}rQ (hu]hv]hw]hx]h{]uh}Müh]rR hˆXX…rS }rT (hjXXhkjO ubaubahqjŚubjĶ)rU }rV (hjUhs}rW (hu]hv]hw]hx]h{]uhkj5 h]rX h™)rY }rZ (hjXXhkjU hohphqhœhs}r[ (hu]hv]hw]hx]h{]uh}Müh]r\ hˆXX…r] }r^ (hjXXhkjY ubaubahqjŚubjĶ)r_ }r` (hjUhs}ra (hu]hv]hw]hx]h{]uhkj5 h]rb h™)rc }rd (hjXXhkj_ hohphqhœhs}re (hu]hv]hw]hx]h{]uh}Müh]rf hˆXX…rg }rh (hjXXhkjc ubaubahqjŚubehqjēubjČ)ri }rj (hjUhs}rk (hu]hv]hw]hx]h{]uhkj©h]rl (jĶ)rm }rn (hjUhs}ro (hu]hv]hw]hx]h{]uhkji h]rp h™)rq }rr (hjX idkAM574xrs hkjm hohphqhœhs}rt (hu]hv]hw]hx]h{]uh}Mžh]ru hˆX idkAM574xrv …rw }rx (hjjs hkjq ubaubahqjŚubjĶ)ry }rz (hjUhs}r{ (hu]hv]hw]hx]h{]uhkji h]hqjŚubjĶ)r| }r} (hjUhs}r~ (hu]hv]hw]hx]h{]uhkji h]hqjŚubjĶ)r }r€ (hjUhs}r (hu]hv]hw]hx]h{]uhkji h]r‚ h™)rƒ }r„ (hjXXhkj hohphqhœhs}r… (hu]hv]hw]hx]h{]uh}Mžh]r† hˆXX…r‡ }rˆ (hjXXhkjƒ ubaubahqjŚubjĶ)r‰ }rŠ (hjUhs}r‹ (hu]hv]hw]hx]h{]uhkji h]rŒ h™)r }rŽ (hjXXhkj‰ hohphqhœhs}r (hu]hv]hw]hx]h{]uh}Mžh]r hˆXX…r‘ }r’ (hjXXhkj ubaubahqjŚubjĶ)r“ }r” (hjUhs}r• (hu]hv]hw]hx]h{]uhkji h]r– h™)r— }r˜ (hjXXhkj“ hohphqhœhs}r™ (hu]hv]hw]hx]h{]uh}Mžh]rš hˆXX…r› }rœ (hjXXhkj— ubaubahqjŚubehqjēubjČ)r }rž (hjUhs}rŸ (hu]hv]hw]hx]h{]uhkj©h]r  (jĶ)r” }r¢ (hjUhs}r£ (hu]hv]hw]hx]h{]uhkj h]r¤ h™)r„ }r¦ (hjX evmAM572xr§ hkj” hohphqhœhs}rØ (hu]hv]hw]hx]h{]uh}Mh]r© hˆX evmAM572xrŖ …r« }r¬ (hjj§ hkj„ ubaubahqjŚubjĶ)r­ }r® (hjUhs}rÆ (hu]hv]hw]hx]h{]uhkj h]hqjŚubjĶ)r° }r± (hjUhs}r² (hu]hv]hw]hx]h{]uhkj h]hqjŚubjĶ)r³ }r“ (hjUhs}rµ (hu]hv]hw]hx]h{]uhkj h]r¶ h™)r· }rø (hjXXhkj³ hohphqhœhs}r¹ (hu]hv]hw]hx]h{]uh}Mh]rŗ hˆXX…r» }r¼ (hjXXhkj· ubaubahqjŚubjĶ)r½ }r¾ (hjUhs}ræ (hu]hv]hw]hx]h{]uhkj h]rĄ h™)rĮ }rĀ (hjXXhkj½ hohphqhœhs}rĆ (hu]hv]hw]hx]h{]uh}Mh]rÄ hˆXX…rÅ }rĘ (hjXXhkjĮ ubaubahqjŚubjĶ)rĒ }rČ (hjUhs}rÉ (hu]hv]hw]hx]h{]uhkj h]rŹ h™)rĖ }rĢ (hjXXhkjĒ hohphqhœhs}rĶ (hu]hv]hw]hx]h{]uh}Mh]rĪ hˆXX…rĻ }rŠ (hjXXhkjĖ ubaubahqjŚubehqjēubjČ)rŃ }rŅ (hjUhs}rÓ (hu]hv]hw]hx]h{]uhkj©h]rŌ (jĶ)rÕ }rÖ (hjUhs}r× (hx]hw]hu]hv]UmorerowsKh{]uhkjŃ h]rŲ h™)rŁ }rŚ (hjXK2GrŪ hkjÕ hohphqhœhs}rÜ (hu]hv]hw]hx]h{]uh}Mh]rŻ hˆXK2GrŽ …rß }rą (hjjŪ hkjŁ ubaubahqjŚubjĶ)rį }rā (hjUhs}rć (hu]hv]hw]hx]h{]uhkjŃ h]rä h™)rå }rę (hjXevmK2Grē hkjį hohphqhœhs}rč (hu]hv]hw]hx]h{]uh}Mh]ré hˆXevmK2Grź …rė }rģ (hjjē hkjå ubaubahqjŚubjĶ)rķ }rī (hjUhs}rļ (hu]hv]hw]hx]h{]uhkjŃ h]hqjŚubjĶ)rš }rń (hjUhs}rņ (hu]hv]hw]hx]h{]uhkjŃ h]hqjŚubjĶ)ró }rō (hjUhs}rõ (hu]hv]hw]hx]h{]uhkjŃ h]rö h™)r÷ }rų (hjXXhkjó hohphqhœhs}rł (hu]hv]hw]hx]h{]uh}Mh]rś hˆXX…rū }rü (hjXXhkj÷ ubaubahqjŚubjĶ)rż }rž (hjUhs}r’ (hu]hv]hw]hx]h{]uhkjŃ h]r h™)r }r (hjXXhkjż hohphqhœhs}r (hu]hv]hw]hx]h{]uh}Mh]r hˆXX…r }r (hjXXhkj ubaubahqjŚubjĶ)r }r (hjUhs}r (hu]hv]hw]hx]h{]uhkjŃ h]hqjŚubehqjēubjČ)r }r (hjUhs}r (hu]hv]hw]hx]h{]uhkj©h]r (jĶ)r }r (hjUhs}r (hu]hv]hw]hx]h{]uhkj h]r h™)r }r (hjXiceK2Gr hkj hohphqhœhs}r (hu]hv]hw]hx]h{]uh}Mh]r hˆXiceK2Gr …r }r (hjj hkj ubaubahqjŚubjĶ)r }r (hjUhs}r (hu]hv]hw]hx]h{]uhkj h]hqjŚubjĶ)r }r (hjUhs}r (hu]hv]hw]hx]h{]uhkj h]hqjŚubjĶ)r }r! (hjUhs}r" (hu]hv]hw]hx]h{]uhkj h]r# h™)r$ }r% (hjXXhkj hohphqhœhs}r& (hu]hv]hw]hx]h{]uh}Mh]r' hˆXX…r( }r) (hjXXhkj$ ubaubahqjŚubjĶ)r* }r+ (hjUhs}r, (hu]hv]hw]hx]h{]uhkj h]r- h™)r. }r/ (hjXXhkj* hohphqhœhs}r0 (hu]hv]hw]hx]h{]uh}Mh]r1 hˆXX…r2 }r3 (hjXXhkj. ubaubahqjŚubjĶ)r4 }r5 (hjUhs}r6 (hu]hv]hw]hx]h{]uhkj h]hqjŚubehqjēubehqj‡ubehqjˆubaubh™)r7 }r8 (hjXwhere,r9 hkj hohphqhœhs}r: (hu]hv]hw]hx]h{]uh}Mh~hh]r; hˆXwhere,r< …r= }r> (hjj9 hkj7 ubaubh™)r? }r@ (hjX X - supportedrA hkj hohphqhœhs}rB (hu]hv]hw]hx]h{]uh}M h~hh]rC hˆX X - supportedrD …rE }rF (hjjA hkj? ubaubeubhl)rG }rH (hjUhkjęhohphqhrhs}rI (hu]hv]hw]hx]rJ U build-setuprK ah{]rL hZauh}M h~hh]rM (h)rN }rO (hjX Build SetuprP hkjG hohphqh…hs}rQ (hu]hv]hw]hx]h{]uh}M h~hh]rR hˆX Build SetuprS …rT }rU (hjjP hkjN ubaubhŚ)rV }rW (hjUhkjG hohphqj hs}rX (hŽX-hx]hw]hu]hv]h{]uh}M h~hh]rY (hą)rZ }r[ (hjXˆFor Windows : Download and install `Strawberry Perl `__.r\ hkjV hohphqhõhs}r] (hu]hv]hw]hx]h{]uh}Nh~hh]r^ h™)r_ }r` (hjj\ hkjZ hohphqhœhs}ra (hu]hv]hw]hx]h{]uh}M h]rb (hˆX#For Windows : Download and install rc …rd }re (hjX#For Windows : Download and install hkj_ ubh¢)rf }rg (hjXd`Strawberry Perl `__hs}rh (UnameXStrawberry Perlh¦XNhttp://strawberryperl.com/download/5.28.0.1/strawberry-perl-5.28.0.1-64bit.msihx]hw]hu]hv]h{]uhkj_ h]ri hˆXStrawberry Perlrj …rk }rl (hjUhkjf ubahqh«ubhˆX.…rm }rn (hjX.hkj_ ubeubaubhą)ro }rp (hjX\For Linux : Execute the command "sudo apt-get -y install perl" at the linux command prompt. hkjV hohphqhõhs}rq (hu]hv]hw]hx]h{]uh}Nh~hh]rr h™)rs }rt (hjX[For Linux : Execute the command "sudo apt-get -y install perl" at the linux command prompt.ru hkjo hohphqhœhs}rv (hu]hv]hw]hx]h{]uh}Mh]rw hˆX[For Linux : Execute the command "sudo apt-get -y install perl" at the linux command prompt.rx …ry }rz (hjju hkjs ubaubaubeubhĢ)r{ }r| (hjXJThis is an one-time installation and need not be repeated for every build.r} hkjG hohphqhĻhs}r~ (hu]hv]hw]hx]h{]uh}Nh~hh]r h™)r€ }r (hjj} hkj{ hohphqhœhs}r‚ (hu]hv]hw]hx]h{]uh}Mh]rƒ hˆXJThis is an one-time installation and need not be repeated for every build.r„ …r… }r† (hjj} hkj€ ubaubaubeubjähl)r‡ }rˆ (hjUhkjęhohphqhrhs}r‰ (hu]hv]hw]hx]rŠ Urunning-the-applicationr‹ ah{]rŒ hauh}MJh~hh]r (h)rŽ }r (hjXRunning the Applicationr hkj‡ hohphqh…hs}r‘ (hu]hv]hw]hx]h{]uh}MJh~hh]r’ hˆXRunning the Applicationr“ …r” }r• (hjj hkjŽ ubaubcdocutils.nodes enumerated_list r– )r— }r˜ (hjUhkj‡ hohphqUenumerated_listr™ hs}rš (Usuffixr› U.hx]hw]hu]Uprefixrœ Uhv]h{]Uenumtyper Uarabicrž uh}MKh~hh]rŸ (hą)r  }r” (hjX3Launch CCS and and switch to the Debug Perspective.r¢ hkj— hohphqhõhs}r£ (hu]hv]hw]hx]h{]uh}Nh~hh]r¤ h™)r„ }r¦ (hjj¢ hkj  hohphqhœhs}r§ (hu]hv]hw]hx]h{]uh}MKh]rØ hˆX3Launch CCS and and switch to the Debug Perspective.r© …rŖ }r« (hjj¢ hkj„ ubaubaubhą)r¬ }r­ (hjX:Launch the Target configuration and connect to the target.r® hkj— hohphqhõhs}rÆ (hu]hv]hw]hx]h{]uh}Nh~hh]r° h™)r± }r² (hjj® hkj¬ hohphqhœhs}r³ (hu]hv]hw]hx]h{]uh}MLh]r“ hˆX:Launch the Target configuration and connect to the target.rµ …r¶ }r· (hjj® hkj± ubaubaubhą)rø }r¹ (hjXÜLoad the binaries to the selected core using Run->Load->Load Program.If you need help in CCS setup, refer section `Setup CCS `__ explaining this further.hkj— hohphqhõhs}rŗ (hu]hv]hw]hx]h{]uh}Nh~hh]r» h™)r¼ }r½ (hjXÜLoad the binaries to the selected core using Run->Load->Load Program.If you need help in CCS setup, refer section `Setup CCS `__ explaining this further.hkjø hohphqhœhs}r¾ (hu]hv]hw]hx]h{]uh}MMh]ræ (hˆXrLoad the binaries to the selected core using Run->Load->Load Program.If you need help in CCS setup, refer section rĄ …rĮ }rĀ (hjXrLoad the binaries to the selected core using Run->Load->Load Program.If you need help in CCS setup, refer section hkj¼ ubh¢)rĆ }rÄ (hjXQ`Setup CCS `__hs}rÅ (UnameX Setup CCSh¦XAindex_how_to_guides.html#setup-ccs-for-evm-and-processor-sdk-rtoshx]hw]hu]hv]h{]uhkj¼ h]rĘ hˆX Setup CCSrĒ …rČ }rÉ (hjUhkjĆ ubahqh«ubhˆX explaining this further.rŹ …rĖ }rĢ (hjX explaining this further.hkj¼ ubeubaubhą)rĶ }rĪ (hjXELaunch the serial console utility with the following configurations: hkj— hohphqhõhs}rĻ (hu]hv]hw]hx]h{]uh}Nh~hh]rŠ h™)rŃ }rŅ (hjXDLaunch the serial console utility with the following configurations:rÓ hkjĶ hohphqhœhs}rŌ (hu]hv]hw]hx]h{]uh}MPh]rÕ hˆXDLaunch the serial console utility with the following configurations:rÖ …r× }rŲ (hjjÓ hkjŃ ubaubaubeubhŚ)rŁ }rŚ (hjUhkj‡ hohphqj hs}rŪ (hŽX*hx]hw]hu]hv]h{]uh}MRh~hh]rÜ (hą)rŻ }rŽ (hjXBaud Rate: 115200 hkjŁ hohphqhõhs}rß (hu]hv]hw]hx]h{]uh}Nh~hh]rą h™)rį }rā (hjXBaud Rate: 115200rć hkjŻ hohphqhœhs}rä (hu]hv]hw]hx]h{]uh}MRh]rå hˆXBaud Rate: 115200rę …rē }rč (hjjć hkjį ubaubaubhą)ré }rź (hjXData : 8 bits hkjŁ hohphqhõhs}rė (hu]hv]hw]hx]h{]uh}Nh~hh]rģ h™)rķ }rī (hjX Data : 8 bitsrļ hkjé hohphqhœhs}rš (hu]hv]hw]hx]h{]uh}MTh]rń hˆX Data : 8 bitsrņ …ró }rō (hjjļ hkjķ ubaubaubhą)rõ }rö (hjXParity : None hkjŁ hohphqhõhs}r÷ (hu]hv]hw]hx]h{]uh}Nh~hh]rų h™)rł }rś (hjX Parity : Nonerū hkjõ hohphqhœhs}rü (hu]hv]hw]hx]h{]uh}MVh]rż hˆX Parity : Nonerž …r’ }r (hjjū hkjł ubaubaubhą)r }r (hjX Stop : 1 bit hkjŁ hohphqhõhs}r (hu]hv]hw]hx]h{]uh}Nh~hh]r h™)r }r (hjX Stop : 1 bitr hkj hohphqhœhs}r (hu]hv]hw]hx]h{]uh}MXh]r hˆX Stop : 1 bitr …r }r (hjj hkj ubaubaubhą)r }r (hjXFlow Control : None hkjŁ hohphqhõhs}r (hu]hv]hw]hx]h{]uh}Nh~hh]r h™)r }r (hjXFlow Control : Noner hkj hohphqhœhs}r (hu]hv]hw]hx]h{]uh}MZh]r hˆXFlow Control : Noner …r }r (hjj hkj ubaubaubeubh™)r }r (hjX>Verified utilities are Teraterm (Windows) and Minicom (Linux).r hkj‡ hohphqhœhs}r (hu]hv]hw]hx]h{]uh}M\h~hh]r hˆX>Verified utilities are Teraterm (Windows) and Minicom (Linux).r …r }r (hjj hkj ubaubj– )r! }r" (hjUhkj‡ hohphqj™ hs}r# (j› U.Ustartr$ Khx]hw]hu]jœ Uhv]h{]j jž uh}M^h~hh]r% hą)r& }r' (hjXMRun the program in CCS and check for the below output on the serial console: hkj! hohphqhõhs}r( (hu]hv]hw]hx]h{]uh}Nh~hh]r) h™)r* }r+ (hjXLRun the program in CCS and check for the below output on the serial console:r, hkj& hohphqhœhs}r- (hu]hv]hw]hx]h{]uh}M^h]r. hˆXLRun the program in CCS and check for the below output on the serial console:r/ …r0 }r1 (hjj, hkj* ubaubaubaubjG)r2 }r3 (hjXC++ Build Successful!hkj‡ hohphqjJhs}r4 (jLjMhx]hw]hu]hv]h{]uh}Mbh~hh]r5 hˆXC++ Build Successful!r6 …r7 }r8 (hjUhkj2 ubaubeubeubhohphqhrhs}r9 (hu]hv]hw]hx]r: Usteps-to-buildr; ah{]r< hauh}Mh~hh]r= (h)r> }r? (hjXSteps to Buildr@ hkjähohphqh…hs}rA (hu]hv]hw]hx]h{]uh}Mh~hh]rB hˆXSteps to BuildrC …rD }rE (hjj@ hkj> ubaubh™)rF }rG (hjXFThe following are the steps to build and test the Cpptest Application.rH hkjähohphqhœhs}rI (hu]hv]hw]hx]h{]uh}Mh~hh]rJ hˆXFThe following are the steps to build and test the Cpptest Application.rK …rL }rM (hjjH hkjF ubaubj– )rN }rO (hjUhkjähohphqj™ hs}rP (j› U.hx]hw]hu]jœ Uhv]h{]j jž uh}Mh~hh]rQ hą)rR }rS (hjXBuild the PDK package hkjN hohphqhõhs}rT (hu]hv]hw]hx]h{]uh}Nh~hh]rU h™)rV }rW (hjXBuild the PDK packagerX hkjR hohphqhœhs}rY (hu]hv]hw]hx]h{]uh}Mh]rZ hˆXBuild the PDK packager[ …r\ }r] (hjjX hkjV ubaubaubaubhĢ)r^ }r_ (hjX]Building PDK package completely is neccessary before invoking a build on Cpptest application.hkjähohphqhĻhs}r` (hu]hv]hw]hx]h{]uh}Nh~hh]ra h™)rb }rc (hjX]Building PDK package completely is neccessary before invoking a build on Cpptest application.rd hkj^ hohphqhœhs}re (hu]hv]hw]hx]h{]uh}Mh]rf hˆX]Building PDK package completely is neccessary before invoking a build on Cpptest application.rg …rh }ri (hjjd hkjb ubaubaubhŚ)rj }rk (hjUhkjähohphqj hs}rl (hŽX-hx]hw]hu]hv]h{]uh}M!h~hh]rm hą)rn }ro (hjX For Windows:rp hkjj hohphqhõhs}rq (hu]hv]hw]hx]h{]uh}Nh~hh]rr h™)rs }rt (hjjp hkjn hohphqhœhs}ru (hu]hv]hw]hx]h{]uh}M!h]rv hˆX For Windows:rw …rx }ry (hjjp hkjs ubaubaubaubjG)rz }r{ (hjX0cd $(PDK_INSTALL_PATH) pdksetupenv.bat gmake allhkjähohphqjJhs}r| (jLjMhx]hw]hu]hv]h{]uh}M$h~hh]r} hˆX0cd $(PDK_INSTALL_PATH) pdksetupenv.bat gmake allr~ …r }r€ (hjUhkjz ubaubhŚ)r }r‚ (hjUhkjähohphqj hs}rƒ (hŽX-hx]hw]hu]hv]h{]uh}M)h~hh]r„ hą)r… }r† (hjX For Linux:r‡ hkj hohphqhõhs}rˆ (hu]hv]hw]hx]h{]uh}Nh~hh]r‰ h™)rŠ }r‹ (hjj‡ hkj… hohphqhœhs}rŒ (hu]hv]hw]hx]h{]uh}M)h]r hˆX For Linux:rŽ …r }r (hjj‡ hkjŠ ubaubaubaubjG)r‘ }r’ (hjX5cd $(PDK_INSTALL_PATH) source pdksetupenv.sh make allhkjähohphqjJhs}r“ (jLjMhx]hw]hu]hv]h{]uh}M,h~hh]r” hˆX5cd $(PDK_INSTALL_PATH) source pdksetupenv.sh make allr• …r– }r— (hjUhkj‘ ubaubj– )r˜ }r™ (hjUhkjähohphqj™ hs}rš (j› U.j$ Khx]hw]hu]jœ Uhv]h{]j jž uh}M1h~hh]r› hą)rœ }r (hjXDInvoke the Cpptest application build, using the following commands. hkj˜ hohphqhõhs}rž (hu]hv]hw]hx]h{]uh}Nh~hh]rŸ h™)r  }r” (hjXCInvoke the Cpptest application build, using the following commands.r¢ hkjœ hohphqhœhs}r£ (hu]hv]hw]hx]h{]uh}M1h]r¤ hˆXCInvoke the Cpptest application build, using the following commands.r„ …r¦ }r§ (hjj¢ hkj  ubaubaubaubhŚ)rØ }r© (hjUhkjähohphqj hs}rŖ (hŽX-hx]hw]hu]hv]h{]uh}M3h~hh]r« hą)r¬ }r­ (hjX For Windows:r® hkjØ hohphqhõhs}rÆ (hu]hv]hw]hx]h{]uh}Nh~hh]r° h™)r± }r² (hjj® hkj¬ hohphqhœhs}r³ (hu]hv]hw]hx]h{]uh}M3h]r“ hˆX For Windows:rµ …r¶ }r· (hjj® hkj± ubaubaubaubjG)rø }r¹ (hjXcd ti/osal/test/cpptest gmake BOARD= CORE= CPLUSPLUS_BUILD=yes Example: gmake BOARD=idkAM572x CORE=a15_0 CPLUSPLUS_BUILD=yeshkjähohphqjJhs}rŗ (jLjMhx]hw]hu]hv]h{]uh}M6h~hh]r» hˆXcd ti/osal/test/cpptest gmake BOARD= CORE= CPLUSPLUS_BUILD=yes Example: gmake BOARD=idkAM572x CORE=a15_0 CPLUSPLUS_BUILD=yesr¼ …r½ }r¾ (hjUhkjø ubaubhŚ)ræ }rĄ (hjUhkjähohphqj hs}rĮ (hŽX-hx]hw]hu]hv]h{]uh}M;h~hh]rĀ hą)rĆ }rÄ (hjX For Linux:rÅ hkjæ hohphqhõhs}rĘ (hu]hv]hw]hx]h{]uh}Nh~hh]rĒ h™)rČ }rÉ (hjjÅ hkjĆ hohphqhœhs}rŹ (hu]hv]hw]hx]h{]uh}M;h]rĖ hˆX For Linux:rĢ …rĶ }rĪ (hjjÅ hkjČ ubaubaubaubjG)rĻ }rŠ (hjXŽcd ti/osal/test/cpptest make BOARD= CORE= CPLUSPLUS_BUILD=yes Example: make BOARD=idkAM572x CORE=a15_0 CPLUSPLUS_BUILD=yeshkjähohphqjJhs}rŃ (jLjMhx]hw]hu]hv]h{]uh}M>h~hh]rŅ hˆXŽcd ti/osal/test/cpptest make BOARD= CORE= CPLUSPLUS_BUILD=yes Example: make BOARD=idkAM572x CORE=a15_0 CPLUSPLUS_BUILD=yesrÓ …rŌ }rÕ (hjUhkjĻ ubaubh™)rÖ }r× (hjXERefer section :ref:`platform_supported` for the BOARD and CORE names.rŲ hkjähohphqhœhs}rŁ (hu]hv]hw]hx]h{]uh}MDh~hh]rŚ (hˆXRefer section rŪ …rÜ }rŻ (hjXRefer section hkjÖ ubj0)rŽ }rß (hjX:ref:`platform_supported`rą hkjÖ hohphqj4hs}rį (UreftypeXrefj6ˆj7Xplatform_supportedU refdomainXstdrā hx]hw]U refexplicit‰hu]hv]h{]j9j:uh}MDh]rć j<)rä }rå (hjją hs}rę (hu]hv]rē (jAjā Xstd-refrč ehw]hx]h{]uhkjŽ h]ré hˆXplatform_supportedrź …rė }rģ (hjUhkjä ubahqjGubaubhˆX for the BOARD and CORE names.rķ …rī }rļ (hjX for the BOARD and CORE names.hkjÖ ubeubj– )rš }rń (hjUhkjähohphqj™ hs}rņ (j› U.j$ Khx]hw]hu]jœ Uhv]h{]j jž uh}MFh~hh]ró hą)rō }rõ (hjXyUpon successful build, the application binaries are created under $(PDK_INSTALL_PATH)/ti/binary/cpptest/bin/ hkjš hohphqhõhs}rö (hu]hv]hw]hx]h{]uh}Nh~hh]r÷ h™)rų }rł (hjXxUpon successful build, the application binaries are created under $(PDK_INSTALL_PATH)/ti/binary/cpptest/bin/rś hkjō hohphqhœhs}rū (hu]hv]hw]hx]h{]uh}MFh]rü hˆXxUpon successful build, the application binaries are created under $(PDK_INSTALL_PATH)/ti/binary/cpptest/bin/rż …rž }r’ (hjjś hkjų ubaubaubaubeubhohphqj8hs}r (hu]UlevelKhx]hw]Usourcehphv]h{]UlineM"Utypej:uh}M!h~hh]r h™)r }r (hjX;Bullet list ends without a blank line; unexpected unindent.hs}r (hu]hv]hw]hx]h{]uhkjāh]r hˆX;Bullet list ends without a blank line; unexpected unindent.r …r }r (hjUhkj ubahqhœubaubhg)r }r (hjUhkjähohphqj8hs}r (hu]UlevelKhx]hw]Usourcehphv]h{]UlineM*Utypej:uh}M)h~hh]r h™)r }r (hjX;Bullet list ends without a blank line; unexpected unindent.hs}r (hu]hv]hw]hx]h{]uhkj h]r hˆX;Bullet list ends without a blank line; unexpected unindent.r …r }r (hjUhkj ubahqhœubaubhg)r }r (hjUhkjähohphqj8hs}r (hu]UlevelKhx]hw]Usourcehphv]h{]UlineMŌUtypeUINFOr uh}M1h~hh]r h™)r }r (hjX:Enumerated list start value not ordinal-1: "2" (ordinal 2)hs}r (hu]hv]hw]hx]h{]uhkj h]r hˆX:Enumerated list start value not ordinal-1: "2" (ordinal 2)r …r }r (hjUhkj ubahqhœubaubhg)r }r! (hjUhkjähohphqj8hs}r" (hu]UlevelKhx]hw]Usourcehphv]h{]UlineM4Utypej:uh}M3h~hh]r# h™)r$ }r% (hjX;Bullet list ends without a blank line; unexpected unindent.hs}r& (hu]hv]hw]hx]h{]uhkj h]r' hˆX;Bullet list ends without a blank line; unexpected unindent.r( …r) }r* (hjUhkj$ ubahqhœubaubhg)r+ }r, (hjUhkjähohphqj8hs}r- (hu]UlevelKhx]hw]Usourcehphv]h{]UlineM<Utypej:uh}M;h~hh]r. h™)r/ }r0 (hjX;Bullet list ends without a blank line; unexpected unindent.hs}r1 (hu]hv]hw]hx]h{]uhkj+ h]r2 hˆX;Bullet list ends without a blank line; unexpected unindent.r3 …r4 }r5 (hjUhkj/ ubahqhœubaubhg)r6 }r7 (hjUhkjähohphqj8hs}r8 (hu]UlevelKhx]hw]Usourcehphv]h{]UlineMŌUtypej uh}MFh~hh]r9 h™)r: }r; (hjX:Enumerated list start value not ordinal-1: "3" (ordinal 3)hs}r< (hu]hv]hw]hx]h{]uhkj6 h]r= hˆX:Enumerated list start value not ordinal-1: "3" (ordinal 3)r> …r? }r@ (hjUhkj: ubahqhœubaubhg)rA }rB (hjUhkj‡ hohphqj8hs}rC (hu]UlevelKhx]hw]Usourcehphv]h{]UlineMŌUtypej uh}M^h~hh]rD h™)rE }rF (hjX:Enumerated list start value not ordinal-1: "5" (ordinal 5)hs}rG (hu]hv]hw]hx]h{]uhkjA h]rH hˆX:Enumerated list start value not ordinal-1: "5" (ordinal 5)rI …rJ }rK (hjUhkjE ubahqhœubaubhg)rL }rM (hjUhkj‡ hohphqj8hs}rN (hu]UlevelKhx]hw]Usourcehphv]h{]UlineMfUtypejuh}Mfh~hh]rO (h™)rP }rQ (hjX;Content block expected for the "raw" directive; none found.hs}rR (hu]hv]hw]hx]h{]uhkjL h]rS hˆX;Content block expected for the "raw" directive; none found.rT …rU }rV (hjUhkjP ubahqhœubjG)rW }rX (hjX .. raw:: htmlrY hs}rZ (jLjMhx]hw]hu]hv]h{]uhkjL h]r[ hˆX .. raw:: htmlr\ …r] }r^ (hjUhkjW ubahqjJubeubeUcurrent_sourcer_ NU decorationr` NUautofootnote_startra KUnameidsrb }rc (hjhUgeneral-supportrd hU0what-documentation-exists-for-processor-sdk-rtosre h j9h jźh jüh jOh j˜hUwwhat-is-the-difference-between-soc-specific-driver-library-and-the-soc-independent-generic-core-specific-driver-libraryrf hjhU#where-can-i-locate-ipc-faq-documentrg hU-how-do-i-resolve-edma-instance-usage-conflictrh hj«hU edma-libraryri hj‰hU^why-did-i-encounter-a-build-issue-while-rebuilding-dsplib-imglib-or-mathlib-with-c6000-cgt-8-xrj hU?processor-sdk-rtos-porting-guide-for-am571x-am570x-speed-gradesrk hU%mcsdk-to-processor-sdk-rtos-migrationrl hUKcan-i-use-ndk-software-stack-on-all-devices-supported-in-processor-sdk-rtosrm hhæhUGhow-do-i-find-out-if-a-driver-is-supported-in-the-package-for-my-devicern hU release-notesro hUnetworking-supportrp hj‹ hj#hj; h jÉh!Uchip-support-library-cslrq h"jRh#jāh$jh%UZdoes-processor-sdk-rtos-release-support-all-device-part-numbers-in-supported-device-familyrr h&Udsp-optimized-librariesrs h'jh(Uqin-a-ti-sgmii-to-fpga-phy-port-connection-data-corruption-is-observed-on-egress-direction-what-could-be-the-causert h)U4are-there-any-bare-metal-examples-in-the-pdk-packageru h*Uawhy-does-the-performance-of-the-dsp-libraries-not-match-with-the-performance-in-the-documentationrv h+jˆh,UZhow-to-create-arm-baremetal-ccs-project-that-link-to-pdk-driver-libraries-using-gnu-linkerrw h-jh.U#how-do-i-build-and-run-ipc-examplesrx h/UFhow-do-i-find-out-which-csl-header-and-source-files-apply-to-my-devicery h0U•what-filesystem-support-if-provided-by-processor-sdk-rtos-can-i-use-ubifs-ramfs-or-fatfs-with-ti-rtos-when-using-external-non-volatile-memory-devicesrz h1j h2U!inter-processor-communication-ipcr{ h3Ulis-processor-sdk-rtos-replacing-mcsdk-how-do-i-migrate-from-mcsdk-to-processor-sdk-rtos-for-keystone-devicesr| h4j…h5j h6Uis-there-any-training-content-available-for-processor-sdk-rtosr‚ h>jTh?U)ccs-7-1-platform-cant-be-verified-warningrƒ h@UGwhy-my-sd-card-stopped-booting-with-the-latest-processor-sdk-bootloaderr„ hAUMi-am-a-current-sitara-starterware-user-should-i-migrate-to-processor-sdk-rtosr… hBjnhCUgcan-i-read-core-specific-registers-on-multi-core-devices-supported-in-processor-sdk-rtos-using-csl-coder† hDUdevice-driversr‡ hEjbhFj!hGhzhHUZhow-do-i-program-the-phy-through-mdio-interface-i-find-that-ti-init-mdio-function-is-emptyrˆ hIU@what-are-the-advantages-of-using-the-processor-sdk-rtos-softwarer‰ hJURhow-to-setup-sgmii-interface-to-a-phy-or-to-another-sgmii-port-without-using-a-phyrŠ hKj<hLjShMj½hNU3where-do-i-find-the-documentation-for-the-ndk-stackr‹ hOjŹhPjwhQU4how-can-i-run-ti-rtos-ipc-examples-on-am57xx-devicesrŒ hRUsecondary-bootloaderr hSUtraining-and-documentationrŽ hTjhUjśhVU6what-is-the-system-memory-map-used-by-the-sdk-examplesr hWj-hXh“hYUChow-do-i-make-a-feature-request-or-file-bugs-for-processor-sdk-rtosr hZjK h[jh\Ujwhat-board-initialization-is-required-in-the-application-after-booting-using-the-secondary-boot-loader-sblr‘ h]jh^UVhow-do-i-know-the-list-of-known-issues-and-bugs-resolved-in-processor-sdk-rtos-releaser’ h_U„when-i-use-ccs-7-1-for-processor-sdk-rtos-4-0-projects-i-saw-a-warning-platform-name-ti-platforms-xxxxxx-could-not-be-verified-your-project-may-not-build-as-expectedr“ h`U4where-can-i-find-example-projects-for-device-driversr” haj¹hbjduh]r• (cdocutils.nodes comment r– )r— }r˜ (hjX>http://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_FAQhkhhohphqUcommentr™ hs}rš (jLjMhx]hw]hu]hv]h{]uh}Kh~hh]r› hˆX>http://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_FAQrœ …r }rž (hjUhkj— ubaubhl)rŸ }r  (hjUhkhhohphqhrhs}r” (hu]hv]hw]hx]r¢ jd ah{]r£ hauh}Kh~hh]r¤ (h)r„ }r¦ (hjXGeneral Supportr§ hkjŸ hohphqh…hs}rØ (hu]hv]hw]hx]h{]uh}Kh~hh]r© hˆXGeneral SupportrŖ …r« }r¬ (hjj§ hkj„ ubaubhŒ)r­ }r® (hjXFWhat are the main advantages of using the Processor SDK RTOS software?rÆ hkjŸ hohphqhhs}r° (hx]r± j‰ ahw]hu]hv]h{]r² hIauh}Nh~hh]r³ hˆXFWhat are the main advantages of using the Processor SDK RTOS software?r“ …rµ }r¶ (hjjÆ hkj­ ubaubh™)r· }rø (hjXmHere are some key features of the Processor SDK RTOS that maximize software reuse for application developers:r¹ hkjŸ hohphqhœhs}rŗ (hu]hv]hw]hx]h{]uh}K h~hh]r» hˆXmHere are some key features of the Processor SDK RTOS that maximize software reuse for application developers:r¼ …r½ }r¾ (hjj¹ hkj· ubaubhŚ)ræ }rĄ (hjUhkjŸ hohphqj hs}rĮ (hŽX-hx]hw]hu]hv]h{]uh}K h~hh]rĀ (hą)rĆ }rÄ (hjX)**Common API Interface**: Processor SDK RTOS software is designed to maximize application software reuse and reduce the time to market for end application developers. It provides a unified approach to software by maintaining a common API interface in low-level drivers, inter-processor communication (IPC) drivers, and optimized libraries across all supported platforms. The API interface also enables ease of migration for TI MCU customers moving to TI ARM or DSP platforms by maintaining the same API interface for common IPs like SPI, I2C, UART,etc. hkjæ hohphqhõhs}rÅ (hu]hv]hw]hx]h{]uh}Nh~hh]rĘ h™)rĒ }rČ (hjX(**Common API Interface**: Processor SDK RTOS software is designed to maximize application software reuse and reduce the time to market for end application developers. It provides a unified approach to software by maintaining a common API interface in low-level drivers, inter-processor communication (IPC) drivers, and optimized libraries across all supported platforms. The API interface also enables ease of migration for TI MCU customers moving to TI ARM or DSP platforms by maintaining the same API interface for common IPs like SPI, I2C, UART,etc.hkjĆ hohphqhœhs}rÉ (hu]hv]hw]hx]h{]uh}K h]rŹ (h±)rĖ }rĢ (hjX**Common API Interface**hs}rĶ (hu]hv]hw]hx]h{]uhkjĒ h]rĪ hˆXCommon API InterfacerĻ …rŠ }rŃ (hjUhkjĖ ubahqh¹ubhˆX: Processor SDK RTOS software is designed to maximize application software reuse and reduce the time to market for end application developers. It provides a unified approach to software by maintaining a common API interface in low-level drivers, inter-processor communication (IPC) drivers, and optimized libraries across all supported platforms. The API interface also enables ease of migration for TI MCU customers moving to TI ARM or DSP platforms by maintaining the same API interface for common IPs like SPI, I2C, UART,etc.rŅ …rÓ }rŌ (hjX: Processor SDK RTOS software is designed to maximize application software reuse and reduce the time to market for end application developers. It provides a unified approach to software by maintaining a common API interface in low-level drivers, inter-processor communication (IPC) drivers, and optimized libraries across all supported platforms. The API interface also enables ease of migration for TI MCU customers moving to TI ARM or DSP platforms by maintaining the same API interface for common IPs like SPI, I2C, UART,etc.hkjĒ ubeubaubhą)rÕ }rÖ (hjXX**Ease of Migration to Custom Platform**: Processor SDK RTOS consolidates all board-specific software into a single software component referred to as the "board library". All of the other components rely on this board library to configure the underlying hardware. Migration to a custom platform requires only modification of the board library. hkjæ hohphqhõhs}r× (hu]hv]hw]hx]h{]uh}Nh~hh]rŲ h™)rŁ }rŚ (hjXW**Ease of Migration to Custom Platform**: Processor SDK RTOS consolidates all board-specific software into a single software component referred to as the "board library". All of the other components rely on this board library to configure the underlying hardware. Migration to a custom platform requires only modification of the board library.hkjÕ hohphqhœhs}rŪ (hu]hv]hw]hx]h{]uh}Kh]rÜ (h±)rŻ }rŽ (hjX(**Ease of Migration to Custom Platform**hs}rß (hu]hv]hw]hx]h{]uhkjŁ h]rą hˆX$Ease of Migration to Custom Platformrį …rā }rć (hjUhkjŻ ubahqh¹ubhˆX/: Processor SDK RTOS consolidates all board-specific software into a single software component referred to as the "board library". All of the other components rely on this board library to configure the underlying hardware. Migration to a custom platform requires only modification of the board library.rä …rå }rę (hjX/: Processor SDK RTOS consolidates all board-specific software into a single software component referred to as the "board library". All of the other components rely on this board library to configure the underlying hardware. Migration to a custom platform requires only modification of the board library.hkjŁ ubeubaubhą)rē }rč (hjXø**Integrated Board Diagnostic Software**: The board diagnostic software included in the SDK allows for quick validation of the board functionality using bare-metal (no-OS) unit tests. hkjæ hohphqhõhs}ré (hu]hv]hw]hx]h{]uh}Nh~hh]rź h™)rė }rģ (hjX·**Integrated Board Diagnostic Software**: The board diagnostic software included in the SDK allows for quick validation of the board functionality using bare-metal (no-OS) unit tests.hkjē hohphqhœhs}rķ (hu]hv]hw]hx]h{]uh}Kh]rī (h±)rļ }rš (hjX(**Integrated Board Diagnostic Software**hs}rń (hu]hv]hw]hx]h{]uhkjė h]rņ hˆX$Integrated Board Diagnostic Softwareró …rō }rõ (hjUhkjļ ubahqh¹ubhˆX: The board diagnostic software included in the SDK allows for quick validation of the board functionality using bare-metal (no-OS) unit tests.rö …r÷ }rų (hjX: The board diagnostic software included in the SDK allows for quick validation of the board functionality using bare-metal (no-OS) unit tests.hkjė ubeubaubhą)rł }rś (hjXh**Reduces Need to Relearn TI Software**: All future software releases for TI SoC platforms will use this software methodology and will maintain the common API interface for a given peripheral. Application developers who have already developed their software on one of TI`s Processors using Processor SDK will not need to re-learn working with the TI software. hkjæ hohphqhõhs}rū (hu]hv]hw]hx]h{]uh}Nh~hh]rü h™)rż }rž (hjXg**Reduces Need to Relearn TI Software**: All future software releases for TI SoC platforms will use this software methodology and will maintain the common API interface for a given peripheral. Application developers who have already developed their software on one of TI`s Processors using Processor SDK will not need to re-learn working with the TI software.hkjł hohphqhœhs}r’ (hu]hv]hw]hx]h{]uh}K"h]r(h±)r}r(hjX'**Reduces Need to Relearn TI Software**hs}r(hu]hv]hw]hx]h{]uhkjż h]rhˆX#Reduces Need to Relearn TI Softwarer…r}r(hjUhkjubahqh¹ubhˆX@: All future software releases for TI SoC platforms will use this software methodology and will maintain the common API interface for a given peripheral. Application developers who have already developed their software on one of TI`s Processors using Processor SDK will not need to re-learn working with the TI software.r…r }r (hjX@: All future software releases for TI SoC platforms will use this software methodology and will maintain the common API interface for a given peripheral. Application developers who have already developed their software on one of TI`s Processors using Processor SDK will not need to re-learn working with the TI software.hkjż ubeubaubhą)r }r (hjXP**Feature Addition and Reduced Software Costs**: Due to the ease of migration of baseline software across platforms, developers can spend more time customizing their application and add more features to enhance it. This also helps to reduce the duration of the application development cycle and helps reduce software development costs. hkjæ hohphqhõhs}r (hu]hv]hw]hx]h{]uh}Nh~hh]rh™)r}r(hjXO**Feature Addition and Reduced Software Costs**: Due to the ease of migration of baseline software across platforms, developers can spend more time customizing their application and add more features to enhance it. This also helps to reduce the duration of the application development cycle and helps reduce software development costs.hkj hohphqhœhs}r(hu]hv]hw]hx]h{]uh}K)h]r(h±)r}r(hjX/**Feature Addition and Reduced Software Costs**hs}r(hu]hv]hw]hx]h{]uhkjh]rhˆX+Feature Addition and Reduced Software Costsr…r}r(hjUhkjubahqh¹ubhˆX : Due to the ease of migration of baseline software across platforms, developers can spend more time customizing their application and add more features to enhance it. This also helps to reduce the duration of the application development cycle and helps reduce software development costs.r…r}r(hjX : Due to the ease of migration of baseline software across platforms, developers can spend more time customizing their application and add more features to enhance it. This also helps to reduce the duration of the application development cycle and helps reduce software development costs.hkjubeubaubhą)r}r(hjX**Quarterly Software Updates**: Processor SDK RTOS is updated every three months with bug fixes, new features, and new platform support. Users can subscribe to updates by using the "Alert Me" button for the package from the software download page on ti.com. hkjæ hohphqhõhs}r(hu]hv]hw]hx]h{]uh}Nh~hh]r h™)r!}r"(hjX**Quarterly Software Updates**: Processor SDK RTOS is updated every three months with bug fixes, new features, and new platform support. Users can subscribe to updates by using the "Alert Me" button for the package from the software download page on ti.com.hkjhohphqhœhs}r#(hu]hv]hw]hx]h{]uh}K/h]r$(h±)r%}r&(hjX**Quarterly Software Updates**hs}r'(hu]hv]hw]hx]h{]uhkj!h]r(hˆXQuarterly Software Updatesr)…r*}r+(hjUhkj%ubahqh¹ubhˆXć: Processor SDK RTOS is updated every three months with bug fixes, new features, and new platform support. Users can subscribe to updates by using the "Alert Me" button for the package from the software download page on ti.com.r,…r-}r.(hjXć: Processor SDK RTOS is updated every three months with bug fixes, new features, and new platform support. Users can subscribe to updates by using the "Alert Me" button for the package from the software download page on ti.com.hkj!ubeubaubeubhĢ)r/}r0(hjXTIf you are unable to locate the "Alert Me" option, please check the screenshot here:hkjŸ hohphqhĻhs}r1(hu]hv]hw]hx]h{]uh}Nh~hh]r2h™)r3}r4(hjXTIf you are unable to locate the "Alert Me" option, please check the screenshot here:r5hkj/hohphqhœhs}r6(hu]hv]hw]hx]h{]uh}K5h]r7hˆXTIf you are unable to locate the "Alert Me" option, please check the screenshot here:r8…r9}r:(hjj5hkj3ubaubaubcdocutils.nodes image r;)r<}r=(hjX".. Image:: ../images/Alert_Me.png hkjŸ hohphqUimager>hs}r?(UuriXrtos/../images/Alert_Me.pngr@hx]hw]hu]hv]U candidatesrA}rBU*j@sh{]uh}K9h~hh]ubjģ)rC}rD(hjUhkjŸ hohphqjļhs}rE(hu]hv]hw]hx]h{]uh}K:h~hh]rFjņ)rG}rH(hjUjõKhkjChohphqh}hs}rI(hu]hv]hw]hx]h{]uh}Kh~hh]ubaubhŒ)rJ}rK(hjXDHow do I make a feature request or file bugs for Processor SDK RTOS?rLhkjŸ hohphqhhs}rM(hx]rNj ahw]hu]hv]h{]rOhYauh}Nh~hh]rPhˆXDHow do I make a feature request or file bugs for Processor SDK RTOS?rQ…rR}rS(hjjLhkjJubaubh™)rT}rU(hjXXTI E2E device-specific forums can be used to report a bug or a feature addition request:rVhkjŸ hohphqhœhs}rW(hu]hv]hw]hx]h{]uh}K@h~hh]rXhˆXXTI E2E device-specific forums can be used to report a bug or a feature addition request:rY…rZ}r[(hjjVhkjTubaubhŚ)r\}r](hjUhkjŸ hohphqj hs}r^(hŽX-hx]hw]hu]hv]h{]uh}KCh~hh]r_hą)r`}ra(hjXA`E2E Processor Support `_ for the version of the SDK you wish to use.hkjŸ hohphqhœhs}r(hu]hv]hw]hx]h{]uh}KIh~hh]r‚(hˆXXThe information on known issues and bug fixes in Processor SDK RTOS can be found in the rƒ…r„}r…(hjXXThe information on known issues and bug fixes in Processor SDK RTOS can be found in the hkjubh¢)r†}r‡(hjX6`Release Notes `_hs}rˆ(UnameX Release Notesh¦X#Release_Specific.html#release-notesr‰hx]hw]hu]hv]h{]uhkjh]rŠhˆX Release Notesr‹…rŒ}r(hjUhkj†ubahqh«ubj)rŽ}r(hjX& jKhkjhqjhs}r(Urefurij‰hx]r‘jo ahw]hu]hv]h{]r’hauh]ubhˆX, for the version of the SDK you wish to use.r“…r”}r•(hjX, for the version of the SDK you wish to use.hkjubeubhŒ)r–}r—(hjXOI am a current Sitara Starterware user. Should I migrate to Processor SDK RTOS?r˜hkjŸ hohphqhhs}r™(hx]ršj… ahw]hu]hv]h{]r›hAauh}Nh~hh]rœhˆXOI am a current Sitara Starterware user. Should I migrate to Processor SDK RTOS?r…rž}rŸ(hjj˜hkj–ubaubh™)r }r”(hjX±Starterware software is no longer active and will not have any further releases. Existing starterware users should refer the following article to determine the migration path: `Processor SDK RTOS Migration Guide Wiki `__. For all new development, we recommend that users start with the Processor SDK RTOS, which is currently under active development and provides periodic updates and bug fixes.hkjŸ hohphqhœhs}r¢(hu]hv]hw]hx]h{]uh}KQh~hh]r£(hˆX°Starterware software is no longer active and will not have any further releases. Existing starterware users should refer the following article to determine the migration path: r¤…r„}r¦(hjX°Starterware software is no longer active and will not have any further releases. Existing starterware users should refer the following article to determine the migration path: hkj ubh¢)r§}rØ(hjXS`Processor SDK RTOS Migration Guide Wiki `__hs}r©(UnameX'Processor SDK RTOS Migration Guide Wikih¦X%Release_Specific.html#migration-guidehx]hw]hu]hv]h{]uhkj h]rŖhˆX'Processor SDK RTOS Migration Guide Wikir«…r¬}r­(hjUhkj§ubahqh«ubhˆX®. For all new development, we recommend that users start with the Processor SDK RTOS, which is currently under active development and provides periodic updates and bug fixes.r®…rÆ}r°(hjX®. For all new development, we recommend that users start with the Processor SDK RTOS, which is currently under active development and provides periodic updates and bug fixes.hkj ubeubhŒ)r±}r²(hjXnIs Processor SDK RTOS replacing MCSDK? How do I migrate from MCSDK to Processor SDK RTOS for KeyStone devices?r³hkjŸ hohphqhhs}r“(hx]rµj| ahw]hu]hv]h{]r¶h3auh}Nh~hh]r·hˆXnIs Processor SDK RTOS replacing MCSDK? How do I migrate from MCSDK to Processor SDK RTOS for KeyStone devices?rø…r¹}rŗ(hjj³hkj±ubaubh™)r»}r¼(hjXęYes. We recommend that for all new development, users should use Processor SDK RTOS for application development. For existing users, the Processor SDK RTOS provides an easy migration path for existing MCSDK 3.x (K2X) and MCSDK 2.x (C66xx) developers to move their application to the new software package. For complete details please refer to the wiki `MCSDK to Processor SDK RTOS Migration `_.hkjŸ hohphqhœhs}r½(hu]hv]hw]hx]h{]uh}K]h~hh]r¾(hˆX_Yes. We recommend that for all new development, users should use Processor SDK RTOS for application development. For existing users, the Processor SDK RTOS provides an easy migration path for existing MCSDK 3.x (K2X) and MCSDK 2.x (C66xx) developers to move their application to the new software package. For complete details please refer to the wiki r慁rĄ}rĮ(hjX_Yes. We recommend that for all new development, users should use Processor SDK RTOS for application development. For existing users, the Processor SDK RTOS provides an easy migration path for existing MCSDK 3.x (K2X) and MCSDK 2.x (C66xx) developers to move their application to the new software package. For complete details please refer to the wiki hkj»ubh¢)rĀ}rĆ(hjX†`MCSDK to Processor SDK RTOS Migration `_hs}rÄ(UnameX%MCSDK to Processor SDK RTOS Migrationh¦X[http://processors.wiki.ti.com/index.php/MCSDK_to_Processor_SDK_Migration#Processor_SDK_RTOSrÅhx]hw]hu]hv]h{]uhkj»h]rĘhˆX%MCSDK to Processor SDK RTOS MigrationrĒ…rČ}rÉ(hjUhkjĀubahqh«ubj)rŹ}rĖ(hjX^ jKhkj»hqjhs}rĢ(UrefurijÅhx]rĶjl ahw]hu]hv]h{]rĪhauh]ubhˆX.…rĻ}rŠ(hjX.hkj»ubeubhŒ)rŃ}rŅ(hjX8How do I download earlier version of Processor SDK RTOS?rÓhkjŸ hohphqhhs}rŌ(hx]rÕj ahw]hu]hv]h{]rÖh9auh}Nh~hh]r×hˆX8How do I download earlier version of Processor SDK RTOS?rŲ…rŁ}rŚ(hjjÓhkjŃubaubh™)rŪ}rÜ(hjXĒThe download page for every Processor SDK RTOS release contains links to the previous release. Users can revert back to earlier releases using this link provided under the section "Previous Release."rŻhkjŸ hohphqhœhs}rŽ(hu]hv]hw]hx]h{]uh}Khh~hh]rßhˆXĒThe download page for every Processor SDK RTOS release contains links to the previous release. Users can revert back to earlier releases using this link provided under the section "Previous Release."rą…rį}rā(hjjŻhkjŪubaubhŒ)rć}rä(hjX[Does processor SDK RTOS release support all device part numbers in supported device family?råhkjŸ hohphqhhs}rę(hx]rējr ahw]hu]hv]h{]rčh%auh}Nh~hh]réhˆX[Does processor SDK RTOS release support all device part numbers in supported device family?rź…rė}rģ(hjjåhkjćubaubh™)rķ}rī(hjXĶProcessor SDK RTOS software is tested and validated on TI evaluation platforms that generally includes the superset part in the device family however, the software components like CSL, LLD drivers and RTOS are applicable on reduced feature set variant of the devices. Most of the code in the Processor SDK RTOS for multi-core devices is independent of how many cores exists on the device as they provide baseline platform software that can be run from any core.rļhkjŸ hohphqhœhs}rš(hu]hv]hw]hx]h{]uh}Koh~hh]rńhˆXĶProcessor SDK RTOS software is tested and validated on TI evaluation platforms that generally includes the superset part in the device family however, the software components like CSL, LLD drivers and RTOS are applicable on reduced feature set variant of the devices. Most of the code in the Processor SDK RTOS for multi-core devices is independent of how many cores exists on the device as they provide baseline platform software that can be run from any core.rņ…ró}rō(hjjļhkjķubaubh™)rõ}rö(hjXÉIt is the users responsibility to modify components that deploy tasks/software on slave cores like OpenMP, OpenCL, IPC and MultiProc Manager so that they use the feature set that is available on their device. In most cases software documentation will provide guidance on updating the software package however this should not be considered a comprehensive list of software components to be updated to run the software on a reduced feature set device variant.r÷hkjŸ hohphqhœhs}rų(hu]hv]hw]hx]h{]uh}Kth~hh]rłhˆXÉIt is the users responsibility to modify components that deploy tasks/software on slave cores like OpenMP, OpenCL, IPC and MultiProc Manager so that they use the feature set that is available on their device. In most cases software documentation will provide guidance on updating the software package however this should not be considered a comprehensive list of software components to be updated to run the software on a reduced feature set device variant.rś…rū}rü(hjj÷hkjõubaubh™)rż}rž(hjXµExample: `Processor SDK RTOS porting guide for AM571x/AM570x Speed Grades `_hkjŸ hohphqhœhs}r’(hu]hv]hw]hx]h{]uh}Kyh~hh]r(hˆX Example: r…r}r(hjX Example: hkjżubh¢)r}r(hjX¬`Processor SDK RTOS porting guide for AM571x/AM570x Speed Grades `_hs}r(UnameX?Processor SDK RTOS porting guide for AM571x/AM570x Speed Gradesh¦Xghttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_Porting_Guide_for_AM571x/AM570x_Speed_Gradesrhx]hw]hu]hv]h{]uhkjżh]rhˆX?Processor SDK RTOS porting guide for AM571x/AM570x Speed Gradesr …r }r (hjUhkjubahqh«ubj)r }r (hjXj jKhkjżhqjhs}r(Urefurijhx]rjk ahw]hu]hv]h{]rhauh]ubeubh™)r}r(hjX§Features noted as ā€œnot supported,ā€ in device datasheet must not be used. Their functionality is not supported by TI for this family of devices. These features are subject to removal without notice on future device revisions. Any information regarding the unsupported features has been retained in the documentation solely for the purpose of clarifying signal names or for consistency with previous feature descriptions.rhkjŸ hohphqhœhs}r(hu]hv]hw]hx]h{]uh}K|h~hh]rhˆX§Features noted as ā€œnot supported,ā€ in device datasheet must not be used. Their functionality is not supported by TI for this family of devices. These features are subject to removal without notice on future device revisions. Any information regarding the unsupported features has been retained in the documentation solely for the purpose of clarifying signal names or for consistency with previous feature descriptions.r…r}r(hjjhkjubaubjģ)r}r(hjUhkjŸ hohphqjļhs}r(hu]hv]hw]hx]h{]uh}Kh~hh]rjņ)r}r(hjUjõKhkjhohphqh}hs}r(hu]hv]hw]hx]h{]uh}Kh~hh]ubaubeubhl)r }r!(hjUhkhhohphqhrhs}r"(hu]hv]hw]hx]r#jŽ ah{]r$hSauh}K„h~hh]r%(h)r&}r'(hjXTraining and Documentationr(hkj hohphqh…hs}r)(hu]hv]hw]hx]h{]uh}K„h~hh]r*hˆXTraining and Documentationr+…r,}r-(hjj(hkj&ubaubhŒ)r.}r/(hjX?Is there any training content available for Processor SDK RTOS?r0hkj hohphqhhs}r1(hx]r2j‚ ahw]hu]hv]h{]r3h=auh}Nh~hh]r4hˆX?Is there any training content available for Processor SDK RTOS?r5…r6}r7(hjj0hkj.ubaubh™)r8}r9(hjXńThere are multiple Processor SDK RTOS training modules available online as part of the `Processor SDK Training Series `__. Link to the complete series or refer to the direct links below:hkj hohphqhœhs}r:(hu]hv]hw]hx]h{]uh}KŠh~hh]r;(hˆXWThere are multiple Processor SDK RTOS training modules available online as part of the r<…r=}r>(hjXWThere are multiple Processor SDK RTOS training modules available online as part of the hkj8ubh¢)r?}r@(hjXY`Processor SDK Training Series `__hs}rA(UnameXProcessor SDK Training Seriesh¦X5https://training.ti.com/processor-sdk-training-serieshx]hw]hu]hv]h{]uhkj8h]rBhˆXProcessor SDK Training SeriesrC…rD}rE(hjUhkj?ubahqh«ubhˆXA. Link to the complete series or refer to the direct links below:rF…rG}rH(hjXA. Link to the complete series or refer to the direct links below:hkj8ubeubh™)rI}rJ(hjXTraining URLs:rKhkj hohphqhœhs}rL(hu]hv]hw]hx]h{]uh}Kh~hh]rMhˆXTraining URLs:rN…rO}rP(hjjKhkjIubaubhŚ)rQ}rR(hjUhkj hohphqj hs}rS(hŽX-hx]hw]hu]hv]h{]uh}K‘h~hh]rT(hą)rU}rV(hjXq`Processor SDK RTOS Overview Part I `__hkjQhohphqhõhs}rW(hu]hv]hw]hx]h{]uh}Nh~hh]rXh™)rY}rZ(hjXq`Processor SDK RTOS Overview Part I `__r[hkjUhohphqhœhs}r\(hu]hv]hw]hx]h{]uh}K‘h]r]h¢)r^}r_(hjj[hs}r`(UnameX"Processor SDK RTOS Overview Part Ih¦XHhttps://training.ti.com/introduction-processor-sdk-rtos-part-1?cu=519268hx]hw]hu]hv]h{]uhkjYh]rahˆX"Processor SDK RTOS Overview Part Irb…rc}rd(hjUhkj^ubahqh«ubaubaubhą)re}rf(hjXr`Processor SDK RTOS Overview Part II `__hkjQhohphqhõhs}rg(hu]hv]hw]hx]h{]uh}Nh~hh]rhh™)ri}rj(hjXr`Processor SDK RTOS Overview Part II `__rkhkjehohphqhœhs}rl(hu]hv]hw]hx]h{]uh}K“h]rmh¢)rn}ro(hjjkhs}rp(UnameX#Processor SDK RTOS Overview Part IIh¦XHhttps://training.ti.com/introduction-processor-sdk-rtos-part-2?cu=519268hx]hw]hu]hv]h{]uhkjih]rqhˆX#Processor SDK RTOS Overview Part IIrr…rs}rt(hjUhkjnubahqh«ubaubaubhą)ru}rv(hjXŠ`Application Development Using Processor SDK RTOS `__ hkjQhohphqhõhs}rw(hu]hv]hw]hx]h{]uh}Nh~hh]rxh™)ry}rz(hjX‰`Application Development Using Processor SDK RTOS `__r{hkjuhohphqhœhs}r|(hu]hv]hw]hx]h{]uh}K•h]r}h¢)r~}r(hjj{hs}r€(UnameX0Application Development Using Processor SDK RTOSh¦XRhttps://training.ti.com/application-development-using-processor-sdk-rtos?cu=519268hx]hw]hu]hv]h{]uhkjyh]rhˆX0Application Development Using Processor SDK RTOSr‚…rƒ}r„(hjUhkj~ubahqh«ubaubaubeubhŒ)r…}r†(hjX1What documentation exists for Processor SDK RTOS?r‡hkj hohphqhhs}rˆ(hx]r‰je ahw]hu]hv]h{]rŠhauh}Nh~hh]r‹hˆX1What documentation exists for Processor SDK RTOS?rŒ…r}rŽ(hjj‡hkj…ubaubh™)r}r(hjX6There are three main documents for Processor SDK RTOS:r‘hkj hohphqhœhs}r’(hu]hv]hw]hx]h{]uh}K›h~hh]r“hˆX6There are three main documents for Processor SDK RTOS:r”…r•}r–(hjj‘hkjubaubhŚ)r—}r˜(hjUhkj hohphqj hs}r™(hŽX-hx]hw]hu]hv]h{]uh}Kh~hh]rš(hą)r›}rœ(hjXÅ:ref:`Getting Started Guide ` Provides information on setting up software and running basic examples/demonstrations bundled within the Processor SDK.hkj—hohphqhõhs}r(hu]hv]hw]hx]h{]uh}Nh~hh]ržh™)rŸ}r (hjXÅ:ref:`Getting Started Guide ` Provides information on setting up software and running basic examples/demonstrations bundled within the Processor SDK.hkj›hohphqhœhs}r”(hu]hv]hw]hx]h{]uh}Kh]r¢(j0)r£}r¤(hjXM:ref:`Getting Started Guide `r„hkjŸhohphqj4hs}r¦(UreftypeXrefj6ˆj7X.processor-sdk-rtos-getting-started-guide-labelU refdomainXstdr§hx]hw]U refexplicitˆhu]hv]h{]j9j:uh}Kh]rØj<)r©}rŖ(hjj„hs}r«(hu]hv]r¬(jAj§Xstd-refr­ehw]hx]h{]uhkj£h]r®hˆXGetting Started GuiderÆ…r°}r±(hjUhkj©ubahqjGubaubhˆXx Provides information on setting up software and running basic examples/demonstrations bundled within the Processor SDK.r²…r³}r“(hjXx Provides information on setting up software and running basic examples/demonstrations bundled within the Processor SDK.hkjŸubeubaubhą)rµ}r¶(hjXg`Software Developer Guide `__: Provides information on features, functions, delivery package, and compile tools for the Processor SDK RTOS release. This guide also provides detailed information regarding software elements and software infrastructure to allow developers to start creating applications.hkj—hohphqhõhs}r·(hu]hv]hw]hx]h{]uh}Nh~hh]røh™)r¹}rŗ(hjXg`Software Developer Guide `__: Provides information on features, functions, delivery package, and compile tools for the Processor SDK RTOS release. This guide also provides detailed information regarding software elements and software infrastructure to allow developers to start creating applications.hkjµhohphqhœhs}r»(hu]hv]hw]hx]h{]uh}K h]r¼(h¢)r½}r¾(hjXW`Software Developer Guide `__hs}ræ(UnameXSoftware Developer Guideh¦X8index.html#processor-sdk-rtos-software-developer-s-guidehx]hw]hu]hv]h{]uhkj¹h]rĄhˆXSoftware Developer GuiderĮ…rĀ}rĆ(hjUhkj½ubahqh«ubhˆX: Provides information on features, functions, delivery package, and compile tools for the Processor SDK RTOS release. This guide also provides detailed information regarding software elements and software infrastructure to allow developers to start creating applications.rÄ…rÅ}rĘ(hjX: Provides information on features, functions, delivery package, and compile tools for the Processor SDK RTOS release. This guide also provides detailed information regarding software elements and software infrastructure to allow developers to start creating applications.hkj¹ubeubaubhą)rĒ}rČ(hjX™`Migration Guide `__: Provides migration information for applications built on top of the Processor SDK for RTOS. hkj—hohphqhõhs}rÉ(hu]hv]hw]hx]h{]uh}Nh~hh]rŹh™)rĖ}rĢ(hjX˜`Migration Guide `__: Provides migration information for applications built on top of the Processor SDK for RTOS.hkjĒhohphqhœhs}rĶ(hu]hv]hw]hx]h{]uh}K§h]rĪ(h¢)rĻ}rŠ(hjX;`Migration Guide `__hs}rŃ(UnameXMigration Guideh¦X%Release_Specific.html#migration-guidehx]hw]hu]hv]h{]uhkjĖh]rŅhˆXMigration GuiderÓ…rŌ}rÕ(hjUhkjĻubahqh«ubhˆX]: Provides migration information for applications built on top of the Processor SDK for RTOS.rÖ…r×}rŲ(hjX]: Provides migration information for applications built on top of the Processor SDK for RTOS.hkjĖubeubaubeubjģ)rŁ}rŚ(hjUhkj hohphqjļhs}rŪ(hu]hv]hw]hx]h{]uh}K«h~hh]rÜjņ)rŻ}rŽ(hjUjõKhkjŁhohphqh}hs}rß(hu]hv]hw]hx]h{]uh}Kh~hh]ubaubeubhmhl)rą}rį(hjUhkhhohphqhrhs}rā(hu]hv]hw]hx]rćj‡ ah{]rähDauh}MŠh~hh]rå(h)rę}rē(hjXDevice Driversrčhkjąhohphqh…hs}ré(hu]hv]hw]hx]h{]uh}MŠh~hh]rźhˆXDevice Driversrė…rģ}rķ(hjjčhkjęubaubhŒ)rī}rļ(hjXHHow do I find out if a driver is supported in the package for my device?ršhkjąhohphqhhs}rń(hx]rņjn ahw]hu]hv]h{]róhauh}Nh~hh]rōhˆXHHow do I find out if a driver is supported in the package for my device?rõ…rö}r÷(hjjšhkjīubaubh™)rų}rł(hjX®For all SoC and board-specific driver support, we recommend that you refer to the `Release Notes `__ corresponding to your release.hkjąhohphqhœhs}rś(hu]hv]hw]hx]h{]uh}Mh~hh]rū(hˆXRFor all SoC and board-specific driver support, we recommend that you refer to the rü…rż}rž(hjXRFor all SoC and board-specific driver support, we recommend that you refer to the hkjųubh¢)r’}r(hjX=`Release Notes `__hs}r(UnameX Release Notesh¦X)Release_Specific.html#supported-platformshx]hw]hu]hv]h{]uhkjųh]rhˆX Release Notesr…r}r(hjUhkj’ubahqh«ubhˆX corresponding to your release.r…r}r(hjX corresponding to your release.hkjųubeubh™)r }r (hjX¼If you need further details for driver support on all cores on heterogeneous multi-core devices, please reach out to the engineering team using `E2E forums `__.hkjąhohphqhœhs}r (hu]hv]hw]hx]h{]uh}M”h~hh]r (hˆXIf you need further details for driver support on all cores on heterogeneous multi-core devices, please reach out to the engineering team using r …r}r(hjXIf you need further details for driver support on all cores on heterogeneous multi-core devices, please reach out to the engineering team using hkj ubh¢)r}r(hjX+`E2E forums `__hs}r(UnameX E2E forumsh¦Xhttp://e2e.ti.com/support/hx]hw]hu]hv]h{]uhkj h]rhˆX E2E forumsr…r}r(hjUhkjubahqh«ubhˆX.…r}r(hjX.hkj ubeubhŒ)r}r(hjX5Where can I find example projects for device drivers?rhkjąhohphqhhs}r(hx]rj” ahw]hu]hv]h{]rh`auh}Nh~hh]rhˆX5Where can I find example projects for device drivers?r …r!}r"(hjjhkjubaubh™)r#}r$(hjX—The PDK package in processor SDK RTOS does not contain pre-canned CCS projects for driver examples. But it does provide scripts to set up the development environment and create the example CCS projects based on that setup. This allows the SDK the flexibility to create CCS projects based on the user-specific host setup. In order to create the example projects, users can follow the sequence provided below:r%hkjąhohphqhœhs}r&(hu]hv]hw]hx]h{]uh}M›h~hh]r'hˆX—The PDK package in processor SDK RTOS does not contain pre-canned CCS projects for driver examples. But it does provide scripts to set up the development environment and create the example CCS projects based on that setup. This allows the SDK the flexibility to create CCS projects based on the user-specific host setup. In order to create the example projects, users can follow the sequence provided below:r(…r)}r*(hjj%hkj#ubaubj– )r+}r,(hjUhkjąhohphqj™ hs}r-(j› U.hx]hw]hu]jœ Uhv]h{]j jž uh}M¢h~hh]r.(hą)r/}r0(hjX~Users are required to setup their development environment using `Processor SDK RTOS Setup `__hkj+hohphqhõhs}r1(hu]hv]hw]hx]h{]uh}Nh~hh]r2h™)r3}r4(hjX~Users are required to setup their development environment using `Processor SDK RTOS Setup `__hkj/hohphqhœhs}r5(hu]hv]hw]hx]h{]uh}M¢h]r6(hˆX@Users are required to setup their development environment using r7…r8}r9(hjX@Users are required to setup their development environment using hkj3ubh¢)r:}r;(hjX>`Processor SDK RTOS Setup `__hs}r<(UnameXProcessor SDK RTOS Setuph¦XOverview.html#setup-environmenthx]hw]hu]hv]h{]uhkj3h]r=hˆXProcessor SDK RTOS Setupr>…r?}r@(hjUhkj:ubahqh«ubeubaubhą)rA}rB(hjXsSetup the PDK build environment `PDK Setup `__.hkj+hohphqhõhs}rC(hu]hv]hw]hx]h{]uh}Nh~hh]rDh™)rE}rF(hjXsSetup the PDK build environment `PDK Setup `__.hkjAhohphqhœhs}rG(hu]hv]hw]hx]h{]uh}M¤h]rH(hˆX Setup the PDK build environment rI…rJ}rK(hjX Setup the PDK build environment hkjEubh¢)rL}rM(hjXR`PDK Setup `__hs}rN(UnameX PDK Setuph¦XBHow_to_Guides.html#building-pdk-using-gmake-in-windows-environmenthx]hw]hu]hv]h{]uhkjEh]rOhˆX PDK SetuprP…rQ}rR(hjUhkjLubahqh«ubhˆX.…rS}rT(hjX.hkjEubeubaubhą)rU}rV(hjXĀExecute the PdkProjectCreate script in ${PDK_INSTALL_PATH}/packages as described on the `PDK Example and Test Project Creation wiki `__ hkj+hohphqhõhs}rW(hu]hv]hw]hx]h{]uh}Nh~hh]rXh™)rY}rZ(hjXĮExecute the PdkProjectCreate script in ${PDK_INSTALL_PATH}/packages as described on the `PDK Example and Test Project Creation wiki `__hkjUhohphqhœhs}r[(hu]hv]hw]hx]h{]uh}M¦h]r\(hˆXXExecute the PdkProjectCreate script in ${PDK_INSTALL_PATH}/packages as described on the r]…r^}r_(hjXXExecute the PdkProjectCreate script in ${PDK_INSTALL_PATH}/packages as described on the hkjYubh¢)r`}ra(hjXi`PDK Example and Test Project Creation wiki `__hs}rb(UnameX*PDK Example and Test Project Creation wikih¦X8How_to_Guides.html#pdk-example-and-test-project-creationhx]hw]hu]hv]h{]uhkjYh]rchˆX*PDK Example and Test Project Creation wikird…re}rf(hjUhkj`ubahqh«ubeubaubeubhŒ)rg}rh(hjXzWhat is the difference between SOC-specific driver library and the SOC-independent (Generic core-specific) driver library?rihkjąhohphqhhs}rj(hx]rkjf ahw]hu]hv]h{]rlhauh}Nh~hh]rmhˆXzWhat is the difference between SOC-specific driver library and the SOC-independent (Generic core-specific) driver library?rn…ro}rp(hjjihkjgubaubh™)rq}rr(hjX‚Each low level driver (LLD) in the PDK package contains two versions of the driver library. The naming conventions are as follows:rshkjąhohphqhœhs}rt(hu]hv]hw]hx]h{]uh}M®h~hh]ruhˆX‚Each low level driver (LLD) in the PDK package contains two versions of the driver library. The naming conventions are as follows:rv…rw}rx(hjjshkjqubaubhŚ)ry}rz(hjUhkjąhohphqj hs}r{(hŽX-hx]hw]hu]hv]h{]uh}M±h~hh]r|hą)r}}r~(hjXV**Generic Core-specific Driver Library**Ā : ti.drv.. hkjyhohphqhõhs}r(hu]hv]hw]hx]h{]uh}Nh~hh]r€h™)r}r‚(hjXU**Generic Core-specific Driver Library**Ā : ti.drv..hkj}hohphqhœhs}rƒ(hu]hv]hw]hx]h{]uh}M±h]r„(h±)r…}r†(hjX(**Generic Core-specific Driver Library**hs}r‡(hu]hv]hw]hx]h{]uhkjh]rˆhˆX$Generic Core-specific Driver Libraryr‰…rŠ}r‹(hjUhkj…ubahqh¹ubhˆX-Ā : ti.drv..rŒ…r}rŽ(hjX-Ā : ti.drv..hkjubeubaubaubh™)r}r(hjXCExample: ti.drv.gpio.aa15fg (A15 core-specific GPIO driver library)r‘hkjąhohphqhœhs}r’(hu]hv]hw]hx]h{]uh}M“h~hh]r“hˆXCExample: ti.drv.gpio.aa15fg (A15 core-specific GPIO driver library)r”…r•}r–(hjj‘hkjubaubhŚ)r—}r˜(hjUhkjąhohphqj hs}r™(hŽX-hx]hw]hu]hv]h{]uh}M¶h~hh]ršhą)r›}rœ(hjXQ**SOC-specific Driver Library**: ti.pdk... hkj—hohphqhõhs}r(hu]hv]hw]hx]h{]uh}Nh~hh]ržh™)rŸ}r (hjXP**SOC-specific Driver Library**: ti.pdk...hkj›hohphqhœhs}r”(hu]hv]hw]hx]h{]uh}M¶h]r¢(h±)r£}r¤(hjX**SOC-specific Driver Library**hs}r„(hu]hv]hw]hx]h{]uhkjŸh]r¦hˆXSOC-specific Driver Libraryr§…rØ}r©(hjUhkj£ubahqh¹ubhˆX1: ti.pdk...rŖ…r«}r¬(hjX1: ti.pdk...hkjŸubeubaubaubh™)r­}r®(hjXGExample: ti.drv.gpio.am572x.aa15fg (A15 GPIO driver library for AM572x)rÆhkjąhohphqhœhs}r°(hu]hv]hw]hx]h{]uh}M¹h~hh]r±hˆXGExample: ti.drv.gpio.am572x.aa15fg (A15 GPIO driver library for AM572x)r²…r³}r“(hjjÆhkj­ubaubh™)rµ}r¶(hjXāWhen using the core-specific driver library, users are required to provide SOC-specific driver initialization structures that provide information regarding the module instance used, interrupt numbers, configuration modes, etc.r·hkjąhohphqhœhs}rø(hu]hv]hw]hx]h{]uh}M»h~hh]r¹hˆXāWhen using the core-specific driver library, users are required to provide SOC-specific driver initialization structures that provide information regarding the module instance used, interrupt numbers, configuration modes, etc.rŗ…r»}r¼(hjj·hkjµubaubh™)r½}r¾(hjX™The SOC-specific driver library contains a default configuration (provided in _soc.c file) built into the library that gets used to initialize the driver on TI EVMs and to run sample applications provided in driver package. It may need to be modified to suit for a custom board and/or target application. The default configuration includes a specific peripheral instance, interrupt configuration, etc.ræhkjąhohphqhœhs}rĄ(hu]hv]hw]hx]h{]uh}MĄh~hh]rĮhˆX™The SOC-specific driver library contains a default configuration (provided in _soc.c file) built into the library that gets used to initialize the driver on TI EVMs and to run sample applications provided in driver package. It may need to be modified to suit for a custom board and/or target application. The default configuration includes a specific peripheral instance, interrupt configuration, etc.rĀ…rĆ}rÄ(hjjæhkj½ubaubhŒ)rÅ}rĘ(hjX[How to create ARM baremetal CCS project that link to PDK driver libraries using GNU Linker?rĒhkjąhohphqhhs}rČ(hx]rÉjw ahw]hu]hv]h{]rŹh,auh}Nh~hh]rĖhˆX[How to create ARM baremetal CCS project that link to PDK driver libraries using GNU Linker?rĢ…rĶ}rĪ(hjjĒhkjÅubaubh™)rĻ}rŠ(hjX¦The static libraries in Platform development kit (PDK) drivers use the convention ti.drv..a. For example, the UART driver library for A15 is named "ti.drv.uart.aa15fg". This is different form the convention of naming the libraries with a suffix of "lib" and extension ".a" which is generally the case for ARM compiler libraries (e.g., librdimon.a, libgcc.a, libm.a). This is usually not an issue when building applications using GCC compiler and make/gmake as libraries can be linked using "-l" option. However, when building bare-metal (no-OS) ARM projects in CCS, the IDE expects the libraries to have the name with suffix "lib" and extension ".a". If developers try to link libraries which does not follow this convention, they observe a linking error that mentions that the library doesn`t exist. There are a couple of work around options available to users when working with baremetal PDK driver libraries:rŃhkjąhohphqhœhs}rŅ(hu]hv]hw]hx]h{]uh}MĖh~hh]rÓhˆX¦The static libraries in Platform development kit (PDK) drivers use the convention ti.drv..a. For example, the UART driver library for A15 is named "ti.drv.uart.aa15fg". This is different form the convention of naming the libraries with a suffix of "lib" and extension ".a" which is generally the case for ARM compiler libraries (e.g., librdimon.a, libgcc.a, libm.a). This is usually not an issue when building applications using GCC compiler and make/gmake as libraries can be linked using "-l" option. However, when building bare-metal (no-OS) ARM projects in CCS, the IDE expects the libraries to have the name with suffix "lib" and extension ".a". If developers try to link libraries which does not follow this convention, they observe a linking error that mentions that the library doesn`t exist. There are a couple of work around options available to users when working with baremetal PDK driver libraries:rŌ…rÕ}rÖ(hjjŃhkjĻubaubh™)r×}rŲ(hjX˜**Option 1:** Add a colon in front of the library name when adding the ARM driver library to "Build Settings"->"GNU Linker"->"Libraries" as shown below:hkjąhohphqhœhs}rŁ(hu]hv]hw]hx]h{]uh}MŚh~hh]rŚ(h±)rŪ}rÜ(hjX **Option 1:**hs}rŻ(hu]hv]hw]hx]h{]uhkj×h]rŽhˆX Option 1:rß…rą}rį(hjUhkjŪubahqh¹ubhˆX‹ Add a colon in front of the library name when adding the ARM driver library to "Build Settings"->"GNU Linker"->"Libraries" as shown below:rā…rć}rä(hjX‹ Add a colon in front of the library name when adding the ARM driver library to "Build Settings"->"GNU Linker"->"Libraries" as shown below:hkj×ubeubj;)rå}rę(hjX0.. Image:: ../images/Bare-metal_driver_link.png hkjąhohphqj>hs}rē(UuriX)rtos/../images/Bare-metal_driver_link.pngrčhx]hw]hu]hv]jA}réU*jčsh{]uh}Mßh~hh]ubh™)rź}rė(hjXS**Option 2:** Add driver libraries using linker command file using the INPUT syntaxhkjąhohphqhœhs}rģ(hu]hv]hw]hx]h{]uh}Mąh~hh]rķ(h±)rī}rļ(hjX **Option 2:**hs}rš(hu]hv]hw]hx]h{]uhkjźh]rńhˆX Option 2:rņ…ró}rō(hjUhkjīubahqh¹ubhˆXF Add driver libraries using linker command file using the INPUT syntaxrõ…rö}r÷(hjXF Add driver libraries using linker command file using the INPUT syntaxhkjźubeubjG)rų}rł(hjXWINPUT( "C:\ti\pdk_am335x_1_0_6\packages\ti\drv\gpio\lib\a8\release\ti.drv.gpio.profiling.aa8fg" "C:\ti\pdk_am335x_1_0_6\packages\ti\utils\profiling\lib\a8\release\ti.utils.profiling.aa8fg" "C:\ti\pdk_am335x_1_0_6\packages\ti\board\lib\icev2AM335x\a8\release\ti.board.aa8fg" "C:\ti\pdk_am335x_1_0_6\packages\ti\drv\i2c\lib\a8\release\ti.drv.i2c.aa8fg" "C:\ti\pdk_am335x_1_0_6\packages\ti\drv\uart\lib\a8\release\ti.drv.uart.aa8fg" "C:\ti\pdk_am335x_1_0_6\packages\ti\csl\lib\am335x\a8\release\ti.csl.aa8fg" "C:\ti\pdk_am335x_1_0_6\packages\ti\osal\lib\tirtos\a8\release\ti.osal.aa8fg" )hkjąhohphqjJhs}rś(jLjMhx]hw]hu]hv]h{]uh}Måh~hh]rūhˆXWINPUT( "C:\ti\pdk_am335x_1_0_6\packages\ti\drv\gpio\lib\a8\release\ti.drv.gpio.profiling.aa8fg" "C:\ti\pdk_am335x_1_0_6\packages\ti\utils\profiling\lib\a8\release\ti.utils.profiling.aa8fg" "C:\ti\pdk_am335x_1_0_6\packages\ti\board\lib\icev2AM335x\a8\release\ti.board.aa8fg" "C:\ti\pdk_am335x_1_0_6\packages\ti\drv\i2c\lib\a8\release\ti.drv.i2c.aa8fg" "C:\ti\pdk_am335x_1_0_6\packages\ti\drv\uart\lib\a8\release\ti.drv.uart.aa8fg" "C:\ti\pdk_am335x_1_0_6\packages\ti\csl\lib\am335x\a8\release\ti.csl.aa8fg" "C:\ti\pdk_am335x_1_0_6\packages\ti\osal\lib\tirtos\a8\release\ti.osal.aa8fg" )rü…rż}rž(hjUhkjųubaubjģ)r’}r(hjUhkjąhohphqjļhs}r(hu]hv]hw]hx]h{]uh}Mļh~hh]rjņ)r}r(hjUjõKhkj’hohphqh}hs}r(hu]hv]hw]hx]h{]uh}Kh~hh]ubaubeubhl)r}r(hjUhkhhohphqhrhs}r(hu]hv]hw]hx]r jq ah{]r h!auh}Mņh~hh]r (h)r }r (hjXChip Support Library (CSL)rhkjhohphqh…hs}r(hu]hv]hw]hx]h{]uh}Mņh~hh]rhˆXChip Support Library (CSL)r…r}r(hjjhkj ubaubhŒ)r}r(hjX5Are there any bare-metal examples in the PDK package?rhkjhohphqhhs}r(hx]rju ahw]hu]hv]h{]rh)auh}Nh~hh]rhˆX5Are there any bare-metal examples in the PDK package?r…r}r(hjjhkjubaubh™)r}r(hjXCustomers who are wanting to start bare-metal code development can refer to the diagnostics package which uses the PDK drivers and does not rely on the TI RTOS. There are also CSL examples included in the package under the path ${PDK_INSTALL_PATH}\\packages\\ti\\csl\\test.hkjhohphqhœhs}r (hu]hv]hw]hx]h{]uh}M÷h~hh]r!hˆX Customers who are wanting to start bare-metal code development can refer to the diagnostics package which uses the PDK drivers and does not rely on the TI RTOS. There are also CSL examples included in the package under the path ${PDK_INSTALL_PATH}\packages\ti\csl\test.r"…r#}r$(hjXCustomers who are wanting to start bare-metal code development can refer to the diagnostics package which uses the PDK drivers and does not rely on the TI RTOS. There are also CSL examples included in the package under the path ${PDK_INSTALL_PATH}\\packages\\ti\\csl\\test.hkjubaubh™)r%}r&(hjX¼In addition to CSL example, the PDK contains bare-metal diagnostic test cases that help in testing EVM functionality. These can be located under pdk_am57xx_x_x_x\\packages\\ti\\board\\diaghkjhohphqhœhs}r'(hu]hv]hw]hx]h{]uh}Müh~hh]r(hˆXøIn addition to CSL example, the PDK contains bare-metal diagnostic test cases that help in testing EVM functionality. These can be located under pdk_am57xx_x_x_x\packages\ti\board\diagr)…r*}r+(hjX¼In addition to CSL example, the PDK contains bare-metal diagnostic test cases that help in testing EVM functionality. These can be located under pdk_am57xx_x_x_x\\packages\\ti\\board\\diaghkj%ubaubh™)r,}r-(hjX†Some of the driver examples contain a flag for BARE METAL usage of the driver. Example: GPIO/SPI already have these flags implemented.r.hkjhohphqhœhs}r/(hu]hv]hw]hx]h{]uh}Mh~hh]r0hˆX†Some of the driver examples contain a flag for BARE METAL usage of the driver. Example: GPIO/SPI already have these flags implemented.r1…r2}r3(hjj.hkj,ubaubhŒ)r4}r5(hjXhCan I read core-specific registers on multi-core devices supported in Processor SDK RTOS using CSL code?r6hkjhohphqhhs}r7(hx]r8j† ahw]hu]hv]h{]r9hCauh}Nh~hh]r:hˆXhCan I read core-specific registers on multi-core devices supported in Processor SDK RTOS using CSL code?r;…r<}r=(hjj6hkj4ubaubh™)r>}r?(hjXYes, SDK provides CSL code to read core status and system configurations using the CSL provided for specific core. For CSL code specific to cores and peripherals present on your device, please refer to the header files provided under ${PDK_INSTALL_PATH}\\packages\\ti\\csl\\src\\ip.hkjhohphqhœhs}r@(hu]hv]hw]hx]h{]uh}Mh~hh]rAhˆXYes, SDK provides CSL code to read core status and system configurations using the CSL provided for specific core. For CSL code specific to cores and peripherals present on your device, please refer to the header files provided under ${PDK_INSTALL_PATH}\packages\ti\csl\src\ip.rB…rC}rD(hjXYes, SDK provides CSL code to read core status and system configurations using the CSL provided for specific core. For CSL code specific to cores and peripherals present on your device, please refer to the header files provided under ${PDK_INSTALL_PATH}\\packages\\ti\\csl\\src\\ip.hkj>ubaubh™)rE}rF(hjX'A good example of where you may need to access CSL code to read core-specific information is on a multi-core device. You can have code shared between multiple cores and would like to use a different code path or internal buffer based on core ID. The CSL code helps you implement this as follows:rGhkjhohphqhœhs}rH(hu]hv]hw]hx]h{]uh}M h~hh]rIhˆX'A good example of where you may need to access CSL code to read core-specific information is on a multi-core device. You can have code shared between multiple cores and would like to use a different code path or internal buffer based on core ID. The CSL code helps you implement this as follows:rJ…rK}rL(hjjGhkjEubaubh™)rM}rN(hjXHFor example, if you need to read the core ID on a multi-core DSP device:rOhkjhohphqhœhs}rP(hu]hv]hw]hx]h{]uh}Mh~hh]rQhˆXHFor example, if you need to read the core ID on a multi-core DSP device:rR…rS}rT(hjjOhkjMubaubjG)rU}rV(hjXVuint32_t coreNum; /* Get the core number. */ coreNum = CSL_chipReadReg(CSL_CHIP_DNUM);hkjhohphqjJhs}rW(jLjMhx]hw]hu]hv]h{]uh}Mh~hh]rXhˆXVuint32_t coreNum; /* Get the core number. */ coreNum = CSL_chipReadReg(CSL_CHIP_DNUM);rY…rZ}r[(hjUhkjUubaubh™)r\}r](hjX[To do the same on the multi-core A15 device, you can use the following code in the A15 CSL:r^hkjhohphqhœhs}r_(hu]hv]hw]hx]h{]uh}Mh~hh]r`hˆX[To do the same on the multi-core A15 device, you can use the following code in the A15 CSL:ra…rb}rc(hjj^hkj\ubaubjG)rd}re(hjXeunsigned int armNum; armNum = CSL_a15ReadCoreId(); //This gets the core ID using the MPIDR in the A15hkjhohphqjJhs}rf(jLjMhx]hw]hu]hv]h{]uh}Mh~hh]rghˆXeunsigned int armNum; armNum = CSL_a15ReadCoreId(); //This gets the core ID using the MPIDR in the A15rh…ri}rj(hjUhkjdubaubhŒ)rk}rl(hjXGHow do I find out which CSL header and source files apply to my device?rmhkjhohphqhhs}rn(hx]rojy ahw]hu]hv]h{]rph/auh}Nh~hh]rqhˆXGHow do I find out which CSL header and source files apply to my device?rr…rs}rt(hjjmhkjkubaubh™)ru}rv(hjX7The CSL package that is part of the SDK is a unified CSL that covers all devices supported by the Processor SDK RTOS. When you link to the CSL library or include the header files for a specific IP, the CSL library requires users to add a MACRO definition (-D SOC_XX####) to your build to indicate which SOC you are using. In order to locate the IP files for your device, always look at the header file at the top of the CSL directory pdk__xx_xx_xx\\packages\\ti\\csl and the files that are found under the SOC_XX#### corresponds to the SOC that you are using.hkjhohphqhœhs}rw(hu]hv]hw]hx]h{]uh}M&h~hh]rxhˆX4The CSL package that is part of the SDK is a unified CSL that covers all devices supported by the Processor SDK RTOS. When you link to the CSL library or include the header files for a specific IP, the CSL library requires users to add a MACRO definition (-D SOC_XX####) to your build to indicate which SOC you are using. In order to locate the IP files for your device, always look at the header file at the top of the CSL directory pdk__xx_xx_xx\packages\ti\csl and the files that are found under the SOC_XX#### corresponds to the SOC that you are using.ry…rz}r{(hjX7The CSL package that is part of the SDK is a unified CSL that covers all devices supported by the Processor SDK RTOS. When you link to the CSL library or include the header files for a specific IP, the CSL library requires users to add a MACRO definition (-D SOC_XX####) to your build to indicate which SOC you are using. In order to locate the IP files for your device, always look at the header file at the top of the CSL directory pdk__xx_xx_xx\\packages\\ti\\csl and the files that are found under the SOC_XX#### corresponds to the SOC that you are using.hkjuubaubh™)r|}r}(hjXkSOC-specific files can also be found under the pdk__xx_xx_xx\\packages\\ti\\csl\\soc\\hkjhohphqhœhs}r~(hu]hv]hw]hx]h{]uh}M/h~hh]rhˆXfSOC-specific files can also be found under the pdk__xx_xx_xx\packages\ti\csl\soc\r€…r}r‚(hjXkSOC-specific files can also be found under the pdk__xx_xx_xx\\packages\\ti\\csl\\soc\\hkj|ubaubhŒ)rƒ}r„(hjX7What is the system memory map used by the SDK examples?r…hkjhohphqhhs}r†(hx]r‡j ahw]hu]hv]h{]rˆhVauh}Nh~hh]r‰hˆX7What is the system memory map used by the SDK examples?rŠ…r‹}rŒ(hjj…hkjƒubaubh™)r}rŽ(hjX The TI RTOS-based examples included in the SDK rely on the platform definitions provided inside bios_6_xx_xx_xx\\packages\\ti\\platforms for partitioning the SOC memory between all the available cores on the SoC. Please take a look at the snapshot below for AM572x:hkjhohphqhœhs}r(hu]hv]hw]hx]h{]uh}M5h~hh]rhˆXThe TI RTOS-based examples included in the SDK rely on the platform definitions provided inside bios_6_xx_xx_xx\packages\ti\platforms for partitioning the SOC memory between all the available cores on the SoC. Please take a look at the snapshot below for AM572x:r‘…r’}r“(hjX The TI RTOS-based examples included in the SDK rely on the platform definitions provided inside bios_6_xx_xx_xx\\packages\\ti\\platforms for partitioning the SOC memory between all the available cores on the SoC. Please take a look at the snapshot below for AM572x:hkjubaubjG)r”}r•(hjXu/* Memory Map for ti.platforms.evmAM572X * * Virtual Physical Size Comment * ------------------------------------------------------------------------ * 8000_0000 1000_0000 ( 256 MB) External Memory * * 0000_0000 0 8000_0000 100 ( 256 B) -------- * 8000_0100 FF00 ( ~64 KB) -------- * 0000_0000 8001_0000 100 ( 256 B) -------- * 8001_0100 FF00 ( ~64 KB) -------- * 0000_0000 8002_0000 100 ( 256 B) -------- * 8002_0100 FF00 ( ~64 KB) -------- * 0000_0000 8003_0000 100 ( 256 B) -------- * 8003_0100 FE_FF00 ( ~16 MB) -------- * 1 8100_0000 40_0000 ( 4 MB) -------- * 8140_0000 C0_0000 ( 12 MB) -------- * 2 8200_0000 40_0000 ( 4 MB) -------- * 8240_0000 C0_0000 ( 12 MB) -------- * 3 8300_0000 40_0000 ( 4 MB) -------- * 8340_0000 C0_0000 ( 12 MB) -------- * 4 8400_0000 40_0000 ( 4 MB) -------- * 8440_0000 C0_0000 ( 12 MB) -------- * 5 8500_0000 100_0000 ( 16 MB) -------- * 6 8600_0000 100_0000 ( 16 MB) -------- * 7 8700_0000 100_0000 ( 16 MB) -------- * 8 8800_0000 100_0000 ( 16 MB) -------- * 9 8900_0000 100_0000 ( 16 MB) -------- * A 8A00_0000 80_0000 ( 8 MB) IPU1 (code, data), benelli * 8A80_0000 80_0000 ( 8 MB) IPU2 (code, data), benelli * B 8B00_0000 100_0000 ( 16 MB) HOST (code, data) * C 8C00_0000 100_0000 ( 16 MB) DSP1 (code, data) * D 8D00_0000 100_0000 ( 16 MB) DSP2 (code, data) * E 8E00_0000 100_0000 ( 16 MB) SR_0 (ipc) * F 8F00_0000 100_0000 ( 16 MB) -------- */hkjhohphqjJhs}r–(jLjMhx]hw]hu]hv]h{]uh}M<h~hh]r—hˆXu/* Memory Map for ti.platforms.evmAM572X * * Virtual Physical Size Comment * ------------------------------------------------------------------------ * 8000_0000 1000_0000 ( 256 MB) External Memory * * 0000_0000 0 8000_0000 100 ( 256 B) -------- * 8000_0100 FF00 ( ~64 KB) -------- * 0000_0000 8001_0000 100 ( 256 B) -------- * 8001_0100 FF00 ( ~64 KB) -------- * 0000_0000 8002_0000 100 ( 256 B) -------- * 8002_0100 FF00 ( ~64 KB) -------- * 0000_0000 8003_0000 100 ( 256 B) -------- * 8003_0100 FE_FF00 ( ~16 MB) -------- * 1 8100_0000 40_0000 ( 4 MB) -------- * 8140_0000 C0_0000 ( 12 MB) -------- * 2 8200_0000 40_0000 ( 4 MB) -------- * 8240_0000 C0_0000 ( 12 MB) -------- * 3 8300_0000 40_0000 ( 4 MB) -------- * 8340_0000 C0_0000 ( 12 MB) -------- * 4 8400_0000 40_0000 ( 4 MB) -------- * 8440_0000 C0_0000 ( 12 MB) -------- * 5 8500_0000 100_0000 ( 16 MB) -------- * 6 8600_0000 100_0000 ( 16 MB) -------- * 7 8700_0000 100_0000 ( 16 MB) -------- * 8 8800_0000 100_0000 ( 16 MB) -------- * 9 8900_0000 100_0000 ( 16 MB) -------- * A 8A00_0000 80_0000 ( 8 MB) IPU1 (code, data), benelli * 8A80_0000 80_0000 ( 8 MB) IPU2 (code, data), benelli * B 8B00_0000 100_0000 ( 16 MB) HOST (code, data) * C 8C00_0000 100_0000 ( 16 MB) DSP1 (code, data) * D 8D00_0000 100_0000 ( 16 MB) DSP2 (code, data) * E 8E00_0000 100_0000 ( 16 MB) SR_0 (ipc) * F 8F00_0000 100_0000 ( 16 MB) -------- */r˜…r™}rš(hjUhkj”ubaubh™)r›}rœ(hjX¾For bare-metal code, users are required to use a linker command file for each of the cores and partition the memory manually so that there is no memory overlap in the applications running on each of the cores. For bare-metal linker command files, you can refer to the CCS templates for `Hello World `__ or the linker command file used in the common folder of the the diagnostics package.hkjhohphqhœhs}r(hu]hv]hw]hx]h{]uh}M`h~hh]rž(hˆXFor bare-metal code, users are required to use a linker command file for each of the cores and partition the memory manually so that there is no memory overlap in the applications running on each of the cores. For bare-metal linker command files, you can refer to the CCS templates for rŸ…r }r”(hjXFor bare-metal code, users are required to use a linker command file for each of the cores and partition the memory manually so that there is no memory overlap in the applications running on each of the cores. For bare-metal linker command files, you can refer to the CCS templates for hkj›ubh¢)r¢}r£(hjXK`Hello World `__hs}r¤(UnameX Hello Worldh¦X9Examples_and_Demonstrations.html#no-os-bare-metal-examplehx]hw]hu]hv]h{]uhkj›h]r„hˆX Hello Worldr¦…r§}rØ(hjUhkj¢ubahqh«ubhˆXU or the linker command file used in the common folder of the the diagnostics package.r©…rŖ}r«(hjXU or the linker command file used in the common folder of the the diagnostics package.hkj›ubeubjģ)r¬}r­(hjUhkjhohphqjļhs}r®(hu]hv]hw]hx]h{]uh}Mhh~hh]rÆjņ)r°}r±(hjUjõKhkj¬hohphqh}hs}r²(hu]hv]hw]hx]h{]uh}Kh~hh]ubaubeubjPhl)r³}r“(hjUhkhhohphqhrhs}rµ(hu]hv]hw]hx]r¶j ah{]r·hRauh}Mńh~hh]rø(h)r¹}rŗ(hjXSecondary Bootloaderr»hkj³hohphqh…hs}r¼(hu]hv]hw]hx]h{]uh}Mńh~hh]r½hˆXSecondary Bootloaderr¾…ræ}rĄ(hjj»hkj¹ubaubhŒ)rĮ}rĀ(hjXmWhat board initialization is required in the application after booting using the Secondary Boot Loader (SBL)?rĆhkj³hohphqhhs}rÄ(hx]rÅj‘ ahw]hu]hv]h{]rĘh\auh}Nh~hh]rĒhˆXmWhat board initialization is required in the application after booting using the Secondary Boot Loader (SBL)?rČ…rÉ}rŹ(hjjĆhkjĮubaubh™)rĖ}rĢ(hjX›SBL calls the board library to set up the PLL clock, DDR, and Pin Mux, and to power on slave cores and the I/O peripheral from which it will boot the application. Excluding those just mentioned, any other configuration need to be done from the application code. As long as you have added all of the device initialization to the board library, you will not need to add any initialization code in the application.rĶhkj³hohphqhœhs}rĪ(hu]hv]hw]hx]h{]uh}M÷h~hh]rĻhˆX›SBL calls the board library to set up the PLL clock, DDR, and Pin Mux, and to power on slave cores and the I/O peripheral from which it will boot the application. Excluding those just mentioned, any other configuration need to be done from the application code. As long as you have added all of the device initialization to the board library, you will not need to add any initialization code in the application.rŠ…rŃ}rŅ(hjjĶhkjĖubaubhĢ)rÓ}rŌ(hjX§For AM57xx devices, the AVS and ABB settings required for all core rails is added to the SBL code, as this initialization is required only in a production environment.hkj³hohphqhĻhs}rÕ(hu]hv]hw]hx]h{]uh}Nh~hh]rÖh™)r×}rŲ(hjX§For AM57xx devices, the AVS and ABB settings required for all core rails is added to the SBL code, as this initialization is required only in a production environment.rŁhkjÓhohphqhœhs}rŚ(hu]hv]hw]hx]h{]uh}M’h]rŪhˆX§For AM57xx devices, the AVS and ABB settings required for all core rails is added to the SBL code, as this initialization is required only in a production environment.rÜ…rŻ}rŽ(hjjŁhkj×ubaubaubhŒ)rß}rą(hjX=Where do I locate flashing and boot utilities in the package?rįhkj³hohphqhhs}rā(hx]rćj} ahw]hu]hv]h{]räh6auh}Nh~hh]råhˆX=Where do I locate flashing and boot utilities in the package?rꅁrē}rč(hjjįhkjßubaubh™)ré}rź(hjXøThe documentation for the booting and flashing of images to EVMs using Processor SDK RTOS is provided from the wiki article :ref:`Processor SDK RTOS Boot Documentation `hkj³hohphqhœhs}rė(hu]hv]hw]hx]h{]uh}Mh~hh]rģ(hˆX|The documentation for the booting and flashing of images to EVMs using Processor SDK RTOS is provided from the wiki article rķ…rī}rļ(hjX|The documentation for the booting and flashing of images to EVMs using Processor SDK RTOS is provided from the wiki article hkjéubj0)rš}rń(hjX<:ref:`Processor SDK RTOS Boot Documentation `rņhkjéhohphqj4hs}ró(UreftypeXrefj6ˆj7X fc-boot-labelU refdomainXstdrōhx]hw]U refexplicitˆhu]hv]h{]j9j:uh}Mh]rõj<)rö}r÷(hjjņhs}rų(hu]hv]rł(jAjōXstd-refrśehw]hx]h{]uhkjšh]rūhˆX%Processor SDK RTOS Boot Documentationrü…rż}rž(hjUhkjöubahqjGubaubeubh™)r’}r(hjX¬The :ref:`Boot and Flashing Utilities ` for all devices is located in the PDK package under the path pdk__x_x_x\\packages\\ti\\boot\\sbl\\tools.hkj³hohphqhœhs}r(hu]hv]hw]hx]h{]uh}M h~hh]r(hˆXThe r…r}r(hjXThe hkj’ubj0)r}r(hjX2:ref:`Boot and Flashing Utilities `rhkj’hohphqj4hs}r (UreftypeXrefj6ˆj7X fc-boot-labelU refdomainXstdr hx]hw]U refexplicitˆhu]hv]h{]j9j:uh}M h]r j<)r }r (hjjhs}r(hu]hv]r(jAj Xstd-refrehw]hx]h{]uhkjh]rhˆXBoot and Flashing Utilitiesr…r}r(hjUhkj ubahqjGubaubhˆXq for all devices is located in the PDK package under the path pdk__x_x_x\packages\ti\boot\sbl\tools.r…r}r(hjXv for all devices is located in the PDK package under the path pdk__x_x_x\\packages\\ti\\boot\\sbl\\tools.hkj’ubeubh™)r}r(hjXˆThe SDK provides secondary bootloader code for all devices, which is loaded by the ROM bootloader. The SBL is responsible for device initialization, waking up secondary cores, and deployment of the application code on different cores on multi-core devices. On single core devices, the SBL is used to manage the device initialization, as well as loading and running applications on the device.rhkj³hohphqhœhs}r(hu]hv]hw]hx]h{]uh}Mh~hh]rhˆXˆThe SDK provides secondary bootloader code for all devices, which is loaded by the ROM bootloader. The SBL is responsible for device initialization, waking up secondary cores, and deployment of the application code on different cores on multi-core devices. On single core devices, the SBL is used to manage the device initialization, as well as loading and running applications on the device.r…r}r(hjjhkjubaubh™)r }r!(hjX\Depending on the boot design you need to implement, the boot and flashing tools that are used for formatting and booting the SBL can also be leveraged to format and boot the application image directly. The flash-writing utilities for different EVMs can be located under the path pdk__x_x_x\\packages\\ti\\boot\\sbl\\tools\\flashWriter.hkj³hohphqhœhs}r"(hu]hv]hw]hx]h{]uh}Mh~hh]r#hˆXVDepending on the boot design you need to implement, the boot and flashing tools that are used for formatting and booting the SBL can also be leveraged to format and boot the application image directly. The flash-writing utilities for different EVMs can be located under the path pdk__x_x_x\packages\ti\boot\sbl\tools\flashWriter.r$…r%}r&(hjX\Depending on the boot design you need to implement, the boot and flashing tools that are used for formatting and booting the SBL can also be leveraged to format and boot the application image directly. The flash-writing utilities for different EVMs can be located under the path pdk__x_x_x\\packages\\ti\\boot\\sbl\\tools\\flashWriter.hkj ubaubh™)r'}r((hjXIf the intent is to restore the KeyStone II EVM to factory settings, then the `Program EVM Script `__ enables users to program the flash on the EVM using the pre-built firmware images provided by TI/board manufacturer.hkj³hohphqhœhs}r)(hu]hv]hw]hx]h{]uh}Mh~hh]r*(hˆXNIf the intent is to restore the KeyStone II EVM to factory settings, then the r+…r,}r-(hjXNIf the intent is to restore the KeyStone II EVM to factory settings, then the hkj'ubh¢)r.}r/(hjXW`Program EVM Script `__hs}r0(UnameXProgram EVM Scripth¦X>How_to_Guides.html#flash-bootable-images-c66x-k2h-k2e-k2l-onlyhx]hw]hu]hv]h{]uhkj'h]r1hˆXProgram EVM Scriptr2…r3}r4(hjUhkj.ubahqh«ubhˆXu enables users to program the flash on the EVM using the pre-built firmware images provided by TI/board manufacturer.r5…r6}r7(hjXu enables users to program the flash on the EVM using the pre-built firmware images provided by TI/board manufacturer.hkj'ubeubhŒ)r8}r9(hjXIWhy my SD card stopped booting with the latest Processor SDK bootloader ?r:hkj³hohphqhhs}r;(hx]r<j„ ahw]hu]hv]h{]r=h@auh}Nh~hh]r>hˆXIWhy my SD card stopped booting with the latest Processor SDK bootloader ?r?…r@}rA(hjj:hkj8ubaubh™)rB}rC(hjXThe FATFS library of processor SDK expects the SD card FAT partition entry should be in a specific format. The SD card may be having a different partition entry than the FATFS library that expects to process the media. The user has to reformat the SD card. The documentation for formatting the SD card through windows or linux is provided from the wiki article **SDK Create SD Card Script** for `Windows `__ and `Linux `__.hkj³hohphqhœhs}rD(hu]hv]hw]hx]h{]uh}M%h~hh]rE(hˆXiThe FATFS library of processor SDK expects the SD card FAT partition entry should be in a specific format. The SD card may be having a different partition entry than the FATFS library that expects to process the media. The user has to reformat the SD card. The documentation for formatting the SD card through windows or linux is provided from the wiki article rF…rG}rH(hjXiThe FATFS library of processor SDK expects the SD card FAT partition entry should be in a specific format. The SD card may be having a different partition entry than the FATFS library that expects to process the media. The user has to reformat the SD card. The documentation for formatting the SD card through windows or linux is provided from the wiki article hkjBubh±)rI}rJ(hjX**SDK Create SD Card Script**hs}rK(hu]hv]hw]hx]h{]uhkjBh]rLhˆXSDK Create SD Card ScriptrM…rN}rO(hjUhkjIubahqh¹ubhˆX for rP…rQ}rR(hjX for hkjBubh¢)rS}rT(hjX@`Windows `__hs}rU(UnameXWindowsh¦X2index_overview.html#windows-sd-card-creation-guidehx]hw]hu]hv]h{]uhkjBh]rVhˆXWindowsrW…rX}rY(hjUhkjSubahqh«ubhˆX and rZ…r[}r\(hjX and hkjBubh¢)r]}r^(hjX@`Linux `__hs}r_(UnameXLinuxh¦X4index_overview.html#tools-create-sd-card-linux-labelhx]hw]hu]hv]h{]uhkjBh]r`hˆXLinuxra…rb}rc(hjUhkj]ubahqh«ubhˆX.…rd}re(hjX.hkjBubeubjģ)rf}rg(hjUhkj³hohphqjļhs}rh(hu]hv]hw]hx]h{]uh}M,h~hh]rijņ)rj}rk(hjUjõKhkjfhohphqh}hs}rl(hu]hv]hw]hx]h{]uh}Kh~hh]ubaubeubjµhl)rm}rn(hjUhkhhohphqhrhs}ro(hu]hv]hw]hx]rpj€ ah{]rqh;auh}MNh~hh]rr(h)rs}rt(hjXFilesystem Supportruhkjmhohphqh…hs}rv(hu]hv]hw]hx]h{]uh}MNh~hh]rwhˆXFilesystem Supportrx…ry}rz(hjjuhkjsubaubhŒ)r{}r|(hjX›What filesystem support if provided by Processor SDK RTOSĀ ? Can I use UBIFS, RAMFS, or FATFS with TI RTOS when using external non-volatile memory devices?r}hkjmhohphqhhs}r~(hx]rjz ahw]hu]hv]h{]r€h0auh}Nh~hh]rhˆX›What filesystem support if provided by Processor SDK RTOSĀ ? Can I use UBIFS, RAMFS, or FATFS with TI RTOS when using external non-volatile memory devices?r‚…rƒ}r„(hjj}hkj{ubaubh™)r…}r†(hjXĢProcessor SDK RTOS only supports use of FATFS filesystem for some devices. For availability of support for your devices check the `Release Notes `__ There are numerous examples for using FATFS with USB driver and SD/MMC driver in the SDK that you can use for reference. The FATFS-specific documentation for Processor SDK RTOS is available in the `FATFS wiki section of the Processor SDK RTOS `__.hkjmhohphqhœhs}r‡(hu]hv]hw]hx]h{]uh}MUh~hh]rˆ(hˆX‚Processor SDK RTOS only supports use of FATFS filesystem for some devices. For availability of support for your devices check the r‰…rŠ}r‹(hjX‚Processor SDK RTOS only supports use of FATFS filesystem for some devices. For availability of support for your devices check the hkj…ubh¢)rŒ}r(hjX7`Release Notes `__hs}rŽ(UnameX Release Notesh¦X#Release_Specific.html#release-noteshx]hw]hu]hv]h{]uhkj…h]rhˆX Release Notesr…r‘}r’(hjUhkjŒubahqh«ubhˆXĘ There are numerous examples for using FATFS with USB driver and SD/MMC driver in the SDK that you can use for reference. The FATFS-specific documentation for Processor SDK RTOS is available in the r“…r”}r•(hjXĘ There are numerous examples for using FATFS with USB driver and SD/MMC driver in the SDK that you can use for reference. The FATFS-specific documentation for Processor SDK RTOS is available in the hkj…ubh¢)r–}r—(hjXL`FATFS wiki section of the Processor SDK RTOS `__hs}r˜(UnameX,FATFS wiki section of the Processor SDK RTOSh¦XDevice_Drivers.html#fatfshx]hw]hu]hv]h{]uhkj…h]r™hˆX,FATFS wiki section of the Processor SDK RTOSrš…r›}rœ(hjUhkj–ubahqh«ubhˆX.…r}rž(hjX.hkj…ubeubhŒ)rŸ}r (hjX%Is Unicode string supported in FATFS?r”hkjmhohphqhhs}r¢(hx]r£j ahw]hu]hv]h{]r¤hProcessor SDK RTOS only supports ANSI string for the path and file names. To switch to Unicode support, please: set the _LFN_UNICODE to 1 in the FATFS (ffconf.h) and rebuild the FATFS library. Also, Unicode support uses 16-bit WCHAR for CHAR. When calling the FATFS APIs (in ff.h), the application needs to pass WCHAR.r«hkjmhohphqhœhs}r¬(hu]hv]hw]hx]h{]uh}M`h~hh]r­hˆX>Processor SDK RTOS only supports ANSI string for the path and file names. To switch to Unicode support, please: set the _LFN_UNICODE to 1 in the FATFS (ffconf.h) and rebuild the FATFS library. Also, Unicode support uses 16-bit WCHAR for CHAR. When calling the FATFS APIs (in ff.h), the application needs to pass WCHAR.r®…rÆ}r°(hjj«hkj©ubaubjģ)r±}r²(hjUhkjmhohphqjļhs}r³(hu]hv]hw]hx]h{]uh}Meh~hh]r“jņ)rµ}r¶(hjUjõKhkj±hohphqh}hs}r·(hu]hv]hw]hx]h{]uh}Kh~hh]ubaubeubjhl)rø}r¹(hjUhkhhohphqhrhs}rŗ(hu]hv]hw]hx]r»jp ah{]r¼hauh}Mžh~hh]r½(h)r¾}ræ(hjXNetworking SupportrĄhkjøhohphqh…hs}rĮ(hu]hv]hw]hx]h{]uh}Mžh~hh]rĀhˆXNetworking SupportrĆ…rÄ}rÅ(hjjĄhkj¾ubaubhŒ)rĘ}rĒ(hjXLCan I use NDK software stack on all devices supported in Processor SDK RTOS?rČhkjøhohphqhhs}rÉ(hx]rŹjm ahw]hu]hv]h{]rĖhauh}Nh~hh]rĢhˆXLCan I use NDK software stack on all devices supported in Processor SDK RTOS?rĶ…rĪ}rĻ(hjjČhkjĘubaubh™)rŠ}rŃ(hjXThe NDK software stack provided by TI typically requires a transport layer called Network Interface Management Unit (NIMU) layer to interface the underlying platform software elements and device drivers. Please check the `Processor SDK RTOS Release Notes `__ for support of the NIMU transport driver to determine if NDK software can be utilized on your device.hkjøhohphqhœhs}rŅ(hu]hv]hw]hx]h{]uh}Mh~hh]rÓ(hˆXŻThe NDK software stack provided by TI typically requires a transport layer called Network Interface Management Unit (NIMU) layer to interface the underlying platform software elements and device drivers. Please check the rŌ…rÕ}rÖ(hjXŻThe NDK software stack provided by TI typically requires a transport layer called Network Interface Management Unit (NIMU) layer to interface the underlying platform software elements and device drivers. Please check the hkjŠubh¢)r×}rŲ(hjXJ`Processor SDK RTOS Release Notes `__hs}rŁ(UnameX Processor SDK RTOS Release Notesh¦X#Release_Specific.html#release-noteshx]hw]hu]hv]h{]uhkjŠh]rŚhˆX Processor SDK RTOS Release NotesrŪ…rÜ}rŻ(hjUhkj×ubahqh«ubhˆXf for support of the NIMU transport driver to determine if NDK software can be utilized on your device.rŽ…rß}rą(hjXf for support of the NIMU transport driver to determine if NDK software can be utilized on your device.hkjŠubeubhŒ)rį}rā(hjX4Where do I find the documentation for the NDK stack?rćhkjøhohphqhhs}rä(hx]råj‹ ahw]hu]hv]h{]ręhNauh}Nh~hh]rēhˆX4Where do I find the documentation for the NDK stack?r腁ré}rź(hjjćhkjįubaubh™)rė}rģ(hjXAll the networking-related documentation for Processor SDK RTOS, along with the NDK software stack, is linked from the wiki `NDK Documentation and References `__.hkjøhohphqhœhs}rķ(hu]hv]hw]hx]h{]uh}Mh~hh]rī(hˆX|All the networking-related documentation for Processor SDK RTOS, along with the NDK software stack, is linked from the wiki rļ…rš}rń(hjX|All the networking-related documentation for Processor SDK RTOS, along with the NDK software stack, is linked from the wiki hkjėubh¢)rņ}ró(hjX‰`NDK Documentation and References `__hs}rō(UnameX NDK Documentation and Referencesh¦Xbhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_NDK#Additional_Documentation_Referenceshx]hw]hu]hv]h{]uhkjėh]rõhˆX NDK Documentation and Referencesrö…r÷}rų(hjUhkjņubahqh«ubhˆX.…rł}rś(hjX.hkjėubeubjģ)rū}rü(hjUhkjøhohphqjļhs}rż(hu]hv]hw]hx]h{]uh}Mh~hh]ržjņ)r’}r(hjUjõKhkjūhohphqh}hs}r(hu]hv]hw]hx]h{]uh}Kh~hh]ubaubeubhl)r}r(hjUhkhhohphqhrhs}r(hu]hv]hw]hx]rj{ ah{]rh2auh}Mh~hh]r(h)r}r (hjX#Inter-processor Communication (IPC)r hkjhohphqh…hs}r (hu]hv]hw]hx]h{]uh}Mh~hh]r hˆX#Inter-processor Communication (IPC)r …r}r(hjj hkjubaubhŒ)r}r(hjX$How do I build and run IPC examples?rhkjhohphqhhs}r(hx]rjx ahw]hu]hv]h{]rh.auh}Nh~hh]rhˆX$How do I build and run IPC examples?r…r}r(hjjhkjubaubh™)r}r(hjXGIPC and corresponding examples are designed to be built from the top level `Processor SDK RTOS IPC Make Target `__. Please ensure the `Processor SDK RTOS build `__ environments have been set up before running the "make ipc_bios" or [make ipc_examples] option.hkjhohphqhœhs}r(hu]hv]hw]hx]h{]uh}Mh~hh]r(hˆXKIPC and corresponding examples are designed to be built from the top level r…r}r (hjXKIPC and corresponding examples are designed to be built from the top level hkjubh¢)r!}r"(hjXI`Processor SDK RTOS IPC Make Target `__hs}r#(UnameX"Processor SDK RTOS IPC Make Targeth¦X Overview.html#additional-targetshx]hw]hu]hv]h{]uhkjh]r$hˆX"Processor SDK RTOS IPC Make Targetr%…r&}r'(hjUhkj!ubahqh«ubhˆX. Please ensure the r(…r)}r*(hjX. Please ensure the hkjubh¢)r+}r,(hjX?`Processor SDK RTOS build `__hs}r-(UnameXProcessor SDK RTOS buildh¦X Overview.html#additional-targetshx]hw]hu]hv]h{]uhkjh]r.hˆXProcessor SDK RTOS buildr/…r0}r1(hjUhkj+ubahqh«ubhˆX` environments have been set up before running the "make ipc_bios" or [make ipc_examples] option.r2…r3}r4(hjX` environments have been set up before running the "make ipc_bios" or [make ipc_examples] option.hkjubeubh™)r5}r6(hjXÜThe documentation to run the IPC examples is provided as part of ReadMe.txt in the IPC examples or on a device-specific wiki article like `How to Run AM57x IPC Examples `__.hkjhohphqhœhs}r7(hu]hv]hw]hx]h{]uh}M!h~hh]r8(hˆXŠThe documentation to run the IPC examples is provided as part of ReadMe.txt in the IPC examples or on a device-specific wiki article like r9…r:}r;(hjXŠThe documentation to run the IPC examples is provided as part of ReadMe.txt in the IPC examples or on a device-specific wiki article like hkj5ubh¢)r<}r=(hjXQ`How to Run AM57x IPC Examples `__hs}r>(UnameXHow to Run AM57x IPC Examplesh¦X-How_to_Guides.html#run-ipc-examples-on-am572xhx]hw]hu]hv]h{]uhkj5h]r?hˆXHow to Run AM57x IPC Examplesr@…rA}rB(hjUhkj<ubahqh«ubhˆX.…rC}rD(hjX.hkj5ubeubhŒ)rE}rF(hjX$Where can I locate IPC FAQ document?rGhkjhohphqhhs}rH(hx]rIjg ahw]hu]hv]h{]rJhauh}Nh~hh]rKhˆX$Where can I locate IPC FAQ document?rL…rM}rN(hjjGhkjEubaubh™)rO}rP(hjX¼For IPC-related questions, please refer to the `IPC FAQ wiki article `__ that consolidates the FAQ across all multi-core TI processors.hkjhohphqhœhs}rQ(hu]hv]hw]hx]h{]uh}M)h~hh]rR(hˆX/For IPC-related questions, please refer to the rS…rT}rU(hjX/For IPC-related questions, please refer to the hkjOubh¢)rV}rW(hjXN`IPC FAQ wiki article `__hs}rX(UnameXIPC FAQ wiki articleh¦X3http://processors.wiki.ti.com/index.php/IPC_3.x_FAQhx]hw]hu]hv]h{]uhkjOh]rYhˆXIPC FAQ wiki articlerZ…r[}r\(hjUhkjVubahqh«ubhˆX? that consolidates the FAQ across all multi-core TI processors.r]…r^}r_(hjX? that consolidates the FAQ across all multi-core TI processors.hkjOubeubhŒ)r`}ra(hjX5How can I run TI RTOS IPC examples on AM57xx devices?rbhkjhohphqhhs}rc(hx]rdjŒ ahw]hu]hv]h{]rehQauh}Nh~hh]rfhˆX5How can I run TI RTOS IPC examples on AM57xx devices?rg…rh}ri(hjjbhkj`ubaubh™)rj}rk(hjXÆThe instructions to run the IPC examples on AM57xx are provided in the wiki article "`Running IPC Examples on AM57xx/DRA7xx `__"hkjhohphqhœhs}rl(hu]hv]hw]hx]h{]uh}M0h~hh]rm(hˆXUThe instructions to run the IPC examples on AM57xx are provided in the wiki article "rn…ro}rp(hjXUThe instructions to run the IPC examples on AM57xx are provided in the wiki article "hkjjubh¢)rq}rr(hjXY`Running IPC Examples on AM57xx/DRA7xx `__hs}rs(UnameX%Running IPC Examples on AM57xx/DRA7xxh¦X-How_to_Guides.html#run-ipc-examples-on-am572xhx]hw]hu]hv]h{]uhkjjh]rthˆX%Running IPC Examples on AM57xx/DRA7xxru…rv}rw(hjUhkjqubahqh«ubhˆX"…rx}ry(hjX"hkjjubeubjģ)rz}r{(hjUhkjhohphqjļhs}r|(hu]hv]hw]hx]h{]uh}M4h~hh]r}jņ)r~}r(hjUjõKhkjzhohphqh}hs}r€(hu]hv]hw]hx]h{]uh}Kh~hh]ubaubeubhl)r}r‚(hjUhkhhohphqhrhs}rƒ(hu]hv]hw]hx]r„js ah{]r…h&auh}M7h~hh]r†(h)r‡}rˆ(hjXDSP-Optimized Librariesr‰hkjhohphqh…hs}rŠ(hu]hv]hw]hx]h{]uh}M7h~hh]r‹hˆXDSP-Optimized LibrariesrŒ…r}rŽ(hjj‰hkj‡ubaubhŒ)r}r(hjXaWhy did I encounter a build issue while rebuilding DSPLIB, IMGLIB, or MATHLIB with C6000 CGT 8.x?r‘hkjhohphqhhs}r’(hx]r“jj ahw]hu]hv]h{]r”hauh}Nh~hh]r•hˆXaWhy did I encounter a build issue while rebuilding DSPLIB, IMGLIB, or MATHLIB with C6000 CGT 8.x?r–…r—}r˜(hjj‘hkjubaubh™)r™}rš(hjXÅThis is a known issue. Please refer to the note provided on the `Software Libraries wiki `__ to fix the issue.hkjhohphqhœhs}r›(hu]hv]hw]hx]h{]uh}M=h~hh]rœ(hˆX@This is a known issue. Please refer to the note provided on the r…rž}rŸ(hjX@This is a known issue. Please refer to the note provided on the hkj™ubh¢)r }r”(hjXs`Software Libraries wiki `__hs}r¢(UnameXSoftware Libraries wikih¦XUhttp://processors.wiki.ti.com/index.php/Software_libraries#Library_Object_File_Formathx]hw]hu]hv]h{]uhkj™h]r£hˆXSoftware Libraries wikir¤…r„}r¦(hjUhkj ubahqh«ubhˆX to fix the issue.r§…rØ}r©(hjX to fix the issue.hkj™ubeubhŒ)rŖ}r«(hjXbWhy does the performance of the DSP Libraries not match with the performance in the documentation?r¬hkjhohphqhhs}r­(hx]r®jv ahw]hu]hv]h{]rÆh*auh}Nh~hh]r°hˆXbWhy does the performance of the DSP Libraries not match with the performance in the documentation?r±…r²}r³(hjj¬hkjŖubaubh™)r“}rµ(hjX!The performance documented in the optimized DSP libraries that are part of the Processor SDK RTOS has been obtained using a C66x simulator interface which only works with a flat memory model. In order to obtain performance similar to the documentation, the user is expected to perform the SOC-specific optimization. This includes placing the data buffers in internal DSP memory, using optimized compiler settings in the application code, enabling cache if buffers are in DDR memory, enabling EDMA for moving data from external memory to L2, etc.r¶hkjhohphqhœhs}r·(hu]hv]hw]hx]h{]uh}MFh~hh]røhˆX!The performance documented in the optimized DSP libraries that are part of the Processor SDK RTOS has been obtained using a C66x simulator interface which only works with a flat memory model. In order to obtain performance similar to the documentation, the user is expected to perform the SOC-specific optimization. This includes placing the data buffers in internal DSP memory, using optimized compiler settings in the application code, enabling cache if buffers are in DDR memory, enabling EDMA for moving data from external memory to L2, etc.r¹…rŗ}r»(hjj¶hkj“ubaubh™)r¼}r½(hjXĢThe CSL libraries for the SOC and TI RTOS provide APIs for cache management of instruction memory as well as data memory. There are some useful documents that enable benchmarking on the DSP and ARM cores.r¾hkjhohphqhœhs}ræ(hu]hv]hw]hx]h{]uh}MOh~hh]rĄhˆXĢThe CSL libraries for the SOC and TI RTOS provide APIs for cache management of instruction memory as well as data memory. There are some useful documents that enable benchmarking on the DSP and ARM cores.rĮ…rĀ}rĆ(hjj¾hkj¼ubaubhŚ)rÄ}rÅ(hjUhkjhohphqj hs}rĘ(hŽX-hx]hw]hu]hv]h{]uh}MSh~hh]rĒ(hą)rČ}rÉ(hjXH`Introduction to DSP Optimization `__hkjÄhohphqhõhs}rŹ(hu]hv]hw]hx]h{]uh}Nh~hh]rĖh™)rĢ}rĶ(hjXH`Introduction to DSP Optimization `__rĪhkjČhohphqhœhs}rĻ(hu]hv]hw]hx]h{]uh}MSh]rŠh¢)rŃ}rŅ(hjjĪhs}rÓ(UnameX Introduction to DSP Optimizationh¦X!http://www.ti.com/lit/pdf/sprabf2hx]hw]hu]hv]h{]uhkjĢh]rŌhˆX Introduction to DSP OptimizationrÕ…rÖ}r×(hjUhkjŃubahqh«ubaubaubhą)rŲ}rŁ(hjXu`TI portal for Core Benchmarking `__hkjÄhohphqhõhs}rŚ(hu]hv]hw]hx]h{]uh}Nh~hh]rŪh™)rÜ}rŻ(hjXu`TI portal for Core Benchmarking `__rŽhkjŲhohphqhœhs}rß(hu]hv]hw]hx]h{]uh}MUh]rąh¢)rį}rā(hjjŽhs}rć(UnameXTI portal for Core Benchmarkingh¦XOhttp://www.ti.com/lsds/ti/processors/technology/benchmarks/core-benchmarks.pagehx]hw]hu]hv]h{]uhkjÜh]rähˆXTI portal for Core Benchmarkingr允rę}rē(hjUhkjįubahqh«ubaubaubhą)rč}ré(hjXO`TI DSP Benchmarking Application Report `__ hkjÄhohphqhõhs}rź(hu]hv]hw]hx]h{]uh}Nh~hh]rėh™)rģ}rķ(hjXN`TI DSP Benchmarking Application Report `__rīhkjčhohphqhœhs}rļ(hu]hv]hw]hx]h{]uh}MWh]ršh¢)rń}rņ(hjjīhs}ró(UnameX&TI DSP Benchmarking Application Reporth¦X!http://www.ti.com/lit/pdf/sprac13hx]hw]hu]hv]h{]uhkjģh]rōhˆX&TI DSP Benchmarking Application Reportrõ…rö}r÷(hjUhkjńubahqh«ubaubaubeubjģ)rų}rł(hjUhkjhohphqjļhs}rś(hu]hv]hw]hx]h{]uh}MZh~hh]rūjņ)rü}rż(hjUjõKhkjųhohphqh}hs}rž(hu]hv]hw]hx]h{]uh}Kh~hh]ubaubeubhl)r’}r(hjUhkhhohphqhrhs}r(hu]hv]hw]hx]rji ah{]rhauh}M]h~hh]r(h)r}r(hjX EDMA Libraryrhkj’hohphqh…hs}r(hu]hv]hw]hx]h{]uh}M]h~hh]r hˆX EDMA Libraryr …r }r (hjjhkjubaubhŒ)r }r(hjX.How do I resolve EDMA instance usage conflict?rhkj’hohphqhhs}r(hx]rjh ahw]hu]hv]h{]rhauh}Nh~hh]rhˆX.How do I resolve EDMA instance usage conflict?r…r}r(hjjhkj ubaubh™)r}r(hjXThere are several RTOS driver example projects using EDMA (e.g., PCIE, SPI, UART, and MMCSD). These projects typically can run on A15, DSP, or M4 cores. As a driver example, these projects use the first EDMA instance (EDMA #0), assuming that no others are using it at the system level.rhkj’hohphqhœhs}r(hu]hv]hw]hx]h{]uh}Mbh~hh]rhˆXThere are several RTOS driver example projects using EDMA (e.g., PCIE, SPI, UART, and MMCSD). These projects typically can run on A15, DSP, or M4 cores. As a driver example, these projects use the first EDMA instance (EDMA #0), assuming that no others are using it at the system level.r…r}r(hjjhkjubaubh™)r}r (hjXLThere may be an issue if the EDMA instance #0 is already being used in the system. For example, if the A15 core runs Linux and uses the EDMA #0 already, and a user wants to run a Processor SDK RTOS example on C66x with default EDMA #0. To resolve such an issue, please choose an unused instance. For example, EDMA #1 in the example.r!hkj’hohphqhœhs}r"(hu]hv]hw]hx]h{]uh}Mhh~hh]r#hˆXLThere may be an issue if the EDMA instance #0 is already being used in the system. For example, if the A15 core runs Linux and uses the EDMA #0 already, and a user wants to run a Processor SDK RTOS example on C66x with default EDMA #0. To resolve such an issue, please choose an unused instance. For example, EDMA #1 in the example.r$…r%}r&(hjj!hkjubaubhŒ)r'}r((hjX*CCS 7.1 platform can't be verified warningr)hkj’hohphqhhs}r*(hx]r+jƒ ahw]hu]hv]h{]r,h?auh}Nh~hh]r-hˆX*CCS 7.1 platform can't be verified warningr.…r/}r0(hjj)hkj'ubaubhŒ)r1}r2(hjX¬When I use CCS 7.1 for Processor SDK RTOS 4.0 projects, I saw a warning "Platform name 'ti.platforms.xxxxxx' could not be verified. Your project may not build as expected."r3hkj’hohphqhhs}r4(hx]r5j“ ahw]hu]hv]h{]r6h_auh}Nh~hh]r7hˆX¬When I use CCS 7.1 for Processor SDK RTOS 4.0 projects, I saw a warning "Platform name 'ti.platforms.xxxxxx' could not be verified. Your project may not build as expected."r8…r9}r:(hjj3hkj1ubaubh™)r;}r<(hjX±The warning shows in Properties---->General of a CCS project in CCS 7.1. The warning is due to a change made in CCS 7.1, whereby the User Interface tries to verify the project's target/platform name against a list of known names and if it cannot be verified then it shows the warning. The warning, in itself, does not necessarily mean that the target-name is incorrect. Especially in this case where we are looking at a known good project, it is likely showing up because the known target-names list it is checking against is incomplete. Hence you can treat the warning as harmless and ignore it. This causes some confusion we have decided to remove the warning in the next release of CCS.r=hkj’hohphqhœhs}r>(hu]hv]hw]hx]h{]uh}Mvh~hh]r?hˆX±The warning shows in Properties---->General of a CCS project in CCS 7.1. The warning is due to a change made in CCS 7.1, whereby the User Interface tries to verify the project's target/platform name against a list of known names and if it cannot be verified then it shows the warning. The warning, in itself, does not necessarily mean that the target-name is incorrect. Especially in this case where we are looking at a known good project, it is likely showing up because the known target-names list it is checking against is incomplete. Hence you can treat the warning as harmless and ignore it. This causes some confusion we have decided to remove the warning in the next release of CCS.r@…rA}rB(hjj=hkj;ubaubhŒ)rC}rD(hjX(Keystone I and II devices SGMII/MDIO/PHYrEhkj’hohphqhhs}rF(hx]rGj~ ahw]hu]hv]h{]rHh7auh}Nh~hh]rIhˆX(Keystone I and II devices SGMII/MDIO/PHYrJ…rK}rL(hjjEhkjCubaubhŒ)rM}rN(hjXSHow to setup SGMII interface to a PHY or to another SGMII port without using a PHY?rOhkj’hohphqhhs}rP(hx]rQjŠ ahw]hu]hv]h{]rRhJauh}Nh~hh]rShˆXSHow to setup SGMII interface to a PHY or to another SGMII port without using a PHY?rT…rU}rV(hjjOhkjMubaubh™)rW}rX(hjX³There are 3 SGMII connectivity modes: ā€¢ SGMII port with PHY attached and auto-negotiation enabled - for connecting to an external PHY ā€¢ SGMII master to SGMII slave with auto-negotiation enabled - this is for connecting two SGMII devices, one has to be set as master and the other as slave ā€¢ SGMII port to SGMII port with forced link configuration ā€“ generally this is used when one of the ports does not support auto-negotiationrYhkj’hohphqhœhs}rZ(hu]hv]hw]hx]h{]uh}Mˆh~hh]r[hˆX³There are 3 SGMII connectivity modes: ā€¢ SGMII port with PHY attached and auto-negotiation enabled - for connecting to an external PHY ā€¢ SGMII master to SGMII slave with auto-negotiation enabled - this is for connecting two SGMII devices, one has to be set as master and the other as slave ā€¢ SGMII port to SGMII port with forced link configuration ā€“ generally this is used when one of the ports does not support auto-negotiationr\…r]}r^(hjjYhkjWubaubh™)r_}r`(hjX~When a device having an SGMII MAC port is connected to a PHY device, the SGMII MAC is the slave in this link and the PHY is the master. The link is established using auto-negotiation across the SGMII link that is initiated by the master with an expected response by the slave. If the auto-negotiation is not initiated by the link master (PHY), the link will remain down. In TI Keystone EVMs, the Processor with an SGMII MAC port is connected to a PHY, which provides a copper interface to a Gigabit RJ-45 connector. The Processorā€™s SGMII MAC port is configured as a slave with auto-negotiation enabled. This is done in the Init_SGMII().rahkj’hohphqhœhs}rb(hu]hv]hw]hx]h{]uh}Mh~hh]rchˆX~When a device having an SGMII MAC port is connected to a PHY device, the SGMII MAC is the slave in this link and the PHY is the master. The link is established using auto-negotiation across the SGMII link that is initiated by the master with an expected response by the slave. If the auto-negotiation is not initiated by the link master (PHY), the link will remain down. In TI Keystone EVMs, the Processor with an SGMII MAC port is connected to a PHY, which provides a copper interface to a Gigabit RJ-45 connector. The Processorā€™s SGMII MAC port is configured as a slave with auto-negotiation enabled. This is done in the Init_SGMII().rd…re}rf(hjjahkj_ubaubh™)rg}rh(hjX&When a SGMII MAC port is connected to another SGMII MAC port and auto-negotiation is enabled, one must be configured to emulate a master while the other is a slave. The master port uses the MR_ADV_ABILITY register to determine speed and duplex setting instead of the MR_LP_ADV_ABILITY register.rihkj’hohphqhœhs}rj(hu]hv]hw]hx]h{]uh}Mšh~hh]rkhˆX&When a SGMII MAC port is connected to another SGMII MAC port and auto-negotiation is enabled, one must be configured to emulate a master while the other is a slave. The master port uses the MR_ADV_ABILITY register to determine speed and duplex setting instead of the MR_LP_ADV_ABILITY register.rl…rm}rn(hjjihkjgubaubh™)ro}rp(hjXAlternately, when an SGMII MAC port is connected to another SGMII MAC port and auto-negotiation is not enabled, or not available, a ā€œforced linkā€ can be established. Again, the MR_ADV_ABILITY register determines the speed and duplex setting. Please refer to the TI KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide, section 3.3, SGMII_CONTROL, MR_ADV_ABILITY and MR_LP_ADV_ABILITY registers for detail. The corresponding CSL code is implemented in packages\\ti\\csl\\src\\ip\\sgmii\\Vx\\csl_cpsgmiiAux.h.hkj’hohphqhœhs}rq(hu]hv]hw]hx]h{]uh}M h~hh]rrhˆX Alternately, when an SGMII MAC port is connected to another SGMII MAC port and auto-negotiation is not enabled, or not available, a ā€œforced linkā€ can be established. Again, the MR_ADV_ABILITY register determines the speed and duplex setting. Please refer to the TI KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide, section 3.3, SGMII_CONTROL, MR_ADV_ABILITY and MR_LP_ADV_ABILITY registers for detail. The corresponding CSL code is implemented in packages\ti\csl\src\ip\sgmii\Vx\csl_cpsgmiiAux.h.rs…rt}ru(hjXAlternately, when an SGMII MAC port is connected to another SGMII MAC port and auto-negotiation is not enabled, or not available, a ā€œforced linkā€ can be established. Again, the MR_ADV_ABILITY register determines the speed and duplex setting. Please refer to the TI KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide, section 3.3, SGMII_CONTROL, MR_ADV_ABILITY and MR_LP_ADV_ABILITY registers for detail. The corresponding CSL code is implemented in packages\\ti\\csl\\src\\ip\\sgmii\\Vx\\csl_cpsgmiiAux.h.hkjoubaubhŒ)rv}rw(hjXvIn a TI SGMII to FPGA (PHY port) connection, data corruption is observed on egress direction, what could be the cause?rxhkj’hohphqhhs}ry(hx]rzjt ahw]hu]hv]h{]r{h(auh}Nh~hh]r|hˆXvIn a TI SGMII to FPGA (PHY port) connection, data corruption is observed on egress direction, what could be the cause?r}…r~}r(hjjxhkjvubaubh™)r€}r(hjXßFirst to check if the FPGA side is a PHY port or 1000BASE-X media port. There are many similarities but they are not identical. It is important to recognize that from an electrical point of view, the SGMII interface is very similar to the 1000BASE-X interface. Both use 8B/10B encoding, a serial interface and an embedded clock. Systems can operate with SGMII connected to a media port but they are not guaranteed to operate as they are not consistent with the Ethernet standard.r‚hkj’hohphqhœhs}rƒ(hu]hv]hw]hx]h{]uh}M­h~hh]r„hˆXßFirst to check if the FPGA side is a PHY port or 1000BASE-X media port. There are many similarities but they are not identical. It is important to recognize that from an electrical point of view, the SGMII interface is very similar to the 1000BASE-X interface. Both use 8B/10B encoding, a serial interface and an embedded clock. Systems can operate with SGMII connected to a media port but they are not guaranteed to operate as they are not consistent with the Ethernet standard.r……r†}r‡(hjj‚hkj€ubaubh™)rˆ}r‰(hjXŅAlso, check Rx equalization. Some FPGA may have different choices of robust mode (dynamic feedback equalization, aka DFE) or more basic mode (linear equalizer). The DFE allows better compensation of transmission channel losses by providing a closer adjustment of filter parameters than when using a linear equalizer. However, a DFE cannot remove the pre-cursor of a transmitted bit; it only compensates for the post cursors. Try to use basic mode to see if it helps.rŠhkj’hohphqhœhs}r‹(hu]hv]hw]hx]h{]uh}Mµh~hh]rŒhˆXŅAlso, check Rx equalization. Some FPGA may have different choices of robust mode (dynamic feedback equalization, aka DFE) or more basic mode (linear equalizer). The DFE allows better compensation of transmission channel losses by providing a closer adjustment of filter parameters than when using a linear equalizer. However, a DFE cannot remove the pre-cursor of a transmitted bit; it only compensates for the post cursors. Try to use basic mode to see if it helps.r…rŽ}r(hjjŠhkjˆubaubhŒ)r}r‘(hjX^How do I program the PHY through MDIO interface? I find that TI Init_MDIO() function is empty?r’hkj’hohphqhhs}r“(hx]r”jˆ ahw]hu]hv]h{]r•hHauh}Nh~hh]r–hˆX^How do I program the PHY through MDIO interface? I find that TI Init_MDIO() function is empty?r—…r˜}r™(hjj’hkjubaubh™)rš}r›(hjX×For some TI EVMs, Init_MDIO() is empty because that PHY is configured using pin strapping and no MDIO control is needed to enable it to operate through auto-negotiation in the optimum configuration. Sample CSL code to access PHY via MDIO can be found under packages\\ti\\csl\\src\\ip\\mdio\\Vx\\csl_mdioAux.h. The MDIO user access register is used to communicate with the physical transceiver connected to the MDIO bus, not to a register of the Keystone SOC MDIO itself. The code must be customized for what you want to get or set within the PHY. To do this you must set the correct PHY address and then identify PHY register that you want to access. Those registers are defined in the PHY datasheet, not TI Keystone documents.hkj’hohphqhœhs}rœ(hu]hv]hw]hx]h{]uh}MĮh~hh]rhˆXŠFor some TI EVMs, Init_MDIO() is empty because that PHY is configured using pin strapping and no MDIO control is needed to enable it to operate through auto-negotiation in the optimum configuration. Sample CSL code to access PHY via MDIO can be found under packages\ti\csl\src\ip\mdio\Vx\csl_mdioAux.h. The MDIO user access register is used to communicate with the physical transceiver connected to the MDIO bus, not to a register of the Keystone SOC MDIO itself. The code must be customized for what you want to get or set within the PHY. To do this you must set the correct PHY address and then identify PHY register that you want to access. Those registers are defined in the PHY datasheet, not TI Keystone documents.rž…rŸ}r (hjX×For some TI EVMs, Init_MDIO() is empty because that PHY is configured using pin strapping and no MDIO control is needed to enable it to operate through auto-negotiation in the optimum configuration. Sample CSL code to access PHY via MDIO can be found under packages\\ti\\csl\\src\\ip\\mdio\\Vx\\csl_mdioAux.h. The MDIO user access register is used to communicate with the physical transceiver connected to the MDIO bus, not to a register of the Keystone SOC MDIO itself. The code must be customized for what you want to get or set within the PHY. To do this you must set the correct PHY address and then identify PHY register that you want to access. Those registers are defined in the PHY datasheet, not TI Keystone documents.hkjšubaubh™)r”}r¢(hjXTAfter PHY is programmed, the MDIO controller will continue polling the PHY periodically for status. The PHY Alive Status Register (ALIVE) and PHY Link Status Register (LINK) can be read to monitor this status of the PHY and link (please refer to the TI KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide, section 3.4).r£hkj’hohphqhœhs}r¤(hu]hv]hw]hx]h{]uh}MĶh~hh]r„hˆXTAfter PHY is programmed, the MDIO controller will continue polling the PHY periodically for status. The PHY Alive Status Register (ALIVE) and PHY Link Status Register (LINK) can be read to monitor this status of the PHY and link (please refer to the TI KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide, section 3.4).r¦…r§}rØ(hjj£hkj”ubaubeubjęehjUU transformerr©NU footnote_refsrŖ}r«Urefnamesr¬}r­X=e2e processor support