cdocutils.nodes document q)q}q(U nametypesq}q(Xrecompiling on linuxqNXbuild procedureqNX memory mapqNXtests & examplesq NXipc 3.x vs ipc lldq NXapploader usageq NXnew type_devmem entryq NXinstalling tests in qnxq NX-interprocessor-communication-related-packagesqXconfiguring entry point for sblqNXc codeqNXflash-programming-verificationqXnor bootqNXapplication integrationqNXrebuilding ipcqNXsearching nameserver instancesqNXmpmqNXDbuilding the ipc resource manager in debug mode (ipc 3.35 and above)qNXversion-and-hw-informationqXruntime troubleshootingqNXhow do i change the pbm buffer?qNX am65x/j721eqNX)getting information about a shared regionqNXdebugging-tipsqXcreating a heap*mp instanceqNX#standard ipc function call sequenceqNXgenerating examplesq NX*how to share a tcp/ip socket across tasks?q!NXallocating memory from the heapq"NX presumptionsq#X#linux benchmark test: messageqbenchq$NXtest applicationq%NX windows hostq&NX custom transport implementationsq'NXipc daemons and driversq(NXbios install guideq)NX:speeding up boot by increasing speed of the boot interfaceq*NXbooting the target.q+NXxdaisq,NX]why are the peripherals mapped to 0x6xxx:xxxx virtual memory for ipu (cortex-m4) test images?q-NXdirectory structureq.NX ping exampleq/NX#building the sbl and its componentsq0NX omap-l138-1q1X omap-l138-2q2X"thread synchronization (bios only)q3NXam57xx interrupt resourcesq4NXnandq5NXbooting via mcspiq6NXadditional referencesq7NXacronyms-used-in-this-articleq8X fc-boot-labelq9Xipc lld for am65x/j721eq:X@powerful but easy-to-use messaging with messageq (hlos and bios)q;NX compiler and linker optimizationqNX compilationq?NXhereq@X mpm transport srio configurationqANX,making loadable user application image (app)qBNXarm linux transportsrioqCNXam655x-image-formatsqDXsource referenceqENXslave-side-trace-outputqFXbootloader execution sequenceqGNX throughputqHNXchangesqINXbootloader-execution-sequenceqJXipcqKNXmessage prioritiesqLNXpreparing qspi flashqMNX0tasks internally created from timesync_drvinit()qNNX ipc-linux.makqONX!the role of ibl in pcie boot modeqPNX boot sequenceqQNX list moduleqRNXtoolsqSNX(minimal use scenario (bios-to-bios only)qTNX/remote communication via transports (bios only)qUNXipc configurationqVNXopening a message queueqWNX!ddr-timings-and-configuration-sblqXXarm linux transportqmssqYNX nimu for cpswqZNXclosing a gatemp instanceq[NXnormal operation of bootloader:q\NX(bootloader build files for am335x/am437xq]NXmpm-mailbox-moduleq^Xdeleting a heap*mp instanceq_NXsbl avs and abb setupq`NXwindows environmentqaNX spi writerqbNXsystem-state-at-boot-failureqcX8q-how-to-build-and-run-the-qmssipcbenchmark-on-c6678-evmqdXlinux install guideqeNXipc user's guideqfNXinstallqgNXbooting via mmcsdqhNX$inserting and removing list elementsqiNXexampleqjX8is there any multicast streams limitation using the ndk?qkNXhost-side-trace-outputqlXopening a gatemp instanceqmNXbooting-the-targetqnX,choosing and configuring messageq transportsqoNXopening a heap*mp instanceqpNX xdc runtimeqqNXnetwork developers kit faqqrXipc performanceqsNXcleaning flash writerqtNXti sdo utils packagequNXam655x-compiling-apps-for-sblqvX2cc-link ie field network basic example descriptionqwNX ndk overviewqxNX emulator-based-debugging-of-bootqyX ipc-qnx.makqzXconfigq{NXadvanced topicsq|NXnq-how-can-i-build-the-qmssipcbenchmark-of-pdk_c6678_1_1_2_x-pdk_c6678_1_1_2_x-with-release-build-configurationq}Xfaqq~NXbooting via sd cardqNXladqX2trace-from-ipc-resource-manager-ipc-3.35-and-aboveqX post bootqNXbuilding the bootloaderqNX6creating and removing nameserver instances dynamicallyqNX nimu for icssqNXresource custom tableqNXsbl customizationqNXquerying heap statisticsqNXpreparing the sd cardqNXoptimizing shared memory usageqNX9arm linux transportsrio source delivery and recompilationqNXq-in-ipc-packages-there-are-lot-of-test-examplesample.c-code-given-in-the-path-ipc_3_3x_xx_xxpackagestiipctests.-but-there-is-only-command-line-option-to-build-the-whole-ipc-package.-no-option-available-to-build-the-test-examples-individually.-this-is-time-consuming-to-build-the-whole-ipc-package.-customers-were-asking-for-ccs-based-environment-to-build-and-test-as-individual-example-for-both-dsp-and-arm-side.qXexpected-outputqX-keystone ipc frequently asked questions (faq)qNXsbl-and-app-entry-pointsqXoptimizing local memory usageqNXbooting via nandqNXLqhow-to-import-the-slave-code-of-image-processing-demo-and-how-do-i-build-itqXbuild questionsqNXdriver-configuration-pktlibqXadding table entries staticallyqNX#modifying table entries dynamicallyqNXoptimizing ipc applicationsqNX gatemp moduleqNXprotocol overviewqNX+configuring the messageq module (bios only)qNX9inspect the state of a slave core (ipc 3.23.01 and above)qNXandroidqNX&common steps to debug application bootqNX flash writersqNX%sample runtime program flow (dynamic)qNX building sblqNXterms and abbreviationsqNXcreating a gatemp instanceqNX initial stepsqNXproject-modificationsqXbios-side buildqNXtesting the sblqNX notify moduleqNXapploader load addressqNXnetworkqNXgq-for-keystone-ii-is-there-any-ccs-based-examples-to-demonstrate-a-simple-communication-between-arm-dspqXipc 3.xqNXbooting targetqNXboot mode settingsqNXloading the test applicationqNX!how helloworld boot example worksqNXlinux environmentqNXallocating a messageqNXcode organizationqNXsys/bios dsp transportqmssqNXbuilding the examplesqNXomapl137/omapl138/c6748qNXfcqNXc66xqNXmodes of operationqNX'choosing and configuring notify driversqNXoptimizing runtime performanceqNX<sys/bios dsp transportqmss source delivery and recompilationqNX introductionqXadditional detailsqNXtips-on-system-startupqX listmp moduleqNXtest application image creationqNXdoes ipc 3.x support smp bios?qNXnameserver interactionqNX replyqueueqNXq-for-keystone-ii-devices-where-do-i-find-the-source-code-of-the-image-processing-demo-and-how-to-i-re-build-them-using-arm-core-as-a-master-dsp-cores-as-slaves.qĈXusing memory in a shared regionqNXipc resource managerqNXsys/bios dsp transportsrioqNXbooting-the-target-1qȈXfirst-openmp-projectqɈX3special build option for industrial ddrless bootingqNXbootloader debuggingqNXqspiqNXnameserver configurationqNX?guide on building and running the ipc examples of processor sdkqNX nand writerqNXhow post boot example worksqNXbooting via spiqNXipc throughput cpu utilizationqNX am335x/am437xqNXbuildqNXonlineqՈX4creating nameserver instances statically (bios-only)qNX)how do i enable the jumbo packet support?qNX project-setupq؈Xsoftware debug stepsqNXpreparing flash deviceqNXfreeing memory to the heapqNXpreparing the emmcqNXtools and binary formatsqNXincluding header filesqNX linux buildqNXuse cases for ipcqNX&optimizing notify and messageq latencyqNXam655x-sbl-directory-structureqX am437x trmqXslave binariesqNXipc benchmarkingqNX ipc trainingqNX eeprom writerqNX ipc-bios.makqNX nor writerqNX ethernet bootqNXti-rtos kernelqNXrunning standalone examplesqNXapplication image creationqNXatomic list operationsqNXsbl-and-app-memory-mapqX5how do i configure the memory used by shmemallocator?qNX9how to check which versions of nimu driver is for my soc?qNXxdc.runtime.iheap interfaceqXqspi boot modeqNXbuild-and-loadqXrecompiling on windowsqNX srio bootqNXpreparing-flash-device-2qXpreparing-flash-device-1qXsending a messageqNX3q-how-to-re-build-the-ipc-package-and-its-librariesqXconceptual-overviewqXti sdo ipc packageqNXadditional-referencesqXipc transportsqNX9arm linux transportqmss source delivery and recompilationqNXbuild-and-executerXuart console setuprNX omap-l138rNX!recompiling through yocto/bitbakerNXBlad reports nameserver_setup: connect failed: 22, invalid argumentrNXpktlibrNXmultiproc pagerXdisabling auto-recoveryrNXpreparing sd cardrNX#creating connections with multiprocr NXconfiguring the bspr NX source coder NXomap54xxr X^keystone pa or ndk example doesn’t work in other boot mode than no-boot mode using ccs/jtag?r NXdriver-configuration-nwalrXmessageq allocation and heapsrNXmmcsd boot moderNXjq-while-building-the-armmaster-side-code-of-image-processing-demo-i-see-a-linker-error-message-like-below.rXdeleting a gatemp instancerNX(building ipc examples using products.makrNXbooting via qspirNXq-while-building-the-armmaster-side-code-of-image-processing-demo-i-see-a-compilation-error-message-about-std.h-as-below-when-i-make-it-with-or-without-build_localtrue.rX linux hostrNXbios-side virtqueue assertionsrNX6how to tune tcp buffer size for an optimal throughput?rNXconfidence-testrXoverviewrNX pcie bootrNXlinuxrNX ipc modulerNXipc faqrNX"when should ipc_start() be called?rNXdebugging application bootr NX"messageq allocation without a heapr!NX boot-modesr"Xbooting via emmcr#NX heapmp moduler$NXbasic fifo operation of a listr%NXinstrumentation configurationr&NX&lad reports _gatemp_ti_dgate not foundr'NXclosing a heap*mp instancer(NX installationr)Xother optional configurationsr*NX'pointing a ccs project at a rebuilt ipcr+NXipc average round trip timer,NX#installing remote core applicationsr-NX block diagramr.NXtry cleaning firstr/NX6running ndk example on arm core of keystone ii devicesr0NX&gatemp support for uio and misc driverr1NXmessageq moduler2NXmmcsdr3NXbuilding ipc examplesr4NXam655x-sbl-high-level-archr5Xother nameserver apisr6NX nand bootr7NX!how dsp local reset example worksr8NXmpm-sync-moduler9Xsee alsor:NXam655x-sbl-memory-usager;Xoptimizing code sizer<NX developmentr=NX$building timesync examples/unit testr>NXipc module apisr?NX#do you have any raw packet example?r@NX image formatsrANX#lad reports lad_connect() failed: 4rBNXmultiproc run-time apirCX}q-after-building-the-slave-code-of-the-image-processing-demo-using-ccs-where-it-needs-to-be-replaced-in-the-linux-file-systemrDX k2h/k2e/k2lrENXdriver-featuresrFXMload and unload individual cores while ipc is running (ipc 3.23.01 and above)rGNX usage notesrHNX memory usagerINXmulti-proc-manager-linux-modulerJXboot modes supportedrKNX products.makrLNXhlos loading failuresrMNXaq-is-there-any-simple-example-to-demonstrate-ipc-methods-like-message-q-or-notify-for-keystone-iirNXhow do i change the memory map?rONX0trace-from-ipc-user-libraries-ipc-3.35-and-aboverPXnimu transportrQNXboard-specific-configurationrRXrebuilding apploaderrSNX"recompiling through git repositoryrTNXam65xrUNXk2grVNXTqnx ipc driver takes a long time to load the slave executable(s) when '-g' is thrownrWNXopenclrXNXbooting via uartrYNX!source delivery and recompilationrZNX)data passing scenario (bios-to-bios only)r[NXflashing the bootloaderr\NXusager]NXbios configurationr^NXopenmpr_NX qnx buildr`NXnameserver moduleraNXqnx install guiderbNX$bios application configuration filesrcNX"binary format conversion procedurerdNX.configuring clusters with the multiproc modulereNX$reducing size of sbl and applicationrfNXmultiproc modulergNXsys/biosrhNXstart-your-openmp-projectriXchanging boot media offsetsrjNXtimesync (ptp)rkNX#binary format conversion in windowsrlNX timesync-configuration-structurermXam57xrnNXsupported platformsroNX&rtos ipc benchmark applications in sdkrpNX platformsrqNXcclinkrrNXreceiving a messagersNX boot examplertNXresource usageruNXkernel boot-up parametersrvNXq-the-image-processing-demo-does-not-work-on-the-version-of-mcsdk-v3.0x.xx.x-on-both-the-k2h-and-k2e-evms.-the-earlier-version-of-mcsdk-works-on-both-the-evms.-will-it-be-fixed-on-next-versionrwXtransport configurationrxNX5i have a question that's not answered here, what now?ryNXlinux ipc_start() failuresrzNXinstalling testsr{NXconfiguring kernelr|NXconfiguring a heap*mp moduler}NX mpm transport qmss configurationr~NXrunrNX/linux spurious "msg received with no recepient"rNXfaq for keystone devicesrNXqnxrNXndk example descriptionrNXbuilding-flash-writerrNXndkrNXrunning test applicationsrNXuartrNXtracingrNX/dynamic allocation scenario (bios-to-bios only)rNXbuilding the sblrNXshared region modulerNX#additional documentation referencesrNXipc install guidesrNXexecute-and-see-outputrX.running cc-link ie field network basic examplerNXsample examplesrNXerror handling in ipcrNX!binary format conversion in linuxrNXcclink examplerNXquerying a gatemp instancerNXbooting the targetrNXsecond-openmp-projectrXcreating a messageq objectrNX"srio serdes and lane configurationrNXentering a gatemp instancerNXbiosrNXdisabling runtime auto-suspendrNXmaking bootable sbl image (mlo)rNXipc examples: detailsrNX<q-where-do-i-look-for-the-list-of-ipc-api-reference-documentrXapisrXinterrupt map usagerNX3why a pipe creation fails and fderror() returns -1?rNXformatting the sd cardrNXuart apploaderrNXleaving a gatemp instancerNXbuilding the ndk examplesrNX,procedure to build and run linux host loaderrNXdeleting a messageq objectrNXexamplesrNXmodes-of-operationrX cleaning sblrNXproject-setup-1rXhow-to-obtain-supportrX linux/androidrNXhardware debug stepsrNXiterating over a listrNXdriversrXbootrNX)ipc module configuration (bios-side only)rNX(updating the ibl ethernet configurationsrNX transportrNXpreparing spi flashrNXeq-how-to-re-build-the-ipc---qmss-transport-library-and-generate-ti.transport.ipc.qmss.transports.ae66rX mcspi/spirNXloading test applicationrNX spi boot moderNX boot modesrNX ipc examplesrNXadditional build optionsrNXpre-requisitesrNX tftp bootrNuUsubstitution_defsr}r(X srmCfg_Img2rcdocutils.nodes substitution_definition r)r}r(U rawsourcerX.. |srmCfg_Img2| Image:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.html Uparentrcdocutils.nodes section r)r}r(jUjj)r}r(jUjj)r}r(jUjhUsourcerX\/home/gtbldadm/nightlybuilds/processor-sdk-doc/source/rtos/index_Foundational_Components.rstrUtagnamerUsectionrU attributesr}r(Udupnamesr]Uclassesr]Ubackrefsr]Uidsr]rUipcraUnamesr]rhKauUlinerKUdocumentrhUchildrenr]r(cdocutils.nodes title r)r}r(jXIPCrjjjjjUtitlerj}r(j]j]j]j]j]ujKjhj]rcdocutils.nodes Text rXIPCrr}r(jjjjubaubcdocutils.nodes note r)r}r(jXThis section mainly provides details of the software distributed part of the IPC 3.x package (installed under ipc_). The IPC package provides the IPC APIs with higher level software abstraction. In addition,starting from Processor SDK 6.1 release, a lower level IPC driver (IPC LLD) using rpmsg based transport is included specifically for AM6x/J7 platforms. See the following link for additional details `IPC 3.x vs IPC LLD`_rjjjjjUnoterj}r(j]j]j]j]j]ujNjhj]rcdocutils.nodes paragraph r)r}r(jjjjjjjU paragraphrj}r(j]j]j]j]j]ujKj]r(jXThis section mainly provides details of the software distributed part of the IPC 3.x package (installed under ipc_). The IPC package provides the IPC APIs with higher level software abstraction. In addition,starting from Processor SDK 6.1 release, a lower level IPC driver (IPC LLD) using rpmsg based transport is included specifically for AM6x/J7 platforms. See the following link for additional details rr}r(jXThis section mainly provides details of the software distributed part of the IPC 3.x package (installed under ipc_). The IPC package provides the IPC APIs with higher level software abstraction. In addition,starting from Processor SDK 6.1 release, a lower level IPC driver (IPC LLD) using rpmsg based transport is included specifically for AM6x/J7 platforms. See the following link for additional details jjubcdocutils.nodes reference r)r}r(jX`IPC 3.x vs IPC LLD`_UresolvedrKjjjU referencerj}r(UnameXIPC 3.x vs IPC LLDj]j]j]j]j]UrefidrUipc-3-x-vs-ipc-lldruj]rjXIPC 3.x vs IPC LLDrr}r(jUjjubaubeubaubj)r}r(jX?Starting with releases after the 6.3 release, IPC3.x will be deprecated on the AM65x device and IPC LLD is the only IPC stack supported. Please stop new development on top of IPC3.x for AM65x, and migrate to IPC LLD stack. Please see `IPC LLD for AM65x/J721E `_ for information on IPC LLD.r jjjjjjj}r (j]j]j]j]j]ujNjhj]r j)r }r (jj jjjjjjj}r(j]j]j]j]j]ujKj]r(jXStarting with releases after the 6.3 release, IPC3.x will be deprecated on the AM65x device and IPC LLD is the only IPC stack supported. Please stop new development on top of IPC3.x for AM65x, and migrate to IPC LLD stack. Please see rr}r(jXStarting with releases after the 6.3 release, IPC3.x will be deprecated on the AM65x device and IPC LLD is the only IPC stack supported. Please stop new development on top of IPC3.x for AM65x, and migrate to IPC LLD stack. Please see jj ubj)r}r(jX9`IPC LLD for AM65x/J721E `_j}r(UnameXIPC LLD for AM65x/J721EUrefurirXindex_device_drv.html#ipclldrj]j]j]j]j]ujj j]rjXIPC LLD for AM65x/J721Err}r(jUjjubajjubcdocutils.nodes target r)r}r(jX U referencedrKjj jUtargetr j}r!(Urefurijj]r"Uipc-lld-for-am65x-j721er#aj]j]j]j]r$h:auj]ubjX for information on IPC LLD.r%r&}r'(jX for information on IPC LLD.jj ubeubaubj)r(}r)(jUjjjjjjj}r*(j]j]j]j]r+Uipc-user-s-guider,aj]r-hfaujKjhj]r.(j)r/}r0(jXIPC User's Guider1jj(jjjjj}r2(j]j]j]j]j]ujKjhj]r3jXIPC User's Guider4r5}r6(jj1jj/ubaubcdocutils.nodes comment r7)r8}r9(jX7http://processors.wiki.ti.com/index.php/IPC_Users_Guidejj(jcdocutils.nodes reprunicode r:X=source/rtos/PDK_Platform_Software/IPC/IPC_Users_Guide.rst.incr;r<}r=bjUcommentr>j}r?(U xml:spacer@UpreserverAj]j]j]j]j]ujKjhj]rBjX7http://processors.wiki.ti.com/index.php/IPC_Users_GuiderCrD}rE(jUjj8ubaubj)rF}rG(jX.. |ipcCfg_Img| Image:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.html jj(jj<jUsubstitution_definitionrHj}rI(j]j]j]j]j]rJX ipcCfg_ImgrKaujKjhj]rLj)rM}rN(jjKj}rO(UrefuriXhhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlrPj]j]j]j]j]ujjFj]rQcdocutils.nodes image rR)rS}rT(jXImage:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlrUj}rV(UuriXrtos/../images/Book_cfg.pngrWj]j]j]j]U candidatesrX}rYU*jWsj]UaltjKujjMj]jUimagerZubajjubaubj)r[}r\(jX.. |ipcRun_Img| Image:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/index.html jj(jj<jjHj}r](j]j]j]j]j]r^X ipcRun_Imgr_aujKjhj]r`j)ra}rb(jj_j}rc(UrefuriXhhttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/index.htmlrdj]j]j]j]j]ujj[j]rejR)rf}rg(jXImage:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/index.htmlrhj}ri(UuriXrtos/../images/Book_run.pngrjj]j]j]j]jX}rkU*jjsj]Ualtj_ujjaj]jjZubajjubaubj)rl}rm(jXInter-Processor Communication (IPC) provides a processor-agnostic API which can be used for communication between processors in a multi-processor environment (inter-core), communication to other threads on same processor (inter-process), and communication to peripherals (inter-device). The API supports message passing, streams, and linked lists. IPC can be used to communicate with the following:rnjj(jj<jjj}ro(j]j]j]j]j]ujK jhj]rpjXInter-Processor Communication (IPC) provides a processor-agnostic API which can be used for communication between processors in a multi-processor environment (inter-core), communication to other threads on same processor (inter-process), and communication to peripherals (inter-device). The API supports message passing, streams, and linked lists. IPC can be used to communicate with the following:rqrr}rs(jjnjjlubaubcdocutils.nodes bullet_list rt)ru}rv(jUjj(jj<jU bullet_listrwj}rx(UbulletryX-j]j]j]j]j]ujKjhj]rz(cdocutils.nodes list_item r{)r|}r}(jX#Other threads on the same processorr~jjujj<jU list_itemrj}r(j]j]j]j]j]ujNjhj]rj)r}r(jj~jj|jj<jjj}r(j]j]j]j]j]ujKj]rjX#Other threads on the same processorrr}r(jj~jjubaubaubj{)r}r(jX,Threads on other processors running SYS/BIOSrjjujj<jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj<jjj}r(j]j]j]j]j]ujKj]rjX,Threads on other processors running SYS/BIOSrr}r(jjjjubaubaubj{)r}r(jXHThreads on other processors running an HLOS (e.g., Linux, QNX, Android) jjujj<jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXGThreads on other processors running an HLOS (e.g., Linux, QNX, Android)rjjjj<jjj}r(j]j]j]j]j]ujKj]rjXGThreads on other processors running an HLOS (e.g., Linux, QNX, Android)rr}r(jjjjubaubaubeubjR)r}r(jX+.. image:: ../images/IPC_comm_features.JPG jj(jj<jjZj}r(UuriX$rtos/../images/IPC_comm_features.JPGrj]j]j]j]jX}rU*jsj]ujKjhj]ubeubj)r}r(jUjKjjjj<jjj}r(j]rXoverviewraj]j]j]rUoverviewraj]ujKjhj]r(j)r}r(jXOverviewrjjjj<jjj}r(j]j]j]j]j]ujKjhj]rjXOverviewrr}r(jjjjubaubj)r}r(jXThis user's guide contains the topics in the following list. It also links to API reference documentation for static configuration (|ipcCfg_Img|) and run-time C processing (|ipcRun_Img|) for each module.jjjj<jjj}r(j]j]j]j]j]ujKjhj]r(jXThis user's guide contains the topics in the following list. It also links to API reference documentation for static configuration (rr}r(jXThis user's guide contains the topics in the following list. It also links to API reference documentation for static configuration (jjubj)r}r(jjKjjjNjjj}r(UrefurijPj]j]j]j]j]ujNjhj]rjR)r}r(jjUjjjNjjZj}r(UuriXrtos/../images/Book_cfg.pngrj]j]j]j]jX}rU*jsj]UaltjKujNj]ubaubjX) and run-time C processing (rr}r(jX) and run-time C processing (jjubj)r}r(jj_jjjNjjj}r(Urefurijdj]j]j]j]j]ujNjhj]rjR)r}r(jjhjjjNjjZj}r(UuriXrtos/../images/Book_run.pngrj]j]j]j]jX}rU*jsj]Ualtj_ujNj]ubaubjX) for each module.rr}r(jX) for each module.jjubeubj)r}r(jX**Getting Started**rjjjj<jjj}r(j]j]j]j]j]ujKjhj]rcdocutils.nodes strong r)r}r(jjj}r(j]j]j]j]j]ujjj]rjXGetting Startedrr}r(jUjjubajUstrongrubaubjt)r}r(jUjjjj<jjwj}r(jyX-j]j]j]j]j]ujKjhj]r(j{)r}r(jXu`Use Cases for IPC `__ explains the various use cases for IPC. jjjj<jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXt`Use Cases for IPC `__ explains the various use cases for IPC.jjjj<jjj}r(j]j]j]j]j]ujKj]r(j)r}r(jXL`Use Cases for IPC `__j}r(UnameXUse Cases for IPCjX4index_Foundational_Components.html#use-cases-for-ipcj]j]j]j]j]ujjj]rjXUse Cases for IPCrr}r(jUjjubajjubjX( explains the various use cases for IPC.rr}r(jX( explains the various use cases for IPC.jjubeubaubj{)r}r(jXx`IPC Examples `__ explains how to build and generate the IPC examples. jjjj<jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXw`IPC Examples `__ explains how to build and generate the IPC examples.jjjj<jjj}r(j]j]j]j]j]ujKj]r(j)r}r(jXB`IPC Examples `__j}r(UnameX IPC ExamplesjX/index_Foundational_Components.html#ipc-examplesj]j]j]j]j]ujjj]rjX IPC Examplesrr}r(jUjjubajjubjX5 explains how to build and generate the IPC examples.rr }r (jX5 explains how to build and generate the IPC examples.jjubeubaubj{)r }r (jXa`IPC Training `__ lists available IPC training. jjjj<jjj}r (j]j]j]j]j]ujNjhj]rj)r}r(jX``IPC Training `__ lists available IPC training.jj jj<jjj}r(j]j]j]j]j]ujK!j]r(j)r}r(jXB`IPC Training `__j}r(UnameX IPC TrainingjX/index_Foundational_Components.html#ipc-trainingj]j]j]j]j]ujjj]rjX IPC Trainingrr}r(jUjjubajjubjX lists available IPC training.rr}r(jX lists available IPC training.jjubeubaubj{)r}r(jX^`IPC 3.x `__ Provides details of IPC 3.x releases jjjj<jjj}r(j]j]j]j]j]ujNjhj]r j)r!}r"(jX]`IPC 3.x `__ Provides details of IPC 3.x releasesjjjj<jjj}r#(j]j]j]j]j]ujK#j]r$(j)r%}r&(jX8`IPC 3.x `__j}r'(UnameXIPC 3.xjX*index_Foundational_Components.html#ipc-3-xj]j]j]j]j]ujj!j]r(jXIPC 3.xr)r*}r+(jUjj%ubajjubjX% Provides details of IPC 3.x releasesr,r-}r.(jX% Provides details of IPC 3.x releasesjj!ubeubaubj{)r/}r0(jX`Run IPC Examples on AM572x `__ jjjj<jjj}r1(j]j]j]j]j]ujNjhj]r2j)r3}r4(jX`Run IPC Examples on AM572x `__r5jj/jj<jjj}r6(j]j]j]j]j]ujK&j]r7j)r8}r9(jj5j}r:(UnameXRun IPC Examples on AM572xjXuhttp://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_how_to_guides.html#run-ipc-examples-on-am572xj]j]j]j]j]ujj3j]r;jXRun IPC Examples on AM572xr<r=}r>(jUjj8ubajjubaubaubj{)r?}r@(jX`Run IPC Examples on AM65xx `__ jjjj<jjj}rA(j]j]j]j]j]ujNjhj]rBj)rC}rD(jX`Run IPC Examples on AM65xx `__rEjj?jj<jjj}rF(j]j]j]j]j]ujK(j]rGj)rH}rI(jjEj}rJ(UnameXRun IPC Examples on AM65xxjXuhttp://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_how_to_guides.html#run-ipc-examples-on-am65xxj]j]j]j]j]ujjCj]rKjXRun IPC Examples on AM65xxrLrM}rN(jUjjHubajjubaubaubeubj)rO}rP(jX**Application Development**rQjjjj<jjj}rR(j]j]j]j]j]ujK*jhj]rSj)rT}rU(jjQj}rV(j]j]j]j]j]ujjOj]rWjXApplication DevelopmentrXrY}rZ(jUjjTubajjubaubjt)r[}r\(jUjjjj<jjwj}r](jyX-j]j]j]j]j]ujK,jhj]r^(j{)r_}r`(jX`Create DSP and IPU firmware using PDK drivers and IPC to load from ARM Linux on AM57xx devices `__ jj[jj<jjj}ra(j]j]j]j]j]ujNjhj]rbj)rc}rd(jX`Create DSP and IPU firmware using PDK drivers and IPC to load from ARM Linux on AM57xx devices `__rejj_jj<jjj}rf(j]j]j]j]j]ujK,j]rgj)rh}ri(jjej}rj(UnameX^Create DSP and IPU firmware using PDK drivers and IPC to load from ARM Linux on AM57xx devicesjXhttp://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/How_to_Guides.html#create-dsp-and-ipu-firmware-using-pdk-drivers-and-ipc-to-load-from-arm-linux-on-am57xx-devicesj]j]j]j]j]ujjcj]rkjX^Create DSP and IPU firmware using PDK drivers and IPC to load from ARM Linux on AM57xx devicesrlrm}rn(jUjjhubajjubaubaubj{)ro}rp(jX`Customizing Memory map for creating Multicore Applications on AM57xx using IPC `__ jj[jj<jjj}rq(j]j]j]j]j]ujNjhj]rrj)rs}rt(jX`Customizing Memory map for creating Multicore Applications on AM57xx using IPC `__rujjojj<jjj}rv(j]j]j]j]j]ujK.j]rwj)rx}ry(jjuj}rz(UnameXNCustomizing Memory map for creating Multicore Applications on AM57xx using IPCjXhttp://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/How_to_Guides.html#customizing-memory-map-for-creating-multicore-applications-on-am57xx-using-ipcj]j]j]j]j]ujjsj]r{jXNCustomizing Memory map for creating Multicore Applications on AM57xx using IPCr|r}}r~(jUjjxubajjubaubaubj{)r}r(jX`Optimizing IPC Applications `__ provides hints for improving the runtime performance and shared memory usage of applications that use IPC. jj[jj<jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX`Optimizing IPC Applications `__ provides hints for improving the runtime performance and shared memory usage of applications that use IPC.jjjj<jjj}r(j]j]j]j]j]ujK0j]r(j)r}r(jX``Optimizing IPC Applications `__j}r(UnameXOptimizing IPC ApplicationsjX>index_Foundational_Components.html#optimizing-ipc-applicationsj]j]j]j]j]ujjj]rjXOptimizing IPC Applicationsrr}r(jUjjubajjubjXk provides hints for improving the runtime performance and shared memory usage of applications that use IPC.rr}r(jXk provides hints for improving the runtime performance and shared memory usage of applications that use IPC.jjubeubaubj{)r}r(jXi`IPC Benchmarking `__ IPC Benchmarking with IPC 3.x jj[jj<jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXh`IPC Benchmarking `__ IPC Benchmarking with IPC 3.xjjjj<jjj}r(j]j]j]j]j]ujK5j]r(j)r}r(jXJ`IPC Benchmarking `__j}r(UnameXIPC BenchmarkingjX3index_Foundational_Components.html#ipc-benchmarkingj]j]j]j]j]ujjj]rjXIPC Benchmarkingrr}r(jUjjubajjubjX IPC Benchmarking with IPC 3.xrr}r(jX IPC Benchmarking with IPC 3.xjjubeubaubj{)r}r(jX`IPC Custom ResourceTable `__ Provides details of customizing the resource table. jj[jj<jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX`IPC Custom ResourceTable `__ Provides details of customizing the resource table.jjjj<jjj}r(j]j]j]j]j]ujK9j]r(j)r}r(jXW`IPC Custom ResourceTable `__j}r(UnameXIPC Custom ResourceTablejX8index_Foundational_Components.html#resource-custom-tablej]j]j]j]j]ujjj]rjXIPC Custom ResourceTablerr}r(jUjjubajjubjX4 Provides details of customizing the resource table.rr}r(jX4 Provides details of customizing the resource table.jjubeubaubj{)r}r(jX`IPC Debugging Tools and Techniques on AM57xx `__ jj[jj<jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX`IPC Debugging Tools and Techniques on AM57xx `__rjjjj<jjj}r(j]j]j]j]j]ujK=j]rj)r}r(jjj}r(UnameX,IPC Debugging Tools and Techniques on AM57xxjXhttp://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/How_to_Guides.html#ipc-debugging-tools-and-techniques-on-am57xxj]j]j]j]j]ujjj]rjX,IPC Debugging Tools and Techniques on AM57xxrr}r(jUjjubajjubaubaubeubj)r}r(jX)**IPC Internal/API & Other Useful Links**rjjjj<jjj}r(j]j]j]j]j]ujK?jhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX%IPC Internal/API & Other Useful Linksrr}r(jUjjubajjubaubjt)r}r(jUjjjj<jjwj}r(jyX-j]j]j]j]j]ujKAjhj]r(j{)r}r(jX`The TI SDO IPC Package `__ section describes the modules in the ti.sdo.ipc package. jjjj<jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX`The TI SDO IPC Package `__ section describes the modules in the ti.sdo.ipc package.jjjj<jjj}r(j]j]j]j]j]ujKAj]r(j)r}r(jXR`The TI SDO IPC Package `__j}r(UnameXThe TI SDO IPC PackagejX5index_Foundational_Components.html#ti-sdo-ipc-packagej]j]j]j]j]ujjj]rjXThe TI SDO IPC Packagerr}r(jUjjubajjubjX9 section describes the modules in the ti.sdo.ipc package.rr}r(jX9 section describes the modules in the ti.sdo.ipc package.jjubeubaubj{)r}r(jX`The TI SDO Utils Package `__ section describes the modules in the ti.sdo.utils package. jjjj<jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX`The TI SDO Utils Package `__ section describes the modules in the ti.sdo.utils package.jjjj<jjj}r(j]j]j]j]j]ujKDj]r(j)r}r(jXV`The TI SDO Utils Package `__j}r(UnameXThe TI SDO Utils PackagejX7index_Foundational_Components.html#ti-sdo-utils-packagej]j]j]j]j]ujjj]rjXThe TI SDO Utils Packagerr}r(jUjjubajjubjX; section describes the modules in the ti.sdo.utils package.rr}r(jX; section describes the modules in the ti.sdo.utils package.jjubeubaubj{)r}r(jX`IPC 3.x Migration Guide `__ Provides details of migrating to IPC 3.x from previous releases jjjj<jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX`IPC 3.x Migration Guide `__ Provides details of migrating to IPC 3.x from previous releasesjjjj<jjj}r(j]j]j]j]j]ujKGj]r(j)r}r(jX]`IPC 3.x Migration Guide `__j}r(UnameXIPC 3.x Migration GuidejX?http://processors.wiki.ti.com/index.php/IPC_3.x_Migration_Guidej]j]j]j]j]ujjj]rjXIPC 3.x Migration Guiderr}r(jUjjubajjubjX@ Provides details of migrating to IPC 3.x from previous releasesrr }r (jX@ Provides details of migrating to IPC 3.x from previous releasesjjubeubaubj{)r }r (jX`IPC GateMP Support for UIO and Misc Driver `__ Provides details of IPC GateMP support with UIO driver jjjj<jjj}r (j]j]j]j]j]ujNjhj]rj)r}r(jX`IPC GateMP Support for UIO and Misc Driver `__ Provides details of IPC GateMP support with UIO driverjj jj<jjj}r(j]j]j]j]j]ujKKj]r(j)r}r(jXz`IPC GateMP Support for UIO and Misc Driver `__j}r(UnameX*IPC GateMP Support for UIO and Misc DriverjXIindex_Foundational_Components.html#gatemp-support-for-uio-and-misc-driverj]j]j]j]j]ujjj]rjX*IPC GateMP Support for UIO and Misc Driverrr}r(jUjjubajjubjX7 Provides details of IPC GateMP support with UIO driverrr}r(jX7 Provides details of IPC GateMP support with UIO driverjjubeubaubj{)r}r(jX`RTOS IPC Transports `__ explains details of the additional RTOS IPC transports provided via the Processor SDK PDK component. jjjj<jjj}r(j]j]j]j]j]ujNjhj]r j)r!}r"(jX`RTOS IPC Transports `__ explains details of the additional RTOS IPC transports provided via the Processor SDK PDK component.jjjj<jjj}r#(j]j]j]j]j]ujKOj]r$(j)r%}r&(jXK`RTOS IPC Transports `__j}r'(UnameXRTOS IPC TransportsjX1index_Foundational_Components.html#ipc-transportsj]j]j]j]j]ujj!j]r(jXRTOS IPC Transportsr)r*}r+(jUjj%ubajjubjXe explains details of the additional RTOS IPC transports provided via the Processor SDK PDK component.r,r-}r.(jXe explains details of the additional RTOS IPC transports provided via the Processor SDK PDK component.jj!ubeubaubj{)r/}r0(jX`Rebuilding IPC `__ explains how to rebuild the IPC libraries if you modify the source files. jjjj<jjj}r1(j]j]j]j]j]ujNjhj]r2j)r3}r4(jX`Rebuilding IPC `__ explains how to rebuild the IPC libraries if you modify the source files.jj/jj<jjj}r5(j]j]j]j]j]ujKTj]r6(j)r7}r8(jXF`Rebuilding IPC `__j}r9(UnameXRebuilding IPCjX1index_Foundational_Components.html#rebuilding-ipcj]j]j]j]j]ujj3j]r:jXRebuilding IPCr;r<}r=(jUjj7ubajjubjXJ explains how to rebuild the IPC libraries if you modify the source files.r>r?}r@(jXJ explains how to rebuild the IPC libraries if you modify the source files.jj3ubeubaubeubj)rA}rB(jX**FAQ**rCjjjj<jjj}rD(j]j]j]j]j]ujKXjhj]rEj)rF}rG(jjCj}rH(j]j]j]j]j]ujjAj]rIjXFAQrJrK}rL(jUjjFubajjubaubjt)rM}rN(jUjjjj<jjwj}rO(jyX-j]j]j]j]j]ujKZjhj]rPj{)rQ}rR(jXc`IPC 3.x FAQ `__ Frequently asked questions on IPC 3.x jjMjj<jjj}rS(j]j]j]j]j]ujNjhj]rTj)rU}rV(jXb`IPC 3.x FAQ `__ Frequently asked questions on IPC 3.xjjQjj<jjj}rW(j]j]j]j]j]ujKZj]rX(j)rY}rZ(jX<`IPC 3.x FAQ `__j}r[(UnameX IPC 3.x FAQjX*index_Foundational_Components.html#ipc-faqj]j]j]j]j]ujjUj]r\jX IPC 3.x FAQr]r^}r_(jUjjYubajjubjX& Frequently asked questions on IPC 3.xr`ra}rb(jX& Frequently asked questions on IPC 3.xjjUubeubaubaubcdocutils.nodes line_block rc)rd}re(jUjjjj<jU line_blockrfj}rg(j]j]j]j]j]ujK^jhj]rhcdocutils.nodes line ri)rj}rk(jUUindentrlKjjdjj<jjj}rm(j]j]j]j]j]ujKjhj]ubaubj)rn}ro(jXPlease see the release notes in your IPC installation before starting to use IPC. The release notes contain important information about feature support, issues, and compatibility information for a particular release.jjjj<jjj}rp(j]j]j]j]j]ujNjhj]rqj)rr}rs(jXPlease see the release notes in your IPC installation before starting to use IPC. The release notes contain important information about feature support, issues, and compatibility information for a particular release.rtjjnjj<jjj}ru(j]j]j]j]j]ujKaj]rvjXPlease see the release notes in your IPC installation before starting to use IPC. The release notes contain important information about feature support, issues, and compatibility information for a particular release.rwrx}ry(jjtjjrubaubaubjc)rz}r{(jUjjjj<jjfj}r|(j]j]j]j]j]ujKejhj]r}ji)r~}r(jUjlKjjzjj<jjj}r(j]j]j]j]j]ujKjhj]ubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rUuse-cases-for-ipcraj]rhaujKjhj]r(j)r}r(jXUse Cases for IPCrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXUse Cases for IPCrr}r(jjjjubaubj7)r}r(jXIhttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/Use_Cases_for_IPCjjjj:X?source/rtos/PDK_Platform_Software/IPC/Use_Cases_for_IPC.rst.incrr}rbjj>j}r(j@jAj]j]j]j]j]ujKjhj]rjXIhttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/Use_Cases_for_IPCrr}r(jUjjubaubj)r}r(jXYou can use IPC modules in a variety of combinations. From the simplest setup to the setup with the most functionality, the use case options are as follows. A number of variations of these cases are also possible:rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXYou can use IPC modules in a variety of combinations. From the simplest setup to the setup with the most functionality, the use case options are as follows. A number of variations of these cases are also possible:rr}r(jjjjubaubjt)r}r(jUjjjjjjwj}r(jyX-j]j]j]j]j]ujKjhj]r(j{)r}r(jXM**Minimal use of IPC. (BIOS-to-BIOS only)** This scenario performs inter-processor notification. The amount of data passed with a notification is minimal--typically on the order of 32 bits. This scenario is best used for simple synchronization between processors without the overhead and complexity of message-passing infrastructure.jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXM**Minimal use of IPC. (BIOS-to-BIOS only)** This scenario performs inter-processor notification. The amount of data passed with a notification is minimal--typically on the order of 32 bits. This scenario is best used for simple synchronization between processors without the overhead and complexity of message-passing infrastructure.jjjjjjj}r(j]j]j]j]j]ujKj]r(j)r}r(jX+**Minimal use of IPC. (BIOS-to-BIOS only)**j}r(j]j]j]j]j]ujjj]rjX'Minimal use of IPC. (BIOS-to-BIOS only)rr}r(jUjjubajjubjX" This scenario performs inter-processor notification. The amount of data passed with a notification is minimal--typically on the order of 32 bits. This scenario is best used for simple synchronization between processors without the overhead and complexity of message-passing infrastructure.rr}r(jX" This scenario performs inter-processor notification. The amount of data passed with a notification is minimal--typically on the order of 32 bits. This scenario is best used for simple synchronization between processors without the overhead and complexity of message-passing infrastructure.jjubeubaubj{)r}r(jX**Add data passing. (BIOS-to-BIOS only)** This scenario adds the ability to pass linked list elements between processors to the previous minimal scenario. The linked list implementation may optionally use shared memory and/or gates to manage synchronization.jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX**Add data passing. (BIOS-to-BIOS only)** This scenario adds the ability to pass linked list elements between processors to the previous minimal scenario. The linked list implementation may optionally use shared memory and/or gates to manage synchronization.jjjjjjj}r(j]j]j]j]j]ujK j]r(j)r}r(jX)**Add data passing. (BIOS-to-BIOS only)**j}r(j]j]j]j]j]ujjj]rjX%Add data passing. (BIOS-to-BIOS only)rr}r(jUjjubajjubjX This scenario adds the ability to pass linked list elements between processors to the previous minimal scenario. The linked list implementation may optionally use shared memory and/or gates to manage synchronization.rr}r(jX This scenario adds the ability to pass linked list elements between processors to the previous minimal scenario. The linked list implementation may optionally use shared memory and/or gates to manage synchronization.jjubeubaubj{)r}r(jX**Add dynamic allocation. (BIOS-to-BIOS only)** This scenario adds the ability to dynamically allocate linked list elements from a heap.jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX**Add dynamic allocation. (BIOS-to-BIOS only)** This scenario adds the ability to dynamically allocate linked list elements from a heap.jjjjjjj}r(j]j]j]j]j]ujKj]r(j)r}r(jX/**Add dynamic allocation. (BIOS-to-BIOS only)**j}r(j]j]j]j]j]ujjj]rjX+Add dynamic allocation. (BIOS-to-BIOS only)rr}r(jUjjubajjubjXY This scenario adds the ability to dynamically allocate linked list elements from a heap.rr}r(jXY This scenario adds the ability to dynamically allocate linked list elements from a heap.jjubeubaubj{)r}r(jX **Powerful but easy-to-use messaging. (HLOS and BIOS)** This scenario uses the MessageQ module for messaging. The application configures other modules. However, the APIs for other modules are then used internally by MessageQ, rather than directly by the application. jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX **Powerful but easy-to-use messaging. (HLOS and BIOS)** This scenario uses the MessageQ module for messaging. The application configures other modules. However, the APIs for other modules are then used internally by MessageQ, rather than directly by the application.jjjjjjj}r(j]j]j]j]j]ujKj]r(j)r}r(jX7**Powerful but easy-to-use messaging. (HLOS and BIOS)**j}r(j]j]j]j]j]ujjj]rjX3Powerful but easy-to-use messaging. (HLOS and BIOS)rr}r(jUjjubajjubjX This scenario uses the MessageQ module for messaging. The application configures other modules. However, the APIs for other modules are then used internally by MessageQ, rather than directly by the application.rr}r(jX This scenario uses the MessageQ module for messaging. The application configures other modules. However, the APIs for other modules are then used internally by MessageQ, rather than directly by the application.jjubeubaubeubj)r}r(jXFIn the following sections, figures show modules used by each scenario.rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXFIn the following sections, figures show modules used by each scenario.rr}r(jjjjubaubjt)r}r(jUjjjjjjwj}r(jyX-j]j]j]j]j]ujKjhj]r(j{)r}r(jX:raw-html:`Blue boxes,` identify modules for which your application will call C API functions other than those used to dynamically create objects.rjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujKj]r(cdocutils.nodes raw r)r}r(jX1:raw-html:`Blue boxes,`jjjjjUrawrj}r(Uformatj:Xhtmlrr }r bj@jAj]j]j]j]r Uraw-htmlr aj]ujKj]r jX%Blue boxes,rr}r(jUjjubaubjX{ identify modules for which your application will call C API functions other than those used to dynamically create objects.rr}r(jX{ identify modules for which your application will call C API functions other than those used to dynamically create objects.jjubeubaubj{)r}r(jX:raw-html:`Red boxes,` identify modules that require only configuration by your application. Static configuration is performed in an XDCtools configuration script (.cfg). Dynamic configuration is performed in C code.rjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujKj]r(j)r}r(jX/:raw-html:`Red boxes,`jjjjjjj}r(Uformatj j@jAj]j]j]j]r j aj]ujKj]r!jX#Red boxes,r"r#}r$(jUjjubaubjX identify modules that require only configuration by your application. Static configuration is performed in an XDCtools configuration script (.cfg). Dynamic configuration is performed in C code.r%r&}r'(jX identify modules that require only configuration by your application. Static configuration is performed in an XDCtools configuration script (.cfg). Dynamic configuration is performed in C code.jjubeubaubj{)r(}r)(jX:raw-html:`Grey boxes,` identify modules that are used internally but do not need to be configured or have their APIs called. jjjjjjj}r*(j]j]j]j]j]ujNjhj]r+j)r,}r-(jX:raw-html:`Grey boxes,` identify modules that are used internally but do not need to be configured or have their APIs called.jj(jjjjj}r.(j]j]j]j]j]ujKj]r/(j)r0}r1(jX1:raw-html:`Grey boxes,`jj,jjjjj}r2(Uformatj j@jAj]j]j]j]r3j aj]ujKj]r4jX%Grey boxes,r5r6}r7(jUjj0ubaubjXf identify modules that are used internally but do not need to be configured or have their APIs called.r8r9}r:(jXf identify modules that are used internally but do not need to be configured or have their APIs called.jj,ubeubaubeubj)r;}r<(jUjjjjjjj}r=(j]j]j]j]r>U&minimal-use-scenario-bios-to-bios-onlyr?aj]r@hTaujK"jhj]rA(j)rB}rC(jX(Minimal Use Scenario (BIOS-to-BIOS only)rDjj;jjjjj}rE(j]j]j]j]j]ujK"jhj]rFjX(Minimal Use Scenario (BIOS-to-BIOS only)rGrH}rI(jjDjjBubaubj)rJ}rK(jXFThis scenario performs inter-processor notification using a Notify driver, which is used by the Notify module. This scenario is best used for simple synchronization in which you want to send a message to another processor to tell it to perform some action and optionally have it notify the first processor when it is finished.rLjj;jjjjj}rM(j]j]j]j]j]ujK$jhj]rNjXFThis scenario performs inter-processor notification using a Notify driver, which is used by the Notify module. This scenario is best used for simple synchronization in which you want to send a message to another processor to tell it to perform some action and optionally have it notify the first processor when it is finished.rOrP}rQ(jjLjjJubaubjR)rR}rS(jX*.. Image:: ../images/IpcUG_over_1_2_1.png jj;jjjjZj}rT(UuriX#rtos/../images/IpcUG_over_1_2_1.pngrUj]j]j]j]jX}rVU*jUsj]ujK+jhj]ubj)rW}rX(jXIn this scenario, you make API calls to the Notify module. For example, the Notify_sendEvent() function sends an event to the specified processor. You can dynamically register callback functions with the Notify module to handle such events.rYjj;jjjjj}rZ(j]j]j]j]j]ujK,jhj]r[jXIn this scenario, you make API calls to the Notify module. For example, the Notify_sendEvent() function sends an event to the specified processor. You can dynamically register callback functions with the Notify module to handle such events.r\r]}r^(jjYjjWubaubj)r_}r`(jX_You must statically configure MultiProc module properties, which are used by the Notify module.rajj;jjjjj}rb(j]j]j]j]j]ujK1jhj]rcjX_You must statically configure MultiProc module properties, which are used by the Notify module.rdre}rf(jjajj_ubaubj)rg}rh(jXThe amount of data passed with a notification is minimal. You can send an event number, which is typically used by the callback function to determine what action it needs to perform. Optionally, a small "payload"? of data can also be sent.rijj;jjjjj}rj(j]j]j]j]j]ujK4jhj]rkjXThe amount of data passed with a notification is minimal. You can send an event number, which is typically used by the callback function to determine what action it needs to perform. Optionally, a small "payload"? of data can also be sent.rlrm}rn(jjijjgubaubj)ro}rp(jXSee `Notify Module `__ and `MultiProc Module `__.jj;jjjjj}rq(j]j]j]j]j]ujK9jhj]rr(jXSee rsrt}ru(jXSee jjoubj)rv}rw(jXD`Notify Module `__j}rx(UnameX Notify ModulejX0index_Foundational_Components.html#notify-modulej]j]j]j]j]ujjoj]ryjX Notify Modulerzr{}r|(jUjjvubajjubjX and r}r~}r(jX and jjoubj)r}r(jXJ`MultiProc Module `__j}r(UnameXMultiProc ModulejX3index_Foundational_Components.html#multiproc-modulej]j]j]j]j]ujjoj]rjXMultiProc Modulerr}r(jUjjubajjubjX.r}r(jX.jjoubeubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rU'data-passing-scenario-bios-to-bios-onlyraj]rj[aujK>jhj]r(j)r}r(jX)Data Passing Scenario (BIOS-to-BIOS only)rjjjjjjj}r(j]j]j]j]j]ujK>jhj]rjX)Data Passing Scenario (BIOS-to-BIOS only)rr}r(jjjjubaubj)r}r(jXIn addition to the IPC modules used in the previous scenario, you can use the ListMP module to share a linked list between processors.rjjjjjjj}r(j]j]j]j]j]ujK@jhj]rjXIn addition to the IPC modules used in the previous scenario, you can use the ListMP module to share a linked list between processors.rr}r(jjjjubaubjR)r}r(jX*.. Image:: ../images/IpcUG_over_1_2_2.png jjjjjjZj}r(UuriX#rtos/../images/IpcUG_over_1_2_2.pngrj]j]j]j]jX}rU*jsj]ujKDjhj]ubj)r}r(jXFIn this scenario, you make API calls to the Notify and ListMP modules.rjjjjjjj}r(j]j]j]j]j]ujKEjhj]rjXFIn this scenario, you make API calls to the Notify and ListMP modules.rr}r(jjjjubaubj)r}r(jXThe ListMP module is a doubly-linked-list designed to be shared by multiple processors. ListMP differs from a conventional "local"? linked list in the following ways:rjjjjjjj}r(j]j]j]j]j]ujKGjhj]rjXThe ListMP module is a doubly-linked-list designed to be shared by multiple processors. ListMP differs from a conventional "local"? linked list in the following ways:rr}r(jjjjubaubjt)r}r(jUjjjjjjwj}r(jyX-j]j]j]j]j]ujKKjhj]r(j{)r}r(jX^Address translation is performed internally upon pointers contained within the data structure.jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX^Address translation is performed internally upon pointers contained within the data structure.rjjjjjjj}r(j]j]j]j]j]ujKKj]rjX^Address translation is performed internally upon pointers contained within the data structure.rr}r(jjjjubaubaubj{)r}r(jXGCache coherency is maintained when the cacheable shared memory is used.jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXGCache coherency is maintained when the cacheable shared memory is used.rjjjjjjj}r(j]j]j]j]j]ujKMj]rjXGCache coherency is maintained when the cacheable shared memory is used.rr}r(jjjjubaubaubj{)r}r(jXnA multi-processor gate (GateMP) is used to protect read/write accesses to the list by two or more processors. jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXmA multi-processor gate (GateMP) is used to protect read/write accesses to the list by two or more processors.rjjjjjjj}r(j]j]j]j]j]ujKOj]rjXmA multi-processor gate (GateMP) is used to protect read/write accesses to the list by two or more processors.rr}r(jjjjubaubaubeubj)r}r(jXListMP uses SharedRegion's lookup table to manage access to shared memory, so configuration of the SharedRegion module is required.rjjjjjjj}r(j]j]j]j]j]ujKRjhj]rjXListMP uses SharedRegion's lookup table to manage access to shared memory, so configuration of the SharedRegion module is required.rr}r(jjjjubaubj)r}r(jXInternally, ListMP can optionally use the NameServer module to manage name/value pairs. The ListMP module also uses a GateMP object, which your application must configure. The GateMP is used internally to synchronize access to the list elements.rjjjjjjj}r(j]j]j]j]j]ujKUjhj]rjXInternally, ListMP can optionally use the NameServer module to manage name/value pairs. The ListMP module also uses a GateMP object, which your application must configure. The GateMP is used internally to synchronize access to the list elements.rr}r(jjjjubaubj)r}r(jX4See `ListMP Module `__, `GateMP Module `__, `SharedRegion Module `__, and `NameServer Module `__.jjjjjjj}r(j]j]j]j]j]ujKZjhj]r(jXSee rr}r(jXSee jjubj)r}r(jXD`ListMP Module `__j}r(UnameX ListMP ModulejX0index_Foundational_Components.html#listmp-modulej]j]j]j]j]ujjj]rjX ListMP Modulerr}r(jUjjubajjubjX, rr}r(jX, jjubj)r}r(jXD`GateMP Module `__j}r(UnameX GateMP ModulejX0index_Foundational_Components.html#gatemp-modulej]j]j]j]j]ujjj]rjX GateMP Modulerr}r(jUjjubajjubjX, rr}r(jX, jjubj)r}r (jXQ`SharedRegion Module `__j}r (UnameXSharedRegion ModulejX7index_Foundational_Components.html#shared-region-modulej]j]j]j]j]ujjj]r jXSharedRegion Moduler r }r(jUjjubajjubjX, and rr}r(jX, and jjubj)r}r(jXL`NameServer Module `__j}r(UnameXNameServer ModulejX4index_Foundational_Components.html#nameserver-modulej]j]j]j]j]ujjj]rjXNameServer Modulerr}r(jUjjubajjubjX.r}r(jX.jjubeubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rU-dynamic-allocation-scenario-bios-to-bios-onlyraj]r jaujKbjhj]r!(j)r"}r#(jX/Dynamic Allocation Scenario (BIOS-to-BIOS only)r$jjjjjjj}r%(j]j]j]j]j]ujKbjhj]r&jX/Dynamic Allocation Scenario (BIOS-to-BIOS only)r'r(}r)(jj$jj"ubaubj)r*}r+(jXmTo the previous scenario, you can add dynamic allocation of ListMP elements using one of the Heap*MP modules.r,jjjjjjj}r-(j]j]j]j]j]ujKdjhj]r.jXmTo the previous scenario, you can add dynamic allocation of ListMP elements using one of the Heap*MP modules.r/r0}r1(jj,jj*ubaubjR)r2}r3(jX*.. Image:: ../images/IpcUG_over_1_2_3.png jjjjjjZj}r4(UuriX#rtos/../images/IpcUG_over_1_2_3.pngr5j]j]j]j]jX}r6U*j5sj]ujKhjhj]ubj)r7}r8(jX[In this scenario, you make API calls to the Notify and ListMP modules and a Heap*MP module.r9jjjjjjj}r:(j]j]j]j]j]ujKijhj]r;jX[In this scenario, you make API calls to the Notify and ListMP modules and a Heap*MP module.r<r=}r>(jj9jj7ubaubj)r?}r@(jXIn addition to the modules that you configured for the previous scenario, the Heap*MP modules use a GateMP that you must configure. You may use the same GateMP instance used by ListMP.rAjjjjjjj}rB(j]j]j]j]j]ujKljhj]rCjXIn addition to the modules that you configured for the previous scenario, the Heap*MP modules use a GateMP that you must configure. You may use the same GateMP instance used by ListMP.rDrE}rF(jjAjj?ubaubj)rG}rH(jXSee `Heap*MP Modules `__ and `GateMP Module `__.jjjjjjj}rI(j]j]j]j]j]ujKpjhj]rJ(jXSee rKrL}rM(jXSee jjGubj)rN}rO(jXF`Heap*MP Modules `__j}rP(UnameXHeap*MP ModulesjX0index_Foundational_Components.html#heapmp-modulej]j]j]j]j]ujjGj]rQjXHeap*MP ModulesrRrS}rT(jUjjNubajjubjX and rUrV}rW(jX and jjGubj)rX}rY(jXD`GateMP Module `__j}rZ(UnameX GateMP ModulejX0index_Foundational_Components.html#gatemp-modulej]j]j]j]j]ujjGj]r[jX GateMP Moduler\r]}r^(jUjjXubajjubjX.r_}r`(jX.jjGubeubeubj)ra}rb(jUjjjjjjj}rc(j]j]j]j]rdU>powerful-but-easy-to-use-messaging-with-messageq-hlos-and-biosreaj]rfh;aujKujhj]rg(j)rh}ri(jX@Powerful But Easy-to-Use Messaging with MessageQ (HLOS and BIOS)rjjjajjjjj}rk(j]j]j]j]j]ujKujhj]rljX@Powerful But Easy-to-Use Messaging with MessageQ (HLOS and BIOS)rmrn}ro(jjjjjhubaubj)rp}rq(jXFinally, to use the most sophisticated inter-processor communication scenario supported by IPC, you can add the MessageQ module. Note that the following diagram shows one particular transport (TransportShm) and may not apply to all devices and/or environments.rrjjajjjjj}rs(j]j]j]j]j]ujKwjhj]rtjXFinally, to use the most sophisticated inter-processor communication scenario supported by IPC, you can add the MessageQ module. Note that the following diagram shows one particular transport (TransportShm) and may not apply to all devices and/or environments.rurv}rw(jjrjjpubaubjR)rx}ry(jX*.. Image:: ../images/IpcUG_over_1_2_4.png jjajjjjZj}rz(UuriX#rtos/../images/IpcUG_over_1_2_4.pngr{j]j]j]j]jX}r|U*j{sj]ujK}jhj]ubj)r}}r~(jX^In this scenario, you make API calls to the MessageQ module for inter-processor communication.rjjajjjjj}r(j]j]j]j]j]ujK~jhj]rjX^In this scenario, you make API calls to the MessageQ module for inter-processor communication.rr}r(jjjj}ubaubj)r}r(jXAPI calls made to the Notify, ListMP, and Heap*MP modules in the previous scenarios are not needed. Instead, your application only needs to configure the MultiProc and (if the underlying MessageQ transport requires it) the SharedRegion modules.rjjajjjjj}r(j]j]j]j]j]ujKjhj]rjXAPI calls made to the Notify, ListMP, and Heap*MP modules in the previous scenarios are not needed. Instead, your application only needs to configure the MultiProc and (if the underlying MessageQ transport requires it) the SharedRegion modules.rr}r(jjjjubaubj)r}r(jXSome MessageQ transports do not use SharedRegion, but instead copy the message payloads. This may be done because of hardware limitations (e.g. no shared memory is available) or software design (e.g. transports built on Linux kernel-friendly rpmsg drivers).jjajjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXSome MessageQ transports do not use SharedRegion, but instead copy the message payloads. This may be done because of hardware limitations (e.g. no shared memory is available) or software design (e.g. transports built on Linux kernel-friendly rpmsg drivers).rjjjjjjj}r(j]j]j]j]j]ujKj]rjXSome MessageQ transports do not use SharedRegion, but instead copy the message payloads. This may be done because of hardware limitations (e.g. no shared memory is available) or software design (e.g. transports built on Linux kernel-friendly rpmsg drivers).rr}r(jjjjubaubaubj)r}r(jXThe ``Ipc_start()`` API call configures all the necessary underlying modules (e.g. Notify, HeapMemMP, ListMP, TransportShm, NameServer, and GateMP). The actual details of what modules ``Ipc_start()`` initializes varies from environment to environment.jjajjjjj}r(j]j]j]j]j]ujKjhj]r(jXThe rr}r(jXThe jjubcdocutils.nodes literal r)r}r(jX``Ipc_start()``j}r(j]j]j]j]j]ujjj]rjX Ipc_start()rr}r(jUjjubajUliteralrubjX API call configures all the necessary underlying modules (e.g. Notify, HeapMemMP, ListMP, TransportShm, NameServer, and GateMP). The actual details of what modules rr}r(jX API call configures all the necessary underlying modules (e.g. Notify, HeapMemMP, ListMP, TransportShm, NameServer, and GateMP). The actual details of what modules jjubj)r}r(jX``Ipc_start()``j}r(j]j]j]j]j]ujjj]rjX Ipc_start()rr}r(jUjjubajjubjX4 initializes varies from environment to environment.rr}r(jX4 initializes varies from environment to environment.jjubeubj)r}r(jXIt is possible to use MessageQ in a single-processor SYS/BIOS application. In such a case, only API calls to MessageQ and configuration of any xdc.runtime.IHeap implementation are needed.rjjajjjjj}r(j]j]j]j]j]ujKjhj]rjXIt is possible to use MessageQ in a single-processor SYS/BIOS application. In such a case, only API calls to MessageQ and configuration of any xdc.runtime.IHeap implementation are needed.rr}r(jjjjubaubeubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rU ipc-examplesraj]rjaujK%jhj]r(j)r}r(jX IPC Examplesrjjjjjjj}r(j]j]j]j]j]ujK%jhj]rjX IPC Examplesrr}r(jjjjubaubj7)r}r(jX@http://processors.wiki.ti.com/index.php/IPC_Users_Guide/Examplesjjjj:X:source/rtos/PDK_Platform_Software/IPC/IPC_examples.rst.incrr}rbjj>j}r(j@jAj]j]j]j]j]ujKjhj]rjX@http://processors.wiki.ti.com/index.php/IPC_Users_Guide/Examplesrr}r(jUjjubaubj)r}r(jUjjjjjjj}r(j]j]j]j]rUbuilding-ipc-examplesraj]rj4aujKjhj]r(j)r}r(jXBuilding IPC Examplesrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXBuilding IPC Examplesrr}r(jjjjubaubj)r}r(jXThe IPC BIOS examples are located in the Processor SDK RTOS IPC directory within the examples folder. Please refer to the readme of each example for details on each example.rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXThe IPC BIOS examples are located in the Processor SDK RTOS IPC directory within the examples folder. Please refer to the readme of each example for details on each example.rr}r(jjjjubaubj)r}r(jXThe examples are makefile based and can be built using the top-level makefile provided in the Processor SDK RTOS folder. The following commands will build all of the IPC examples.rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXThe examples are makefile based and can be built using the top-level makefile provided in the Processor SDK RTOS folder. The following commands will build all of the IPC examples.rr}r(jjjjubaubj)r}r(jX**Windows** ::jjjjjjj}r(j]j]j]j]j]ujK jhj]rj)r}r(jX **Windows**j}r(j]j]j]j]j]ujjj]rjXWindowsrr}r(jUjjubajjubaubcdocutils.nodes literal_block r)r}r(jX>cd (Processor SDK RTOS folder) setupenv.bat gmake ipc_examplesjjjjjU literal_blockrj}r(j@jAj]j]j]j]j]ujM5jhj]rjX>cd (Processor SDK RTOS folder) setupenv.bat gmake ipc_examplesrr}r (jUjjubaubj)r }r (jX **Linux** ::jjjjjjj}r (j]j]j]j]j]ujKjhj]r j)r}r(jX **Linux**j}r(j]j]j]j]j]ujj j]rjXLinuxrr}r(jUjjubajjubaubj)r}r(jXEcd (Processor SDK RTOS folder) source ./setupenv.sh make ipc_examplesjjjjjjj}r(j@jAj]j]j]j]j]ujM<jhj]rjXEcd (Processor SDK RTOS folder) source ./setupenv.sh make ipc_examplesrr}r(jUjjubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rUipc-examples-detailsr aj]r!jaujKjhj]r"(j)r#}r$(jXIPC Examples: Detailsr%jjjjjjj}r&(j]j]j]j]j]ujKjhj]r'jXIPC Examples: Detailsr(r)}r*(jj%jj#ubaubj)r+}r,(jXThis section explains some of the common details about IPC examples. The sub-directories under the examples are organised into the code for each of the cores in the SOC. For exampler-jjjjjjj}r.(j]j]j]j]j]ujKjhj]r/jXThis section explains some of the common details about IPC examples. The sub-directories under the examples are organised into the code for each of the cores in the SOC. For exampler0r1}r2(jj-jj+ubaubcdocutils.nodes block_quote r3)r4}r5(jUjjjNjU block_quoter6j}r7(j]j]j]j]j]ujNjhj]r8jt)r9}r:(jUj}r;(jyX-j]j]j]j]j]ujj4j]r<(j{)r=}r>(jXHostr?j}r@(j]j]j]j]j]ujj9j]rAj)rB}rC(jj?jj=jjjjj}rD(j]j]j]j]j]ujKj]rEjXHostrFrG}rH(jj?jjBubaubajjubj{)rI}rJ(jXDSP1rKj}rL(j]j]j]j]j]ujj9j]rMj)rN}rO(jjKjjIjjjjj}rP(j]j]j]j]j]ujK j]rQjXDSP1rRrS}rT(jjKjjNubaubajjubj{)rU}rV(jXDSP2rWj}rX(j]j]j]j]j]ujj9j]rYj)rZ}r[(jjWjjUjjjjj}r\(j]j]j]j]j]ujK!j]r]jXDSP2r^r_}r`(jjWjjZubaubajjubj{)ra}rb(jXIPU1rcj}rd(j]j]j]j]j]ujj9j]rej)rf}rg(jjcjjajjjjj}rh(j]j]j]j]j]ujK"j]rijXIPU1rjrk}rl(jjcjjfubaubajjubj{)rm}rn(jXIPU2 j}ro(j]j]j]j]j]ujj9j]rpj)rq}rr(jXIPU2rsjjmjjjjj}rt(j]j]j]j]j]ujK#j]rujXIPU2rvrw}rx(jjsjjqubaubajjubejjwubaubj)ry}rz(jXTypically we have a host core which is the main core in the SOC and other slave cores. The directory name of the slave cores have a base name (like DSP, IPU etc) which indicates the type of core and a core number. Depending on the example, the Host can run TI BIOS or Linux or QNX and the slave cores in general run TI BIOS only. So the specific build related files need to be interpreted accordingly.r{jjjjjjj}r|(j]j]j]j]j]ujK%jhj]r}jXTypically we have a host core which is the main core in the SOC and other slave cores. The directory name of the slave cores have a base name (like DSP, IPU etc) which indicates the type of core and a core number. Depending on the example, the Host can run TI BIOS or Linux or QNX and the slave cores in general run TI BIOS only. So the specific build related files need to be interpreted accordingly.r~r}r(jj{jjyubaubj)r}r(jUjjjjjjj}r(j]j]j]j]rU$bios-application-configuration-filesraj]rjcaujK+jhj]r(j)r}r(jX$BIOS Application Configuration Filesrjjjjjjj}r(j]j]j]j]j]ujK+jhj]rjX$BIOS Application Configuration Filesrr}r(jjjjubaubj)r}r(jXpThe cores running BIOS in general has a config file which brings in all the modules needed to complete the application running on the specific core. This section explains the details of the entries in the config file. Note: The details here are just representative of a typical configuration. In general the configuration is customized based on the particular example.rjjjjjjj}r(j]j]j]j]j]ujK,jhj]rjXpThe cores running BIOS in general has a config file which brings in all the modules needed to complete the application running on the specific core. This section explains the details of the entries in the config file. Note: The details here are just representative of a typical configuration. In general the configuration is customized based on the particular example.rr}r(jjjjubaubj)r}r(jUjjjjjjj}r(j]j]j]j]rUbios-configurationraj]rj^aujK1jhj]r(j)r}r(jXBIOS Configurationrjjjjjjj}r(j]j]j]j]j]ujK1jhj]rjXBIOS Configurationrr}r(jjjjubaubj)r}r(jX>The following configuration are related to configuring BIOS ::jjjjjjj}r(j]j]j]j]j]ujK2jhj]rjX;The following configuration are related to configuring BIOSrr}r(jX;The following configuration are related to configuring BIOSjjubaubj)r}r(jXvar BIOS = xdc.useModule('ti.sysbios.BIOS'); /* This adds ipc Startup to be done part of BIOS startup before main*/ BIOS.addUserStartupFunction('&IpcMgr_ipcStartup'); /* The following configures Debug libtype with Debug build */ if (Program.build.profile == "debug") { BIOS.libType = BIOS.LibType_Debug; } else { BIOS.libType = BIOS.LibType_Custom; } var Sem = xdc.useModule('ti.sysbios.knl.Semaphore'); var instSem0_Params = new Sem.Params(); instSem0_Params.mode = Sem.Mode_BINARY; Program.global.runOmpSem = Sem.create(0, instSem0_Params); Program.global.runOmpSem_complete = Sem.create(0, instSem0_Params); var Task = xdc.useModule('ti.sysbios.knl.Task'); Task.common$.namedInstance = true; /* default memory heap */ var Memory = xdc.useModule('xdc.runtime.Memory'); var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem'); var heapMemParams = new HeapMem.Params(); heapMemParams.size = 0x8000; Memory.defaultHeapInstance = HeapMem.create(heapMemParams); /* create a heap for MessageQ messages */ var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf'); var params = new HeapBuf.Params; params.align = 8; params.blockSize = 512; params.numBlocks = 20;jjjjjjj}r(j@jAj]j]j]j]j]ujM^jhj]rjXvar BIOS = xdc.useModule('ti.sysbios.BIOS'); /* This adds ipc Startup to be done part of BIOS startup before main*/ BIOS.addUserStartupFunction('&IpcMgr_ipcStartup'); /* The following configures Debug libtype with Debug build */ if (Program.build.profile == "debug") { BIOS.libType = BIOS.LibType_Debug; } else { BIOS.libType = BIOS.LibType_Custom; } var Sem = xdc.useModule('ti.sysbios.knl.Semaphore'); var instSem0_Params = new Sem.Params(); instSem0_Params.mode = Sem.Mode_BINARY; Program.global.runOmpSem = Sem.create(0, instSem0_Params); Program.global.runOmpSem_complete = Sem.create(0, instSem0_Params); var Task = xdc.useModule('ti.sysbios.knl.Task'); Task.common$.namedInstance = true; /* default memory heap */ var Memory = xdc.useModule('xdc.runtime.Memory'); var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem'); var heapMemParams = new HeapMem.Params(); heapMemParams.size = 0x8000; Memory.defaultHeapInstance = HeapMem.create(heapMemParams); /* create a heap for MessageQ messages */ var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf'); var params = new HeapBuf.Params; params.align = 8; params.blockSize = 512; params.numBlocks = 20;rr}r(jUjjubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rU xdc-runtimeraj]rhqaujKXjhj]r(j)r}r(jX XDC Runtimerjjjjjjj}r(j]j]j]j]j]ujKXjhj]rjX XDC Runtimerr}r(jjjjubaubj)r}r(jXPThe following configuration are in general used by an IPC application in BIOS ::jjjjjjj}r(j]j]j]j]j]ujKYjhj]rjXMThe following configuration are in general used by an IPC application in BIOSrr}r(jXMThe following configuration are in general used by an IPC application in BIOSjjubaubj)r}r(jXA/* application uses the following modules and packages */ xdc.useModule('xdc.runtime.Assert'); xdc.useModule('xdc.runtime.Diags'); xdc.useModule('xdc.runtime.Error'); xdc.useModule('xdc.runtime.Log'); xdc.useModule('xdc.runtime.Registry'); xdc.useModule('ti.sysbios.knl.Semaphore'); xdc.useModule('ti.sysbios.knl.Task');jjjjjjj}r(j@jAj]j]j]j]j]ujMjhj]rjXA/* application uses the following modules and packages */ xdc.useModule('xdc.runtime.Assert'); xdc.useModule('xdc.runtime.Diags'); xdc.useModule('xdc.runtime.Error'); xdc.useModule('xdc.runtime.Log'); xdc.useModule('xdc.runtime.Registry'); xdc.useModule('ti.sysbios.knl.Semaphore'); xdc.useModule('ti.sysbios.knl.Task');rr}r(jUjjubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rUipc-configurationraj]rhVaujKgjhj]r(j)r}r(jXIPC Configurationrjjjjjjj}r(j]j]j]j]j]ujKgjhj]rjXIPC Configurationrr}r(jjjjubaubj)r}r(jXCThe following IPC modules are used in a typical IPC application. ::jjjjjjj}r(j]j]j]j]j]ujKhjhj]rjX@The following IPC modules are used in a typical IPC application.rr}r(jX@The following IPC modules are used in a typical IPC application.jjubaubj)r}r(jXxdc.useModule('ti.sdo.ipc.Ipc'); xdc.useModule('ti.ipc.ipcmgr.IpcMgr'); var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc'); /* The following configures the PROC List */ MultiProc.setConfig("CORE0", ["HOST", "CORE0"]); var msgHeap = HeapBuf.create(params); var MessageQ = xdc.useModule('ti.sdo.ipc.MessageQ'); /* Register msgHeap with messageQ */ MessageQ.registerHeapMeta(msgHeap, 0);jjjjjjj}r(j@jAj]j]j]j]j]ujMjhj]rjXxdc.useModule('ti.sdo.ipc.Ipc'); xdc.useModule('ti.ipc.ipcmgr.IpcMgr'); var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc'); /* The following configures the PROC List */ MultiProc.setConfig("CORE0", ["HOST", "CORE0"]); var msgHeap = HeapBuf.create(params); var MessageQ = xdc.useModule('ti.sdo.ipc.MessageQ'); /* Register msgHeap with messageQ */ MessageQ.registerHeapMeta(msgHeap, 0);rr}r(jUjjubaubj)r}r(jXThe following lines configure placement of Resource table in memory. Note that some platforms or applications the placement of memory can be in a different section in the memory map. ::jjjjjjj}r(j]j]j]j]j]ujKwjhj]rjXThe following lines configure placement of Resource table in memory. Note that some platforms or applications the placement of memory can be in a different section in the memory map.rr}r(jXThe following lines configure placement of Resource table in memory. Note that some platforms or applications the placement of memory can be in a different section in the memory map.jjubaubj)r}r(jX/* Enable Memory Translation module that operates on the Resource Table */ var Resource = xdc.useModule('ti.ipc.remoteproc.Resource'); Resource.loadSegment = Program.platform.dataMemory;jjjjjjj}r(j@jAj]j]j]j]j]ujMjhj]rjX/* Enable Memory Translation module that operates on the Resource Table */ var Resource = xdc.useModule('ti.ipc.remoteproc.Resource'); Resource.loadSegment = Program.platform.dataMemory;rr}r(jUjjubaubeubj)r}r(jUjKjjjjjjj}r(j]rXtransport configurationraj]j]j]rUtransport-configurationraj]ujKjhj]r(j)r}r(jXTransport Configurationrjjjjjjj}r(j]j]j]j]j]ujKjhj]r jXTransport Configurationr r }r (jjjjubaubj)r }r(jXwTypically the transport to be used by IPC is specified here. The following snippet configures RPMsg based transport. ::jjjjjjj}r(j]j]j]j]j]ujKjhj]rjXtTypically the transport to be used by IPC is specified here. The following snippet configures RPMsg based transport.rr}r(jXtTypically the transport to be used by IPC is specified here. The following snippet configures RPMsg based transport.jj ubaubj)r}r(jX/* Setup MessageQ transport */ var VirtioSetup = xdc.useModule('ti.ipc.transports.TransportRpmsgSetup'); MessageQ.SetupTransportProxy = VirtioSetup;jjjjjjj}r(j@jAj]j]j]j]j]ujMjhj]rjX/* Setup MessageQ transport */ var VirtioSetup = xdc.useModule('ti.ipc.transports.TransportRpmsgSetup'); MessageQ.SetupTransportProxy = VirtioSetup;rr}r(jUjjubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rUnameserver-configurationraj]r haujKjhj]r!(j)r"}r#(jXNameServer Configurationr$jjjjjjj}r%(j]j]j]j]j]ujKjhj]r&jXNameServer Configurationr'r(}r)(jj$jj"ubaubj)r*}r+(jX0The Name server to be used is specified here. ::jjjjjjj}r,(j]j]j]j]j]ujKjhj]r-jX-The Name server to be used is specified here.r.r/}r0(jX-The Name server to be used is specified here.jj*ubaubj)r1}r2(jX/* Setup NameServer remote proxy */ var NameServer = xdc.useModule("ti.sdo.utils.NameServer"); var NsRemote = xdc.useModule("ti.ipc.namesrv.NameServerRemoteRpmsg"); NameServer.SetupProxy = NsRemote;jjjjjjj}r3(j@jAj]j]j]j]j]ujMjhj]r4jX/* Setup NameServer remote proxy */ var NameServer = xdc.useModule("ti.sdo.utils.NameServer"); var NsRemote = xdc.useModule("ti.ipc.namesrv.NameServerRemoteRpmsg"); NameServer.SetupProxy = NsRemote;r5r6}r7(jUjj1ubaubeubj)r8}r9(jUjjjjjjj}r:(j]j]j]j]r;Uinstrumentation-configurationr<aj]r=j&aujKjhj]r>(j)r?}r@(jXInstrumentation ConfigurationrAjj8jjjjj}rB(j]j]j]j]j]ujKjhj]rCjXInstrumentation ConfigurationrDrE}rF(jjAjj?ubaubj)rG}rH(jXOThe following configuration are required for system logging and diagnostics. ::jj8jjjjj}rI(j]j]j]j]j]ujKjhj]rJjXLThe following configuration are required for system logging and diagnostics.rKrL}rM(jXLThe following configuration are required for system logging and diagnostics.jjGubaubj)rN}rO(jX& /* system logger */ var LoggerSys = xdc.useModule('xdc.runtime.LoggerSys'); var LoggerSysParams = new LoggerSys.Params(); var Defaults = xdc.useModule('xdc.runtime.Defaults'); Defaults.common$.logger = LoggerSys.create(LoggerSysParams); /* enable runtime Diags_setMask() for non-XDC spec'd modules */ var Diags = xdc.useModule('xdc.runtime.Diags'); Diags.setMaskEnabled = true; /* override diags mask for selected modules */ xdc.useModule('xdc.runtime.Main'); Diags.setMaskMeta("xdc.runtime.Main", Diags.ENTRY | Diags.EXIT | Diags.INFO, Diags.RUNTIME_ON); var Registry = xdc.useModule('xdc.runtime.Registry'); Registry.common$.diags_ENTRY = Diags.RUNTIME_OFF; Registry.common$.diags_EXIT = Diags.RUNTIME_OFF; Registry.common$.diags_INFO = Diags.RUNTIME_OFF; Registry.common$.diags_USER1 = Diags.RUNTIME_OFF; Registry.common$.diags_LIFECYCLE = Diags.RUNTIME_OFF; Registry.common$.diags_STATUS = Diags.RUNTIME_OFF; var Main = xdc.useModule('xdc.runtime.Main'); Main.common$.diags_ASSERT = Diags.ALWAYS_ON; Main.common$.diags_INTERNAL = Diags.ALWAYS_ON;jj8jjjjj}rP(j@jAj]j]j]j]j]ujMjhj]rQjX& /* system logger */ var LoggerSys = xdc.useModule('xdc.runtime.LoggerSys'); var LoggerSysParams = new LoggerSys.Params(); var Defaults = xdc.useModule('xdc.runtime.Defaults'); Defaults.common$.logger = LoggerSys.create(LoggerSysParams); /* enable runtime Diags_setMask() for non-XDC spec'd modules */ var Diags = xdc.useModule('xdc.runtime.Diags'); Diags.setMaskEnabled = true; /* override diags mask for selected modules */ xdc.useModule('xdc.runtime.Main'); Diags.setMaskMeta("xdc.runtime.Main", Diags.ENTRY | Diags.EXIT | Diags.INFO, Diags.RUNTIME_ON); var Registry = xdc.useModule('xdc.runtime.Registry'); Registry.common$.diags_ENTRY = Diags.RUNTIME_OFF; Registry.common$.diags_EXIT = Diags.RUNTIME_OFF; Registry.common$.diags_INFO = Diags.RUNTIME_OFF; Registry.common$.diags_USER1 = Diags.RUNTIME_OFF; Registry.common$.diags_LIFECYCLE = Diags.RUNTIME_OFF; Registry.common$.diags_STATUS = Diags.RUNTIME_OFF; var Main = xdc.useModule('xdc.runtime.Main'); Main.common$.diags_ASSERT = Diags.ALWAYS_ON; Main.common$.diags_INTERNAL = Diags.ALWAYS_ON;rRrS}rT(jUjjNubaubeubj)rU}rV(jUjjjjjjj}rW(j]j]j]j]rXUother-optional-configurationsrYaj]rZj*aujKjhj]r[(j)r\}r](jXOther Optional Configurationsr^jjUjjjjj}r_(j]j]j]j]j]ujKjhj]r`jXOther Optional Configurationsrarb}rc(jj^jj\ubaubj)rd}re(jXIn addition to the above configurations there are other platform specific configurations may be used to enable certain features.rfjjUjjjjj}rg(j]j]j]j]j]ujKjhj]rhjXIn addition to the above configurations there are other platform specific configurations may be used to enable certain features.rirj}rk(jjfjjdubaubj)rl}rm(jXFor example the following sections shows the sections used to enable device exception handler. ( But the deh module may not be available on all devices) ::jjUjjjjj}rn(j]j]j]j]j]ujKjhj]rojXFor example the following sections shows the sections used to enable device exception handler. ( But the deh module may not be available on all devices)rprq}rr(jXFor example the following sections shows the sections used to enable device exception handler. ( But the deh module may not be available on all devices)jjlubaubj)rs}rt(jXvar Idle = xdc.useModule('ti.sysbios.knl.Idle'); var Deh = xdc.useModule('ti.deh.Deh'); /* Must be placed before pwr mgmt */ Idle.addFunc('&ti_deh_Deh_idleBegin');jjUjjjjj}ru(j@jAj]j]j]j]j]ujMjhj]rvjXvar Idle = xdc.useModule('ti.sysbios.knl.Idle'); var Deh = xdc.useModule('ti.deh.Deh'); /* Must be placed before pwr mgmt */ Idle.addFunc('&ti_deh_Deh_idleBegin');rwrx}ry(jUjjsubaubeubeubeubj)rz}r{(jUjjjjjjj}r|(j]j]j]j]r}U(building-ipc-examples-using-products-makr~aj]rjaujKjhj]r(j)r}r(jX(Building IPC examples using products.makrjjzjjjjj}r(j]j]j]j]j]ujKjhj]rjX(Building IPC examples using products.makrr}r(jjjjubaubj)r}r(jXlThe following sections discuss how to individually build the IPC examples by modifying the product.mak file.rjjzjjjjj}r(j]j]j]j]j]ujKjhj]rjXlThe following sections discuss how to individually build the IPC examples by modifying the product.mak file.rr}r(jjjjubaubj)r}r(jX!The IPC product contains an examples/archive directory with device-specific examples. Once identifying your device, the examples can be unzipped anywhere on your build host. Typically once unzipped, the user edits the example's individual **products.mak** file and simply invokes **make**.jjzjjjjj}r(j]j]j]j]j]ujKjhj]r(jXThe IPC product contains an examples/archive directory with device-specific examples. Once identifying your device, the examples can be unzipped anywhere on your build host. Typically once unzipped, the user edits the example's individual rr}r(jXThe IPC product contains an examples/archive directory with device-specific examples. Once identifying your device, the examples can be unzipped anywhere on your build host. Typically once unzipped, the user edits the example's individual jjubj)r}r(jX**products.mak**j}r(j]j]j]j]j]ujjj]rjX products.makrr}r(jUjjubajjubjX file and simply invokes rr}r(jX file and simply invokes jjubj)r}r(jX**make**j}r(j]j]j]j]j]ujjj]rjXmakerr}r(jUjjubajjubjX.r}r(jX.jjubeubj)r}r(jXA common place to unzip the examples is into the **IPC_INSTALL_DIR/examples/** directory. Each example's **products.mak** file is smart enough to look up two directories (in this case, into **IPC_INSTALL_DIR**) for a master **products.mak** file, and if found it uses those variables. This technique enables users to set the dependency variables in one place, namely **IPC_INSTALL_DIR/products.mak**.jjzjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXA common place to unzip the examples is into the **IPC_INSTALL_DIR/examples/** directory. Each example's **products.mak** file is smart enough to look up two directories (in this case, into **IPC_INSTALL_DIR**) for a master **products.mak** file, and if found it uses those variables. This technique enables users to set the dependency variables in one place, namely **IPC_INSTALL_DIR/products.mak**.jjjjjjj}r(j]j]j]j]j]ujKj]r(jX1A common place to unzip the examples is into the rr}r(jX1A common place to unzip the examples is into the jjubj)r}r(jX**IPC_INSTALL_DIR/examples/**j}r(j]j]j]j]j]ujjj]rjXIPC_INSTALL_DIR/examples/rr}r(jUjjubajjubjX directory. Each example's rr}r(jX directory. Each example's jjubj)r}r(jX**products.mak**j}r(j]j]j]j]j]ujjj]rjX products.makrr}r(jUjjubajjubjXE file is smart enough to look up two directories (in this case, into rr}r(jXE file is smart enough to look up two directories (in this case, into jjubj)r}r(jX**IPC_INSTALL_DIR**j}r(j]j]j]j]j]ujjj]rjXIPC_INSTALL_DIRrr}r(jUjjubajjubjX) for a master rr}r(jX) for a master jjubj)r}r(jX**products.mak**j}r(j]j]j]j]j]ujjj]rjX products.makrr}r(jUjjubajjubjX file, and if found it uses those variables. This technique enables users to set the dependency variables in one place, namely rr}r(jX file, and if found it uses those variables. This technique enables users to set the dependency variables in one place, namely jjubj)r}r(jX **IPC_INSTALL_DIR/products.mak**j}r(j]j]j]j]j]ujjj]rjXIPC_INSTALL_DIR/products.makrr}r(jUjjubajjubjX.r}r(jX.jjubeubaubj)r}r(jXEEach example contains a **readme.txt** with example-specific details.rjjzjjjjj}r(j]j]j]j]j]ujKjhj]r(jXEach example contains a rr}r(jXEach example contains a jjubj)r}r(jX**readme.txt**j}r(j]j]j]j]j]ujjj]rjX readme.txtrr}r(jUjjubajjubjX with example-specific details.rr}r(jX with example-specific details.jjubeubj)r}r(jUjjzjjjjj}r(j]j]j]j]rUgenerating-examplesraj]rh aujKjhj]r(j)r }r (jXGenerating Examplesr jjjjjjj}r (j]j]j]j]j]ujKjhj]r jXGenerating Examplesr r }r (jj jj ubaubj)r }r (jXThe IPC product will come with the generated examples directory. The IPC product is what is typically delivered with SDKs such as Processor SDK. However, some SDKs point directly to the IPC git tree for the IPC source. In this case, the IPC Examples can be generated separately.r jjjjjjj}r (j]j]j]j]j]ujKjhj]r jXThe IPC product will come with the generated examples directory. The IPC product is what is typically delivered with SDKs such as Processor SDK. However, some SDKs point directly to the IPC git tree for the IPC source. In this case, the IPC Examples can be generated separately.r r }r (jj jj ubaubeubj)r }r (jUjKjjzjjjjj}r (j]r Xtoolsr aj]j]j]r Utoolsr aj]ujKjhj]r (j)r }r (jXToolsr jj jjjjj}r (j]j]j]j]j]ujKjhj]r jXToolsr r }r (jj jj ubaubcdocutils.nodes definition_list r )r! }r" (jUjj jNjUdefinition_listr# j}r$ (j]j]j]j]j]ujNjhj]r% cdocutils.nodes definition_list_item r& )r' }r( (jXThe following tools need to be installed: - `XDC tools `__ (check the IPC release notes for compatible version) jj! jjjUdefinition_list_itemr) j}r* (j]j]j]j]j]ujKj]r+ (cdocutils.nodes term r, )r- }r. (jX)The following tools need to be installed:r/ jj' jjjUtermr0 j}r1 (j]j]j]j]j]ujKj]r2 jX)The following tools need to be installed:r3 r4 }r5 (jj/ jj- ubaubcdocutils.nodes definition r6 )r7 }r8 (jUj}r9 (j]j]j]j]j]ujj' j]r: jt)r; }r< (jUj}r= (jyX-j]j]j]j]j]ujj7 j]r> j{)r? }r@ (jX`XDC tools `__ (check the IPC release notes for compatible version) j}rA (j]j]j]j]j]ujj; j]rB j)rC }rD (jX`XDC tools `__ (check the IPC release notes for compatible version)jj? jjjjj}rE (j]j]j]j]j]ujKj]rF (j)rG }rH (jXX`XDC tools `__j}rI (UnameX XDC toolsjXHhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/rtsc/j]j]j]j]j]ujjC j]rJ jX XDC toolsrK rL }rM (jUjjG ubajjubjX5 (check the IPC release notes for compatible version)rN rO }rP (jX5 (check the IPC release notes for compatible version)jjC ubeubajjubajjwubajU definitionrQ ubeubaubeubj)rR }rS (jUjjzjjjjj}rT (j]j]j]j]rU U source-coderV aj]rW j aujKjhj]rX (j)rY }rZ (jX Source Coder[ jjR jjjjj}r\ (j]j]j]j]j]ujKjhj]r] jX Source Coder^ r_ }r` (jj[ jjY ubaubj)ra }rb (jXpmkdir ipc cd ipc git clone git://git.ti.com/ipc/ipc-metadata.git git clone git://git.ti.com/ipc/ipc-examples.gitjjR jjjjj}rc (j@jAj]j]j]j]j]ujM jhj]rd jXpmkdir ipc cd ipc git clone git://git.ti.com/ipc/ipc-metadata.git git clone git://git.ti.com/ipc/ipc-examples.gitre rf }rg (jUjja ubaubj)rh }ri (jXzThen checkout the IPC release tag that is associated with the IPC version being used. Do this for both repos. For example:rj jjR jjjjj}rk (j]j]j]j]j]ujKjhj]rl jXzThen checkout the IPC release tag that is associated with the IPC version being used. Do this for both repos. For example:rm rn }ro (jjj jjh ubaubj)rp }rq (jXgit checkout 3.42.01.03jjR jjjjj}rr (j@jAj]j]j]j]j]ujMjhj]rs jXgit checkout 3.42.01.03rt ru }rv (jUjjp ubaubeubj)rw }rx (jUjKjjzjjjjj}ry (j]rz Xbuildr{ aj]j]j]r| Ubuildr} aj]ujKjhj]r~ (j)r }r (jXBuildr jjw jjjjj}r (j]j]j]j]j]ujKjhj]r jXBuildr r }r (jj jj ubaubj)r }r (jXncd ipc-examples/src make .examples XDC_INSTALL_DIR= IPCTOOLS=/src/etcjjw jjjjj}r (j@jAj]j]j]j]j]ujMjhj]r jXncd ipc-examples/src make .examples XDC_INSTALL_DIR= IPCTOOLS=/src/etcr r }r (jUjj ubaubj)r }r (jXFor example: ::jjw jjjjj}r (j]j]j]j]j]ujKjhj]r jX For example:r r }r (jX For example:jj ubaubj)r }r (jXlmake .examples XDC_INSTALL_DIR=/opt/ti/xdctools_3_32_00_06_core IPCTOOLS=/home/user/ipc/ipc-metadata/src/etcjjw jjjjj}r (j@jAj]j]j]j]j]ujM"jhj]r jXlmake .examples XDC_INSTALL_DIR=/opt/ti/xdctools_3_32_00_06_core IPCTOOLS=/home/user/ipc/ipc-metadata/src/etcr r }r (jUjj ubaubj)r }r (jXMThe "examples" director will be generated in the path "ipc-examples/src/": ::jjw jjjjj}r (j]j]j]j]j]ujKjhj]r jXJThe "examples" director will be generated in the path "ipc-examples/src/":r r }r (jXJThe "examples" director will be generated in the path "ipc-examples/src/":jj ubaubj)r }r (jXipc-examples/src/examplesjjw jXQinternal padding after source/rtos/PDK_Platform_Software/IPC/IPC_examples.rst.incr jjj}r (j@jAj]j]j]j]j]ujM'jhj]r jXipc-examples/src/examplesr r }r (jUjj ubaubeubeubeubj)r }r (jUjjjjjjj}r (j]j]j]j]r U ipc-trainingr aj]r haujK*jhj]r (j)r }r (jX IPC Trainingr jj jjjjj}r (j]j]j]j]j]ujK*jhj]r jX IPC Trainingr r }r (jj jj ubaubj7)r }r (jX/http://processors.wiki.ti.com/index.php/IPC_3.xjj jj:X&source/common/IPC/IPC_Training.rst.incr r }r bjj>j}r (j@jAj]j]j]j]j]ujKjhj]r jX/http://processors.wiki.ti.com/index.php/IPC_3.xr r }r (jUjj ubaubj)r }r (jX `Introduction to Inter-Processor Communication (IPC) for KeyStone and Sitara™ Devices `__ - The IPC software package is designed to hide the lower-layer hardware complexity of multi-core devices and help users to quickly develop applications for data transfer between cores or devices. IPC also maximizes application software reuse by providing a common API interface across all supported platforms, including AM65x, AM57x, 66AK2Gx, 66AK2Ex, 66AK2Hx, TCI663x, TDA3XX, OMAP-L138, OMAP54XX, DRA7XX, and more. This training video introduces the IPC features and modules, shows how to build the IPC libraries for your platform, examines the RPMsg framework, and provides a look at the included examples and benchmarks.jj jj jjj}r (j]j]j]j]j]ujKjhj]r (j)r }r (jX`Introduction to Inter-Processor Communication (IPC) for KeyStone and Sitara™ Devices `__j}r (UnameXVIntroduction to Inter-Processor Communication (IPC) for KeyStone and Sitara™ DevicesjX<https://training.ti.com/intro-to-ipc-for-keystone-and-sitaraj]j]j]j]j]ujj j]r jXVIntroduction to Inter-Processor Communication (IPC) for KeyStone and Sitara™ Devicesr r }r (jUjj ubajjubjXq - The IPC software package is designed to hide the lower-layer hardware complexity of multi-core devices and help users to quickly develop applications for data transfer between cores or devices. IPC also maximizes application software reuse by providing a common API interface across all supported platforms, including AM65x, AM57x, 66AK2Gx, 66AK2Ex, 66AK2Hx, TCI663x, TDA3XX, OMAP-L138, OMAP54XX, DRA7XX, and more. This training video introduces the IPC features and modules, shows how to build the IPC libraries for your platform, examines the RPMsg framework, and provides a look at the included examples and benchmarks.r r }r (jXq - The IPC software package is designed to hide the lower-layer hardware complexity of multi-core devices and help users to quickly develop applications for data transfer between cores or devices. IPC also maximizes application software reuse by providing a common API interface across all supported platforms, including AM65x, AM57x, 66AK2Gx, 66AK2Ex, 66AK2Hx, TCI663x, TDA3XX, OMAP-L138, OMAP54XX, DRA7XX, and more. This training video introduces the IPC features and modules, shows how to build the IPC libraries for your platform, examines the RPMsg framework, and provides a look at the included examples and benchmarks.jj ubeubjc)r }r (jUjj jj jjfj}r (j]j]j]j]j]ujKjhj]r ji)r }r (jUjlKjj jj jjj}r (j]j]j]j]j]ujKjhj]ubaubj)r }r (jX>`Building and Running Inter-Processor Communication (IPC) Examples on the AM572x GP EVM `__ - For TI embedded processors with heterogeneous multi-core architectures – like the AM57x family of devices, which have integrated ARM, DSP, and M4 cores – the TI Processor Software Development Kit (SDK) provides a software component called Inter-processor Communication (IPC). This video demonstrates how to build and run IPC examples on the AM572x General Purpose Evaluation Module (GP EVM) using Processor SDK for Linux.jj jj jjj}r (j]j]j]j]j]ujK jhj]r (j)r }r (jX`Building and Running Inter-Processor Communication (IPC) Examples on the AM572x GP EVM `__j}r (UnameXVBuilding and Running Inter-Processor Communication (IPC) Examples on the AM572x GP EVMjX5https://training.ti.com/am572x-build-run-ipc-examplesj]j]j]j]j]ujj j]r jXVBuilding and Running Inter-Processor Communication (IPC) Examples on the AM572x GP EVMr r }r (jUjj ubajjubjX - For TI embedded processors with heterogeneous multi-core architectures – like the AM57x family of devices, which have integrated ARM, DSP, and M4 cores – the TI Processor Software Development Kit (SDK) provides a software component called Inter-processor Communication (IPC). This video demonstrates how to build and run IPC examples on the AM572x General Purpose Evaluation Module (GP EVM) using Processor SDK for Linux.r r }r (jX - For TI embedded processors with heterogeneous multi-core architectures – like the AM57x family of devices, which have integrated ARM, DSP, and M4 cores – the TI Processor Software Development Kit (SDK) provides a software component called Inter-processor Communication (IPC). This video demonstrates how to build and run IPC examples on the AM572x General Purpose Evaluation Module (GP EVM) using Processor SDK for Linux.jj ubeubjc)r }r (jUjj jj jjfj}r (j]j]j]j]j]ujK jhj]r ji)r }r (jUjlKjj jj jjj}r (j]j]j]j]j]ujKjhj]ubaubj)r }r (jXIPC Training v2.21 - IPC 3.x Full Training Material :download:`(PowerPoint) <../files/IPC_Training_2_21.pptx>` :download:`(PowerPointShow) <../files/IPC_Training_2_21.ppsx>` :download:`(PDF) <../files/IPC_Training_2_21.pdf>`r jj jj jjj}r (j]j]j]j]j]ujKjhj]r (jX4IPC Training v2.21 - IPC 3.x Full Training Material r r }r (jX4IPC Training v2.21 - IPC 3.x Full Training Material jj ubcsphinx.addnodes download_reference r )r }r (jX::download:`(PowerPoint) <../files/IPC_Training_2_21.pptx>`r jj jj jUdownload_referencer j}r (UreftypeXdownloadr Urefwarnr U reftargetr X../files/IPC_Training_2_21.pptxU refdomainUj]j]U refexplicitj]j]j]Urefdocr X"rtos/index_Foundational_Componentsr Ufilenamer XIPC_Training_2_21.pptxr ujKj]r j)r }r (jj j}r (j]j]r (Uxrefr j ej]j]j]ujj j]r jX (PowerPoint)r r }r (jUjj ubajjubaubjX r }r (jX jj ubj )r }r (jX>:download:`(PowerPointShow) <../files/IPC_Training_2_21.ppsx>`r jj jj jj j}r (UreftypeXdownloadr j j X../files/IPC_Training_2_21.ppsxU refdomainUj]j]U refexplicitj]j]j]j j j XIPC_Training_2_21.ppsxr ujKj]r j)r }r (jj j}r (j]j]r (j j ej]j]j]ujj j]r jX(PowerPointShow)r r }r (jUjj ubajjubaubjX r }r (jX jj ubj )r }r! (jX2:download:`(PDF) <../files/IPC_Training_2_21.pdf>`r" jj jj jj j}r# (UreftypeXdownloadr$ j j X../files/IPC_Training_2_21.pdfU refdomainUj]j]U refexplicitj]j]j]j j j XIPC_Training_2_21.pdfr% ujKj]r& j)r' }r( (jj" j}r) (j]j]r* (j j$ ej]j]j]ujj j]r+ jX(PDF)r, r- }r. (jUjj' ubajjubaubeubjc)r/ }r0 (jUjj jj jjfj}r1 (j]j]j]j]j]ujKjhj]r2 ji)r3 }r4 (jUjlKjj/ jj jjj}r5 (j]j]j]j]j]ujKjhj]ubaubj)r6 }r7 (jXIPC Lab 1 - Hello :download:`(PowerPoint) <../files/IPC_Lab_1_Hello.pptx>` :download:`(PowerPointShow) <../files/IPC_Lab_1_Hello.ppsx>` :download:`(PDF) <../files/IPC_Lab_1_Hello.pdf>`r8 jj jj jjj}r9 (j]j]j]j]j]ujKjhj]r: (jXIPC Lab 1 - Hello r; r< }r= (jXIPC Lab 1 - Hello jj6 ubj )r> }r? (jX8:download:`(PowerPoint) <../files/IPC_Lab_1_Hello.pptx>`r@ jj6 jj jj j}rA (UreftypeXdownloadrB j j X../files/IPC_Lab_1_Hello.pptxU refdomainUj]j]U refexplicitj]j]j]j j j XIPC_Lab_1_Hello.pptxrC ujKj]rD j)rE }rF (jj@ j}rG (j]j]rH (j jB ej]j]j]ujj> j]rI jX (PowerPoint)rJ rK }rL (jUjjE ubajjubaubjX rM }rN (jX jj6 ubj )rO }rP (jX<:download:`(PowerPointShow) <../files/IPC_Lab_1_Hello.ppsx>`rQ jj6 jj jj j}rR (UreftypeXdownloadrS j j X../files/IPC_Lab_1_Hello.ppsxU refdomainUj]j]U refexplicitj]j]j]j j j XIPC_Lab_1_Hello.ppsxrT ujKj]rU j)rV }rW (jjQ j}rX (j]j]rY (j jS ej]j]j]ujjO j]rZ jX(PowerPointShow)r[ r\ }r] (jUjjV ubajjubaubjX r^ }r_ (jX jj6 ubj )r` }ra (jX0:download:`(PDF) <../files/IPC_Lab_1_Hello.pdf>`rb jj6 jj jj j}rc (UreftypeXdownloadrd j j X../files/IPC_Lab_1_Hello.pdfU refdomainUj]j]U refexplicitj]j]j]j j j XIPC_Lab_1_Hello.pdfre ujKj]rf j)rg }rh (jjb j}ri (j]j]rj (j jd ej]j]j]ujj` j]rk jX(PDF)rl rm }rn (jUjjg ubajjubaubeubj)ro }rp (jXIPC Lab 2 - MessageQ :download:`(PowerPoint) <../files/IPC_Lab_2_MessageQ.pptx>` :download:`(PowerPointShow) <../files/IPC_Lab_2_MessageQ.ppsx>` :download:`(PDF) <../files/IPC_Lab_2_MessageQ.pdf>`rq jj jj jjj}rr (j]j]j]j]j]ujKjhj]rs (jXIPC Lab 2 - MessageQ rt ru }rv (jXIPC Lab 2 - MessageQ jjo ubj )rw }rx (jX;:download:`(PowerPoint) <../files/IPC_Lab_2_MessageQ.pptx>`ry jjo jj jj j}rz (UreftypeXdownloadr{ j j X ../files/IPC_Lab_2_MessageQ.pptxU refdomainUj]j]U refexplicitj]j]j]j j j XIPC_Lab_2_MessageQ.pptxr| ujKj]r} j)r~ }r (jjy j}r (j]j]r (j j{ ej]j]j]ujjw j]r jX (PowerPoint)r r }r (jUjj~ ubajjubaubjX r }r (jX jjo ubj )r }r (jX?:download:`(PowerPointShow) <../files/IPC_Lab_2_MessageQ.ppsx>`r jjo jj jj j}r (UreftypeXdownloadr j j X ../files/IPC_Lab_2_MessageQ.ppsxU refdomainUj]j]U refexplicitj]j]j]j j j XIPC_Lab_2_MessageQ.ppsxr ujKj]r j)r }r (jj j}r (j]j]r (j j ej]j]j]ujj j]r jX(PowerPointShow)r r }r (jUjj ubajjubaubjX r }r (jX jjo ubj )r }r (jX3:download:`(PDF) <../files/IPC_Lab_2_MessageQ.pdf>`r jjo jj jj j}r (UreftypeXdownloadr j j X../files/IPC_Lab_2_MessageQ.pdfU refdomainUj]j]U refexplicitj]j]j]j j j XIPC_Lab_2_MessageQ.pdfr ujKj]r j)r }r (jj j}r (j]j]r (j j ej]j]j]ujj j]r jX(PDF)r r }r (jUjj ubajjubaubeubj)r }r (jXIPC Lab 3 - Scalability :download:`(PowerPoint) <../files/IPC_Lab_3_Scalability.pptx>` :download:`(PowerPointShow) <../files/IPC_Lab_3_Scalability.ppsx>` :download:`(PDF) <../files/IPC_Lab_3_Scalability.pdf>`r jj jj jjj}r (j]j]j]j]j]ujKjhj]r (jXIPC Lab 3 - Scalability r r }r (jXIPC Lab 3 - Scalability jj ubj )r }r (jX>:download:`(PowerPoint) <../files/IPC_Lab_3_Scalability.pptx>`r jj jj jj j}r (UreftypeXdownloadr j j X#../files/IPC_Lab_3_Scalability.pptxU refdomainUj]j]U refexplicitj]j]j]j j j XIPC_Lab_3_Scalability.pptxr ujKj]r j)r }r (jj j}r (j]j]r (j j ej]j]j]ujj j]r jX (PowerPoint)r r }r (jUjj ubajjubaubjX r }r (jX jj ubj )r }r (jXB:download:`(PowerPointShow) <../files/IPC_Lab_3_Scalability.ppsx>`r jj jj jj j}r (UreftypeXdownloadr j j X#../files/IPC_Lab_3_Scalability.ppsxU refdomainUj]j]U refexplicitj]j]j]j j j XIPC_Lab_3_Scalability.ppsxr ujKj]r j)r }r (jj j}r (j]j]r (j j ej]j]j]ujj j]r jX(PowerPointShow)r r }r (jUjj ubajjubaubjX r }r (jX jj ubj )r }r (jX6:download:`(PDF) <../files/IPC_Lab_3_Scalability.pdf>`r jj jj jj j}r (UreftypeXdownloadr j j X"../files/IPC_Lab_3_Scalability.pdfU refdomainUj]j]U refexplicitj]j]j]j j j XIPC_Lab_3_Scalability.pdfr ujKj]r j)r }r (jj j}r (j]j]r (j j ej]j]j]ujj j]r jX(PDF)r r }r (jUjj ubajjubaubeubeubjj)r }r (jUjjjjjjj}r (j]j]j]j]r Uti-sdo-utils-packager aj]r huaujKUjhj]r (j)r }r (jXTI SDO Utils Packager jj jjjjj}r (j]j]j]j]j]ujKUjhj]r jXTI SDO Utils Packager r }r (jj jj ubaubj7)r }r (jXPhttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/The_ti.sdo.utils_Packagejj jj:XFsource/rtos/PDK_Platform_Software/IPC/The_ti.sdo.utils_Package.rst.incr r }r bjj>j}r (j@jAj]j]j]j]j]ujKjhj]r jXPhttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/The_ti.sdo.utils_Packager r }r (jUjj ubaubj)r }r (jX=This page introduces the modules in the ti.sdo.utils package.r jj jj jjj}r (j]j]j]j]j]ujKjhj]r jX=This page introduces the modules in the ti.sdo.utils package.r r }r (jj jj ubaubj)r }r (jXiThe ti.sdo.utils package contains modules that are used as utilities by other modules in the IPC product.r jj jj jjj}r (j]j]j]j]j]ujKjhj]r jXiThe ti.sdo.utils package contains modules that are used as utilities by other modules in the IPC product.r r }r (jj jj ubaubjt)r }r (jUjj jj jjwj}r (jyX-j]j]j]j]j]ujKjhj]r (j{)r }r (jXbList. This module provides a doubly-linked list manager for use by other modules. See List Module.r jj jj jjj}r (j]j]j]j]j]ujNjhj]r j)r }r (jj jj jj jjj}r (j]j]j]j]j]ujKj]r jXbList. This module provides a doubly-linked list manager for use by other modules. See List Module.r r }r (jj jj ubaubaubj{)r }r (jX}MultiProc. This module stores processor IDs in a centralized location for multi-processor applications. See MultiProc Module.r jj jj jjj}r (j]j]j]j]j]ujNjhj]r j)r }r (jj jj jj jjj}r! (j]j]j]j]j]ujKj]r" jX}MultiProc. This module stores processor IDs in a centralized location for multi-processor applications. See MultiProc Module.r# r$ }r% (jj jj ubaubaubj{)r& }r' (jXcNameServer. This module manages name/value pairs for use by other modules. See NameServer Module. jj jX]internal padding after source/rtos/PDK_Platform_Software/IPC/The_ti.sdo.utils_Package.rst.incr( jjj}r) (j]j]j]j]j]ujNjhj]r* j)r+ }r, (jXaNameServer. This module manages name/value pairs for use by other modules. See NameServer Module.r- jj& jj jjj}r. (j]j]j]j]j]ujK j]r/ jXaNameServer. This module manages name/value pairs for use by other modules. See NameServer Module.r0 r1 }r2 (jj- jj+ ubaubaubeubj)r3 }r4 (jUjj jjjjj}r5 (j]j]j]j]r6 U list-moduler7 aj]r8 hRaujKYjhj]r9 (j)r: }r; (jX List Moduler< jj3 jjjjj}r= (j]j]j]j]j]ujKYjhj]r> jX List Moduler? r@ }rA (jj< jj: ubaubj7)rB }rC (jXChttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/List_Modulejj3 jj:X9source/rtos/PDK_Platform_Software/IPC/List_Module.rst.incrD rE }rF bjj>j}rG (j@jAj]j]j]j]j]ujKjhj]rH jXChttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/List_ModulerI rJ }rK (jUjjB ubaubj)rL }rM (jX.. |lisCfg_Img1| Image:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.html jj3 jjE jjHj}rN (j]j]j]j]j]rO X lisCfg_Img1rP aujKjhj]rQ j)rR }rS (jjP j}rT (UrefuriXhhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlrU j]j]j]j]j]ujjL j]rV jR)rW }rX (jXImage:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlrY j}rZ (UuriXrtos/../images/Book_cfg.pngr[ j]j]j]j]jX}r\ U*j[ sj]UaltjP ujjR j]jjZubajjubaubj)r] }r^ (jX.. |lisRun_Img1| Image:: ../images/Book_run.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/syslink/latest/docs/html/_list_8h.html jj3 jjE jjHj}r_ (j]j]j]j]j]r` X lisRun_Img1ra aujKjhj]rb j)rc }rd (jja j}re (UrefuriXihttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/syslink/latest/docs/html/_list_8h.htmlrf j]j]j]j]j]ujj] j]rg jR)rh }ri (jXImage:: ../images/Book_run.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/syslink/latest/docs/html/_list_8h.htmlrj j}rk (UuriXrtos/../images/Book_run.pngrl j]j]j]j]jX}rm U*jl sj]Ualtja ujjc j]jjZubajjubaubjc)rn }ro (jUjj3 jjE jjfj}rp (j]j]j]j]j]ujK jhj]rq ji)rr }rs (jUjlKjjn jjE jjj}rt (j]j]j]j]j]ujKjhj]ubaubj3)ru }rv (jUjj3 jjE jj6j}rw (j]j]j]j]j]ujNjhj]rx cdocutils.nodes table ry )rz }r{ (jUj}r| (j]j]j]j]j]ujju j]r} cdocutils.nodes tgroup r~ )r }r (jUj}r (j]j]j]j]j]UcolsKujjz j]r (cdocutils.nodes colspec r )r }r (jUj}r (j]j]j]j]j]UcolwidthKujj j]jUcolspecr ubj )r }r (jUj}r (j]j]j]j]j]UcolwidthKujj j]jj ubcdocutils.nodes thead r )r }r (jUj}r (j]j]j]j]j]ujj j]r cdocutils.nodes row r )r }r (jUj}r (j]j]j]j]j]ujj j]r cdocutils.nodes entry r )r }r (jUj}r (j]UmorecolsKj]j]j]j]ujj j]r j)r }r (jXAPI Reference Linksr jj jjE jjj}r (j]j]j]j]j]ujK j]r jXAPI Reference Linksr r }r (jj jj ubaubajUentryr ubajUrowr ubajUtheadr ubcdocutils.nodes tbody r )r }r (jUj}r (j]j]j]j]j]ujj j]r j )r }r (jUj}r (j]j]j]j]j]ujj j]r (j )r }r (jUj}r (j]j]j]j]j]ujj j]r j)r }r (jX |lisCfg_Img1|r jj jjE jjj}r (j]j]j]j]j]ujKj]r j)r }r (jjP jj jNjjj}r (UrefurijU j]j]j]j]j]ujNj]r jR)r }r (jjY jj jNjjZj}r (UuriXrtos/../images/Book_cfg.pngr j]j]j]j]jX}r U*j sj]UaltjP ujNj]ubaubaubajj ubj )r }r (jUj}r (j]j]j]j]j]ujj j]r j)r }r (jX |lisRun_Img1|r jj jjE jjj}r (j]j]j]j]j]ujKj]r j)r }r (jja jj jNjjj}r (Urefurijf j]j]j]j]j]ujNj]r jR)r }r (jjj jj jNjjZj}r (UuriXrtos/../images/Book_run.pngr j]j]j]j]jX}r U*j sj]Ualtja ujNj]ubaubaubajj ubejj ubajUtbodyr ubejUtgroupr ubajUtabler ubaubj)r }r (jXThe ti.sdo.utils.List module provides support for creating lists of objects. A List is implemented as a doubly-linked list, so that elements can be inserted or removed from anywhere in the list. Lists do not have a maximum size.r jj3 jjE jjj}r (j]j]j]j]j]ujKjhj]r jXThe ti.sdo.utils.List module provides support for creating lists of objects. A List is implemented as a doubly-linked list, so that elements can be inserted or removed from anywhere in the list. Lists do not have a maximum size.r r }r (jj jj ubaubj)r }r (jUjj3 jjE jjj}r (j]j]j]j]r Ubasic-fifo-operation-of-a-listr aj]r j%aujKjhj]r (j)r }r (jXBasic FIFO Operation of a Listr jj jjE jjj}r (j]j]j]j]j]ujKjhj]r jXBasic FIFO Operation of a Listr r }r (jj jj ubaubj)r }r (jXpTo add a structure to a List, its first field needs to be of type List_Elem. The following example shows a structure that can be added to a List. A List has a "head", which is the front of the list. List_put() adds elements to the back of the list, and List_get() removes and returns the element at the head of the list. Together, these functions support a FIFO queue.r jj jjE jjj}r (j]j]j]j]j]ujKjhj]r jXpTo add a structure to a List, its first field needs to be of type List_Elem. The following example shows a structure that can be added to a List. A List has a "head", which is the front of the list. List_put() adds elements to the back of the list, and List_get() removes and returns the element at the head of the list. Together, these functions support a FIFO queue.r r }r (jj jj ubaubj)r }r (jXn**Run-time example:** The following example demonstrates the basic List operations--List_put() and List_get().r jj jjE jjj}r (j]j]j]j]j]ujKjhj]r (j)r }r (jX**Run-time example:**j}r (j]j]j]j]j]ujj j]r jXRun-time example:r r }r (jUjj ubajjubjXY The following example demonstrates the basic List operations--List_put() and List_get().r r }r (jXY The following example demonstrates the basic List operations--List_put() and List_get().jj ubeubj)r }r (jXP/* This structure can be added to a List because the first * field is a List_Elem. Declared globally. */ typedef struct Rec { List_Elem elem; Int data; } Rec; ... List_Handle myList; /* in main() */ Rec r1, r2; Rec* rp; r1.data = 100; r2.data = 200; /* No parameters are needed to create a List. */ myList = List_create(NULL, NULL); /* Add r1 and r2 to the back of myList. */ List_put(myList, &(r1.elem)); List_put(myList, &(r2.elem)); /* get the records and print their data */ while ((rp = List_get(myList)) != NULL) { System_printf("rec: %d\n", rp->data); }jj jjE jjj}r (j@jAj]j]j]j]j]ujM jhj]r jXP/* This structure can be added to a List because the first * field is a List_Elem. Declared globally. */ typedef struct Rec { List_Elem elem; Int data; } Rec; ... List_Handle myList; /* in main() */ Rec r1, r2; Rec* rp; r1.data = 100; r2.data = 200; /* No parameters are needed to create a List. */ myList = List_create(NULL, NULL); /* Add r1 and r2 to the back of myList. */ List_put(myList, &(r1.elem)); List_put(myList, &(r2.elem)); /* get the records and print their data */ while ((rp = List_get(myList)) != NULL) { System_printf("rec: %d\n", rp->data); }r r }r (jUjj ubaubj)r }r (jX!The example prints the following:r jj jjE jjj}r (j]j]j]j]j]ujK>jhj]r jX!The example prints the following:r r }r (jj jj ubaubj)r }r (jXrec: 100 rec: 200jj jjE jjj}r (j@jAj]j]j]j]j]ujM jhj]r jXrec: 100 rec: 200r r }r (jUjj ubaubjc)r }r (jUjj jjE jjfj}r (j]j]j]j]j]ujKEjhj]r ji)r }r (jUjlKjj jjE jjj}r (j]j]j]j]j]ujKjhj]ubaubeubj)r }r! (jUjj3 jjE jjj}r" (j]j]j]j]r# Uiterating-over-a-listr$ aj]r% jaujKHjhj]r& (j)r' }r( (jXIterating Over a Listr) jj jjE jjj}r* (j]j]j]j]j]ujKHjhj]r+ jXIterating Over a Listr, r- }r. (jj) jj' ubaubj)r/ }r0 (jXCThe List module also provides several APIs for looping over a List.r1 jj jjE jjj}r2 (j]j]j]j]j]ujKIjhj]r3 jXCThe List module also provides several APIs for looping over a List.r4 r5 }r6 (jj1 jj/ ubaubj)r7 }r8 (jXList_next() with NULL returns the element at the front of the List (without removing it). List_next() with an elem returns the next elem. NULL is returned when the end of the List is reached.r9 jj jjE jjj}r: (j]j]j]j]j]ujKKjhj]r; jXList_next() with NULL returns the element at the front of the List (without removing it). List_next() with an elem returns the next elem. NULL is returned when the end of the List is reached.r< r= }r> (jj9 jj7 ubaubj)r? }r@ (jXSimilarly, List_prev() with NULL returns the tail. List_prev() with an elem returns the previous elem. NULL is returned when the beginning of the List is reached.rA jj jjE jjj}rB (j]j]j]j]j]ujKNjhj]rC jXSimilarly, List_prev() with NULL returns the tail. List_prev() with an elem returns the previous elem. NULL is returned when the beginning of the List is reached.rD rE }rF (jjA jj? ubaubj)rG }rH (jX**Run-time example:** The following example demonstrates one way to iterate over a List once from beginning to end. In this example, "myList" is a List_Handle.jj jjE jjj}rI (j]j]j]j]j]ujKQjhj]rJ (j)rK }rL (jX**Run-time example:**j}rM (j]j]j]j]j]ujjG j]rN jXRun-time example:rO rP }rQ (jUjjK ubajjubjX The following example demonstrates one way to iterate over a List once from beginning to end. In this example, "myList" is a List_Handle.rR rS }rT (jX The following example demonstrates one way to iterate over a List once from beginning to end. In this example, "myList" is a List_Handle.jjG ubeubj)rU }rV (jXkList_Elem *elem = NULL; Rec* rp; ... /* To start the search at the beginning of the List */ rp = NULL; /* Begin protection against modification of the List */ key = Gate_enterSystem(); while ((elem = List_next(myList, elem)) != NULL) { System_printf("rec: %d\n", rp->data); } /* End protection against modification of the List */ Gate_leaveSystem(key);jj jjE jjj}rW (j@jAj]j]j]j]j]ujM jhj]rX jXkList_Elem *elem = NULL; Rec* rp; ... /* To start the search at the beginning of the List */ rp = NULL; /* Begin protection against modification of the List */ key = Gate_enterSystem(); while ((elem = List_next(myList, elem)) != NULL) { System_printf("rec: %d\n", rp->data); } /* End protection against modification of the List */ Gate_leaveSystem(key);rY rZ }r[ (jUjjU ubaubjc)r\ }r] (jUjj jjE jjfj}r^ (j]j]j]j]j]ujKgjhj]r_ ji)r` }ra (jUjlKjj\ jjE jjj}rb (j]j]j]j]j]ujKjhj]ubaubeubj)rc }rd (jUjj3 jjE jjj}re (j]j]j]j]rf U$inserting-and-removing-list-elementsrg aj]rh hiaujKjjhj]ri (j)rj }rk (jX$Inserting and Removing List Elementsrl jjc jjE jjj}rm (j]j]j]j]j]ujKjjhj]rn jX$Inserting and Removing List Elementsro rp }rq (jjl jjj ubaubj)rr }rs (jX4Elements can also be inserted or removed from anywhere in the middle of a List using List_insert() and List_remove(). List_insert() inserts an element in front of the specified element. Use List_putHead() to place an element at the front of the List and List_put() to place an element at the end of the List.rt jjc jjE jjj}ru (j]j]j]j]j]ujKkjhj]rv jX4Elements can also be inserted or removed from anywhere in the middle of a List using List_insert() and List_remove(). List_insert() inserts an element in front of the specified element. Use List_putHead() to place an element at the front of the List and List_put() to place an element at the end of the List.rw rx }ry (jjt jjr ubaubj)rz }r{ (jXHList_remove() removes the specified element from whatever List it is in.r| jjc jjE jjj}r} (j]j]j]j]j]ujKpjhj]r~ jXHList_remove() removes the specified element from whatever List it is in.r r }r (jj| jjz ubaubj)r }r (jXiNote that List does not provide any APIs for inserting or removing elements at a given index in the List.r jjc jjE jjj}r (j]j]j]j]j]ujKrjhj]r jXiNote that List does not provide any APIs for inserting or removing elements at a given index in the List.r r }r (jj jj ubaubj)r }r (jXY**Run-time example:** The following example demonstrates List_insert() and List_remove():r jjc jjE jjj}r (j]j]j]j]j]ujKtjhj]r (j)r }r (jX**Run-time example:**j}r (j]j]j]j]j]ujj j]r jXRun-time example:r r }r (jUjj ubajjubjXD The following example demonstrates List_insert() and List_remove():r r }r (jXD The following example demonstrates List_insert() and List_remove():jj ubeubj)r }r (jX/* Insert r2 in front of r1 in the List. */ List_insert(myList, &(r1.elem), &(r2.elem)); /* Remove r1 from the List. */ List_remove(myList, &(r1.elem));jjc jjE jjj}r (j@jAj]j]j]j]j]ujM1 jhj]r jX/* Insert r2 in front of r1 in the List. */ List_insert(myList, &(r1.elem), &(r2.elem)); /* Remove r1 from the List. */ List_remove(myList, &(r1.elem));r r }r (jUjj ubaubjc)r }r (jUjjc jjE jjfj}r (j]j]j]j]j]ujK~jhj]r ji)r }r (jUjlKjj jjE jjj}r (j]j]j]j]j]ujKjhj]ubaubj)r }r (jXp**Run-time example:** The following example treats the List as a LIFO stack using List_putHead() and List_get():r jjc jjE jjj}r (j]j]j]j]j]ujKjhj]r (j)r }r (jX**Run-time example:**j}r (j]j]j]j]j]ujj j]r jXRun-time example:r r }r (jUjj ubajjubjX[ The following example treats the List as a LIFO stack using List_putHead() and List_get():r r }r (jX[ The following example treats the List as a LIFO stack using List_putHead() and List_get():jj ubeubj)r }r (jX List_Elem elem[NUMELEM]; List_Elem *tmpElem; // push onto the top (i.e. head) for (i = 0; i < NUMELEM; i++) { List_putHead(listHandle, &(elem[i])); } // remove the buffers in FIFO order. while((tmpElem = List_get(listHandle)) != NULL) { // process tmpElem }jjc jjE jjj}r (j@jAj]j]j]j]j]ujM= jhj]r jX List_Elem elem[NUMELEM]; List_Elem *tmpElem; // push onto the top (i.e. head) for (i = 0; i < NUMELEM; i++) { List_putHead(listHandle, &(elem[i])); } // remove the buffers in FIFO order. while((tmpElem = List_get(listHandle)) != NULL) { // process tmpElem }r r }r (jUjj ubaubjc)r }r (jUjjc jjE jjfj}r (j]j]j]j]j]ujKjhj]r ji)r }r (jUjlKjj jjE jjj}r (j]j]j]j]j]ujKjhj]ubaubeubj)r }r (jUjj3 jjE jjj}r (j]j]j]j]r Uatomic-list-operationsr aj]r haujKjhj]r (j)r }r (jXAtomic List Operationsr jj jjE jjj}r (j]j]j]j]j]ujKjhj]r jXAtomic List Operationsr r }r (jj jj ubaubj)r }r (jXOLists are commonly shared across multiple threads in the system, which might lead to concurrent modifications of the List by different threads, which would corrupt the List. List provides several "atomic" APIs that disable interrupts before operating on the List. These APIs are List_get() List_put(), List_putHead(), and List_empty().r jj jjE jjj}r (j]j]j]j]j]ujKjhj]r jXOLists are commonly shared across multiple threads in the system, which might lead to concurrent modifications of the List by different threads, which would corrupt the List. List provides several "atomic" APIs that disable interrupts before operating on the List. These APIs are List_get() List_put(), List_putHead(), and List_empty().r r }r (jj jj ubaubj)r }r (jXAn atomic API completes in core functionality without being interrupted. Therefore, atomic APIs are thread-safe. An example is List_put(). Multiple threads can call this API at the same time. The threads do not have to manage the synchronization.r jj jjE jjj}r (j]j]j]j]j]ujKjhj]r jXAn atomic API completes in core functionality without being interrupted. Therefore, atomic APIs are thread-safe. An example is List_put(). Multiple threads can call this API at the same time. The threads do not have to manage the synchronization.r r }r (jj jj ubaubj)r }r (jXoOther APIs--List_prev(), List_next(), List_insert(), and List_remove()--should be protected by the application.r jj jjE jjj}r (j]j]j]j]j]ujKjhj]r jXoOther APIs--List_prev(), List_next(), List_insert(), and List_remove()--should be protected by the application.r r }r (jj jj ubaubeubeubj)r }r (jUjj jjjjj}r (j]j]j]j]r Umultiproc-moduler aj]r jgaujK]jhj]r (j)r }r (jXMultiProc Moduler jj jjjjj}r (j]j]j]j]j]ujK]jhj]r jXMultiProc Moduler r }r (jj jj ubaubj7)r }r (jXHhttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/MultiProc_Modulejj jj:X>source/rtos/PDK_Platform_Software/IPC/MultiProc_Module.rst.incr r }r bjj>j}r (j@jAj]j]j]j]j]ujKjhj]r jXHhttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/MultiProc_Moduler r }r (jUjj ubaubj)r }r (jX.. |mpmCfg_Img1| Image:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.html jj jj jjHj}r (j]j]j]j]j]r X mpmCfg_Img1r aujKjhj]r j)r }r (jj j}r (UrefuriXhhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlr j]j]j]j]j]ujj j]r jR)r }r (jXImage:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlr j}r (UuriXrtos/../images/Book_cfg.pngr j]j]j]j]jX}r U*j sj]Ualtj ujj j]jjZubajjubaubj)r }r (jX.. |mpmCfg_Img2| Image:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.html jj jj jjHj}r (j]j]j]j]j]r X mpmCfg_Img2r aujKjhj]r j)r }r (jj j}r (UrefuriXhhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlr j]j]j]j]j]ujj j]r jR)r }r! (jXImage:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlr" j}r# (UuriXrtos/../images/Book_cfg.pngr$ j]j]j]j]jX}r% U*j$ sj]Ualtj ujj j]jjZubajjubaubj)r& }r' (jX.. |mpmRun_Img1| Image:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_multi_proc_8h.html jj jj jjHj}r( (j]j]j]j]j]r) X mpmRun_Img1r* aujK jhj]r+ j)r, }r- (jj* j}r. (UrefuriXqhttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_multi_proc_8h.htmlr/ j]j]j]j]j]ujj& j]r0 jR)r1 }r2 (jXImage:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_multi_proc_8h.htmlr3 j}r4 (UuriXrtos/../images/Book_run.pngr5 j]j]j]j]jX}r6 U*j5 sj]Ualtj* ujj, j]jjZubajjubaubj)r7 }r8 (jX.. |mpmRun_Img2| Image:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_multi_proc_8h.html jj jj jjHj}r9 (j]j]j]j]j]r: X mpmRun_Img2r; aujK jhj]r< j)r= }r> (jj; j}r? (UrefuriXqhttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_multi_proc_8h.htmlr@ j]j]j]j]j]ujj7 j]rA jR)rB }rC (jXImage:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_multi_proc_8h.htmlrD j}rE (UuriXrtos/../images/Book_run.pngrF j]j]j]j]jX}rG U*jF sj]Ualtj; ujj= j]jjZubajjubaubjc)rH }rI (jUjj jj jjfj}rJ (j]j]j]j]j]ujKjhj]rK ji)rL }rM (jUjlKjjH jj jjj}rN (j]j]j]j]j]ujKjhj]ubaubj3)rO }rP (jUjj jj jj6j}rQ (j]j]j]j]j]ujNjhj]rR jy )rS }rT (jUj}rU (j]j]j]j]j]ujjO j]rV j~ )rW }rX (jUj}rY (j]j]j]j]j]UcolsKujjS j]rZ (j )r[ }r\ (jUj}r] (j]j]j]j]j]UcolwidthKujjW j]jj ubj )r^ }r_ (jUj}r` (j]j]j]j]j]UcolwidthKujjW j]jj ubj )ra }rb (jUj}rc (j]j]j]j]j]ujjW j]rd j )re }rf (jUj}rg (j]j]j]j]j]ujja j]rh j )ri }rj (jUj}rk (j]UmorecolsKj]j]j]j]ujje j]rl j)rm }rn (jXAPI Reference Linksro jji jj jjj}rp (j]j]j]j]j]ujKj]rq jXAPI Reference Linksrr rs }rt (jjo jjm ubaubajj ubajj ubajj ubj )ru }rv (jUj}rw (j]j]j]j]j]ujjW j]rx j )ry }rz (jUj}r{ (j]j]j]j]j]ujju j]r| (j )r} }r~ (jUj}r (j]j]j]j]j]ujjy j]r j)r }r (jX |mpmCfg_Img1|r jj} jj jjj}r (j]j]j]j]j]ujKj]r j)r }r (jj jj jNjjj}r (Urefurij j]j]j]j]j]ujNj]r jR)r }r (jj jj jNjjZj}r (UuriXrtos/../images/Book_cfg.pngr j]j]j]j]jX}r U*j sj]Ualtj ujNj]ubaubaubajj ubj )r }r (jUj}r (j]j]j]j]j]ujjy j]r j)r }r (jX |mpmRun_Img1|r jj jj jjj}r (j]j]j]j]j]ujKj]r j)r }r (jj* jj jNjjj}r (Urefurij/ j]j]j]j]j]ujNj]r jR)r }r (jj3 jj jNjjZj}r (UuriXrtos/../images/Book_run.pngr j]j]j]j]jX}r U*j sj]Ualtj* ujNj]ubaubaubajj ubejj ubajj ubejj ubajj ubaubj)r }r (jUjKjj jj jjj}r (j]r X introductionr aj]j]j]r Uid6r aj]ujKjhj]r (j)r }r (jX Introductionr jj jj jjj}r (j]j]j]j]j]ujKjhj]r jX Introductionr r }r (jj jj ubaubj)r }r (jX|Many IPC modules require the ability to uniquely specify and identify processors in a multi-processor environment. The MultiProc module centralizes processor ID management into one module. Most multi-processor IPC applications require that you configure this module using the MultiProc.setConfig() function in the *.cfg script. The setConfig() function tells the MultiProc module:jj jj jjj}r (j]j]j]j]j]ujKjhj]r (jX:Many IPC modules require the ability to uniquely specify and identify processors in a multi-processor environment. The MultiProc module centralizes processor ID management into one module. Most multi-processor IPC applications require that you configure this module using the MultiProc.setConfig() function in the r r }r (jX:Many IPC modules require the ability to uniquely specify and identify processors in a multi-processor environment. The MultiProc module centralizes processor ID management into one module. Most multi-processor IPC applications require that you configure this module using the MultiProc.setConfig() function in the jj ubcdocutils.nodes problematic r )r }r (jX*j}r (j]r Uid8r aj]j]j]j]UrefidUid7r ujj j]r jX*r }r (jUjj ubajU problematicr ubjXA.cfg script. The setConfig() function tells the MultiProc module:r r }r (jXA.cfg script. The setConfig() function tells the MultiProc module:jj ubeubjt)r }r (jUjj jj jjwj}r (jyX-j]j]j]j]j]ujK jhj]r (j{)r }r (jXAThe specific processor for which this application is being built.r jj jj jjj}r (j]j]j]j]j]ujNjhj]r j)r }r (jj jj jj jjj}r (j]j]j]j]j]ujK j]r jXAThe specific processor for which this application is being built.r r }r (jj jj ubaubaubj{)r }r (jXJThe processors in this cluster. A "cluster" is a set of processors within jj jj jjj}r (j]j]j]j]j]ujNjhj]r j)r }r (jXIThe processors in this cluster. A "cluster" is a set of processors withinr jj jj jjj}r (j]j]j]j]j]ujK!j]r jXIThe processors in this cluster. A "cluster" is a set of processors withinr r }r (jj jj ubaubaubeubj)r }r (jX^a system that share some memory and for which notification between those processors is needed.r jj jj jjj}r (j]j]j]j]j]ujK#jhj]r jX^a system that share some memory and for which notification between those processors is needed.r r }r (jj jj ubaubj)r }r (jXMost systems contain a single cluster. For systems with multiple clusters, you also need to configure the numProcessors and baseIdOfCluster properties.r jj jj jjj}r (j]j]j]j]j]ujK%jhj]r jXMost systems contain a single cluster. For systems with multiple clusters, you also need to configure the numProcessors and baseIdOfCluster properties.r r }r (jj jj ubaubj)r }r (jXEach processor reference by the MultiProc module can be uniquely identified by either its name string or an integer ranging from 0 to MultiProc.maxProcessors - 1.r jj jj jjj}r (j]j]j]j]j]ujK'jhj]r jXEach processor reference by the MultiProc module can be uniquely identified by either its name string or an integer ranging from 0 to MultiProc.maxProcessors - 1.r r }r (jj jj ubaubj)r }r (jXThe following XDCtools configuration statements set up a MultiProc array. At runtime, the "DSP" processor running this configuration gets assigned an ID value of 2. The other processors in the system are "VIDEO" with a processor ID of 0 and "DSS" with a processor ID of 1.r jj jj jjj}r (j]j]j]j]j]ujK)jhj]r jXThe following XDCtools configuration statements set up a MultiProc array. At runtime, the "DSP" processor running this configuration gets assigned an ID value of 2. The other processors in the system are "VIDEO" with a processor ID of 0 and "DSS" with a processor ID of 1.r r}r(jj jj ubaubj)r}r(jX/* DSP will get assigned processor id 2. */ var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc'); MultiProc.setConfig("DSP", ["VIDEO", "DSS", "DSP"]);jj jj jjj}r(j@jAj]j]j]j]j]ujM jhj]rjX/* DSP will get assigned processor id 2. */ var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc'); MultiProc.setConfig("DSP", ["VIDEO", "DSS", "DSP"]);rr}r(jUjjubaubjc)r }r (jUjj jj jjfj}r (j]j]j]j]j]ujK4jhj]r ji)r }r(jUjlKjj jj jjj}r(j]j]j]j]j]ujKjhj]ubaubj)r}r(jXThe ID is a software-only setting. It does not correlate to hardware core IDs or any other type of hardware identification. For devices with more than one core, each core must have its own unique processor ID. The ID is also independent of any OS setting. The processor ID is not always known at configuration time. It might need to be determined at initialization time via a GPIO pin, flash setting, or some other method. You can call the MultiProc_setLocalId() API (with the restriction that it must be called before module startup) to set the processor ID. However, other modules that use MultiProc need to know that the static ID will be changed during initialization. Setting the local name to NULL in the MultiProc.setConfig statement in the configuration indicates that the MultiProc_setLocalId() API will be used at runtime. Other modules that use MultiProc should act accordingly by deferring processing until the actual ID is known.rjj jj jjj}r(j]j]j]j]j]ujK6jhj]rjXThe ID is a software-only setting. It does not correlate to hardware core IDs or any other type of hardware identification. For devices with more than one core, each core must have its own unique processor ID. The ID is also independent of any OS setting. The processor ID is not always known at configuration time. It might need to be determined at initialization time via a GPIO pin, flash setting, or some other method. You can call the MultiProc_setLocalId() API (with the restriction that it must be called before module startup) to set the processor ID. However, other modules that use MultiProc need to know that the static ID will be changed during initialization. Setting the local name to NULL in the MultiProc.setConfig statement in the configuration indicates that the MultiProc_setLocalId() API will be used at runtime. Other modules that use MultiProc should act accordingly by deferring processing until the actual ID is known.rr}r(jjjjubaubj)r}r(jXFor example, the following fragment of configuration code requires that the MultiProc_setLocalId() API be run during startup to fill in the NULL processor name.rjj jj jjj}r(j]j]j]j]j]ujK9jhj]rjXFor example, the following fragment of configuration code requires that the MultiProc_setLocalId() API be run during startup to fill in the NULL processor name.rr}r(jjjjubaubj)r }r!(jX"/* Specify startup function */ var Startup = xdc.useModule('xdc.runtime.Startup'); Startup.firstFxns.$add('&setMyId'); /* Specify MultiProc config; current processor unknown */ var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc'); MultiProc.setConfig(null, ["CORE0", "CORE1", "CORE2"]);jj jj jjj}r"(j@jAj]j]j]j]j]ujM jhj]r#jX"/* Specify startup function */ var Startup = xdc.useModule('xdc.runtime.Startup'); Startup.firstFxns.$add('&setMyId'); /* Specify MultiProc config; current processor unknown */ var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc'); MultiProc.setConfig(null, ["CORE0", "CORE1", "CORE2"]);r$r%}r&(jUjj ubaubjc)r'}r((jUjj jj jjfj}r)(j]j]j]j]j]ujKEjhj]r*ji)r+}r,(jUjlKjj'jj jjj}r-(j]j]j]j]j]ujKjhj]ubaubj)r.}r/(jX_Then, the application code could contain the following setMyID() function to be run at startup:r0jj jj jjj}r1(j]j]j]j]j]ujKGjhj]r2jX_Then, the application code could contain the following setMyID() function to be run at startup:r3r4}r5(jj0jj.ubaubj)r6}r7(jX3Void setMyId() { UInt16 procId; Int status; // // Board specific determination of processor id. // Example: GPIO_READ reads register of GPIO pin 5 // if (GPIO_READ(5) == 0) { procId = 0; } else { procId = 1; } MultiProc_setLocalId(procId); }jj jj jjj}r8(j@jAj]j]j]j]j]ujM jhj]r9jX3Void setMyId() { UInt16 procId; Int status; // // Board specific determination of processor id. // Example: GPIO_READ reads register of GPIO pin 5 // if (GPIO_READ(5) == 0) { procId = 0; } else { procId = 1; } MultiProc_setLocalId(procId); }r:r;}r<(jUjj6ubaubjc)r=}r>(jUjj jj jjfj}r?(j]j]j]j]j]ujK^jhj]r@ji)rA}rB(jUjlKjj=jj jjj}rC(j]j]j]j]j]ujKjhj]ubaubj)rD}rE(jXYour application can query the MultiProc table using various runtime APIs. At runtime, the MultiProc_getId() call returns the MultiProc ID for any processor name. At config-time, the MultiProc.getIdMeta() call returns the same value. For example:rFjj jj jjj}rG(j]j]j]j]j]ujK`jhj]rHjXYour application can query the MultiProc table using various runtime APIs. At runtime, the MultiProc_getId() call returns the MultiProc ID for any processor name. At config-time, the MultiProc.getIdMeta() call returns the same value. For example:rIrJ}rK(jjFjjDubaubj)rL}rM(jX'core1ProcId = MultiProc_getId("CORE1");jj jj jjj}rN(j@jAj]j]j]j]j]ujM jhj]rOjX'core1ProcId = MultiProc_getId("CORE1");rPrQ}rR(jUjjLubaubjc)rS}rT(jUjj jj jjfj}rU(j]j]j]j]j]ujKgjhj]rVji)rW}rX(jUjlKjjSjj jjj}rY(j]j]j]j]j]ujKjhj]ubaubj)rZ}r[(jXXMultiProc_self() returns the processor ID of the processor running the API. For example:r\jj jj jjj}r](j]j]j]j]j]ujKijhj]r^jXXMultiProc_self() returns the processor ID of the processor running the API. For example:r_r`}ra(jj\jjZubaubj)rb}rc(jX:System_printf("My MultiProc id = %d\n", MultiProc_self());jj jj jjj}rd(j@jAj]j]j]j]j]ujM jhj]rejX:System_printf("My MultiProc id = %d\n", MultiProc_self());rfrg}rh(jUjjbubaubjc)ri}rj(jUjj jj jjfj}rk(j]j]j]j]j]ujKojhj]rlji)rm}rn(jUjlKjjijj jjj}ro(j]j]j]j]j]ujKjhj]ubaubj)rp}rq(jXMultiProc_getBaseIdOfCluster() returns the MultiProc ID of the base processor in the cluster to which this processor belongs. The MultiProc_getName() API returns that processor name if given the MultiProc ID. For example:rrjj jj jjj}rs(j]j]j]j]j]ujKqjhj]rtjXMultiProc_getBaseIdOfCluster() returns the MultiProc ID of the base processor in the cluster to which this processor belongs. The MultiProc_getName() API returns that processor name if given the MultiProc ID. For example:rurv}rw(jjrjjpubaubj)rx}ry(jX!core0Name = MultiProc_getName(0);jj jj jjj}rz(j@jAj]j]j]j]j]ujM jhj]r{jX!core0Name = MultiProc_getName(0);r|r}}r~(jUjjxubaubjc)r}r(jUjj jj jjfj}r(j]j]j]j]j]ujKxjhj]rji)r}r(jUjlKjjjj jjj}r(j]j]j]j]j]ujKjhj]ubaubj)r}r(jXIMultiProc_getNumProcessors() evaluates to the total number of processors.rjj jj jjj}r(j]j]j]j]j]ujKzjhj]rjXIMultiProc_getNumProcessors() evaluates to the total number of processors.rr}r(jjjjubaubj)r}r(jXhSystem_printf("Number of processors in the system = %d\n", MultiProc_getNumProcessors() );jj jj jjj}r(j@jAj]j]j]j]j]ujM jhj]rjXhSystem_printf("Number of processors in the system = %d\n", MultiProc_getNumProcessors() );rr}r(jUjjubaubjc)r}r(jUjj jj jjfj}r(j]j]j]j]j]ujKjhj]rji)r}r(jUjlKjjjj jjj}r(j]j]j]j]j]ujKjhj]ubaubj)r}r(jXMultiProc_getBaseIdOfCluster() returns the MultiProc ID of the base processor in the cluster to which this processor belongs. The MultiProc_getName() API returns that processor name if given the MultiProc ID. For example:rjj jj jjj}r(j]j]j]j]j]ujKjhj]rjXMultiProc_getBaseIdOfCluster() returns the MultiProc ID of the base processor in the cluster to which this processor belongs. The MultiProc_getName() API returns that processor name if given the MultiProc ID. For example:rr}r(jjjjubaubj)r}r(jX!core0Name = MultiProc_getName(0);jj jj jjj}r(j@jAj]j]j]j]j]ujM jhj]rjX!core0Name = MultiProc_getName(0);rr}r(jUjjubaubjc)r}r(jUjj jj jjfj}r(j]j]j]j]j]ujKjhj]rji)r}r(jUjlKjjjj jjj}r(j]j]j]j]j]ujKjhj]ubaubj)r}r(jXIMultiProc_getNumProcessors() evaluates to the total number of processors.rjj jj jjj}r(j]j]j]j]j]ujKjhj]rjXIMultiProc_getNumProcessors() evaluates to the total number of processors.rr}r(jjjjubaubj)r}r(jXhSystem_printf("Number of processors in the system = %d\n", MultiProc_getNumProcessors() );jj jj jjj}r(j@jAj]j]j]j]j]ujM jhj]rjXhSystem_printf("Number of processors in the system = %d\n", MultiProc_getNumProcessors() );rr}r(jUjjubaubjc)r}r(jUjj jj jjfj}r(j]j]j]j]j]ujKjhj]rji)r}r(jUjlKjjjj jjj}r(j]j]j]j]j]ujKjhj]ubaubj)r}r(jXqMultiProc_getNumProcsInCluster() returns the number of processors in the cluster to which this processor belongs.rjj jj jjj}r(j]j]j]j]j]ujKjhj]rjXqMultiProc_getNumProcsInCluster() returns the number of processors in the cluster to which this processor belongs.rr}r(jjjjubaubeubj)r}r(jUjj jj jjj}r(j]j]j]j]rU.configuring-clusters-with-the-multiproc-moduleraj]rjeaujKjhj]r(j)r}r(jX.Configuring Clusters With the MultiProc Modulerjjjj jjj}r(j]j]j]j]j]ujKjhj]rjX.Configuring Clusters With the MultiProc Modulerr}r(jjjjubaubj)r}r(jXCA "cluster" is a set of processors within a system that share some memory and for which notification between those processors is needed. If your system has multiple clusters, you need to configure the MultiProc module's numProcessors and baseIdOfCluster properties in addition to calling the MultiProc.setConfig() function.rjjjj jjj}r(j]j]j]j]j]ujKjhj]rjXCA "cluster" is a set of processors within a system that share some memory and for which notification between those processors is needed. If your system has multiple clusters, you need to configure the MultiProc module's numProcessors and baseIdOfCluster properties in addition to calling the MultiProc.setConfig() function.rr}r(jjjjubaubj)r}r(jX;Notifications are not supported between different clusters.rjjjj jjj}r(j]j]j]j]j]ujKjhj]rjX;Notifications are not supported between different clusters.rr}r(jjjjubaubj)r}r(jXFor example, in a system with two 'C6678 devices that each use eight homogeneous cores, you could configure the first 'C6678 device as follows:rjjjj jjj}r(j]j]j]j]j]ujKjhj]rjXFor example, in a system with two 'C6678 devices that each use eight homogeneous cores, you could configure the first 'C6678 device as follows:rr}r(jjjjubaubj)r}r(jXvar MultiProc = xdc.useModule('ti.sdo.utils.MultiProc'); MultiProc.baseIdOfCluster = 0; MultiProc.numProcessors = 16; MultiProc.setConfig(null, ["CORE0", "CORE1", "CORE2", "CORE3", "CORE4", "CORE5", "CORE6", "CORE7"]);jjjj jjj}r(j@jAj]j]j]j]j]ujM jhj]rjXvar MultiProc = xdc.useModule('ti.sdo.utils.MultiProc'); MultiProc.baseIdOfCluster = 0; MultiProc.numProcessors = 16; MultiProc.setConfig(null, ["CORE0", "CORE1", "CORE2", "CORE3", "CORE4", "CORE5", "CORE6", "CORE7"]);rr}r(jUjjubaubjc)r}r(jUjjjj jjfj}r(j]j]j]j]j]ujKjhj]rji)r}r(jUjlKjjjj jjj}r(j]j]j]j]j]ujKjhj]ubaubj)r}r(jX8You could configure the second 'C6678 device as follows:rjjjj jjj}r(j]j]j]j]j]ujKjhj]r jX8You could configure the second 'C6678 device as follows:r r }r (jjjjubaubj)r }r(jXvar MultiProc = xdc.useModule('ti.sdo.utils.MultiProc'); MultiProc.baseIdOfCluster = 8; MultiProc.numProcessors = 16; MultiProc.setConfig(null, ["CORE0", "CORE1", "CORE2", "CORE3", "CORE4", "CORE5", "CORE6", "CORE7"]);jjjj jjj}r(j@jAj]j]j]j]j]ujM jhj]rjXvar MultiProc = xdc.useModule('ti.sdo.utils.MultiProc'); MultiProc.baseIdOfCluster = 8; MultiProc.numProcessors = 16; MultiProc.setConfig(null, ["CORE0", "CORE1", "CORE2", "CORE3", "CORE4", "CORE5", "CORE6", "CORE7"]);rr}r(jUjj ubaubjc)r}r(jUjjjj jjfj}r(j]j]j]j]j]ujKjhj]rji)r}r(jUjlKjjjj jjj}r(j]j]j]j]j]ujKjhj]ubaubj)r}r(jXSNotice that the MultiProc.numProcessors property specifies the total number of processors in the system, while the length of the array passed to setConfig() specifies the number of processors in the cluster. (If you are not using multiple clusters, the numProcessors property is configured automatically.) The MultiProc.baseIdOfCluster property is set to the MultiProc ID number you want to use for the first processor in the array for this cluster. For example, if there are 8 processors in a cluster, the baseIdOfCluster property should be 0 for the first cluster and 8 for the second cluster.rjjjj jjj}r(j]j]j]j]j]ujKjhj]rjXSNotice that the MultiProc.numProcessors property specifies the total number of processors in the system, while the length of the array passed to setConfig() specifies the number of processors in the cluster. (If you are not using multiple clusters, the numProcessors property is configured automatically.) The MultiProc.baseIdOfCluster property is set to the MultiProc ID number you want to use for the first processor in the array for this cluster. For example, if there are 8 processors in a cluster, the baseIdOfCluster property should be 0 for the first cluster and 8 for the second cluster.r r!}r"(jjjjubaubj)r#}r$(jX|mpmCfg_Img2| The latest version of the MultiProc module configuration documentation is available in `MultiProc page `_jjjj jjj}r%(j]j]j]j]j]ujKjhj]r&(j)r'}r((jj jj#jNjjj}r)(Urefurij j]j]j]j]j]ujNjhj]r*jR)r+}r,(jj" jj'jNjjZj}r-(UuriXrtos/../images/Book_cfg.pngr.j]j]j]j]jX}r/U*j.sj]Ualtj ujNj]ubaubjXX The latest version of the MultiProc module configuration documentation is available in r0r1}r2(jXX The latest version of the MultiProc module configuration documentation is available in jj#ubj)r3}r4(jX`MultiProc page `_j}r5(UnameXMultiProc pagejX~http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/index.html#ti/sdo/utils/MultiProc.htmlr6j]j]j]j]j]ujj#j]r7jXMultiProc pager8r9}r:(jUjj3ubajjubj)r;}r<(jX jKjj#jj j}r=(Urefurij6j]r>Umultiproc-pager?aj]j]j]j]r@jauj]ubeubeubj)rA}rB(jUjj jj jjj}rC(j]j]j]j]rDU#creating-connections-with-multiprocrEaj]rFj aujKjhj]rG(j)rH}rI(jX#Creating Connections with MultiProcrJjjAjj jjj}rK(j]j]j]j]j]ujKjhj]rLjX#Creating Connections with MultiProcrMrN}rO(jjJjjHubaubj)rP}rQ(jXvThe Ipc_start() and Ipc_attach() APIs can only be used to attach and synchronizes with processors in the same cluster.rRjjAjj jjj}rS(j]j]j]j]j]ujKjhj]rTjXvThe Ipc_start() and Ipc_attach() APIs can only be used to attach and synchronizes with processors in the same cluster.rUrV}rW(jjRjjPubaubj)rX}rY(jXQTo create a connection between cores in different clusters, you must manually create a connection using the MessageQ and ti.sdo.ipc.NameServerMessageQ modules. The NameServerMessageQ module supports NameServer requests between different clusters by using MessageQ, which in turns uses the MessageQ transport to send a NameServer request.rZjjAjj jjj}r[(j]j]j]j]j]ujKjhj]r\jXQTo create a connection between cores in different clusters, you must manually create a connection using the MessageQ and ti.sdo.ipc.NameServerMessageQ modules. The NameServerMessageQ module supports NameServer requests between different clusters by using MessageQ, which in turns uses the MessageQ transport to send a NameServer request.r]r^}r_(jjZjjXubaubj)r`}ra(jXzYou can control the timeout period for the NameServerMessageQ module by configuring its timeoutInMicroSecs parameter, which defaults to 1 second. If a response is not received within the timeout period, the NameServer request returns a failure status. The NameServerRemoteNotify module also has a timeoutInMicroSecs parameter that you can configure; it defaults to wait forever.rbjjAjj jjj}rc(j]j]j]j]j]ujKjhj]rdjXzYou can control the timeout period for the NameServerMessageQ module by configuring its timeoutInMicroSecs parameter, which defaults to 1 second. If a response is not received within the timeout period, the NameServer request returns a failure status. The NameServerRemoteNotify module also has a timeoutInMicroSecs parameter that you can configure; it defaults to wait forever.rerf}rg(jjbjj`ubaubj)rh}ri(jXCreating a connection between cores in different clusters allows you to call MessageQ_open() even for a core on a different cluster. Note that these calls must occur after the MessageQ heap has been registered, because they allocate memory from the heap.rjjjAjj jjj}rk(j]j]j]j]j]ujKjhj]rljXCreating a connection between cores in different clusters allows you to call MessageQ_open() even for a core on a different cluster. Note that these calls must occur after the MessageQ heap has been registered, because they allocate memory from the heap.rmrn}ro(jjjjjhubaubj)rp}rq(jXOnce the connection has been created, MessageQ can be used between different processors on different clusters just as it is used between different processors in the same cluster.rrjjAjj jjj}rs(j]j]j]j]j]ujKjhj]rtjXOnce the connection has been created, MessageQ can be used between different processors on different clusters just as it is used between different processors in the same cluster.rurv}rw(jjrjjpubaubj)rx}ry(jX|mpmRun_Img2| The latest version of the MultiProc module run-time API documentation is available in `MultiProc run-time API `_jjAjj jjj}rz(j]j]j]j]j]ujKjhj]r{(j)r|}r}(jj; jjxjNjjj}r~(Urefurij@ j]j]j]j]j]ujNjhj]rjR)r}r(jjD jj|jNjjZj}r(UuriXrtos/../images/Book_run.pngrj]j]j]j]jX}rU*jsj]Ualtj; ujNj]ubaubjXW The latest version of the MultiProc module run-time API documentation is available in rr}r(jXW The latest version of the MultiProc module run-time API documentation is available in jjxubj)r}r(jX`MultiProc run-time API `_j}r(UnameXMultiProc run-time APIjXqhttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_multi_proc_8h.htmlrj]j]j]j]j]ujjxj]rjXMultiProc run-time APIrr}r(jUjjubajjubj)r}r(jXu jKjjxjj j}r(Urefurijj]rUmultiproc-run-time-apiraj]j]j]j]rjCauj]ubeubeubj)r}r(jUjKjj jj jjj}r(j]rXexampleraj]j]j]rUexampleraj]ujKjhj]r(j)r}r(jXExamplerjjjj jjj}r(j]j]j]j]j]ujKjhj]rjXExamplerr}r(jjjjubaubj)r}r(jXThe following example function creates a NameServerMessageQ and TransportXXX to communicate remotely with a processor in a different cluster. The "remoteProcId" would be specified to be the MultiProc ID of the processor in the system. "TransportXXX" must be a copy-based transport that does not require any shared memory. You would need to create such a transport, because IPC does not provide one.rjjjj jjj}r(j]j]j]j]j]ujKjhj]rjXThe following example function creates a NameServerMessageQ and TransportXXX to communicate remotely with a processor in a different cluster. The "remoteProcId" would be specified to be the MultiProc ID of the processor in the system. "TransportXXX" must be a copy-based transport that does not require any shared memory. You would need to create such a transport, because IPC does not provide one.rr}r(jjjjubaubj)r}r(jXVoid myRemoteCreateFunction(Uint16 remoteProcId) { NameServerMessageQ_Params nsParams; NameServerMessageQ_Handle nsHandle; TransportXXX_Handle tranHandle; TransportXXX_Params tranParams; Error_Block eb; Error_init(&eb); /* * Note: You must register a MessageQ heap prior to * calling NameServerMessageQ_create(). */ /* init nsParams */ NameServerMessageQ_Params_init(&nsParams); /* create driver to remote processor */ nsHandle = NameServerMessageQ_create( remoteProcId, /* MultiProc ID of proc on 2nd cluster */ &nsParams, &eb); if (nsHandle == NULL) { SYS_abort("NameServerMessageQ_create() failed"); } /* initialize the transport parameters */ TransportXXX_Params_init(&tranParams); tranHandle = TransportXXX_create( remoteProcId, /* MultiProc ID of proc on 2nd cluster */ &tranParams, &eb); if (tranHandle == NULL) { SYS_abort("TransportXXX_create() failed"); } }jjjj jjj}r(j@jAj]j]j]j]j]ujM3 jhj]rjXVoid myRemoteCreateFunction(Uint16 remoteProcId) { NameServerMessageQ_Params nsParams; NameServerMessageQ_Handle nsHandle; TransportXXX_Handle tranHandle; TransportXXX_Params tranParams; Error_Block eb; Error_init(&eb); /* * Note: You must register a MessageQ heap prior to * calling NameServerMessageQ_create(). */ /* init nsParams */ NameServerMessageQ_Params_init(&nsParams); /* create driver to remote processor */ nsHandle = NameServerMessageQ_create( remoteProcId, /* MultiProc ID of proc on 2nd cluster */ &nsParams, &eb); if (nsHandle == NULL) { SYS_abort("NameServerMessageQ_create() failed"); } /* initialize the transport parameters */ TransportXXX_Params_init(&tranParams); tranHandle = TransportXXX_create( remoteProcId, /* MultiProc ID of proc on 2nd cluster */ &tranParams, &eb); if (tranHandle == NULL) { SYS_abort("TransportXXX_create() failed"); } }rr}r(jUjjubaubjc)r}r(jUjjjj jjfj}r(j]j]j]j]j]ujKjhj]rji)r}r(jUjlKjjjj jjj}r(j]j]j]j]j]ujKjhj]ubaubeubeubj)r}r(jUjj jjjjj}r(j]j]j]j]rUnameserver-moduleraj]rjaaujKajhj]r(j)r}r(jXNameServer Modulerjjjjjjj}r(j]j]j]j]j]ujKajhj]rjXNameServer Modulerr}r(jjjjubaubj7)r}r(jXIhttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/NameServer_Modulejjjj:X;source/rtos/PDK_Platform_Software/IPC/NameServer_Module.incrr}rbjj>j}r(j@jAj]j]j]j]j]ujKjhj]rjXIhttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/NameServer_Modulerr}r(jUjjubaubj)r}r(jX.. |nsmCfg_Img1| Image:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/index.html#ti/sdo/utils/NameServer.html jjjjjjHj}r(j]j]j]j]j]rX nsmCfg_Img1raujKjhj]rj)r}r(jjj}r(UrefuriXhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/index.html#ti/sdo/utils/NameServer.htmlrj]j]j]j]j]ujjj]rjR)r}r(jXImage:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/index.html#ti/sdo/utils/NameServer.htmlrj}r(UuriXrtos/../images/Book_cfg.pngrj]j]j]j]jX}rU*jsj]Ualtjujjj]jjZubajjubaubj)r}r(jX.. |nsmCfg_Img2| Image:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.html jjjjjjHj}r(j]j]j]j]j]rX nsmCfg_Img2raujKjhj]rj)r}r(jjj}r(UrefuriXhhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlrj]j]j]j]j]ujjj]rjR)r}r(jXImage:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlrj}r(UuriXrtos/../images/Book_cfg.pngrj]j]j]j]jX}rU*jsj]Ualtjujjj]jjZubajjubaubj)r}r(jX.. |nsmRun_Img1| Image:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_name_server_8h.html jjjjjjHj}r(j]j]j]j]j]rX nsmRun_Img1raujK jhj]rj)r}r(jjj}r(UrefuriXrhttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_name_server_8h.htmlrj]j]j]j]j]ujjj]rjR)r}r(jXImage:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_name_server_8h.htmlrj}r(UuriXrtos/../images/Book_run.pngrj]j]j]j]jX}rU*jsj]Ualtjujjj]jjZubajjubaubj)r}r (jX.. |nsmRun_Img2| Image:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_name_server_8h.html jjjjjjHj}r (j]j]j]j]j]r X nsmRun_Img2r aujK jhj]r j)r}r(jj j}r(UrefuriXrhttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_name_server_8h.htmlrj]j]j]j]j]ujjj]rjR)r}r(jXImage:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_name_server_8h.htmlrj}r(UuriXrtos/../images/Book_run.pngrj]j]j]j]jX}rU*jsj]Ualtj ujjj]jjZubajjubaubjc)r}r(jUjjjjjjfj}r(j]j]j]j]j]ujKjhj]rji)r}r(jUjlKjjjjjjj}r(j]j]j]j]j]ujKjhj]ubaubj3)r }r!(jUjjjjjj6j}r"(j]j]j]j]j]ujNjhj]r#jy )r$}r%(jUj}r&(j]j]j]j]j]ujj j]r'j~ )r(}r)(jUj}r*(j]j]j]j]j]UcolsKujj$j]r+(j )r,}r-(jUj}r.(j]j]j]j]j]UcolwidthKujj(j]jj ubj )r/}r0(jUj}r1(j]j]j]j]j]UcolwidthKujj(j]jj ubj )r2}r3(jUj}r4(j]j]j]j]j]ujj(j]r5j )r6}r7(jUj}r8(j]j]j]j]j]ujj2j]r9j )r:}r;(jUj}r<(j]UmorecolsKj]j]j]j]ujj6j]r=j)r>}r?(jXAPI Reference Linksr@jj:jjjjj}rA(j]j]j]j]j]ujKj]rBjXAPI Reference LinksrCrD}rE(jj@jj>ubaubajj ubajj ubajj ubj )rF}rG(jUj}rH(j]j]j]j]j]ujj(j]rIj )rJ}rK(jUj}rL(j]j]j]j]j]ujjFj]rM(j )rN}rO(jUj}rP(j]j]j]j]j]ujjJj]rQj)rR}rS(jX |nsmCfg_Img1|rTjjNjjjjj}rU(j]j]j]j]j]ujKj]rVj)rW}rX(jjjjRjNjjj}rY(Urefurijj]j]j]j]j]ujNj]rZjR)r[}r\(jjjjWjNjjZj}r](UuriXrtos/../images/Book_cfg.pngr^j]j]j]j]jX}r_U*j^sj]UaltjujNj]ubaubaubajj ubj )r`}ra(jUj}rb(j]j]j]j]j]ujjJj]rcj)rd}re(jX |nsmRun_Img1|rfjj`jjjjj}rg(j]j]j]j]j]ujKj]rhj)ri}rj(jjjjdjNjjj}rk(Urefurijj]j]j]j]j]ujNj]rljR)rm}rn(jjjjijNjjZj}ro(UuriXrtos/../images/Book_run.pngrpj]j]j]j]jX}rqU*jpsj]UaltjujNj]ubaubaubajj ubejj ubajj ubejj ubajj ubaubj)rr}rs(jXUThe NameServer module manages local name/value pairs. This enables an application and other modules to store and retrieve values based on a name. The NameServer module maintains thread-safety for its APIs. However, NameServer APIs cannot be called from an interrupt (that is, Hwi context). They can be called from Swis (BIOS-only) and Tasks.rtjjjjjjj}ru(j]j]j]j]j]ujKjhj]rvjXUThe NameServer module manages local name/value pairs. This enables an application and other modules to store and retrieve values based on a name. The NameServer module maintains thread-safety for its APIs. However, NameServer APIs cannot be called from an interrupt (that is, Hwi context). They can be called from Swis (BIOS-only) and Tasks.rwrx}ry(jjtjjrubaubj)rz}r{(jXThis module supports different lengths of values. The NameServer_add() and NameServer_get() functions support variable-length values. The NameServer_addUInt32() function is optimized for UInt32 variables and constants.r|jjjjjjj}r}(j]j]j]j]j]ujKjhj]r~jXThis module supports different lengths of values. The NameServer_add() and NameServer_get() functions support variable-length values. The NameServer_addUInt32() function is optimized for UInt32 variables and constants.rr}r(jj|jjzubaubj)r}r(jXThe NameServer module currently does not perform any endian or word size conversion. Also there is no asynchronous support at this time.rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXThe NameServer module currently does not perform any endian or word size conversion. Also there is no asynchronous support at this time.rr}r(jjjjubaubj)r}r(jXnYou can create NameServer instances dynamically. On BIOS, you can also create NameServer instances statically.rjjjjjjj}r(j]j]j]j]j]ujK jhj]rjXnYou can create NameServer instances dynamically. On BIOS, you can also create NameServer instances statically.rr}r(jjjjubaubj)r}r(jUjjjjjjj}r(j]j]j]j]rU2creating-nameserver-instances-statically-bios-onlyraj]rhaujK#jhj]r(j)r}r(jX4Creating NameServer Instances Statically (BIOS-only)rjjjjjjj}r(j]j]j]j]j]ujK#jhj]rjX4Creating NameServer Instances Statically (BIOS-only)rr}r(jjjjubaubj)r}r(jXTo create a NameServer instance statically, you can add statements similar to the following to your XDCtools configuration script:rjjjjjjj}r(j]j]j]j]j]ujK$jhj]rjXTo create a NameServer instance statically, you can add statements similar to the following to your XDCtools configuration script:rr}r(jjjjubaubj)r}r(jXvar NameServer = xdc.useModule('ti.sdo.utils.NameServer'); var nameServerParams = new NameServer.Params; nameServerParams.maxRuntimeEntries = 10; nameServerParams.maxNameLen = 32; var nameServer0 = NameServer.create("nameServer0", nameServerParams);jjjjjjj}r(j@jAj]j]j]j]j]ujM jhj]rjXvar NameServer = xdc.useModule('ti.sdo.utils.NameServer'); var nameServerParams = new NameServer.Params; nameServerParams.maxRuntimeEntries = 10; nameServerParams.maxNameLen = 32; var nameServer0 = NameServer.create("nameServer0", nameServerParams);rr}r(jUjjubaubj)r}r(jXIf you want to specify the heap to be used by the NameServer module and a NameServer instance, use configuration statements similar to the following:rjjjjjjj}r(j]j]j]j]j]ujK/jhj]rjXIf you want to specify the heap to be used by the NameServer module and a NameServer instance, use configuration statements similar to the following:rr}r(jjjjubaubj)r}r(jXzvar NameServer = xdc.useModule('ti.sdo.utils.NameServer'); var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem'); var heapParams = new HeapMem.Params; heapParams.size = 1024; var heapMem = HeapMem.create(heapParams); var nameServerParams = new NameServer.Params; nameServerParams.tableHeap = heapMem; var nameServer = NameServer.create("staticNameServer", nameServerParams);jjjjjjj}r(j@jAj]j]j]j]j]ujM jhj]rjXzvar NameServer = xdc.useModule('ti.sdo.utils.NameServer'); var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem'); var heapParams = new HeapMem.Params; heapParams.size = 1024; var heapMem = HeapMem.create(heapParams); var nameServerParams = new NameServer.Params; nameServerParams.tableHeap = heapMem; var nameServer = NameServer.create("staticNameServer", nameServerParams);rr}r(jUjjubaubj)r}r(jXTo create a NameServer instance dynamically, initialize a NameServer_Params structure with NameServer_Params_init() and customize the values as needed. The parameters include the following:rjjjjjjj}r(j]j]j]j]j]ujK?jhj]rjXTo create a NameServer instance dynamically, initialize a NameServer_Params structure with NameServer_Params_init() and customize the values as needed. The parameters include the following:rr}r(jjjjubaubjt)r}r(jUjjjjjjwj}r(jyX-j]j]j]j]j]ujKCjhj]r(j{)r}r(jXv**checkExisting.** If true, NameServer check to see if a name already exists in the name/value table before adding it.rjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujKCj]r(j)r}r(jX**checkExisting.**j}r(j]j]j]j]j]ujjj]rjXcheckExisting.rr}r(jUjjubajjubjXd If true, NameServer check to see if a name already exists in the name/value table before adding it.rr}r(jXd If true, NameServer check to see if a name already exists in the name/value table before adding it.jjubeubaubj{)r}r(jXZ**maxNameLen.** Specify the maximum length, in characters, of the name field in the table.rjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujKDj]r(j)r}r(jX**maxNameLen.**j}r(j]j]j]j]j]ujjj]rjX maxNameLen.rr}r(jUjjubajjubjXK Specify the maximum length, in characters, of the name field in the table.rr}r(jXK Specify the maximum length, in characters, of the name field in the table.jjubeubaubj{)r}r(jX**maxRuntimeEntries.** Specify the maximum number of name/value pairs this table can hold. If you set this parameter to NameServer_ALLOWGROWTH, then NameServer allows dynamic growth of the table.rjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujKEj]r(j)r}r(jX**maxRuntimeEntries.**j}r(j]j]j]j]j]ujjj]rjXmaxRuntimeEntries.rr}r(jUjjubajjubjX Specify the maximum number of name/value pairs this table can hold. If you set this parameter to NameServer_ALLOWGROWTH, then NameServer allows dynamic growth of the table.rr}r(jX Specify the maximum number of name/value pairs this table can hold. If you set this parameter to NameServer_ALLOWGROWTH, then NameServer allows dynamic growth of the table.jjubeubaubj{)r}r(jXV**maxValueLen.** Specify the maximum length, in MAUs, of the value field in the table.rjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r }r (jjjjjjjjj}r (j]j]j]j]j]ujKFj]r (j)r }r(jX**maxValueLen.**j}r(j]j]j]j]j]ujj j]rjX maxValueLen.rr}r(jUjj ubajjubjXF Specify the maximum length, in MAUs, of the value field in the table.rr}r(jXF Specify the maximum length, in MAUs, of the value field in the table.jj ubeubaubj{)r}r(jX**tableHeap.** The heap to allocate the name/value table from when allocating dynamically. If this parameter is NULL, the heap used for object allocation is also used here. jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX**tableHeap.** The heap to allocate the name/value table from when allocating dynamically. If this parameter is NULL, the heap used for object allocation is also used here.jjjjjjj}r(j]j]j]j]j]ujKGj]r(j)r}r (jX**tableHeap.**j}r!(j]j]j]j]j]ujjj]r"jX tableHeap.r#r$}r%(jUjjubajjubjX The heap to allocate the name/value table from when allocating dynamically. If this parameter is NULL, the heap used for object allocation is also used here.r&r'}r((jX The heap to allocate the name/value table from when allocating dynamically. If this parameter is NULL, the heap used for object allocation is also used here.jjubeubaubeubj)r)}r*(jXAfter setting parameters, use NameServer_create() to create an instance. Each NameServer instance manages its own name/value table.r+jjjjjjj}r,(j]j]j]j]j]ujKIjhj]r-jXAfter setting parameters, use NameServer_create() to create an instance. Each NameServer instance manages its own name/value table.r.r/}r0(jj+jj)ubaubj)r1}r2(jX|nsmCfg_Img2| The latest version of the NameServer module configuration documentation is available `online `_.jjjjjjj}r3(j]j]j]j]j]ujKLjhj]r4(j)r5}r6(jjjj1jNjjj}r7(Urefurijj]j]j]j]j]ujNjhj]r8jR)r9}r:(jjjj5jNjjZj}r;(UuriXrtos/../images/Book_cfg.pngr<j]j]j]j]jX}r=U*j<sj]UaltjujNj]ubaubjXV The latest version of the NameServer module configuration documentation is available r>r?}r@(jXV The latest version of the NameServer module configuration documentation is available jj1ubj)rA}rB(jXt`online `_j}rC(UnameXonlinerDjXhhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlrEj]j]j]j]j]ujj1j]rFjXonlinerGrH}rI(jUjjAubajjubj)rJ}rK(jXk jKjj1jj j}rL(UrefurijEj]rMUid9rNaj]j]rOjDaj]j]uj]ubjX.rP}rQ(jX.jj1ubeubeubj)rR}rS(jUjjjjjjj}rT(j]j]j]j]rUU6creating-and-removing-nameserver-instances-dynamicallyrVaj]rWhaujKPjhj]rX(j)rY}rZ(jX6Creating and Removing NameServer Instances Dynamicallyr[jjRjjjjj}r\(j]j]j]j]j]ujKPjhj]r]jX6Creating and Removing NameServer Instances Dynamicallyr^r_}r`(jj[jjYubaubj)ra}rb(jXThe following C example creates a NameServer instance dynamically. The instance allows a maximum of 10 runtime entries (instead of using ALLOWGROWTH). This example also specifies where to allocate the memory needed for the tables (instead of using the default).rcjjRjjjjj}rd(j]j]j]j]j]ujKQjhj]rejXThe following C example creates a NameServer instance dynamically. The instance allows a maximum of 10 runtime entries (instead of using ALLOWGROWTH). This example also specifies where to allocate the memory needed for the tables (instead of using the default).rfrg}rh(jjcjjaubaubj)ri}rj(jXNameServer_Handle NSHandle; NameServer_Params params; NameServer_Params_init(¶ms); params.tableHeap = HeapStd_Handle_upCast(myHeap); params.maxRuntimeEntries = 10; NSHandle = NameServer_create("myTable", ¶ms); if (NSHandle == NULL) { // manage error }jjRjjjjj}rk(j@jAj]j]j]j]j]ujM jhj]rljXNameServer_Handle NSHandle; NameServer_Params params; NameServer_Params_init(¶ms); params.tableHeap = HeapStd_Handle_upCast(myHeap); params.maxRuntimeEntries = 10; NSHandle = NameServer_create("myTable", ¶ms); if (NSHandle == NULL) { // manage error }rmrn}ro(jUjjiubaubj)rp}rq(jX9This example C code adds and removes entries at run-time:rrjjRjjjjj}rs(j]j]j]j]j]ujKbjhj]rtjX9This example C code adds and removes entries at run-time:rurv}rw(jjrjjpubaubj)rx}ry(jXPtr key; key = NameServer_addUInt32(NSHandle, "volume", 5); if (key == NULL) { // manage error } NameServer_removeEntry(NSHandle, key); // or NameServer_remove(NSHandle, "volume");jjRjjjjj}rz(j@jAj]j]j]j]j]ujM jhj]r{jXPtr key; key = NameServer_addUInt32(NSHandle, "volume", 5); if (key == NULL) { // manage error } NameServer_removeEntry(NSHandle, key); // or NameServer_remove(NSHandle, "volume");r|r}}r~(jUjjxubaubj)r}r(jX|nsmRun_Img2| The latest version of the NameServer module run-time API documentation is available `online `_.jjRjjjjj}r(j]j]j]j]j]ujKrjhj]r(j)r}r(jj jjjNjjj}r(Urefurijj]j]j]j]j]ujNjhj]rjR)r}r(jjjjjNjjZj}r(UuriXrtos/../images/Book_run.pngrj]j]j]j]jX}rU*jsj]Ualtj ujNj]ubaubjXU The latest version of the NameServer module run-time API documentation is available rr}r(jXU The latest version of the NameServer module run-time API documentation is available jjubj)r}r(jX~`online `_j}r(UnameXonlinerjXrhttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_name_server_8h.htmlrj]j]j]j]j]ujjj]rjXonlinerr}r(jUjjubajjubj)r}r(jXu jKjjjj j}r(Urefurijj]rUid10raj]j]rjaj]j]uj]ubjX.r}r(jX.jjubeubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rUsearching-nameserver-instancesraj]rhaujKwjhj]r(j)r}r(jXSearching NameServer Instancesrjjjjjjj}r(j]j]j]j]j]ujKwjhj]rjXSearching NameServer Instancesrr}r(jjjjubaubj)r}r(jXThe following example searches the NameServer instance pointed to by "handle" on the specified processor for a name-value pair with the name stored in nameToFind. It returns the value of the pair to valueBuf.rjjjjjjj}r(j]j]j]j]j]ujKxjhj]rjXThe following example searches the NameServer instance pointed to by "handle" on the specified processor for a name-value pair with the name stored in nameToFind. It returns the value of the pair to valueBuf.rr}r(jjjjubaubj)r}r(jXh/* Search NameServer */ status = NameServer_get(NSHandle, nameToFind, valueBuf, sizeof(UInt32), procId);jjjjjjj}r(j@jAj]j]j]j]j]ujM jhj]rjXh/* Search NameServer */ status = NameServer_get(NSHandle, nameToFind, valueBuf, sizeof(UInt32), procId);rr}r(jUjjubaubj)r}r(jXlUsing different parameters for different table instances allows you to meet requirements like the following:rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXlUsing different parameters for different table instances allows you to meet requirements like the following:rr}r(jjjjubaubjt)r}r(jUjjjjjjwj}r(jyX-j]j]j]j]j]ujKjhj]r(j{)r}r(jX**Size differences.** The maxValueLen parameter specifies the maximum length, in MAUs, of the value field in the table. One table could allow long values (for example, > 32 bits), while another table could be used to store integers. This customization enables better memory usage.rjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujKj]r(j)r}r(jX**Size differences.**j}r(j]j]j]j]j]ujjj]rjXSize differences.rr}r(jUjjubajjubjX The maxValueLen parameter specifies the maximum length, in MAUs, of the value field in the table. One table could allow long values (for example, > 32 bits), while another table could be used to store integers. This customization enables better memory usage.rr}r(jX The maxValueLen parameter specifies the maximum length, in MAUs, of the value field in the table. One table could allow long values (for example, > 32 bits), while another table could be used to store integers. This customization enables better memory usage.jjubeubaubj{)r}r(jXj**Performance.** Multiple NameServer tables can improve the search time when retrieving a name/value pair.rjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujKj]r(j)r}r(jX**Performance.**j}r(j]j]j]j]j]ujjj]rjX Performance.rr}r(jUjjubajjubjXZ Multiple NameServer tables can improve the search time when retrieving a name/value pair.rr}r(jXZ Multiple NameServer tables can improve the search time when retrieving a name/value pair.jjubeubaubj{)r}r(jXx**Relax name uniqueness.** Names in a specific table must be unique, but the same name can be used in different tables. jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXw**Relax name uniqueness.** Names in a specific table must be unique, but the same name can be used in different tables.jjjjjjj}r(j]j]j]j]j]ujKj]r(j)r}r(jX**Relax name uniqueness.**j}r(j]j]j]j]j]ujjj]rjXRelax name uniqueness.rr}r(jUjjubajjubjX] Names in a specific table must be unique, but the same name can be used in different tables.rr}r(jX] Names in a specific table must be unique, but the same name can be used in different tables.jjubeubaubeubj)r}r(jXWhen you call NameServer_delete(), the memory for the name/values pairs is freed. You do not need to call NameServer_remove() on the entries before deleting a NameServer instance.rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXWhen you call NameServer_delete(), the memory for the name/values pairs is freed. You do not need to call NameServer_remove() on the entries before deleting a NameServer instance.rr}r (jjjjubaubeubj)r }r (jUjjjjjjj}r (j]j]j]j]r Uother-nameserver-apisraj]rj6aujKjhj]r(j)r}r(jXOther NameServer APIsrjj jjjjj}r(j]j]j]j]j]ujKjhj]rjXOther NameServer APIsrr}r(jjjjubaubj)r}r(jX`In addition to the functions mentioned above, the NameServer module provides the following APIs:rjj jjjjj}r(j]j]j]j]j]ujKjhj]rjX`In addition to the functions mentioned above, the NameServer module provides the following APIs:rr}r (jjjjubaubjt)r!}r"(jUjj jjjjwj}r#(jyX-j]j]j]j]j]ujKjhj]r$(j{)r%}r&(jXi**NameServer_get()** Retrieves the value portion of a local name/value pair from the specified processor.r'jj!jjjjj}r((j]j]j]j]j]ujNjhj]r)j)r*}r+(jj'jj%jjjjj}r,(j]j]j]j]j]ujKj]r-(j)r.}r/(jX**NameServer_get()**j}r0(j]j]j]j]j]ujj*j]r1jXNameServer_get()r2r3}r4(jUjj.ubajjubjXU Retrieves the value portion of a local name/value pair from the specified processor.r5r6}r7(jXU Retrieves the value portion of a local name/value pair from the specified processor.jj*ubeubaubj{)r8}r9(jXQ**NameServer_getLocal()** Retrieves the value portion of a local name/value pair.r:jj!jjjjj}r;(j]j]j]j]j]ujNjhj]r<j)r=}r>(jj:jj8jjjjj}r?(j]j]j]j]j]ujKj]r@(j)rA}rB(jX**NameServer_getLocal()**j}rC(j]j]j]j]j]ujj=j]rDjXNameServer_getLocal()rErF}rG(jUjjAubajjubjX8 Retrieves the value portion of a local name/value pair.rHrI}rJ(jX8 Retrieves the value portion of a local name/value pair.jj=ubeubaubj{)rK}rL(jXN**NameServer_remove()** Removes a name/value pair from the table given a name.rMjj!jjjjj}rN(j]j]j]j]j]ujNjhj]rOj)rP}rQ(jjMjjKjjjjj}rR(j]j]j]j]j]ujKj]rS(j)rT}rU(jX**NameServer_remove()**j}rV(j]j]j]j]j]ujjPj]rWjXNameServer_remove()rXrY}rZ(jUjjTubajjubjX7 Removes a name/value pair from the table given a name.r[r\}r](jX7 Removes a name/value pair from the table given a name.jjPubeubaubj{)r^}r_(jXZ**NameServer_removeEntry()** Removes an entry from the table given a pointer to an entry. jj!jjjjj}r`(j]j]j]j]j]ujNjhj]raj)rb}rc(jXY**NameServer_removeEntry()** Removes an entry from the table given a pointer to an entry.jj^jjjjj}rd(j]j]j]j]j]ujKj]re(j)rf}rg(jX**NameServer_removeEntry()**j}rh(j]j]j]j]j]ujjbj]rijXNameServer_removeEntry()rjrk}rl(jUjjfubajjubjX= Removes an entry from the table given a pointer to an entry.rmrn}ro(jX= Removes an entry from the table given a pointer to an entry.jjbubeubaubeubj)rp}rq(jXNameServer maintains the name/values table in local memory, not in shared memory. However the NameServer module can be used in a multiprocessor system. The module communicates with other processors via NameServer Remote drivers, which are implementations of the INameServerRemote interface. The communication to the other processors is dependent on the Remote drivers implementation. When a remote driver is created, it registers with NameServer via the NameServer_registerRemoteDriver() API.rrjj jjjjj}rs(j]j]j]j]j]ujKjhj]rtjXNameServer maintains the name/values table in local memory, not in shared memory. However the NameServer module can be used in a multiprocessor system. The module communicates with other processors via NameServer Remote drivers, which are implementations of the INameServerRemote interface. The communication to the other processors is dependent on the Remote drivers implementation. When a remote driver is created, it registers with NameServer via the NameServer_registerRemoteDriver() API.rurv}rw(jjrjjpubaubj)rx}ry(jXThe NameServer module uses the MultiProc module to identify different processors. Which remote processors to query and the order in which they are queried is determined by the procId array passed to the NameServer_get() function.rzjj jjjjj}r{(j]j]j]j]j]ujKjhj]r|jXThe NameServer module uses the MultiProc module to identify different processors. Which remote processors to query and the order in which they are queried is determined by the procId array passed to the NameServer_get() function.r}r~}r(jjzjjxubaubeubeubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rUoptimizing-ipc-applicationsraj]rhaujKfjhj]r(j)r}r(jXOptimizing IPC Applicationsrjjjjjjj}r(j]j]j]j]j]ujKfjhj]rjXOptimizing IPC Applicationsrr}r(jjjjubaubj7)r}r(jXShttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/Optimizing_IPC_Applicationsjjjj:XIsource/rtos/PDK_Platform_Software/IPC/Optimizing_IPC_Applications.rst.incrr}rbjj>j}r(j@jAj]j]j]j]j]ujKjhj]rjXShttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/Optimizing_IPC_Applicationsrr}r(jUjjubaubj)r}r(jUjjjjjjj}r(j]j]j]j]rU compiler-and-linker-optimizationraj]rhr?}r@(jj;jj9ubaubajj ubj )rA}rB(jUj}rC(j]j]j]j]j]ujj%j]rDj)rE}rF(jXLoggingrGjjAjjjjj}rH(j]j]j]j]j]ujK.j]rIjXLoggingrJrK}rL(jjGjjEubaubajj ubj )rM}rN(jUj}rO(j]j]j]j]j]ujj%j]rPj)rQ}rR(jX Code SizerSjjMjjjjj}rT(j]j]j]j]j]ujK.j]rUjX Code SizerVrW}rX(jjSjjQubaubajj ubj )rY}rZ(jUj}r[(j]j]j]j]j]ujj%j]r\j)r]}r^(jXRun-Time Performancer_jjYjjjjj}r`(j]j]j]j]j]ujK.j]rajXRun-Time Performancerbrc}rd(jj_jj]ubaubajj ubejj ubajj ubj )re}rf(jUj}rg(j]j]j]j]j]ujjj]rh(j )ri}rj(jUj}rk(j]j]j]j]j]ujjej]rl(j )rm}rn(jUj}ro(j]j]j]j]j]ujjij]rpj)rq}rr(jX+Instrumente d (BIOS.LibTy pe_Instrume nted)rsjjmjjjjj}rt(j]j]j]j]j]ujK1j]rujX+Instrumente d (BIOS.LibTy pe_Instrume nted)rvrw}rx(jjsjjqubaubajj ubj )ry}rz(jUj}r{(j]j]j]j]j]ujjij]r|j)r}}r~(jXFastrjjyjjjjj}r(j]j]j]j]j]ujK1j]rjXFastrr}r(jjjj}ubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjij]rj)r}r(jXOnrjjjjjjj}r(j]j]j]j]j]ujK1j]rjXOnrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjij]rj)r}r(jXGoodrjjjjjjj}r(j]j]j]j]j]ujK1j]rjXGoodrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjij]rj)r}r(jXGoodrjjjjjjj}r(j]j]j]j]j]ujK1j]rjXGoodrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjej]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX2Non-Instrum ented (BIOS.LibTy pe_NonInstr umented)rjjjjjjj}r(j]j]j]j]j]ujK7j]rjX2Non-Instrum ented (BIOS.LibTy pe_NonInstr umented)rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXFastrjjjjjjj}r(j]j]j]j]j]ujK7j]rjXFastrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXOffrjjjjjjj}r(j]j]j]j]j]ujK7j]rjXOffrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXBetterrjjjjjjj}r(j]j]j]j]j]ujK7j]rjXBetterrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXBetterrjjjjjjj}r(j]j]j]j]j]ujK7j]rjXBetterrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjej]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXCustom (BIOS.LibTy pe_Custom)rjjjjjjj}r(j]j]j]j]j]ujK=j]rjXCustom (BIOS.LibTy pe_Custom)rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXFast (slow first time)rjjjjjjj}r(j]j]j]j]j]ujK=j]rjXFast (slow first time)rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r }r (jX As configuredr jjjjjjj}r (j]j]j]j]j]ujK=j]r jX As configuredrr}r(jj jj ubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXBestrjjjjjjj}r(j]j]j]j]j]ujK=j]rjXBestrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r j)r!}r"(jXBestr#jjjjjjj}r$(j]j]j]j]j]ujK=j]r%jXBestr&r'}r((jj#jj!ubaubajj ubejj ubj )r)}r*(jUj}r+(j]j]j]j]j]ujjej]r,(j )r-}r.(jUj}r/(j]j]j]j]j]ujj)j]r0j)r1}r2(jXDebug (BIOS.LibTy pe_Debug)r3jj-jjjjj}r4(j]j]j]j]j]ujKAj]r5jXDebug (BIOS.LibTy pe_Debug)r6r7}r8(jj3jj1ubaubajj ubj )r9}r:(jUj}r;(j]j]j]j]j]ujj)j]r<j)r=}r>(jXSlowerr?jj9jjjjj}r@(j]j]j]j]j]ujKAj]rAjXSlowerrBrC}rD(jj?jj=ubaubajj ubj )rE}rF(jUj}rG(j]j]j]j]j]ujj)j]rHj)rI}rJ(jX As configuredrKjjEjjjjj}rL(j]j]j]j]j]ujKAj]rMjX As configuredrNrO}rP(jjKjjIubaubajj ubj )rQ}rR(jUj}rS(j]j]j]j]j]ujj)j]jj ubj )rT}rU(jUj}rV(j]j]j]j]j]ujj)j]jj ubejj ubejj ubejj ubaubjt)rW}rX(jUjjjjjjwj}rY(jyX-j]j]j]j]j]ujKFjhj]rZ(j{)r[}r\(jX**Instrumented.** (default) This option links with pre-built SYS/BIOS (and IPC) libraries that have instrumentation available. All Asserts and Diags settings are checked. Your configuration file can enable or disable various Diags and logging related settings. However, note that the checks to see if Diags are enabled before outputting a Log event are always performed, which has an impact on performance even if you use the ALWAYS_ON or ALWAYS_OFF setting. The resulting code size when using this option may be too large to fit on some targets, such as C28x and MSP430. This option is easy to use and debug and provides a fast build time.jjWjjjjj}r](j]j]j]j]j]ujNjhj]r^j)r_}r`(jX**Instrumented.** (default) This option links with pre-built SYS/BIOS (and IPC) libraries that have instrumentation available. All Asserts and Diags settings are checked. Your configuration file can enable or disable various Diags and logging related settings. However, note that the checks to see if Diags are enabled before outputting a Log event are always performed, which has an impact on performance even if you use the ALWAYS_ON or ALWAYS_OFF setting. The resulting code size when using this option may be too large to fit on some targets, such as C28x and MSP430. This option is easy to use and debug and provides a fast build time.jj[jjjjj}ra(j]j]j]j]j]ujKFj]rb(j)rc}rd(jX**Instrumented.**j}re(j]j]j]j]j]ujj_j]rfjX Instrumented.rgrh}ri(jUjjcubajjubjXo (default) This option links with pre-built SYS/BIOS (and IPC) libraries that have instrumentation available. All Asserts and Diags settings are checked. Your configuration file can enable or disable various Diags and logging related settings. However, note that the checks to see if Diags are enabled before outputting a Log event are always performed, which has an impact on performance even if you use the ALWAYS_ON or ALWAYS_OFF setting. The resulting code size when using this option may be too large to fit on some targets, such as C28x and MSP430. This option is easy to use and debug and provides a fast build time.rjrk}rl(jXo (default) This option links with pre-built SYS/BIOS (and IPC) libraries that have instrumentation available. All Asserts and Diags settings are checked. Your configuration file can enable or disable various Diags and logging related settings. However, note that the checks to see if Diags are enabled before outputting a Log event are always performed, which has an impact on performance even if you use the ALWAYS_ON or ALWAYS_OFF setting. The resulting code size when using this option may be too large to fit on some targets, such as C28x and MSP430. This option is easy to use and debug and provides a fast build time.jj_ubeubaubj{)rm}rn(jX**Non-Instrumented.** This option links with pre-built SYS/BIOS (and IPC) libraries that have instrumentation turned off. No Assert or Diag settings are checked, and logging information is not available at run-time. The checking for Asserts and Diags is compiled out of the libraries, so run-time performance and code size are optimized. Checking of Error_Blocks and handling errors in ways other than logging an event are still supported. This option is easy to use and provides a fast build time.jjWjjjjj}ro(j]j]j]j]j]ujNjhj]rpj)rq}rr(jX**Non-Instrumented.** This option links with pre-built SYS/BIOS (and IPC) libraries that have instrumentation turned off. No Assert or Diag settings are checked, and logging information is not available at run-time. The checking for Asserts and Diags is compiled out of the libraries, so run-time performance and code size are optimized. Checking of Error_Blocks and handling errors in ways other than logging an event are still supported. This option is easy to use and provides a fast build time.jjmjjjjj}rs(j]j]j]j]j]ujKPj]rt(j)ru}rv(jX**Non-Instrumented.**j}rw(j]j]j]j]j]ujjqj]rxjXNon-Instrumented.ryrz}r{(jUjjuubajjubjX This option links with pre-built SYS/BIOS (and IPC) libraries that have instrumentation turned off. No Assert or Diag settings are checked, and logging information is not available at run-time. The checking for Asserts and Diags is compiled out of the libraries, so run-time performance and code size are optimized. Checking of Error_Blocks and handling errors in ways other than logging an event are still supported. This option is easy to use and provides a fast build time.r|r}}r~(jX This option links with pre-built SYS/BIOS (and IPC) libraries that have instrumentation turned off. No Assert or Diag settings are checked, and logging information is not available at run-time. The checking for Asserts and Diags is compiled out of the libraries, so run-time performance and code size are optimized. Checking of Error_Blocks and handling errors in ways other than logging an event are still supported. This option is easy to use and provides a fast build time.jjqubeubaubj{)r}r(jX**Custom.** This option builds custom versions of the SYS/BIOS (and IPC) libraries that contain the modules and APIs that your application needs to access. If you have not used a particular module in your .cfg file or your C code (and it is not required internally by a SYS/BIOS module that is used), that module is not contained in the custom libraries compiled for your application. This option provides the best run-time performance and best code size given the needs of your application. Instrumentation is available to whatever extent your application configures it. The first time you build a project with the custom libType, the build will be longer. The custom libraries are stored in the "src" directory of your project. Subsequent builds may be faster; libraries do not need to be rebuilt unless you change one of the few configuration properties that affect the build settings, or you use an additional module that wasn't already used in the previous configuration.: jjWjjjjj}r(j]j]j]j]j]ujNjhj]r(j)r}r(jX;**Custom.** This option builds custom versions of the SYS/BIOS (and IPC) libraries that contain the modules and APIs that your application needs to access. If you have not used a particular module in your .cfg file or your C code (and it is not required internally by a SYS/BIOS module that is used), that module is not contained in the custom libraries compiled for your application. This option provides the best run-time performance and best code size given the needs of your application. Instrumentation is available to whatever extent your application configures it.jjjjjjj}r(j]j]j]j]j]ujKXj]r(j)r}r(jX **Custom.**j}r(j]j]j]j]j]ujjj]rjXCustom.rr}r(jUjjubajjubjX0 This option builds custom versions of the SYS/BIOS (and IPC) libraries that contain the modules and APIs that your application needs to access. If you have not used a particular module in your .cfg file or your C code (and it is not required internally by a SYS/BIOS module that is used), that module is not contained in the custom libraries compiled for your application. This option provides the best run-time performance and best code size given the needs of your application. Instrumentation is available to whatever extent your application configures it.rr}r(jX0 This option builds custom versions of the SYS/BIOS (and IPC) libraries that contain the modules and APIs that your application needs to access. If you have not used a particular module in your .cfg file or your C code (and it is not required internally by a SYS/BIOS module that is used), that module is not contained in the custom libraries compiled for your application. This option provides the best run-time performance and best code size given the needs of your application. Instrumentation is available to whatever extent your application configures it.jjubeubj)r}r(jXThe first time you build a project with the custom libType, the build will be longer. The custom libraries are stored in the "src" directory of your project. Subsequent builds may be faster; libraries do not need to be rebuilt unless you change one of the few configuration properties that affect the build settings, or you use an additional module that wasn't already used in the previous configuration.:rjjjjjjj}r(j]j]j]j]j]ujKbj]rjXThe first time you build a project with the custom libType, the build will be longer. The custom libraries are stored in the "src" directory of your project. Subsequent builds may be faster; libraries do not need to be rebuilt unless you change one of the few configuration properties that affect the build settings, or you use an additional module that wasn't already used in the previous configuration.:rr}r(jjjjubaubeubeubj)r}r(jX,If you disable SYS/BIOS Task or Swi scheduling, you must use the "custom" option in order to successfully link your application. The custom option uses program optimization that removes many initialized constants and small code fragments (often "glue" code) from the final executable image. Such classic optimizations as constant folding and function inlining are used, including across module boundaries. The custom build preserves enough debug information to make it still possible to step through the optimized code in CCS and locate global variables.:jjjjjjj}r(j]j]j]j]j]ujNjhj]r(j)r}r(jXIf you disable SYS/BIOS Task or Swi scheduling, you must use the "custom" option in order to successfully link your application.rjjjjjjj}r(j]j]j]j]j]ujKlj]rjXIf you disable SYS/BIOS Task or Swi scheduling, you must use the "custom" option in order to successfully link your application.rr}r(jjjjubaubj)r}r(jXThe custom option uses program optimization that removes many initialized constants and small code fragments (often "glue" code) from the final executable image. Such classic optimizations as constant folding and function inlining are used, including across module boundaries. The custom build preserves enough debug information to make it still possible to step through the optimized code in CCS and locate global variables.:rjjjjjjj}r(j]j]j]j]j]ujKoj]rjXThe custom option uses program optimization that removes many initialized constants and small code fragments (often "glue" code) from the final executable image. Such classic optimizations as constant folding and function inlining are used, including across module boundaries. The custom build preserves enough debug information to make it still possible to step through the optimized code in CCS and locate global variables.:rr}r(jjjjubaubeubjt)r}r(jUjjjjjjwj}r(jyX-j]j]j]j]j]ujKwjhj]rj{)r}r(jXl**Debug.** This option is not recommended; it is intended for internal use by Texas Instruments developers. jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXk**Debug.** This option is not recommended; it is intended for internal use by Texas Instruments developers.jjjjjjj}r(j]j]j]j]j]ujKwj]r(j)r}r(jX **Debug.**j}r(j]j]j]j]j]ujjj]rjXDebug.rr}r(jUjjubajjubjXa This option is not recommended; it is intended for internal use by Texas Instruments developers.rr}r(jXa This option is not recommended; it is intended for internal use by Texas Instruments developers.jjubeubaubaubj)r}r(jXMThe following example statements set the BIOS.libType configuration property:rjjjjjjj}r(j]j]j]j]j]ujKzjhj]rjXMThe following example statements set the BIOS.libType configuration property:rr}r(jjjjubaubj)r}r(jXPvar BIOS = xdc.useModule('ti.sysbios.BIOS'); BIOS.libType = BIOS.LibType_Custom;jjjjjjj}r(j@jAj]j]j]j]j]ujM jhj]rjXPvar BIOS = xdc.useModule('ti.sysbios.BIOS'); BIOS.libType = BIOS.LibType_Custom;rr}r(jUjjubaubj)r}r(jXIf you use the custom option for the BIOS.libType, you can also set the BIOS.customCCOpts property to customize the C compiler command-line options used when compiling the SYS/BIOS libraries. If you want to change this property, it is important to first examine and understand the default command-line options used to compile the SYS/BIOS libraries for your target. You can see the default in XGCONF or by placing the following statement in your configuration script and building the project:rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXIf you use the custom option for the BIOS.libType, you can also set the BIOS.customCCOpts property to customize the C compiler command-line options used when compiling the SYS/BIOS libraries. If you want to change this property, it is important to first examine and understand the default command-line options used to compile the SYS/BIOS libraries for your target. You can see the default in XGCONF or by placing the following statement in your configuration script and building the project:rr}r(jjjjubaubj)r}r(jX+print("customCCOpts =", BIOS.customCCOpts);jjjjjjj}r(j@jAj]j]j]j]j]ujM jhj]rjX+print("customCCOpts =", BIOS.customCCOpts);rr}r(jUjjubaubj)r}r(jXBe careful not to cause problems for the SYS/BIOS compilation when you modify this property. For example, the --program_level_compile option is required. (Some --define and --include_path options are used on the compiler command line but are not listed in the customCCOpts definition; these also cannot be removed.) For example, to create a debuggable custom library, you can remove the -o3 option from the BIOS.customCCOpts definition by specifying it with the following string for a C64x+ target:rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXBe careful not to cause problems for the SYS/BIOS compilation when you modify this property. For example, the --program_level_compile option is required. (Some --define and --include_path options are used on the compiler command line but are not listed in the customCCOpts definition; these also cannot be removed.) For example, to create a debuggable custom library, you can remove the -o3 option from the BIOS.customCCOpts definition by specifying it with the following string for a C64x+ target:rr}r(jjjjubaubj)r}r(jXBIOS.customCCOpts = "-mv64p --abi=eabi -q -mi10 -mo -pdr -pden -pds=238 -pds=880 -pds1110 --embed_inline_assembly --program_level_compile -g";jjjjjjj}r(j@jAj]j]j]j]j]ujM jhj]rjXBIOS.customCCOpts = "-mv64p --abi=eabi -q -mi10 -mo -pdr -pden -pds=238 -pds=880 -pds1110 --embed_inline_assembly --program_level_compile -g";rr}r(jUjjubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rUoptimizing-runtime-performanceraj]rhaujKjhj]r(j)r}r(jXOptimizing Runtime Performancerjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXOptimizing Runtime Performancerr}r(jjjjubaubj)r}r(jXkYou can use one or more of the following techniques to improve the runtime performance of IPC applications:rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXkYou can use one or more of the following techniques to improve the runtime performance of IPC applications:rr}r(jjjjubaubjt)r}r(jUjjjjjjwj}r (jyX-j]j]j]j]j]ujKjhj]r j{)r }r (jXAfter you have finished debugging an application, you can disable asserts and logging with the following configuration statements: jjjjjjj}r (j]j]j]j]j]ujNjhj]rj)r}r(jXAfter you have finished debugging an application, you can disable asserts and logging with the following configuration statements:rjj jjjjj}r(j]j]j]j]j]ujKj]rjXAfter you have finished debugging an application, you can disable asserts and logging with the following configuration statements:rr}r(jjjjubaubaubaubj)r}r(jXvar Diags = xdc.useModule("xdc.runtime.Diags"); var Defaults = xdc.useModule('xdc.runtime.Defaults'); Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF; Defaults.common$.logger = null;jjjjjjj}r(j@jAj]j]j]j]j]ujM jhj]rjXvar Diags = xdc.useModule("xdc.runtime.Diags"); var Defaults = xdc.useModule('xdc.runtime.Defaults'); Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF; Defaults.common$.logger = null;rr}r(jUjjubaubjt)r}r(jUjjjjjjwj}r (jyX-j]j]j]j]j]ujKjhj]r!j{)r"}r#(jX!If shared memory has the same address on all processors, you can use the following configuration statement to set the SharedRegion.translate property to false. See `SharedRegion Module `__ for more about SharedRegion configuration. jjjjjjj}r$(j]j]j]j]j]ujNjhj]r%j)r&}r'(jX If shared memory has the same address on all processors, you can use the following configuration statement to set the SharedRegion.translate property to false. See `SharedRegion Module `__ for more about SharedRegion configuration.jj"jjjjj}r((j]j]j]j]j]ujKj]r)(jXIf shared memory has the same address on all processors, you can use the following configuration statement to set the SharedRegion.translate property to false. See r*r+}r,(jXIf shared memory has the same address on all processors, you can use the following configuration statement to set the SharedRegion.translate property to false. See jj&ubj)r-}r.(jXQ`SharedRegion Module `__j}r/(UnameXSharedRegion ModulejX7index_Foundational_Components.html#shared-region-modulej]j]j]j]j]ujj&j]r0jXSharedRegion Moduler1r2}r3(jUjj-ubajjubjX+ for more about SharedRegion configuration.r4r5}r6(jX+ for more about SharedRegion configuration.jj&ubeubaubaubj)r7}r8(jXSharedRegion.translate = false;jjjjjjj}r9(j@jAj]j]j]j]j]ujM jhj]r:jXSharedRegion.translate = false;r;r<}r=(jUjj7ubaubjt)r>}r?(jUjjjjjjwj}r@(jyX-j]j]j]j]j]ujKjhj]rA(j{)rB}rC(jX Ensure that code, data, and shared data are all placed in cacheable memory. Refer to the SYS/BIOS documentation for information on how to configure a cache. See the *TI SYS/BIOS Real-time* *Operating System v6.x User's Guide* (`SPRUEX3 `__) for details.jj>jjjjj}rD(j]j]j]j]j]ujNjhj]rEj)rF}rG(jX Ensure that code, data, and shared data are all placed in cacheable memory. Refer to the SYS/BIOS documentation for information on how to configure a cache. See the *TI SYS/BIOS Real-time* *Operating System v6.x User's Guide* (`SPRUEX3 `__) for details.jjBjjjjj}rH(j]j]j]j]j]ujKj]rI(jXEnsure that code, data, and shared data are all placed in cacheable memory. Refer to the SYS/BIOS documentation for information on how to configure a cache. See the rJrK}rL(jXEnsure that code, data, and shared data are all placed in cacheable memory. Refer to the SYS/BIOS documentation for information on how to configure a cache. See the jjFubcdocutils.nodes emphasis rM)rN}rO(jX*TI SYS/BIOS Real-time*j}rP(j]j]j]j]j]ujjFj]rQjXTI SYS/BIOS Real-timerRrS}rT(jUjjNubajUemphasisrUubjX rV}rW(jX jjFubjM)rX}rY(jX$*Operating System v6.x User's Guide*j}rZ(j]j]j]j]j]ujjFj]r[jX"Operating System v6.x User's Guider\r]}r^(jUjjXubajjUubjX (r_r`}ra(jX (jjFubj)rb}rc(jX/`SPRUEX3 `__j}rd(UnameXSPRUEX3jX!http://www.ti.com/lit/pdf/SPRUEX3j]j]j]j]j]ujjFj]rejXSPRUEX3rfrg}rh(jUjjbubajjubjX) for details.rirj}rk(jX) for details.jjFubeubaubj{)rl}rm(jXYou can reduce contention between multiple processors and multiple threads by creating a new gate for use by a new IPC module instance. Leaving the params.gate property set to NULL causes the default system GateMP instance to be used for context protection. However, in some cases it may be optimal to create a new GateMP instance and supply it to the instance creation. See `GateMP Module `__ for more information. For example: jj>jjjjj}rn(j]j]j]j]j]ujNjhj]roj)rp}rq(jXYou can reduce contention between multiple processors and multiple threads by creating a new gate for use by a new IPC module instance. Leaving the params.gate property set to NULL causes the default system GateMP instance to be used for context protection. However, in some cases it may be optimal to create a new GateMP instance and supply it to the instance creation. See `GateMP Module `__ for more information. For example:jjljjjjj}rr(j]j]j]j]j]ujKj]rs(jXwYou can reduce contention between multiple processors and multiple threads by creating a new gate for use by a new IPC module instance. Leaving the params.gate property set to NULL causes the default system GateMP instance to be used for context protection. However, in some cases it may be optimal to create a new GateMP instance and supply it to the instance creation. See rtru}rv(jXwYou can reduce contention between multiple processors and multiple threads by creating a new gate for use by a new IPC module instance. Leaving the params.gate property set to NULL causes the default system GateMP instance to be used for context protection. However, in some cases it may be optimal to create a new GateMP instance and supply it to the instance creation. See jjpubj)rw}rx(jXD`GateMP Module `__j}ry(UnameX GateMP ModulejX0index_Foundational_Components.html#gatemp-modulej]j]j]j]j]ujjpj]rzjX GateMP Moduler{r|}r}(jUjjwubajjubjX# for more information. For example:r~r}r(jX# for more information. For example:jjpubeubaubeubj)r}r(jXGateMP_Params gateParams; GateMP_Handle gateHandle; HeapBufMP_Params heapParams; GateMP_Params_init(&gateParams); gateHandle = GateMP_create(&gateParams); HeapBufMP_Params_init(&heapParams); heapParams.gate = gateHandle;jjjjjjj}r(UlinenosrUlanguagerXcj@jAj]j]j]Uhighlight_argsr}j]j]ujKjhj]rjXGateMP_Params gateParams; GateMP_Handle gateHandle; HeapBufMP_Params heapParams; GateMP_Params_init(&gateParams); gateHandle = GateMP_create(&gateParams); HeapBufMP_Params_init(&heapParams); heapParams.gate = gateHandle;rr}r(jUjjubaubjt)r}r(jUjjjjjjwj}r(jyX-j]j]j]j]j]ujKjhj]rj{)r}r(jX If a unicache is shared between two cores in shared memory and you expect to share certain IPC instances (such as a GateMP or ListMP) solely between those two cores, you may be able to improve performance by creating a SharedRegion with cache disabled for use between those two cores only. Since region 0 needs to be accessible by all cores on a system, region 1 can be created with a cache line size of 0 and a cacheEnable configuration of FALSE. Any IPC instance created within a SharedRegion inherits the cache settings (the cacheEnabled flag and the cacheLineSize) from this region. Therefore, unnecessary cache operations can be avoided by creating an instance in region 1. The following configuration statements create a SharedRegion with the cache disabled (on OMAP4430): jjjjjjj}r(j]j]j]j]j]ujNjhj]r(j)r}r(jXIf a unicache is shared between two cores in shared memory and you expect to share certain IPC instances (such as a GateMP or ListMP) solely between those two cores, you may be able to improve performance by creating a SharedRegion with cache disabled for use between those two cores only. Since region 0 needs to be accessible by all cores on a system, region 1 can be created with a cache line size of 0 and a cacheEnable configuration of FALSE. Any IPC instance created within a SharedRegion inherits the cache settings (the cacheEnabled flag and the cacheLineSize) from this region. Therefore, unnecessary cache operations can be avoided by creating an instance in region 1.rjjjjjjj}r(j]j]j]j]j]ujKj]rjXIf a unicache is shared between two cores in shared memory and you expect to share certain IPC instances (such as a GateMP or ListMP) solely between those two cores, you may be able to improve performance by creating a SharedRegion with cache disabled for use between those two cores only. Since region 0 needs to be accessible by all cores on a system, region 1 can be created with a cache line size of 0 and a cacheEnable configuration of FALSE. Any IPC instance created within a SharedRegion inherits the cache settings (the cacheEnabled flag and the cacheLineSize) from this region. Therefore, unnecessary cache operations can be avoided by creating an instance in region 1.rr}r(jjjjubaubj)r}r(jXcThe following configuration statements create a SharedRegion with the cache disabled (on OMAP4430):rjjjjjjj}r(j]j]j]j]j]ujKj]rjXcThe following configuration statements create a SharedRegion with the cache disabled (on OMAP4430):rr}r(jjjjubaubeubaubj)r}r(jX SharedRegion.setEntryMeta(1, /* Create shared region 1 */ { base: 0x86000000, len: 0x10000, ownerProcId: 0, isValid: true, cacheEnabled: false, /* Cache operations unneeded */ cacheLineSize: 0, /* Cache padding unneeded */ name: "DDR2", }); The following C code creates a HeapBufMP instance in this SharedRegion::jjjjjjj}r(jjXcj@jAj]j]j]j}j]j]ujKjhj]rjX SharedRegion.setEntryMeta(1, /* Create shared region 1 */ { base: 0x86000000, len: 0x10000, ownerProcId: 0, isValid: true, cacheEnabled: false, /* Cache operations unneeded */ cacheLineSize: 0, /* Cache padding unneeded */ name: "DDR2", }); The following C code creates a HeapBufMP instance in this SharedRegion::rr}r(jUjjubaubj)r}r(jX HeapBufMP_Params heapParams; HeapBufMP_Handle heapHandle; HeapBufMP_Params_init(&heapParams); heapParams.regionId = 1; heapHandle = HeapBufMP_create(&heapParams); This heap can be used by either of the Cortex M3 cores on an OMAP4430, because they both share a unicache. Do not use this heap (or anything else belonging to a SharedRegion with caching disabled) from any other processor if the shared memory belonging to the SharedRegion is cacheable.jjjjjjj}r(jjXcj@jAj]j]j]j}j]j]ujKjhj]rjX HeapBufMP_Params heapParams; HeapBufMP_Handle heapHandle; HeapBufMP_Params_init(&heapParams); heapParams.regionId = 1; heapHandle = HeapBufMP_create(&heapParams); This heap can be used by either of the Cortex M3 cores on an OMAP4430, because they both share a unicache. Do not use this heap (or anything else belonging to a SharedRegion with caching disabled) from any other processor if the shared memory belonging to the SharedRegion is cacheable.rr}r(jUjjubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rU&optimizing-notify-and-messageq-latencyraj]rhaujMjhj]r(j)r}r(jX&Optimizing Notify and MessageQ Latencyrjjjjjjj}r(j]j]j]j]j]ujMjhj]rjX&Optimizing Notify and MessageQ Latencyrr}r(jjjjubaubj)r}r(jXBy default, IPC applications are configured to use the ti.sdo.ipc.notifyDrivers.NotifyDriverShm Notify driver and the ti.sdo.ipc.transports.TransportShm MessageQ transport. These modules are used by default because they offer backward compatibility with older IPC/SysLink releases. In addition, these modules may offer functionality not supported by their newer, lower-latency counterparts.rjjjjjjj}r(j]j]j]j]j]ujMjhj]rjXBy default, IPC applications are configured to use the ti.sdo.ipc.notifyDrivers.NotifyDriverShm Notify driver and the ti.sdo.ipc.transports.TransportShm MessageQ transport. These modules are used by default because they offer backward compatibility with older IPC/SysLink releases. In addition, these modules may offer functionality not supported by their newer, lower-latency counterparts.rr}r(jjjjubaubj)r}r(jXIf your application does not need functionality provided only by the default Notify drivers or MessageQ transport, you can reduce the latency by switching to alternative MessageQ transports and/or Notify drivers.rjjjjjjj}r(j]j]j]j]j]ujM jhj]rjXIf your application does not need functionality provided only by the default Notify drivers or MessageQ transport, you can reduce the latency by switching to alternative MessageQ transports and/or Notify drivers.rr}r(jjjjubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rU'choosing-and-configuring-notify-driversraj]rhaujMjhj]r(j)r}r(jX'Choosing and Configuring Notify Driversrjjjjjjj}r(j]j]j]j]j]ujMjhj]rjX'Choosing and Configuring Notify Driversrr}r(jjjjubaubj)r}r(jXTo switch to a different Notify driver, set the Notify.SetupProxy configuration to the family-specific Notify setup module. For example, the following statements configure an application on the DM6446 to use the NotifyDriverCirc driver for that device:rjjjjjjj}r(j]j]j]j]j]ujMjhj]rjXTo switch to a different Notify driver, set the Notify.SetupProxy configuration to the family-specific Notify setup module. For example, the following statements configure an application on the DM6446 to use the NotifyDriverCirc driver for that device:rr}r(jjjjubaubj)r}r(jXvar Notify = xdc.useModule('ti.sdo.ipc.Notify'); Notify.SetupProxy = xdc.useModule('ti.sdo.ipc.family.dm6446.NotifyCircSetup');jjjjjjj}r(j@jAj]j]j]j]j]ujM# jhj]rjXvar Notify = xdc.useModule('ti.sdo.ipc.Notify'); Notify.SetupProxy = xdc.useModule('ti.sdo.ipc.family.dm6446.NotifyCircSetup');rr}r(jUjjubaubjc)r}r(jUjjjjjjfj}r(j]j]j]j]j]ujMjhj]rji)r}r(jUjlKjjjjjjj}r(j]j]j]j]j]ujKjhj]ubaubj)r}r(jXIPC provides the following Notify drivers. Each has a corresponding setup module that should be used as the Notify.SetupProxy module.rjjjjjjj}r(j]j]j]j]j]ujM jhj]rjXIPC provides the following Notify drivers. Each has a corresponding setup module that should be used as the Notify.SetupProxy module.rr}r(jjjjubaubjy )r}r(jUjjjjjj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujjj]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthK/ujjj]jj ubj )r}r (jUj}r (j]j]j]j]j]UcolwidthKujjj]jj ubj )r }r (jUj}r (j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXModules and Descriptionrjjjjjjj}r(j]j]j]j]j]ujM$j]rjXModules and Descriptionrr }r!(jjjjubaubajj ubj )r"}r#(jUj}r$(j]j]j]j]j]ujjj]r%j)r&}r'(jX&Supports Disabling and Enabling Eventsr(jj"jjjjj}r)(j]j]j]j]j]ujM$j]r*jX&Supports Disabling and Enabling Eventsr+r,}r-(jj(jj&ubaubajj ubj )r.}r/(jUj}r0(j]j]j]j]j]ujjj]r1j)r2}r3(jXLatencyr4jj.jjjjj}r5(j]j]j]j]j]ujM$j]r6jXLatencyr7r8}r9(jj4jj2ubaubajj ubejj ubajj ubj )r:}r;(jUj}r<(j]j]j]j]j]ujjj]r=(j )r>}r?(jUj}r@(j]j]j]j]j]ujj:j]rA(j )rB}rC(jUj}rD(j]j]j]j]j]ujj>j]rE(j)rF}rG(jXOti.sdo.ipc.notifyDrivers.NotifyDriverShm ti.sdo.ipc.family..NotifySetuprHjjBjjjjj}rI(j]j]j]j]j]ujM'j]rJjXOti.sdo.ipc.notifyDrivers.NotifyDriverShm ti.sdo.ipc.family..NotifySetuprKrL}rM(jjHjjFubaubjc)rN}rO(jUj}rP(j]j]j]j]j]ujjBj]rQji)rR}rS(jUjlKjjNjjjjj}rT(j]j]j]j]j]ujKj]ubajjfubj)rU}rV(jXjThis shared-memory Notify driver offers room for a single pending notification in shared memory per event.rWjjBjjjjj}rX(j]j]j]j]j]ujM,j]rYjXjThis shared-memory Notify driver offers room for a single pending notification in shared memory per event.rZr[}r\(jjWjjUubaubejj ubj )r]}r^(jUj}r_(j]j]j]j]j]ujj>j]r`j)ra}rb(jXYesrcjj]jjjjj}rd(j]j]j]j]j]ujM'j]rejXYesrfrg}rh(jjcjjaubaubajj ubj )ri}rj(jUj}rk(j]j]j]j]j]ujj>j]rlj)rm}rn(jXDefaultrojjijjjjj}rp(j]j]j]j]j]ujM'j]rqjXDefaultrrrs}rt(jjojjmubaubajj ubejj ubj )ru}rv(jUj}rw(j]j]j]j]j]ujj:j]rx(j )ry}rz(jUj}r{(j]j]j]j]j]ujjuj]r|(j)r}}r~(jXTti.sdo.ipc.notifyDrivers.NotifyDriverCirc ti.sdo.ipc.family..NotifyCircSetuprjjyjjjjj}r(j]j]j]j]j]ujM1j]rjXTti.sdo.ipc.notifyDrivers.NotifyDriverCirc ti.sdo.ipc.family..NotifyCircSetuprr}r(jjjj}ubaubjc)r}r(jUj}r(j]j]j]j]j]ujjyj]rji)r}r(jUjlKjjjjjjj}r(j]j]j]j]j]ujKj]ubajjfubj)r}r(jXThis shared-memory Notify driver uses a circular buffer to store notifications. Unlike NotifyDriverShm, this driver stores all notifications in the same circular buffer (whose size is configurable).rjjyjjjjj}r(j]j]j]j]j]ujM6j]rjXThis shared-memory Notify driver uses a circular buffer to store notifications. Unlike NotifyDriverShm, this driver stores all notifications in the same circular buffer (whose size is configurable).rr}r(jjjjubaubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjuj]rj)r}r(jXNorjjjjjjj}r(j]j]j]j]j]ujM1j]rjXNorr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjuj]rj)r}r(jXBetter than NotifyDriverShmrjjjjjjj}r(j]j]j]j]j]ujM1j]rjXBetter than NotifyDriverShmrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujj:j]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]r(j)r}r(jXYti.sdo.ipc.family.ti8 1xx.\ **NotifyDriverM bx** ti.sdo.ipc.family.ti8 1xx.NotifyMbxSetupjjjjjjj}r(j]j]j]j]j]ujMBj]r(jXti.sdo.ipc.family.ti8 1xx.rr}r(jXti.sdo.ipc.family.ti8 1xx.\ jjubj)r}r(jX**NotifyDriverM bx**j}r(j]j]j]j]j]ujjj]rjXNotifyDriverM bxrr}r(jUjjubajjubjX) ti.sdo.ipc.family.ti8 1xx.NotifyMbxSetuprr}r(jX) ti.sdo.ipc.family.ti8 1xx.NotifyMbxSetupjjubeubjc)r}r(jUj}r(j]j]j]j]j]ujjj]rji)r}r(jUjlKjjjjjjj}r(j]j]j]j]j]ujKj]ubajjfubj)r}r(jXThis TI81xx-only Notify driver uses the hardware mailbox. This driver is not usable by other devices. Notifications are stored in hardware mailbox queues present on TI81xx devices.rjjjjjjj}r(j]j]j]j]j]ujMJj]rjXThis TI81xx-only Notify driver uses the hardware mailbox. This driver is not usable by other devices. Notifications are stored in hardware mailbox queues present on TI81xx devices.rr}r(jjjjubaubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXNorjjjjjjj}r(j]j]j]j]j]ujMBj]rjXNorr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX0Better than NotifyDriverCirc and NotifyDriverShmrjjjjjjj}r(j]j]j]j]j]ujMBj]rjX0Better than NotifyDriverCirc and NotifyDriverShmrr}r(jjjjubaubajj ubejj ubejj ubejj ubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rU,choosing-and-configuring-messageq-transportsraj]rhoaujMXjhj]r(j)r}r(jX,Choosing and Configuring MessageQ Transportsrjjjjjjj}r(j]j]j]j]j]ujMXjhj]rjX,Choosing and Configuring MessageQ Transportsrr}r(jjjjubaubj)r}r(jXSimilarly, to use an alternative MessageQ transport, configure the MessageQ.SetupTransportProxy property to use the transport's corresponding Transport Setup proxy. For example, to use the TransportShmNotify module, use the following configuration:rjjjjjjj}r(j]j]j]j]j]ujMZjhj]rjXSimilarly, to use an alternative MessageQ transport, configure the MessageQ.SetupTransportProxy property to use the transport's corresponding Transport Setup proxy. For example, to use the TransportShmNotify module, use the following configuration:rr}r(jjjjubaubj)r}r(jXvar MessageQ = xdc.module('ti.sdo.ipc.MessageQ'); MessageQ.SetupTransportProxy = xdc.module('ti.sdo.ipc.transports.TransportShmNotifySetup');jjjjjjj}r(j@jAj]j]j]j]j]ujMj jhj]rjXvar MessageQ = xdc.module('ti.sdo.ipc.MessageQ'); MessageQ.SetupTransportProxy = xdc.module('ti.sdo.ipc.transports.TransportShmNotifySetup');rr}r (jUjjubaubj)r }r (jXUnlike the Notify setup modules, Transport setup modules are generally not family-specific; most are located in the ti.sdo.ipc.transports package. IPC provides the following transports. Each has a corresponding setup module for use as the MessageQ.SetupTransportProxy module.r jjjjjjj}r (j]j]j]j]j]ujMejhj]rjXUnlike the Notify setup modules, Transport setup modules are generally not family-specific; most are located in the ti.sdo.ipc.transports package. IPC provides the following transports. Each has a corresponding setup module for use as the MessageQ.SetupTransportProxy module.rr}r(jj jj ubaubjy )r}r(jUjjjjjj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujjj]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthK#ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthK#ujjj]jj ubj )r }r!(jUj}r"(j]j]j]j]j]ujjj]r#j )r$}r%(jUj}r&(j]j]j]j]j]ujj j]r'(j )r(}r)(jUj}r*(j]j]j]j]j]ujj$j]r+j)r,}r-(jXModules and Descriptionr.jj(jjjjj}r/(j]j]j]j]j]ujMlj]r0jXModules and Descriptionr1r2}r3(jj.jj,ubaubajj ubj )r4}r5(jUj}r6(j]j]j]j]j]ujj$j]r7j)r8}r9(jXTransport Speedr:jj4jjjjj}r;(j]j]j]j]j]ujMlj]r<jXTransport Speedr=r>}r?(jj:jj8ubaubajj ubejj ubajj ubj )r@}rA(jUj}rB(j]j]j]j]j]ujjj]rC(j )rD}rE(jUj}rF(j]j]j]j]j]ujj@j]rG(j )rH}rI(jUj}rJ(j]j]j]j]j]ujjDj]rK(j)rL}rM(jXRti.sdo.ipc.transports.\ **Transpo rtShm** ti.sdo.ipc.transports.TransportSh mSetupjjHjjjjj}rN(j]j]j]j]j]ujMnj]rO(jXti.sdo.ipc.transports.rPrQ}rR(jXti.sdo.ipc.transports.\ jjLubj)rS}rT(jX**Transpo rtShm**j}rU(j]j]j]j]j]ujjLj]rVjX Transpo rtShmrWrX}rY(jUjjSubajjubjX) ti.sdo.ipc.transports.TransportSh mSetuprZr[}r\(jX) ti.sdo.ipc.transports.TransportSh mSetupjjLubeubjc)r]}r^(jUj}r_(j]j]j]j]j]ujjHj]r`ji)ra}rb(jUjlKjj]jjjjj}rc(j]j]j]j]j]ujKj]ubajjfubj)rd}re(jX%This shared-memory MessageQ transport uses ListMP to temporarily queue messages in shared memory before the messages are moved to the destination queue. This transport is typically slowest because of the overhead of queuing messages using a linked list. This is the default MessageQ transport.rfjjHjjjjj}rg(j]j]j]j]j]ujMuj]rhjX%This shared-memory MessageQ transport uses ListMP to temporarily queue messages in shared memory before the messages are moved to the destination queue. This transport is typically slowest because of the overhead of queuing messages using a linked list. This is the default MessageQ transport.rirj}rk(jjfjjdubaubejj ubj )rl}rm(jUj}rn(j]j]j]j]j]ujjDj]roj)rp}rq(jXSlowestrrjjljjjjj}rs(j]j]j]j]j]ujMnj]rtjXSlowestrurv}rw(jjrjjpubaubajj ubejj ubj )rx}ry(jUj}rz(j]j]j]j]j]ujj@j]r{(j )r|}r}(jUj}r~(j]j]j]j]j]ujjxj]r(j)r}r(jXZti.sdo.ipc.transports.\ **Transpo rtShmCirc** ti.sdo.ipc.transports.TransportSh mCircSetupjj|jjjjj}r(j]j]j]j]j]ujMj]r(jXti.sdo.ipc.transports.rr}r(jXti.sdo.ipc.transports.\ jjubj)r}r(jX**Transpo rtShmCirc**j}r(j]j]j]j]j]ujjj]rjXTranspo rtShmCircrr}r(jUjjubajjubjX- ti.sdo.ipc.transports.TransportSh mCircSetuprr}r(jX- ti.sdo.ipc.transports.TransportSh mCircSetupjjubeubjc)r}r(jUj}r(j]j]j]j]j]ujj|j]rji)r}r(jUjlKjjjjjjj}r(j]j]j]j]j]ujKj]ubajjfubj)r}r(jX=This shared-memory MessageQ transport uses a fixed-length circular buffer to temporarily queue messages in shared memory before the messages are moved to the destination queue. This transport is typically faster than TransportShm because of the efficiencies gained by using a circular buffer instead of a linked list.rjj|jjjjj}r(j]j]j]j]j]ujMj]rjX=This shared-memory MessageQ transport uses a fixed-length circular buffer to temporarily queue messages in shared memory before the messages are moved to the destination queue. This transport is typically faster than TransportShm because of the efficiencies gained by using a circular buffer instead of a linked list.rr}r(jjjjubaubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjxj]rj)r}r(jXMediumrjjjjjjj}r(j]j]j]j]j]ujMj]rjXMediumrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujj@j]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]r(j)r}r(jX^ti.sdo.ipc.transports.\ **Transpo rtShmNotify** ti.sdo.ipc.transports.TransportSh mNotifySetupjjjjjjj}r(j]j]j]j]j]ujMj]r(jXti.sdo.ipc.transports.rr}r(jXti.sdo.ipc.transports.\ jjubj)r}r(jX**Transpo rtShmNotify**j}r(j]j]j]j]j]ujjj]rjXTranspo rtShmNotifyrr}r(jUjjubajjubjX/ ti.sdo.ipc.transports.TransportSh mNotifySetuprr}r(jX/ ti.sdo.ipc.transports.TransportSh mNotifySetupjjubeubjc)r}r(jUj}r(j]j]j]j]j]ujjj]rji)r}r(jUjlKjjjjjjj}r(j]j]j]j]j]ujKj]ubajjfubj)r}r(jXThis shared-memory MessageQ transport does no buffering before the messages are moved to the destination queue. Because of the lack of buffering, this transport tends to offer lower MessageQ latency than either TransportShm or TransportShm. However, If messages aren't received quickly enough by the receiver, the sender may spin while waiting for the receiver to move the message to its local queue.rjjjjjjj}r(j]j]j]j]j]ujMj]rjXThis shared-memory MessageQ transport does no buffering before the messages are moved to the destination queue. Because of the lack of buffering, this transport tends to offer lower MessageQ latency than either TransportShm or TransportShm. However, If messages aren't received quickly enough by the receiver, the sender may spin while waiting for the receiver to move the message to its local queue.rr}r(jjjjubaubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX?Fastest, but depends on fast processing of messages by receiverrjjjjjjj}r(j]j]j]j]j]ujMj]rjX?Fastest, but depends on fast processing of messages by receiverrr}r(jjjjubaubajj ubejj ubejj ubejj ubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rUoptimizing-shared-memory-usageraj]rhaujMjhj]r(j)r}r(jXOptimizing Shared Memory Usagerjjjjjjj}r(j]j]j]j]j]ujMjhj]rjXOptimizing Shared Memory Usagerr}r(jjjjubaubj)r}r(jXnYou can use one or more of the following techniques to reduce the shared memory footprint of IPC applications:rjjjjjjj}r(j]j]j]j]j]ujMjhj]rjXnYou can use one or more of the following techniques to reduce the shared memory footprint of IPC applications:rr}r(jjjjubaubjt)r}r(jUjjjjjjwj}r(jyX-j]j]j]j]j]ujMjhj]rj{)r}r(jXIf some connections between processors are not needed, it is not necessary to attach to those cores. To selectively attach between cores, use pair-wise synchronization as described in `Ipc Module `__. Your C code must call Ipc_attach() for processors you want to connect to if you are using pair-wise synchronization. The following configuration statement causes the Ipc module to expect pair-wise synchronization. jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXIf some connections between processors are not needed, it is not necessary to attach to those cores. To selectively attach between cores, use pair-wise synchronization as described in `Ipc Module `__. Your C code must call Ipc_attach() for processors you want to connect to if you are using pair-wise synchronization. The following configuration statement causes the Ipc module to expect pair-wise synchronization.jjjjjjj}r(j]j]j]j]j]ujMj]r(jXIf some connections between processors are not needed, it is not necessary to attach to those cores. To selectively attach between cores, use pair-wise synchronization as described in rr}r(jXIf some connections between processors are not needed, it is not necessary to attach to those cores. To selectively attach between cores, use pair-wise synchronization as described in jjubj)r}r(jX>`Ipc Module `__j}r(UnameX Ipc ModulejX-index_Foundational_Components.html#ipc-modulej]j]j]j]j]ujjj]r jX Ipc Moduler r }r (jUjjubajjubjX. Your C code must call Ipc_attach() for processors you want to connect to if you are using pair-wise synchronization. The following configuration statement causes the Ipc module to expect pair-wise synchronization.r r}r(jX. Your C code must call Ipc_attach() for processors you want to connect to if you are using pair-wise synchronization. The following configuration statement causes the Ipc module to expect pair-wise synchronization.jjubeubaubaubj)r}r(jX!Ipc.procSync = Ipc.ProcSync_PAIR;jjjjjjj}r(j@jAj]j]j]j]j]ujM jhj]rjX!Ipc.procSync = Ipc.ProcSync_PAIR;rr}r(jUjjubaubjc)r}r(jUjjjjjjfj}r(j]j]j]j]j]ujMjhj]rji)r}r(jUjlKjjjjjjj}r(j]j]j]j]j]ujKjhj]ubaubj)r}r(jXnAt run-time, only call Ipc_attach() to a remote processor if one or more of the following conditions is true::jjjjjjj}r (j]j]j]j]j]ujMjhj]r!jXmAt run-time, only call Ipc_attach() to a remote processor if one or more of the following conditions is true:r"r#}r$(jXmAt run-time, only call Ipc_attach() to a remote processor if one or more of the following conditions is true:jjubaubj)r%}r&(jX- The remote processor is the owner of region 0. - It is necessary to send Notifications between this processor and the remote processor. - It is necessary to send MessageQ messages between this processor and the remote processor. - It is necessary for either the local or remote processor to open a module instance using *MODULE*\ \_open() that has been created on the other processor.jjjjjjj}r'(j@jAj]j]j]j]j]ujM jhj]r(jX- The remote processor is the owner of region 0. - It is necessary to send Notifications between this processor and the remote processor. - It is necessary to send MessageQ messages between this processor and the remote processor. - It is necessary for either the local or remote processor to open a module instance using *MODULE*\ \_open() that has been created on the other processor.r)r*}r+(jUjj%ubaubjt)r,}r-(jUjjjjjjwj}r.(jyX-j]j]j]j]j]ujMjhj]r/j{)r0}r1(jXConfigure the Ipc.setEntryMeta property to disable components of IPC that are not required. For example, if an application uses Notify but not MessageQ, disabling MessageQ avoids the creation of MessageQ transports during Ipc_attach(). jj,jjjjj}r2(j]j]j]j]j]ujNjhj]r3j)r4}r5(jXConfigure the Ipc.setEntryMeta property to disable components of IPC that are not required. For example, if an application uses Notify but not MessageQ, disabling MessageQ avoids the creation of MessageQ transports during Ipc_attach().r6jj0jjjjj}r7(j]j]j]j]j]ujMj]r8jXConfigure the Ipc.setEntryMeta property to disable components of IPC that are not required. For example, if an application uses Notify but not MessageQ, disabling MessageQ avoids the creation of MessageQ transports during Ipc_attach().r9r:}r;(jj6jj4ubaubaubaubj)r<}r=(jX/* To avoid wasting shared mem for MessageQ transports */ for (var i = 0; i < MultiProc.numProcessors; i++) { Ipc.setEntryMeta({ remoteProcId: 1, setupMessageQ: false, }); }jjjjjjj}r>(jjXcj@jAj]j]j]j}j]j]ujMjhj]r?jX/* To avoid wasting shared mem for MessageQ transports */ for (var i = 0; i < MultiProc.numProcessors; i++) { Ipc.setEntryMeta({ remoteProcId: 1, setupMessageQ: false, }); }r@rA}rB(jUjj<ubaubjt)rC}rD(jUjjjjjjwj}rE(jyX-j]j]j]j]j]ujMjhj]rFj{)rG}rH(jXConfigure Notify.numEvents to a lower number. The default value of 32 is often significantly more than the total number of Notify events required on a system. See `Notify Module `__ for more information. For example, a simple MessageQ application may simply use two events (one for NameServer and one for the MessageQ transport). In this case, we can optimize memory use with the following configuration: jjCjjjjj}rI(j]j]j]j]j]ujNjhj]rJ(j)rK}rL(jXConfigure Notify.numEvents to a lower number. The default value of 32 is often significantly more than the total number of Notify events required on a system. See `Notify Module `__ for more information.jjGjjjjj}rM(j]j]j]j]j]ujMj]rN(jXConfigure Notify.numEvents to a lower number. The default value of 32 is often significantly more than the total number of Notify events required on a system. See rOrP}rQ(jXConfigure Notify.numEvents to a lower number. The default value of 32 is often significantly more than the total number of Notify events required on a system. See jjKubj)rR}rS(jXD`Notify Module `__j}rT(UnameX Notify ModulejX0index_Foundational_Components.html#notify-modulej]j]j]j]j]ujjKj]rUjX Notify ModulerVrW}rX(jUjjRubajjubjX for more information.rYrZ}r[(jX for more information.jjKubeubj)r\}r](jXFor example, a simple MessageQ application may simply use two events (one for NameServer and one for the MessageQ transport). In this case, we can optimize memory use with the following configuration:r^jjGjjjjj}r_(j]j]j]j]j]ujMj]r`jXFor example, a simple MessageQ application may simply use two events (one for NameServer and one for the MessageQ transport). In this case, we can optimize memory use with the following configuration:rarb}rc(jj^jj\ubaubeubaubj)rd}re(jXkvar Notify = xdc.useModule('ti.sdo.ipc.Notify'); /* Reduce the total number of supported events from 32 to 2 */ Notify.numEvents = 2; var NameServerRemoteNotify = xdc.useModule('ti.sdo.ipc.NameServerRemoteNotify'); NameServerRemoteNotify.notifyEventId = 1; var TransportShm = xdc.useModule('ti.sdo.ipc.transports.TransportShm'); TransportShm.notifyEventId = 0;jjjjjjj}rf(jjX javascriptj@jAj]j]j]j}j]j]ujMjhj]rgjXkvar Notify = xdc.useModule('ti.sdo.ipc.Notify'); /* Reduce the total number of supported events from 32 to 2 */ Notify.numEvents = 2; var NameServerRemoteNotify = xdc.useModule('ti.sdo.ipc.NameServerRemoteNotify'); NameServerRemoteNotify.notifyEventId = 1; var TransportShm = xdc.useModule('ti.sdo.ipc.transports.TransportShm'); TransportShm.notifyEventId = 0;rhri}rj(jUjjdubaubjt)rk}rl(jUjjjjjjwj}rm(jyX-j]j]j]j]j]ujMjhj]rnj{)ro}rp(jXReduce the cacheLineSize property of a SharedRegion to reflect the actual size of the cache line. IPC uses the cacheLineSize setting to pad data structures in shared memory. Padding is required so that cache write-back and invalidate operations on data in shared memory do not affect the cache status of adjacent data. The larger the cacheLineSize setting, the more shared memory is used for the sole purpose of padding. Therefore, the cacheLineSize setting should optimally be set to the actual size of the cache line. The default cacheLineSize for SharedRegion is 128. Using the correct size has both performance and size benefits. The following example (for C6472) sets the cacheLineSize property to 64 because the shared L2 memory has this cache line size. jjkjjjjj}rq(j]j]j]j]j]ujNjhj]rr(j)rs}rt(jXyReduce the cacheLineSize property of a SharedRegion to reflect the actual size of the cache line. IPC uses the cacheLineSize setting to pad data structures in shared memory. Padding is required so that cache write-back and invalidate operations on data in shared memory do not affect the cache status of adjacent data. The larger the cacheLineSize setting, the more shared memory is used for the sole purpose of padding. Therefore, the cacheLineSize setting should optimally be set to the actual size of the cache line. The default cacheLineSize for SharedRegion is 128. Using the correct size has both performance and size benefits.rujjojjjjj}rv(j]j]j]j]j]ujMj]rwjXyReduce the cacheLineSize property of a SharedRegion to reflect the actual size of the cache line. IPC uses the cacheLineSize setting to pad data structures in shared memory. Padding is required so that cache write-back and invalidate operations on data in shared memory do not affect the cache status of adjacent data. The larger the cacheLineSize setting, the more shared memory is used for the sole purpose of padding. Therefore, the cacheLineSize setting should optimally be set to the actual size of the cache line. The default cacheLineSize for SharedRegion is 128. Using the correct size has both performance and size benefits.rxry}rz(jjujjsubaubj)r{}r|(jX~The following example (for C6472) sets the cacheLineSize property to 64 because the shared L2 memory has this cache line size.r}jjojjjjj}r~(j]j]j]j]j]ujMj]rjX~The following example (for C6472) sets the cacheLineSize property to 64 because the shared L2 memory has this cache line size.rr}r(jj}jj{ubaubeubaubj)r}r(jXSharedRegion.setEntryMeta(0, { base: SHAREDMEM, len: SHAREDMEMSIZE, ownerProcId: 0, isValid: true, cacheLineSize: 64, /* SL2 cache line size = 64 */ name: "SL2_RAM", });jjjjjjj}r(jjXcj@jAj]j]j]j}j]j]ujMjhj]rjXSharedRegion.setEntryMeta(0, { base: SHAREDMEM, len: SHAREDMEMSIZE, ownerProcId: 0, isValid: true, cacheLineSize: 64, /* SL2 cache line size = 64 */ name: "SL2_RAM", });rr}r(jUjjubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rUoptimizing-local-memory-usageraj]rhaujM jhj]r(j)r}r(jXOptimizing Local Memory Usagerjjjjjjj}r(j]j]j]j]j]ujM jhj]rjXOptimizing Local Memory Usagerr}r(jjjjubaubj)r}r(jXIf the Custom1 and Custom2 GateMP proxies will never be used, make sure they are both plugged with the ti.sdo.ipc.gates.GateMPSupportNull GateMP delegate. By default, GateMP plugs the Custom1 proxy with the GatePeterson delegate. A considerable amount of local memory is reserved for use by GatePeterson. You can plug the Custom1 proxy with the GateMPSupportNull delegate by adding the following configuration statements to your application:rjjjjjjj}r(j]j]j]j]j]ujM jhj]rjXIf the Custom1 and Custom2 GateMP proxies will never be used, make sure they are both plugged with the ti.sdo.ipc.gates.GateMPSupportNull GateMP delegate. By default, GateMP plugs the Custom1 proxy with the GatePeterson delegate. A considerable amount of local memory is reserved for use by GatePeterson. You can plug the Custom1 proxy with the GateMPSupportNull delegate by adding the following configuration statements to your application:rr}r(jjjjubaubj)r}r(jXvar GateMP = xdc.useModule('ti.sdo.ipc.GateMP'); GateMP.RemoteCustom1Proxy = xdc.useModule('ti.sdo.ipc.gates.GateMPSupportNull');jjjjjjj}r(jjX javascriptj@jAj]j]j]j}j]j]ujMjhj]rjXvar GateMP = xdc.useModule('ti.sdo.ipc.GateMP'); GateMP.RemoteCustom1Proxy = xdc.useModule('ti.sdo.ipc.gates.GateMPSupportNull');rr}r(jUjjubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rUoptimizing-code-sizeraj]rj<aujMjhj]r(j)r}r(jXOptimizing Code Sizerjjjjjjj}r(j]j]j]j]j]ujMjhj]rjXOptimizing Code Sizerr}r(jjjjubaubj)r}r(jXvThis section provides tips and suggestions for minimizing the code size of a SYS/BIOS-based application that uses IPC.rjjjjjjj}r(j]j]j]j]j]ujMjhj]rjXvThis section provides tips and suggestions for minimizing the code size of a SYS/BIOS-based application that uses IPC.rr}r(jjjjubaubjt)r}r(jUjjjjjjwj}r(jyX-j]j]j]j]j]ujM jhj]rj{)r}r(jXFor a number of ways to configure SYS/BIOS that reduce code size by using custom built SYS/BIOS libraries and by disabling various features, see Section E.3 of the *TI SYS/BIOS Real-time Operating* *System v6.x User's Guide* (`SPRUEX3 `__). In particular, after you have debugged your code, disabling Asserts as follows helps reduce the size of your code. jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXFor a number of ways to configure SYS/BIOS that reduce code size by using custom built SYS/BIOS libraries and by disabling various features, see Section E.3 of the *TI SYS/BIOS Real-time Operating* *System v6.x User's Guide* (`SPRUEX3 `__). In particular, after you have debugged your code, disabling Asserts as follows helps reduce the size of your code.jjjjjjj}r(j]j]j]j]j]ujM j]r(jXFor a number of ways to configure SYS/BIOS that reduce code size by using custom built SYS/BIOS libraries and by disabling various features, see Section E.3 of the rr}r(jXFor a number of ways to configure SYS/BIOS that reduce code size by using custom built SYS/BIOS libraries and by disabling various features, see Section E.3 of the jjubjM)r}r(jX!*TI SYS/BIOS Real-time Operating*j}r(j]j]j]j]j]ujjj]rjXTI SYS/BIOS Real-time Operatingrr}r(jUjjubajjUubjX r}r(jX jjubjM)r}r(jX*System v6.x User's Guide*j}r(j]j]j]j]j]ujjj]rjXSystem v6.x User's Guiderr}r(jUjjubajjUubjX (rr}r(jX (jjubj)r}r(jX/`SPRUEX3 `__j}r(UnameXSPRUEX3jX!http://www.ti.com/lit/pdf/SPRUEX3j]j]j]j]j]ujjj]rjXSPRUEX3rr}r(jUjjubajjubjXu). In particular, after you have debugged your code, disabling Asserts as follows helps reduce the size of your code.rr}r(jXu). In particular, after you have debugged your code, disabling Asserts as follows helps reduce the size of your code.jjubeubaubaubj )r}r(jUjjjjjj# j}r(j]j]j]j]j]ujNjhj]rj& )r}r(jX:: var Defaults = xdc.useModule('xdc.runtime.Defaults'); var Diags = xdc.useModule('xdc.runtimg.Diags'); Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF; jjjjjj) j}r(j]j]j]j]j]ujM+j]r(j, )r}r(jX::rjjjjjj0 j}r(j]j]j]j]j]ujM+j]rjX::rr}r(jjjjubaubj6 )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXvar Defaults = xdc.useModule('xdc.runtime.Defaults'); var Diags = xdc.useModule('xdc.runtimg.Diags'); Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;rjjjjjjj}r(j]j]j]j]j]ujM)j]rjXvar Defaults = xdc.useModule('xdc.runtime.Defaults'); var Diags = xdc.useModule('xdc.runtimg.Diags'); Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;rr}r(jjjjubaubajjQ ubeubaubjt)r}r(jUjjjjjjwj}r (jyX-j]j]j]j]j]ujM-jhj]r (j{)r }r (jXThe NotifyDriverCirc notification driver and the TransportShmNotify or TransportShmCirc MessageQ transports described in **Optimizing IPC Applications** use less code space than the default Notify driver and MessageQ transport.jjjjjjj}r (j]j]j]j]j]ujNjhj]rj)r}r(jXThe NotifyDriverCirc notification driver and the TransportShmNotify or TransportShmCirc MessageQ transports described in **Optimizing IPC Applications** use less code space than the default Notify driver and MessageQ transport.jj jjjjj}r(j]j]j]j]j]ujM-j]r(jXyThe NotifyDriverCirc notification driver and the TransportShmNotify or TransportShmCirc MessageQ transports described in rr}r(jXyThe NotifyDriverCirc notification driver and the TransportShmNotify or TransportShmCirc MessageQ transports described in jjubj)r}r(jX**Optimizing IPC Applications**j}r(j]j]j]j]j]ujjj]rjXOptimizing IPC Applicationsrr}r(jUjjubajjubjXK use less code space than the default Notify driver and MessageQ transport.rr}r(jXK use less code space than the default Notify driver and MessageQ transport.jjubeubaubj{)r }r!(jXYou can reduce code size by not using the HeapBufMP Heap implementation. Since IPC uses the HeapMemMP implementation internally, using HeapMemMP in your application does not increase the code size. However, you should be aware that, depending on how your application uses heaps, HeapMemMP may lead to problems with heap fragmentation. See `Heap*MP Modules `__ for more about Heap implementations. jjjjjjj}r"(j]j]j]j]j]ujNjhj]r#j)r$}r%(jXYou can reduce code size by not using the HeapBufMP Heap implementation. Since IPC uses the HeapMemMP implementation internally, using HeapMemMP in your application does not increase the code size. However, you should be aware that, depending on how your application uses heaps, HeapMemMP may lead to problems with heap fragmentation. See `Heap*MP Modules `__ for more about Heap implementations.jj jjjjj}r&(j]j]j]j]j]ujM1j]r'(jXSYou can reduce code size by not using the HeapBufMP Heap implementation. Since IPC uses the HeapMemMP implementation internally, using HeapMemMP in your application does not increase the code size. However, you should be aware that, depending on how your application uses heaps, HeapMemMP may lead to problems with heap fragmentation. See r(r)}r*(jXSYou can reduce code size by not using the HeapBufMP Heap implementation. Since IPC uses the HeapMemMP implementation internally, using HeapMemMP in your application does not increase the code size. However, you should be aware that, depending on how your application uses heaps, HeapMemMP may lead to problems with heap fragmentation. See jj$ubj)r+}r,(jXF`Heap*MP Modules `__j}r-(UnameXHeap*MP ModulesjX0index_Foundational_Components.html#heapmp-modulej]j]j]j]j]ujj$j]r.jXHeap*MP Modulesr/r0}r1(jUjj+ubajjubjX% for more about Heap implementations.r2r3}r4(jX% for more about Heap implementations.jj$ubeubaubeubjc)r5}r6(jUjjjjjjfj}r7(j]j]j]j]j]ujM:jhj]r8ji)r9}r:(jUjlKjj5jjjjj}r;(j]j]j]j]j]ujKjhj]ubaubeubeubj)r<}r=(jUjjjjjjj}r>(j]j]j]j]r?Urebuilding-ipcr@aj]rAhaujKjjhj]rB(j)rC}rD(jXRebuilding IPCrEjj<jjjjj}rF(j]j]j]j]j]ujKjjhj]rGjXRebuilding IPCrHrI}rJ(jjEjjCubaubj7)rK}rL(jXFhttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/Rebuilding_IPCjj<jj:X<source/rtos/PDK_Platform_Software/IPC/Rebuilding_IPC.rst.incrMrN}rObjj>j}rP(j@jAj]j]j]j]j]ujKjhj]rQjXFhttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/Rebuilding_IPCrRrS}rT(jUjjKubaubj)rU}rV(jX7This page describes how to rebuild the IPC source code.rWjj<jjNjjj}rX(j]j]j]j]j]ujKjhj]rYjX7This page describes how to rebuild the IPC source code.rZr[}r\(jjWjjUubaubj)r]}r^(jX\The IPC product includes source files and build scripts that allow you to modify the IPC sources and rebuild its libraries. You can do this in order to modify, update, or add functionality. If you edit the IPC source code and/or corresponding build scripts, you must also rebuild IPC in order to create new libraries containing these modifications.r_jj<jjNjjj}r`(j]j]j]j]j]ujKjhj]rajX\The IPC product includes source files and build scripts that allow you to modify the IPC sources and rebuild its libraries. You can do this in order to modify, update, or add functionality. If you edit the IPC source code and/or corresponding build scripts, you must also rebuild IPC in order to create new libraries containing these modifications.rbrc}rd(jj_jj]ubaubj)re}rf(jXNote that you can cause the BIOS-side IPC (and BIOS) libraries to be rebuilt as part of the application build - this is called a 'Custom Build'. The custom-built libraries will be stored with other output from executing your config script, and will contain only modules and APIs that your application needs to access. You can cause such a Custom Build to occur using the BIOS.libType config param as follows.rgjj<jjNjjj}rh(j]j]j]j]j]ujKjhj]rijXNote that you can cause the BIOS-side IPC (and BIOS) libraries to be rebuilt as part of the application build - this is called a 'Custom Build'. The custom-built libraries will be stored with other output from executing your config script, and will contain only modules and APIs that your application needs to access. You can cause such a Custom Build to occur using the BIOS.libType config param as follows.rjrk}rl(jjgjjeubaubj)rm}rn(jXPvar BIOS = xdc.useModule('ti.sysbios.BIOS'); BIOS.libType = BIOS.LibType_Custom;jj<jjNjjj}ro(j@jAj]j]j]j]rp(UcoderqXcej]ujK jhj]rr(cdocutils.nodes inline rs)rt}ru(jXvarj}rv(j]j]rwUnamerxaj]j]j]ujjmj]ryjXvarrzr{}r|(jUjjtubajUinliner}ubjX r~}r(jX jjmubjs)r}r(jXBIOSj}r(j]j]rUnameraj]j]j]ujjmj]rjXBIOSrr}r(jUjjubajj}ubjX r}r(jX jjmubjs)r}r(jX=j}r(j]j]rUoperatorraj]j]j]ujjmj]rjX=r}r(jUjjubajj}ubjX r}r(jX jjmubjs)r}r(jXxdcj}r(j]j]rUnameraj]j]j]ujjmj]rjXxdcrr}r(jUjjubajj}ubjs)r}r(jX.j}r(j]j]rU punctuationraj]j]j]ujjmj]rjX.r}r(jUjjubajj}ubjs)r}r(jX useModulej}r(j]j]rUnameraj]j]j]ujjmj]rjX useModulerr}r(jUjjubajj}ubjs)r}r(jX(j}r(j]j]rU punctuationraj]j]j]ujjmj]rjX(r}r(jUjjubajj}ubjs)r}r(jX'j}r(j]j]rUerrorraj]j]j]ujjmj]rjX'r}r(jUjjubajj}ubjs)r}r(jXtij}r(j]j]rUnameraj]j]j]ujjmj]rjXtirr}r(jUjjubajj}ubjs)r}r(jX.j}r(j]j]rU punctuationraj]j]j]ujjmj]rjX.r}r(jUjjubajj}ubjs)r}r(jXsysbiosj}r(j]j]rUnameraj]j]j]ujjmj]rjXsysbiosrr}r(jUjjubajj}ubjs)r}r(jX.j}r(j]j]rU punctuationraj]j]j]ujjmj]rjX.r}r(jUjjubajj}ubjs)r}r(jXBIOSj}r(j]j]rUnameraj]j]j]ujjmj]rjXBIOSrr}r(jUjjubajj}ubjs)r}r(jX'j}r(j]j]rUerrorraj]j]j]ujjmj]rjX'r}r(jUjjubajj}ubjs)r}r(jX);j}r(j]j]rU punctuationraj]j]j]ujjmj]rjX);rr}r(jUjjubajj}ubjX r}r(jX jjmubjs)r}r(jXBIOSj}r(j]j]rUnameraj]j]j]ujjmj]rjXBIOSrr}r(jUjjubajj}ubjs)r}r(jX.j}r(j]j]r U punctuationr aj]j]j]ujjmj]r jX.r }r (jUjjubajj}ubjs)r}r(jXlibTypej}r(j]j]rUnameraj]j]j]ujjmj]rjXlibTyperr}r(jUjjubajj}ubjX r}r(jX jjmubjs)r}r(jX=j}r(j]j]rUoperatorraj]j]j]ujjmj]rjX=r}r (jUjjubajj}ubjX r!}r"(jX jjmubjs)r#}r$(jXBIOSj}r%(j]j]r&Unamer'aj]j]j]ujjmj]r(jXBIOSr)r*}r+(jUjj#ubajj}ubjs)r,}r-(jX.j}r.(j]j]r/U punctuationr0aj]j]j]ujjmj]r1jX.r2}r3(jUjj,ubajj}ubjs)r4}r5(jXLibType_Customj}r6(j]j]r7Unamer8aj]j]j]ujjmj]r9jXLibType_Customr:r;}r<(jUjj4ubajj}ubjs)r=}r>(jX;j}r?(j]j]r@U punctuationrAaj]j]j]ujjmj]rBjX;rC}rD(jUjj=ubajj}ubeubj)rE}rF(jXThis page provides details about rebuilding the IPC source code. We strongly recommend that you copy the IPC installation to a directory with a different name and rebuild that copy, rather than rebuilding the original installation.rGjj<jjNjjj}rH(j]j]j]j]j]ujNjhj]rIj)rJ}rK(jjGjjEjjNjjj}rL(j]j]j]j]j]ujKj]rMjXThis page provides details about rebuilding the IPC source code. We strongly recommend that you copy the IPC installation to a directory with a different name and rebuild that copy, rather than rebuilding the original installation.rNrO}rP(jjGjjJubaubaubj)rQ}rR(jUjj<jjNjjj}rS(j]j]j]j]rTUbuild-procedurerUaj]rVhaujKjhj]rW(j)rX}rY(jXBuild ProcedurerZjjQjjNjjj}r[(j]j]j]j]j]ujKjhj]r\jXBuild Procedurer]r^}r_(jjZjjXubaubj)r`}ra(jXThe IPC package now comes bundled with Processor SDK RTOS and can be rebuilt using the top-level makefile located in the Processor SDK RTOS folder. The following commands will build the BIOS-side IPC package.rbjjQjjNjjj}rc(j]j]j]j]j]ujKjhj]rdjXThe IPC package now comes bundled with Processor SDK RTOS and can be rebuilt using the top-level makefile located in the Processor SDK RTOS folder. The following commands will build the BIOS-side IPC package.rerf}rg(jjbjj`ubaubj)rh}ri(jX Windows ::jjQjjNjjj}rj(j]j]j]j]j]ujKjhj]rkjXWindowsrlrm}rn(jXWindowsjjhubaubj)ro}rp(jX:cd (Processor SDK RTOS folder) setupenv.bat gmake ipc_biosjjQjjNjjj}rq(j@jAj]j]j]j]j]ujMdjhj]rrjX:cd (Processor SDK RTOS folder) setupenv.bat gmake ipc_biosrsrt}ru(jUjjoubaubj)rv}rw(jXLinux ::jjQjjNjjj}rx(j]j]j]j]j]ujKjhj]ryjXLinuxrzr{}r|(jXLinuxjjvubaubj)r}}r~(jXAcd (Processor SDK RTOS folder) source ./setupenv.sh make ipc_biosjjQjjNjjj}r(j@jAj]j]j]j]j]ujMkjhj]rjXAcd (Processor SDK RTOS folder) source ./setupenv.sh make ipc_biosrr}r(jUjj}ubaubj)r}r(jXAThe IPC package can also be cleaned using the following commands.rjjQjjNjjj}r(j]j]j]j]j]ujK#jhj]rjXAThe IPC package can also be cleaned using the following commands.rr}r(jjjjubaubj)r}r(jX Windows ::jjQjjNjjj}r(j]j]j]j]j]ujK%jhj]rjXWindowsrr}r(jXWindowsjjubaubj)r}r(jXCcd (Processor SDK RTOS folder) setupenv.bat gmake ipc_cleanjjQjjNjjj}r(j@jAj]j]j]j]j]ujMtjhj]rjXCcd (Processor SDK RTOS folder) setupenv.bat gmake ipc_cleanrr}r(jUjjubaubj)r}r(jXLinux ::jjQjjNjjj}r(j]j]j]j]j]ujK,jhj]rjXLinuxrr}r(jXLinuxjjubaubj)r}r(jXBcd (Processor SDK RTOS folder) source ./setupenv.sh make ipc_cleanjjQjjNjjj}r(j@jAj]j]j]j]j]ujM{jhj]rjXBcd (Processor SDK RTOS folder) source ./setupenv.sh make ipc_cleanrr}r(jUjjubaubj)r}r(jXtThe install guides below have been kept here for those using older, legacy versions of IPC outside of Processor SDK.rjjQjjNjjj}r(j]j]j]j]j]ujK3jhj]rjXtThe install guides below have been kept here for those using older, legacy versions of IPC outside of Processor SDK.rr}r(jjjjubaubj)r}r(jXThe various IPC Install Guides describe the mechanics of rebuilding IPC libraries. Please consult the Install Guide appropriate for your environment.rjjQjjNjjj}r(j]j]j]j]j]ujK5jhj]rjXThe various IPC Install Guides describe the mechanics of rebuilding IPC libraries. Please consult the Install Guide appropriate for your environment.rr}r(jjjjubaubjt)r}r(jUjjQjjNjjwj}r(jyX-j]j]j]j]j]ujK9jhj]r(j{)r}r(jXn`IPC Install Guide BIOS `__ - for all-BIOS environmentsjjjjNjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXn`IPC Install Guide BIOS `__ - for all-BIOS environmentsjjjjNjjj}r(j]j]j]j]j]ujK9j]r(j)r}r(jXR`IPC Install Guide BIOS `__j}r(UnameXIPC Install Guide BIOSjX5index_Foundational_Components.html#bios-install-guidej]j]j]j]j]ujjj]rjXIPC Install Guide BIOSrr}r(jUjjubajjubjX - for all-BIOS environmentsrr}r(jX - for all-BIOS environmentsjjubeubaubj{)r}r(jX`IPC Install Guide Linux `__ - for environments with a combination of Linux and BIOSjjjjNjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX`IPC Install Guide Linux `__ - for environments with a combination of Linux and BIOSjjjjNjjj}r(j]j]j]j]j]ujK;j]r(j)r}r(jXT`IPC Install Guide Linux `__j}r(UnameXIPC Install Guide LinuxjX6index_Foundational_Components.html#linux-install-guidej]j]j]j]j]ujjj]rjXIPC Install Guide Linuxrr}r(jUjjubajjubjX8 - for environments with a combination of Linux and BIOSrr}r(jX8 - for environments with a combination of Linux and BIOSjjubeubaubj{)r}r(jX`IPC Install Guide QNX `__ - for environments with a combination of QNX and BIOS jjjjNjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX`IPC Install Guide QNX `__ - for environments with a combination of QNX and BIOSjjjjNjjj}r(j]j]j]j]j]ujK=j]r(j)r}r(jXP`IPC Install Guide QNX `__j}r(UnameXIPC Install Guide QNXjX4index_Foundational_Components.html#qnx-install-guidej]j]j]j]j]ujjj]rjXIPC Install Guide QNXrr}r(jUjjubajjubjX6 - for environments with a combination of QNX and BIOSrr}r(jX6 - for environments with a combination of QNX and BIOSjjubeubaubeubeubj)r}r(jUjj<jjNjjj}r(j]j]j]j]rU'pointing-a-ccs-project-at-a-rebuilt-ipcraj]rj+aujKAjhj]r(j)r}r(jX'Pointing a CCS Project at a Rebuilt IPCrjjjjNjjj}r(j]j]j]j]j]ujKAjhj]rjX'Pointing a CCS Project at a Rebuilt IPCrr}r(jjjjubaubj)r}r(jXTo build your application using the version of IPC you have rebuilt, you must point your project to this rebuilt version by following these steps:rjjjjNjjj}r(j]j]j]j]j]ujKCjhj]rjXTo build your application using the version of IPC you have rebuilt, you must point your project to this rebuilt version by following these steps:rr}r(jjjjubaubcdocutils.nodes enumerated_list r )r }r (jUjjjjNjUenumerated_listr j}r (UsuffixrU.j]j]j]UprefixrUj]j]UenumtyperUarabicrujKGjhj]r(j{)r}r(jX@Open CCS and select the application project you want to rebuild.rjj jjNjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjNjjj}r(j]j]j]j]j]ujKGj]rjX@Open CCS and select the application project you want to rebuild.rr}r(jjjjubaubaubj{)r}r (jXRight-click on your project and choose **Build Properties**. If you have a configuration project that is separate from your application project, open the build properties for the configuration project.jj jjNjjj}r!(j]j]j]j]j]ujNjhj]r"j)r#}r$(jXRight-click on your project and choose **Build Properties**. If you have a configuration project that is separate from your application project, open the build properties for the configuration project.jjjjNjjj}r%(j]j]j]j]j]ujKHj]r&(jX'Right-click on your project and choose r'r(}r)(jX'Right-click on your project and choose jj#ubj)r*}r+(jX**Build Properties**j}r,(j]j]j]j]j]ujj#j]r-jXBuild Propertiesr.r/}r0(jUjj*ubajjubjX. If you have a configuration project that is separate from your application project, open the build properties for the configuration project.r1r2}r3(jX. If you have a configuration project that is separate from your application project, open the build properties for the configuration project.jj#ubeubaubj{)r4}r5(jXPIn the **CCS Build** category of the Properties dialog, choose the **RTSC** tab.jj jjNjjj}r6(j]j]j]j]j]ujNjhj]r7j)r8}r9(jXPIn the **CCS Build** category of the Properties dialog, choose the **RTSC** tab.jj4jjNjjj}r:(j]j]j]j]j]ujKKj]r;(jXIn the r<r=}r>(jXIn the jj8ubj)r?}r@(jX **CCS Build**j}rA(j]j]j]j]j]ujj8j]rBjX CCS BuildrCrD}rE(jUjj?ubajjubjX/ category of the Properties dialog, choose the rFrG}rH(jX/ category of the Properties dialog, choose the jj8ubj)rI}rJ(jX**RTSC**j}rK(j]j]j]j]j]ujj8j]rLjXRTSCrMrN}rO(jUjjIubajjubjX tab.rPrQ}rR(jX tab.jj8ubeubaubj{)rS}rT(jXUnder the **Products and Repositories** tab, uncheck *all* the boxes for IPC. This ensures that no version is selected. .. image:: ../images/Rebuild_deselect.png jj jNjjj}rU(j]j]j]j]j]ujNjhj]rV(j)rW}rX(jXwUnder the **Products and Repositories** tab, uncheck *all* the boxes for IPC. This ensures that no version is selected.jjSjjNjjj}rY(j]j]j]j]j]ujKMj]rZ(jX Under the r[r\}r](jX Under the jjWubj)r^}r_(jX**Products and Repositories**j}r`(j]j]j]j]j]ujjWj]rajXProducts and Repositoriesrbrc}rd(jUjj^ubajjubjX tab, uncheck rerf}rg(jX tab, uncheck jjWubjM)rh}ri(jX*all*j}rj(j]j]j]j]j]ujjWj]rkjXallrlrm}rn(jUjjhubajjUubjX= the boxes for IPC. This ensures that no version is selected.rorp}rq(jX= the boxes for IPC. This ensures that no version is selected.jjWubeubjR)rr}rs(jX*.. image:: ../images/Rebuild_deselect.png j}rt(UuriX#rtos/../images/Rebuild_deselect.pngruj]j]j]j]jX}rvU*jusj]ujjSj]jjZubeubj{)rw}rx(jXGClick the **Add** button next to the **Products and Repositories** tab.jj jjNjjj}ry(j]j]j]j]j]ujNjhj]rzj)r{}r|(jXGClick the **Add** button next to the **Products and Repositories** tab.jjwjjNjjj}r}(j]j]j]j]j]ujKRj]r~(jX Click the rr}r(jX Click the jj{ubj)r}r(jX**Add**j}r(j]j]j]j]j]ujj{j]rjXAddrr}r(jUjjubajjubjX button next to the rr}r(jX button next to the jj{ubj)r}r(jX**Products and Repositories**j}r(j]j]j]j]j]ujj{j]rjXProducts and Repositoriesrr}r(jUjjubajjubjX tab.rr}r(jX tab.jj{ubeubaubj{)r}r(jXChoose **Select repository from file-system**, and browse to the "packages" directory of the location where you copied and rebuilt IPC. For example, the location may be C:\myIpcBuilds\custom_ipc_1_22_##-##\packages. .. image:: ../images/Rebuild_addrep.png jj jNjjj}r(j]j]j]j]j]ujNjhj]r(j)r}r(jXChoose **Select repository from file-system**, and browse to the "packages" directory of the location where you copied and rebuilt IPC. For example, the location may be C:\myIpcBuilds\custom_ipc_1_22_##-##\packages.jjjjNjjj}r(j]j]j]j]j]ujKTj]r(jXChoose rr}r(jXChoose jjubj)r}r(jX&**Select repository from file-system**j}r(j]j]j]j]j]ujjj]rjX"Select repository from file-systemrr}r(jUjjubajjubjX, and browse to the "packages" directory of the location where you copied and rebuilt IPC. For example, the location may be C:myIpcBuildscustom_ipc_1_22_##-##packages.rr}r(jX, and browse to the "packages" directory of the location where you copied and rebuilt IPC. For example, the location may be C:\myIpcBuilds\custom_ipc_1_22_##-##\packages.jjubeubjR)r}r(jX(.. image:: ../images/Rebuild_addrep.png j}r(UuriX!rtos/../images/Rebuild_addrep.pngrj]j]j]j]jX}rU*jsj]ujjj]jjZubeubj{)r}r(jX3Click **OK** to apply these changes to the project.rjj jjNjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjNjjj}r(j]j]j]j]j]ujK[j]r(jXClick rr}r(jXClick jjubj)r}r(jX**OK**j}r(j]j]j]j]j]ujjj]rjXOKrr}r(jUjjubajjubjX' to apply these changes to the project.rr}r(jX' to apply these changes to the project.jjubeubaubj{)r}r(jXDYou may now rebuild your project using the re-built version of IPC. jj jjNjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXCYou may now rebuild your project using the re-built version of IPC.rjjjjNjjj}r(j]j]j]j]j]ujK\j]rjXCYou may now rebuild your project using the re-built version of IPC.rr}r(jjjjubaubaubeubjc)r}r(jUjjjjNjjfj}r(j]j]j]j]j]ujK^jhj]rji)r}r(jUjlKjjjjNjjj}r(j]j]j]j]j]ujKjhj]ubaubjc)r}r(jUjjjjjjfj}r(j]j]j]j]j]ujKnjhj]rji)r}r(jUjlKjjjjjjj}r(j]j]j]j]j]ujKjhj]ubaubeubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rUipc-transportsraj]rhaujKqjhj]r(j)r}r(jXIPC Transportsrjjjjjjj}r(j]j]j]j]j]ujKqjhj]rjXIPC Transportsrr}r(jjjjubaubj7)r}r(jXIhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_IPC_Transportsjjjj:X(source/common/IPC/IPC_Transports.rst.incrr}rbjj>j}r(j@jAj]j]j]j]j]ujKjhj]rjXIhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_IPC_Transportsrr}r(jUjjubaubj)r}r(jUjKjjjjjjj}r(j]rX introductionraj]j]j]rUid11raj]ujKjhj]r(j)r}r(jX Introductionrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjX Introductionrr}r(jjjjubaubj)r }r (jXIPC transports are the underlying configurable data paths over shared memory and hardware resources, which implement the IPC MessageQ APIs. MessageQ provides a common IPC interface between processors within a system containing a single or multiple KeyStone devices. Communication between the processors is enabled through the use of IPC transports. The transports supplied with the IPC component are shared memory based, capable of intra-device communication. Additional transports, utilizing the QMSS and SRIO LLDs, are supplied via Yocto/bitbake for ARMv7 Linux IPC and PROCSDK PDK for SYS/BIOS DSP IPC, enabling intra-SoC and inter-SoC communication, respectively.r jjjjjjj}r (j]j]j]j]j]ujKjhj]r jXIPC transports are the underlying configurable data paths over shared memory and hardware resources, which implement the IPC MessageQ APIs. MessageQ provides a common IPC interface between processors within a system containing a single or multiple KeyStone devices. Communication between the processors is enabled through the use of IPC transports. The transports supplied with the IPC component are shared memory based, capable of intra-device communication. Additional transports, utilizing the QMSS and SRIO LLDs, are supplied via Yocto/bitbake for ARMv7 Linux IPC and PROCSDK PDK for SYS/BIOS DSP IPC, enabling intra-SoC and inter-SoC communication, respectively.rr}r(jj jj ubaubj)r}r(jXuThe below table gives an overview of the transport offerings, their location, and the communication path they enable.rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXuThe below table gives an overview of the transport offerings, their location, and the communication path they enable.rr}r(jjjjubaubjy )r}r(jUjjjNjj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujjj]r (j )r!}r"(jUj}r#(j]j]j]j]j]UcolwidthKujjj]jj ubj )r$}r%(jUj}r&(j]j]j]j]j]UcolwidthKujjj]jj ubj )r'}r((jUj}r)(j]j]j]j]j]UcolwidthKujjj]jj ubj )r*}r+(jUj}r,(j]j]j]j]j]UcolwidthKujjj]jj ubj )r-}r.(jUj}r/(j]j]j]j]j]UcolwidthKujjj]jj ubj )r0}r1(jUj}r2(j]j]j]j]j]UcolwidthKujjj]jj ubj )r3}r4(jUj}r5(j]j]j]j]j]ujjj]r6(j )r7}r8(jUj}r9(j]j]j]j]j]ujj3j]r:(j )r;}r<(jUj}r=(j]j]j]j]j]ujj7j]r>j)r?}r@(jX **Transport**rAjj;jjjjj}rB(j]j]j]j]j]ujKj]rCj)rD}rE(jjAj}rF(j]j]j]j]j]ujj?j]rGjX TransportrHrI}rJ(jUjjDubajjubaubajj ubj )rK}rL(jUj}rM(j]j]j]j]j]ujj7j]rNj)rO}rP(jX**MessageQ Interface Type**rQjjKjjjjj}rR(j]j]j]j]j]ujKj]rSj)rT}rU(jjQj}rV(j]j]j]j]j]ujjOj]rWjXMessageQ Interface TyperXrY}rZ(jUjjTubajjubaubajj ubj )r[}r\(jUj}r](j]j]j]j]j]ujj7j]r^j)r_}r`(jX **Location**rajj[jjjjj}rb(j]j]j]j]j]ujKj]rcj)rd}re(jjaj}rf(j]j]j]j]j]ujj_j]rgjXLocationrhri}rj(jUjjdubajjubaubajj ubj )rk}rl(jUj}rm(j]j]j]j]j]ujj7j]rnj)ro}rp(jX**Communication Route**rqjjkjjjjj}rr(j]j]j]j]j]ujKj]rsj)rt}ru(jjqj}rv(j]j]j]j]j]ujjoj]rwjXCommunication Routerxry}rz(jUjjtubajjubaubajj ubj )r{}r|(jUj}r}(j]j]j]j]j]ujj7j]r~j)r}r(jX**Enabled Communication Path**rjj{jjjjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXEnabled Communication Pathrr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj7j]rj)r}r(jX**Special Considerations**rjjjjjjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXSpecial Considerationsrr}r(jUjjubajjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujj3j]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXTransport Shm...rjjjjjjj}r(j]j]j]j]j]ujKj]rjXTransport Shm...rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXMessageQ (priority based)rjjjjjjj}r(j]j]j]j]j]ujKj]rjXMessageQ (priority based)rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX(IPC component - SYS/BIOS subdirect oriesrjjjjjjj}r(j]j]j]j]j]ujKj]rjX(IPC component - SYS/BIOS subdirect oriesrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX Shared memoryrjjjjjjj}r(j]j]j]j]j]ujKj]rjX Shared memoryrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXSYS/BIOS DSP to DSPrjjjjjjj}r(j]j]j]j]j]ujKj]rjXSYS/BIOS DSP to DSPrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXThere are multiple implementations of Transport Shm delivered within the IPC component Please see the IPC documentation provided with the component for more information on these shared memory transport implementionsrjjjjjjj}r(j]j]j]j]j]ujKj]rjXThere are multiple implementations of Transport Shm delivered within the IPC component Please see the IPC documentation provided with the component for more information on these shared memory transport implementionsrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujj3j]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXTransport Rpmsgrjjjjjjj}r(j]j]j]j]j]ujK(j]rjXTransport Rpmsgrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXMessageQ (priority based)rjjjjjjj}r(j]j]j]j]j]ujK(j]rjXMessageQ (priority based)rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rjt)r}r(jUj}r (jyX-j]j]j]j]j]ujjj]r (j{)r }r (jX+IPC component - ARMv7 Linux subdirect oriesj}r (j]j]j]j]j]ujjj]rj)r}r(jX+IPC component - ARMv7 Linux subdirect oriesrjj jjjjj}r(j]j]j]j]j]ujK(j]rjX+IPC component - ARMv7 Linux subdirect oriesrr}r(jjjjubaubajjubj{)r}r(jX(IPC component - SYS/BIOS subdirect oriesj}r(j]j]j]j]j]ujjj]rj)r}r(jX(IPC component - SYS/BIOS subdirect oriesrjjjjjjj}r(j]j]j]j]j]ujK-j]rjX(IPC component - SYS/BIOS subdirect oriesr r!}r"(jjjjubaubajjubj{)r#}r$(jX'Yocto/ bitbake ti-ipc recipe j}r%(j]j]j]j]j]ujjj]r&j)r'}r((jXYocto/ bitbake ti-ipc reciper)jj#jjjjj}r*(j]j]j]j]j]ujK2j]r+jXYocto/ bitbake ti-ipc reciper,r-}r.(jj)jj'ubaubajjubejjwubajj ubj )r/}r0(jUj}r1(j]j]j]j]j]ujjj]r2j)r3}r4(jX Shared memoryr5jj/jjjjj}r6(j]j]j]j]j]ujK(j]r7jX Shared memoryr8r9}r:(jj5jj3ubaubajj ubj )r;}r<(jUj}r=(j]j]j]j]j]ujjj]r>jt)r?}r@(jUj}rA(jyX-j]j]j]j]j]ujj;j]rBj{)rC}rD(jX6ARMv7 Linux to/from SYS/BIOS DSP j}rE(j]j]j]j]j]ujj?j]rFj)rG}rH(jX ARMv7 Linux to/from SYS/BIOS DSPrIjjCjjjjj}rJ(j]j]j]j]j]ujK(j]rKjX ARMv7 Linux to/from SYS/BIOS DSPrLrM}rN(jjIjjGubaubajjubajjwubajj ubj )rO}rP(jUj}rQ(j]j]j]j]j]ujjj]rRj)rS}rT(jX[MessageQ messages sent over Transport Rpmsg traveling from/to ARMv7 user space go through the Linux kernel before reaching the DSP. This provides *clean* partitioning between user memory and DSP memory. However, Transport Rpmsg is considered a *slow path* since the user space MessageQ messages must be copied from/to DSP memory by kernel and DSP.jjOjjjjj}rU(j]j]j]j]j]ujK(j]rV(jXMessageQ messages sent over Transport Rpmsg traveling from/to ARMv7 user space go through the Linux kernel before reaching the DSP. This provides rWrX}rY(jXMessageQ messages sent over Transport Rpmsg traveling from/to ARMv7 user space go through the Linux kernel before reaching the DSP. This provides jjSubjM)rZ}r[(jX*clean*j}r\(j]j]j]j]j]ujjSj]r]jXcleanr^r_}r`(jUjjZubajjUubjX[ partitioning between user memory and DSP memory. However, Transport Rpmsg is considered a rarb}rc(jX[ partitioning between user memory and DSP memory. However, Transport Rpmsg is considered a jjSubjM)rd}re(jX *slow path*j}rf(j]j]j]j]j]ujjSj]rgjX slow pathrhri}rj(jUjjdubajjUubjX\ since the user space MessageQ messages must be copied from/to DSP memory by kernel and DSP.rkrl}rm(jX\ since the user space MessageQ messages must be copied from/to DSP memory by kernel and DSP.jjSubeubajj ubejj ubj )rn}ro(jUj}rp(j]j]j]j]j]ujj3j]rq(j )rr}rs(jUj}rt(j]j]j]j]j]ujjnj]ruj)rv}rw(jXSYS/BIOS DSP Transport Sriorxjjrjjjjj}ry(j]j]j]j]j]ujKBj]rzjXSYS/BIOS DSP Transport Srior{r|}r}(jjxjjvubaubajj ubj )r~}r(jUj}r(j]j]j]j]j]ujjnj]rj)r}r(jXNetworkrjj~jjjjj}r(j]j]j]j]j]ujKBj]rjXNetworkrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjnj]rj)r}r(jXPROCSDK RTOS PDKrjjjjjjj}r(j]j]j]j]j]ujKBj]rjXPROCSDK RTOS PDKrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjnj]rj)r}r(jXSRIO LLDrjjjjjjj}r(j]j]j]j]j]ujKBj]rjXSRIO LLDrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjnj]rjt)r}r(jUj}r(jyX-j]j]j]j]j]ujjj]r(j{)r}r(jX:SYS/BIOS DSP to/from SYS/BIOS DSP (intra and inter-device)j}r(j]j]j]j]j]ujjj]rj)r}r(jX:SYS/BIOS DSP to/from SYS/BIOS DSP (intra and inter-device)rjjjjjjj}r(j]j]j]j]j]ujKBj]rjX:SYS/BIOS DSP to/from SYS/BIOS DSP (intra and inter-device)rr}r(jjjjubaubajjubj{)r}r(jX]SYS/BIOS DSP to/from ARMv7 Linux (intra- and inter- device) j}r(j]j]j]j]j]ujjj]rj)r}r(jX;SYS/BIOS DSP to/from ARMv7 Linux (intra- and inter- device)rjjjjjjj}r(j]j]j]j]j]ujKGj]rjX;SYS/BIOS DSP to/from ARMv7 Linux (intra- and inter- device)rr}r(jjjjubaubajjubejjwubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjnj]r(j)r}r(jXTransportSrio can send MessageQ messages to ARMv7 and DSP processors on remote devices in a multiple device system. IPC MultiProc must be configured to be aware of all processors existing on all devices and all devices must be connected over a SRIO interconnect.rjjjjjjj}r(j]j]j]j]j]ujKBj]rjXTransportSrio can send MessageQ messages to ARMv7 and DSP processors on remote devices in a multiple device system. IPC MultiProc must be configured to be aware of all processors existing on all devices and all devices must be connected over a SRIO interconnect.rr}r(jjjjubaubj)r}r(jX8The main purpose of TransportSrio is for multi-device communication over MessageQ. The transmission latency is greater for this transport due to the latter capability Therefore it is recommended a shared memory or other LLD-based transport is used for intra-device communication due to their lower latency costs.rjjjjjjj}r(j]j]j]j]j]ujKVj]rjX8The main purpose of TransportSrio is for multi-device communication over MessageQ. The transmission latency is greater for this transport due to the latter capability Therefore it is recommended a shared memory or other LLD-based transport is used for intra-device communication due to their lower latency costs.rr}r(jjjjubaubejj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujj3j]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXARMv7 Linux Transport Sriorjjjjjjj}r(j]j]j]j]j]ujKoj]rjXARMv7 Linux Transport Sriorr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXNetworkrjjjjjjj}r(j]j]j]j]j]ujKoj]rjXNetworkrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX(Yocto/bit bake ti-transp ort-srio reciperjjjjjjj}r(j]j]j]j]j]ujKoj]rjX(Yocto/bit bake ti-transp ort-srio reciperr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXSRIO LLDrjjjjjjj}r(j]j]j]j]j]ujKoj]rjXSRIO LLDrr}r (jjjjubaubajj ubj )r }r (jUj}r (j]j]j]j]j]ujjj]r jt)r}r(jUj}r(jyX-j]j]j]j]j]ujj j]r(j{)r}r(jX9ARMv7 Linux to/from ARMv7 Linux (intra- and inter-device)j}r(j]j]j]j]j]ujjj]rj)r}r(jX9ARMv7 Linux to/from ARMv7 Linux (intra- and inter-device)rjjjjjjj}r(j]j]j]j]j]ujKoj]rjX9ARMv7 Linux to/from ARMv7 Linux (intra- and inter-device)rr}r(jjjjubaubajjubj{)r}r(jX]SYS/BIOS DSP to/from ARMv7 Linux (intra- and inter-device) j}r (j]j]j]j]j]ujjj]r!j)r"}r#(jX:SYS/BIOS DSP to/from ARMv7 Linux (intra- and inter-device)r$jjjjjjj}r%(j]j]j]j]j]ujKtj]r&jX:SYS/BIOS DSP to/from ARMv7 Linux (intra- and inter-device)r'r(}r)(jj$jj"ubaubajjubejjwubajj ubj )r*}r+(jUj}r,(j]j]j]j]j]ujjj]r-(j)r.}r/(jXTransportSrio can send MessageQ messages to ARMv7 and DSP processors on remote devices in a multiple device system. IPC MultiProc must be configured to be aware of all processors existing on all devices and all devices must be connected over a SRIO interconnect.r0jj*jjjjj}r1(j]j]j]j]j]ujKoj]r2jXTransportSrio can send MessageQ messages to ARMv7 and DSP processors on remote devices in a multiple device system. IPC MultiProc must be configured to be aware of all processors existing on all devices and all devices must be connected over a SRIO interconnect.r3r4}r5(jj0jj.ubaubj)r6}r7(jX:The main purpose of TransportSrio is for multi-device communication over MessageQ. The transmission latency is greater for this transport due to the latter capability. Therefore, it is recommended a shared memory or other LLD-based transport is used for intra-device communication due to their lower latency costs.r8jj*jjjjj}r9(j]j]j]j]j]ujKj]r:jX:The main purpose of TransportSrio is for multi-device communication over MessageQ. The transmission latency is greater for this transport due to the latter capability. Therefore, it is recommended a shared memory or other LLD-based transport is used for intra-device communication due to their lower latency costs.r;r<}r=(jj8jj6ubaubejj ubejj ubj )r>}r?(jUj}r@(j]j]j]j]j]ujj3j]rA(j )rB}rC(jUj}rD(j]j]j]j]j]ujj>j]rEj)rF}rG(jXSYS/BIOS DSP Transport QmssrHjjBjjjjj}rI(j]j]j]j]j]ujKj]rJjXSYS/BIOS DSP Transport QmssrKrL}rM(jjHjjFubaubajj ubj )rN}rO(jUj}rP(j]j]j]j]j]ujj>j]rQj)rR}rS(jXNetworkrTjjNjjjjj}rU(j]j]j]j]j]ujKj]rVjXNetworkrWrX}rY(jjTjjRubaubajj ubj )rZ}r[(jUj}r\(j]j]j]j]j]ujj>j]jj ubj )r]}r^(jUj}r_(j]j]j]j]j]ujj>j]r`j)ra}rb(jXQMSS LLDrcjj]jjjjj}rd(j]j]j]j]j]ujKj]rejXQMSS LLDrfrg}rh(jjcjjaubaubajj ubj )ri}rj(jUj}rk(j]j]j]j]j]ujj>j]rljt)rm}rn(jUj}ro(jyX-j]j]j]j]j]ujjij]rp(j{)rq}rr(jX!SYS/BIOS DSP to/from SYS/BIOS DSPj}rs(j]j]j]j]j]ujjmj]rtj)ru}rv(jX!SYS/BIOS DSP to/from SYS/BIOS DSPrwjjqjjjjj}rx(j]j]j]j]j]ujKj]ryjX!SYS/BIOS DSP to/from SYS/BIOS DSPrzr{}r|(jjwjjuubaubajjubj{)r}}r~(jX SYS/BIOS DSP to/from ARMv7 Linuxj}r(j]j]j]j]j]ujjmj]rj)r}r(jX SYS/BIOS DSP to/from ARMv7 Linuxrjj}jjjjj}r(j]j]j]j]j]ujKj]rjX SYS/BIOS DSP to/from ARMv7 Linuxrr}r(jjjjubaubajjubejjwubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj>j]jj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujj3j]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rjt)r}r(jUj}r(jyX-j]j]j]j]j]ujjj]r(j{)r}r(jXARMv7 Linux process to process.j}r(j]j]j]j]j]ujjj]rj)r}r(jXARMv7 Linux process to process.rjjjjjjj}r(j]j]j]j]j]ujKj]rjXARMv7 Linux process to process.rr}r(jjjjubaubajjubj{)r}r(jX ARMv7 Linux to/from SYS/BIOS DSPj}r(j]j]j]j]j]ujjj]rj)r}r(jX ARMv7 Linux to/from SYS/BIOS DSPrjjjjjjj}r(j]j]j]j]j]ujKj]rjX ARMv7 Linux to/from SYS/BIOS DSPrr}r(jjjjubaubajjubejjwubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]jj ubejj ubejj ubejj ubaubj)r}r(jXThe IPC component (ARMv7 and SYS/BIOS) is available in PROCSDK RTOS and Linux installations. It will be installed in /ipc_#_##_##_##. Additionally, the IPC component's ARMv7 source is packaged in a Yocto/bitbake recipe. A user can develop ARMv7 Linux user-space applications with IPC on Keystone I and KeyStone II devices by building the ti-ipc package in Yocto.rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXThe IPC component (ARMv7 and SYS/BIOS) is available in PROCSDK RTOS and Linux installations. It will be installed in /ipc_#_##_##_##. Additionally, the IPC component's ARMv7 source is packaged in a Yocto/bitbake recipe. A user can develop ARMv7 Linux user-space applications with IPC on Keystone I and KeyStone II devices by building the ti-ipc package in Yocto.rr}r(jjjjubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rUmodes-of-operationraj]rhaujKjhj]r(j)r}r(jXModes of Operationrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXModes of Operationrr}r(jjjjubaubj)r}r(jUjKjjjjjjj}r(j]rXsys/bios dsp transportsrioraj]j]j]rUsys-bios-dsp-transportsrioraj]ujKjhj]r(j)r}r(jXSYS/BIOS DSP TransportSriorjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXSYS/BIOS DSP TransportSriorr}r(jjjjubaubj)r}r(jX.The following SRIO socket types are supported:rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjX.The following SRIO socket types are supported:rr}r(jjjjubaubj)r}r(jX**TransportSrio_srioSockType_TYPE_9**: In this mode, the SRIO IPC transport will use Type 9 sockets to communicate with other SRIO IPC transport endpoints.jjjjjjj}r(j]j]j]j]j]ujKjhj]r(j)r}r(jX%**TransportSrio_srioSockType_TYPE_9**j}r(j]j]j]j]j]ujjj]rjX!TransportSrio_srioSockType_TYPE_9rr}r(jUjjubajjubjXv: In this mode, the SRIO IPC transport will use Type 9 sockets to communicate with other SRIO IPC transport endpoints.rr}r(jXv: In this mode, the SRIO IPC transport will use Type 9 sockets to communicate with other SRIO IPC transport endpoints.jjubeubj)r}r(jX**TransportSrio_srioSockType_TYPE_11**: In this mode, the SRIO IPC transport will use Type 11 sockets to communicate with other SRIO IPC transport endpoints.jjjjjjj}r(j]j]j]j]j]ujKjhj]r(j)r}r(jX&**TransportSrio_srioSockType_TYPE_11**j}r(j]j]j]j]j]ujjj]rjX"TransportSrio_srioSockType_TYPE_11rr}r(jUjjubajjubjXw: In this mode, the SRIO IPC transport will use Type 11 sockets to communicate with other SRIO IPC transport endpoints.rr}r (jXw: In this mode, the SRIO IPC transport will use Type 11 sockets to communicate with other SRIO IPC transport endpoints.jjubeubeubj)r }r (jUjKjjjjjjj}r (j]r Xarm linux transportsrioraj]j]j]rUarm-linux-transportsrioraj]ujKjhj]r(j)r}r(jXARM Linux TransportSriorjj jjjjj}r(j]j]j]j]j]ujKjhj]rjXARM Linux TransportSriorr}r(jjjjubaubj)r}r(jX.The following SRIO socket types are supported:rjj jjjjj}r(j]j]j]j]j]ujKjhj]rjX.The following SRIO socket types are supported:rr }r!(jjjjubaubj)r"}r#(jX**sock_TYPE_9**: In this mode, the ARM Linux SRIO IPC transport will use Type 9 sockets to communicate with other SRIO IPC transport endpoints.jj jjjjj}r$(j]j]j]j]j]ujKjhj]r%(j)r&}r'(jX**sock_TYPE_9**j}r((j]j]j]j]j]ujj"j]r)jX sock_TYPE_9r*r+}r,(jUjj&ubajjubjX: In this mode, the ARM Linux SRIO IPC transport will use Type 9 sockets to communicate with other SRIO IPC transport endpoints.r-r.}r/(jX: In this mode, the ARM Linux SRIO IPC transport will use Type 9 sockets to communicate with other SRIO IPC transport endpoints.jj"ubeubj)r0}r1(jX**sock_TYPE_11**: In this mode, the ARM Linux SRIO IPC transport will use Type 11 sockets to communicate with other SRIO IPC transport endpoints.jj jjjjj}r2(j]j]j]j]j]ujKjhj]r3(j)r4}r5(jX**sock_TYPE_11**j}r6(j]j]j]j]j]ujj0j]r7jX sock_TYPE_11r8r9}r:(jUjj4ubajjubjX: In this mode, the ARM Linux SRIO IPC transport will use Type 11 sockets to communicate with other SRIO IPC transport endpoints.r;r<}r=(jX: In this mode, the ARM Linux SRIO IPC transport will use Type 11 sockets to communicate with other SRIO IPC transport endpoints.jj0ubeubeubj)r>}r?(jUjKjjjjjjj}r@(j]rAXsys/bios dsp transportqmssrBaj]j]j]rCUsys-bios-dsp-transportqmssrDaj]ujKjhj]rE(j)rF}rG(jXSYS/BIOS DSP TransportQmssrHjj>jjjjj}rI(j]j]j]j]j]ujKjhj]rJjXSYS/BIOS DSP TransportQmssrKrL}rM(jjHjjFubaubj)rN}rO(jX5The following QMSS receive queue types are supported:rPjj>jjjjj}rQ(j]j]j]j]j]ujKjhj]rRjX5The following QMSS receive queue types are supported:rSrT}rU(jjPjjNubaubj)rV}rW(jX**TransportQmss_queueRcvType_ACCUMULATOR**: In this mode, the QMSS accumulator logic is used as the reception mechanism for the QMSS Transport.jj>jjjjj}rX(j]j]j]j]j]ujKjhj]rY(j)rZ}r[(jX***TransportQmss_queueRcvType_ACCUMULATOR**j}r\(j]j]j]j]j]ujjVj]r]jX&TransportQmss_queueRcvType_ACCUMULATORr^r_}r`(jUjjZubajjubjXe: In this mode, the QMSS accumulator logic is used as the reception mechanism for the QMSS Transport.rarb}rc(jXe: In this mode, the QMSS accumulator logic is used as the reception mechanism for the QMSS Transport.jjVubeubj)rd}re(jX**TransportQmss_queueRcvType_QPEND**: In this mode, a QMSS QPEND (direct interrupt) queue is used as the reception mechanism for the QMSS Transport.jj>jjjjj}rf(j]j]j]j]j]ujKjhj]rg(j)rh}ri(jX$**TransportQmss_queueRcvType_QPEND**j}rj(j]j]j]j]j]ujjdj]rkjX TransportQmss_queueRcvType_QPENDrlrm}rn(jUjjhubajjubjXp: In this mode, a QMSS QPEND (direct interrupt) queue is used as the reception mechanism for the QMSS Transport.rorp}rq(jXp: In this mode, a QMSS QPEND (direct interrupt) queue is used as the reception mechanism for the QMSS Transport.jjdubeubeubj)rr}rs(jUjKjjjjjjj}rt(j]ruXarm linux transportqmssrvaj]j]j]rwUarm-linux-transportqmssrxaj]ujKjhj]ry(j)rz}r{(jXARM Linux TransportQmssr|jjrjjjjj}r}(j]j]j]j]j]ujKjhj]r~jXARM Linux TransportQmssrr}r(jj|jjzubaubj)r}r(jXcA QMSS QPEND queue will always be used as the reception mechanism for the ARM Linux QMSS Transport.rjjrjjjjj}r(j]j]j]j]j]ujKjhj]rjXcA QMSS QPEND queue will always be used as the reception mechanism for the ARM Linux QMSS Transport.rr}r(jjjjubaubeubeubj)r}r(jUjKjjjjjjj}r(j]rjaj]j]j]rUid12raj]ujKjhj]r(j)r}r(jXTransport Configurationrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXTransport Configurationrr}r(jjjjubaubj)r}r(jUjKjjjjjjj}r(j]rjaj]j]j]rUid13raj]ujKjhj]r(j)r}r(jXSYS/BIOS DSP TransportSriorjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXSYS/BIOS DSP TransportSriorr}r(jjjjubaubj)r}r(jUjKjjjjjjj}r(j]rX"srio serdes and lane configurationraj]j]j]rU"srio-serdes-and-lane-configurationraj]ujKjhj]r(j)r}r(jX"SRIO SERDES and Lane Configurationrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjX"SRIO SERDES and Lane Configurationrr}r(jjjjubaubj)r}r(jX2Configuration of the SRIO SERDES and lanes are required before calling any driver APIs. Examples of the initialization sequences for supported EVMs are provided in the TransportSrio example folder. The examples call the SrioDevice_init() API prior to configuring the transport. SrioDevice_init() reference:rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjX2Configuration of the SRIO SERDES and lanes are required before calling any driver APIs. Examples of the initialization sequences for supported EVMs are provided in the TransportSrio example folder. The examples call the SrioDevice_init() API prior to configuring the transport. SrioDevice_init() reference:rr}r(jjjjubaubj)r}r(jX3ti/transport/ipc/c66/srio/example/src/device_srio.cjjjjjjj}r(j@jAj]j]j]j]j]ujMjhj]rjX3ti/transport/ipc/c66/srio/example/src/device_srio.crr}r(jUjjubaubj)r}r(jXDevelopers can modify the configurations made in the stock device_srio.c to change SRIO endpoint IDs, routing information, lane rates, loopback modes, etc.rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXDevelopers can modify the configurations made in the stock device_srio.c to change SRIO endpoint IDs, routing information, lane rates, loopback modes, etc.rr}r(jjjjubaubeubj)r}r(jUjKjjjjjjj}r(j]rXapisraj]j]j]rUapisraj]ujKjhj]r(j)r}r(jXAPIsrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXAPIsrr}r(jjjjubaubj)r}r(jXAPI reference for application:rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXAPI reference for application:rr}r(jjjjubaubj)r}r(jX4#include jjjjjjj}r(j@jAj]j]j]j]j]ujMjhj]rjX4#include rr}r(jUjjubaubeubeubj)r}r(jUjKjjjjjjj}r(j]rjaj]j]j]rUid14raj]ujMjhj]r(j)r}r(jXARM Linux TransportSriorjjjjjjj}r(j]j]j]j]j]ujMjhj]rjXARM Linux TransportSriorr}r(jjjjubaubj)r}r(jUjKjjjjjjj}r(j]r jaj]j]j]r Uid15r aj]ujMjhj]r (j)r }r (jX"SRIO SERDES and Lane Configurationr jjjjjjj}r (j]j]j]j]j]ujMjhj]r jX"SRIO SERDES and Lane Configurationr r }r (jj jj ubaubj)r }r (jX`Configuration of the SRIO SERDES and lanes are required before calling any driver APIs. Examples of the initialization sequences for supported EVMs are provided in the TransportSrio test folder. The examples call the SrioDevice_init() API prior to configuring the transport. SrioDevice_init() reference from keystone-linux/ipc-transport git repository:r jjjjjjj}r (j]j]j]j]j]ujMjhj]r jX`Configuration of the SRIO SERDES and lanes are required before calling any driver APIs. Examples of the initialization sequences for supported EVMs are provided in the TransportSrio test folder. The examples call the SrioDevice_init() API prior to configuring the transport. SrioDevice_init() reference from keystone-linux/ipc-transport git repository:r r }r (jj jj ubaubj)r }r (jX4linux/srio/test/[consumer or producer]_device_srio.cjjjjjjj}r (j@jAj]j]j]j]j]ujMjhj]r jX4linux/srio/test/[consumer or producer]_device_srio.cr r }r (jUjj ubaubj)r }r (jXDevelopers can modify the configurations made in the stock device_srio.c to change SRIO endpoint IDs, routing information, lane rates, loopback modes, etc.r jjjjjjj}r (j]j]j]j]j]ujMjhj]r jXDevelopers can modify the configurations made in the stock device_srio.c to change SRIO endpoint IDs, routing information, lane rates, loopback modes, etc.r r! }r" (jj jj ubaubeubj)r# }r$ (jUjjjjjjj}r% (j]j]j]j]r& U mpm-transport-srio-configurationr' aj]r( hAaujMjhj]r) (j)r* }r+ (jX MPM Transport SRIO Configurationr, jj# jjjjj}r- (j]j]j]j]j]ujMjhj]r. jX MPM Transport SRIO Configurationr/ r0 }r1 (jj, jj* ubaubj)r2 }r3 (jXjTransportSrio leverages MPM Transport in order to manage configuration of the QMSS, CPPI, and SRIO LLDs. As a result, the transport's descriptor and descriptor buffer management is pushed to MPM Transport in the ARM Linux version of TransportSrio. The MPM Transport JSON configuration file can be modified to change QMSS descriptor and buffer related parameters.r4 jj# jjjjj}r5 (j]j]j]j]j]ujMjhj]r6 jXjTransportSrio leverages MPM Transport in order to manage configuration of the QMSS, CPPI, and SRIO LLDs. As a result, the transport's descriptor and descriptor buffer management is pushed to MPM Transport in the ARM Linux version of TransportSrio. The MPM Transport JSON configuration file can be modified to change QMSS descriptor and buffer related parameters.r7 r8 }r9 (jj4 jj2 ubaubj)r: }r; (jXiThe MPM Transport JSON configuration file is located in the Linux file system at /etc/mpm/mpm_config.jsonr< jj# jjjjj}r= (j]j]j]j]j]ujM!jhj]r> jXiThe MPM Transport JSON configuration file is located in the Linux file system at /etc/mpm/mpm_config.jsonr? r@ }rA (jj< jj: ubaubeubj)rB }rC (jUjKjjjjjjj}rD (j]rE jaj]j]j]rF Uid16rG aj]ujM%jhj]rH (j)rI }rJ (jXAPIsrK jjB jjjjj}rL (j]j]j]j]j]ujM%jhj]rM jXAPIsrN rO }rP (jjK jjI ubaubj)rQ }rR (jXOAPI reference for application from keystone-linux/ipc-transport git repository:rS jjB jjjjj}rT (j]j]j]j]j]ujM'jhj]rU jXOAPI reference for application from keystone-linux/ipc-transport git repository:rV rW }rX (jjS jjQ ubaubj)rY }rZ (jX%#include jjB jjjjj}r[ (j@jAj]j]j]j]j]ujMjhj]r\ jX%#include r] r^ }r_ (jUjjY ubaubeubeubj)r` }ra (jUjKjjjjjjj}rb (j]rc jBaj]j]j]rd Uid17re aj]ujM/jhj]rf (j)rg }rh (jXSYS/BIOS DSP TransportQmssri jj` jjjjj}rj (j]j]j]j]j]ujM/jhj]rk jXSYS/BIOS DSP TransportQmssrl rm }rn (jji jjg ubaubj)ro }rp (jUjKjj` jjjjj}rq (j]rr Xapisrs aj]j]j]rt Uid18ru aj]ujM2jhj]rv (j)rw }rx (jXAPIsry jjo jjjjj}rz (j]j]j]j]j]ujM2jhj]r{ jXAPIsr| r} }r~ (jjy jjw ubaubj)r }r (jXAPI reference for application:r jjo jjjjj}r (j]j]j]j]j]ujM4jhj]r jXAPI reference for application:r r }r (jj jj ubaubj)r }r (jX4#include jjo jjjjj}r (j@jAj]j]j]j]j]ujMjhj]r jX4#include r r }r (jUjj ubaubeubeubj)r }r (jUjKjjjjjjj}r (j]r jvaj]j]j]r Uid19r aj]ujM;jhj]r (j)r }r (jXARM Linux TransportQmssr jj jjjjj}r (j]j]j]j]j]ujM;jhj]r jXARM Linux TransportQmssr r }r (jj jj ubaubj)r }r (jUjj jjjjj}r (j]j]j]j]r U mpm-transport-qmss-configurationr aj]r j~aujM>jhj]r (j)r }r (jX MPM Transport QMSS Configurationr jj jjjjj}r (j]j]j]j]j]ujM>jhj]r jX MPM Transport QMSS Configurationr r }r (jj jj ubaubj)r }r (jXcTransportQmss leverages MPM Transport in order to manage configuration of the QMSS and CPPI LLDs. As a result, the transport's descriptor and descriptor buffer management is pushed to MPM Transport in the ARM Linux version of TransportQmss. The MPM Transport JSON configuration file can be modified to change QMSS descriptor and buffer related parameters.r jj jjjjj}r (j]j]j]j]j]ujM@jhj]r jXcTransportQmss leverages MPM Transport in order to manage configuration of the QMSS and CPPI LLDs. As a result, the transport's descriptor and descriptor buffer management is pushed to MPM Transport in the ARM Linux version of TransportQmss. The MPM Transport JSON configuration file can be modified to change QMSS descriptor and buffer related parameters.r r }r (jj jj ubaubj)r }r (jXiThe MPM Transport JSON configuration file is located in the Linux file system at /etc/mpm/mpm_config.jsonr jj jjjjj}r (j]j]j]j]j]ujMFjhj]r jXiThe MPM Transport JSON configuration file is located in the Linux file system at /etc/mpm/mpm_config.jsonr r }r (jj jj ubaubeubj)r }r (jUjKjj jjjjj}r (j]r Xapisr aj]j]j]r Uid20r aj]ujMJjhj]r (j)r }r (jXAPIsr jj jjjjj}r (j]j]j]j]j]ujMJjhj]r jXAPIsr r }r (jj jj ubaubj)r }r (jXOAPI reference for application from keystone-linux/ipc-transport git repository:r jj jjjjj}r (j]j]j]j]j]ujMLjhj]r jXOAPI reference for application from keystone-linux/ipc-transport git repository:r r }r (jj jj ubaubj)r }r (jX%#include jj jjjjj}r (j@jAj]j]j]j]j]ujMjhj]r jX%#include r r }r (jUjj ubaubeubeubeubj)r }r (jUjjjjjjj}r (j]j]j]j]r U!source-delivery-and-recompilationr aj]r jZaujMTjhj]r (j)r }r (jX!Source Delivery and Recompilationr jj jjjjj}r (j]j]j]j]j]ujMTjhj]r jX!Source Delivery and Recompilationr r }r (jj jj ubaubj)r }r (jUjKjj jjjjj}r (j]r Xsys/bios dsp transportsrior aj]j]j]r Uid21r aj]ujMWjhj]r (j)r }r (jXSYS/BIOS DSP TransportSrior jj jjjjj}r (j]j]j]j]j]ujMWjhj]r jXSYS/BIOS DSP TransportSrior r }r (jj jj ubaubj)r }r (jX~The SYS/BIOS DSP TransportSrio source code and examples are delivered within the PROCSDK RTOS PDK component. DSP TransportSrio can be rebuilt using the environment setup scripts provided with the PDK package. DSP TransportSrio example applications are created as part of the pdkProjectCreate scripts. They can be imported and built the same as PDK LLD example and test CCS projects.r jj jjjjj}r (j]j]j]j]j]ujMYjhj]r jX~The SYS/BIOS DSP TransportSrio source code and examples are delivered within the PROCSDK RTOS PDK component. DSP TransportSrio can be rebuilt using the environment setup scripts provided with the PDK package. DSP TransportSrio example applications are created as part of the pdkProjectCreate scripts. They can be imported and built the same as PDK LLD example and test CCS projects.r r!}r!(jj jj ubaubj)r!}r!(jUjKjj jjjjj}r!(j]r!Xrecompiling on windowsr!aj]j]j]r!Urecompiling-on-windowsr!aj]ujMajhj]r !(j)r !}r !(jXRecompiling on Windowsr !jj!jjjjj}r !(j]j]j]j]j]ujMajhj]r!jXRecompiling on Windowsr!r!}r!(jj !jj !ubaubj )r!}r!(jUjj!jjjj j}r!(jU.j]j]j]jUj]j]jjujMcjhj]r!(j{)r!}r!(jXKOpen a Windows command terminal and navigate to /packages.jj!jjjjj}r!(j]j]j]j]j]ujNjhj]r!j)r!}r!(jXKOpen a Windows command terminal and navigate to /packages.r!jj!jjjjj}r!(j]j]j]j]j]ujMcj]r!jXKOpen a Windows command terminal and navigate to /packages.r!r !}r!!(jj!jj!ubaubaubj{)r"!}r#!(jX$Run pdksetupenv.bat >pdksetupenv.batjj!jjjjj}r$!(j]j]j]j]j]ujNjhj]r%!j)r&!}r'!(jX$Run pdksetupenv.bat >pdksetupenv.batr(!jj"!jjjjj}r)!(j]j]j]j]j]ujMej]r*!jX$Run pdksetupenv.bat >pdksetupenv.batr+!r,!}r-!(jj(!jj&!ubaubaubj{)r.!}r/!(jXBNavigate to /packages/ti/transport/ipc/c66/srio/r0!jj!jjjjj}r1!(j]j]j]j]j]ujNjhj]r2!j)r3!}r4!(jj0!jj.!jjjjj}r5!(j]j]j]j]j]ujMgj]r6!jXBNavigate to /packages/ti/transport/ipc/c66/srio/r7!r8!}r9!(jj0!jj3!ubaubaubj{)r:!}r;!(jX,Build the IPC SRIO Transport library >gmake jj!jjjjj}r!}r?!(jX+Build the IPC SRIO Transport library >gmaker@!jj:!jjjjj}rA!(j]j]j]j]j]ujMhj]rB!jX+Build the IPC SRIO Transport library >gmakerC!rD!}rE!(jj@!jj>!ubaubaubeubj)rF!}rG!(jXLIssue the following commands if the SRIO transport ever needs to be rebuilt:rH!jj!jjjjj}rI!(j]j]j]j]j]ujMkjhj]rJ!jXLIssue the following commands if the SRIO transport ever needs to be rebuilt:rK!rL!}rM!(jjH!jjF!ubaubj)rN!}rO!(jX>gmake clean >gmakerP!jj!jjjjj}rQ!(j]j]j]j]j]ujMnjhj]rR!jX>gmake clean >gmakerS!rT!}rU!(jjP!jjN!ubaubeubj)rV!}rW!(jUjKjj jjjjj}rX!(j]rY!Xrecompiling on linuxrZ!aj]j]j]r[!Urecompiling-on-linuxr\!aj]ujMrjhj]r]!(j)r^!}r_!(jXRecompiling on Linuxr`!jjV!jjjjj}ra!(j]j]j]j]j]ujMrjhj]rb!jXRecompiling on Linuxrc!rd!}re!(jj`!jj^!ubaubj )rf!}rg!(jUjjV!jjjj j}rh!(jU.j]j]j]jUj]j]jjujMtjhj]ri!(j{)rj!}rk!(jXFOpen a Linux bash terminal and navigate to /packages.jjf!jjjjj}rl!(j]j]j]j]j]ujNjhj]rm!j)rn!}ro!(jXFOpen a Linux bash terminal and navigate to /packages.rp!jjj!jjjjj}rq!(j]j]j]j]j]ujMtj]rr!jXFOpen a Linux bash terminal and navigate to /packages.rs!rt!}ru!(jjp!jjn!ubaubaubj{)rv!}rw!(jX*Run pdksetupenv.sh $ source pdksetupenv.shjjf!jjjjj}rx!(j]j]j]j]j]ujNjhj]ry!j)rz!}r{!(jX*Run pdksetupenv.sh $ source pdksetupenv.shr|!jjv!jjjjj}r}!(j]j]j]j]j]ujMvj]r~!jX*Run pdksetupenv.sh $ source pdksetupenv.shr!r!}r!(jj|!jjz!ubaubaubj{)r!}r!(jXBNavigate to /packages/ti/transport/ipc/c66/srio/r!jjf!jjjjj}r!(j]j]j]j]j]ujNjhj]r!j)r!}r!(jj!jj!jjjjj}r!(j]j]j]j]j]ujMxj]r!jXBNavigate to /packages/ti/transport/ipc/c66/srio/r!r!}r!(jj!jj!ubaubaubj{)r!}r!(jX,Build the IPC SRIO Transport library $ make jjf!jjjjj}r!(j]j]j]j]j]ujNjhj]r!j)r!}r!(jX+Build the IPC SRIO Transport library $ maker!jj!jjjjj}r!(j]j]j]j]j]ujMyj]r!jX+Build the IPC SRIO Transport library $ maker!r!}r!(jj!jj!ubaubaubeubj)r!}r!(jXLIssue the following commands if the SRIO transport ever needs to be rebuilt:r!jjV!jjjjj}r!(j]j]j]j]j]ujM|jhj]r!jXLIssue the following commands if the SRIO transport ever needs to be rebuilt:r!r!}r!(jj!jj!ubaubj)r!}r!(jX$ make clean $ maker!jjV!jjjjj}r!(j]j]j]j]j]ujMjhj]r!jX$ make clean $ maker!r!}r!(jj!jj!ubaubeubeubj)r!}r!(jUjj jjjjj}r!(j]j]j]j]r!U9arm-linux-transportsrio-source-delivery-and-recompilationr!aj]r!haujMjhj]r!(j)r!}r!(jX9ARM Linux TransportSrio Source Delivery and Recompilationr!jj!jjjjj}r!(j]j]j]j]j]ujMjhj]r!jX9ARM Linux TransportSrio Source Delivery and Recompilationr!r!}r!(jj!jj!ubaubj)r!}r!(jXThe ARM Linux TransportSrio source code can be downloaded and built two ways. The transport source code is delivered and built as part of Yocto/bitbake. The source code can also be downloaded and built directly from the GIT repository.r!jj!jjjjj}r!(j]j]j]j]j]ujMjhj]r!jXThe ARM Linux TransportSrio source code can be downloaded and built two ways. The transport source code is delivered and built as part of Yocto/bitbake. The source code can also be downloaded and built directly from the GIT repository.r!r!}r!(jj!jj!ubaubj)r!}r!(jUjKjj!jjjjj}r!(j]r!X!recompiling through yocto/bitbaker!aj]j]j]r!U!recompiling-through-yocto-bitbaker!aj]ujMjhj]r!(j)r!}r!(jX!Recompiling Through Yocto/bitbaker!jj!jjjjj}r!(j]j]j]j]j]ujMjhj]r!jX!Recompiling Through Yocto/bitbaker!r!}r!(jj!jj!ubaubj )r!}r!(jUjj!jjjj j}r!(jU.j]j]j]jUj]j]jjujMjhj]r!(j{)r!}r!(jXFollow the instructions in the Exploring section of the user guide to configure the `Yocto build environment `__. The tisdk-server-rootfs-image does not need to be built. Instead look at the section for `building other components `__jj!jjjjj}r!(j]j]j]j]j]ujNjhj]r!j)r!}r!(jXFollow the instructions in the Exploring section of the user guide to configure the `Yocto build environment `__. The tisdk-server-rootfs-image does not need to be built. Instead look at the section for `building other components `__jj!jjjjj}r!(j]j]j]j]j]ujMj]r!(jXTFollow the instructions in the Exploring section of the user guide to configure the r!r!}r!(jXTFollow the instructions in the Exploring section of the user guide to configure the jj!ubj)r!}r!(jX`Yocto build environment `__j}r!(UnameXYocto build environmentjXbhttp://software-dl.ti.com/processor-sdk-linux/esd/docs/latest/linux/Overview_Building_the_SDK.htmlj]j]j]j]j]ujj!j]r!jXYocto build environmentr!r!}r!(jUjj!ubajjubjX[. The tisdk-server-rootfs-image does not need to be built. Instead look at the section for r!r!}r!(jX[. The tisdk-server-rootfs-image does not need to be built. Instead look at the section for jj!ubj)r!}r!(jX`building other components `__j}r!(UnameXbuilding other componentsjXjhttp://software-dl.ti.com/processor-sdk-linux/esd/docs/latest/linux/Overview_Building_the_SDK.html#recipesj]j]j]j]j]ujj!j]r!jXbuilding other componentsr!r!}r!(jUjj!ubajjubeubaubj{)r!}r!(jX2Build the TransportSrio libraries, ipc-transport-srio recipe, and user-space tests, ipc-transport-srio-test recipe: $ MACHINE=k2hk-evm TOOLCHAIN_BRAND=linaro ARAGO_BRAND=mcsdk bitbake ipc-transport-srio $ MACHINE=k2hk-evm TOOLCHAIN_BRAND=linaro ARAGO_BRAND=mcsdk bitbake ipc-transport-srio-test .. note:: The initial build may take quite some time since the kernel is built as a dependency .. note:: Building with just the ipc-transport-srio-test recipe will also build the ipc-transport-srio recipe since the test recipe depends on the library recipe. jj!jNjjj}r!(j]j]j]j]j]ujNjhj]r!(j)r!}r!(jX&Build the TransportSrio libraries, ipc-transport-srio recipe, and user-space tests, ipc-transport-srio-test recipe: $ MACHINE=k2hk-evm TOOLCHAIN_BRAND=linaro ARAGO_BRAND=mcsdk bitbake ipc-transport-srio $ MACHINE=k2hk-evm TOOLCHAIN_BRAND=linaro ARAGO_BRAND=mcsdk bitbake ipc-transport-srio-testr!jj!jjjjj}r!(j]j]j]j]j]ujMj]r!jX&Build the TransportSrio libraries, ipc-transport-srio recipe, and user-space tests, ipc-transport-srio-test recipe: $ MACHINE=k2hk-evm TOOLCHAIN_BRAND=linaro ARAGO_BRAND=mcsdk bitbake ipc-transport-srio $ MACHINE=k2hk-evm TOOLCHAIN_BRAND=linaro ARAGO_BRAND=mcsdk bitbake ipc-transport-srio-testr!r!}r!(jj!jj!ubaubj)r!}r!(jXTThe initial build may take quite some time since the kernel is built as a dependencyr!j}r"(j]j]j]j]j]ujj!j]r"j)r"}r"(jj!jj!jjjjj}r"(j]j]j]j]j]ujMj]r"jXTThe initial build may take quite some time since the kernel is built as a dependencyr"r"}r"(jj!jj"ubaubajjubj)r "}r "(jXBuilding with just the ipc-transport-srio-test recipe will also build the ipc-transport-srio recipe since the test recipe depends on the library recipe.j}r "(j]j]j]j]j]ujj!j]r "j)r "}r"(jXBuilding with just the ipc-transport-srio-test recipe will also build the ipc-transport-srio recipe since the test recipe depends on the library recipe.r"jj "jjjjj}r"(j]j]j]j]j]ujMj]r"jXBuilding with just the ipc-transport-srio-test recipe will also build the ipc-transport-srio recipe since the test recipe depends on the library recipe.r"r"}r"(jj"jj "ubaubajjubeubj{)r"}r"(jX4The built TransportSrio static library will be located in /oe-layersetup/build/arago-tmp-external-linaro-toolchain/work/cortexa15hf-vfp-neon-3.8-oe-linux-gnueabi/ipc-transport-srio//packages-split/ipc-transport-srio-staticdev/usr/lib/libTransportSrio.a The built TransportSrio shared library will be located in /oe-layersetup/build/arago-tmp-external-linaro-toolchain/work/cortexa15hf-vfp-neon-3.8-oe-linux-gnueabi/ipc-transport-srio//packages-split/ipc-transport-srio/usr/lib/libTransportSrio.so.1.0.0jj!jjjjj}r"(j]j]j]j]j]ujNjhj]r"j)r"}r"(jX4The built TransportSrio static library will be located in /oe-layersetup/build/arago-tmp-external-linaro-toolchain/work/cortexa15hf-vfp-neon-3.8-oe-linux-gnueabi/ipc-transport-srio//packages-split/ipc-transport-srio-staticdev/usr/lib/libTransportSrio.a The built TransportSrio shared library will be located in /oe-layersetup/build/arago-tmp-external-linaro-toolchain/work/cortexa15hf-vfp-neon-3.8-oe-linux-gnueabi/ipc-transport-srio//packages-split/ipc-transport-srio/usr/lib/libTransportSrio.so.1.0.0r"jj"jjjjj}r"(j]j]j]j]j]ujMj]r"jX4The built TransportSrio static library will be located in /oe-layersetup/build/arago-tmp-external-linaro-toolchain/work/cortexa15hf-vfp-neon-3.8-oe-linux-gnueabi/ipc-transport-srio//packages-split/ipc-transport-srio-staticdev/usr/lib/libTransportSrio.a The built TransportSrio shared library will be located in /oe-layersetup/build/arago-tmp-external-linaro-toolchain/work/cortexa15hf-vfp-neon-3.8-oe-linux-gnueabi/ipc-transport-srio//packages-split/ipc-transport-srio/usr/lib/libTransportSrio.so.1.0.0r"r"}r "(jj"jj"ubaubaubj{)r!"}r""(jXfThe ipc-transport-srio-test recipe will build test static and shared library executables for all supported devices. The executables will be located in base_path>/oe-layersetup/build/arago-tmp-external-linaro-toolchain/work/cortexa15hf-vfp-neon-3.8-oe-linux-gnueabi/ipc-transport-srio-test//packages-split/ipc-transport-srio-test/usr/bin/ jj!jjjjj}r#"(j]j]j]j]j]ujNjhj]r$"j)r%"}r&"(jXeThe ipc-transport-srio-test recipe will build test static and shared library executables for all supported devices. The executables will be located in base_path>/oe-layersetup/build/arago-tmp-external-linaro-toolchain/work/cortexa15hf-vfp-neon-3.8-oe-linux-gnueabi/ipc-transport-srio-test//packages-split/ipc-transport-srio-test/usr/bin/r'"jj!"jjjjj}r("(j]j]j]j]j]ujMj]r)"jXeThe ipc-transport-srio-test recipe will build test static and shared library executables for all supported devices. The executables will be located in base_path>/oe-layersetup/build/arago-tmp-external-linaro-toolchain/work/cortexa15hf-vfp-neon-3.8-oe-linux-gnueabi/ipc-transport-srio-test//packages-split/ipc-transport-srio-test/usr/bin/r*"r+"}r,"(jj'"jj%"ubaubaubeubeubj)r-"}r."(jUjKjj!jjjjj}r/"(j]r0"X"recompiling through git repositoryr1"aj]j]j]r2"U"recompiling-through-git-repositoryr3"aj]ujMjhj]r4"(j)r5"}r6"(jX"Recompiling Through GIT Repositoryr7"jj-"jjjjj}r8"(j]j]j]j]j]ujMjhj]r9"jX"Recompiling Through GIT Repositoryr:"r;"}r<"(jj7"jj5"ubaubj)r="}r>"(jX4Recompiling through the ARM Linux TransportSrio GIT repository requires that the latest PROCSDK Linux installation. The PROCSDK Linux PDK component and the Linux devkit must be installed. The Linux devkit installation script can be found in /procsdk_linux_3_XX_YY_ZZ/linux-devkit/r?"jj-"jjjjj}r@"(j]j]j]j]j]ujMjhj]rA"jX4Recompiling through the ARM Linux TransportSrio GIT repository requires that the latest PROCSDK Linux installation. The PROCSDK Linux PDK component and the Linux devkit must be installed. The Linux devkit installation script can be found in /procsdk_linux_3_XX_YY_ZZ/linux-devkit/rB"rC"}rD"(jj?"jj="ubaubj )rE"}rF"(jUjj-"jjjj j}rG"(jU.j]j]j]jUj]j]jjujMjhj]rH"(j{)rI"}rJ"(jXClone the keystone-linux/ipc-transport repository from git.ti.com $ git clone git://git.ti.com/keystone-linux/ipc-transport.gitjjE"jjjjj}rK"(j]j]j]j]j]ujNjhj]rL"j)rM"}rN"(jXClone the keystone-linux/ipc-transport repository from git.ti.com $ git clone git://git.ti.com/keystone-linux/ipc-transport.gitrO"jjI"jjjjj}rP"(j]j]j]j]j]ujMj]rQ"jXClone the keystone-linux/ipc-transport repository from git.ti.com $ git clone git://git.ti.com/keystone-linux/ipc-transport.gitrR"rS"}rT"(jjO"jjM"ubaubaubj{)rU"}rV"(jXNavigate to the PROCSDK Linux installation of pdk_3_XX_YY_ZZ/packages and source armv7setupenv.sh. .. note:: The armv7setupenv.sh script must be modified to point to the linaro toolchain and installed devkit path $ source armv7setupenv.sh jjE"jNjjj}rW"(j]j]j]j]j]ujNjhj]rX"(j)rY"}rZ"(jXbNavigate to the PROCSDK Linux installation of pdk_3_XX_YY_ZZ/packages and source armv7setupenv.sh.r["jjU"jjjjj}r\"(j]j]j]j]j]ujMj]r]"jXbNavigate to the PROCSDK Linux installation of pdk_3_XX_YY_ZZ/packages and source armv7setupenv.sh.r^"r_"}r`"(jj["jjY"ubaubj)ra"}rb"(jXThe armv7setupenv.sh script must be modified to point to the linaro toolchain and installed devkit path $ source armv7setupenv.shj}rc"(j]j]j]j]j]ujjU"j]rd"(j)re"}rf"(jXgThe armv7setupenv.sh script must be modified to point to the linaro toolchain and installed devkit pathrg"jja"jjjjj}rh"(j]j]j]j]j]ujMj]ri"jXgThe armv7setupenv.sh script must be modified to point to the linaro toolchain and installed devkit pathrj"rk"}rl"(jjg"jje"ubaubj)rm"}rn"(jX$ source armv7setupenv.shro"jja"jjjjj}rp"(j]j]j]j]j]ujMj]rq"jX$ source armv7setupenv.shrr"rs"}rt"(jjo"jjm"ubaubejjubeubj{)ru"}rv"(jXNavigate back to the SRIO transport directory in the ipc-transport GIT repository $ cd /ipc-transport/linus/sriojjE"jjjjj}rw"(j]j]j]j]j]ujNjhj]rx"j)ry"}rz"(jXNavigate back to the SRIO transport directory in the ipc-transport GIT repository $ cd /ipc-transport/linus/srior{"jju"jjjjj}r|"(j]j]j]j]j]ujMj]r}"jXNavigate back to the SRIO transport directory in the ipc-transport GIT repository $ cd /ipc-transport/linus/srior~"r"}r"(jj{"jjy"ubaubaubj{)r"}r"(jXXBuild the TransportSrio library and user-space test executables: $ make lib $ make testsjjE"jjjjj}r"(j]j]j]j]j]ujNjhj]r"j)r"}r"(jXXBuild the TransportSrio library and user-space test executables: $ make lib $ make testsr"jj"jjjjj}r"(j]j]j]j]j]ujMj]r"jXXBuild the TransportSrio library and user-space test executables: $ make lib $ make testsr"r"}r"(jj"jj"ubaubaubj{)r"}r"(jXThe TransportSrio static and shared libraries will be copied directly into the Linux devkit's /usr/lib folder as long as the devkit install path was setup correctly prior to running the armv7setupenv.sh scriptjjE"jjjjj}r"(j]j]j]j]j]ujNjhj]r"j)r"}r"(jXThe TransportSrio static and shared libraries will be copied directly into the Linux devkit's /usr/lib folder as long as the devkit install path was setup correctly prior to running the armv7setupenv.sh scriptr"jj"jjjjj}r"(j]j]j]j]j]ujMj]r"jXThe TransportSrio static and shared libraries will be copied directly into the Linux devkit's /usr/lib folder as long as the devkit install path was setup correctly prior to running the armv7setupenv.sh scriptr"r"}r"(jj"jj"ubaubaubj{)r"}r"(jXThe test executables will be generated in the /ipc-transport/bin//test/ folder. Only the device specified in the armv7setupenv.sh will be built. jjE"jjjjj}r"(j]j]j]j]j]ujNjhj]r"j)r"}r"(jXThe test executables will be generated in the /ipc-transport/bin//test/ folder. Only the device specified in the armv7setupenv.sh will be built.r"jj"jjjjj}r"(j]j]j]j]j]ujMj]r"jXThe test executables will be generated in the /ipc-transport/bin//test/ folder. Only the device specified in the armv7setupenv.sh will be built.r"r"}r"(jj"jj"ubaubaubeubj)r"}r"(jXSetting the USEDYNAMIC_LIB environment variable to "yes" will generate the shared library test executables $ export USEDYNAMIC_LIB=yesjj-"jjjjj}r"(j]j]j]j]j]ujNjhj]r"(j)r"}r"(jXjSetting the USEDYNAMIC_LIB environment variable to "yes" will generate the shared library test executablesr"jj"jjjjj}r"(j]j]j]j]j]ujMj]r"jXjSetting the USEDYNAMIC_LIB environment variable to "yes" will generate the shared library test executablesr"r"}r"(jj"jj"ubaubj)r"}r"(jX$ export USEDYNAMIC_LIB=yesr"jj"jjjjj}r"(j]j]j]j]j]ujMj]r"jX$ export USEDYNAMIC_LIB=yesr"r"}r"(jj"jj"ubaubeubeubeubj)r"}r"(jUjj jjjjj}r"(j]j]j]j]r"U/packages.jj"jjjjj}r"(j]j]j]j]j]ujNjhj]r"j)r"}r"(jXKOpen a Windows command terminal and navigate to /packages.r"jj"jjjjj}r"(j]j]j]j]j]ujMj]r"jXKOpen a Windows command terminal and navigate to /packages.r"r"}r"(jj"jj"ubaubaubj{)r"}r"(jX$Run pdksetupenv.bat >pdksetupenv.batjj"jjjjj}r"(j]j]j]j]j]ujNjhj]r"j)r"}r"(jX$Run pdksetupenv.bat >pdksetupenv.batr"jj"jjjjj}r"(j]j]j]j]j]ujMj]r"jX$Run pdksetupenv.bat >pdksetupenv.batr"r"}r"(jj"jj"ubaubaubj{)r"}r"(jXBNavigate to /packages/ti/transport/ipc/c66/qmss/r"jj"jjjjj}r"(j]j]j]j]j]ujNjhj]r"j)r#}r#(jj"jj"jjjjj}r#(j]j]j]j]j]ujMj]r#jXBNavigate to /packages/ti/transport/ipc/c66/qmss/r#r#}r#(jj"jj#ubaubaubj{)r#}r#(jX,Build the IPC QMSS Transport library >gmake jj"jjjjj}r #(j]j]j]j]j]ujNjhj]r #j)r #}r #(jX+Build the IPC QMSS Transport library >gmaker #jj#jjjjj}r#(j]j]j]j]j]ujMj]r#jX+Build the IPC QMSS Transport library >gmaker#r#}r#(jj #jj #ubaubaubeubj)r#}r#(jXLIssue the following commands if the QMSS transport ever needs to be rebuilt:r#jj"jjjjj}r#(j]j]j]j]j]ujMjhj]r#jXLIssue the following commands if the QMSS transport ever needs to be rebuilt:r#r#}r#(jj#jj#ubaubj)r#}r#(jX>gmake clean >gmaker#jj"jjjjj}r#(j]j]j]j]j]ujMjhj]r#jX>gmake clean >gmaker #r!#}r"#(jj#jj#ubaubeubj)r##}r$#(jUjKjj"jjjjj}r%#(j]r&#jZ!aj]j]j]r'#Uid23r(#aj]ujMjhj]r)#(j)r*#}r+#(jXRecompiling on Linuxr,#jj##jjjjj}r-#(j]j]j]j]j]ujMjhj]r.#jXRecompiling on Linuxr/#r0#}r1#(jj,#jj*#ubaubj )r2#}r3#(jUjj##jjjj j}r4#(jU.j]j]j]jUj]j]jjujMjhj]r5#(j{)r6#}r7#(jXFOpen a Linux bash terminal and navigate to /packages.jj2#jjjjj}r8#(j]j]j]j]j]ujNjhj]r9#j)r:#}r;#(jXFOpen a Linux bash terminal and navigate to /packages.r<#jj6#jjjjj}r=#(j]j]j]j]j]ujMj]r>#jXFOpen a Linux bash terminal and navigate to /packages.r?#r@#}rA#(jj<#jj:#ubaubaubj{)rB#}rC#(jX*Run pdksetupenv.sh $ source pdksetupenv.shjj2#jjjjj}rD#(j]j]j]j]j]ujNjhj]rE#j)rF#}rG#(jX*Run pdksetupenv.sh $ source pdksetupenv.shrH#jjB#jjjjj}rI#(j]j]j]j]j]ujMj]rJ#jX*Run pdksetupenv.sh $ source pdksetupenv.shrK#rL#}rM#(jjH#jjF#ubaubaubj{)rN#}rO#(jXBNavigate to /packages/ti/transport/ipc/c66/qmss/rP#jj2#jjjjj}rQ#(j]j]j]j]j]ujNjhj]rR#j)rS#}rT#(jjP#jjN#jjjjj}rU#(j]j]j]j]j]ujMj]rV#jXBNavigate to /packages/ti/transport/ipc/c66/qmss/rW#rX#}rY#(jjP#jjS#ubaubaubj{)rZ#}r[#(jX,Build the IPC QMSS Transport library $ make jj2#jjjjj}r\#(j]j]j]j]j]ujNjhj]r]#j)r^#}r_#(jX+Build the IPC QMSS Transport library $ maker`#jjZ#jjjjj}ra#(j]j]j]j]j]ujMj]rb#jX+Build the IPC QMSS Transport library $ makerc#rd#}re#(jj`#jj^#ubaubaubeubj)rf#}rg#(jXLIssue the following commands if the QMSS transport ever needs to be rebuilt:rh#jj##jjjjj}ri#(j]j]j]j]j]ujMjhj]rj#jXLIssue the following commands if the QMSS transport ever needs to be rebuilt:rk#rl#}rm#(jjh#jjf#ubaubj)rn#}ro#(jX$ make clean $ makerp#jj##jjjjj}rq#(j]j]j]j]j]ujMjhj]rr#jX$ make clean $ makers#rt#}ru#(jjp#jjn#ubaubeubeubj)rv#}rw#(jUjj jjjjj}rx#(j]j]j]j]ry#U9arm-linux-transportqmss-source-delivery-and-recompilationrz#aj]r{#haujMjhj]r|#(j)r}#}r~#(jX9ARM Linux TransportQmss Source Delivery and Recompilationr#jjv#jjjjj}r#(j]j]j]j]j]ujMjhj]r#jX9ARM Linux TransportQmss Source Delivery and Recompilationr#r#}r#(jj#jj}#ubaubj)r#}r#(jXThe ARM Linux TransportQmss source code can be downloaded and built two ways. The transport source code is delivered and built as part of Yocto/bitbake. The source code can also be downloaded and built directly from the GIT repository.r#jjv#jjjjj}r#(j]j]j]j]j]ujMjhj]r#jXThe ARM Linux TransportQmss source code can be downloaded and built two ways. The transport source code is delivered and built as part of Yocto/bitbake. The source code can also be downloaded and built directly from the GIT repository.r#r#}r#(jj#jj#ubaubj)r#}r#(jUjKjjv#jjjjj}r#(j]r#j!aj]j]j]r#Uid24r#aj]ujMjhj]r#(j)r#}r#(jX!Recompiling Through Yocto/bitbaker#jj#jjjjj}r#(j]j]j]j]j]ujMjhj]r#jX!Recompiling Through Yocto/bitbaker#r#}r#(jj#jj#ubaubj )r#}r#(jUjj#jjjj j}r#(jU.j]j]j]jUj]j]jjujMjhj]r#(j{)r#}r#(jXFollow the instructions in the Exploring section of the user guide to configure the `Yocto build environment `__. The tisdk-server-rootfs-image does not need to be built. Instead look at the section for `building other components `__jj#jjjjj}r#(j]j]j]j]j]ujNjhj]r#j)r#}r#(jXFollow the instructions in the Exploring section of the user guide to configure the `Yocto build environment `__. The tisdk-server-rootfs-image does not need to be built. Instead look at the section for `building other components `__jj#jjjjj}r#(j]j]j]j]j]ujMj]r#(jXTFollow the instructions in the Exploring section of the user guide to configure the r#r#}r#(jXTFollow the instructions in the Exploring section of the user guide to configure the jj#ubj)r#}r#(jXf`Yocto build environment `__j}r#(UnameXYocto build environmentjXHhttp://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Exploring#Yoctoj]j]j]j]j]ujj#j]r#jXYocto build environmentr#r#}r#(jUjj#ubajjubjX[. The tisdk-server-rootfs-image does not need to be built. Instead look at the section for r#r#}r#(jX[. The tisdk-server-rootfs-image does not need to be built. Instead look at the section for jj#ubj)r#}r#(jX`building other components `__j}r#(UnameXbuilding other componentsjXehttp://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Exploring#Building_other_components_in_Yoctoj]j]j]j]j]ujj#j]r#jXbuilding other componentsr#r#}r#(jUjj#ubajjubeubaubj{)r#}r#(jX5Build the TransportQmss libraries, ipc-transport-qmss recipe, and user-space tests, ipc-transport-qmss-test recipe: $ MACHINE=k2hk-evm TOOLCHAIN_BRAND=linaro ARAGO_BRAND=mcsdk bitbake ipc-transport-qmss $ MACHINE=k2hk-evm TOOLCHAIN_BRAND=linaro ARAGO_BRAND=mcsdk bitbake ipc-transport-qmss-test .. note:: The initial build may take quite some time since the kernel is built as a dependency .. note:: Building with just the ipc-transport-qmss-test recipe will also build the ipc-transport-qmss recipe since the test recipe depends on the library recipe. jj#jNjjj}r#(j]j]j]j]j]ujNjhj]r#(j)r#}r#(jX&Build the TransportQmss libraries, ipc-transport-qmss recipe, and user-space tests, ipc-transport-qmss-test recipe: $ MACHINE=k2hk-evm TOOLCHAIN_BRAND=linaro ARAGO_BRAND=mcsdk bitbake ipc-transport-qmss $ MACHINE=k2hk-evm TOOLCHAIN_BRAND=linaro ARAGO_BRAND=mcsdk bitbake ipc-transport-qmss-testr#jj#jjjjj}r#(j]j]j]j]j]ujMj]r#jX&Build the TransportQmss libraries, ipc-transport-qmss recipe, and user-space tests, ipc-transport-qmss-test recipe: $ MACHINE=k2hk-evm TOOLCHAIN_BRAND=linaro ARAGO_BRAND=mcsdk bitbake ipc-transport-qmss $ MACHINE=k2hk-evm TOOLCHAIN_BRAND=linaro ARAGO_BRAND=mcsdk bitbake ipc-transport-qmss-testr#r#}r#(jj#jj#ubaubj)r#}r#(jXTThe initial build may take quite some time since the kernel is built as a dependencyj}r#(j]j]j]j]j]ujj#j]r#j)r#}r#(jXTThe initial build may take quite some time since the kernel is built as a dependencyr#jj#jjjjj}r#(j]j]j]j]j]ujMj]r#jXTThe initial build may take quite some time since the kernel is built as a dependencyr#r#}r#(jj#jj#ubaubajjubj)r#}r#(jXBuilding with just the ipc-transport-qmss-test recipe will also build the ipc-transport-qmss recipe since the test recipe depends on the library recipe.j}r#(j]j]j]j]j]ujj#j]r#j)r#}r#(jXBuilding with just the ipc-transport-qmss-test recipe will also build the ipc-transport-qmss recipe since the test recipe depends on the library recipe.r#jj#jjjjj}r#(j]j]j]j]j]ujMj]r#jXBuilding with just the ipc-transport-qmss-test recipe will also build the ipc-transport-qmss recipe since the test recipe depends on the library recipe.r#r#}r#(jj#jj#ubaubajjubeubj{)r#}r#(jX4The built TransportQmss static library will be located in /oe-layersetup/build/arago-tmp-external-linaro-toolchain/work/cortexa15hf-vfp-neon-3.8-oe-linux-gnueabi/ipc-transport-qmss//packages-split/ipc-transport-qmss-staticdev/usr/lib/libTransportQmss.a The built TransportQmss shared library will be located in /oe-layersetup/build/arago-tmp-external-linaro-toolchain/work/cortexa15hf-vfp-neon-3.8-oe-linux-gnueabi/ipc-transport-qmss//packages-split/ipc-transport-qmss/usr/lib/libTransportQmss.so.1.0.0jj#jjjjj}r#(j]j]j]j]j]ujNjhj]r#j)r#}r#(jX4The built TransportQmss static library will be located in /oe-layersetup/build/arago-tmp-external-linaro-toolchain/work/cortexa15hf-vfp-neon-3.8-oe-linux-gnueabi/ipc-transport-qmss//packages-split/ipc-transport-qmss-staticdev/usr/lib/libTransportQmss.a The built TransportQmss shared library will be located in /oe-layersetup/build/arago-tmp-external-linaro-toolchain/work/cortexa15hf-vfp-neon-3.8-oe-linux-gnueabi/ipc-transport-qmss//packages-split/ipc-transport-qmss/usr/lib/libTransportQmss.so.1.0.0r#jj#jjjjj}r#(j]j]j]j]j]ujMj]r#jX4The built TransportQmss static library will be located in /oe-layersetup/build/arago-tmp-external-linaro-toolchain/work/cortexa15hf-vfp-neon-3.8-oe-linux-gnueabi/ipc-transport-qmss//packages-split/ipc-transport-qmss-staticdev/usr/lib/libTransportQmss.a The built TransportQmss shared library will be located in /oe-layersetup/build/arago-tmp-external-linaro-toolchain/work/cortexa15hf-vfp-neon-3.8-oe-linux-gnueabi/ipc-transport-qmss//packages-split/ipc-transport-qmss/usr/lib/libTransportQmss.so.1.0.0r#r#}r#(jj#jj#ubaubaubj{)r#}r#(jXfThe ipc-transport-qmss-test recipe will build test static and shared library executables for all supported devices. The executables will be located in base_path>/oe-layersetup/build/arago-tmp-external-linaro-toolchain/work/cortexa15hf-vfp-neon-3.8-oe-linux-gnueabi/ipc-transport-qmss-test//packages-split/ipc-transport-qmss-test/usr/bin/ jj#jjjjj}r#(j]j]j]j]j]ujNjhj]r#j)r#}r#(jXeThe ipc-transport-qmss-test recipe will build test static and shared library executables for all supported devices. The executables will be located in base_path>/oe-layersetup/build/arago-tmp-external-linaro-toolchain/work/cortexa15hf-vfp-neon-3.8-oe-linux-gnueabi/ipc-transport-qmss-test//packages-split/ipc-transport-qmss-test/usr/bin/r#jj#jjjjj}r#(j]j]j]j]j]ujM"j]r#jXeThe ipc-transport-qmss-test recipe will build test static and shared library executables for all supported devices. The executables will be located in base_path>/oe-layersetup/build/arago-tmp-external-linaro-toolchain/work/cortexa15hf-vfp-neon-3.8-oe-linux-gnueabi/ipc-transport-qmss-test//packages-split/ipc-transport-qmss-test/usr/bin/r#r#}r#(jj#jj#ubaubaubeubeubj)r#}r#(jUjKjjv#jjjjj}r#(j]r#j1"aj]j]j]r#Uid25r#aj]ujM(jhj]r#(j)r#}r$(jX"Recompiling Through GIT Repositoryr$jj#jjjjj}r$(j]j]j]j]j]ujM(jhj]r$jX"Recompiling Through GIT Repositoryr$r$}r$(jj$jj#ubaubj)r$}r$(jX<Recompiling through the ARMv7 Linux TransportQmss GIT repository requires that the latest PROCSDK Linux installation. The PROCSDK Linux PDK component and the Linux devkit must be installed. The Linux devkit installation script can be found in /processor_sdk_linux_3_XX_YY_ZZ/linux-devkit/r $jj#jjjjj}r $(j]j]j]j]j]ujM*jhj]r $jX<Recompiling through the ARMv7 Linux TransportQmss GIT repository requires that the latest PROCSDK Linux installation. The PROCSDK Linux PDK component and the Linux devkit must be installed. The Linux devkit installation script can be found in /processor_sdk_linux_3_XX_YY_ZZ/linux-devkit/r $r $}r$(jj $jj$ubaubj )r$}r$(jUjj#jjjj j}r$(jU.j]j]j]jUj]j]jjujM0jhj]r$(j{)r$}r$(jXClone the keystone-linux/ipc-transport repository from git.ti.com $ git clone git://git.ti.com/keystone-linux/ipc-transport.gitjj$jjjjj}r$(j]j]j]j]j]ujNjhj]r$j)r$}r$(jXClone the keystone-linux/ipc-transport repository from git.ti.com $ git clone git://git.ti.com/keystone-linux/ipc-transport.gitr$jj$jjjjj}r$(j]j]j]j]j]ujM0j]r$jXClone the keystone-linux/ipc-transport repository from git.ti.com $ git clone git://git.ti.com/keystone-linux/ipc-transport.gitr$r$}r$(jj$jj$ubaubaubj{)r$}r $(jXNavigate to the PROCSDK Linux installation of pdk_3_XX_YY_ZZ/packages and source armv7setupenv.sh. .. note:: The armv7setupenv.sh script must be modified build for the correct K2 device, and to point to the linaro toolchain and installed devkit path $ source armv7setupenv.sh jj$jNjjj}r!$(j]j]j]j]j]ujNjhj]r"$(j)r#$}r$$(jXbNavigate to the PROCSDK Linux installation of pdk_3_XX_YY_ZZ/packages and source armv7setupenv.sh.r%$jj$jjjjj}r&$(j]j]j]j]j]ujM2j]r'$jXbNavigate to the PROCSDK Linux installation of pdk_3_XX_YY_ZZ/packages and source armv7setupenv.sh.r($r)$}r*$(jj%$jj#$ubaubj)r+$}r,$(jXThe armv7setupenv.sh script must be modified build for the correct K2 device, and to point to the linaro toolchain and installed devkit path $ source armv7setupenv.shj}r-$(j]j]j]j]j]ujj$j]r.$(j)r/$}r0$(jXThe armv7setupenv.sh script must be modified build for the correct K2 device, and to point to the linaro toolchain and installed devkit pathr1$jj+$jjjjj}r2$(j]j]j]j]j]ujM6j]r3$jXThe armv7setupenv.sh script must be modified build for the correct K2 device, and to point to the linaro toolchain and installed devkit pathr4$r5$}r6$(jj1$jj/$ubaubj)r7$}r8$(jX$ source armv7setupenv.shr9$jj+$jjjjj}r:$(j]j]j]j]j]ujM:j]r;$jX$ source armv7setupenv.shr<$r=$}r>$(jj9$jj7$ubaubejjubeubj{)r?$}r@$(jXNavigate back to the QMSS transport directory in the ipc-transport GIT repository $ cd /ipc-transport/linus/qmssjj$jjjjj}rA$(j]j]j]j]j]ujNjhj]rB$j)rC$}rD$(jXNavigate back to the QMSS transport directory in the ipc-transport GIT repository $ cd /ipc-transport/linus/qmssrE$jj?$jjjjj}rF$(j]j]j]j]j]ujM<j]rG$jXNavigate back to the QMSS transport directory in the ipc-transport GIT repository $ cd /ipc-transport/linus/qmssrH$rI$}rJ$(jjE$jjC$ubaubaubj{)rK$}rL$(jXXBuild the TransportQmss library and user-space test executables: $ make lib $ make testsjj$jjjjj}rM$(j]j]j]j]j]ujNjhj]rN$j)rO$}rP$(jXXBuild the TransportQmss library and user-space test executables: $ make lib $ make testsrQ$jjK$jjjjj}rR$(j]j]j]j]j]ujM?j]rS$jXXBuild the TransportQmss library and user-space test executables: $ make lib $ make testsrT$rU$}rV$(jjQ$jjO$ubaubaubj{)rW$}rX$(jXThe TransportQmss static and shared libraries will be copied directly into the Linux devkit's /usr/lib folder as long as the devkit install path was setup correctly prior to running the armv7setupenv.sh scriptjj$jjjjj}rY$(j]j]j]j]j]ujNjhj]rZ$j)r[$}r\$(jXThe TransportQmss static and shared libraries will be copied directly into the Linux devkit's /usr/lib folder as long as the devkit install path was setup correctly prior to running the armv7setupenv.sh scriptr]$jjW$jjjjj}r^$(j]j]j]j]j]ujMBj]r_$jXThe TransportQmss static and shared libraries will be copied directly into the Linux devkit's /usr/lib folder as long as the devkit install path was setup correctly prior to running the armv7setupenv.sh scriptr`$ra$}rb$(jj]$jj[$ubaubaubj{)rc$}rd$(jXThe test executables will be generated in the /ipc-transport/bin//test/ folder. Only the device specified in the armv7setupenv.sh will be built. jj$jjjjj}re$(j]j]j]j]j]ujNjhj]rf$j)rg$}rh$(jXThe test executables will be generated in the /ipc-transport/bin//test/ folder. Only the device specified in the armv7setupenv.sh will be built.ri$jjc$jjjjj}rj$(j]j]j]j]j]ujMEj]rk$jXThe test executables will be generated in the /ipc-transport/bin//test/ folder. Only the device specified in the armv7setupenv.sh will be built.rl$rm$}rn$(jji$jjg$ubaubaubeubj)ro$}rp$(jXSetting the USEDYNAMIC_LIB environment variable to "yes" will generate the shared library test executables $ export USEDYNAMIC_LIB=yesjj#jjjjj}rq$(j]j]j]j]j]ujNjhj]rr$(j)rs$}rt$(jXjSetting the USEDYNAMIC_LIB environment variable to "yes" will generate the shared library test executablesru$jjo$jjjjj}rv$(j]j]j]j]j]ujMJj]rw$jXjSetting the USEDYNAMIC_LIB environment variable to "yes" will generate the shared library test executablesrx$ry$}rz$(jju$jjs$ubaubj3)r{$}r|$(jUj}r}$(j]j]j]j]j]ujjo$j]r~$j)r$}r$(jX$ export USEDYNAMIC_LIB=yesr$jj{$jjjjj}r$(j]j]j]j]j]ujMMj]r$jX$ export USEDYNAMIC_LIB=yesr$r$}r$(jj$jj$ubaubajj6ubeubeubeubeubj)r$}r$(jUjjjjjjj}r$(j]j]j]j]r$Utests-examplesr$aj]r$h aujMPjhj]r$(j)r$}r$(jXTests & Examplesr$jj$jjjjj}r$(j]j]j]j]j]ujMPjhj]r$jXTests & Examplesr$r$}r$(jj$jj$ubaubj)r$}r$(jUjKjj$jjjjj}r$(j]r$Xsys/bios dsp transportsrior$aj]j]j]r$Uid26r$aj]ujMSjhj]r$(j)r$}r$(jXSYS/BIOS DSP TransportSrior$jj$jjjjj}r$(j]j]j]j]j]ujMSjhj]r$jXSYS/BIOS DSP TransportSrior$r$}r$(jj$jj$ubaubjy )r$}r$(jUjj$jjjj j}r$(j]j]j]j]j]ujNjhj]r$j~ )r$}r$(jUj}r$(j]j]j]j]j]UcolsKujj$j]r$(j )r$}r$(jUj}r$(j]j]j]j]j]UcolwidthKujj$j]jj ubj )r$}r$(jUj}r$(j]j]j]j]j]UcolwidthKujj$j]jj ubj )r$}r$(jUj}r$(j]j]j]j]j]UcolwidthKujj$j]jj ubj )r$}r$(jUj}r$(j]j]j]j]j]ujj$j]r$j )r$}r$(jUj}r$(j]j]j]j]j]ujj$j]r$(j )r$}r$(jUj}r$(j]j]j]j]j]ujj$j]r$j)r$}r$(jXNamer$jj$jjjjj}r$(j]j]j]j]j]ujMVj]r$jXNamer$r$}r$(jj$jj$ubaubajj ubj )r$}r$(jUj}r$(j]j]j]j]j]ujj$j]r$j)r$}r$(jX Descriptionr$jj$jjjjj}r$(j]j]j]j]j]ujMVj]r$jX Descriptionr$r$}r$(jj$jj$ubaubajj ubj )r$}r$(jUj}r$(j]j]j]j]j]ujj$j]r$j)r$}r$(jXExpected Resultsr$jj$jjjjj}r$(j]j]j]j]j]ujMVj]r$jXExpected Resultsr$r$}r$(jj$jj$ubaubajj ubejj ubajj ubj )r$}r$(jUj}r$(j]j]j]j]j]ujj$j]r$(j )r$}r$(jUj}r$(j]j]j]j]j]ujj$j]r$(j )r$}r$(jUj}r$(j]j]j]j]j]ujj$j]r$j)r$}r$(jX,SYS/BIOS DSP TransportSrio Benchmark Exampler$jj$jjjjj}r$(j]j]j]j]j]ujMXj]r$jX,SYS/BIOS DSP TransportSrio Benchmark Exampler$r$}r$(jj$jj$ubaubajj ubj )r$}r$(jUj}r$(j]j]j]j]j]ujj$j]r$jc)r$}r$(jUj}r$(j]j]j]j]j]ujj$j]r$ji)r$}r%(jX Example demonstrating intra-SoC, DSP to DSP, transport over SRIO use while also measuring latency and throughput performance. The example consists of multiple iterations where each iteration runs SRIO with different lane configurations. Reference example for developersr%jlKjj$jjjjj}r%(j]j]j]j]j]ujKj]r%jX Example demonstrating intra-SoC, DSP to DSP, transport over SRIO use while also measuring latency and throughput performance. The example consists of multiple iterations where each iteration runs SRIO with different lane configurations. Reference example for developersr%r%}r%(jj%jj$ubaubajjfubajj ubj )r%}r%(jUj}r %(j]j]j]j]j]ujj$j]r %jc)r %}r %(jUj}r %(j]j]j]j]j]ujj%j]r%ji)r%}r%(jXBSuccessful completion on two DSP cores for all example iterations.r%jlKjj %jjjjj}r%(j]j]j]j]j]ujKj]r%jXBSuccessful completion on two DSP cores for all example iterations.r%r%}r%(jj%jj%ubaubajjfubajj ubejj ubj )r%}r%(jUj}r%(j]j]j]j]j]ujj$j]r%(j )r%}r%(jUj}r%(j]j]j]j]j]ujj%j]r%j)r%}r %(jX4SYS/BIOS DSP TransportSrio Producer/Consumer Exampler!%jj%jjjjj}r"%(j]j]j]j]j]ujMij]r#%jX4SYS/BIOS DSP TransportSrio Producer/Consumer Exampler$%r%%}r&%(jj!%jj%ubaubajj ubj )r'%}r(%(jUj}r)%(j]j]j]j]j]ujj%j]r*%jc)r+%}r,%(jUj}r-%(j]j]j]j]j]ujj'%j]r.%ji)r/%}r0%(jXExample demonstrates inter-SoC, DSP to DSP, transport over SRIO. The example consists of multiple iterations where each iteration runs SRIO with different lane configurations.r1%jlKjj+%jjjjj}r2%(j]j]j]j]j]ujKj]r3%jXExample demonstrates inter-SoC, DSP to DSP, transport over SRIO. The example consists of multiple iterations where each iteration runs SRIO with different lane configurations.r4%r5%}r6%(jj1%jj/%ubaubajjfubajj ubj )r7%}r8%(jUj}r9%(j]j]j]j]j]ujj%j]r:%j)r;%}r<%(jXdSuccessful completion for all example iterations on two DSP cores per producer and consumer devices.r=%jj7%jjjjj}r>%(j]j]j]j]j]ujMij]r?%jXdSuccessful completion for all example iterations on two DSP cores per producer and consumer devices.r@%rA%}rB%(jj=%jj;%ubaubajj ubejj ubejj ubejj ubaubeubj)rC%}rD%(jUjKjj$jjjjj}rE%(j]rF%Xarm linux transportsriorG%aj]j]j]rH%Uid27rI%aj]ujMwjhj]rJ%(j)rK%}rL%(jXARM Linux TransportSriorM%jjC%jjjjj}rN%(j]j]j]j]j]ujMwjhj]rO%jXARM Linux TransportSriorP%rQ%}rR%(jjM%jjK%ubaubjy )rS%}rT%(jUjjC%jjjj j}rU%(j]j]j]j]j]ujNjhj]rV%j~ )rW%}rX%(jUj}rY%(j]j]j]j]j]UcolsKujjS%j]rZ%(j )r[%}r\%(jUj}r]%(j]j]j]j]j]UcolwidthKujjW%j]jj ubj )r^%}r_%(jUj}r`%(j]j]j]j]j]UcolwidthKujjW%j]jj ubj )ra%}rb%(jUj}rc%(j]j]j]j]j]UcolwidthKujjW%j]jj ubj )rd%}re%(jUj}rf%(j]j]j]j]j]ujjW%j]rg%j )rh%}ri%(jUj}rj%(j]j]j]j]j]ujjd%j]rk%(j )rl%}rm%(jUj}rn%(j]j]j]j]j]ujjh%j]ro%j)rp%}rq%(jXNamerr%jjl%jjjjj}rs%(j]j]j]j]j]ujMzj]rt%jXNameru%rv%}rw%(jjr%jjp%ubaubajj ubj )rx%}ry%(jUj}rz%(j]j]j]j]j]ujjh%j]r{%j)r|%}r}%(jX Descriptionr~%jjx%jjjjj}r%(j]j]j]j]j]ujMzj]r%jX Descriptionr%r%}r%(jj~%jj|%ubaubajj ubj )r%}r%(jUj}r%(j]j]j]j]j]ujjh%j]r%j)r%}r%(jXExpected Resultsr%jj%jjjjj}r%(j]j]j]j]j]ujMzj]r%jXExpected Resultsr%r%}r%(jj%jj%ubaubajj ubejj ubajj ubj )r%}r%(jUj}r%(j]j]j]j]j]ujjW%j]r%j )r%}r%(jUj}r%(j]j]j]j]j]ujj%j]r%(j )r%}r%(jUj}r%(j]j]j]j]j]ujj%j]r%j)r%}r%(jX1ARM Linux TransportSrio Producer/Consumer Exampler%jj%jjjjj}r%(j]j]j]j]j]ujM|j]r%jX1ARM Linux TransportSrio Producer/Consumer Exampler%r%}r%(jj%jj%ubaubajj ubj )r%}r%(jUj}r%(j]j]j]j]j]ujj%j]r%jc)r%}r%(jUj}r%(j]j]j]j]j]ujj%j]r%ji)r%}r%(jXExample demonstrates inter-SoC, ARM Linux to ARM Linux, transport over SRIO. The example consists of multiple iterations where each iteration runs SRIO with different lane configurations.r%jlKjj%jjjjj}r%(j]j]j]j]j]ujKj]r%jXExample demonstrates inter-SoC, ARM Linux to ARM Linux, transport over SRIO. The example consists of multiple iterations where each iteration runs SRIO with different lane configurations.r%r%}r%(jj%jj%ubaubajjfubajj ubj )r%}r%(jUj}r%(j]j]j]j]j]ujj%j]r%j)r%}r%(jXjSuccessful completion for all example iterations on two Linux processes per producer and consumer devices.r%jj%jjjjj}r%(j]j]j]j]j]ujM|j]r%jXjSuccessful completion for all example iterations on two Linux processes per producer and consumer devices.r%r%}r%(jj%jj%ubaubajj ubejj ubajj ubejj ubaubeubj)r%}r%(jUjKjj$jjjjj}r%(j]r%Xsys/bios dsp transportqmssr%aj]j]j]r%Uid28r%aj]ujMjhj]r%(j)r%}r%(jXSYS/BIOS DSP TransportQmssr%jj%jjjjj}r%(j]j]j]j]j]ujMjhj]r%jXSYS/BIOS DSP TransportQmssr%r%}r%(jj%jj%ubaubjy )r%}r%(jUjj%jjjj j}r%(j]j]j]j]j]ujNjhj]r%j~ )r%}r%(jUj}r%(j]j]j]j]j]UcolsKujj%j]r%(j )r%}r%(jUj}r%(j]j]j]j]j]UcolwidthKujj%j]jj ubj )r%}r%(jUj}r%(j]j]j]j]j]UcolwidthKujj%j]jj ubj )r%}r%(jUj}r%(j]j]j]j]j]UcolwidthKujj%j]jj ubj )r%}r%(jUj}r%(j]j]j]j]j]ujj%j]r%j )r%}r%(jUj}r%(j]j]j]j]j]ujj%j]r%(j )r%}r%(jUj}r%(j]j]j]j]j]ujj%j]r%j)r%}r%(jXNamer%jj%jjjjj}r%(j]j]j]j]j]ujMj]r%jXNamer%r%}r%(jj%jj%ubaubajj ubj )r%}r%(jUj}r%(j]j]j]j]j]ujj%j]r%j)r%}r%(jX Descriptionr%jj%jjjjj}r%(j]j]j]j]j]ujMj]r%jX Descriptionr%r%}r&(jj%jj%ubaubajj ubj )r&}r&(jUj}r&(j]j]j]j]j]ujj%j]r&j)r&}r&(jXExpected Resultsr&jj&jjjjj}r&(j]j]j]j]j]ujMj]r &jXExpected Resultsr &r &}r &(jj&jj&ubaubajj ubejj ubajj ubj )r &}r&(jUj}r&(j]j]j]j]j]ujj%j]r&(j )r&}r&(jUj}r&(j]j]j]j]j]ujj &j]r&(j )r&}r&(jUj}r&(j]j]j]j]j]ujj&j]r&j)r&}r&(jX,SYS/BIOS DSP TransportQmss Benchmark Exampler&jj&jjjjj}r&(j]j]j]j]j]ujMj]r&jX,SYS/BIOS DSP TransportQmss Benchmark Exampler&r&}r &(jj&jj&ubaubajj ubj )r!&}r"&(jUj}r#&(j]j]j]j]j]ujj&j]r$&jc)r%&}r&&(jUj}r'&(j]j]j]j]j]ujj!&j]r(&ji)r)&}r*&(jX+Example demonstrating intra-SoC, DSP to DSP, transport over QMSS use while also measuring latency and throughput performance. The example consists of multiple iterations where each iteration runs QMSS with different reception mechanisms (accumulator or QPEND queue). Reference example for developersr+&jlKjj%&jjjjj}r,&(j]j]j]j]j]ujKj]r-&jX+Example demonstrating intra-SoC, DSP to DSP, transport over QMSS use while also measuring latency and throughput performance. The example consists of multiple iterations where each iteration runs QMSS with different reception mechanisms (accumulator or QPEND queue). Reference example for developersr.&r/&}r0&(jj+&jj)&ubaubajjfubajj ubj )r1&}r2&(jUj}r3&(j]j]j]j]j]ujj&j]r4&jc)r5&}r6&(jUj}r7&(j]j]j]j]j]ujj1&j]r8&ji)r9&}r:&(jXBSuccessful completion on two DSP cores for all example iterations.r;&jlKjj5&jjjjj}r<&(j]j]j]j]j]ujKj]r=&jXBSuccessful completion on two DSP cores for all example iterations.r>&r?&}r@&(jj;&jj9&ubaubajjfubajj ubejj ubj )rA&}rB&(jUj}rC&(j]j]j]j]j]ujj &j]rD&(j )rE&}rF&(jUj}rG&(j]j]j]j]j]ujjA&j]rH&j)rI&}rJ&(jXCSYS/BIOS DSP TransportQmss DSP-Side of Heterogeneous Processor TestrK&jjE&jjjjj}rL&(j]j]j]j]j]ujMj]rM&jXCSYS/BIOS DSP TransportQmss DSP-Side of Heterogeneous Processor TestrN&rO&}rP&(jjK&jjI&ubaubajj ubj )rQ&}rR&(jUj}rS&(j]j]j]j]j]ujjA&j]rT&jc)rU&}rV&(jUj}rW&(j]j]j]j]j]ujjQ&j]rX&ji)rY&}rZ&(jXUTests inter-SoC, ARM Linux to DSP, transport over QMSS. Reference test for developersr[&jlKjjU&jjjjj}r\&(j]j]j]j]j]ujKj]r]&jXUTests inter-SoC, ARM Linux to DSP, transport over QMSS. Reference test for developersr^&r_&}r`&(jj[&jjY&ubaubajjfubajj ubj )ra&}rb&(jUj}rc&(j]j]j]j]j]ujjA&j]rd&j)re&}rf&(jX?Successful completion on two DSP cores and two Linux processes.rg&jja&jjjjj}rh&(j]j]j]j]j]ujMj]ri&jX?Successful completion on two DSP cores and two Linux processes.rj&rk&}rl&(jjg&jje&ubaubajj ubejj ubejj ubejj ubaubeubj)rm&}rn&(jUjKjj$jjjjj}ro&(j]rp&Xarm linux transportqmssrq&aj]j]j]rr&Uid29rs&aj]ujMjhj]rt&(j)ru&}rv&(jXARM Linux TransportQmssrw&jjm&jjjjj}rx&(j]j]j]j]j]ujMjhj]ry&jXARM Linux TransportQmssrz&r{&}r|&(jjw&jju&ubaubjy )r}&}r~&(jUjjm&jjjj j}r&(j]j]j]j]j]ujNjhj]r&j~ )r&}r&(jUj}r&(j]j]j]j]j]UcolsKujj}&j]r&(j )r&}r&(jUj}r&(j]j]j]j]j]UcolwidthKujj&j]jj ubj )r&}r&(jUj}r&(j]j]j]j]j]UcolwidthKujj&j]jj ubj )r&}r&(jUj}r&(j]j]j]j]j]UcolwidthKujj&j]jj ubj )r&}r&(jUj}r&(j]j]j]j]j]ujj&j]r&j )r&}r&(jUj}r&(j]j]j]j]j]ujj&j]r&(j )r&}r&(jUj}r&(j]j]j]j]j]ujj&j]r&j)r&}r&(jXNamer&jj&jjjjj}r&(j]j]j]j]j]ujMj]r&jXNamer&r&}r&(jj&jj&ubaubajj ubj )r&}r&(jUj}r&(j]j]j]j]j]ujj&j]r&j)r&}r&(jX Descriptionr&jj&jjjjj}r&(j]j]j]j]j]ujMj]r&jX Descriptionr&r&}r&(jj&jj&ubaubajj ubj )r&}r&(jUj}r&(j]j]j]j]j]ujj&j]r&j)r&}r&(jXExpected Resultsr&jj&jjjjj}r&(j]j]j]j]j]ujMj]r&jXExpected Resultsr&r&}r&(jj&jj&ubaubajj ubejj ubajj ubj )r&}r&(jUj}r&(j]j]j]j]j]ujj&j]r&(j )r&}r&(jUj}r&(j]j]j]j]j]ujj&j]r&(j )r&}r&(jUj}r&(j]j]j]j]j]ujj&j]r&j)r&}r&(jX*ARM Linux TransportQmss Multi-Process Testr&jj&jjjjj}r&(j]j]j]j]j]ujMj]r&jX*ARM Linux TransportQmss Multi-Process Testr&r&}r&(jj&jj&ubaubajj ubj )r&}r&(jUj}r&(j]j]j]j]j]ujj&j]r&jc)r&}r&(jUj}r&(j]j]j]j]j]ujj&j]r&ji)r&}r&(jXbTests Linux inter-process communication via IPC transport over QMSS. Reference test for developersr&jlKjj&jjjjj}r&(j]j]j]j]j]ujKj]r&jXbTests Linux inter-process communication via IPC transport over QMSS. Reference test for developersr&r&}r&(jj&jj&ubaubajjfubajj ubj )r&}r&(jUj}r&(j]j]j]j]j]ujj&j]r&jc)r&}r&(jUj}r&(j]j]j]j]j]ujj&j]r&ji)r&}r&(jX.Successful completion on four Linux processes.r&jlKjj&jjjjj}r&(j]j]j]j]j]ujKj]r&jX.Successful completion on four Linux processes.r&r&}r&(jj&jj&ubaubajjfubajj ubejj ubj )r&}r&(jUj}r&(j]j]j]j]j]ujj&j]r&(j )r&}r&(jUj}r&(j]j]j]j]j]ujj&j]r&j)r&}r&(jXBARM Linux TransportQmss Linux-Side of Heterogeneous Processor Testr&jj&jjjjj}r&(j]j]j]j]j]ujMj]r&jXBARM Linux TransportQmss Linux-Side of Heterogeneous Processor Testr&r&}r&(jj&jj&ubaubajj ubj )r&}r&(jUj}r'(j]j]j]j]j]ujj&j]r'jc)r'}r'(jUj}r'(j]j]j]j]j]ujj&j]r'ji)r'}r'(jXUTests inter-SoC, ARM Linux to DSP, transport over QMSS. Reference test for developersr'jlKjj'jjjjj}r '(j]j]j]j]j]ujKj]r 'jXUTests inter-SoC, ARM Linux to DSP, transport over QMSS. Reference test for developersr 'r '}r '(jj'jj'ubaubajjfubajj ubj )r'}r'(jUj}r'(j]j]j]j]j]ujj&j]r'j)r'}r'(jX?Successful completion on two DSP cores and two Linux processes.r'jj'jjjjj}r'(j]j]j]j]j]ujMj]r'jX?Successful completion on two DSP cores and two Linux processes.r'r'}r'(jj'jj'ubaubajj ubejj ubejj ubejj ubaubeubeubj)r'}r'(jUjKjjjjjjj}r'(j]r'Xadditional referencesr'aj]j]j]r'Uadditional-referencesr 'aj]ujMjhj]r!'(j)r"'}r#'(jXAdditional Referencesr$'jj'jjjjj}r%'(j]j]j]j]j]ujMjhj]r&'jXAdditional Referencesr''r('}r)'(jj$'jj"'ubaubjy )r*'}r+'(jUjj'jjjj j}r,'(j]j]j]j]j]ujNjhj]r-'j~ )r.'}r/'(jUj}r0'(j]j]j]j]j]UcolsKujj*'j]r1'(j )r2'}r3'(jUj}r4'(j]j]j]j]j]UcolwidthK#ujj.'j]jj ubj )r5'}r6'(jUj}r7'(j]j]j]j]j]UcolwidthK#ujj.'j]jj ubj )r8'}r9'(jUj}r:'(j]j]j]j]j]ujj.'j]r;'(j )r<'}r='(jUj}r>'(j]j]j]j]j]ujj8'j]r?'(j )r@'}rA'(jUj}rB'(j]j]j]j]j]ujj<'j]rC'j)rD'}rE'(jX **Document**rF'jj@'jjjjj}rG'(j]j]j]j]j]ujMj]rH'j)rI'}rJ'(jjF'j}rK'(j]j]j]j]j]ujjD'j]rL'jXDocumentrM'rN'}rO'(jUjjI'ubajjubaubajj ubj )rP'}rQ'(jUj}rR'(j]j]j]j]j]ujj<'j]rS'j)rT'}rU'(jX **Location**rV'jjP'jjjjj}rW'(j]j]j]j]j]ujMj]rX'j)rY'}rZ'(jjV'j}r['(j]j]j]j]j]ujjT'j]r\'jXLocationr]'r^'}r_'(jUjjY'ubajjubaubajj ubejj ubj )r`'}ra'(jUj}rb'(j]j]j]j]j]ujj8'j]rc'(j )rd'}re'(jUj}rf'(j]j]j]j]j]ujj`'j]rg'j)rh'}ri'(jX"TransportQmss API Reference Manualrj'jjd'jjjjj}rk'(j]j]j]j]j]ujMj]rl'jX"TransportQmss API Reference Manualrm'rn'}ro'(jjj'jjh'ubaubajj ubj )rp'}rq'(jUj}rr'(j]j]j]j]j]ujj`'j]rs'j)rt'}ru'(jXW$(TI_PDK_INSTALL_DIR)/packages/ti /transport/ipc/c66/qmss/docs/doxy gen/html/index.htmlrv'jjp'jjjjj}rw'(j]j]j]j]j]ujMj]rx'jXW$(TI_PDK_INSTALL_DIR)/packages/ti /transport/ipc/c66/qmss/docs/doxy gen/html/index.htmlry'rz'}r{'(jjv'jjt'ubaubajj ubejj ubj )r|'}r}'(jUj}r~'(j]j]j]j]j]ujj8'j]r'(j )r'}r'(jUj}r'(j]j]j]j]j]ujj|'j]r'j)r'}r'(jXTransportQmss Release Notesr'jj'jjjjj}r'(j]j]j]j]j]ujMj]r'jXTransportQmss Release Notesr'r'}r'(jj'jj'ubaubajj ubj )r'}r'(jUj}r'(j]j]j]j]j]ujj|'j]r'j)r'}r'(jX^$(TI_PDK_INSTALL_DIR)/packages/ti /transport/ipc/c66/qmss/docs/Rele aseNotes_TransportQmss.pdfr'jj'jjjjj}r'(j]j]j]j]j]ujMj]r'jX^$(TI_PDK_INSTALL_DIR)/packages/ti /transport/ipc/c66/qmss/docs/Rele aseNotes_TransportQmss.pdfr'r'}r'(jj'jj'ubaubajj ubejj ubj )r'}r'(jUj}r'(j]j]j]j]j]ujj8'j]r'(j )r'}r'(jUj}r'(j]j]j]j]j]ujj'j]r'j)r'}r'(jX"TransportSrio API Reference Manualr'jj'jjjjj}r'(j]j]j]j]j]ujMj]r'jX"TransportSrio API Reference Manualr'r'}r'(jj'jj'ubaubajj ubj )r'}r'(jUj}r'(j]j]j]j]j]ujj'j]r'j)r'}r'(jXW$(TI_PDK_INSTALL_DIR)/packages/ti /transport/ipc/c66/srio/docs/doxy gen/html/index.htmlr'jj'jjjjj}r'(j]j]j]j]j]ujMj]r'jXW$(TI_PDK_INSTALL_DIR)/packages/ti /transport/ipc/c66/srio/docs/doxy gen/html/index.htmlr'r'}r'(jj'jj'ubaubajj ubejj ubj )r'}r'(jUj}r'(j]j]j]j]j]ujj8'j]r'(j )r'}r'(jUj}r'(j]j]j]j]j]ujj'j]r'j)r'}r'(jXTransportSrio Release Notesr'jj'jjjjj}r'(j]j]j]j]j]ujMj]r'jXTransportSrio Release Notesr'r'}r'(jj'jj'ubaubajj ubj )r'}r'(jUj}r'(j]j]j]j]j]ujj'j]r'j)r'}r'(jX^$(TI_PDK_INSTALL_DIR)/packages/ti /transport/ipc/c66/srio/docs/Rele aseNotes_TransportSrio.pdfr'jj'jjjjj}r'(j]j]j]j]j]ujMj]r'jX^$(TI_PDK_INSTALL_DIR)/packages/ti /transport/ipc/c66/srio/docs/Rele aseNotes_TransportSrio.pdfr'r'}r'(jj'jj'ubaubajj ubejj ubejj ubejj ubaubeubeubj)r'}r'(jUjjjjjjj}r'(j]j]j]j]r'Uipc-benchmarkingr'aj]r'haujKujhj]r'(j)r'}r'(jXIPC Benchmarkingr'jj'jjjjj}r'(j]j]j]j]j]ujKujhj]r'jXIPC Benchmarkingr'r'}r'(jj'jj'ubaubj7)r'}r'(jX8http://processors.wiki.ti.com/index.php/IPC_BenchMarkingjj'jj:X>source/rtos/PDK_Platform_Software/IPC/IPC_BenchMarking.rst.incr'r'}r'bjj>j}r'(j@jAj]j]j]j]j]ujKjhj]r'jX8http://processors.wiki.ti.com/index.php/IPC_BenchMarkingr'r'}r'(jUjj'ubaubj)r'}r'(jUjj'jj'jjj}r'(j]j]j]j]r'U&rtos-ipc-benchmark-applications-in-sdkr'aj]r'jpaujKjhj]r'(j)r'}r'(jX&RTOS IPC Benchmark applications in SDKr'jj'jj'jjj}r'(j]j]j]j]j]ujKjhj]r'jX&RTOS IPC Benchmark applications in SDKr'r'}r'(jj'jj'ubaubj)r'}r'(jX8Processor SDK RTOS includes a ping_benchmark_example under processor_sdk_rtos__/demos/ipc-examples/ping_benchmark_example. This example shows multiple cores running RTOS communicating with each other through the IPC MessageQ API. The example measures and displays the round trip delay numbers for the IPC. Note the main example sends multiple messages from each of the cores, with all the cores sending messages simultaneously. The example can be built with option to just R5F0 as the originator and all the other cores just respond back with reply.r'jj'jj'jjj}r'(j]j]j]j]j]ujKjhj]r'jX8Processor SDK RTOS includes a ping_benchmark_example under processor_sdk_rtos__/demos/ipc-examples/ping_benchmark_example. This example shows multiple cores running RTOS communicating with each other through the IPC MessageQ API. The example measures and displays the round trip delay numbers for the IPC. Note the main example sends multiple messages from each of the cores, with all the cores sending messages simultaneously. The example can be built with option to just R5F0 as the originator and all the other cores just respond back with reply.r'r'}r'(jj'jj'ubaubj)r(}r((jUjKjj'jj'jjj}r((j]r(j{ aj]j]j]r(Uid30r(aj]ujK jhj]r((j)r(}r((jXBuildr (jj(jj'jjj}r ((j]j]j]j]j]ujK jhj]r (jXBuildr (r (}r((jj (jj(ubaubj)r(}r((jXrThe example can be built by running the top level make from the processor_sdk_rtos__ directory.r(jj(jj'jjj}r((j]j]j]j]j]ujKjhj]r(jXrThe example can be built by running the top level make from the processor_sdk_rtos__ directory.r(r(}r((jj(jj(ubaubj)r(}r((jUjj(jj'jjj}r((j]j]j]j]r(U linux-hostr(aj]r(jaujKjhj]r((j)r(}r((jX Linux Hostr (jj(jj'jjj}r!((j]j]j]j]j]ujKjhj]r"(jX Linux Hostr#(r$(}r%((jj (jj(ubaubj)r&(}r'((jXDcd processor_sdk_rtos__ make sdk_ipc_examples_alljj(jj'jjj}r(((j@jAj]j]j]j]j]ujMjhj]r)(jXDcd processor_sdk_rtos__ make sdk_ipc_examples_allr*(r+(}r,((jUjj&(ubaubeubj)r-(}r.((jUjj(jj'jjj}r/((j]j]j]j]r0(U windows-hostr1(aj]r2(h&aujKjhj]r3((j)r4(}r5((jX Windows Hostr6(jj-(jj'jjj}r7((j]j]j]j]j]ujKjhj]r8(jX Windows Hostr9(r:(}r;((jj6(jj4(ubaubj)r<(}r=((jXRcd processor_sdk_rtos__ setupenv.bat gmake sdk_ipc_examples_allr>(jj-(jj'jjj}r?((j]j]j]j]j]ujKjhj]r@(jXRcd processor_sdk_rtos__ setupenv.bat gmake sdk_ipc_examples_allrA(rB(}rC((jj>(jj<(ubaubj)rD(}rE((jXfOnce the build commands are executed, the binaries will be in their respective directories as follows.rF(jj-(jj'jjj}rG((j]j]j]j]j]ujKjhj]rH(jXfOnce the build commands are executed, the binaries will be in their respective directories as follows.rI(rJ(}rK((jjF(jjD(ubaubj)rL(}rM((jXAM65X:rN(jj-(jj'jjj}rO((j]j]j]j]j]ujK jhj]rP(jXAM65X:rQ(rR(}rS((jjN(jjL(ubaubj)rT(}rU((jX3Host A53: ./demos/ipc-examples/ping_benchmark_example/hosta53/bin/am65xx_evm/release/server_host.xa53fg R5F-0: ./demos/ipc-examples/ping_benchmark_example/r5f-0/bin/am65xx_evm/release/server_r5f-0.xer5f R5F-1: ./demos/ipc-examples/ping_benchmark_example/r5f-1/bin/am65xx_evm/release/server_r5f-1.xer5fjj-(jj'jjj}rV((j@jAj]j]j]j]j]ujMjhj]rW(jX3Host A53: ./demos/ipc-examples/ping_benchmark_example/hosta53/bin/am65xx_evm/release/server_host.xa53fg R5F-0: ./demos/ipc-examples/ping_benchmark_example/r5f-0/bin/am65xx_evm/release/server_r5f-0.xer5f R5F-1: ./demos/ipc-examples/ping_benchmark_example/r5f-1/bin/am65xx_evm/release/server_r5f-1.xer5frX(rY(}rZ((jUjjT(ubaubj)r[(}r\((jX1And also the R5F0 only as sender images are here:r](jj-(jj'jjj}r^((j]j]j]j]j]ujK)jhj]r_(jX1And also the R5F0 only as sender images are here:r`(ra(}rb((jj](jj[(ubaubj)rc(}rd((jX]Host A53: ./demos/ipc-examples/ping_benchmark_example/hosta53/bin/am65xx_evm/app_r5f0_only/release/server_host.xa53fg R5F-0: ./demos/ipc-examples/ping_benchmark_example/r5f-0/bin/am65xx_evm/app_r5f0_only/release/server_r5f-0.xer5f R5F-1: ./demos/ipc-examples/ping_benchmark_example/r5f-1/bin/am65xx_evm/app_r5f0_only/release/server_r5f-1.xer5fjj-(jj'jjj}re((j@jAj]j]j]j]j]ujMjhj]rf(jX]Host A53: ./demos/ipc-examples/ping_benchmark_example/hosta53/bin/am65xx_evm/app_r5f0_only/release/server_host.xa53fg R5F-0: ./demos/ipc-examples/ping_benchmark_example/r5f-0/bin/am65xx_evm/app_r5f0_only/release/server_r5f-0.xer5f R5F-1: ./demos/ipc-examples/ping_benchmark_example/r5f-1/bin/am65xx_evm/app_r5f0_only/release/server_r5f-1.xer5frg(rh(}ri((jUjjc(ubaubj)rj(}rk((jXKAlso the SBL bootable images can be created by using the following commandsrl(jj-(jj'jjj}rm((j]j]j]j]j]ujK2jhj]rn(jXKAlso the SBL bootable images can be created by using the following commandsro(rp(}rq((jjl(jjj(ubaubj)rr(}rs((jX Linux Host:rt(jj-(jj'jjj}ru((j]j]j]j]j]ujK4jhj]rv(jX Linux Host:rw(rx(}ry((jjt(jjr(ubaubj)rz(}r{((jX=make sdk_ipc_examples_app make sdk_ipc_examples_app_r5f0_onlyjj-(jj'jjj}r|((j@jAj]j]j]j]j]ujMjhj]r}(jX=make sdk_ipc_examples_app make sdk_ipc_examples_app_r5f0_onlyr~(r(}r((jUjjz(ubaubj)r(}r((jX Windows host:r(jj-(jj'jjj}r((j]j]j]j]j]ujK;jhj]r(jX Windows host:r(r(}r((jj(jj(ubaubj )r(}r((jUjj-(jj'jj# j}r((j]j]j]j]j]ujNjhj]r(j& )r(}r((jXC:: gmake sdk_ipc_examples_app gmake sdk_ipc_examples_app_r5f0_only jj(jj'jj) j}r((j]j]j]j]j]ujK?j]r((j, )r(}r((jX::r(jj(jj'jj0 j}r((j]j]j]j]j]ujK?j]r(jX::r(r(}r((jj(jj(ubaubj6 )r(}r((jUj}r((j]j]j]j]j]ujj(j]r(j)r(}r((jX?gmake sdk_ipc_examples_app gmake sdk_ipc_examples_app_r5f0_onlyr(jj(jj'jjj}r((j]j]j]j]j]ujK>j]r(jX?gmake sdk_ipc_examples_app gmake sdk_ipc_examples_app_r5f0_onlyr(r(}r((jj(jj(ubaubajjQ ubeubaubj)r(}r((jX-The application images will be located under:r(jj-(jj'jjj}r((j]j]j]j]j]ujKAjhj]r(jX-The application images will be located under:r(r(}r((jj(jj(ubaubj)r(}r((jXdemos/ipc-examples/ping_benchmark_example/output.appimage demos/ipc-examples/ping_benchmark_example/am65xx_evm/app_r5f0_only/output.appimagejj-(jj'jjj}r((j@jAj]j]j]j]j]ujMjhj]r(jXdemos/ipc-examples/ping_benchmark_example/output.appimage demos/ipc-examples/ping_benchmark_example/am65xx_evm/app_r5f0_only/output.appimager(r(}r((jUjj(ubaubeubeubj)r(}r((jUjKjj'jj'jjj}r((j]r(Xrunr(aj]j]j]r(Urunr(aj]ujKIjhj]r((j)r(}r((jXRunr(jj(jj'jjj}r((j]j]j]j]j]ujKIjhj]r(jXRunr(r(}r((jj(jj(ubaubj)r(}r((jX1Pre-requisites: Bootable SD card loaded with SBL.r(jj(jj'jjj}r((j]j]j]j]j]ujKKjhj]r(jX1Pre-requisites: Bootable SD card loaded with SBL.r(r(}r((jj(jj(ubaubj)r(}r((jUjj(jj'jjj}r((j]j]j]j]r(Uam65xr(aj]r(jUaujKNjhj]r((j)r(}r((jXAM65xr(jj(jj'jjj}r((j]j]j]j]j]ujKNjhj]r(jXAM65xr(r(}r((jj(jj(ubaubj)r(}r((jXLoad the app from this directory into the SD card with filename "app" and load into the EVM to boot. (Note: Make sure the UART port is connected to the terminal to observe the application prints)r(jj(jj'jjj}r((j]j]j]j]j]ujKPjhj]r(jXLoad the app from this directory into the SD card with filename "app" and load into the EVM to boot. (Note: Make sure the UART port is connected to the terminal to observe the application prints)r(r(}r((jj(jj(ubaubj)r(}r((jXQOn running the application the benchmark data will be displayed on the UART port.r(jj(jj'jjj}r((j]j]j]j]j]ujKSjhj]r(jXQOn running the application the benchmark data will be displayed on the UART port.r(r(}r((jj(jj(ubaubj)r(}r((jXLFor the main application the benchmark data will be displayed on UART port0:r(jj(jj'jjj}r((j]j]j]j]j]ujKUjhj]r(jXLFor the main application the benchmark data will be displayed on UART port0:r(r(}r((jj(jj(ubaubj)r(}r((jXjOverhead:34 Payload Size: 176 Proc id 0, Delta count: 3829025 Proc id 0 to Proc Id 0: Average Roundtrip time is: 19 us Proc id 1, Delta count: 8920087 Proc id 0 to Proc Id 1: Average Roundtrip time is: 44 us Proc id 2, Delta count: 7091251 Proc id 0 to Proc Id 2: Average Roundtrip time is: 35 us AppHost_run: Test Passed MainHost_appTskFxn: Test Passedjj(jj'jjj}r((j@jAj]j]j]j]j]ujMjhj]r(jXjOverhead:34 Payload Size: 176 Proc id 0, Delta count: 3829025 Proc id 0 to Proc Id 0: Average Roundtrip time is: 19 us Proc id 1, Delta count: 8920087 Proc id 0 to Proc Id 1: Average Roundtrip time is: 44 us Proc id 2, Delta count: 7091251 Proc id 0 to Proc Id 2: Average Roundtrip time is: 35 us AppHost_run: Test Passed MainHost_appTskFxn: Test Passedr(r(}r((jUjj(ubaubj)r(}r((jXPFor the R5F0 app only build, the benchmark data will be displayed on UART port1:r(jj(jj'jjj}r((j]j]j]j]j]ujKnjhj]r(jXPFor the R5F0 app only build, the benchmark data will be displayed on UART port1:r(r)}r)(jj(jj(ubaubj)r)}r)(jXJOverhead:144 Payload Size: 176 Proc id 0, Delta count: 8460883 Proc id 1 to Proc Id 0: Average Roundtrip time is: 42 us Proc id 1, Delta count: 1046906 Proc id 1 to Proc Id 1: Average Roundtrip time is: 5 us Proc id 2, Delta count: 6297313 Proc id 1 to Proc Id 2: Average Roundtrip time is: 31 us AppR5f_0_run: Test Passedjj(jj'jjj}r)(j@jAj]j]j]j]j]ujMjhj]r)jXJOverhead:144 Payload Size: 176 Proc id 0, Delta count: 8460883 Proc id 1 to Proc Id 0: Average Roundtrip time is: 42 us Proc id 1, Delta count: 1046906 Proc id 1 to Proc Id 1: Average Roundtrip time is: 5 us Proc id 2, Delta count: 6297313 Proc id 1 to Proc Id 2: Average Roundtrip time is: 31 us AppR5f_0_run: Test Passedr)r)}r)(jUjj)ubaubeubeubeubj)r )}r )(jUjj'jj'jjj}r )(j]j]j]j]r )U"linux-benchmark-test-messageqbenchr )aj]r)h$aujKjhj]r)(j)r)}r)(jX#Linux Benchmark test: MessageQBenchr)jj )jj'jjj}r)(j]j]j]j]j]ujKjhj]r)jX#Linux Benchmark test: MessageQBenchr)r)}r)(jj)jj)ubaubj)r)}r)(jXThe application utilizes the IPC 3.x stack to communicate from the main processor to the slave core via the MessageQ interface. The application measures the time taken to accomplish this. The MessageQBench binaries are included in the Linux file system and they are located in:r)jj )jj'jjj}r)(j]j]j]j]j]ujKjhj]r)jXThe application utilizes the IPC 3.x stack to communicate from the main processor to the slave core via the MessageQ interface. The application measures the time taken to accomplish this. The MessageQBench binaries are included in the Linux file system and they are located in:r)r)}r)(jj)jj)ubaubjc)r )}r!)(jUjj )jj'jjfj}r")(j]j]j]j]j]ujKjhj]r#)(ji)r$)}r%)(jX)Linux Application: /usr/bin/MessageQBenchr&)jlKjj )jj'jjj}r')(j]j]j]j]j]ujKjhj]r()jX)Linux Application: /usr/bin/MessageQBenchr))r*)}r+)(jj&)jj$)ubaubji)r,)}r-)(jXWDSP binary: /lib/firmware/ipc/ti_platforms_[platform]_core0/messageq_single.xe66r.)jlKjj )jj'jjj}r/)(j]j]j]j]j]ujKjhj]r0)jXWDSP binary: /lib/firmware/ipc/ti_platforms_[platform]_core0/messageq_single.xe66r1)r2)}r3)(jj.)jj,)ubaubji)r4)}r5)(jUjlKjj )jj'jjj}r6)(j]j]j]j]j]ujKjhj]ubeubj)r7)}r8)(jX6The MessageQBench can be built following the instruction described in the below Build section or using high level build in Linux Processor SDK as described in `IPC Quick Start Guide `__jj )jj'jjj}r9)(j]j]j]j]j]ujKjhj]r:)(jXThe MessageQBench can be built following the instruction described in the below Build section or using high level build in Linux Processor SDK as described in r;)r<)}r=)(jXThe MessageQBench can be built following the instruction described in the below Build section or using high level build in Linux Processor SDK as described in jj7)ubj)r>)}r?)(jX`IPC Quick Start Guide `__j}r@)(UnameXIPC Quick Start GuidejXzhttp://software-dl.ti.com/processor-sdk-linux/esd/docs/latest/linux/Foundational_Components_IPC.html#ipc-quick-start-guidej]j]j]j]j]ujj7)j]rA)jXIPC Quick Start GuiderB)rC)}rD)(jUjj>)ubajjubeubj)rE)}rF)(jUjKjj )jj'jjj}rG)(j]rH)XbuildrI)aj]j]j]rJ)Uid31rK)aj]ujKjhj]rL)(j)rM)}rN)(jXBuildrO)jjE)jj'jjj}rP)(j]j]j]j]j]ujKjhj]rQ)jXBuildrR)rS)}rT)(jjO)jjM)ubaubj)rU)}rV)(jXJThis section outlines the build process for the MessageQBench application.rW)jjE)jj'jjj}rX)(j]j]j]j]j]ujKjhj]rY)jXJThis section outlines the build process for the MessageQBench application.rZ)r[)}r\)(jjW)jjU)ubaubj)r])}r^)(jUjKjjE)jj'jjj}r_)(j]r`)Xlinuxra)aj]j]j]rb)Ulinuxrc)aj]ujKjhj]rd)(j)re)}rf)(jXLinuxrg)jj])jj'jjj}rh)(j]j]j]j]j]ujKjhj]ri)jXLinuxrj)rk)}rl)(jjg)jje)ubaubj)rm)}rn)(jXTo build the application, follow the `Linux IPC Install Guide `__ to configure and build the Linux-side applications for your device. You'll also need to build the corresponding BIOS side of IPC as indicated in the guide.jj])jj'jjj}ro)(j]j]j]j]j]ujKjhj]rp)(jX%To build the application, follow the rq)rr)}rs)(jX%To build the application, follow the jjm)ubj)rt)}ru)(jXT`Linux IPC Install Guide `__j}rv)(UnameXLinux IPC Install GuidejX6index_Foundational_Components.html#linux-install-guidej]j]j]j]j]ujjm)j]rw)jXLinux IPC Install Guiderx)ry)}rz)(jUjjt)ubajjubjX to configure and build the Linux-side applications for your device. You'll also need to build the corresponding BIOS side of IPC as indicated in the guide.r{)r|)}r})(jX to configure and build the Linux-side applications for your device. You'll also need to build the corresponding BIOS side of IPC as indicated in the guide.jjm)ubeubeubj)r~)}r)(jUjKjjE)jj'jjj}r)(j]r)Xqnxr)aj]j]j]r)Uqnxr)aj]ujKjhj]r)(j)r)}r)(jXQNXr)jj~)jj'jjj}r)(j]j]j]j]j]ujKjhj]r)jXQNXr)r)}r)(jj)jj)ubaubj)r)}r)(jXTo build the application, follow the `QNX IPC Install Guide `__ to configure and build the QNX-side test applications for your device. You'll also need to build the corresponding BIOS side of IPC as indicated in the guide.jj~)jj'jjj}r)(j]j]j]j]j]ujKjhj]r)(jX%To build the application, follow the r)r)}r)(jX%To build the application, follow the jj)ubj)r)}r)(jXP`QNX IPC Install Guide `__j}r)(UnameXQNX IPC Install GuidejX4index_Foundational_Components.html#qnx-install-guidej]j]j]j]j]ujj)j]r)jXQNX IPC Install Guider)r)}r)(jUjj)ubajjubjX to configure and build the QNX-side test applications for your device. You'll also need to build the corresponding BIOS side of IPC as indicated in the guide.r)r)}r)(jX to configure and build the QNX-side test applications for your device. You'll also need to build the corresponding BIOS side of IPC as indicated in the guide.jj)ubeubeubj)r)}r)(jUjjE)jj'jjj}r)(j]j]j]j]r)Uandroidr)aj]r)haujKjhj]r)(j)r)}r)(jXAndroidr)jj)jj'jjj}r)(j]j]j]j]j]ujKjhj]r)jXAndroidr)r)}r)(jj)jj)ubaubj)r)}r)(jXThe IPC development sources should be included in the Android Filesystem (AFS) indicated by the manifest provided in your AFS distribution. The sources are located in $(AFS_ROOT)/hardware/ti/ipc directory.r)jj)jj'jjj}r)(j]j]j]j]j]ujKjhj]r)jXThe IPC development sources should be included in the Android Filesystem (AFS) indicated by the manifest provided in your AFS distribution. The sources are located in $(AFS_ROOT)/hardware/ti/ipc directory.r)r)}r)(jj)jj)ubaubj)r)}r)(jXETo build the IPC applications, follow the same procedure to build the entire AFS. If you want to specifically build the IPC content, you can issue the following command to build the needed IPC libraries and application from the top your AFS installation (must configure and pick the correct **lunch** target for your device).jj)jj'jjj}r)(j]j]j]j]j]ujKjhj]r)(jX#To build the IPC applications, follow the same procedure to build the entire AFS. If you want to specifically build the IPC content, you can issue the following command to build the needed IPC libraries and application from the top your AFS installation (must configure and pick the correct r)r)}r)(jX#To build the IPC applications, follow the same procedure to build the entire AFS. If you want to specifically build the IPC content, you can issue the following command to build the needed IPC libraries and application from the top your AFS installation (must configure and pick the correct jj)ubj)r)}r)(jX **lunch**j}r)(j]j]j]j]j]ujj)j]r)jXlunchr)r)}r)(jUjj)ubajjubjX target for your device).r)r)}r)(jX target for your device).jj)ubeubj)r)}r)(jX$buildhost make -j messageQApp \ messageQBench \ messageQMulti \ nameServerApp \ ping_rpmsg \ lad_dra7xx \ libmmrpcjj)jj'jjj}r)(j@jAj]j]j]j]j]ujMJjhj]r)jX$buildhost make -j messageQApp \ messageQBench \ messageQMulti \ nameServerApp \ ping_rpmsg \ lad_dra7xx \ libmmrpcr)r)}r)(jUjj)ubaubj)r)}r)(jXTo build the corresponding SysBios side of IPC follow the `IPC Install Guide `__.jj)jj'jjj}r)(j]j]j]j]j]ujKjhj]r)(jX:To build the corresponding SysBios side of IPC follow the r)r)}r)(jX:To build the corresponding SysBios side of IPC follow the jj)ubj)r)}r)(jXN`IPC Install Guide `__j}r)(UnameXIPC Install GuidejX6index_Foundational_Components.html#linux-install-guidej]j]j]j]j]ujj)j]r)jXIPC Install Guider)r)}r)(jUjj)ubajjubjX.r)}r)(jX.jj)ubeubeubeubj)r)}r)(jUjKjj )jj'jjj}r)(j]r)j(aj]j]j]r)Uid32r)aj]ujKjhj]r)(j)r)}r)(jXRunr)jj)jj'jjj}r)(j]j]j]j]j]ujKjhj]r)jXRunr)r)}r)(jj)jj)ubaubj)r)}r)(jXHThis section illustrates the steps to run the MessageQBench application.r)jj)jj'jjj}r)(j]j]j]j]j]ujKjhj]r)jXHThis section illustrates the steps to run the MessageQBench application.r)r)}r)(jj)jj)ubaubj)r)}r)(jUjj)jj'jjj}r)(j]j]j]j]r)U linux-androidr)aj]r)jaujKjhj]r)(j)r)}r)(jX Linux/Androidr)jj)jj'jjj}r)(j]j]j]j]j]ujKjhj]r*jX Linux/Androidr*r*}r*(jj)jj)ubaubj)r*}r*(jXaThe built IPC libraries and applications must be copied (installed) onto the devices filesystem. The LAD Daemon must be running and application's corresponding slave-side binary must be loaded via the remoteproc kernel module. The slave-side binary (messageq_single.x), is located in the $(IPC_ROOT)/packages/ti/ipc/tests/bin/ directory.r*jj)jj'jjj}r*(j]j]j]j]j]ujKjhj]r*jXaThe built IPC libraries and applications must be copied (installed) onto the devices filesystem. The LAD Daemon must be running and application's corresponding slave-side binary must be loaded via the remoteproc kernel module. The slave-side binary (messageq_single.x), is located in the $(IPC_ROOT)/packages/ti/ipc/tests/bin/ directory.r *r *}r *(jj*jj*ubaubjc)r *}r *(jUjj)jj'jjfj}r*(j]j]j]j]j]ujKjhj]r*(ji)r*}r*(jUjlKjj *jj'jjj}r*(j]j]j]j]j]ujKjhj]ubji)r*}r*(jXDetailed information regarding this can be found in the **Installing Tests** and **IPC Daemons and Drivers** section of the `IPC Install Guide `__.jlKjj *jj'jjj}r*(j]j]j]j]j]ujKjhj]r*(jX8Detailed information regarding this can be found in the r*r*}r*(jX8Detailed information regarding this can be found in the jj*ubj)r*}r*(jX**Installing Tests**j}r*(j]j]j]j]j]ujj*j]r*jXInstalling Testsr*r*}r *(jUjj*ubajjubjX and r!*r"*}r#*(jX and jj*ubj)r$*}r%*(jX**IPC Daemons and Drivers**j}r&*(j]j]j]j]j]ujj*j]r'*jXIPC Daemons and Driversr(*r)*}r**(jUjj$*ubajjubjX section of the r+*r,*}r-*(jX section of the jj*ubj)r.*}r/*(jXN`IPC Install Guide `__j}r0*(UnameXIPC Install GuidejX6index_Foundational_Components.html#linux-install-guidej]j]j]j]j]ujj*j]r1*jXIPC Install Guider2*r3*}r4*(jUjj.*ubajjubjX.r5*}r6*(jX.jj*ubeubeubjc)r7*}r8*(jUjj)jj'jjfj}r9*(j]j]j]j]j]ujKjhj]r:*ji)r;*}r<*(jUjlKjj7*jj'jjj}r=*(j]j]j]j]j]ujKjhj]ubaubj)r>*}r?*(jXAndroid users - The Android binaries (lad_dra7xx and messageQBench) will be located in the $(AFS_ROOT)/out/target/product//system/binary directory. There are also dependent libraries (libtiipc.so, libtiipcutils.so, and libtiipcutils_lad.so) in the $(AFS_ROOT)/out/target/product//system/lib directory. These files need to be copied to your device filesystem for execution.jj)jj'jjj}r@*(j]j]j]j]j]ujNjhj]rA*j)rB*}rC*(jXAndroid users - The Android binaries (lad_dra7xx and messageQBench) will be located in the $(AFS_ROOT)/out/target/product//system/binary directory. There are also dependent libraries (libtiipc.so, libtiipcutils.so, and libtiipcutils_lad.so) in the $(AFS_ROOT)/out/target/product//system/lib directory. These files need to be copied to your device filesystem for execution.rD*jj>*jj'jjj}rE*(j]j]j]j]j]ujKj]rF*jXAndroid users - The Android binaries (lad_dra7xx and messageQBench) will be located in the $(AFS_ROOT)/out/target/product//system/binary directory. There are also dependent libraries (libtiipc.so, libtiipcutils.so, and libtiipcutils_lad.so) in the $(AFS_ROOT)/out/target/product//system/lib directory. These files need to be copied to your device filesystem for execution.rG*rH*}rI*(jjD*jjB*ubaubaubjc)rJ*}rK*(jUjj)jj'jjfj}rL*(j]j]j]j]j]ujKjhj]rM*(ji)rN*}rO*(jUjlKjjJ*jj'jjj}rP*(j]j]j]j]j]ujKjhj]ubji)rQ*}rR*(jXOnce the LAD daemon is running and the slave core binary has been loaded. You can execute the following to run the application:rS*jlKjjJ*jj'jjj}rT*(j]j]j]j]j]ujKjhj]rU*jXOnce the LAD daemon is running and the slave core binary has been loaded. You can execute the following to run the application:rV*rW*}rX*(jjS*jjQ*ubaubeubj)rY*}rZ*(jXtarget# /usr/bin/MessageQBenchjj)jj'jjj}r[*(j@jAj]j]j]j]j]ujMxjhj]r\*jXtarget# /usr/bin/MessageQBenchr]*r^*}r_*(jUjjY*ubaubj)r`*}ra*(jXThe application will exchange 1000 messages with a payload of 8 by default with an average round trip time per message. The following is the usage parameters for the application.rb*jj)jj'jjj}rc*(j]j]j]j]j]ujKjhj]rd*jXThe application will exchange 1000 messages with a payload of 8 by default with an average round trip time per message. The following is the usage parameters for the application.re*rf*}rg*(jjb*jj`*ubaubj)rh*}ri*(jX}Usage: ./bin/MessageQBench [] [] [] Defaults: numLoops: 1000; payloadSize: 8, ProcId: 1jj)jj'jjj}rj*(j@jAj]j]j]j]j]ujMjhj]rk*jX}Usage: ./bin/MessageQBench [] [] [] Defaults: numLoops: 1000; payloadSize: 8, ProcId: 1rl*rm*}rn*(jUjjh*ubaubeubj)ro*}rp*(jUjKjj)jj'jjj}rq*(j]rr*j)aj]j]j]rs*Uid33rt*aj]ujKjhj]ru*(j)rv*}rw*(jXQNXrx*jjo*jj'jjj}ry*(j]j]j]j]j]ujKjhj]rz*jXQNXr{*r|*}r}*(jjx*jjv*ubaubj)r~*}r*(jXnThe built IPC libraries and test applications must be copied (installed) onto the devices filesystem. The IPC resource manager must be running and the application's corresponding slave-side binary must be loaded using the resource manager. The slave-side binary (messageq_single.x), is located in the $(IPC_ROOT)/packages/ti/ipc/tests/bin/ directory.r*jjo*jj'jjj}r*(j]j]j]j]j]ujKjhj]r*jXnThe built IPC libraries and test applications must be copied (installed) onto the devices filesystem. The IPC resource manager must be running and the application's corresponding slave-side binary must be loaded using the resource manager. The slave-side binary (messageq_single.x), is located in the $(IPC_ROOT)/packages/ti/ipc/tests/bin/ directory.r*r*}r*(jj*jj~*ubaubjc)r*}r*(jUjjo*jj'jjfj}r*(j]j]j]j]j]ujKjhj]r*(ji)r*}r*(jUjlKjj*jj'jjj}r*(j]j]j]j]j]ujKjhj]ubji)r*}r*(jXDetailed information regarding this can be found in the **Installing Tests in QNX**, **IPC resource manager** and **Running Test Applications** sections of the `IPC Install Guide `__.jlKjj*jj'jjj}r*(j]j]j]j]j]ujMjhj]r*(jX8Detailed information regarding this can be found in the r*r*}r*(jX8Detailed information regarding this can be found in the jj*ubj)r*}r*(jX**Installing Tests in QNX**j}r*(j]j]j]j]j]ujj*j]r*jXInstalling Tests in QNXr*r*}r*(jUjj*ubajjubjX, r*r*}r*(jX, jj*ubj)r*}r*(jX**IPC resource manager**j}r*(j]j]j]j]j]ujj*j]r*jXIPC resource managerr*r*}r*(jUjj*ubajjubjX and r*r*}r*(jX and jj*ubj)r*}r*(jX**Running Test Applications**j}r*(j]j]j]j]j]ujj*j]r*jXRunning Test Applicationsr*r*}r*(jUjj*ubajjubjX sections of the r*r*}r*(jX sections of the jj*ubj)r*}r*(jXL`IPC Install Guide `__j}r*(UnameXIPC Install GuidejX4index_Foundational_Components.html#qnx-install-guidej]j]j]j]j]ujj*j]r*jXIPC Install Guider*r*}r*(jUjj*ubajjubjX.r*}r*(jX.jj*ubeubeubj)r*}r*(jXOnce the IPC resource manager is running and the slave core binary has been loaded. You can execute the following to run the application:r*jjo*jj'jjj}r*(j]j]j]j]j]ujMjhj]r*jXOnce the IPC resource manager is running and the slave core binary has been loaded. You can execute the following to run the application:r*r*}r*(jj*jj*ubaubj)r*}r*(jX7target# tests/MessageQBench 1000 8 jjo*jj'jjj}r*(j@jAj]j]j]j]j]ujMjhj]r*jX7target# tests/MessageQBench 1000 8 r*r*}r*(jUjj*ubaubj)r*}r*(jXThe application will exchange 1000 messages with a payload of 8 with the core identified by 'procId' and show an average round trip time per message. The following shows the usage parameters for the application.r*jjo*jj'jjj}r*(j]j]j]j]j]ujM jhj]r*jXThe application will exchange 1000 messages with a payload of 8 with the core identified by 'procId' and show an average round trip time per message. The following shows the usage parameters for the application.r*r*}r*(jj*jj*ubaubj)r*}r*(jX?Syntax: MessageQBench [] [] []jjo*jj'jjj}r*(j@jAj]j]j]j]j]ujMjhj]r*jX?Syntax: MessageQBench [] [] []r*r*}r*(jUjj*ubaubeubeubeubj)r*}r*(jUjj'jj'jjj}r*(j]j]j]j]r*Uipc-performancer*aj]r*hsaujMjhj]r*(j)r*}r*(jXIPC Performancer*jj*jj'jjj}r*(j]j]j]j]j]ujMjhj]r*jXIPC Performancer*r*}r*(jj*jj*ubaubj)r*}r*(jXUThe performance numbers in this section are gathered using Processor SDK 5.2 release.r*jj*jj'jjj}r*(j]j]j]j]j]ujMjhj]r*jXUThe performance numbers in this section are gathered using Processor SDK 5.2 release.r*r*}r*(jj*jj*ubaubj)r*}r*(jUjj*jj'jjj}r*(j]j]j]j]r*Uipc-average-round-trip-timer*aj]r*j,aujMjhj]r*(j)r*}r*(jXIPC Average Round Trip Timer*jj*jj'jjj}r*(j]j]j]j]j]ujMjhj]r*jXIPC Average Round Trip Timer*r*}r*(jj*jj*ubaubj)r*}r+(jXThe average round trip time is measured using MessageQBench which calculates the time for sending 1000 messages from the main processor to slave core and divided by the number of messages sent (1000).r+jj*jj'jjj}r+(j]j]j]j]j]ujMjhj]r+jXThe average round trip time is measured using MessageQBench which calculates the time for sending 1000 messages from the main processor to slave core and divided by the number of messages sent (1000).r+r+}r+(jj+jj*ubaubj)r+}r+(jX=Average Round Trip Time (ARTT) for K2H/E/G and OMAP-L138 EVMsr +jj*jj'jjj}r +(j]j]j]j]j]ujM"jhj]r +jX=Average Round Trip Time (ARTT) for K2H/E/G and OMAP-L138 EVMsr +r +}r+(jj +jj+ubaubjy )r+}r+(jUjj*jj'jj j}r+(j]j]j]j]j]ujNjhj]r+j~ )r+}r+(jUj}r+(j]j]j]j]j]UcolsKujj+j]r+(j )r+}r+(jUj}r+(j]j]j]j]j]UcolwidthKujj+j]jj ubj )r+}r+(jUj}r+(j]j]j]j]j]UcolwidthKujj+j]jj ubj )r+}r+(jUj}r+(j]j]j]j]j]UcolwidthKujj+j]jj ubj )r +}r!+(jUj}r"+(j]j]j]j]j]UcolwidthKujj+j]jj ubj )r#+}r$+(jUj}r%+(j]j]j]j]j]UcolwidthKujj+j]jj ubj )r&+}r'+(jUj}r(+(j]j]j]j]j]ujj+j]r)+j )r*+}r++(jUj}r,+(j]j]j]j]j]ujj&+j]r-+(j )r.+}r/+(jUj}r0+(j]j]j]j]j]ujj*+j]r1+j)r2+}r3+(jX PLSDK 5.2r4+jj.+jj'jjj}r5+(j]j]j]j]j]ujKj]r6+jX PLSDK 5.2r7+r8+}r9+(jj4+jj2+ubaubajj ubj )r:+}r;+(jUj}r<+(j]j]j]j]j]ujj*+j]r=+j)r>+}r?+(jXK2Hr@+jj:+jj'jjj}rA+(j]j]j]j]j]ujKj]rB+jXK2HrC+rD+}rE+(jj@+jj>+ubaubajj ubj )rF+}rG+(jUj}rH+(j]j]j]j]j]ujj*+j]rI+j)rJ+}rK+(jXK2ErL+jjF+jj'jjj}rM+(j]j]j]j]j]ujKj]rN+jXK2ErO+rP+}rQ+(jjL+jjJ+ubaubajj ubj )rR+}rS+(jUj}rT+(j]j]j]j]j]ujj*+j]rU+j)rV+}rW+(jXK2GrX+jjR+jj'jjj}rY+(j]j]j]j]j]ujKj]rZ+jXK2Gr[+r\+}r]+(jjX+jjV+ubaubajj ubj )r^+}r_+(jUj}r`+(j]j]j]j]j]ujj*+j]ra+j)rb+}rc+(jX OMAP-L138rd+jj^+jj'jjj}re+(j]j]j]j]j]ujKj]rf+jX OMAP-L138rg+rh+}ri+(jjd+jjb+ubaubajj ubejj ubajj ubj )rj+}rk+(jUj}rl+(j]j]j]j]j]ujj+j]rm+(j )rn+}ro+(jUj}rp+(j]j]j]j]j]ujjj+j]rq+(j )rr+}rs+(jUj}rt+(j]j]j]j]j]ujjn+j]ru+j)rv+}rw+(jX CPU Speedrx+jjr+jj'jjj}ry+(j]j]j]j]j]ujKj]rz+jX CPU Speedr{+r|+}r}+(jjx+jjv+ubaubajj ubj )r~+}r+(jUj}r+(j]j]j]j]j]ujjn+j]r+j)r+}r+(jX1.2GHzr+jj~+jj'jjj}r+(j]j]j]j]j]ujKj]r+jX1.2GHzr+r+}r+(jj+jj+ubaubajj ubj )r+}r+(jUj}r+(j]j]j]j]j]ujjn+j]r+j)r+}r+(jX1.4GHzr+jj+jj'jjj}r+(j]j]j]j]j]ujKj]r+jX1.4GHzr+r+}r+(jj+jj+ubaubajj ubj )r+}r+(jUj}r+(j]j]j]j]j]ujjn+j]r+j)r+}r+(jX1GHzr+jj+jj'jjj}r+(j]j]j]j]j]ujKj]r+jX1GHzr+r+}r+(jj+jj+ubaubajj ubj )r+}r+(jUj}r+(j]j]j]j]j]ujjn+j]r+j)r+}r+(jX456MHzr+jj+jj'jjj}r+(j]j]j]j]j]ujKj]r+jX456MHzr+r+}r+(jj+jj+ubaubajj ubejj ubj )r+}r+(jUj}r+(j]j]j]j]j]ujjj+j]r+(j )r+}r+(jUj}r+(j]j]j]j]j]ujj+j]r+j)r+}r+(jX ARTT (us)r+jj+jj'jjj}r+(j]j]j]j]j]ujKj]r+jX ARTT (us)r+r+}r+(jj+jj+ubaubajj ubj )r+}r+(jUj}r+(j]j]j]j]j]ujj+j]r+j)r+}r+(jX115r+jj+jj'jjj}r+(j]j]j]j]j]ujKj]r+jX115r+r+}r+(jj+jj+ubaubajj ubj )r+}r+(jUj}r+(j]j]j]j]j]ujj+j]r+j)r+}r+(jX68r+jj+jj'jjj}r+(j]j]j]j]j]ujKj]r+jX68r+r+}r+(jj+jj+ubaubajj ubj )r+}r+(jUj}r+(j]j]j]j]j]ujj+j]r+j)r+}r+(jX81r+jj+jj'jjj}r+(j]j]j]j]j]ujKj]r+jX81r+r+}r+(jj+jj+ubaubajj ubj )r+}r+(jUj}r+(j]j]j]j]j]ujj+j]r+j)r+}r+(jX904r+jj+jj'jjj}r+(j]j]j]j]j]ujKj]r+jX904r+r+}r+(jj+jj+ubaubajj ubejj ubj )r+}r+(jUj}r+(j]j]j]j]j]ujjj+j]r+(j )r+}r+(jUj}r+(j]j]j]j]j]ujj+j]r+j)r+}r+(jXARTT @ 1GHz (us)r+jj+jj'jjj}r+(j]j]j]j]j]ujKj]r+jXARTT @ 1GHz (us)r+r+}r+(jj+jj+ubaubajj ubj )r+}r+(jUj}r,(j]j]j]j]j]ujj+j]r,j)r,}r,(jX121r,jj+jj'jjj}r,(j]j]j]j]j]ujKj]r,jX121r,r,}r ,(jj,jj,ubaubajj ubj )r ,}r ,(jUj}r ,(j]j]j]j]j]ujj+j]r ,j)r,}r,(jX94r,jj ,jj'jjj}r,(j]j]j]j]j]ujKj]r,jX94r,r,}r,(jj,jj,ubaubajj ubj )r,}r,(jUj}r,(j]j]j]j]j]ujj+j]r,j)r,}r,(jX81r,jj,jj'jjj}r,(j]j]j]j]j]ujKj]r,jX81r,r ,}r!,(jj,jj,ubaubajj ubj )r",}r#,(jUj}r$,(j]j]j]j]j]ujj+j]r%,j)r&,}r',(jXN/Ar(,jj",jj'jjj}r),(j]j]j]j]j]ujKj]r*,jXN/Ar+,r,,}r-,(jj(,jj&,ubaubajj ubejj ubejj ubejj ubaubj)r.,}r/,(jX)Table: IPC Average Round Trip Time (ARTT)r0,jj*jj'jjj}r1,(j]j]j]j]j]ujM+jhj]r2,jX)Table: IPC Average Round Trip Time (ARTT)r3,r4,}r5,(jj0,jj.,ubaubj)r6,}r7,(jXThe MessageQBench is a user space application which needs to call into kernel space and involves linux context switch, process priority, and multiple copies during the delivery of a message. Each message may show different latency deviated from the average round trip time.jj*jj'jjj}r8,(j]j]j]j]j]ujNjhj]r9,j)r:,}r;,(jXThe MessageQBench is a user space application which needs to call into kernel space and involves linux context switch, process priority, and multiple copies during the delivery of a message. Each message may show different latency deviated from the average round trip time.r<,jj6,jj'jjj}r=,(j]j]j]j]j]ujM.j]r>,jXThe MessageQBench is a user space application which needs to call into kernel space and involves linux context switch, process priority, and multiple copies during the delivery of a message. Each message may show different latency deviated from the average round trip time.r?,r@,}rA,(jj<,jj:,ubaubaubeubj)rB,}rC,(jUjj*jj'jjj}rD,(j]j]j]j]rE,U throughputrF,aj]rG,hHaujM5jhj]rH,(j)rI,}rJ,(jX ThroughputrK,jjB,jj'jjj}rL,(j]j]j]j]j]ujM5jhj]rM,jX ThroughputrN,rO,}rP,(jjK,jjI,ubaubj)rQ,}rR,(jXThroughput benchmark uses a max transmit window of 130 outstanding messages to get the maximum throughput. Beyond the max transit window of 130, there won't be enough resource to allocate additional messages before the resource is returned by the outstanding messages. In this case, the benchmark application will fail to run. Different payload sizes from 8 bytes to max of 448 bytes are measured for each direction, and the numbers apply to either direction. The throughput are measured with ARM/DSP running at 1 GHz.rS,jjB,jj'jjj}rT,(j]j]j]j]j]ujM7jhj]rU,jXThroughput benchmark uses a max transmit window of 130 outstanding messages to get the maximum throughput. Beyond the max transit window of 130, there won't be enough resource to allocate additional messages before the resource is returned by the outstanding messages. In this case, the benchmark application will fail to run. Different payload sizes from 8 bytes to max of 448 bytes are measured for each direction, and the numbers apply to either direction. The throughput are measured with ARM/DSP running at 1 GHz.rV,rW,}rX,(jjS,jjQ,ubaubj)rY,}rZ,(jX)Throughput for K2H/E/G and OMAP-L138 EVMsr[,jjB,jj'jjj}r\,(j]j]j]j]j]ujM?jhj]r],jX)Throughput for K2H/E/G and OMAP-L138 EVMsr^,r_,}r`,(jj[,jjY,ubaubjy )ra,}rb,(jUjjB,jj'jj j}rc,(j]j]j]j]j]ujNjhj]rd,j~ )re,}rf,(jUj}rg,(j]j]j]j]j]UcolsKujja,j]rh,(j )ri,}rj,(jUj}rk,(j]j]j]j]j]UcolwidthKujje,j]jj ubj )rl,}rm,(jUj}rn,(j]j]j]j]j]UcolwidthKujje,j]jj ubj )ro,}rp,(jUj}rq,(j]j]j]j]j]UcolwidthKujje,j]jj ubj )rr,}rs,(jUj}rt,(j]j]j]j]j]UcolwidthKujje,j]jj ubj )ru,}rv,(jUj}rw,(j]j]j]j]j]UcolwidthKujje,j]jj ubj )rx,}ry,(jUj}rz,(j]j]j]j]j]ujje,j]r{,j )r|,}r},(jUj}r~,(j]j]j]j]j]ujjx,j]r,(j )r,}r,(jUj}r,(j]j]j]j]j]ujj|,j]r,j)r,}r,(jXPayload (Bytes)r,jj,jj'jjj}r,(j]j]j]j]j]ujKj]r,jXPayload (Bytes)r,r,}r,(jj,jj,ubaubajj ubj )r,}r,(jUj}r,(j]j]j]j]j]ujj|,j]r,j)r,}r,(jX K2H (MB/s)r,jj,jj'jjj}r,(j]j]j]j]j]ujKj]r,jX K2H (MB/s)r,r,}r,(jj,jj,ubaubajj ubj )r,}r,(jUj}r,(j]j]j]j]j]ujj|,j]r,j)r,}r,(jX K2E (MB/s)r,jj,jj'jjj}r,(j]j]j]j]j]ujKj]r,jX K2E (MB/s)r,r,}r,(jj,jj,ubaubajj ubj )r,}r,(jUj}r,(j]j]j]j]j]ujj|,j]r,j)r,}r,(jX K2G (MB/s)r,jj,jj'jjj}r,(j]j]j]j]j]ujKj]r,jX K2G (MB/s)r,r,}r,(jj,jj,ubaubajj ubj )r,}r,(jUj}r,(j]j]j]j]j]ujj|,j]r,j)r,}r,(jXOMAP-L138 (MB/s)r,jj,jj'jjj}r,(j]j]j]j]j]ujKj]r,jXOMAP-L138 (MB/s)r,r,}r,(jj,jj,ubaubajj ubejj ubajj ubj )r,}r,(jUj}r,(j]j]j]j]j]ujje,j]r,(j )r,}r,(jUj}r,(j]j]j]j]j]ujj,j]r,(j )r,}r,(jUj}r,(j]j]j]j]j]ujj,j]r,j)r,}r,(jX8jj,jj'jjj}r,(j]j]j]j]j]ujKj]r,jX8r,}r,(jX8jj,ubaubajj ubj )r,}r,(jUj}r,(j]j]j]j]j]ujj,j]r,j)r,}r,(jX0.234r,jj,jj'jjj}r,(j]j]j]j]j]ujKj]r,jX0.234r,r,}r,(jj,jj,ubaubajj ubj )r,}r,(jUj}r,(j]j]j]j]j]ujj,j]r,j)r,}r,(jX0.442r,jj,jj'jjj}r,(j]j]j]j]j]ujKj]r,jX0.442r,r,}r,(jj,jj,ubaubajj ubj )r,}r,(jUj}r,(j]j]j]j]j]ujj,j]r,j)r,}r,(jX0.265r,jj,jj'jjj}r,(j]j]j]j]j]ujKj]r,jX0.265r,r,}r,(jj,jj,ubaubajj ubj )r,}r,(jUj}r,(j]j]j]j]j]ujj,j]r,j)r,}r,(jX0.065r,jj,jj'jjj}r,(j]j]j]j]j]ujKj]r,jX0.065r,r,}r,(jj,jj,ubaubajj ubejj ubj )r,}r,(jUj}r-(j]j]j]j]j]ujj,j]r-(j )r-}r-(jUj}r-(j]j]j]j]j]ujj,j]r-j)r-}r-(jX16r-jj-jj'jjj}r -(j]j]j]j]j]ujKj]r -jX16r -r -}r -(jj-jj-ubaubajj ubj )r-}r-(jUj}r-(j]j]j]j]j]ujj,j]r-j)r-}r-(jX0.362r-jj-jj'jjj}r-(j]j]j]j]j]ujKj]r-jX0.362r-r-}r-(jj-jj-ubaubajj ubj )r-}r-(jUj}r-(j]j]j]j]j]ujj,j]r-j)r-}r-(jX0.681r -jj-jj'jjj}r!-(j]j]j]j]j]ujKj]r"-jX0.681r#-r$-}r%-(jj -jj-ubaubajj ubj )r&-}r'-(jUj}r(-(j]j]j]j]j]ujj,j]r)-j)r*-}r+-(jX0.333r,-jj&-jj'jjj}r--(j]j]j]j]j]ujKj]r.-jX0.333r/-r0-}r1-(jj,-jj*-ubaubajj ubj )r2-}r3-(jUj}r4-(j]j]j]j]j]ujj,j]r5-j)r6-}r7-(jX0.099r8-jj2-jj'jjj}r9-(j]j]j]j]j]ujKj]r:-jX0.099r;-r<-}r=-(jj8-jj6-ubaubajj ubejj ubj )r>-}r?-(jUj}r@-(j]j]j]j]j]ujj,j]rA-(j )rB-}rC-(jUj}rD-(j]j]j]j]j]ujj>-j]rE-j)rF-}rG-(jX32rH-jjB-jj'jjj}rI-(j]j]j]j]j]ujKj]rJ-jX32rK-rL-}rM-(jjH-jjF-ubaubajj ubj )rN-}rO-(jUj}rP-(j]j]j]j]j]ujj>-j]rQ-j)rR-}rS-(jX0.599rT-jjN-jj'jjj}rU-(j]j]j]j]j]ujKj]rV-jX0.599rW-rX-}rY-(jjT-jjR-ubaubajj ubj )rZ-}r[-(jUj}r\-(j]j]j]j]j]ujj>-j]r]-j)r^-}r_-(jX1.078r`-jjZ-jj'jjj}ra-(j]j]j]j]j]ujKj]rb-jX1.078rc-rd-}re-(jj`-jj^-ubaubajj ubj )rf-}rg-(jUj}rh-(j]j]j]j]j]ujj>-j]ri-j)rj-}rk-(jX0.548rl-jjf-jj'jjj}rm-(j]j]j]j]j]ujKj]rn-jX0.548ro-rp-}rq-(jjl-jjj-ubaubajj ubj )rr-}rs-(jUj}rt-(j]j]j]j]j]ujj>-j]ru-j)rv-}rw-(jX0.163rx-jjr-jj'jjj}ry-(j]j]j]j]j]ujKj]rz-jX0.163r{-r|-}r}-(jjx-jjv-ubaubajj ubejj ubj )r~-}r-(jUj}r-(j]j]j]j]j]ujj,j]r-(j )r-}r-(jUj}r-(j]j]j]j]j]ujj~-j]r-j)r-}r-(jX64r-jj-jj'jjj}r-(j]j]j]j]j]ujKj]r-jX64r-r-}r-(jj-jj-ubaubajj ubj )r-}r-(jUj}r-(j]j]j]j]j]ujj~-j]r-j)r-}r-(jX1.073r-jj-jj'jjj}r-(j]j]j]j]j]ujKj]r-jX1.073r-r-}r-(jj-jj-ubaubajj ubj )r-}r-(jUj}r-(j]j]j]j]j]ujj~-j]r-j)r-}r-(jX1.928r-jj-jj'jjj}r-(j]j]j]j]j]ujKj]r-jX1.928r-r-}r-(jj-jj-ubaubajj ubj )r-}r-(jUj}r-(j]j]j]j]j]ujj~-j]r-j)r-}r-(jX1.101r-jj-jj'jjj}r-(j]j]j]j]j]ujKj]r-jX1.101r-r-}r-(jj-jj-ubaubajj ubj )r-}r-(jUj}r-(j]j]j]j]j]ujj~-j]r-j)r-}r-(jX0.286r-jj-jj'jjj}r-(j]j]j]j]j]ujKj]r-jX0.286r-r-}r-(jj-jj-ubaubajj ubejj ubj )r-}r-(jUj}r-(j]j]j]j]j]ujj,j]r-(j )r-}r-(jUj}r-(j]j]j]j]j]ujj-j]r-j)r-}r-(jX128r-jj-jj'jjj}r-(j]j]j]j]j]ujKj]r-jX128r-r-}r-(jj-jj-ubaubajj ubj )r-}r-(jUj}r-(j]j]j]j]j]ujj-j]r-j)r-}r-(jX1.833r-jj-jj'jjj}r-(j]j]j]j]j]ujKj]r-jX1.833r-r-}r-(jj-jj-ubaubajj ubj )r-}r-(jUj}r-(j]j]j]j]j]ujj-j]r-j)r-}r-(jX3.57r-jj-jj'jjj}r-(j]j]j]j]j]ujKj]r-jX3.57r-r-}r-(jj-jj-ubaubajj ubj )r-}r-(jUj}r-(j]j]j]j]j]ujj-j]r-j)r-}r-(jX2.116r-jj-jj'jjj}r-(j]j]j]j]j]ujKj]r-jX2.116r-r-}r-(jj-jj-ubaubajj ubj )r-}r-(jUj}r-(j]j]j]j]j]ujj-j]r-j)r-}r-(jX0.524r-jj-jj'jjj}r-(j]j]j]j]j]ujKj]r-jX0.524r-r-}r-(jj-jj-ubaubajj ubejj ubj )r-}r-(jUj}r.(j]j]j]j]j]ujj,j]r.(j )r.}r.(jUj}r.(j]j]j]j]j]ujj-j]r.j)r.}r.(jX256r.jj.jj'jjj}r .(j]j]j]j]j]ujKj]r .jX256r .r .}r .(jj.jj.ubaubajj ubj )r.}r.(jUj}r.(j]j]j]j]j]ujj-j]r.j)r.}r.(jX3.288r.jj.jj'jjj}r.(j]j]j]j]j]ujKj]r.jX3.288r.r.}r.(jj.jj.ubaubajj ubj )r.}r.(jUj}r.(j]j]j]j]j]ujj-j]r.j)r.}r.(jX6.693r .jj.jj'jjj}r!.(j]j]j]j]j]ujKj]r".jX6.693r#.r$.}r%.(jj .jj.ubaubajj ubj )r&.}r'.(jUj}r(.(j]j]j]j]j]ujj-j]r).j)r*.}r+.(jX5.855r,.jj&.jj'jjj}r-.(j]j]j]j]j]ujKj]r..jX5.855r/.r0.}r1.(jj,.jj*.ubaubajj ubj )r2.}r3.(jUj}r4.(j]j]j]j]j]ujj-j]r5.j)r6.}r7.(jX0.988r8.jj2.jj'jjj}r9.(j]j]j]j]j]ujKj]r:.jX0.988r;.r<.}r=.(jj8.jj6.ubaubajj ubejj ubj )r>.}r?.(jUj}r@.(j]j]j]j]j]ujj,j]rA.(j )rB.}rC.(jUj}rD.(j]j]j]j]j]ujj>.j]rE.j)rF.}rG.(jX448(Max)rH.jjB.jj'jjj}rI.(j]j]j]j]j]ujKj]rJ.jX448(Max)rK.rL.}rM.(jjH.jjF.ubaubajj ubj )rN.}rO.(jUj}rP.(j]j]j]j]j]ujj>.j]rQ.j)rR.}rS.(jX5.038rT.jjN.jj'jjj}rU.(j]j]j]j]j]ujKj]rV.jX5.038rW.rX.}rY.(jjT.jjR.ubaubajj ubj )rZ.}r[.(jUj}r\.(j]j]j]j]j]ujj>.j]r].j)r^.}r_.(jX11.056r`.jjZ.jj'jjj}ra.(j]j]j]j]j]ujKj]rb.jX11.056rc.rd.}re.(jj`.jj^.ubaubajj ubj )rf.}rg.(jUj}rh.(j]j]j]j]j]ujj>.j]ri.j)rj.}rk.(jX18.967rl.jjf.jj'jjj}rm.(j]j]j]j]j]ujKj]rn.jX18.967ro.rp.}rq.(jjl.jjj.ubaubajj ubj )rr.}rs.(jUj}rt.(j]j]j]j]j]ujj>.j]ru.j)rv.}rw.(jX1.676rx.jjr.jj'jjj}ry.(j]j]j]j]j]ujKj]rz.jX1.676r{.r|.}r}.(jjx.jjv.ubaubajj ubejj ubejj ubejj ubaubj)r~.}r.(jXTable: IPC Throughputr.jjB,jj'jjj}r.(j]j]j]j]j]ujMLjhj]r.jXTable: IPC Throughputr.r.}r.(jj.jj~.ubaubeubj)r.}r.(jUjj*jj'jjj}r.(j]j]j]j]r.Uipc-throughput-cpu-utilizationr.aj]r.haujMOjhj]r.(j)r.}r.(jXIPC Throughput CPU Utilizationr.jj.jj'jjj}r.(j]j]j]j]j]ujMOjhj]r.jXIPC Throughput CPU Utilizationr.r.}r.(jj.jj.ubaubj)r.}r.(jXiThe CPU utilization is measured using max payload size of 448 bytes with transmit window of 130 messages.r.jj.jj'jjj}r.(j]j]j]j]j]ujMQjhj]r.jXiThe CPU utilization is measured using max payload size of 448 bytes with transmit window of 130 messages.r.r.}r.(jj.jj.ubaubjy )r.}r.(jUjj.jj'jj j}r.(j]j]j]j]j]ujNjhj]r.j~ )r.}r.(jUj}r.(j]j]j]j]j]UcolsKujj.j]r.(j )r.}r.(jUj}r.(j]j]j]j]j]UcolwidthKujj.j]jj ubj )r.}r.(jUj}r.(j]j]j]j]j]UcolwidthKujj.j]jj ubj )r.}r.(jUj}r.(j]j]j]j]j]UcolwidthKujj.j]jj ubj )r.}r.(jUj}r.(j]j]j]j]j]UcolwidthKujj.j]jj ubj )r.}r.(jUj}r.(j]j]j]j]j]UcolwidthKujj.j]jj ubj )r.}r.(jUj}r.(j]j]j]j]j]UcolwidthKujj.j]jj ubj )r.}r.(jUj}r.(j]j]j]j]j]UcolwidthKujj.j]jj ubj )r.}r.(jUj}r.(j]j]j]j]j]ujj.j]r.j )r.}r.(jUj}r.(j]j]j]j]j]ujj.j]r.(j )r.}r.(jUj}r.(j]j]j]j]j]ujj.j]jj ubj )r.}r.(jUj}r.(j]j]j]j]j]ujj.j]r.j)r.}r.(jX K2H (1.2GHz)r.jj.jj'jjj}r.(j]j]j]j]j]ujKj]r.jX K2H (1.2GHz)r.r.}r.(jj.jj.ubaubajj ubj )r.}r.(jUj}r.(j]j]j]j]j]ujj.j]r.j)r.}r.(jX K2E (1.4GHz)r.jj.jj'jjj}r.(j]j]j]j]j]ujKj]r.jX K2E (1.4GHz)r.r.}r.(jj.jj.ubaubajj ubj )r.}r.(jUj}r.(j]j]j]j]j]ujj.j]r.j)r.}r.(jX K2H (1GHz)r.jj.jj'jjj}r.(j]j]j]j]j]ujKj]r.jX K2H (1GHz)r.r.}r.(jj.jj.ubaubajj ubj )r.}r.(jUj}r.(j]j]j]j]j]ujj.j]r.j)r.}r.(jX K2E (1GHz)r.jj.jj'jjj}r.(j]j]j]j]j]ujKj]r.jX K2E (1GHz)r.r.}r.(jj.jj.ubaubajj ubj )r.}r.(jUj}r.(j]j]j]j]j]ujj.j]r.j)r.}r.(jXK2Gr.jj.jj'jjj}r.(j]j]j]j]j]ujKj]r.jXK2Gr.r.}r/(jj.jj.ubaubajj ubj )r/}r/(jUj}r/(j]j]j]j]j]ujj.j]r/j)r/}r/(jX OMAP-L138r/jj/jj'jjj}r/(j]j]j]j]j]ujKj]r /jX OMAP-L138r /r /}r /(jj/jj/ubaubajj ubejj ubajj ubj )r /}r/(jUj}r/(j]j]j]j]j]ujj.j]r/j )r/}r/(jUj}r/(j]j]j]j]j]ujj /j]r/(j )r/}r/(jUj}r/(j]j]j]j]j]ujj/j]r/j)r/}r/(jXCPU Utilizationr/jj/jj'jjj}r/(j]j]j]j]j]ujKj]r/jXCPU Utilizationr/r/}r /(jj/jj/ubaubajj ubj )r!/}r"/(jUj}r#/(j]j]j]j]j]ujj/j]r$/j)r%/}r&/(jX42%r'/jj!/jj'jjj}r(/(j]j]j]j]j]ujKj]r)/jX42%r*/r+/}r,/(jj'/jj%/ubaubajj ubj )r-/}r./(jUj}r//(j]j]j]j]j]ujj/j]r0/j)r1/}r2/(jX47%r3/jj-/jj'jjj}r4/(j]j]j]j]j]ujKj]r5/jX47%r6/r7/}r8/(jj3/jj1/ubaubajj ubj )r9/}r:/(jUj}r;/(j]j]j]j]j]ujj/j]r/(jX44%r?/jj9/jj'jjj}r@/(j]j]j]j]j]ujKj]rA/jX44%rB/rC/}rD/(jj?/jj=/ubaubajj ubj )rE/}rF/(jUj}rG/(j]j]j]j]j]ujj/j]rH/j)rI/}rJ/(jX49%rK/jjE/jj'jjj}rL/(j]j]j]j]j]ujKj]rM/jX49%rN/rO/}rP/(jjK/jjI/ubaubajj ubj )rQ/}rR/(jUj}rS/(j]j]j]j]j]ujj/j]rT/j)rU/}rV/(jX89.5%rW/jjQ/jj'jjj}rX/(j]j]j]j]j]ujKj]rY/jX89.5%rZ/r[/}r\/(jjW/jjU/ubaubajj ubj )r]/}r^/(jUj}r_/(j]j]j]j]j]ujj/j]r`/j)ra/}rb/(jX100%rc/jj]/jj'jjj}rd/(j]j]j]j]j]ujKj]re/jX100%rf/rg/}rh/(jjc/jja/ubaubajj ubejj ubajj ubejj ubaubj)ri/}rj/(jX%Table: IPC Throughput CPU Utilizationrk/jj.jj'jjj}rl/(j]j]j]j]j]ujMYjhj]rm/jX%Table: IPC Throughput CPU Utilizationrn/ro/}rp/(jjk/jji/ubaubeubeubeubj)rq/}rr/(jUjjjjjjj}rs/(j]j]j]j]rt/Uipc-3-xru/aj]rv/haujKyjhj]rw/(j)rx/}ry/(jXIPC 3.xrz/jjq/jjjjj}r{/(j]j]j]j]j]ujKyjhj]r|/jXIPC 3.xr}/r~/}r/(jjz/jjx/ubaubj7)r/}r/(jX/http://processors.wiki.ti.com/index.php/IPC_3.xjjq/jj:X5source/rtos/PDK_Platform_Software/IPC/IPC_3.x.rst.incr/r/}r/bjj>j}r/(j@jAj]j]j]j]j]ujKjhj]r/jX/http://processors.wiki.ti.com/index.php/IPC_3.xr/r/}r/(jUjj/ubaubj)r/}r/(jUjKjjq/jj/jjj}r/(j]r/X introductionr/aj]j]j]r/Uid34r/aj]ujKjhj]r/(j)r/}r/(jX Introductionr/jj/jj/jjj}r/(j]j]j]j]j]ujKjhj]r/jX Introductionr/r/}r/(jj/jj/ubaubj)r/}r/(jXThis page contains details about the IPC 3.x product, TI's solution for interprocessor communication between cores on homogenous and heterogeneous devices.r/jj/jj/jjj}r/(j]j]j]j]j]ujKjhj]r/jXThis page contains details about the IPC 3.x product, TI's solution for interprocessor communication between cores on homogenous and heterogeneous devices.r/r/}r/(jj/jj/ubaubj)r/}r/(jXhIPC 3.x is an evolution of the IPC product, so it helps to understand the scope of previous generations.r/jj/jj/jjj}r/(j]j]j]j]j]ujK jhj]r/jXhIPC 3.x is an evolution of the IPC product, so it helps to understand the scope of previous generations.r/r/}r/(jj/jj/ubaubjt)r/}r/(jUjj/jj/jjwj}r/(jyX-j]j]j]j]j]ujK jhj]r/(j{)r/}r/(jX`The IPC product `__ defines `several interfaces `__ to facilitate multiprocessor communication.jj/jj/jjj}r/(j]j]j]j]j]ujNjhj]r/j)r/}r/(jX`The IPC product `__ defines `several interfaces `__ to facilitate multiprocessor communication.jj/jj/jjj}r/(j]j]j]j]j]ujK j]r/(j)r/}r/(jXg`The IPC product `__j}r/(UnameXThe IPC productjXQhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/index.htmlj]j]j]j]j]ujj/j]r/jXThe IPC productr/r/}r/(jUjj/ubajjubjX defines r/r/}r/(jX defines jj/ubj)r/}r/(jX`several interfaces `__j}r/(UnameXseveral interfacesjXjhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/index.htmlj]j]j]j]j]ujj/j]r/jXseveral interfacesr/r/}r/(jUjj/ubajjubjX, to facilitate multiprocessor communication.r/r/}r/(jX, to facilitate multiprocessor communication.jj/ubeubaubj{)r/}r/(jXThe IPC 1.x product includes implementations of those interfaces for the SYS/BIOS RTOS. It supports communicating between cores running SYS/BIOS, as well to HLOS processors running SysLink 2.x.jj/jj/jjj}r/(j]j]j]j]j]ujNjhj]r/j)r/}r/(jXThe IPC 1.x product includes implementations of those interfaces for the SYS/BIOS RTOS. It supports communicating between cores running SYS/BIOS, as well to HLOS processors running SysLink 2.x.r/jj/jj/jjj}r/(j]j]j]j]j]ujKj]r/jXThe IPC 1.x product includes implementations of those interfaces for the SYS/BIOS RTOS. It supports communicating between cores running SYS/BIOS, as well to HLOS processors running SysLink 2.x.r/r/}r/(jj/jj/ubaubaubj{)r/}r/(jXThe SysLink 2.x provides services to control slave processors (e.g. load, start, stop). It also provides an implementation of the IPC interfaces for High Level OSs (HLOS) like Linux and QNX. SysLink 2.x supports communicating with slave processors running SYS/BIOS and IPC 1.x. jj/jj/jjj}r/(j]j]j]j]j]ujNjhj]r/j)r/}r/(jXThe SysLink 2.x provides services to control slave processors (e.g. load, start, stop). It also provides an implementation of the IPC interfaces for High Level OSs (HLOS) like Linux and QNX. SysLink 2.x supports communicating with slave processors running SYS/BIOS and IPC 1.x.r/jj/jj/jjj}r/(j]j]j]j]j]ujKj]r/jXThe SysLink 2.x provides services to control slave processors (e.g. load, start, stop). It also provides an implementation of the IPC interfaces for High Level OSs (HLOS) like Linux and QNX. SysLink 2.x supports communicating with slave processors running SYS/BIOS and IPC 1.x.r/r/}r/(jj/jj/ubaubaubeubj)r/}r/(jXIPC 3.x merges the IPC 1.x and SysLink 2.x products, creating a single product that defines multiprocessor communication APIs and provides implementations for several OS's, including SYS/BIOS and HLOS's.r/jj/jj/jjj}r/(j]j]j]j]j]ujKjhj]r/jXIPC 3.x merges the IPC 1.x and SysLink 2.x products, creating a single product that defines multiprocessor communication APIs and provides implementations for several OS's, including SYS/BIOS and HLOS's.r/r/}r/(jj/jj/ubaubj)r/}r/(jXThe SysLink name is being retired. The SysLink 2.x product will not be supported on existing devices, and development has stopped and support for new devices will not be added.jj/jj/jjj}r/(j]j]j]j]j]ujNjhj]r/j)r/}r/(jXThe SysLink name is being retired. The SysLink 2.x product will not be supported on existing devices, and development has stopped and support for new devices will not be added.r/jj/jj/jjj}r/(j]j]j]j]j]ujKj]r/jXThe SysLink name is being retired. The SysLink 2.x product will not be supported on existing devices, and development has stopped and support for new devices will not be added.r/r/}r/(jj/jj/ubaubaubeubj)r/}r/(jUjjq/jj/jjj}r/(j]j]j]j]r/Uchangesr/aj]r/hIaujK%jhj]r/(j)r/}r/(jXChangesr/jj/jj/jjj}r0(j]j]j]j]j]ujK%jhj]r0jXChangesr0r0}r0(jj/jj/ubaubj)r0}r0(jXThe key changes between IPC 1.x/SysLink 2.x and IPC 3.x is the HLOS implementation. This table summarizes the IPC 1.x/SysLink 2.x supported APIs against those provided in IPC 3.x.r0jj/jj/jjj}r0(j]j]j]j]j]ujK'jhj]r 0jXThe key changes between IPC 1.x/SysLink 2.x and IPC 3.x is the HLOS implementation. This table summarizes the IPC 1.x/SysLink 2.x supported APIs against those provided in IPC 3.x.r 0r 0}r 0(jj0jj0ubaubjy )r 0}r0(jUjj/jj/jj j}r0(j]j]j]j]j]ujNjhj]r0j~ )r0}r0(jUj}r0(j]j]j]j]j]UcolsKujj 0j]r0(j )r0}r0(jUj}r0(j]j]j]j]j]UcolwidthKujj0j]jj ubj )r0}r0(jUj}r0(j]j]j]j]j]UcolwidthKujj0j]jj ubj )r0}r0(jUj}r0(j]j]j]j]j]UcolwidthKujj0j]jj ubj )r0}r0(jUj}r 0(j]j]j]j]j]ujj0j]r!0j )r"0}r#0(jUj}r$0(j]j]j]j]j]ujj0j]r%0(j )r&0}r'0(jUj}r(0(j]j]j]j]j]ujj"0j]r)0j)r*0}r+0(jXFeaturer,0jj&0jj/jjj}r-0(j]j]j]j]j]ujK,j]r.0jXFeaturer/0r00}r10(jj,0jj*0ubaubajj ubj )r20}r30(jUj}r40(j]j]j]j]j]ujj"0j]r50j)r60}r70(jXIPC 1.x/SysLink 2.xr80jj20jj/jjj}r90(j]j]j]j]j]ujK,j]r:0jXIPC 1.x/SysLink 2.xr;0r<0}r=0(jj80jj60ubaubajj ubj )r>0}r?0(jUj}r@0(j]j]j]j]j]ujj"0j]rA0j)rB0}rC0(jXIPC 3.xrD0jj>0jj/jjj}rE0(j]j]j]j]j]ujK,j]rF0jXIPC 3.xrG0rH0}rI0(jjD0jjB0ubaubajj ubejj ubajj ubj )rJ0}rK0(jUj}rL0(j]j]j]j]j]ujj0j]rM0(j )rN0}rO0(jUj}rP0(j]j]j]j]j]ujjJ0j]rQ0(j )rR0}rS0(jUj}rT0(j]j]j]j]j]ujjN0j]rU0j)rV0}rW0(jX Slave loadingrX0jjR0jj/jjj}rY0(j]j]j]j]j]ujK.j]rZ0jX Slave loadingr[0r\0}r]0(jjX0jjV0ubaubajj ubj )r^0}r_0(jUj}r`0(j]j]j]j]j]ujjN0j]ra0j)rb0}rc0(jXProcMgrrd0jj^0jj/jjj}re0(j]j]j]j]j]ujK.j]rf0jXProcMgrrg0rh0}ri0(jjd0jjb0ubaubajj ubj )rj0}rk0(jUj}rl0(j]j]j]j]j]ujjN0j]rm0j)rn0}ro0(jX9Slaves are loaded on demand, currently without a user APIrp0jjj0jj/jjj}rq0(j]j]j]j]j]ujK.j]rr0jX9Slaves are loaded on demand, currently without a user APIrs0rt0}ru0(jjp0jjn0ubaubajj ubejj ubj )rv0}rw0(jUj}rx0(j]j]j]j]j]ujjJ0j]ry0(j )rz0}r{0(jUj}r|0(j]j]j]j]j]ujjv0j]r}0j)r~0}r0(jXLow-level primitivesr0jjz0jj/jjj}r0(j]j]j]j]j]ujK2j]r0jXLow-level primitivesr0r0}r0(jj0jj~0ubaubajj ubj )r0}r0(jUj}r0(j]j]j]j]j]ujjv0j]r0j)r0}r0(jX2Notify, Heap*MP, Gate*MP, SharedRegion, NameServerr0jj0jj/jjj}r0(j]j]j]j]j]ujK2j]r0jX2Notify, Heap*MP, Gate*MP, SharedRegion, NameServerr0r0}r0(jj0jj0ubaubajj ubj )r0}r0(jUj}r0(j]j]j]j]j]ujjv0j]r0j)r0}r0(jXGAvailable for BIOS-to-BIOS communication, only GateMP available on HLOSr0jj0jj/jjj}r0(j]j]j]j]j]ujK2j]r0jXGAvailable for BIOS-to-BIOS communication, only GateMP available on HLOSr0r0}r0(jj0jj0ubaubajj ubejj ubj )r0}r0(jUj}r0(j]j]j]j]j]ujjJ0j]r0(j )r0}r0(jUj}r0(j]j]j]j]j]ujj0j]r0j)r0}r0(jX Messagingr0jj0jj/jjj}r0(j]j]j]j]j]ujK8j]r0jX Messagingr0r0}r0(jj0jj0ubaubajj ubj )r0}r0(jUj}r0(j]j]j]j]j]ujj0j]r0j)r0}r0(jXMessageQr0jj0jj/jjj}r0(j]j]j]j]j]ujK8j]r0jXMessageQr0r0}r0(jj0jj0ubaubajj ubj )r0}r0(jUj}r0(j]j]j]j]j]ujj0j]r0j)r0}r0(jXMessageQr0jj0jj/jjj}r0(j]j]j]j]j]ujK8j]r0jXMessageQr0r0}r0(jj0jj0ubaubajj ubejj ubj )r0}r0(jUj}r0(j]j]j]j]j]ujjJ0j]r0(j )r0}r0(jUj}r0(j]j]j]j]j]ujj0j]r0j)r0}r0(jXHigher level data passingr0jj0jj/jjj}r0(j]j]j]j]j]ujK:j]r0jXHigher level data passingr0r0}r0(jj0jj0ubaubajj ubj )r0}r0(jUj}r0(j]j]j]j]j]ujj0j]r0j)r0}r0(jXRingIO, FrameQr0jj0jj/jjj}r0(j]j]j]j]j]ujK:j]r0jXRingIO, FrameQr0r0}r0(jj0jj0ubaubajj ubj )r0}r0(jUj}r0(j]j]j]j]j]ujj0j]r0j)r0}r0(jXFNone, though IPC provides primitives to enable higher level frameworksr0jj0jj/jjj}r0(j]j]j]j]j]ujK:j]r0jXFNone, though IPC provides primitives to enable higher level frameworksr0r0}r0(jj0jj0ubaubajj ubejj ubejj ubejj ubaubj)r0}r0(jUjj/jj/jjj}r0(j]j]j]j]r0Ubiosr0aj]r0jaujKAjhj]r0(j)r0}r0(jXBIOSr0jj0jj/jjj}r0(j]j]j]j]j]ujKAjhj]r0jXBIOSr0r0}r0(jj0jj0ubaubj)r0}r0(jX`For BIOS-to-BIOS communication, the same features available in IPC 1.x are available in IPC 3.x.r0jj0jj/jjj}r1(j]j]j]j]j]ujKCjhj]r1jX`For BIOS-to-BIOS communication, the same features available in IPC 1.x are available in IPC 3.x.r1r1}r1(jj0jj0ubaubeubj)r1}r1(jUjKjj/jj/jjj}r1(j]r1ja)aj]j]j]r 1Uid35r 1aj]ujKGjhj]r 1(j)r 1}r 1(jXLinuxr1jj1jj/jjj}r1(j]j]j]j]j]ujKGjhj]r1jXLinuxr1r1}r1(jj1jj 1ubaubj)r1}r1(jXOn Linux, IPC 3.x is built upon services available (and evolving!) in the mainline Linux kernel (3.4+). These core services include remoteproc and rpmsg.r1jj1jj/jjj}r1(j]j]j]j]j]ujKIjhj]r1jXOn Linux, IPC 3.x is built upon services available (and evolving!) in the mainline Linux kernel (3.4+). These core services include remoteproc and rpmsg.r1r1}r1(jj1jj1ubaubj)r1}r1(jXjAbove those Linux services, a few key services from the IPC API (e.g. MessageQ) are provided in user mode.r1jj1jj/jjj}r1(j]j]j]j]j]ujKMjhj]r 1jXjAbove those Linux services, a few key services from the IPC API (e.g. MessageQ) are provided in user mode.r!1r"1}r#1(jj1jj1ubaubeubj)r$1}r%1(jUjKjj/jj/jjj}r&1(j]r'1Xqnxr(1aj]j]j]r)1Uid36r*1aj]ujKQjhj]r+1(j)r,1}r-1(jXQNXr.1jj$1jj/jjj}r/1(j]j]j]j]j]ujKQjhj]r01jXQNXr11r21}r31(jj.1jj,1ubaubj)r41}r51(jXbOn QNX, IPC 3.x provides feature parity to Linux. The QNX OS doesn't inherently provide primitives like Linux's 'remoteproc' and 'rpmsg', so IPC 3.x also includes a loader and rpmsg-compatible communication infrastructure. This rpmsg-compatible MessageQ implementation enables the same BIOS-side image to communicate with either Linux or QNX on the HLOS.r61jj$1jj/jjj}r71(j]j]j]j]j]ujKSjhj]r81jXbOn QNX, IPC 3.x provides feature parity to Linux. The QNX OS doesn't inherently provide primitives like Linux's 'remoteproc' and 'rpmsg', so IPC 3.x also includes a loader and rpmsg-compatible communication infrastructure. This rpmsg-compatible MessageQ implementation enables the same BIOS-side image to communicate with either Linux or QNX on the HLOS.r91r:1}r;1(jj61jj41ubaubeubeubj)r<1}r=1(jUjjq/jj/jjj}r>1(j]j]j]j]r?1U developmentr@1aj]rA1j=aujK[jhj]rB1(j)rC1}rD1(jX DevelopmentrE1jj<1jj/jjj}rF1(j]j]j]j]j]ujK[jhj]rG1jX DevelopmentrH1rI1}rJ1(jjE1jjC1ubaubj)rK1}rL1(jX?IPC 3.x development is being managed at https://git.ti.com/ipc.rM1jj<1jj/jjj}rN1(j]j]j]j]j]ujK]jhj]rO1(jX(IPC 3.x development is being managed at rP1rQ1}rR1(jX(IPC 3.x development is being managed at jjK1ubj)rS1}rT1(jXhttps://git.ti.com/ipcrU1j}rV1(UrefurijU1j]j]j]j]j]ujjK1j]rW1jXhttps://git.ti.com/ipcrX1rY1}rZ1(jUjjS1ubajjubjX.r[1}r\1(jX.jjK1ubeubeubj)r]1}r^1(jUjjq/jjjjj}r_1(j]j]j]j]r`1Uresource-custom-tablera1aj]rb1haujK}jhj]rc1(j)rd1}re1(jXResource Custom Tablerf1jj]1jjjjj}rg1(j]j]j]j]j]ujK}jhj]rh1jXResource Custom Tableri1rj1}rk1(jjf1jjd1ubaubj7)rl1}rm1(jX@http://processors.wiki.ti.com/index.php/IPC_Resource_customTablejj]1jj:XFsource/rtos/PDK_Platform_Software/IPC/IPC_Resource_customTable.rst.incrn1ro1}rp1bjj>j}rq1(j@jAj]j]j]j]j]ujKjhj]rr1jX@http://processors.wiki.ti.com/index.php/IPC_Resource_customTablers1rt1}ru1(jUjjl1ubaubj)rv1}rw1(jUjKjj]1jjo1jjj}rx1(j]ry1X introductionrz1aj]j]j]r{1Uid37r|1aj]ujKjhj]r}1(j)r~1}r1(jX Introductionr1jjv1jjo1jjj}r1(j]j]j]j]j]ujKjhj]r1jX Introductionr1r1}r1(jj1jj~1ubaubj)r1}r1(jXThe IPC 3.x product introduced support for loading slave images which include a `Linux-defined resource table `__. In IPC 3.00.01, `IPC added the ability `__ for users to override the default resource table with their own. This article describes the mechanics involved to do that.jjv1jjo1jjj}r1(j]j]j]j]j]ujKjhj]r1(jXPThe IPC 3.x product introduced support for loading slave images which include a r1r1}r1(jXPThe IPC 3.x product introduced support for loading slave images which include a jj1ubj)r1}r1(jXB`Linux-defined resource table `__j}r1(UnameXLinux-defined resource tablejXhttp://lwn.net/Articles/489009/j]j]j]j]j]ujj1j]r1jXLinux-defined resource tabler1r1}r1(jUjj1ubajjubjX. In IPC 3.00.01, r1r1}r1(jX. In IPC 3.00.01, jj1ubj)r1}r1(jX`IPC added the ability `__j}r1(UnameXIPC added the abilityjXmhttp://git.ti.com/cgit/cgit.cgi/ipc/ipcdev.git/commit/?h=ipc-next&id=44169db6cd6f02193acf7ee97c13f956f599431dj]j]j]j]j]ujj1j]r1jXIPC added the abilityr1r1}r1(jUjj1ubajjubjX{ for users to override the default resource table with their own. This article describes the mechanics involved to do that.r1r1}r1(jX{ for users to override the default resource table with their own. This article describes the mechanics involved to do that.jj1ubeubj)r1}r1(jXoAlthough the Linux community defined the resource table, the IPC port to QNX also uses the same resource table.jjv1jjo1jjj}r1(j]j]j]j]j]ujNjhj]r1j)r1}r1(jXoAlthough the Linux community defined the resource table, the IPC port to QNX also uses the same resource table.r1jj1jjo1jjj}r1(j]j]j]j]j]ujK j]r1jXoAlthough the Linux community defined the resource table, the IPC port to QNX also uses the same resource table.r1r1}r1(jj1jj1ubaubaubj)r1}r1(jXYThis is an expert technique. Most users do not need to modify the default resource table.jjv1jjo1jjj}r1(j]j]j]j]j]ujNjhj]r1j)r1}r1(jXYThis is an expert technique. Most users do not need to modify the default resource table.r1jj1jjo1jjj}r1(j]j]j]j]j]ujKj]r1jXYThis is an expert technique. Most users do not need to modify the default resource table.r1r1}r1(jj1jj1ubaubaubeubj)r1}r1(jUjKjj]1jjo1jjj}r1(j]r1Xconfigr1aj]j]j]r1Uid38r1aj]ujKjhj]r1(j)r1}r1(jXConfigr1jj1jjo1jjj}r1(j]j]j]j]j]ujKjhj]r1jXConfigr1r1}r1(jj1jj1ubaubj)r1}r1(jXTo indicate you want to provide your own resource table, you need to set the ``Resource.customTable`` config parameter ``true``.jj1jjo1jjj}r1(j]j]j]j]j]ujKjhj]r1(jXMTo indicate you want to provide your own resource table, you need to set the r1r1}r1(jXMTo indicate you want to provide your own resource table, you need to set the jj1ubj)r1}r1(jX``Resource.customTable``j}r1(j]j]j]j]j]ujj1j]r1jXResource.customTabler1r1}r1(jUjj1ubajjubjX config parameter r1r1}r1(jX config parameter jj1ubj)r1}r1(jX``true``j}r1(j]j]j]j]j]ujj1j]r1jXtruer1r1}r1(jUjj1ubajjubjX.r1}r1(jX.jj1ubeubj)r1}r1(jX/* Override the default resource table with my own */ var Resource = xdc.useModule('ti.ipc.remoteproc.Resource'); Resource.customTable = true;jj1jjo1jjj}r1(j@jAj]j]j]j]j]ujMojhj]r1jX/* Override the default resource table with my own */ var Resource = xdc.useModule('ti.ipc.remoteproc.Resource'); Resource.customTable = true;r1r1}r1(jUjj1ubaubj)r1}r1(jXWhen ``Resource.customtable`` is set to ``true``, IPC will no longer generate a default table, and the user will be able to supply their own table using a specially-named C struct, ``ti_ipc_remoteproc_ResourceTable``.jj1jjo1jjj}r1(j]j]j]j]j]ujKjhj]r1(jXWhen r1r1}r1(jXWhen jj1ubj)r1}r1(jX``Resource.customtable``j}r1(j]j]j]j]j]ujj1j]r1jXResource.customtabler1r1}r1(jUjj1ubajjubjX is set to r1r1}r1(jX is set to jj1ubj)r1}r1(jX``true``j}r1(j]j]j]j]j]ujj1j]r1jXtruer1r2}r2(jUjj1ubajjubjX, IPC will no longer generate a default table, and the user will be able to supply their own table using a specially-named C struct, r2r2}r2(jX, IPC will no longer generate a default table, and the user will be able to supply their own table using a specially-named C struct, jj1ubj)r2}r2(jX#``ti_ipc_remoteproc_ResourceTable``j}r2(j]j]j]j]j]ujj1j]r2jXti_ipc_remoteproc_ResourceTabler 2r 2}r 2(jUjj2ubajjubjX.r 2}r 2(jX.jj1ubeubeubj)r2}r2(jUjj]1jjo1jjj}r2(j]j]j]j]r2Uc-coder2aj]r2haujK%jhj]r2(j)r2}r2(jXC Coder2jj2jjo1jjj}r2(j]j]j]j]j]ujK%jhj]r2jXC Coder2r2}r2(jj2jj2ubaubj)r2}r2(jX,The user-supplied resource table is a C structure named ``ti_ipc_remoteproc_ResourceTable`` that needs to be linked into the slave executable. The platform-specific default resource tables are provided in IPC's **packages/ti/ip/remoteproc/rsc_table_*.h**, and are the recommended place to start from.jj2jjo1jjj}r2(j]j]j]j]j]ujK&jhj]r 2(jX8The user-supplied resource table is a C structure named r!2r"2}r#2(jX8The user-supplied resource table is a C structure named jj2ubj)r$2}r%2(jX#``ti_ipc_remoteproc_ResourceTable``j}r&2(j]j]j]j]j]ujj2j]r'2jXti_ipc_remoteproc_ResourceTabler(2r)2}r*2(jUjj$2ubajjubjXx that needs to be linked into the slave executable. The platform-specific default resource tables are provided in IPC's r+2r,2}r-2(jXx that needs to be linked into the slave executable. The platform-specific default resource tables are provided in IPC's jj2ubj)r.2}r/2(jX+**packages/ti/ip/remoteproc/rsc_table_*.h**j}r02(j]j]j]j]j]ujj2j]r12jX'packages/ti/ip/remoteproc/rsc_table_*.hr22r32}r42(jUjj.2ubajjubjX., and are the recommended place to start from.r52r62}r72(jX., and are the recommended place to start from.jj2ubeubj)r82}r92(jXAfter finding the default resource table for your platform, you can copy the entirety of it into your own C file, compile it, and link it into your executable.r:2jj2jjo1jjj}r;2(j]j]j]j]j]ujK,jhj]r<2jXAfter finding the default resource table for your platform, you can copy the entirety of it into your own C file, compile it, and link it into your executable.r=2r>2}r?2(jj:2jj82ubaubj)r@2}rA2(jX~When configuring in a TYPE_TRACE element (a trace buffer) you must explicitly declare the symbol as an extern (as below). The trace buffer is generated during config, and unfortunately there is no header to #include that declares the name of this symbol. Also note the size of the trace buffer declared in the resource table must match the size you've specified in your .cfg script.jj2jjo1jjj}rB2(j]j]j]j]j]ujNjhj]rC2j)rD2}rE2(jX~When configuring in a TYPE_TRACE element (a trace buffer) you must explicitly declare the symbol as an extern (as below). The trace buffer is generated during config, and unfortunately there is no header to #include that declares the name of this symbol. Also note the size of the trace buffer declared in the resource table must match the size you've specified in your .cfg script.rF2jj@2jjo1jjj}rG2(j]j]j]j]j]ujK1j]rH2jX~When configuring in a TYPE_TRACE element (a trace buffer) you must explicitly declare the symbol as an extern (as below). The trace buffer is generated during config, and unfortunately there is no header to #include that declares the name of this symbol. Also note the size of the trace buffer declared in the resource table must match the size you've specified in your .cfg script.rI2rJ2}rK2(jjF2jjD2ubaubaubj)rL2}rM2(jXFor reference, here is an Vayu compatible resource table derived from **packages/ti/ipc/remoteproc/rsc_table_vayu_ipu.h**\ ( Disclaimer: This is a reference design only, and it is subject to enhancements, improvements and other changes without notifications).jj2jjo1jjj}rN2(j]j]j]j]j]ujK8jhj]rO2(jXFFor reference, here is an Vayu compatible resource table derived from rP2rQ2}rR2(jXFFor reference, here is an Vayu compatible resource table derived from jjL2ubj)rS2}rT2(jX3**packages/ti/ipc/remoteproc/rsc_table_vayu_ipu.h**j}rU2(j]j]j]j]j]ujjL2j]rV2jX/packages/ti/ipc/remoteproc/rsc_table_vayu_ipu.hrW2rX2}rY2(jUjjS2ubajjubjX( Disclaimer: This is a reference design only, and it is subject to enhancements, improvements and other changes without notifications).rZ2r[2}r\2(jX\ ( Disclaimer: This is a reference design only, and it is subject to enhancements, improvements and other changes without notifications).jjL2ubeubj)r]2}r^2(jX!#include "rsc_types.h" /* IPU Memory Map */ #define L4_DRA7XX_BASE 0x4A000000 /* L4_CFG & L4_WKUP */ #define L4_PERIPHERAL_L4CFG (L4_DRA7XX_BASE) #define IPU_PERIPHERAL_L4CFG 0x6A000000 #define L4_PERIPHERAL_L4PER1 0x48000000 #define IPU_PERIPHERAL_L4PER1 0x68000000 #define L4_PERIPHERAL_L4PER2 0x48400000 #define IPU_PERIPHERAL_L4PER2 0x68400000 #define L4_PERIPHERAL_L4PER3 0x48800000 #define IPU_PERIPHERAL_L4PER3 0x68800000 #define L4_PERIPHERAL_L4EMU 0x54000000 #define IPU_PERIPHERAL_L4EMU 0x74000000 #define L3_PERIPHERAL_PRUSS 0x4B200000 #define IPU_PERIPHERAL_PRUSS 0x6B200000 #define L3_PERIPHERAL_DMM 0x4E000000 #define IPU_PERIPHERAL_DMM 0x6E000000 #define L3_IVAHD_CONFIG 0x5A000000 #define IPU_IVAHD_CONFIG 0x7A000000 #define L3_IVAHD_SL2 0x5B000000 #define IPU_IVAHD_SL2 0x7B000000 #define L3_TILER_MODE_0_1 0x60000000 #define IPU_TILER_MODE_0_1 0xA0000000 #define L3_TILER_MODE_2 0x70000000 #define IPU_TILER_MODE_2 0xB0000000 #define L3_TILER_MODE_3 0x78000000 #define IPU_TILER_MODE_3 0xB8000000 #define L3_OCMC_RAM 0x40300000 #define IPU_OCMC_RAM 0x60300000 #define L3_EMIF_SDRAM 0xA0000000 #define IPU_EMIF_SDRAM 0x10000000 #define IPU_MEM_TEXT 0x0 #define IPU_MEM_DATA 0x80000000 #define IPU_MEM_IOBUFS 0x90000000 #define IPU_MEM_IPC_DATA 0x9F000000 #define IPU_MEM_IPC_VRING 0x60000000 #define IPU_MEM_RPMSG_VRING0 0x60000000 #define IPU_MEM_RPMSG_VRING1 0x60004000 #define IPU_MEM_VRING_BUFS0 0x60040000 #define IPU_MEM_VRING_BUFS1 0x60080000 #define IPU_MEM_IPC_VRING_SIZE SZ_1M #define IPU_MEM_IPC_DATA_SIZE SZ_1M #if defined(VAYU_IPU_1) #define IPU_MEM_TEXT_SIZE (SZ_1M) #elif defined(VAYU_IPU_2) #define IPU_MEM_TEXT_SIZE (SZ_1M * 6) #endif #if defined(VAYU_IPU_1) #define IPU_MEM_DATA_SIZE (SZ_1M * 5) #elif defined(VAYU_IPU_2) #define IPU_MEM_DATA_SIZE (SZ_1M * 48) #endif #define IPU_MEM_IOBUFS_SIZE (SZ_1M * 90) /* * Assign fixed RAM addresses to facilitate a fixed MMU table. * PHYS_MEM_IPC_VRING & PHYS_MEM_IPC_DATA MUST be together. */ /* See CMA BASE addresses in Linux side: arch/arm/mach-omap2/remoteproc.c */ #if defined(VAYU_IPU_1) #define PHYS_MEM_IPC_VRING 0x9D000000 #elif defined (VAYU_IPU_2) #define PHYS_MEM_IPC_VRING 0x95800000 #endif #define PHYS_MEM_IOBUFS 0xBA300000 /* * Sizes of the virtqueues (expressed in number of buffers supported, * and must be power of 2) */ #define IPU_RPMSG_VQ0_SIZE 256 #define IPU_RPMSG_VQ1_SIZE 256 /* flip up bits whose indices represent features we support */ #define RPMSG_IPU_C0_FEATURES 1 struct my_resource_table { struct resource_table base; UInt32 offset[21]; /* Should match 'num' in actual definition */ /* rpmsg vdev entry */ struct fw_rsc_vdev rpmsg_vdev; struct fw_rsc_vdev_vring rpmsg_vring0; struct fw_rsc_vdev_vring rpmsg_vring1; /* text carveout entry */ struct fw_rsc_carveout text_cout; /* data carveout entry */ struct fw_rsc_carveout data_cout; /* ipcdata carveout entry */ struct fw_rsc_carveout ipcdata_cout; /* trace entry */ struct fw_rsc_trace trace; /* devmem entry */ struct fw_rsc_devmem devmem0; /* devmem entry */ struct fw_rsc_devmem devmem1; /* devmem entry */ struct fw_rsc_devmem devmem2; /* devmem entry */ struct fw_rsc_devmem devmem3; /* devmem entry */ struct fw_rsc_devmem devmem4; /* devmem entry */ struct fw_rsc_devmem devmem5; /* devmem entry */ struct fw_rsc_devmem devmem6; /* devmem entry */ struct fw_rsc_devmem devmem7; /* devmem entry */ struct fw_rsc_devmem devmem8; /* devmem entry */ struct fw_rsc_devmem devmem9; /* devmem entry */ struct fw_rsc_devmem devmem10; /* devmem entry */ struct fw_rsc_devmem devmem11; /* devmem entry */ struct fw_rsc_devmem devmem12; /* devmem entry */ struct fw_rsc_devmem devmem13; /* devmem entry */ struct fw_rsc_devmem devmem14; /* devmem entry */ struct fw_rsc_devmem devmem15; }; extern char ti_trace_SysMin_Module_State_0_outbuf__A; #define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A #pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table") #pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096) struct my_resource_table ti_ipc_remoteproc_ResourceTable = { 1, /* we're the first version that implements this */ 21, /* number of entries in the table */ 0, 0, /* reserved, must be zero */ /* offsets to entries */ { offsetof(struct my_resource_table, rpmsg_vdev), offsetof(struct my_resource_table, text_cout), offsetof(struct my_resource_table, data_cout), offsetof(struct my_resource_table, ipcdata_cout), offsetof(struct my_resource_table, trace), offsetof(struct my_resource_table, devmem0), offsetof(struct my_resource_table, devmem1), offsetof(struct my_resource_table, devmem2), offsetof(struct my_resource_table, devmem3), offsetof(struct my_resource_table, devmem4), offsetof(struct my_resource_table, devmem5), offsetof(struct my_resource_table, devmem6), offsetof(struct my_resource_table, devmem7), offsetof(struct my_resource_table, devmem8), offsetof(struct my_resource_table, devmem9), offsetof(struct my_resource_table, devmem10), offsetof(struct my_resource_table, devmem11), offsetof(struct my_resource_table, devmem12), offsetof(struct my_resource_table, devmem13), offsetof(struct my_resource_table, devmem14), offsetof(struct my_resource_table, devmem15), }, /* rpmsg vdev entry */ { TYPE_VDEV, VIRTIO_ID_RPMSG, 0, RPMSG_IPU_C0_FEATURES, 0, 0, 0, 2, { 0, 0 }, /* no config data */ }, /* the two vrings */ { IPU_MEM_RPMSG_VRING0, 4096, IPU_RPMSG_VQ0_SIZE, 1, 0 }, { IPU_MEM_RPMSG_VRING1, 4096, IPU_RPMSG_VQ1_SIZE, 2, 0 }, { TYPE_CARVEOUT, IPU_MEM_TEXT, 0, IPU_MEM_TEXT_SIZE, 0, 0, "IPU_MEM_TEXT", }, { TYPE_CARVEOUT, IPU_MEM_DATA, 0, IPU_MEM_DATA_SIZE, 0, 0, "IPU_MEM_DATA", }, { TYPE_CARVEOUT, IPU_MEM_IPC_DATA, 0, IPU_MEM_IPC_DATA_SIZE, 0, 0, "IPU_MEM_IPC_DATA", }, { TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:sysm3", }, { TYPE_DEVMEM, IPU_MEM_IPC_VRING, PHYS_MEM_IPC_VRING, IPU_MEM_IPC_VRING_SIZE, 0, 0, "IPU_MEM_IPC_VRING", }, { TYPE_DEVMEM, IPU_MEM_IOBUFS, PHYS_MEM_IOBUFS, IPU_MEM_IOBUFS_SIZE, 0, 0, "IPU_MEM_IOBUFS", }, { TYPE_DEVMEM, IPU_TILER_MODE_0_1, L3_TILER_MODE_0_1, SZ_256M, 0, 0, "IPU_TILER_MODE_0_1", }, { TYPE_DEVMEM, IPU_TILER_MODE_2, L3_TILER_MODE_2, SZ_128M, 0, 0, "IPU_TILER_MODE_2", }, { TYPE_DEVMEM, IPU_TILER_MODE_3, L3_TILER_MODE_3, SZ_128M, 0, 0, "IPU_TILER_MODE_3", }, { TYPE_DEVMEM, IPU_PERIPHERAL_L4CFG, L4_PERIPHERAL_L4CFG, SZ_16M, 0, 0, "IPU_PERIPHERAL_L4CFG", }, { TYPE_DEVMEM, IPU_PERIPHERAL_L4PER1, L4_PERIPHERAL_L4PER1, SZ_2M, 0, 0, "IPU_PERIPHERAL_L4PER1", }, { TYPE_DEVMEM, IPU_PERIPHERAL_L4PER2, L4_PERIPHERAL_L4PER2, SZ_4M, 0, 0, "IPU_PERIPHERAL_L4PER2", }, { TYPE_DEVMEM, IPU_PERIPHERAL_L4PER3, L4_PERIPHERAL_L4PER3, SZ_8M, 0, 0, "IPU_PERIPHERAL_L4PER3", }, { TYPE_DEVMEM, IPU_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU, SZ_16M, 0, 0, "IPU_PERIPHERAL_L4EMU", }, { TYPE_DEVMEM, IPU_PERIPHERAL_PRUSS, L3_PERIPHERAL_PRUSS, SZ_1M, 0, 0, "IPU_PERIPHERAL_PRUSS", }, { TYPE_DEVMEM, IPU_IVAHD_CONFIG, L3_IVAHD_CONFIG, SZ_16M, 0, 0, "IPU_IVAHD_CONFIG", }, { TYPE_DEVMEM, IPU_IVAHD_SL2, L3_IVAHD_SL2, SZ_16M, 0, 0, "IPU_IVAHD_SL2", }, { TYPE_DEVMEM, IPU_PERIPHERAL_DMM, L3_PERIPHERAL_DMM, SZ_1M, 0, 0, "IPU_PERIPHERAL_DMM", }, { TYPE_DEVMEM, IPU_OCMC_RAM, L3_OCMC_RAM, SZ_4M, 0, 0, "IPU_OCMC_RAM", }, { TYPE_DEVMEM, IPU_EMIF_SDRAM, L3_EMIF_SDRAM, SZ_256M, 0, 0, "IPU_EMIF_SDRAM", }, };jj2jjo1jjj}r_2(jjXcj@jAj]j]j]j}j]j]ujK=jhj]r`2jX!#include "rsc_types.h" /* IPU Memory Map */ #define L4_DRA7XX_BASE 0x4A000000 /* L4_CFG & L4_WKUP */ #define L4_PERIPHERAL_L4CFG (L4_DRA7XX_BASE) #define IPU_PERIPHERAL_L4CFG 0x6A000000 #define L4_PERIPHERAL_L4PER1 0x48000000 #define IPU_PERIPHERAL_L4PER1 0x68000000 #define L4_PERIPHERAL_L4PER2 0x48400000 #define IPU_PERIPHERAL_L4PER2 0x68400000 #define L4_PERIPHERAL_L4PER3 0x48800000 #define IPU_PERIPHERAL_L4PER3 0x68800000 #define L4_PERIPHERAL_L4EMU 0x54000000 #define IPU_PERIPHERAL_L4EMU 0x74000000 #define L3_PERIPHERAL_PRUSS 0x4B200000 #define IPU_PERIPHERAL_PRUSS 0x6B200000 #define L3_PERIPHERAL_DMM 0x4E000000 #define IPU_PERIPHERAL_DMM 0x6E000000 #define L3_IVAHD_CONFIG 0x5A000000 #define IPU_IVAHD_CONFIG 0x7A000000 #define L3_IVAHD_SL2 0x5B000000 #define IPU_IVAHD_SL2 0x7B000000 #define L3_TILER_MODE_0_1 0x60000000 #define IPU_TILER_MODE_0_1 0xA0000000 #define L3_TILER_MODE_2 0x70000000 #define IPU_TILER_MODE_2 0xB0000000 #define L3_TILER_MODE_3 0x78000000 #define IPU_TILER_MODE_3 0xB8000000 #define L3_OCMC_RAM 0x40300000 #define IPU_OCMC_RAM 0x60300000 #define L3_EMIF_SDRAM 0xA0000000 #define IPU_EMIF_SDRAM 0x10000000 #define IPU_MEM_TEXT 0x0 #define IPU_MEM_DATA 0x80000000 #define IPU_MEM_IOBUFS 0x90000000 #define IPU_MEM_IPC_DATA 0x9F000000 #define IPU_MEM_IPC_VRING 0x60000000 #define IPU_MEM_RPMSG_VRING0 0x60000000 #define IPU_MEM_RPMSG_VRING1 0x60004000 #define IPU_MEM_VRING_BUFS0 0x60040000 #define IPU_MEM_VRING_BUFS1 0x60080000 #define IPU_MEM_IPC_VRING_SIZE SZ_1M #define IPU_MEM_IPC_DATA_SIZE SZ_1M #if defined(VAYU_IPU_1) #define IPU_MEM_TEXT_SIZE (SZ_1M) #elif defined(VAYU_IPU_2) #define IPU_MEM_TEXT_SIZE (SZ_1M * 6) #endif #if defined(VAYU_IPU_1) #define IPU_MEM_DATA_SIZE (SZ_1M * 5) #elif defined(VAYU_IPU_2) #define IPU_MEM_DATA_SIZE (SZ_1M * 48) #endif #define IPU_MEM_IOBUFS_SIZE (SZ_1M * 90) /* * Assign fixed RAM addresses to facilitate a fixed MMU table. * PHYS_MEM_IPC_VRING & PHYS_MEM_IPC_DATA MUST be together. */ /* See CMA BASE addresses in Linux side: arch/arm/mach-omap2/remoteproc.c */ #if defined(VAYU_IPU_1) #define PHYS_MEM_IPC_VRING 0x9D000000 #elif defined (VAYU_IPU_2) #define PHYS_MEM_IPC_VRING 0x95800000 #endif #define PHYS_MEM_IOBUFS 0xBA300000 /* * Sizes of the virtqueues (expressed in number of buffers supported, * and must be power of 2) */ #define IPU_RPMSG_VQ0_SIZE 256 #define IPU_RPMSG_VQ1_SIZE 256 /* flip up bits whose indices represent features we support */ #define RPMSG_IPU_C0_FEATURES 1 struct my_resource_table { struct resource_table base; UInt32 offset[21]; /* Should match 'num' in actual definition */ /* rpmsg vdev entry */ struct fw_rsc_vdev rpmsg_vdev; struct fw_rsc_vdev_vring rpmsg_vring0; struct fw_rsc_vdev_vring rpmsg_vring1; /* text carveout entry */ struct fw_rsc_carveout text_cout; /* data carveout entry */ struct fw_rsc_carveout data_cout; /* ipcdata carveout entry */ struct fw_rsc_carveout ipcdata_cout; /* trace entry */ struct fw_rsc_trace trace; /* devmem entry */ struct fw_rsc_devmem devmem0; /* devmem entry */ struct fw_rsc_devmem devmem1; /* devmem entry */ struct fw_rsc_devmem devmem2; /* devmem entry */ struct fw_rsc_devmem devmem3; /* devmem entry */ struct fw_rsc_devmem devmem4; /* devmem entry */ struct fw_rsc_devmem devmem5; /* devmem entry */ struct fw_rsc_devmem devmem6; /* devmem entry */ struct fw_rsc_devmem devmem7; /* devmem entry */ struct fw_rsc_devmem devmem8; /* devmem entry */ struct fw_rsc_devmem devmem9; /* devmem entry */ struct fw_rsc_devmem devmem10; /* devmem entry */ struct fw_rsc_devmem devmem11; /* devmem entry */ struct fw_rsc_devmem devmem12; /* devmem entry */ struct fw_rsc_devmem devmem13; /* devmem entry */ struct fw_rsc_devmem devmem14; /* devmem entry */ struct fw_rsc_devmem devmem15; }; extern char ti_trace_SysMin_Module_State_0_outbuf__A; #define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A #pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table") #pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096) struct my_resource_table ti_ipc_remoteproc_ResourceTable = { 1, /* we're the first version that implements this */ 21, /* number of entries in the table */ 0, 0, /* reserved, must be zero */ /* offsets to entries */ { offsetof(struct my_resource_table, rpmsg_vdev), offsetof(struct my_resource_table, text_cout), offsetof(struct my_resource_table, data_cout), offsetof(struct my_resource_table, ipcdata_cout), offsetof(struct my_resource_table, trace), offsetof(struct my_resource_table, devmem0), offsetof(struct my_resource_table, devmem1), offsetof(struct my_resource_table, devmem2), offsetof(struct my_resource_table, devmem3), offsetof(struct my_resource_table, devmem4), offsetof(struct my_resource_table, devmem5), offsetof(struct my_resource_table, devmem6), offsetof(struct my_resource_table, devmem7), offsetof(struct my_resource_table, devmem8), offsetof(struct my_resource_table, devmem9), offsetof(struct my_resource_table, devmem10), offsetof(struct my_resource_table, devmem11), offsetof(struct my_resource_table, devmem12), offsetof(struct my_resource_table, devmem13), offsetof(struct my_resource_table, devmem14), offsetof(struct my_resource_table, devmem15), }, /* rpmsg vdev entry */ { TYPE_VDEV, VIRTIO_ID_RPMSG, 0, RPMSG_IPU_C0_FEATURES, 0, 0, 0, 2, { 0, 0 }, /* no config data */ }, /* the two vrings */ { IPU_MEM_RPMSG_VRING0, 4096, IPU_RPMSG_VQ0_SIZE, 1, 0 }, { IPU_MEM_RPMSG_VRING1, 4096, IPU_RPMSG_VQ1_SIZE, 2, 0 }, { TYPE_CARVEOUT, IPU_MEM_TEXT, 0, IPU_MEM_TEXT_SIZE, 0, 0, "IPU_MEM_TEXT", }, { TYPE_CARVEOUT, IPU_MEM_DATA, 0, IPU_MEM_DATA_SIZE, 0, 0, "IPU_MEM_DATA", }, { TYPE_CARVEOUT, IPU_MEM_IPC_DATA, 0, IPU_MEM_IPC_DATA_SIZE, 0, 0, "IPU_MEM_IPC_DATA", }, { TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:sysm3", }, { TYPE_DEVMEM, IPU_MEM_IPC_VRING, PHYS_MEM_IPC_VRING, IPU_MEM_IPC_VRING_SIZE, 0, 0, "IPU_MEM_IPC_VRING", }, { TYPE_DEVMEM, IPU_MEM_IOBUFS, PHYS_MEM_IOBUFS, IPU_MEM_IOBUFS_SIZE, 0, 0, "IPU_MEM_IOBUFS", }, { TYPE_DEVMEM, IPU_TILER_MODE_0_1, L3_TILER_MODE_0_1, SZ_256M, 0, 0, "IPU_TILER_MODE_0_1", }, { TYPE_DEVMEM, IPU_TILER_MODE_2, L3_TILER_MODE_2, SZ_128M, 0, 0, "IPU_TILER_MODE_2", }, { TYPE_DEVMEM, IPU_TILER_MODE_3, L3_TILER_MODE_3, SZ_128M, 0, 0, "IPU_TILER_MODE_3", }, { TYPE_DEVMEM, IPU_PERIPHERAL_L4CFG, L4_PERIPHERAL_L4CFG, SZ_16M, 0, 0, "IPU_PERIPHERAL_L4CFG", }, { TYPE_DEVMEM, IPU_PERIPHERAL_L4PER1, L4_PERIPHERAL_L4PER1, SZ_2M, 0, 0, "IPU_PERIPHERAL_L4PER1", }, { TYPE_DEVMEM, IPU_PERIPHERAL_L4PER2, L4_PERIPHERAL_L4PER2, SZ_4M, 0, 0, "IPU_PERIPHERAL_L4PER2", }, { TYPE_DEVMEM, IPU_PERIPHERAL_L4PER3, L4_PERIPHERAL_L4PER3, SZ_8M, 0, 0, "IPU_PERIPHERAL_L4PER3", }, { TYPE_DEVMEM, IPU_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU, SZ_16M, 0, 0, "IPU_PERIPHERAL_L4EMU", }, { TYPE_DEVMEM, IPU_PERIPHERAL_PRUSS, L3_PERIPHERAL_PRUSS, SZ_1M, 0, 0, "IPU_PERIPHERAL_PRUSS", }, { TYPE_DEVMEM, IPU_IVAHD_CONFIG, L3_IVAHD_CONFIG, SZ_16M, 0, 0, "IPU_IVAHD_CONFIG", }, { TYPE_DEVMEM, IPU_IVAHD_SL2, L3_IVAHD_SL2, SZ_16M, 0, 0, "IPU_IVAHD_SL2", }, { TYPE_DEVMEM, IPU_PERIPHERAL_DMM, L3_PERIPHERAL_DMM, SZ_1M, 0, 0, "IPU_PERIPHERAL_DMM", }, { TYPE_DEVMEM, IPU_OCMC_RAM, L3_OCMC_RAM, SZ_4M, 0, 0, "IPU_OCMC_RAM", }, { TYPE_DEVMEM, IPU_EMIF_SDRAM, L3_EMIF_SDRAM, SZ_256M, 0, 0, "IPU_EMIF_SDRAM", }, };ra2rb2}rc2(jUjj]2ubaubj)rd2}re2(jXEYou can find 3 new TYPE_DEVMEM entries added in above resource table.rf2jj2jjo1jjj}rg2(j]j]j]j]j]ujMjhj]rh2jXEYou can find 3 new TYPE_DEVMEM entries added in above resource table.ri2rj2}rk2(jjf2jjd2ubaubjt)rl2}rm2(jUjj2jjo1jjwj}rn2(jyX-j]j]j]j]j]ujMjhj]ro2(j{)rp2}rq2(jXL3_PERIPHERAL_PRUSSrr2jjl2jjo1jjj}rs2(j]j]j]j]j]ujNjhj]rt2j)ru2}rv2(jjr2jjp2jjo1jjj}rw2(j]j]j]j]j]ujMj]rx2jXL3_PERIPHERAL_PRUSSry2rz2}r{2(jjr2jju2ubaubaubj{)r|2}r}2(jX IPU_OCMC_RAMr~2jjl2jjo1jjj}r2(j]j]j]j]j]ujNjhj]r2j)r2}r2(jj~2jj|2jjo1jjj}r2(j]j]j]j]j]ujMj]r2jX IPU_OCMC_RAMr2r2}r2(jj~2jj2ubaubaubj{)r2}r2(jXIPU_EMIF_SDRAM jjl2jjo1jjj}r2(j]j]j]j]j]ujNjhj]r2j)r2}r2(jXIPU_EMIF_SDRAMr2jj2jjo1jjj}r2(j]j]j]j]j]ujMj]r2jXIPU_EMIF_SDRAMr2r2}r2(jj2jj2ubaubaubeubj)r2}r2(jXAll ELF section placements (as well as the VRINGS, which aren’t in an ELF section) are placed in memory allocated from the remoteproc CMA area and are mapped to the virtual address as specified in the TYPE_CARVEOUT entries.r2jj2jjo1jjj}r2(j]j]j]j]j]ujMjhj]r2jXAll ELF section placements (as well as the VRINGS, which aren’t in an ELF section) are placed in memory allocated from the remoteproc CMA area and are mapped to the virtual address as specified in the TYPE_CARVEOUT entries.r2r2}r2(jj2jj2ubaubj)r2}r2(jX#The virtual addresses #defined are:r2jj2jjo1jjj}r2(j]j]j]j]j]ujMjhj]r2jX#The virtual addresses #defined are:r2r2}r2(jj2jj2ubaubj)r2}r2(jX#define IPU_MEM_TEXT 0x0 #define IPU_MEM_DATA 0x80000000 #define IPU_MEM_IOBUFS 0x90000000 #define IPU_MEM_IPC_DATA 0x9F000000 #define IPU_MEM_IPC_VRING 0x60000000jj2jjo1jjj}r2(jjXcj@jAj]j]j]j}j]j]ujMjhj]r2jX#define IPU_MEM_TEXT 0x0 #define IPU_MEM_DATA 0x80000000 #define IPU_MEM_IOBUFS 0x90000000 #define IPU_MEM_IPC_DATA 0x9F000000 #define IPU_MEM_IPC_VRING 0x60000000r2r2}r2(jUjj2ubaubj)r2}r2(jXJThe followings are fixed physical address to facilitate a fixed MMU table.r2jj2jjo1jjj}r2(j]j]j]j]j]ujMjhj]r2jXJThe followings are fixed physical address to facilitate a fixed MMU table.r2r2}r2(jj2jj2ubaubj)r2}r2(jX#if defined(VAYU_IPU_1) #define PHYS_MEM_IPC_VRING 0x9D000000 #elif defined (VAYU_IPU_2) #define PHYS_MEM_IPC_VRING 0x95800000 #endifjj2jjo1jjj}r2(jjXcj@jAj]j]j]j}j]j]ujMjhj]r2jX#if defined(VAYU_IPU_1) #define PHYS_MEM_IPC_VRING 0x9D000000 #elif defined (VAYU_IPU_2) #define PHYS_MEM_IPC_VRING 0x95800000 #endifr2r2}r2(jUjj2ubaubj)r2}r2(jXpThese PHYS_MEM values match exactly the physical address specified in the remoteproc CMA area in Linux DTS file:r2jj2jjo1jjj}r2(j]j]j]j]j]ujMjhj]r2jXpThese PHYS_MEM values match exactly the physical address specified in the remoteproc CMA area in Linux DTS file:r2r2}r2(jj2jj2ubaubj)r2}r2(jX>ipu2_cma_pool: ipu2_cma@95800000 { compatible = "shared-dma-pool"; reg = <0x95800000 0x3800000>; reusable; status = "okay"; }; ipu1_cma_pool: ipu1_cma@9d000000 { compatible = "shared-dma-pool"; reg = <0x9d000000 0x2000000>; reusable; status = "okay"; };jj2jjo1jjj}r2(j@jAj]j]j]j]j]ujM jhj]r2jX>ipu2_cma_pool: ipu2_cma@95800000 { compatible = "shared-dma-pool"; reg = <0x95800000 0x3800000>; reusable; status = "okay"; }; ipu1_cma_pool: ipu1_cma@9d000000 { compatible = "shared-dma-pool"; reg = <0x9d000000 0x2000000>; reusable; status = "okay"; };r2r2}r2(jUjj2ubaubj)r2}r2(jX'The 1st entry in the resource table is:r2jj2jjo1jjj}r2(j]j]j]j]j]ujMjhj]r2jX'The 1st entry in the resource table is:r2r2}r2(jj2jj2ubaubj)r2}r2(jX/* rpmsg vdev entry */ { TYPE_VDEV, VIRTIO_ID_RPMSG, 0, RPMSG_IPU_C0_FEATURES, 0, 0, 0, 2, { 0, 0 }, /* no config data */ }, /* the two vrings */ { IPU_MEM_RPMSG_VRING0, 4096, IPU_RPMSG_VQ0_SIZE, 1, 0 }, { IPU_MEM_RPMSG_VRING1, 4096, IPU_RPMSG_VQ1_SIZE, 2, 0 },jj2jjo1jjj}r2(jjXcj@jAj]j]j]j}j]j]ujMjhj]r2jX/* rpmsg vdev entry */ { TYPE_VDEV, VIRTIO_ID_RPMSG, 0, RPMSG_IPU_C0_FEATURES, 0, 0, 0, 2, { 0, 0 }, /* no config data */ }, /* the two vrings */ { IPU_MEM_RPMSG_VRING0, 4096, IPU_RPMSG_VQ0_SIZE, 1, 0 }, { IPU_MEM_RPMSG_VRING1, 4096, IPU_RPMSG_VQ1_SIZE, 2, 0 },r2r2}r2(jUjj2ubaubj)r2}r2(jXmThis tells remoteproc to allocate the vrings and vring buffers, and the remoteproc CMA area is used for this.r2jj2jjo1jjj}r2(j]j]j]j]j]ujMjhj]r2jXmThis tells remoteproc to allocate the vrings and vring buffers, and the remoteproc CMA area is used for this.r2r2}r2(jj2jj2ubaubj)r2}r2(jXThe 2nd-4th entries are:r2jj2jjo1jjj}r2(j]j]j]j]j]ujMjhj]r2jXThe 2nd-4th entries are:r2r2}r2(jj2jj2ubaubj)r2}r2(jX{ TYPE_CARVEOUT, IPU_MEM_TEXT, 0, IPU_MEM_TEXT_SIZE, 0, 0, "IPU_MEM_TEXT", }, { TYPE_CARVEOUT, IPU_MEM_DATA, 0, IPU_MEM_DATA_SIZE, 0, 0, "IPU_MEM_DATA", }, { TYPE_CARVEOUT, IPU_MEM_IPC_DATA, 0, IPU_MEM_IPC_DATA_SIZE, 0, 0, "IPU_MEM_IPC_DATA", },jj2jjo1jjj}r2(jjXcj@jAj]j]j]j}j]j]ujMjhj]r2jX{ TYPE_CARVEOUT, IPU_MEM_TEXT, 0, IPU_MEM_TEXT_SIZE, 0, 0, "IPU_MEM_TEXT", }, { TYPE_CARVEOUT, IPU_MEM_DATA, 0, IPU_MEM_DATA_SIZE, 0, 0, "IPU_MEM_DATA", }, { TYPE_CARVEOUT, IPU_MEM_IPC_DATA, 0, IPU_MEM_IPC_DATA_SIZE, 0, 0, "IPU_MEM_IPC_DATA", },r2r2}r2(jUjj2ubaubj)r2}r2(jXNThese carveouts tell remoteproc to allocate memory from its CMA area and map the allocated physical address to the virtual address specified in the carveout (the 1st field after TYPE_CARVEOUT), in the IPU’s MMU (“iommu” in Linux kernel parlance). These are for the ELF sections that are placed (mapped) in those virtual address.r2jj2jjo1jjj}r2(j]j]j]j]j]ujMjhj]r2jXNThese carveouts tell remoteproc to allocate memory from its CMA area and map the allocated physical address to the virtual address specified in the carveout (the 1st field after TYPE_CARVEOUT), in the IPU’s MMU (“iommu” in Linux kernel parlance). These are for the ELF sections that are placed (mapped) in those virtual address.r2r2}r2(jj2jj2ubaubj)r2}r2(jXjThe TYPE_TRACE entry tells remoteproc where the remote executable’s trace buffer is, using its C symbol.r2jj2jjo1jjj}r2(j]j]j]j]j]ujMjhj]r2jXjThe TYPE_TRACE entry tells remoteproc where the remote executable’s trace buffer is, using its C symbol.r2r2}r2(jj2jj2ubaubj)r2}r3(jXThe TYPE_DEVMEM entries are virtual <-> physical mappings. remoteproc just creates an IPU MMU mapping for the entry. The 1st TYPE_DEVMEM entry corresponds to the vrings and creates the IPU MMU mapping needed to access them from the IPU core:r3jj2jjo1jjj}r3(j]j]j]j]j]ujMjhj]r3jXThe TYPE_DEVMEM entries are virtual <-> physical mappings. remoteproc just creates an IPU MMU mapping for the entry. The 1st TYPE_DEVMEM entry corresponds to the vrings and creates the IPU MMU mapping needed to access them from the IPU core:r3r3}r3(jj3jj2ubaubj)r3}r3(jXw{ TYPE_DEVMEM, IPU_MEM_IPC_VRING, PHYS_MEM_IPC_VRING, IPU_MEM_IPC_VRING_SIZE, 0, 0, "IPU_MEM_IPC_VRING", },jj2jjo1jjj}r 3(jjXcj@jAj]j]j]j}j]j]ujMjhj]r 3jXw{ TYPE_DEVMEM, IPU_MEM_IPC_VRING, PHYS_MEM_IPC_VRING, IPU_MEM_IPC_VRING_SIZE, 0, 0, "IPU_MEM_IPC_VRING", },r 3r 3}r 3(jUjj3ubaubeubj)r3}r3(jUjj]1jjo1jjj}r3(j]j]j]j]r3Unew-type-devmem-entryr3aj]r3h aujMjhj]r3(j)r3}r3(jXNew TYPE_DEVMEM entryr3jj3jjo1jjj}r3(j]j]j]j]j]ujMjhj]r3jXNew TYPE_DEVMEM entryr3r3}r3(jj3jj3ubaubj)r3}r3(jXHTo add a new TYPE_DEVMEM entry, for example, to access PRU-ICSS from IPUr3jj3jjo1jjj}r 3(j]j]j]j]j]ujMjhj]r!3jXHTo add a new TYPE_DEVMEM entry, for example, to access PRU-ICSS from IPUr"3r#3}r$3(jj3jj3ubaubjt)r%3}r&3(jUjj3jjo1jjwj}r'3(jyX-j]j]j]j]j]ujMjhj]r(3j{)r)3}r*3(jXE1. specify the physical address of PRU-ICSS and its virutal address. jj%3jNjjj}r+3(j]j]j]j]j]ujNjhj]r,3j )r-3}r.3(jUj}r/3(jU.j]j]j]jUj]j]jjujj)3j]r03j{)r13}r23(jXBspecify the physical address of PRU-ICSS and its virutal address. j}r33(j]j]j]j]j]ujj-3j]r43j)r53}r63(jXAspecify the physical address of PRU-ICSS and its virutal address.r73jj13jjo1jjj}r83(j]j]j]j]j]ujMj]r93jXAspecify the physical address of PRU-ICSS and its virutal address.r:3r;3}r<3(jj73jj53ubaubajjubajj ubaubaubj)r=3}r>3(jXU#define L3_PERIPHERAL_PRUSS 0x4B200000 #define IPU_PERIPHERAL_PRUSS 0x6B200000jj3jjo1jjj}r?3(j@jAj]j]j]j]j]ujM\jhj]r@3jXU#define L3_PERIPHERAL_PRUSS 0x4B200000 #define IPU_PERIPHERAL_PRUSS 0x6B200000rA3rB3}rC3(jUjj=3ubaubjt)rD3}rE3(jUjj3jjo1jjwj}rF3(jyX-j]j]j]j]j]ujM jhj]rG3(j{)rH3}rI3(jXD2. increase size of **offset[X]** array in struct my_resource_table.jjD3jNjjj}rJ3(j]j]j]j]j]ujNjhj]rK3j )rL3}rM3(jUj}rN3(jU.UstartrO3Kj]j]j]jUj]j]jjujjH3j]rP3j{)rQ3}rR3(jXAincrease size of **offset[X]** array in struct my_resource_table.rS3j}rT3(j]j]j]j]j]ujjL3j]rU3j)rV3}rW3(jjS3jjQ3jjo1jjj}rX3(j]j]j]j]j]ujM j]rY3(jXincrease size of rZ3r[3}r\3(jXincrease size of jjV3ubj)r]3}r^3(jX **offset[X]**j}r_3(j]j]j]j]j]ujjV3j]r`3jX offset[X]ra3rb3}rc3(jUjj]3ubajjubjX# array in struct my_resource_table.rd3re3}rf3(jX# array in struct my_resource_table.jjV3ubeubajjubajj ubaubj{)rg3}rh3(jXN3. add new **struct fw_rsc_devmem devmemY** entry in struct my_resource_table.jjD3jjo1jjj}ri3(j]j]j]j]j]ujNjhj]rj3j)rk3}rl3(jXN3. add new **struct fw_rsc_devmem devmemY** entry in struct my_resource_table.jjg3jjo1jjj}rm3(j]j]j]j]j]ujM j]rn3(jX 3. add new ro3rp3}rq3(jX 3. add new jjk3ubj)rr3}rs3(jX **struct fw_rsc_devmem devmemY**j}rt3(j]j]j]j]j]ujjk3j]ru3jXstruct fw_rsc_devmem devmemYrv3rw3}rx3(jUjjr3ubajjubjX# entry in struct my_resource_table.ry3rz3}r{3(jX# entry in struct my_resource_table.jjk3ubeubaubj{)r|3}r}3(jXE4. increase **number** of entries in ti_ipc_remoteproc_ResourceTable.jjD3jNjjj}r~3(j]j]j]j]j]ujNjhj]r3j )r3}r3(jUj}r3(jU.jO3Kj]j]j]jUj]j]jjujj|3j]r3j{)r3}r3(jXBincrease **number** of entries in ti_ipc_remoteproc_ResourceTable.r3j}r3(j]j]j]j]j]ujj3j]r3j)r3}r3(jj3jj3jjo1jjj}r3(j]j]j]j]j]ujMj]r3(jX increase r3r3}r3(jX increase jj3ubj)r3}r3(jX **number**j}r3(j]j]j]j]j]ujj3j]r3jXnumberr3r3}r3(jUjj3ubajjubjX/ of entries in ti_ipc_remoteproc_ResourceTable.r3r3}r3(jX/ of entries in ti_ipc_remoteproc_ResourceTable.jj3ubeubajjubajj ubaubj{)r3}r3(jX\5. add a **offsetof(struct my_resource_table, devmemY)** in ti_ipc_remoteproc_ResourceTable.jjD3jjo1jjj}r3(j]j]j]j]j]ujNjhj]r3j)r3}r3(jX\5. add a **offsetof(struct my_resource_table, devmemY)** in ti_ipc_remoteproc_ResourceTable.jj3jjo1jjj}r3(j]j]j]j]j]ujMj]r3(jX 5. add a r3r3}r3(jX 5. add a jj3ubj)r3}r3(jX/**offsetof(struct my_resource_table, devmemY)**j}r3(j]j]j]j]j]ujj3j]r3jX+offsetof(struct my_resource_table, devmemY)r3r3}r3(jUjj3ubajjubjX$ in ti_ipc_remoteproc_ResourceTable.r3r3}r3(jX$ in ti_ipc_remoteproc_ResourceTable.jj3ubeubaubj{)r3}r3(jX86. add actual entry in ti_ipc_remoteproc_ResourceTable. jjD3jNjjj}r3(j]j]j]j]j]ujNjhj]r3j )r3}r3(jUj}r3(jU.jO3Kj]j]j]jUj]j]jjujj3j]r3j{)r3}r3(jX5add actual entry in ti_ipc_remoteproc_ResourceTable. j}r3(j]j]j]j]j]ujj3j]r3j)r3}r3(jX4add actual entry in ti_ipc_remoteproc_ResourceTable.r3jj3jjo1jjj}r3(j]j]j]j]j]ujMj]r3jX4add actual entry in ti_ipc_remoteproc_ResourceTable.r3r3}r3(jj3jj3ubaubajjubajj ubaubeubj)r3}r3(jXm{ TYPE_DEVMEM, IPU_PERIPHERAL_PRUSS, L3_PERIPHERAL_PRUSS, SZ_1M, 0, 0, "IPU_PERIPHERAL_PRUSS", },jj3jjo1jjj}r3(jjXcj@jAj]j]j]j}j]j]ujMjhj]r3jXm{ TYPE_DEVMEM, IPU_PERIPHERAL_PRUSS, L3_PERIPHERAL_PRUSS, SZ_1M, 0, 0, "IPU_PERIPHERAL_PRUSS", },r3r3}r3(jUjj3ubaubj)r3}r3(jXNote, when MMU is enabled, even though it is a one-to-one mapping, you need to have an entry mapped in the MMU for that, e.g. to access PRU-ICSS from DSP, you must add the following entry in **rsc_table_vayu_dsp.h**jj3jjo1jjj}r3(j]j]j]j]j]ujMjhj]r3(jXNote, when MMU is enabled, even though it is a one-to-one mapping, you need to have an entry mapped in the MMU for that, e.g. to access PRU-ICSS from DSP, you must add the following entry in r3r3}r3(jXNote, when MMU is enabled, even though it is a one-to-one mapping, you need to have an entry mapped in the MMU for that, e.g. to access PRU-ICSS from DSP, you must add the following entry in jj3ubj)r3}r3(jX**rsc_table_vayu_dsp.h**j}r3(j]j]j]j]j]ujj3j]r3jXrsc_table_vayu_dsp.hr3r3}r3(jUjj3ubajjubeubj)r3}r3(jXU#define L3_PRU_ICSS 0x4B200000 #define DSP_PRU_ICSS 0x4B200000jj3jjo1jjj}r3(j@jAj]j]j]j]j]ujMvjhj]r3jXU#define L3_PRU_ICSS 0x4B200000 #define DSP_PRU_ICSS 0x4B200000r3r3}r3(jUjj3ubaubj)r3}r3(jXkThe MMU pagetable can be dumped through debugfs - "cat /sys/kernel/debug/omap_iommu//pagetable"r3jj3jjo1jjj}r3(j]j]j]j]j]ujM%jhj]r3jXkThe MMU pagetable can be dumped through debugfs - "cat /sys/kernel/debug/omap_iommu//pagetable"r3r3}r3(jj3jj3ubaubeubeubj)r3}r3(jUjjq/jjjjj}r3(j]j]j]j]r3Uresource-usager3aj]r3juaujKjhj]r3(j)r3}r3(jXResource Usager3jj3jjjjj}r3(j]j]j]j]j]ujKjhj]r3jXResource Usager3r3}r3(jj3jj3ubaubj)r3}r3(jUjKjj3jj:X@source/rtos/PDK_Platform_Software/IPC/IPC_Resource_Usage.rst.incr3r3}r3bjjj}r3(j]r3jaj]j]j]r3Uid39r3aj]ujKjhj]r3(j)r4}r4(jXOverviewr4jj3jj3jjj}r4(j]j]j]j]j]ujKjhj]r4jXOverviewr4r4}r4(jj4jj4ubaubj)r4}r 4(jXfThe main aim of this page is to capture details about the different resources used in the IPC drivers.r 4jj3jj3jjj}r 4(j]j]j]j]j]ujKjhj]r 4jXfThe main aim of this page is to capture details about the different resources used in the IPC drivers.r 4r4}r4(jj 4jj4ubaubj)r4}r4(jXThis page is under constructionr4jj3jj3jjj}r4(j]j]j]j]j]ujNjhj]r4j)r4}r4(jj4jj4jj3jjj}r4(j]j]j]j]j]ujKj]r4jXThis page is under constructionr4r4}r4(jj4jj4ubaubaubeubj)r4}r4(jUjj3jj3jjj}r4(j]j]j]j]r4Uinterrupt-map-usager 4aj]r!4jaujK jhj]r"4(j)r#4}r$4(jXInterrupt map usager%4jj4jj3jjj}r&4(j]j]j]j]j]ujK jhj]r'4jXInterrupt map usager(4r)4}r*4(jj%4jj#4ubaubj)r+4}r,4(jUjj4jj3jjj}r-4(j]j]j]j]r.4Uam57xx-interrupt-resourcesr/4aj]r04h4aujKjhj]r14(j)r24}r34(jXAM57xx Interrupt resourcesr44jj+4jj3jjj}r54(j]j]j]j]j]ujKjhj]r64jXAM57xx Interrupt resourcesr74r84}r94(jj44jj24ubaubj)r:4}r;4(jXThe following table captures the interrupt resources used by IPC associated with different cores for the AM57xx platform. If customer wants to use any of the interrupt resources, it is better to make sure any of the resources listed here are not used.r<4jj+4jj3jjj}r=4(j]j]j]j]j]ujKjhj]r>4jXThe following table captures the interrupt resources used by IPC associated with different cores for the AM57xx platform. If customer wants to use any of the interrupt resources, it is better to make sure any of the resources listed here are not used.r?4r@4}rA4(jj<4jj:4ubaubj)rB4}rC4(jX**A15 Interrupt Mapping**rD4jj+4jj3jjj}rE4(j]j]j]j]j]ujKjhj]rF4j)rG4}rH4(jjD4j}rI4(j]j]j]j]j]ujjB4j]rJ4jXA15 Interrupt MappingrK4rL4}rM4(jUjjG4ubajjubaubjy )rN4}rO4(jUjj+4jj3jj j}rP4(j]j]j]j]j]ujNjhj]rQ4j~ )rR4}rS4(jUj}rT4(j]j]j]j]j]UcolsKujjN4j]rU4(j )rV4}rW4(jUj}rX4(j]j]j]j]j]UcolwidthK ujjR4j]jj ubj )rY4}rZ4(jUj}r[4(j]j]j]j]j]UcolwidthKujjR4j]jj ubj )r\4}r]4(jUj}r^4(j]j]j]j]j]UcolwidthK ujjR4j]jj ubj )r_4}r`4(jUj}ra4(j]j]j]j]j]UcolwidthKujjR4j]jj ubj )rb4}rc4(jUj}rd4(j]j]j]j]j]UcolwidthKujjR4j]jj ubj )re4}rf4(jUj}rg4(j]j]j]j]j]UcolwidthK$ujjR4j]jj ubj )rh4}ri4(jUj}rj4(j]j]j]j]j]ujjR4j]rk4j )rl4}rm4(jUj}rn4(j]j]j]j]j]ujjh4j]ro4(j )rp4}rq4(jUj}rr4(j]j]j]j]j]ujjl4j]rs4j)rt4}ru4(jXIndexrv4jjp4jj3jjj}rw4(j]j]j]j]j]ujKj]rx4jXIndexry4rz4}r{4(jjv4jjt4ubaubajj ubj )r|4}r}4(jUj}r~4(j]j]j]j]j]ujjl4j]r4j)r4}r4(jXAddrr4jj|4jj3jjj}r4(j]j]j]j]j]ujKj]r4jXAddrr4r4}r4(jj4jj4ubaubajj ubj )r4}r4(jUj}r4(j]j]j]j]j]ujjl4j]r4j)r4}r4(jXValuer4jj4jj3jjj}r4(j]j]j]j]j]ujKj]r4jXValuer4r4}r4(jj4jj4ubaubajj ubj )r4}r4(jUj}r4(j]j]j]j]j]ujjl4j]r4j)r4}r4(jXNamer4jj4jj3jjj}r4(j]j]j]j]j]ujKj]r4jXNamer4r4}r4(jj4jj4ubaubajj ubj )r4}r4(jUj}r4(j]j]j]j]j]ujjl4j]r4j)r4}r4(jXSourcer4jj4jj3jjj}r4(j]j]j]j]j]ujKj]r4jXSourcer4r4}r4(jj4jj4ubaubajj ubj )r4}r4(jUj}r4(j]j]j]j]j]ujjl4j]r4j)r4}r4(jX Descriptionr4jj4jj3jjj}r4(j]j]j]j]j]ujKj]r4jX Descriptionr4r4}r4(jj4jj4ubaubajj ubejj ubajj ubj )r4}r4(jUj}r4(j]j]j]j]j]ujjR4j]r4(j )r4}r4(jUj}r4(j]j]j]j]j]ujj4j]r4(j )r4}r4(jUj}r4(j]j]j]j]j]ujj4j]r4j)r4}r4(jX134r4jj4jj3jjj}r4(j]j]j]j]j]ujKj]r4jX134r4r4}r4(jj4jj4ubaubajj ubj )r4}r4(jUj}r4(j]j]j]j]j]ujj4j]r4j)r4}r4(jX 0x4A002B44r4jj4jj3jjj}r4(j]j]j]j]j]ujKj]r4jX 0x4A002B44r4r4}r4(jj4jj4ubaubajj ubj )r4}r4(jUj}r4(j]j]j]j]j]ujj4j]r4j)r4}r4(jX127r4jj4jj3jjj}r4(j]j]j]j]j]ujKj]r4jX127r4r4}r4(jj4jj4ubaubajj ubj )r4}r4(jUj}r4(j]j]j]j]j]ujj4j]r4j)r4}r4(jXEVE1_IRQ_MBX0_USER3r4jj4jj3jjj}r4(j]j]j]j]j]ujKj]r4jXEVE1_IRQ_MBX0_USER3r4r4}r4(jj4jj4ubaubajj ubj )r4}r4(jUj}r4(j]j]j]j]j]ujj4j]r4j)r4}r4(jX EVE1_MAILBOX0r4jj4jj3jjj}r4(j]j]j]j]j]ujKj]r4jX EVE1_MAILBOX0r4r4}r4(jj4jj4ubaubajj ubj )r4}r4(jUj}r4(j]j]j]j]j]ujj4j]r4j)r5}r5(jXEve1 Mailbox 0 user 3 interruptr5jj4jj3jjj}r5(j]j]j]j]j]ujKj]r5jXEve1 Mailbox 0 user 3 interruptr5r5}r5(jj5jj5ubaubajj ubejj ubj )r5}r 5(jUj}r 5(j]j]j]j]j]ujj4j]r 5(j )r 5}r 5(jUj}r5(j]j]j]j]j]ujj5j]r5j)r5}r5(jX135r5jj 5jj3jjj}r5(j]j]j]j]j]ujKj]r5jX135r5r5}r5(jj5jj5ubaubajj ubj )r5}r5(jUj}r5(j]j]j]j]j]ujj5j]r5j)r5}r5(jX 0x4A002B44r5jj5jj3jjj}r5(j]j]j]j]j]ujKj]r 5jX 0x4A002B44r!5r"5}r#5(jj5jj5ubaubajj ubj )r$5}r%5(jUj}r&5(j]j]j]j]j]ujj5j]r'5j)r(5}r)5(jX128r*5jj$5jj3jjj}r+5(j]j]j]j]j]ujKj]r,5jX128r-5r.5}r/5(jj*5jj(5ubaubajj ubj )r05}r15(jUj}r25(j]j]j]j]j]ujj5j]r35j)r45}r55(jXEVE2_IRQ_MBX0_USER3r65jj05jj3jjj}r75(j]j]j]j]j]ujKj]r85jXEVE2_IRQ_MBX0_USER3r95r:5}r;5(jj65jj45ubaubajj ubj )r<5}r=5(jUj}r>5(j]j]j]j]j]ujj5j]r?5j)r@5}rA5(jX EVE2_MAILBOX0rB5jj<5jj3jjj}rC5(j]j]j]j]j]ujKj]rD5jX EVE2_MAILBOX0rE5rF5}rG5(jjB5jj@5ubaubajj ubj )rH5}rI5(jUj}rJ5(j]j]j]j]j]ujj5j]rK5j)rL5}rM5(jXEve2 Mailbox 0 user 3 interruptrN5jjH5jj3jjj}rO5(j]j]j]j]j]ujKj]rP5jXEve2 Mailbox 0 user 3 interruptrQ5rR5}rS5(jjN5jjL5ubaubajj ubejj ubj )rT5}rU5(jUj}rV5(j]j]j]j]j]ujj4j]rW5(j )rX5}rY5(jUj}rZ5(j]j]j]j]j]ujjT5j]r[5j)r\5}r]5(jX136r^5jjX5jj3jjj}r_5(j]j]j]j]j]ujKj]r`5jX136ra5rb5}rc5(jj^5jj\5ubaubajj ubj )rd5}re5(jUj}rf5(j]j]j]j]j]ujjT5j]rg5j)rh5}ri5(jX 0x4A002B48rj5jjd5jj3jjj}rk5(j]j]j]j]j]ujKj]rl5jX 0x4A002B48rm5rn5}ro5(jjj5jjh5ubaubajj ubj )rp5}rq5(jUj}rr5(j]j]j]j]j]ujjT5j]rs5j)rt5}ru5(jX129rv5jjp5jj3jjj}rw5(j]j]j]j]j]ujKj]rx5jX129ry5rz5}r{5(jjv5jjt5ubaubajj ubj )r|5}r}5(jUj}r~5(j]j]j]j]j]ujjT5j]r5j)r5}r5(jXMAILBOX5_IRQ_USER2r5jj|5jj3jjj}r5(j]j]j]j]j]ujKj]r5jXMAILBOX5_IRQ_USER2r5r5}r5(jj5jj5ubaubajj ubj )r5}r5(jUj}r5(j]j]j]j]j]ujjT5j]r5j)r5}r5(jXMAILBOX5r5jj5jj3jjj}r5(j]j]j]j]j]ujKj]r5jXMAILBOX5r5r5}r5(jj5jj5ubaubajj ubj )r5}r5(jUj}r5(j]j]j]j]j]ujjT5j]r5j)r5}r5(jXMailbox 5 user 2 interruptr5jj5jj3jjj}r5(j]j]j]j]j]ujKj]r5jXMailbox 5 user 2 interruptr5r5}r5(jj5jj5ubaubajj ubejj ubj )r5}r5(jUj}r5(j]j]j]j]j]ujj4j]r5(j )r5}r5(jUj}r5(j]j]j]j]j]ujj5j]r5j)r5}r5(jX137r5jj5jj3jjj}r5(j]j]j]j]j]ujK j]r5jX137r5r5}r5(jj5jj5ubaubajj ubj )r5}r5(jUj}r5(j]j]j]j]j]ujj5j]r5j)r5}r5(jX 0x4A002B48r5jj5jj3jjj}r5(j]j]j]j]j]ujK j]r5jX 0x4A002B48r5r5}r5(jj5jj5ubaubajj ubj )r5}r5(jUj}r5(j]j]j]j]j]ujj5j]r5j)r5}r5(jX130r5jj5jj3jjj}r5(j]j]j]j]j]ujK j]r5jX130r5r5}r5(jj5jj5ubaubajj ubj )r5}r5(jUj}r5(j]j]j]j]j]ujj5j]r5j)r5}r5(jXEVE3_IRQ_MBX0_USER3r5jj5jj3jjj}r5(j]j]j]j]j]ujK j]r5jXEVE3_IRQ_MBX0_USER3r5r5}r5(jj5jj5ubaubajj ubj )r5}r5(jUj}r5(j]j]j]j]j]ujj5j]r5j)r5}r5(jX EVE3_MAILBOX0r5jj5jj3jjj}r5(j]j]j]j]j]ujK j]r5jX EVE3_MAILBOX0r5r5}r5(jj5jj5ubaubajj ubj )r5}r5(jUj}r5(j]j]j]j]j]ujj5j]r5j)r5}r5(jX Eve 3 Mailbox 0 user 3 interruptr5jj5jj3jjj}r5(j]j]j]j]j]ujK j]r5jX Eve 3 Mailbox 0 user 3 interruptr5r5}r5(jj5jj5ubaubajj ubejj ubj )r5}r5(jUj}r5(j]j]j]j]j]ujj4j]r5(j )r5}r5(jUj}r5(j]j]j]j]j]ujj5j]r5j)r5}r5(jX138r5jj5jj3jjj}r5(j]j]j]j]j]ujK"j]r5jX138r5r5}r5(jj5jj5ubaubajj ubj )r5}r5(jUj}r5(j]j]j]j]j]ujj5j]r5j)r6}r6(jX 0x4A002B4Cr6jj5jj3jjj}r6(j]j]j]j]j]ujK"j]r6jX 0x4A002B4Cr6r6}r6(jj6jj6ubaubajj ubj )r6}r 6(jUj}r 6(j]j]j]j]j]ujj5j]r 6j)r 6}r 6(jX131r6jj6jj3jjj}r6(j]j]j]j]j]ujK"j]r6jX131r6r6}r6(jj6jj 6ubaubajj ubj )r6}r6(jUj}r6(j]j]j]j]j]ujj5j]r6j)r6}r6(jXEVE4_IRQ_MBX0_USER3r6jj6jj3jjj}r6(j]j]j]j]j]ujK"j]r6jXEVE4_IRQ_MBX0_USER3r6r6}r6(jj6jj6ubaubajj ubj )r 6}r!6(jUj}r"6(j]j]j]j]j]ujj5j]r#6j)r$6}r%6(jX EVE4_MAILBOX0r&6jj 6jj3jjj}r'6(j]j]j]j]j]ujK"j]r(6jX EVE4_MAILBOX0r)6r*6}r+6(jj&6jj$6ubaubajj ubj )r,6}r-6(jUj}r.6(j]j]j]j]j]ujj5j]r/6j)r06}r16(jXEve4 Mailbox 0 user 3 interruptr26jj,6jj3jjj}r36(j]j]j]j]j]ujK"j]r46jXEve4 Mailbox 0 user 3 interruptr56r66}r76(jj26jj06ubaubajj ubejj ubj )r86}r96(jUj}r:6(j]j]j]j]j]ujj4j]r;6(j )r<6}r=6(jUj}r>6(j]j]j]j]j]ujj86j]r?6j)r@6}rA6(jX141rB6jj<6jj3jjj}rC6(j]j]j]j]j]ujK$j]rD6jX141rE6rF6}rG6(jjB6jj@6ubaubajj ubj )rH6}rI6(jUj}rJ6(j]j]j]j]j]ujj86j]rK6j)rL6}rM6(jX 0x4A002B50rN6jjH6jj3jjj}rO6(j]j]j]j]j]ujK$j]rP6jX 0x4A002B50rQ6rR6}rS6(jjN6jjL6ubaubajj ubj )rT6}rU6(jUj}rV6(j]j]j]j]j]ujj86j]rW6j)rX6}rY6(jX134rZ6jjT6jj3jjj}r[6(j]j]j]j]j]ujK$j]r\6jX134r]6r^6}r_6(jjZ6jjX6ubaubajj ubj )r`6}ra6(jUj}rb6(j]j]j]j]j]ujj86j]rc6j)rd6}re6(jXMAILBOX6_IRQ_USER2rf6jj`6jj3jjj}rg6(j]j]j]j]j]ujK$j]rh6jXMAILBOX6_IRQ_USER2ri6rj6}rk6(jjf6jjd6ubaubajj ubj )rl6}rm6(jUj}rn6(j]j]j]j]j]ujj86j]ro6j)rp6}rq6(jXMAILBOX6rr6jjl6jj3jjj}rs6(j]j]j]j]j]ujK$j]rt6jXMAILBOX6ru6rv6}rw6(jjr6jjp6ubaubajj ubj )rx6}ry6(jUj}rz6(j]j]j]j]j]ujj86j]r{6j)r|6}r}6(jXMailbox 6 user 2 interruptr~6jjx6jj3jjj}r6(j]j]j]j]j]ujK$j]r6jXMailbox 6 user 2 interruptr6r6}r6(jj~6jj|6ubaubajj ubejj ubejj ubejj ubaubj)r6}r6(jX**DSP1 Interrupt Mapping**r6jj+4jj3jjj}r6(j]j]j]j]j]ujK'jhj]r6j)r6}r6(jj6j}r6(j]j]j]j]j]ujj6j]r6jXDSP1 Interrupt Mappingr6r6}r6(jUjj6ubajjubaubjy )r6}r6(jUjj+4jj3jj j}r6(j]j]j]j]j]ujNjhj]r6j~ )r6}r6(jUj}r6(j]j]j]j]j]UcolsKujj6j]r6(j )r6}r6(jUj}r6(j]j]j]j]j]UcolwidthK ujj6j]jj ubj )r6}r6(jUj}r6(j]j]j]j]j]UcolwidthKujj6j]jj ubj )r6}r6(jUj}r6(j]j]j]j]j]UcolwidthK ujj6j]jj ubj )r6}r6(jUj}r6(j]j]j]j]j]UcolwidthKujj6j]jj ubj )r6}r6(jUj}r6(j]j]j]j]j]UcolwidthKujj6j]jj ubj )r6}r6(jUj}r6(j]j]j]j]j]UcolwidthK$ujj6j]jj ubj )r6}r6(jUj}r6(j]j]j]j]j]ujj6j]r6j )r6}r6(jUj}r6(j]j]j]j]j]ujj6j]r6(j )r6}r6(jUj}r6(j]j]j]j]j]ujj6j]r6j)r6}r6(jXIndexr6jj6jj3jjj}r6(j]j]j]j]j]ujK*j]r6jXIndexr6r6}r6(jj6jj6ubaubajj ubj )r6}r6(jUj}r6(j]j]j]j]j]ujj6j]r6j)r6}r6(jXAddrr6jj6jj3jjj}r6(j]j]j]j]j]ujK*j]r6jXAddrr6r6}r6(jj6jj6ubaubajj ubj )r6}r6(jUj}r6(j]j]j]j]j]ujj6j]r6j)r6}r6(jXValuer6jj6jj3jjj}r6(j]j]j]j]j]ujK*j]r6jXValuer6r6}r6(jj6jj6ubaubajj ubj )r6}r6(jUj}r6(j]j]j]j]j]ujj6j]r6j)r6}r6(jXNamer6jj6jj3jjj}r6(j]j]j]j]j]ujK*j]r6jXNamer6r6}r6(jj6jj6ubaubajj ubj )r6}r6(jUj}r6(j]j]j]j]j]ujj6j]r6j)r6}r6(jXSourcer6jj6jj3jjj}r6(j]j]j]j]j]ujK*j]r6jXSourcer6r6}r6(jj6jj6ubaubajj ubj )r6}r6(jUj}r6(j]j]j]j]j]ujj6j]r6j)r6}r6(jX Descriptionr6jj6jj3jjj}r6(j]j]j]j]j]ujK*j]r6jX Descriptionr6r6}r6(jj6jj6ubaubajj ubejj ubajj ubj )r6}r6(jUj}r6(j]j]j]j]j]ujj6j]r6(j )r6}r6(jUj}r7(j]j]j]j]j]ujj6j]r7(j )r7}r7(jUj}r7(j]j]j]j]j]ujj6j]r7j)r7}r7(jX55r7jj7jj3jjj}r 7(j]j]j]j]j]ujK,j]r 7jX55r 7r 7}r 7(jj7jj7ubaubajj ubj )r7}r7(jUj}r7(j]j]j]j]j]ujj6j]r7j)r7}r7(jX 0x4A002974r7jj7jj3jjj}r7(j]j]j]j]j]ujK,j]r7jX 0x4A002974r7r7}r7(jj7jj7ubaubajj ubj )r7}r7(jUj}r7(j]j]j]j]j]ujj6j]r7j)r7}r7(jX24r 7jj7jj3jjj}r!7(j]j]j]j]j]ujK,j]r"7jX24r#7r$7}r%7(jj 7jj7ubaubajj ubj )r&7}r'7(jUj}r(7(j]j]j]j]j]ujj6j]r)7j)r*7}r+7(jXEVE1_IRQ_MBX0_USER1r,7jj&7jj3jjj}r-7(j]j]j]j]j]ujK,j]r.7jXEVE1_IRQ_MBX0_USER1r/7r07}r17(jj,7jj*7ubaubajj ubj )r27}r37(jUj}r47(j]j]j]j]j]ujj6j]r57j)r67}r77(jX EVE1_MAILBOX0r87jj27jj3jjj}r97(j]j]j]j]j]ujK,j]r:7jX EVE1_MAILBOX0r;7r<7}r=7(jj87jj67ubaubajj ubj )r>7}r?7(jUj}r@7(j]j]j]j]j]ujj6j]rA7j)rB7}rC7(jXEve1 Mailbox 0 user 1 interruptrD7jj>7jj3jjj}rE7(j]j]j]j]j]ujK,j]rF7jXEve1 Mailbox 0 user 1 interruptrG7rH7}rI7(jjD7jjB7ubaubajj ubejj ubj )rJ7}rK7(jUj}rL7(j]j]j]j]j]ujj6j]rM7(j )rN7}rO7(jUj}rP7(j]j]j]j]j]ujjJ7j]rQ7j)rR7}rS7(jX56rT7jjN7jj3jjj}rU7(j]j]j]j]j]ujK.j]rV7jX56rW7rX7}rY7(jjT7jjR7ubaubajj ubj )rZ7}r[7(jUj}r\7(j]j]j]j]j]ujjJ7j]r]7j)r^7}r_7(jX 0x4A002978r`7jjZ7jj3jjj}ra7(j]j]j]j]j]ujK.j]rb7jX 0x4A002978rc7rd7}re7(jj`7jj^7ubaubajj ubj )rf7}rg7(jUj}rh7(j]j]j]j]j]ujjJ7j]ri7j)rj7}rk7(jX25rl7jjf7jj3jjj}rm7(j]j]j]j]j]ujK.j]rn7jX25ro7rp7}rq7(jjl7jjj7ubaubajj ubj )rr7}rs7(jUj}rt7(j]j]j]j]j]ujjJ7j]ru7j)rv7}rw7(jXEVE2_IRQ_MBX0_USER1rx7jjr7jj3jjj}ry7(j]j]j]j]j]ujK.j]rz7jXEVE2_IRQ_MBX0_USER1r{7r|7}r}7(jjx7jjv7ubaubajj ubj )r~7}r7(jUj}r7(j]j]j]j]j]ujjJ7j]r7j)r7}r7(jX EVE2_MAILBOX0r7jj~7jj3jjj}r7(j]j]j]j]j]ujK.j]r7jX EVE2_MAILBOX0r7r7}r7(jj7jj7ubaubajj ubj )r7}r7(jUj}r7(j]j]j]j]j]ujjJ7j]r7j)r7}r7(jXEve2 Mailbox 0 user 1 interruptr7jj7jj3jjj}r7(j]j]j]j]j]ujK.j]r7jXEve2 Mailbox 0 user 1 interruptr7r7}r7(jj7jj7ubaubajj ubejj ubj )r7}r7(jUj}r7(j]j]j]j]j]ujj6j]r7(j )r7}r7(jUj}r7(j]j]j]j]j]ujj7j]r7j)r7}r7(jX57r7jj7jj3jjj}r7(j]j]j]j]j]ujK0j]r7jX57r7r7}r7(jj7jj7ubaubajj ubj )r7}r7(jUj}r7(j]j]j]j]j]ujj7j]r7j)r7}r7(jX 0x4A002978r7jj7jj3jjj}r7(j]j]j]j]j]ujK0j]r7jX 0x4A002978r7r7}r7(jj7jj7ubaubajj ubj )r7}r7(jUj}r7(j]j]j]j]j]ujj7j]r7j)r7}r7(jX26r7jj7jj3jjj}r7(j]j]j]j]j]ujK0j]r7jX26r7r7}r7(jj7jj7ubaubajj ubj )r7}r7(jUj}r7(j]j]j]j]j]ujj7j]r7j)r7}r7(jXMAILBOX5_IRQ_USER0r7jj7jj3jjj}r7(j]j]j]j]j]ujK0j]r7jXMAILBOX5_IRQ_USER0r7r7}r7(jj7jj7ubaubajj ubj )r7}r7(jUj}r7(j]j]j]j]j]ujj7j]r7j)r7}r7(jXMAILBOX5r7jj7jj3jjj}r7(j]j]j]j]j]ujK0j]r7jXMAILBOX5r7r7}r7(jj7jj7ubaubajj ubj )r7}r7(jUj}r7(j]j]j]j]j]ujj7j]r7j)r7}r7(jXMailbox 5 user 0 interruptr7jj7jj3jjj}r7(j]j]j]j]j]ujK0j]r7jXMailbox 5 user 0 interruptr7r7}r7(jj7jj7ubaubajj ubejj ubj )r7}r7(jUj}r7(j]j]j]j]j]ujj6j]r7(j )r7}r7(jUj}r7(j]j]j]j]j]ujj7j]r7j)r7}r7(jX58r7jj7jj3jjj}r7(j]j]j]j]j]ujK2j]r7jX58r7r7}r7(jj7jj7ubaubajj ubj )r7}r7(jUj}r7(j]j]j]j]j]ujj7j]r7j)r7}r7(jX 0x4A00297Cr7jj7jj3jjj}r7(j]j]j]j]j]ujK2j]r7jX 0x4A00297Cr7r7}r7(jj7jj7ubaubajj ubj )r7}r7(jUj}r8(j]j]j]j]j]ujj7j]r8j)r8}r8(jX27r8jj7jj3jjj}r8(j]j]j]j]j]ujK2j]r8jX27r8r8}r 8(jj8jj8ubaubajj ubj )r 8}r 8(jUj}r 8(j]j]j]j]j]ujj7j]r 8j)r8}r8(jXEVE3_IRQ_MBX0_USER1r8jj 8jj3jjj}r8(j]j]j]j]j]ujK2j]r8jXEVE3_IRQ_MBX0_USER1r8r8}r8(jj8jj8ubaubajj ubj )r8}r8(jUj}r8(j]j]j]j]j]ujj7j]r8j)r8}r8(jX EVE3_MAILBOX0r8jj8jj3jjj}r8(j]j]j]j]j]ujK2j]r8jX EVE3_MAILBOX0r8r 8}r!8(jj8jj8ubaubajj ubj )r"8}r#8(jUj}r$8(j]j]j]j]j]ujj7j]r%8j)r&8}r'8(jX Eve 3 Mailbox 0 user 1 interruptr(8jj"8jj3jjj}r)8(j]j]j]j]j]ujK2j]r*8jX Eve 3 Mailbox 0 user 1 interruptr+8r,8}r-8(jj(8jj&8ubaubajj ubejj ubj )r.8}r/8(jUj}r08(j]j]j]j]j]ujj6j]r18(j )r28}r38(jUj}r48(j]j]j]j]j]ujj.8j]r58j)r68}r78(jX59r88jj28jj3jjj}r98(j]j]j]j]j]ujK4j]r:8jX59r;8r<8}r=8(jj88jj68ubaubajj ubj )r>8}r?8(jUj}r@8(j]j]j]j]j]ujj.8j]rA8j)rB8}rC8(jX 0x4A00297CrD8jj>8jj3jjj}rE8(j]j]j]j]j]ujK4j]rF8jX 0x4A00297CrG8rH8}rI8(jjD8jjB8ubaubajj ubj )rJ8}rK8(jUj}rL8(j]j]j]j]j]ujj.8j]rM8j)rN8}rO8(jX28rP8jjJ8jj3jjj}rQ8(j]j]j]j]j]ujK4j]rR8jX28rS8rT8}rU8(jjP8jjN8ubaubajj ubj )rV8}rW8(jUj}rX8(j]j]j]j]j]ujj.8j]rY8j)rZ8}r[8(jXEVE4_IRQ_MBX0_USER1r\8jjV8jj3jjj}r]8(j]j]j]j]j]ujK4j]r^8jXEVE4_IRQ_MBX0_USER1r_8r`8}ra8(jj\8jjZ8ubaubajj ubj )rb8}rc8(jUj}rd8(j]j]j]j]j]ujj.8j]re8j)rf8}rg8(jXEVE4_MAILBOX0irh8jjb8jj3jjj}ri8(j]j]j]j]j]ujK4j]rj8jXEVE4_MAILBOX0irk8rl8}rm8(jjh8jjf8ubaubajj ubj )rn8}ro8(jUj}rp8(j]j]j]j]j]ujj.8j]rq8j)rr8}rs8(jXEve4 Mailbox 0 user 1 interruptrt8jjn8jj3jjj}ru8(j]j]j]j]j]ujK4j]rv8jXEve4 Mailbox 0 user 1 interruptrw8rx8}ry8(jjt8jjr8ubaubajj ubejj ubj )rz8}r{8(jUj}r|8(j]j]j]j]j]ujj6j]r}8(j )r~8}r8(jUj}r8(j]j]j]j]j]ujjz8j]r8j)r8}r8(jX60r8jj~8jj3jjj}r8(j]j]j]j]j]ujK6j]r8jX60r8r8}r8(jj8jj8ubaubajj ubj )r8}r8(jUj}r8(j]j]j]j]j]ujjz8j]r8j)r8}r8(jX 0x4A002980r8jj8jj3jjj}r8(j]j]j]j]j]ujK6j]r8jX 0x4A002980r8r8}r8(jj8jj8ubaubajj ubj )r8}r8(jUj}r8(j]j]j]j]j]ujjz8j]r8j)r8}r8(jX29r8jj8jj3jjj}r8(j]j]j]j]j]ujK6j]r8jX29r8r8}r8(jj8jj8ubaubajj ubj )r8}r8(jUj}r8(j]j]j]j]j]ujjz8j]r8j)r8}r8(jXMAILBOX7_IRQ_USER0r8jj8jj3jjj}r8(j]j]j]j]j]ujK6j]r8jXMAILBOX7_IRQ_USER0r8r8}r8(jj8jj8ubaubajj ubj )r8}r8(jUj}r8(j]j]j]j]j]ujjz8j]r8j)r8}r8(jXMAILBOX7r8jj8jj3jjj}r8(j]j]j]j]j]ujK6j]r8jXMAILBOX7r8r8}r8(jj8jj8ubaubajj ubj )r8}r8(jUj}r8(j]j]j]j]j]ujjz8j]r8j)r8}r8(jXMailbox 7 user 0 interruptr8jj8jj3jjj}r8(j]j]j]j]j]ujK6j]r8jXMailbox 7 user 0 interruptr8r8}r8(jj8jj8ubaubajj ubejj ubj )r8}r8(jUj}r8(j]j]j]j]j]ujj6j]r8(j )r8}r8(jUj}r8(j]j]j]j]j]ujj8j]r8j)r8}r8(jX61r8jj8jj3jjj}r8(j]j]j]j]j]ujK8j]r8jX61r8r8}r8(jj8jj8ubaubajj ubj )r8}r8(jUj}r8(j]j]j]j]j]ujj8j]r8j)r8}r8(jX 0x4A002980r8jj8jj3jjj}r8(j]j]j]j]j]ujK8j]r8jX 0x4A002980r8r8}r8(jj8jj8ubaubajj ubj )r8}r8(jUj}r8(j]j]j]j]j]ujj8j]r8j)r8}r8(jX30r8jj8jj3jjj}r8(j]j]j]j]j]ujK8j]r8jX30r8r8}r8(jj8jj8ubaubajj ubj )r8}r8(jUj}r8(j]j]j]j]j]ujj8j]r8j)r8}r8(jXMAILBOX8_IRQ_USER0r8jj8jj3jjj}r8(j]j]j]j]j]ujK8j]r8jXMAILBOX8_IRQ_USER0r8r8}r8(jj8jj8ubaubajj ubj )r8}r8(jUj}r8(j]j]j]j]j]ujj8j]r8j)r8}r8(jXMAILBOX8r9jj8jj3jjj}r9(j]j]j]j]j]ujK8j]r9jXMAILBOX8r9r9}r9(jj9jj8ubaubajj ubj )r9}r9(jUj}r9(j]j]j]j]j]ujj8j]r 9j)r 9}r 9(jXMailbox 8 user 0 interruptr 9jj9jj3jjj}r 9(j]j]j]j]j]ujK8j]r9jXMailbox 8 user 0 interruptr9r9}r9(jj 9jj 9ubaubajj ubejj ubejj ubejj ubaubj)r9}r9(jX**DSP2 Interrupt Mapping**r9jj+4jj3jjj}r9(j]j]j]j]j]ujK;jhj]r9j)r9}r9(jj9j}r9(j]j]j]j]j]ujj9j]r9jXDSP2 Interrupt Mappingr9r9}r9(jUjj9ubajjubaubjy )r9}r9(jUjj+4jj3jj j}r 9(j]j]j]j]j]ujNjhj]r!9j~ )r"9}r#9(jUj}r$9(j]j]j]j]j]UcolsKujj9j]r%9(j )r&9}r'9(jUj}r(9(j]j]j]j]j]UcolwidthK ujj"9j]jj ubj )r)9}r*9(jUj}r+9(j]j]j]j]j]UcolwidthKujj"9j]jj ubj )r,9}r-9(jUj}r.9(j]j]j]j]j]UcolwidthK ujj"9j]jj ubj )r/9}r09(jUj}r19(j]j]j]j]j]UcolwidthKujj"9j]jj ubj )r29}r39(jUj}r49(j]j]j]j]j]UcolwidthKujj"9j]jj ubj )r59}r69(jUj}r79(j]j]j]j]j]UcolwidthK$ujj"9j]jj ubj )r89}r99(jUj}r:9(j]j]j]j]j]ujj"9j]r;9j )r<9}r=9(jUj}r>9(j]j]j]j]j]ujj89j]r?9(j )r@9}rA9(jUj}rB9(j]j]j]j]j]ujj<9j]rC9j)rD9}rE9(jXIndexrF9jj@9jj3jjj}rG9(j]j]j]j]j]ujK>j]rH9jXIndexrI9rJ9}rK9(jjF9jjD9ubaubajj ubj )rL9}rM9(jUj}rN9(j]j]j]j]j]ujj<9j]rO9j)rP9}rQ9(jXAddrrR9jjL9jj3jjj}rS9(j]j]j]j]j]ujK>j]rT9jXAddrrU9rV9}rW9(jjR9jjP9ubaubajj ubj )rX9}rY9(jUj}rZ9(j]j]j]j]j]ujj<9j]r[9j)r\9}r]9(jXValuer^9jjX9jj3jjj}r_9(j]j]j]j]j]ujK>j]r`9jXValuera9rb9}rc9(jj^9jj\9ubaubajj ubj )rd9}re9(jUj}rf9(j]j]j]j]j]ujj<9j]rg9j)rh9}ri9(jXNamerj9jjd9jj3jjj}rk9(j]j]j]j]j]ujK>j]rl9jXNamerm9rn9}ro9(jjj9jjh9ubaubajj ubj )rp9}rq9(jUj}rr9(j]j]j]j]j]ujj<9j]rs9j)rt9}ru9(jXSourcerv9jjp9jj3jjj}rw9(j]j]j]j]j]ujK>j]rx9jXSourcery9rz9}r{9(jjv9jjt9ubaubajj ubj )r|9}r}9(jUj}r~9(j]j]j]j]j]ujj<9j]r9j)r9}r9(jX Descriptionr9jj|9jj3jjj}r9(j]j]j]j]j]ujK>j]r9jX Descriptionr9r9}r9(jj9jj9ubaubajj ubejj ubajj ubj )r9}r9(jUj}r9(j]j]j]j]j]ujj"9j]r9(j )r9}r9(jUj}r9(j]j]j]j]j]ujj9j]r9(j )r9}r9(jUj}r9(j]j]j]j]j]ujj9j]r9j)r9}r9(jX55r9jj9jj3jjj}r9(j]j]j]j]j]ujK@j]r9jX55r9r9}r9(jj9jj9ubaubajj ubj )r9}r9(jUj}r9(j]j]j]j]j]ujj9j]r9j)r9}r9(jX 0x4A0029F4r9jj9jj3jjj}r9(j]j]j]j]j]ujK@j]r9jX 0x4A0029F4r9r9}r9(jj9jj9ubaubajj ubj )r9}r9(jUj}r9(j]j]j]j]j]ujj9j]r9j)r9}r9(jX24r9jj9jj3jjj}r9(j]j]j]j]j]ujK@j]r9jX24r9r9}r9(jj9jj9ubaubajj ubj )r9}r9(jUj}r9(j]j]j]j]j]ujj9j]r9j)r9}r9(jXEVE1_IRQ_MBX1_USER1r9jj9jj3jjj}r9(j]j]j]j]j]ujK@j]r9jXEVE1_IRQ_MBX1_USER1r9r9}r9(jj9jj9ubaubajj ubj )r9}r9(jUj}r9(j]j]j]j]j]ujj9j]r9j)r9}r9(jX EVE1_MAILBOX1r9jj9jj3jjj}r9(j]j]j]j]j]ujK@j]r9jX EVE1_MAILBOX1r9r9}r9(jj9jj9ubaubajj ubj )r9}r9(jUj}r9(j]j]j]j]j]ujj9j]r9j)r9}r9(jXEve1 Mailbox 1 user 1 interruptr9jj9jj3jjj}r9(j]j]j]j]j]ujK@j]r9jXEve1 Mailbox 1 user 1 interruptr9r9}r9(jj9jj9ubaubajj ubejj ubj )r9}r9(jUj}r9(j]j]j]j]j]ujj9j]r9(j )r9}r9(jUj}r9(j]j]j]j]j]ujj9j]r9j)r9}r9(jX56r9jj9jj3jjj}r9(j]j]j]j]j]ujKBj]r9jX56r9r9}r9(jj9jj9ubaubajj ubj )r9}r9(jUj}r9(j]j]j]j]j]ujj9j]r9j)r9}r9(jX 0x4A0029F8r9jj9jj3jjj}r9(j]j]j]j]j]ujKBj]r9jX 0x4A0029F8r9r9}r9(jj9jj9ubaubajj ubj )r9}r9(jUj}r9(j]j]j]j]j]ujj9j]r9j)r9}r9(jX25r9jj9jj3jjj}r9(j]j]j]j]j]ujKBj]r9jX25r9r9}r9(jj9jj9ubaubajj ubj )r:}r:(jUj}r:(j]j]j]j]j]ujj9j]r:j)r:}r:(jXEVE2_IRQ_MBX1_USER1r:jj:jj3jjj}r:(j]j]j]j]j]ujKBj]r:jXEVE2_IRQ_MBX1_USER1r :r :}r :(jj:jj:ubaubajj ubj )r :}r :(jUj}r:(j]j]j]j]j]ujj9j]r:j)r:}r:(jX EVE2_MAILBOX1r:jj :jj3jjj}r:(j]j]j]j]j]ujKBj]r:jX EVE2_MAILBOX1r:r:}r:(jj:jj:ubaubajj ubj )r:}r:(jUj}r:(j]j]j]j]j]ujj9j]r:j)r:}r:(jXEve2 Mailbox 1 user 1 interruptr:jj:jj3jjj}r:(j]j]j]j]j]ujKBj]r :jXEve2 Mailbox 1 user 1 interruptr!:r":}r#:(jj:jj:ubaubajj ubejj ubj )r$:}r%:(jUj}r&:(j]j]j]j]j]ujj9j]r':(j )r(:}r):(jUj}r*:(j]j]j]j]j]ujj$:j]r+:j)r,:}r-:(jX57r.:jj(:jj3jjj}r/:(j]j]j]j]j]ujKDj]r0:jX57r1:r2:}r3:(jj.:jj,:ubaubajj ubj )r4:}r5:(jUj}r6:(j]j]j]j]j]ujj$:j]r7:j)r8:}r9:(jX 0x4A0029F8r::jj4:jj3jjj}r;:(j]j]j]j]j]ujKDj]r<:jX 0x4A0029F8r=:r>:}r?:(jj::jj8:ubaubajj ubj )r@:}rA:(jUj}rB:(j]j]j]j]j]ujj$:j]rC:j)rD:}rE:(jX26rF:jj@:jj3jjj}rG:(j]j]j]j]j]ujKDj]rH:jX26rI:rJ:}rK:(jjF:jjD:ubaubajj ubj )rL:}rM:(jUj}rN:(j]j]j]j]j]ujj$:j]rO:j)rP:}rQ:(jXMAILBOX6_IRQ_USER0rR:jjL:jj3jjj}rS:(j]j]j]j]j]ujKDj]rT:jXMAILBOX6_IRQ_USER0rU:rV:}rW:(jjR:jjP:ubaubajj ubj )rX:}rY:(jUj}rZ:(j]j]j]j]j]ujj$:j]r[:j)r\:}r]:(jXMAILBOX6r^:jjX:jj3jjj}r_:(j]j]j]j]j]ujKDj]r`:jXMAILBOX6ra:rb:}rc:(jj^:jj\:ubaubajj ubj )rd:}re:(jUj}rf:(j]j]j]j]j]ujj$:j]rg:j)rh:}ri:(jXMailbox 6 user 0 interruptrj:jjd:jj3jjj}rk:(j]j]j]j]j]ujKDj]rl:jXMailbox 6 user 0 interruptrm:rn:}ro:(jjj:jjh:ubaubajj ubejj ubj )rp:}rq:(jUj}rr:(j]j]j]j]j]ujj9j]rs:(j )rt:}ru:(jUj}rv:(j]j]j]j]j]ujjp:j]rw:j)rx:}ry:(jX58rz:jjt:jj3jjj}r{:(j]j]j]j]j]ujKFj]r|:jX58r}:r~:}r:(jjz:jjx:ubaubajj ubj )r:}r:(jUj}r:(j]j]j]j]j]ujjp:j]r:j)r:}r:(jX 0x4A0029FCr:jj:jj3jjj}r:(j]j]j]j]j]ujKFj]r:jX 0x4A0029FCr:r:}r:(jj:jj:ubaubajj ubj )r:}r:(jUj}r:(j]j]j]j]j]ujjp:j]r:j)r:}r:(jX27r:jj:jj3jjj}r:(j]j]j]j]j]ujKFj]r:jX27r:r:}r:(jj:jj:ubaubajj ubj )r:}r:(jUj}r:(j]j]j]j]j]ujjp:j]r:j)r:}r:(jXEVE3_IRQ_MLBX1_USER1r:jj:jj3jjj}r:(j]j]j]j]j]ujKFj]r:jXEVE3_IRQ_MLBX1_USER1r:r:}r:(jj:jj:ubaubajj ubj )r:}r:(jUj}r:(j]j]j]j]j]ujjp:j]r:j)r:}r:(jX EVE3_MAILBOX1r:jj:jj3jjj}r:(j]j]j]j]j]ujKFj]r:jX EVE3_MAILBOX1r:r:}r:(jj:jj:ubaubajj ubj )r:}r:(jUj}r:(j]j]j]j]j]ujjp:j]r:j)r:}r:(jX Eve 3 Mailbox 1 user 1 interruptr:jj:jj3jjj}r:(j]j]j]j]j]ujKFj]r:jX Eve 3 Mailbox 1 user 1 interruptr:r:}r:(jj:jj:ubaubajj ubejj ubj )r:}r:(jUj}r:(j]j]j]j]j]ujj9j]r:(j )r:}r:(jUj}r:(j]j]j]j]j]ujj:j]r:j)r:}r:(jX59r:jj:jj3jjj}r:(j]j]j]j]j]ujKHj]r:jX59r:r:}r:(jj:jj:ubaubajj ubj )r:}r:(jUj}r:(j]j]j]j]j]ujj:j]r:j)r:}r:(jX 0x4A0029FCr:jj:jj3jjj}r:(j]j]j]j]j]ujKHj]r:jX 0x4A0029FCr:r:}r:(jj:jj:ubaubajj ubj )r:}r:(jUj}r:(j]j]j]j]j]ujj:j]r:j)r:}r:(jX28r:jj:jj3jjj}r:(j]j]j]j]j]ujKHj]r:jX28r:r:}r:(jj:jj:ubaubajj ubj )r:}r:(jUj}r:(j]j]j]j]j]ujj:j]r:j)r:}r:(jXEVE4_IRQ_MBX1_USER1r:jj:jj3jjj}r:(j]j]j]j]j]ujKHj]r:jXEVE4_IRQ_MBX1_USER1r:r:}r:(jj:jj:ubaubajj ubj )r:}r:(jUj}r:(j]j]j]j]j]ujj:j]r:j)r:}r:(jX EVE4_MAILBOX1r:jj:jj3jjj}r:(j]j]j]j]j]ujKHj]r:jX EVE4_MAILBOX1r:r:}r:(jj:jj:ubaubajj ubj )r:}r:(jUj}r:(j]j]j]j]j]ujj:j]r:j)r;}r;(jXEve4 Mailbox 1 user 1 interruptr;jj:jj3jjj}r;(j]j]j]j]j]ujKHj]r;jXEve4 Mailbox 1 user 1 interruptr;r;}r;(jj;jj;ubaubajj ubejj ubj )r;}r ;(jUj}r ;(j]j]j]j]j]ujj9j]r ;(j )r ;}r ;(jUj}r;(j]j]j]j]j]ujj;j]r;j)r;}r;(jX60r;jj ;jj3jjj}r;(j]j]j]j]j]ujKJj]r;jX60r;r;}r;(jj;jj;ubaubajj ubj )r;}r;(jUj}r;(j]j]j]j]j]ujj;j]r;j)r;}r;(jX 0x4A002A00r;jj;jj3jjj}r;(j]j]j]j]j]ujKJj]r ;jX 0x4A002A00r!;r";}r#;(jj;jj;ubaubajj ubj )r$;}r%;(jUj}r&;(j]j]j]j]j]ujj;j]r';j)r(;}r);(jX29r*;jj$;jj3jjj}r+;(j]j]j]j]j]ujKJj]r,;jX29r-;r.;}r/;(jj*;jj(;ubaubajj ubj )r0;}r1;(jUj}r2;(j]j]j]j]j]ujj;j]r3;j)r4;}r5;(jXMAILBOX7_IRQ_USER1r6;jj0;jj3jjj}r7;(j]j]j]j]j]ujKJj]r8;jXMAILBOX7_IRQ_USER1r9;r:;}r;;(jj6;jj4;ubaubajj ubj )r<;}r=;(jUj}r>;(j]j]j]j]j]ujj;j]r?;j)r@;}rA;(jXMAILBOX7rB;jj<;jj3jjj}rC;(j]j]j]j]j]ujKJj]rD;jXMAILBOX7rE;rF;}rG;(jjB;jj@;ubaubajj ubj )rH;}rI;(jUj}rJ;(j]j]j]j]j]ujj;j]rK;j)rL;}rM;(jXMailbox 7 user 1 interruptrN;jjH;jj3jjj}rO;(j]j]j]j]j]ujKJj]rP;jXMailbox 7 user 1 interruptrQ;rR;}rS;(jjN;jjL;ubaubajj ubejj ubj )rT;}rU;(jUj}rV;(j]j]j]j]j]ujj9j]rW;(j )rX;}rY;(jUj}rZ;(j]j]j]j]j]ujjT;j]r[;j)r\;}r];(jX61r^;jjX;jj3jjj}r_;(j]j]j]j]j]ujKLj]r`;jX61ra;rb;}rc;(jj^;jj\;ubaubajj ubj )rd;}re;(jUj}rf;(j]j]j]j]j]ujjT;j]rg;j)rh;}ri;(jX 0x4A002A00rj;jjd;jj3jjj}rk;(j]j]j]j]j]ujKLj]rl;jX 0x4A002A00rm;rn;}ro;(jjj;jjh;ubaubajj ubj )rp;}rq;(jUj}rr;(j]j]j]j]j]ujjT;j]rs;j)rt;}ru;(jX30rv;jjp;jj3jjj}rw;(j]j]j]j]j]ujKLj]rx;jX30ry;rz;}r{;(jjv;jjt;ubaubajj ubj )r|;}r};(jUj}r~;(j]j]j]j]j]ujjT;j]r;j)r;}r;(jXMAILBOX8_IRQ_USER1r;jj|;jj3jjj}r;(j]j]j]j]j]ujKLj]r;jXMAILBOX8_IRQ_USER1r;r;}r;(jj;jj;ubaubajj ubj )r;}r;(jUj}r;(j]j]j]j]j]ujjT;j]r;j)r;}r;(jXMAILBOX8r;jj;jj3jjj}r;(j]j]j]j]j]ujKLj]r;jXMAILBOX8r;r;}r;(jj;jj;ubaubajj ubj )r;}r;(jUj}r;(j]j]j]j]j]ujjT;j]r;j)r;}r;(jXMailbox 8 user 1 interruptr;jj;jj3jjj}r;(j]j]j]j]j]ujKLj]r;jXMailbox 8 user 1 interruptr;r;}r;(jj;jj;ubaubajj ubejj ubejj ubejj ubaubj)r;}r;(jX**IPU1 Interrupt Mapping**r;jj+4jj3jjj}r;(j]j]j]j]j]ujKOjhj]r;j)r;}r;(jj;j}r;(j]j]j]j]j]ujj;j]r;jXIPU1 Interrupt Mappingr;r;}r;(jUjj;ubajjubaubjy )r;}r;(jUjj+4jj3jj j}r;(j]j]j]j]j]ujNjhj]r;j~ )r;}r;(jUj}r;(j]j]j]j]j]UcolsKujj;j]r;(j )r;}r;(jUj}r;(j]j]j]j]j]UcolwidthK ujj;j]jj ubj )r;}r;(jUj}r;(j]j]j]j]j]UcolwidthKujj;j]jj ubj )r;}r;(jUj}r;(j]j]j]j]j]UcolwidthK ujj;j]jj ubj )r;}r;(jUj}r;(j]j]j]j]j]UcolwidthKujj;j]jj ubj )r;}r;(jUj}r;(j]j]j]j]j]UcolwidthKujj;j]jj ubj )r;}r;(jUj}r;(j]j]j]j]j]UcolwidthK$ujj;j]jj ubj )r;}r;(jUj}r;(j]j]j]j]j]ujj;j]r;j )r;}r;(jUj}r;(j]j]j]j]j]ujj;j]r;(j )r;}r;(jUj}r;(j]j]j]j]j]ujj;j]r;j)r;}r;(jXIndexr;jj;jj3jjj}r;(j]j]j]j]j]ujKRj]r;jXIndexr;r;}r;(jj;jj;ubaubajj ubj )r;}r;(jUj}r;(j]j]j]j]j]ujj;j]r;j)r;}r;(jXAddrr;jj;jj3jjj}r;(j]j]j]j]j]ujKRj]r;jXAddrr;r;}r;(jj;jj;ubaubajj ubj )r;}r;(jUj}r;(j]j]j]j]j]ujj;j]r;j)r;}r;(jXValuer;jj;jj3jjj}r;(j]j]j]j]j]ujKRj]r;jXValuer;r;}r;(jj;jj;ubaubajj ubj )r;}r;(jUj}r;(j]j]j]j]j]ujj;j]r;j)r;}r;(jXNamer;jj;jj3jjj}r;(j]j]j]j]j]ujKRj]r;jXNamer;r;}r;(jj;jj;ubaubajj ubj )r;}r;(jUj}r<(j]j]j]j]j]ujj;j]r<j)r<}r<(jXSourcer<jj;jj3jjj}r<(j]j]j]j]j]ujKRj]r<jXSourcer<r<}r <(jj<jj<ubaubajj ubj )r <}r <(jUj}r <(j]j]j]j]j]ujj;j]r <j)r<}r<(jX Descriptionr<jj <jj3jjj}r<(j]j]j]j]j]ujKRj]r<jX Descriptionr<r<}r<(jj<jj<ubaubajj ubejj ubajj ubj )r<}r<(jUj}r<(j]j]j]j]j]ujj;j]r<(j )r<}r<(jUj}r<(j]j]j]j]j]ujj<j]r<(j )r<}r<(jUj}r <(j]j]j]j]j]ujj<j]r!<j)r"<}r#<(jX64r$<jj<jj3jjj}r%<(j]j]j]j]j]ujKTj]r&<jX64r'<r(<}r)<(jj$<jj"<ubaubajj ubj )r*<}r+<(jUj}r,<(j]j]j]j]j]ujj<j]r-<j)r.<}r/<(jX 0x4A002830r0<jj*<jj3jjj}r1<(j]j]j]j]j]ujKTj]r2<jX 0x4A002830r3<r4<}r5<(jj0<jj.<ubaubajj ubj )r6<}r7<(jUj}r8<(j]j]j]j]j]ujj<j]r9<j)r:<}r;<(jX42r<<jj6<jj3jjj}r=<(j]j]j]j]j]ujKTj]r><jX42r?<r@<}rA<(jj<<jj:<ubaubajj ubj )rB<}rC<(jUj}rD<(j]j]j]j]j]ujj<j]rE<j)rF<}rG<(jXEVE1_IRQ_MBX0_USER2rH<jjB<jj3jjj}rI<(j]j]j]j]j]ujKTj]rJ<jXEVE1_IRQ_MBX0_USER2rK<rL<}rM<(jjH<jjF<ubaubajj ubj )rN<}rO<(jUj}rP<(j]j]j]j]j]ujj<j]rQ<j)rR<}rS<(jX EVE1_MAILBOX0rT<jjN<jj3jjj}rU<(j]j]j]j]j]ujKTj]rV<jX EVE1_MAILBOX0rW<rX<}rY<(jjT<jjR<ubaubajj ubj )rZ<}r[<(jUj}r\<(j]j]j]j]j]ujj<j]r]<j)r^<}r_<(jXEve1 Mailbox 0 user 2 interruptr`<jjZ<jj3jjj}ra<(j]j]j]j]j]ujKTj]rb<jXEve1 Mailbox 0 user 2 interruptrc<rd<}re<(jj`<jj^<ubaubajj ubejj ubj )rf<}rg<(jUj}rh<(j]j]j]j]j]ujj<j]ri<(j )rj<}rk<(jUj}rl<(j]j]j]j]j]ujjf<j]rm<j)rn<}ro<(jX65rp<jjj<jj3jjj}rq<(j]j]j]j]j]ujKVj]rr<jX65rs<rt<}ru<(jjp<jjn<ubaubajj ubj )rv<}rw<(jUj}rx<(j]j]j]j]j]ujjf<j]ry<j)rz<}r{<(jX 0x4A002834r|<jjv<jj3jjj}r}<(j]j]j]j]j]ujKVj]r~<jX 0x4A002834r<r<}r<(jj|<jjz<ubaubajj ubj )r<}r<(jUj}r<(j]j]j]j]j]ujjf<j]r<j)r<}r<(jX43r<jj<jj3jjj}r<(j]j]j]j]j]ujKVj]r<jX43r<r<}r<(jj<jj<ubaubajj ubj )r<}r<(jUj}r<(j]j]j]j]j]ujjf<j]r<j)r<}r<(jXEVE2_IRQ_MBX0_USER2r<jj<jj3jjj}r<(j]j]j]j]j]ujKVj]r<jXEVE2_IRQ_MBX0_USER2r<r<}r<(jj<jj<ubaubajj ubj )r<}r<(jUj}r<(j]j]j]j]j]ujjf<j]r<j)r<}r<(jX EVE2_MAILBOX0r<jj<jj3jjj}r<(j]j]j]j]j]ujKVj]r<jX EVE2_MAILBOX0r<r<}r<(jj<jj<ubaubajj ubj )r<}r<(jUj}r<(j]j]j]j]j]ujjf<j]r<j)r<}r<(jXEve2 Mailbox 0 user 2 interruptr<jj<jj3jjj}r<(j]j]j]j]j]ujKVj]r<jXEve2 Mailbox 0 user 2 interruptr<r<}r<(jj<jj<ubaubajj ubejj ubj )r<}r<(jUj}r<(j]j]j]j]j]ujj<j]r<(j )r<}r<(jUj}r<(j]j]j]j]j]ujj<j]r<j)r<}r<(jX66r<jj<jj3jjj}r<(j]j]j]j]j]ujKXj]r<jX66r<r<}r<(jj<jj<ubaubajj ubj )r<}r<(jUj}r<(j]j]j]j]j]ujj<j]r<j)r<}r<(jX 0x4A002834r<jj<jj3jjj}r<(j]j]j]j]j]ujKXj]r<jX 0x4A002834r<r<}r<(jj<jj<ubaubajj ubj )r<}r<(jUj}r<(j]j]j]j]j]ujj<j]r<j)r<}r<(jX44r<jj<jj3jjj}r<(j]j]j]j]j]ujKXj]r<jX44r<r<}r<(jj<jj<ubaubajj ubj )r<}r<(jUj}r<(j]j]j]j]j]ujj<j]r<j)r<}r<(jXMAILBOX5_IRQ_USER1r<jj<jj3jjj}r<(j]j]j]j]j]ujKXj]r<jXMAILBOX5_IRQ_USER1r<r<}r<(jj<jj<ubaubajj ubj )r<}r<(jUj}r<(j]j]j]j]j]ujj<j]r<j)r<}r<(jXMAILBOX5r<jj<jj3jjj}r<(j]j]j]j]j]ujKXj]r<jXMAILBOX5r<r<}r<(jj<jj<ubaubajj ubj )r<}r<(jUj}r<(j]j]j]j]j]ujj<j]r<j)r<}r<(jXMailbox 5 user 1 interruptr<jj<jj3jjj}r<(j]j]j]j]j]ujKXj]r<jXMailbox 5 user 1 interruptr<r<}r<(jj<jj<ubaubajj ubejj ubj )r<}r<(jUj}r=(j]j]j]j]j]ujj<j]r=(j )r=}r=(jUj}r=(j]j]j]j]j]ujj<j]r=j)r=}r=(jX67r=jj=jj3jjj}r =(j]j]j]j]j]ujKZj]r =jX67r =r =}r =(jj=jj=ubaubajj ubj )r=}r=(jUj}r=(j]j]j]j]j]ujj<j]r=j)r=}r=(jX 0x4A002838r=jj=jj3jjj}r=(j]j]j]j]j]ujKZj]r=jX 0x4A002838r=r=}r=(jj=jj=ubaubajj ubj )r=}r=(jUj}r=(j]j]j]j]j]ujj<j]r=j)r=}r=(jX45r =jj=jj3jjj}r!=(j]j]j]j]j]ujKZj]r"=jX45r#=r$=}r%=(jj =jj=ubaubajj ubj )r&=}r'=(jUj}r(=(j]j]j]j]j]ujj<j]r)=j)r*=}r+=(jXEVE3_IRQ_MBX0_USER2r,=jj&=jj3jjj}r-=(j]j]j]j]j]ujKZj]r.=jXEVE3_IRQ_MBX0_USER2r/=r0=}r1=(jj,=jj*=ubaubajj ubj )r2=}r3=(jUj}r4=(j]j]j]j]j]ujj<j]r5=j)r6=}r7=(jX EVE3_MAILBOX0r8=jj2=jj3jjj}r9=(j]j]j]j]j]ujKZj]r:=jX EVE3_MAILBOX0r;=r<=}r==(jj8=jj6=ubaubajj ubj )r>=}r?=(jUj}r@=(j]j]j]j]j]ujj<j]rA=j)rB=}rC=(jX Eve 3 Mailbox 0 user 2 interruptrD=jj>=jj3jjj}rE=(j]j]j]j]j]ujKZj]rF=jX Eve 3 Mailbox 0 user 2 interruptrG=rH=}rI=(jjD=jjB=ubaubajj ubejj ubj )rJ=}rK=(jUj}rL=(j]j]j]j]j]ujj<j]rM=(j )rN=}rO=(jUj}rP=(j]j]j]j]j]ujjJ=j]rQ=j)rR=}rS=(jX68rT=jjN=jj3jjj}rU=(j]j]j]j]j]ujK\j]rV=jX68rW=rX=}rY=(jjT=jjR=ubaubajj ubj )rZ=}r[=(jUj}r\=(j]j]j]j]j]ujjJ=j]r]=j)r^=}r_=(jX 0x4A002838r`=jjZ=jj3jjj}ra=(j]j]j]j]j]ujK\j]rb=jX 0x4A002838rc=rd=}re=(jj`=jj^=ubaubajj ubj )rf=}rg=(jUj}rh=(j]j]j]j]j]ujjJ=j]ri=j)rj=}rk=(jX46rl=jjf=jj3jjj}rm=(j]j]j]j]j]ujK\j]rn=jX46ro=rp=}rq=(jjl=jjj=ubaubajj ubj )rr=}rs=(jUj}rt=(j]j]j]j]j]ujjJ=j]ru=j)rv=}rw=(jXEVE4_IRQ_MBX0_USER2rx=jjr=jj3jjj}ry=(j]j]j]j]j]ujK\j]rz=jXEVE4_IRQ_MBX0_USER2r{=r|=}r}=(jjx=jjv=ubaubajj ubj )r~=}r=(jUj}r=(j]j]j]j]j]ujjJ=j]r=j)r=}r=(jX EVE4_MAILBOX0r=jj~=jj3jjj}r=(j]j]j]j]j]ujK\j]r=jX EVE4_MAILBOX0r=r=}r=(jj=jj=ubaubajj ubj )r=}r=(jUj}r=(j]j]j]j]j]ujjJ=j]r=j)r=}r=(jXEve4 Mailbox 0 user 2 interruptr=jj=jj3jjj}r=(j]j]j]j]j]ujK\j]r=jXEve4 Mailbox 0 user 2 interruptr=r=}r=(jj=jj=ubaubajj ubejj ubj )r=}r=(jUj}r=(j]j]j]j]j]ujj<j]r=(j )r=}r=(jUj}r=(j]j]j]j]j]ujj=j]r=j)r=}r=(jX69r=jj=jj3jjj}r=(j]j]j]j]j]ujK^j]r=jX69r=r=}r=(jj=jj=ubaubajj ubj )r=}r=(jUj}r=(j]j]j]j]j]ujj=j]r=j)r=}r=(jX 0x4A00283Cr=jj=jj3jjj}r=(j]j]j]j]j]ujK^j]r=jX 0x4A00283Cr=r=}r=(jj=jj=ubaubajj ubj )r=}r=(jUj}r=(j]j]j]j]j]ujj=j]r=j)r=}r=(jX47r=jj=jj3jjj}r=(j]j]j]j]j]ujK^j]r=jX47r=r=}r=(jj=jj=ubaubajj ubj )r=}r=(jUj}r=(j]j]j]j]j]ujj=j]r=j)r=}r=(jXMAILBOX7_IRQ_USER2r=jj=jj3jjj}r=(j]j]j]j]j]ujK^j]r=jXMAILBOX7_IRQ_USER2r=r=}r=(jj=jj=ubaubajj ubj )r=}r=(jUj}r=(j]j]j]j]j]ujj=j]r=j)r=}r=(jXMAILBOX7r=jj=jj3jjj}r=(j]j]j]j]j]ujK^j]r=jXMAILBOX7r=r=}r=(jj=jj=ubaubajj ubj )r=}r=(jUj}r=(j]j]j]j]j]ujj=j]r=j)r=}r=(jXMailbox 7 user 2 interruptr=jj=jj3jjj}r=(j]j]j]j]j]ujK^j]r=jXMailbox 7 user 2 interruptr=r=}r=(jj=jj=ubaubajj ubejj ubj )r=}r=(jUj}r=(j]j]j]j]j]ujj<j]r=(j )r=}r=(jUj}r=(j]j]j]j]j]ujj=j]r=j)r=}r=(jX70r=jj=jj3jjj}r=(j]j]j]j]j]ujK`j]r=jX70r=r=}r=(jj=jj=ubaubajj ubj )r=}r=(jUj}r=(j]j]j]j]j]ujj=j]r=j)r=}r=(jX 0x4A00283Cr=jj=jj3jjj}r=(j]j]j]j]j]ujK`j]r=jX 0x4A00283Cr=r=}r=(jj=jj=ubaubajj ubj )r=}r=(jUj}r>(j]j]j]j]j]ujj=j]r>j)r>}r>(jX48r>jj=jj3jjj}r>(j]j]j]j]j]ujK`j]r>jX48r>r>}r >(jj>jj>ubaubajj ubj )r >}r >(jUj}r >(j]j]j]j]j]ujj=j]r >j)r>}r>(jXMAILBOX8_IRQ_USER2r>jj >jj3jjj}r>(j]j]j]j]j]ujK`j]r>jXMAILBOX8_IRQ_USER2r>r>}r>(jj>jj>ubaubajj ubj )r>}r>(jUj}r>(j]j]j]j]j]ujj=j]r>j)r>}r>(jXMAILBOX8r>jj>jj3jjj}r>(j]j]j]j]j]ujK`j]r>jXMAILBOX8r>r >}r!>(jj>jj>ubaubajj ubj )r">}r#>(jUj}r$>(j]j]j]j]j]ujj=j]r%>j)r&>}r'>(jXMailbox 8 user 2 interruptr(>jj">jj3jjj}r)>(j]j]j]j]j]ujK`j]r*>jXMailbox 8 user 2 interruptr+>r,>}r->(jj(>jj&>ubaubajj ubejj ubj )r.>}r/>(jUj}r0>(j]j]j]j]j]ujj<j]r1>(j )r2>}r3>(jUj}r4>(j]j]j]j]j]ujj.>j]r5>j)r6>}r7>(jX71r8>jj2>jj3jjj}r9>(j]j]j]j]j]ujKbj]r:>jX71r;>r<>}r=>(jj8>jj6>ubaubajj ubj )r>>}r?>(jUj}r@>(j]j]j]j]j]ujj.>j]rA>j)rB>}rC>(jX 0x4A002840rD>jj>>jj3jjj}rE>(j]j]j]j]j]ujKbj]rF>jX 0x4A002840rG>rH>}rI>(jjD>jjB>ubaubajj ubj )rJ>}rK>(jUj}rL>(j]j]j]j]j]ujj.>j]rM>j)rN>}rO>(jX49rP>jjJ>jj3jjj}rQ>(j]j]j]j]j]ujKbj]rR>jX49rS>rT>}rU>(jjP>jjN>ubaubajj ubj )rV>}rW>(jUj}rX>(j]j]j]j]j]ujj.>j]rY>j)rZ>}r[>(jXEVE1_IRQ_MBX1_USER3r\>jjV>jj3jjj}r]>(j]j]j]j]j]ujKbj]r^>jXEVE1_IRQ_MBX1_USER3r_>r`>}ra>(jj\>jjZ>ubaubajj ubj )rb>}rc>(jUj}rd>(j]j]j]j]j]ujj.>j]re>j)rf>}rg>(jX EVE1_MAILBOX1rh>jjb>jj3jjj}ri>(j]j]j]j]j]ujKbj]rj>jX EVE1_MAILBOX1rk>rl>}rm>(jjh>jjf>ubaubajj ubj )rn>}ro>(jUj}rp>(j]j]j]j]j]ujj.>j]rq>j)rr>}rs>(jXEve1 Mailbox 1 user 3 interruptrt>jjn>jj3jjj}ru>(j]j]j]j]j]ujKbj]rv>jXEve1 Mailbox 1 user 3 interruptrw>rx>}ry>(jjt>jjr>ubaubajj ubejj ubj )rz>}r{>(jUj}r|>(j]j]j]j]j]ujj<j]r}>(j )r~>}r>(jUj}r>(j]j]j]j]j]ujjz>j]r>j)r>}r>(jX72r>jj~>jj3jjj}r>(j]j]j]j]j]ujKdj]r>jX72r>r>}r>(jj>jj>ubaubajj ubj )r>}r>(jUj}r>(j]j]j]j]j]ujjz>j]r>j)r>}r>(jX 0x4A002840r>jj>jj3jjj}r>(j]j]j]j]j]ujKdj]r>jX 0x4A002840r>r>}r>(jj>jj>ubaubajj ubj )r>}r>(jUj}r>(j]j]j]j]j]ujjz>j]r>j)r>}r>(jX50r>jj>jj3jjj}r>(j]j]j]j]j]ujKdj]r>jX50r>r>}r>(jj>jj>ubaubajj ubj )r>}r>(jUj}r>(j]j]j]j]j]ujjz>j]r>j)r>}r>(jXEVE2_IRQ_MBX1_USER3r>jj>jj3jjj}r>(j]j]j]j]j]ujKdj]r>jXEVE2_IRQ_MBX1_USER3r>r>}r>(jj>jj>ubaubajj ubj )r>}r>(jUj}r>(j]j]j]j]j]ujjz>j]r>j)r>}r>(jX EVE2_MAILBOX1r>jj>jj3jjj}r>(j]j]j]j]j]ujKdj]r>jX EVE2_MAILBOX1r>r>}r>(jj>jj>ubaubajj ubj )r>}r>(jUj}r>(j]j]j]j]j]ujjz>j]r>j)r>}r>(jXEve2 Mailbox 1 user 3 interruptr>jj>jj3jjj}r>(j]j]j]j]j]ujKdj]r>jXEve2 Mailbox 1 user 3 interruptr>r>}r>(jj>jj>ubaubajj ubejj ubj )r>}r>(jUj}r>(j]j]j]j]j]ujj<j]r>(j )r>}r>(jUj}r>(j]j]j]j]j]ujj>j]r>j)r>}r>(jX73r>jj>jj3jjj}r>(j]j]j]j]j]ujKfj]r>jX73r>r>}r>(jj>jj>ubaubajj ubj )r>}r>(jUj}r>(j]j]j]j]j]ujj>j]r>j)r>}r>(jX 0x4A002844r>jj>jj3jjj}r>(j]j]j]j]j]ujKfj]r>jX 0x4A002844r>r>}r>(jj>jj>ubaubajj ubj )r>}r>(jUj}r>(j]j]j]j]j]ujj>j]r>j)r>}r>(jX51r>jj>jj3jjj}r>(j]j]j]j]j]ujKfj]r>jX51r>r>}r>(jj>jj>ubaubajj ubj )r>}r>(jUj}r>(j]j]j]j]j]ujj>j]r>j)r>}r>(jXMAILBOX5_IRQ_USER3r>jj>jj3jjj}r>(j]j]j]j]j]ujKfj]r>jXMAILBOX5_IRQ_USER3r>r>}r>(jj>jj>ubaubajj ubj )r>}r>(jUj}r>(j]j]j]j]j]ujj>j]r>j)r>}r>(jXMAILBOX5r?jj>jj3jjj}r?(j]j]j]j]j]ujKfj]r?jXMAILBOX5r?r?}r?(jj?jj>ubaubajj ubj )r?}r?(jUj}r?(j]j]j]j]j]ujj>j]r ?j)r ?}r ?(jXMailbox 5 user 3 interruptr ?jj?jj3jjj}r ?(j]j]j]j]j]ujKfj]r?jXMailbox 5 user 3 interruptr?r?}r?(jj ?jj ?ubaubajj ubejj ubj )r?}r?(jUj}r?(j]j]j]j]j]ujj<j]r?(j )r?}r?(jUj}r?(j]j]j]j]j]ujj?j]r?j)r?}r?(jX74r?jj?jj3jjj}r?(j]j]j]j]j]ujKhj]r?jX74r?r ?}r!?(jj?jj?ubaubajj ubj )r"?}r#?(jUj}r$?(j]j]j]j]j]ujj?j]r%?j)r&?}r'?(jX 0x4A002844r(?jj"?jj3jjj}r)?(j]j]j]j]j]ujKhj]r*?jX 0x4A002844r+?r,?}r-?(jj(?jj&?ubaubajj ubj )r.?}r/?(jUj}r0?(j]j]j]j]j]ujj?j]r1?j)r2?}r3?(jX52r4?jj.?jj3jjj}r5?(j]j]j]j]j]ujKhj]r6?jX52r7?r8?}r9?(jj4?jj2?ubaubajj ubj )r:?}r;?(jUj}r?}r??(jXEVE3_IRQ_MBX1_USER3r@?jj:?jj3jjj}rA?(j]j]j]j]j]ujKhj]rB?jXEVE3_IRQ_MBX1_USER3rC?rD?}rE?(jj@?jj>?ubaubajj ubj )rF?}rG?(jUj}rH?(j]j]j]j]j]ujj?j]rI?j)rJ?}rK?(jX EVE3_MAILBOX1rL?jjF?jj3jjj}rM?(j]j]j]j]j]ujKhj]rN?jX EVE3_MAILBOX1rO?rP?}rQ?(jjL?jjJ?ubaubajj ubj )rR?}rS?(jUj}rT?(j]j]j]j]j]ujj?j]rU?j)rV?}rW?(jX Eve 3 Mailbox 1 user 3 interruptrX?jjR?jj3jjj}rY?(j]j]j]j]j]ujKhj]rZ?jX Eve 3 Mailbox 1 user 3 interruptr[?r\?}r]?(jjX?jjV?ubaubajj ubejj ubj )r^?}r_?(jUj}r`?(j]j]j]j]j]ujj<j]ra?(j )rb?}rc?(jUj}rd?(j]j]j]j]j]ujj^?j]re?j)rf?}rg?(jX75rh?jjb?jj3jjj}ri?(j]j]j]j]j]ujKjj]rj?jX75rk?rl?}rm?(jjh?jjf?ubaubajj ubj )rn?}ro?(jUj}rp?(j]j]j]j]j]ujj^?j]rq?j)rr?}rs?(jX 0x4A002848rt?jjn?jj3jjj}ru?(j]j]j]j]j]ujKjj]rv?jX 0x4A002848rw?rx?}ry?(jjt?jjr?ubaubajj ubj )rz?}r{?(jUj}r|?(j]j]j]j]j]ujj^?j]r}?j)r~?}r?(jX53r?jjz?jj3jjj}r?(j]j]j]j]j]ujKjj]r?jX53r?r?}r?(jj?jj~?ubaubajj ubj )r?}r?(jUj}r?(j]j]j]j]j]ujj^?j]r?j)r?}r?(jXEVE4_IRQ_MBX1_USER3r?jj?jj3jjj}r?(j]j]j]j]j]ujKjj]r?jXEVE4_IRQ_MBX1_USER3r?r?}r?(jj?jj?ubaubajj ubj )r?}r?(jUj}r?(j]j]j]j]j]ujj^?j]r?j)r?}r?(jX EVE4_MAILBOX1r?jj?jj3jjj}r?(j]j]j]j]j]ujKjj]r?jX EVE4_MAILBOX1r?r?}r?(jj?jj?ubaubajj ubj )r?}r?(jUj}r?(j]j]j]j]j]ujj^?j]r?j)r?}r?(jXEve4 Mailbox 1 user 3 interruptr?jj?jj3jjj}r?(j]j]j]j]j]ujKjj]r?jXEve4 Mailbox 1 user 3 interruptr?r?}r?(jj?jj?ubaubajj ubejj ubj )r?}r?(jUj}r?(j]j]j]j]j]ujj<j]r?(j )r?}r?(jUj}r?(j]j]j]j]j]ujj?j]r?j)r?}r?(jX76r?jj?jj3jjj}r?(j]j]j]j]j]ujKlj]r?jX76r?r?}r?(jj?jj?ubaubajj ubj )r?}r?(jUj}r?(j]j]j]j]j]ujj?j]r?j)r?}r?(jX 0x4A002848r?jj?jj3jjj}r?(j]j]j]j]j]ujKlj]r?jX 0x4A002848r?r?}r?(jj?jj?ubaubajj ubj )r?}r?(jUj}r?(j]j]j]j]j]ujj?j]r?j)r?}r?(jX54r?jj?jj3jjj}r?(j]j]j]j]j]ujKlj]r?jX54r?r?}r?(jj?jj?ubaubajj ubj )r?}r?(jUj}r?(j]j]j]j]j]ujj?j]r?j)r?}r?(jXMAILBOX8_IRQ_USER2r?jj?jj3jjj}r?(j]j]j]j]j]ujKlj]r?jXMAILBOX8_IRQ_USER2r?r?}r?(jj?jj?ubaubajj ubj )r?}r?(jUj}r?(j]j]j]j]j]ujj?j]r?j)r?}r?(jXMAILBOX8r?jj?jj3jjj}r?(j]j]j]j]j]ujKlj]r?jXMAILBOX8r?r?}r?(jj?jj?ubaubajj ubj )r?}r?(jUj}r?(j]j]j]j]j]ujj?j]r?j)r?}r?(jXMailbox 8 user 2 interruptr?jj?jj3jjj}r?(j]j]j]j]j]ujKlj]r?jXMailbox 8 user 2 interruptr?r?}r?(jj?jj?ubaubajj ubejj ubejj ubejj ubaubjc)r?}r?(jUjj+4jj3jjfj}r?(j]j]j]j]j]ujKojhj]r?ji)r?}r?(jUjlKjj?jj3jjj}r?(j]j]j]j]j]ujKjhj]ubaubj)r?}r?(jX**IPU2 Interrupt Mapping**r?jj+4jj3jjj}r@(j]j]j]j]j]ujKqjhj]r@j)r@}r@(jj?j}r@(j]j]j]j]j]ujj?j]r@jXIPU2 Interrupt Mappingr@r@}r@(jUjj@ubajjubaubjy )r @}r @(jUjj+4jj3jj j}r @(j]j]j]j]j]ujNjhj]r @j~ )r @}r@(jUj}r@(j]j]j]j]j]UcolsKujj @j]r@(j )r@}r@(jUj}r@(j]j]j]j]j]UcolwidthK ujj @j]jj ubj )r@}r@(jUj}r@(j]j]j]j]j]UcolwidthKujj @j]jj ubj )r@}r@(jUj}r@(j]j]j]j]j]UcolwidthK ujj @j]jj ubj )r@}r@(jUj}r@(j]j]j]j]j]UcolwidthKujj @j]jj ubj )r@}r@(jUj}r@(j]j]j]j]j]UcolwidthKujj @j]jj ubj )r @}r!@(jUj}r"@(j]j]j]j]j]UcolwidthK$ujj @j]jj ubj )r#@}r$@(jUj}r%@(j]j]j]j]j]ujj @j]r&@j )r'@}r(@(jUj}r)@(j]j]j]j]j]ujj#@j]r*@(j )r+@}r,@(jUj}r-@(j]j]j]j]j]ujj'@j]r.@j)r/@}r0@(jXIndexr1@jj+@jj3jjj}r2@(j]j]j]j]j]ujKtj]r3@jXIndexr4@r5@}r6@(jj1@jj/@ubaubajj ubj )r7@}r8@(jUj}r9@(j]j]j]j]j]ujj'@j]r:@j)r;@}r<@(jXAddrr=@jj7@jj3jjj}r>@(j]j]j]j]j]ujKtj]r?@jXAddrr@@rA@}rB@(jj=@jj;@ubaubajj ubj )rC@}rD@(jUj}rE@(j]j]j]j]j]ujj'@j]rF@j)rG@}rH@(jXValuerI@jjC@jj3jjj}rJ@(j]j]j]j]j]ujKtj]rK@jXValuerL@rM@}rN@(jjI@jjG@ubaubajj ubj )rO@}rP@(jUj}rQ@(j]j]j]j]j]ujj'@j]rR@j)rS@}rT@(jXNamerU@jjO@jj3jjj}rV@(j]j]j]j]j]ujKtj]rW@jXNamerX@rY@}rZ@(jjU@jjS@ubaubajj ubj )r[@}r\@(jUj}r]@(j]j]j]j]j]ujj'@j]r^@j)r_@}r`@(jXSourcera@jj[@jj3jjj}rb@(j]j]j]j]j]ujKtj]rc@jXSourcerd@re@}rf@(jja@jj_@ubaubajj ubj )rg@}rh@(jUj}ri@(j]j]j]j]j]ujj'@j]rj@j)rk@}rl@(jX Descriptionrm@jjg@jj3jjj}rn@(j]j]j]j]j]ujKtj]ro@jX Descriptionrp@rq@}rr@(jjm@jjk@ubaubajj ubejj ubajj ubj )rs@}rt@(jUj}ru@(j]j]j]j]j]ujj @j]rv@(j )rw@}rx@(jUj}ry@(j]j]j]j]j]ujjs@j]rz@(j )r{@}r|@(jUj}r}@(j]j]j]j]j]ujjw@j]r~@j)r@}r@(jX64r@jj{@jj3jjj}r@(j]j]j]j]j]ujKvj]r@jX64r@r@}r@(jj@jj@ubaubajj ubj )r@}r@(jUj}r@(j]j]j]j]j]ujjw@j]r@j)r@}r@(jX 0x4A0028A4r@jj@jj3jjj}r@(j]j]j]j]j]ujKvj]r@jX 0x4A0028A4r@r@}r@(jj@jj@ubaubajj ubj )r@}r@(jUj}r@(j]j]j]j]j]ujjw@j]r@j)r@}r@(jX42r@jj@jj3jjj}r@(j]j]j]j]j]ujKvj]r@jX42r@r@}r@(jj@jj@ubaubajj ubj )r@}r@(jUj}r@(j]j]j]j]j]ujjw@j]r@j)r@}r@(jXEVE1_IRQ_MBX1_USER2r@jj@jj3jjj}r@(j]j]j]j]j]ujKvj]r@jXEVE1_IRQ_MBX1_USER2r@r@}r@(jj@jj@ubaubajj ubj )r@}r@(jUj}r@(j]j]j]j]j]ujjw@j]r@j)r@}r@(jX EVE1_MAILBOX1r@jj@jj3jjj}r@(j]j]j]j]j]ujKvj]r@jX EVE1_MAILBOX1r@r@}r@(jj@jj@ubaubajj ubj )r@}r@(jUj}r@(j]j]j]j]j]ujjw@j]r@j)r@}r@(jXEve1 Mailbox 1 user 2 interruptr@jj@jj3jjj}r@(j]j]j]j]j]ujKvj]r@jXEve1 Mailbox 1 user 2 interruptr@r@}r@(jj@jj@ubaubajj ubejj ubj )r@}r@(jUj}r@(j]j]j]j]j]ujjs@j]r@(j )r@}r@(jUj}r@(j]j]j]j]j]ujj@j]r@j)r@}r@(jX65r@jj@jj3jjj}r@(j]j]j]j]j]ujKxj]r@jX65r@r@}r@(jj@jj@ubaubajj ubj )r@}r@(jUj}r@(j]j]j]j]j]ujj@j]r@j)r@}r@(jX 0x4A0028A8r@jj@jj3jjj}r@(j]j]j]j]j]ujKxj]r@jX 0x4A0028A8r@r@}r@(jj@jj@ubaubajj ubj )r@}r@(jUj}r@(j]j]j]j]j]ujj@j]r@j)r@}r@(jX43r@jj@jj3jjj}r@(j]j]j]j]j]ujKxj]r@jX43r@r@}r@(jj@jj@ubaubajj ubj )r@}r@(jUj}r@(j]j]j]j]j]ujj@j]r@j)r@}r@(jXEVE2_IRQ_MBX1_USER2r@jj@jj3jjj}r@(j]j]j]j]j]ujKxj]r@jXEVE2_IRQ_MBX1_USER2r@r@}r@(jj@jj@ubaubajj ubj )r@}r@(jUj}r@(j]j]j]j]j]ujj@j]r@j)r@}r@(jX EVE2_MAILBOX1r@jj@jj3jjj}r@(j]j]j]j]j]ujKxj]r@jX EVE2_MAILBOX1rArA}rA(jj@jj@ubaubajj ubj )rA}rA(jUj}rA(j]j]j]j]j]ujj@j]rAj)rA}rA(jXEve2 Mailbox 1 user 2 interruptr AjjAjj3jjj}r A(j]j]j]j]j]ujKxj]r AjXEve2 Mailbox 1 user 2 interruptr Ar A}rA(jj AjjAubaubajj ubejj ubj )rA}rA(jUj}rA(j]j]j]j]j]ujjs@j]rA(j )rA}rA(jUj}rA(j]j]j]j]j]ujjAj]rAj)rA}rA(jX66rAjjAjj3jjj}rA(j]j]j]j]j]ujKzj]rAjX66rArA}rA(jjAjjAubaubajj ubj )rA}r A(jUj}r!A(j]j]j]j]j]ujjAj]r"Aj)r#A}r$A(jX 0x4A0028A8r%AjjAjj3jjj}r&A(j]j]j]j]j]ujKzj]r'AjX 0x4A0028A8r(Ar)A}r*A(jj%Ajj#Aubaubajj ubj )r+A}r,A(jUj}r-A(j]j]j]j]j]ujjAj]r.Aj)r/A}r0A(jX44r1Ajj+Ajj3jjj}r2A(j]j]j]j]j]ujKzj]r3AjX44r4Ar5A}r6A(jj1Ajj/Aubaubajj ubj )r7A}r8A(jUj}r9A(j]j]j]j]j]ujjAj]r:Aj)r;A}rA(j]j]j]j]j]ujKzj]r?AjXMAILBOX6_IRQ_USER1r@ArAA}rBA(jj=Ajj;Aubaubajj ubj )rCA}rDA(jUj}rEA(j]j]j]j]j]ujjAj]rFAj)rGA}rHA(jXMAILBOX6rIAjjCAjj3jjj}rJA(j]j]j]j]j]ujKzj]rKAjXMAILBOX6rLArMA}rNA(jjIAjjGAubaubajj ubj )rOA}rPA(jUj}rQA(j]j]j]j]j]ujjAj]rRAj)rSA}rTA(jXMailbox 6 user 1 interruptrUAjjOAjj3jjj}rVA(j]j]j]j]j]ujKzj]rWAjXMailbox 6 user 1 interruptrXArYA}rZA(jjUAjjSAubaubajj ubejj ubj )r[A}r\A(jUj}r]A(j]j]j]j]j]ujjs@j]r^A(j )r_A}r`A(jUj}raA(j]j]j]j]j]ujj[Aj]rbAj)rcA}rdA(jX67reAjj_Ajj3jjj}rfA(j]j]j]j]j]ujK|j]rgAjX67rhAriA}rjA(jjeAjjcAubaubajj ubj )rkA}rlA(jUj}rmA(j]j]j]j]j]ujj[Aj]rnAj)roA}rpA(jX 0x4A0028ACrqAjjkAjj3jjj}rrA(j]j]j]j]j]ujK|j]rsAjX 0x4A0028ACrtAruA}rvA(jjqAjjoAubaubajj ubj )rwA}rxA(jUj}ryA(j]j]j]j]j]ujj[Aj]rzAj)r{A}r|A(jX45r}AjjwAjj3jjj}r~A(j]j]j]j]j]ujK|j]rAjX45rArA}rA(jj}Ajj{Aubaubajj ubj )rA}rA(jUj}rA(j]j]j]j]j]ujj[Aj]rAj)rA}rA(jXEVE3_IRQ_MBX1_USER2rAjjAjj3jjj}rA(j]j]j]j]j]ujK|j]rAjXEVE3_IRQ_MBX1_USER2rArA}rA(jjAjjAubaubajj ubj )rA}rA(jUj}rA(j]j]j]j]j]ujj[Aj]rAj)rA}rA(jX EVE3_MAILBOX1rAjjAjj3jjj}rA(j]j]j]j]j]ujK|j]rAjX EVE3_MAILBOX1rArA}rA(jjAjjAubaubajj ubj )rA}rA(jUj}rA(j]j]j]j]j]ujj[Aj]rAj)rA}rA(jX Eve 3 Mailbox 1 user 2 interruptrAjjAjj3jjj}rA(j]j]j]j]j]ujK|j]rAjX Eve 3 Mailbox 1 user 2 interruptrArA}rA(jjAjjAubaubajj ubejj ubj )rA}rA(jUj}rA(j]j]j]j]j]ujjs@j]rA(j )rA}rA(jUj}rA(j]j]j]j]j]ujjAj]rAj)rA}rA(jX68rAjjAjj3jjj}rA(j]j]j]j]j]ujK~j]rAjX68rArA}rA(jjAjjAubaubajj ubj )rA}rA(jUj}rA(j]j]j]j]j]ujjAj]rAj)rA}rA(jX 0x4A0028ACrAjjAjj3jjj}rA(j]j]j]j]j]ujK~j]rAjX 0x4A0028ACrArA}rA(jjAjjAubaubajj ubj )rA}rA(jUj}rA(j]j]j]j]j]ujjAj]rAj)rA}rA(jX46rAjjAjj3jjj}rA(j]j]j]j]j]ujK~j]rAjX46rArA}rA(jjAjjAubaubajj ubj )rA}rA(jUj}rA(j]j]j]j]j]ujjAj]rAj)rA}rA(jXEVE4_IRQ_MBX1_USER2rAjjAjj3jjj}rA(j]j]j]j]j]ujK~j]rAjXEVE4_IRQ_MBX1_USER2rArA}rA(jjAjjAubaubajj ubj )rA}rA(jUj}rA(j]j]j]j]j]ujjAj]rAj)rA}rA(jX EVE4_MAILBOX1rAjjAjj3jjj}rA(j]j]j]j]j]ujK~j]rAjX EVE4_MAILBOX1rArA}rA(jjAjjAubaubajj ubj )rA}rA(jUj}rA(j]j]j]j]j]ujjAj]rAj)rA}rA(jXEve4 Mailbox 1 user 2 interruptrAjjAjj3jjj}rA(j]j]j]j]j]ujK~j]rAjXEve4 Mailbox 1 user 2 interruptrArA}rA(jjAjjAubaubajj ubejj ubj )rA}rA(jUj}rA(j]j]j]j]j]ujjs@j]rA(j )rA}rA(jUj}rA(j]j]j]j]j]ujjAj]rAj)rA}rA(jX69rAjjAjj3jjj}rA(j]j]j]j]j]ujKj]rAjX69rBrB}rB(jjAjjAubaubajj ubj )rB}rB(jUj}rB(j]j]j]j]j]ujjAj]rBj)rB}rB(jX 0x4A0028B0r BjjBjj3jjj}r B(j]j]j]j]j]ujKj]r BjX 0x4A0028B0r Br B}rB(jj BjjBubaubajj ubj )rB}rB(jUj}rB(j]j]j]j]j]ujjAj]rBj)rB}rB(jX47rBjjBjj3jjj}rB(j]j]j]j]j]ujKj]rBjX47rBrB}rB(jjBjjBubaubajj ubj )rB}rB(jUj}rB(j]j]j]j]j]ujjAj]rBj)rB}r B(jXMAILBOX7_IRQ_USER3r!BjjBjj3jjj}r"B(j]j]j]j]j]ujKj]r#BjXMAILBOX7_IRQ_USER3r$Br%B}r&B(jj!BjjBubaubajj ubj )r'B}r(B(jUj}r)B(j]j]j]j]j]ujjAj]r*Bj)r+B}r,B(jXMAILBOX7r-Bjj'Bjj3jjj}r.B(j]j]j]j]j]ujKj]r/BjXMAILBOX7r0Br1B}r2B(jj-Bjj+Bubaubajj ubj )r3B}r4B(jUj}r5B(j]j]j]j]j]ujjAj]r6Bj)r7B}r8B(jXMailbox 7 user 3 interruptr9Bjj3Bjj3jjj}r:B(j]j]j]j]j]ujKj]r;BjXMailbox 7 user 3 interruptrB(jj9Bjj7Bubaubajj ubejj ubj )r?B}r@B(jUj}rAB(j]j]j]j]j]ujjs@j]rBB(j )rCB}rDB(jUj}rEB(j]j]j]j]j]ujj?Bj]rFBj)rGB}rHB(jX70rIBjjCBjj3jjj}rJB(j]j]j]j]j]ujKj]rKBjX70rLBrMB}rNB(jjIBjjGBubaubajj ubj )rOB}rPB(jUj}rQB(j]j]j]j]j]ujj?Bj]rRBj)rSB}rTB(jX 0x4A0028B0rUBjjOBjj3jjj}rVB(j]j]j]j]j]ujKj]rWBjX 0x4A0028B0rXBrYB}rZB(jjUBjjSBubaubajj ubj )r[B}r\B(jUj}r]B(j]j]j]j]j]ujj?Bj]r^Bj)r_B}r`B(jX48raBjj[Bjj3jjj}rbB(j]j]j]j]j]ujKj]rcBjX48rdBreB}rfB(jjaBjj_Bubaubajj ubj )rgB}rhB(jUj}riB(j]j]j]j]j]ujj?Bj]rjBj)rkB}rlB(jXMAILBOX8_IRQ_USER3rmBjjgBjj3jjj}rnB(j]j]j]j]j]ujKj]roBjXMAILBOX8_IRQ_USER3rpBrqB}rrB(jjmBjjkBubaubajj ubj )rsB}rtB(jUj}ruB(j]j]j]j]j]ujj?Bj]rvBj)rwB}rxB(jXMAILBOX8ryBjjsBjj3jjj}rzB(j]j]j]j]j]ujKj]r{BjXMAILBOX8r|Br}B}r~B(jjyBjjwBubaubajj ubj )rB}rB(jUj}rB(j]j]j]j]j]ujj?Bj]rBj)rB}rB(jXMailbox 8 user 3 interruptrBjjBjj3jjj}rB(j]j]j]j]j]ujKj]rBjXMailbox 8 user 3 interruptrBrB}rB(jjBjjBubaubajj ubejj ubj )rB}rB(jUj}rB(j]j]j]j]j]ujjs@j]rB(j )rB}rB(jUj}rB(j]j]j]j]j]ujjBj]rBj)rB}rB(jX71rBjjBjj3jjj}rB(j]j]j]j]j]ujKj]rBjX71rBrB}rB(jjBjjBubaubajj ubj )rB}rB(jUj}rB(j]j]j]j]j]ujjBj]rBj)rB}rB(jX 0x4A0028B4rBjjBjj3jjj}rB(j]j]j]j]j]ujKj]rBjX 0x4A0028B4rBrB}rB(jjBjjBubaubajj ubj )rB}rB(jUj}rB(j]j]j]j]j]ujjBj]rBj)rB}rB(jX49rBjjBjj3jjj}rB(j]j]j]j]j]ujKj]rBjX49rBrB}rB(jjBjjBubaubajj ubj )rB}rB(jUj}rB(j]j]j]j]j]ujjBj]rBj)rB}rB(jXEVE1_IRQ_MBX1_USER3rBjjBjj3jjj}rB(j]j]j]j]j]ujKj]rBjXEVE1_IRQ_MBX1_USER3rBrB}rB(jjBjjBubaubajj ubj )rB}rB(jUj}rB(j]j]j]j]j]ujjBj]rBj)rB}rB(jX EVE1_MAILBOX1rBjjBjj3jjj}rB(j]j]j]j]j]ujKj]rBjX EVE1_MAILBOX1rBrB}rB(jjBjjBubaubajj ubj )rB}rB(jUj}rB(j]j]j]j]j]ujjBj]rBj)rB}rB(jXEve1 Mailbox 1 user 3 interruptrBjjBjj3jjj}rB(j]j]j]j]j]ujKj]rBjXEve1 Mailbox 1 user 3 interruptrBrB}rB(jjBjjBubaubajj ubejj ubj )rB}rB(jUj}rB(j]j]j]j]j]ujjs@j]rB(j )rB}rB(jUj}rB(j]j]j]j]j]ujjBj]rBj)rB}rB(jX72rBjjBjj3jjj}rB(j]j]j]j]j]ujKj]rBjX72rBrB}rB(jjBjjBubaubajj ubj )rB}rB(jUj}rB(j]j]j]j]j]ujjBj]rBj)rB}rB(jX 0x4A0028B4rBjjBjj3jjj}rB(j]j]j]j]j]ujKj]rBjX 0x4A0028B4rBrB}rB(jjBjjBubaubajj ubj )rB}rB(jUj}rB(j]j]j]j]j]ujjBj]rBj)rB}rB(jX50rBjjBjj3jjj}rB(j]j]j]j]j]ujKj]rBjX50rBrB}rB(jjBjjBubaubajj ubj )rB}rC(jUj}rC(j]j]j]j]j]ujjBj]rCj)rC}rC(jXEVE2_IRQ_MBX1_USER3rCjjBjj3jjj}rC(j]j]j]j]j]ujKj]rCjXEVE2_IRQ_MBX1_USER3rCr C}r C(jjCjjCubaubajj ubj )r C}r C(jUj}r C(j]j]j]j]j]ujjBj]rCj)rC}rC(jX EVE2_MAILBOX1rCjj Cjj3jjj}rC(j]j]j]j]j]ujKj]rCjX EVE2_MAILBOX1rCrC}rC(jjCjjCubaubajj ubj )rC}rC(jUj}rC(j]j]j]j]j]ujjBj]rCj)rC}rC(jXEve2 Mailbox 1 user 3 interruptrCjjCjj3jjj}rC(j]j]j]j]j]ujKj]rCjXEve2 Mailbox 1 user 3 interruptr Cr!C}r"C(jjCjjCubaubajj ubejj ubj )r#C}r$C(jUj}r%C(j]j]j]j]j]ujjs@j]r&C(j )r'C}r(C(jUj}r)C(j]j]j]j]j]ujj#Cj]r*Cj)r+C}r,C(jX73r-Cjj'Cjj3jjj}r.C(j]j]j]j]j]ujKj]r/CjX73r0Cr1C}r2C(jj-Cjj+Cubaubajj ubj )r3C}r4C(jUj}r5C(j]j]j]j]j]ujj#Cj]r6Cj)r7C}r8C(jX 0x4A0028B8r9Cjj3Cjj3jjj}r:C(j]j]j]j]j]ujKj]r;CjX 0x4A0028B8rC(jj9Cjj7Cubaubajj ubj )r?C}r@C(jUj}rAC(j]j]j]j]j]ujj#Cj]rBCj)rCC}rDC(jX51rECjj?Cjj3jjj}rFC(j]j]j]j]j]ujKj]rGCjX51rHCrIC}rJC(jjECjjCCubaubajj ubj )rKC}rLC(jUj}rMC(j]j]j]j]j]ujj#Cj]rNCj)rOC}rPC(jXMAILBOX6_IRQ_USER3rQCjjKCjj3jjj}rRC(j]j]j]j]j]ujKj]rSCjXMAILBOX6_IRQ_USER3rTCrUC}rVC(jjQCjjOCubaubajj ubj )rWC}rXC(jUj}rYC(j]j]j]j]j]ujj#Cj]rZCj)r[C}r\C(jXMAILBOX6r]CjjWCjj3jjj}r^C(j]j]j]j]j]ujKj]r_CjXMAILBOX6r`CraC}rbC(jj]Cjj[Cubaubajj ubj )rcC}rdC(jUj}reC(j]j]j]j]j]ujj#Cj]rfCj)rgC}rhC(jXMailbox 6 user 3 interruptriCjjcCjj3jjj}rjC(j]j]j]j]j]ujKj]rkCjXMailbox 6 user 3 interruptrlCrmC}rnC(jjiCjjgCubaubajj ubejj ubj )roC}rpC(jUj}rqC(j]j]j]j]j]ujjs@j]rrC(j )rsC}rtC(jUj}ruC(j]j]j]j]j]ujjoCj]rvCj)rwC}rxC(jX74ryCjjsCjj3jjj}rzC(j]j]j]j]j]ujKj]r{CjX74r|Cr}C}r~C(jjyCjjwCubaubajj ubj )rC}rC(jUj}rC(j]j]j]j]j]ujjoCj]rCj)rC}rC(jX 0x4A0028B8rCjjCjj3jjj}rC(j]j]j]j]j]ujKj]rCjX 0x4A0028B8rCrC}rC(jjCjjCubaubajj ubj )rC}rC(jUj}rC(j]j]j]j]j]ujjoCj]rCj)rC}rC(jX52rCjjCjj3jjj}rC(j]j]j]j]j]ujKj]rCjX52rCrC}rC(jjCjjCubaubajj ubj )rC}rC(jUj}rC(j]j]j]j]j]ujjoCj]rCj)rC}rC(jXEVE3_IRQ_MBX1_USER3rCjjCjj3jjj}rC(j]j]j]j]j]ujKj]rCjXEVE3_IRQ_MBX1_USER3rCrC}rC(jjCjjCubaubajj ubj )rC}rC(jUj}rC(j]j]j]j]j]ujjoCj]rCj)rC}rC(jX EVE3_MAILBOX1rCjjCjj3jjj}rC(j]j]j]j]j]ujKj]rCjX EVE3_MAILBOX1rCrC}rC(jjCjjCubaubajj ubj )rC}rC(jUj}rC(j]j]j]j]j]ujjoCj]rCj)rC}rC(jX Eve 3 Mailbox 1 user 3 interruptrCjjCjj3jjj}rC(j]j]j]j]j]ujKj]rCjX Eve 3 Mailbox 1 user 3 interruptrCrC}rC(jjCjjCubaubajj ubejj ubj )rC}rC(jUj}rC(j]j]j]j]j]ujjs@j]rC(j )rC}rC(jUj}rC(j]j]j]j]j]ujjCj]rCj)rC}rC(jX75rCjjCjj3jjj}rC(j]j]j]j]j]ujKj]rCjX75rCrC}rC(jjCjjCubaubajj ubj )rC}rC(jUj}rC(j]j]j]j]j]ujjCj]rCj)rC}rC(jX 0x4A0028BCrCjjCjj3jjj}rC(j]j]j]j]j]ujKj]rCjX 0x4A0028BCrCrC}rC(jjCjjCubaubajj ubj )rC}rC(jUj}rC(j]j]j]j]j]ujjCj]rCj)rC}rC(jX53rCjjCjj3jjj}rC(j]j]j]j]j]ujKj]rCjX53rCrC}rC(jjCjjCubaubajj ubj )rC}rC(jUj}rC(j]j]j]j]j]ujjCj]rCj)rC}rC(jXEVE4_IRQ_MBX1_USER3rCjjCjj3jjj}rC(j]j]j]j]j]ujKj]rCjXEVE4_IRQ_MBX1_USER3rCrC}rC(jjCjjCubaubajj ubj )rC}rC(jUj}rC(j]j]j]j]j]ujjCj]rCj)rC}rC(jX EVE4_MAILBOX1rCjjCjj3jjj}rC(j]j]j]j]j]ujKj]rCjX EVE4_MAILBOX1rCrC}rC(jjCjjCubaubajj ubj )rC}rC(jUj}rC(j]j]j]j]j]ujjCj]rCj)rC}rD(jXEve4 Mailbox 1 user 3 interruptrDjjCjj3jjj}rD(j]j]j]j]j]ujKj]rDjXEve4 Mailbox 1 user 3 interruptrDrD}rD(jjDjjCubaubajj ubejj ubj )rD}rD(jUj}r D(j]j]j]j]j]ujjs@j]r D(j )r D}r D(jUj}r D(j]j]j]j]j]ujjDj]rDj)rD}rD(jX76rDjj Djj3jjj}rD(j]j]j]j]j]ujKj]rDjX76rDrD}rD(jjDjjDubaubajj ubj )rD}rD(jUj}rD(j]j]j]j]j]ujjDj]rDj)rD}rD(jX 0x4A0028BCrDjjDjj3jjj}rD(j]j]j]j]j]ujKj]rDjX 0x4A0028BCr Dr!D}r"D(jjDjjDubaubajj ubj )r#D}r$D(jUj}r%D(j]j]j]j]j]ujjDj]r&Dj)r'D}r(D(jX54r)Djj#Djj3jjj}r*D(j]j]j]j]j]ujKj]r+DjX54r,Dr-D}r.D(jj)Djj'Dubaubajj ubj )r/D}r0D(jUj}r1D(j]j]j]j]j]ujjDj]r2Dj)r3D}r4D(jXMAILBOX8_IRQ_USER3r5Djj/Djj3jjj}r6D(j]j]j]j]j]ujKj]r7DjXMAILBOX8_IRQ_USER3r8Dr9D}r:D(jj5Djj3Dubaubajj ubj )r;D}rDj)r?D}r@D(jXMAILBOX8rADjj;Djj3jjj}rBD(j]j]j]j]j]ujKj]rCDjXMAILBOX8rDDrED}rFD(jjADjj?Dubaubajj ubj )rGD}rHD(jUj}rID(j]j]j]j]j]ujjDj]rJDj)rKD}rLD(jXMailbox 8 user 3 interruptrMDjjGDjj3jjj}rND(j]j]j]j]j]ujKj]rODjXMailbox 8 user 3 interruptrPDrQD}rRD(jjMDjjKDubaubajj ubejj ubejj ubejj ubaubeubeubeubeubj)rSD}rTD(jUjKjjjjjjj}rUD(j]j]j]j]rVDjaj]rWDh aujKjhj]rXD(j)rYD}rZD(jXIPC 3.x vs IPC LLDr[DjjSDjjjjj}r\D(j]j]j]j]j]ujKjhj]r]DjXIPC 3.x vs IPC LLDr^Dr_D}r`D(jj[DjjYDubaubj)raD}rbD(jXLIPC 3.x APIs provide High level IPC APIs that scale across all TI platforms.rcDjjSDjjjjj}rdD(j]j]j]j]j]ujKjhj]reDjXLIPC 3.x APIs provide High level IPC APIs that scale across all TI platforms.rfDrgD}rhD(jjcDjjaDubaubj)riD}rjD(jXmInstead of the IPC 3.x APIs, in certain cases customers can choose to use the IPC Low level Driver (IPC LLD).rkDjjSDjjjjj}rlD(j]j]j]j]j]ujKjhj]rmDjXmInstead of the IPC 3.x APIs, in certain cases customers can choose to use the IPC Low level Driver (IPC LLD).rnDroD}rpD(jjkDjjiDubaubj)rqD}rrD(jXfIn general, the IPC LLD can be used, if the customer application falls under the following categories.rsDjjSDjjjjj}rtD(j]j]j]j]j]ujKjhj]ruDjXfIn general, the IPC LLD can be used, if the customer application falls under the following categories.rvDrwD}rxD(jjsDjjqDubaubj )ryD}rzD(jUjjSDjjjj j}r{D(jU)j]j]j]jUj]j]jU loweralphar|DujKjhj]r}D(j{)r~D}rD(jX_Non-RTOS bare metal applications (Note: IPC 3.x is closely coupled with SYSBIOS and XDC tools)rDjjyDjjjjj}rD(j]j]j]j]j]ujNjhj]rDj)rD}rD(jjDjj~Djjjjj}rD(j]j]j]j]j]ujKj]rDjX_Non-RTOS bare metal applications (Note: IPC 3.x is closely coupled with SYSBIOS and XDC tools)rDrD}rD(jjDjjDubaubaubj{)rD}rD(jXApplications does not need the high level API abstraction and all the features (like GateMP etc) and would like to call the low level driver to just establish basic communication between the cores.rDjjyDjjjjj}rD(j]j]j]j]j]ujNjhj]rDj)rD}rD(jjDjjDjjjjj}rD(j]j]j]j]j]ujKj]rDjXApplications does not need the high level API abstraction and all the features (like GateMP etc) and would like to call the low level driver to just establish basic communication between the cores.rDrD}rD(jjDjjDubaubaubj{)rD}rD(jXApplication needs the same RPMSG/Virtio transport mechanism to communicate with a core running linux and other cores running other operating systems. jjyDjjjjj}rD(j]j]j]j]j]ujNjhj]rDj)rD}rD(jXApplication needs the same RPMSG/Virtio transport mechanism to communicate with a core running linux and other cores running other operating systems.rDjjDjjjjj}rD(j]j]j]j]j]ujKj]rDjXApplication needs the same RPMSG/Virtio transport mechanism to communicate with a core running linux and other cores running other operating systems.rDrD}rD(jjDjjDubaubaubeubj)rD}rD(jXxPlease refer to the following page for details on the IPC LLD: `IPC LLD for AM65x/J721E `_rDjjSDjjjjj}rD(j]j]j]j]j]ujKjhj]rD(jX?Please refer to the following page for details on the IPC LLD: rDrD}rD(jX?Please refer to the following page for details on the IPC LLD: jjDubj)rD}rD(jX9`IPC LLD for AM65x/J721E `_j}rD(UnameXIPC LLD for AM65x/J721EjXindex_device_drv.html#ipclldrDj]j]j]j]j]ujjDj]rDjXIPC LLD for AM65x/J721ErDrD}rD(jUjjDubajjubj)rD}rD(jX jKjjDjj j}rD(UrefurijDj]rDUid40rDaj]j]rDXipc lld for am65x/j721erDaj]j]uj]ubeubeubj)rD}rD(jUjjjjjjj}rD(j]j]j]j]rDUipc-faqrDaj]rDjaujKjhj]rD(j)rD}rD(jXIPC FAQrDjjDjjjjj}rD(j]j]j]j]j]ujKjhj]rDjXIPC FAQrDrD}rD(jjDjjDubaubj7)rD}rD(jX3http://processors.wiki.ti.com/index.php/IPC_3.x_FAQjjDjj:X9source/rtos/PDK_Platform_Software/IPC/IPC_3.x_FAQ.rst.incrDrD}rDbjj>j}rD(j@jAj]j]j]j]j]ujKjhj]rDjX3http://processors.wiki.ti.com/index.php/IPC_3.x_FAQrDrD}rD(jUjjDubaubj)rD}rD(jUjjDjjDjjj}rD(j]j]j]j]rDU3i-have-a-question-that-s-not-answered-here-what-nowrDaj]rDjyaujKjhj]rD(j)rD}rD(jX5I have a question that's not answered here, what now?rDjjDjjDjjj}rD(j]j]j]j]j]ujKjhj]rDjX5I have a question that's not answered here, what now?rDrD}rD(jjDjjDubaubjt)rD}rD(jUjjDjjDjjwj}rD(jyX-j]j]j]j]j]ujKjhj]rD(j{)rD}rD(jXnThere are lots of knowledgeable experts on the `TI E2E Support Forums `__ - posts welcome!jjDjjDjjj}rD(j]j]j]j]j]ujNjhj]rDj)rD}rD(jXnThere are lots of knowledgeable experts on the `TI E2E Support Forums `__ - posts welcome!jjDjjDjjj}rD(j]j]j]j]j]ujKj]rD(jX/There are lots of knowledgeable experts on the rDrD}rD(jX/There are lots of knowledgeable experts on the jjDubj)rD}rD(jX.`TI E2E Support Forums `__j}rD(UnameXTI E2E Support ForumsjXhttp://e2e.ti.com/j]j]j]j]j]ujjDj]rDjXTI E2E Support ForumsrDrD}rD(jUjjDubajjubjX - posts welcome!rDrD}rD(jX - posts welcome!jjDubeubaubj{)rD}rD(jXwHave you tried `Google `__? IPC's been around a while, and Google has lots of details about it. jjDjjDjjj}rD(j]j]j]j]j]ujNjhj]rDj)rD}rD(jXvHave you tried `Google `__? IPC's been around a while, and Google has lots of details about it.jjDjjDjjj}rE(j]j]j]j]j]ujK j]rE(jXHave you tried rErE}rE(jXHave you tried jjDubj)rE}rE(jX"`Google `__j}rE(UnameXGooglejXhttp://www.google.comj]j]j]j]j]ujjDj]rEjXGoogler Er E}r E(jUjjEubajjubjXE? IPC's been around a while, and Google has lots of details about it.r Er E}rE(jXE? IPC's been around a while, and Google has lots of details about it.jjDubeubaubeubeubj)rE}rE(jUjjDjjDjjj}rE(j]j]j]j]rEUdoes-ipc-3-x-support-smp-biosrEaj]rEhaujK jhj]rE(j)rE}rE(jXDoes IPC 3.x support SMP BIOS?rEjjEjjDjjj}rE(j]j]j]j]j]ujK jhj]rEjXDoes IPC 3.x support SMP BIOS?rErE}rE(jjEjjEubaubj)rE}rE(jX`SMP BIOS is described here `__. It is currently only available for dual-core ARM M-class devices, sometimes called "Benelli" or "Ducati".jjEjjDjjj}r E(j]j]j]j]j]ujKjhj]r!E(j)r"E}r#E(jXQ`SMP BIOS is described here `__j}r$E(UnameXSMP BIOS is described herejX0http://processors.wiki.ti.com/index.php/SMP/BIOSj]j]j]j]j]ujjEj]r%EjXSMP BIOS is described herer&Er'E}r(E(jUjj"EubajjubjXk. It is currently only available for dual-core ARM M-class devices, sometimes called "Benelli" or "Ducati".r)Er*E}r+E(jXk. It is currently only available for dual-core ARM M-class devices, sometimes called "Benelli" or "Ducati".jjEubeubj)r,E}r-E(jXdSpecifically where IPC 3.x is concerned, SMP BIOS is only applicable to the following cores/devices:r.EjjEjjDjjj}r/E(j]j]j]j]j]ujKjhj]r0EjXdSpecifically where IPC 3.x is concerned, SMP BIOS is only applicable to the following cores/devices:r1Er2E}r3E(jj.Ejj,Eubaubjt)r4E}r5E(jUjjEjjDjjwj}r6E(jyX-j]j]j]j]j]ujKjhj]r7E(j{)r8E}r9E(jXIPU on OMAP54XXr:Ejj4EjjDjjj}r;E(j]j]j]j]j]ujNjhj]rE(jj:Ejj8EjjDjjj}r?E(j]j]j]j]j]ujKj]r@EjXIPU on OMAP54XXrAErBE}rCE(jj:Ejj=Eubaubaubj{)rDE}rEE(jX2IPU1 (and IPU2, if present) on DRA7XX (e.g. Vayu) jj4EjjDjjj}rFE(j]j]j]j]j]ujNjhj]rGEj)rHE}rIE(jX1IPU1 (and IPU2, if present) on DRA7XX (e.g. Vayu)rJEjjDEjjDjjj}rKE(j]j]j]j]j]ujKj]rLEjX1IPU1 (and IPU2, if present) on DRA7XX (e.g. Vayu)rMErNE}rOE(jjJEjjHEubaubaubeubj)rPE}rQE(jXeThe answer to this question depends on whether you are developing an HLOS-based or BIOS-based system.rREjjEjjDjjj}rSE(j]j]j]j]j]ujKjhj]rTEjXeThe answer to this question depends on whether you are developing an HLOS-based or BIOS-based system.rUErVE}rWE(jjREjjPEubaubjy )rXE}rYE(jUjjEjjDjj j}rZE(j]j]j]j]j]ujNjhj]r[Ej~ )r\E}r]E(jUj}r^E(j]j]j]j]j]UcolsKujjXEj]r_E(j )r`E}raE(jUj}rbE(j]j]j]j]j]UcolwidthK#ujj\Ej]jj ubj )rcE}rdE(jUj}reE(j]j]j]j]j]UcolwidthK#ujj\Ej]jj ubj )rfE}rgE(jUj}rhE(j]j]j]j]j]ujj\Ej]riEj )rjE}rkE(jUj}rlE(j]j]j]j]j]ujjfEj]rmE(j )rnE}roE(jUj}rpE(j]j]j]j]j]ujjjEj]rqEj)rrE}rsE(jX5HLOS-Based (e.g. Linux, QNX, Android on the Cortex-A)rtEjjnEjjDjjj}ruE(j]j]j]j]j]ujKj]rvEjX5HLOS-Based (e.g. Linux, QNX, Android on the Cortex-A)rwErxE}ryE(jjtEjjrEubaubajj ubj )rzE}r{E(jUj}r|E(j]j]j]j]j]ujjjEj]r}Ej)r~E}rE(jX&BIOS-Based (i.e. BIOS on the Cortex-A)rEjjzEjjDjjj}rE(j]j]j]j]j]ujKj]rEjX&BIOS-Based (i.e. BIOS on the Cortex-A)rErE}rE(jjEjj~Eubaubajj ubejj ubajj ubj )rE}rE(jUj}rE(j]j]j]j]j]ujj\Ej]rEj )rE}rE(jUj}rE(j]j]j]j]j]ujjEj]rE(j )rE}rE(jUj}rE(j]j]j]j]j]ujjEj]rE(j)rE}rE(jXIPC 3.x **only** supports SMP BIOS on the IPU(s). In an HLOS-based system, the IPU(s) are loaded and managed as slaves (not peers).jjEjjDjjj}rE(j]j]j]j]j]ujK!j]rE(jXIPC 3.x rErE}rE(jXIPC 3.x jjEubj)rE}rE(jX**only**j}rE(j]j]j]j]j]ujjEj]rEjXonlyrErE}rE(jUjjEubajjubjXs supports SMP BIOS on the IPU(s). In an HLOS-based system, the IPU(s) are loaded and managed as slaves (not peers).rErE}rE(jXs supports SMP BIOS on the IPU(s). In an HLOS-based system, the IPU(s) are loaded and managed as slaves (not peers).jjEubeubj)rE}rE(jX2When managing the IPU as a slave, issues like power management, loading/resetting, and error recovery are key features. Because the 2 cores in a single IPU can't easily be seen as truly independent (e.g. they share a power domain), treating them as one slave (running SMP BIOS) is simpler and more natural.rEjjEjjDjjj}rE(j]j]j]j]j]ujK'j]rEjX2When managing the IPU as a slave, issues like power management, loading/resetting, and error recovery are key features. Because the 2 cores in a single IPU can't easily be seen as truly independent (e.g. they share a power domain), treating them as one slave (running SMP BIOS) is simpler and more natural.rErE}rE(jjEjjEubaubejj ubj )rE}rE(jUj}rE(j]j]j]j]j]ujjEj]rE(j)rE}rE(jXIPC 3.x supports either SMP BIOS or non-SMP BIOS. Note that specifically on DRA7XX's **IPU2**, IPC 3.x only supports SMP BIOS (to reduce the number of core-to-core permutations and thus reduce the number of mailboxes required). In a BIOS-based environment, the IPU(s) are treated as peers (not slaves), and as such some of the concerns about power management, loading, error recovery are no longer an issue.jjEjjDjjj}rE(j]j]j]j]j]ujK!j]rE(jXUIPC 3.x supports either SMP BIOS or non-SMP BIOS. Note that specifically on DRA7XX's rErE}rE(jXUIPC 3.x supports either SMP BIOS or non-SMP BIOS. Note that specifically on DRA7XX's jjEubj)rE}rE(jX**IPU2**j}rE(j]j]j]j]j]ujjEj]rEjXIPU2rErE}rE(jUjjEubajjubjX:, IPC 3.x only supports SMP BIOS (to reduce the number of core-to-core permutations and thus reduce the number of mailboxes required). In a BIOS-based environment, the IPU(s) are treated as peers (not slaves), and as such some of the concerns about power management, loading, error recovery are no longer an issue.rErE}rE(jX:, IPC 3.x only supports SMP BIOS (to reduce the number of core-to-core permutations and thus reduce the number of mailboxes required). In a BIOS-based environment, the IPU(s) are treated as peers (not slaves), and as such some of the concerns about power management, loading, error recovery are no longer an issue.jjEubeubj)rE}rE(jXjNote that the MultiProc configuration used on all cores reflects your SMP-or-not-SMP decision. When using non-SMP BIOS, you must include "IPU1-0" and "IPU1-1" (rather than "IPU1" used when running SMP BIOS) in your MultiProc configuration. See the ex11_ping example provided with the IPC product for an example that supports either "IPU1" or "IPU1-0 and IPU1-1".rEjjEjjDjjj}rE(j]j]j]j]j]ujK0j]rEjXjNote that the MultiProc configuration used on all cores reflects your SMP-or-not-SMP decision. When using non-SMP BIOS, you must include "IPU1-0" and "IPU1-1" (rather than "IPU1" used when running SMP BIOS) in your MultiProc configuration. See the ex11_ping example provided with the IPC product for an example that supports either "IPU1" or "IPU1-0 and IPU1-1".rErE}rE(jjEjjEubaubejj ubejj ubajj ubejj ubaubj)rE}rE(jXFinally, there are a few notable benefits to using SMP BIOS. Many are described in the `SMP/BIOS `__ article, but two are highlighted here:jjEjjDjjj}rE(j]j]j]j]j]ujK>jhj]rE(jXWFinally, there are a few notable benefits to using SMP BIOS. Many are described in the rErE}rE(jXWFinally, there are a few notable benefits to using SMP BIOS. Many are described in the jjEubj)rE}rE(jX?`SMP/BIOS `__j}rE(UnameXSMP/BIOSjX0http://processors.wiki.ti.com/index.php/SMP/BIOSj]j]j]j]j]ujjEj]rEjXSMP/BIOSrErE}rE(jUjjEubajjubjX' article, but two are highlighted here:rErE}rE(jX' article, but two are highlighted here:jjEubeubjt)rE}rE(jUjjEjjDjjwj}rE(jyX-j]j]j]j]j]ujKBjhj]rE(j{)rE}rE(jXF**Free load balancing** - SMP BIOS schedules tasks to run on the less-loaded core to balance IPU usage. Without SMP BIOS, when one of the cores became heavily loaded, users had to repartition the resources; often this meant moving tasks/code from one core to the other, which can affect memory maps, build/config scripts, etc.jjEjjDjjj}rE(j]j]j]j]j]ujNjhj]rEj)rE}rE(jXF**Free load balancing** - SMP BIOS schedules tasks to run on the less-loaded core to balance IPU usage. Without SMP BIOS, when one of the cores became heavily loaded, users had to repartition the resources; often this meant moving tasks/code from one core to the other, which can affect memory maps, build/config scripts, etc.jjEjjDjjj}rE(j]j]j]j]j]ujKBj]rE(j)rE}rE(jX**Free load balancing**j}rE(j]j]j]j]j]ujjEj]rEjXFree load balancingrErE}rE(jUjjEubajjubjX/ - SMP BIOS schedules tasks to run on the less-loaded core to balance IPU usage. Without SMP BIOS, when one of the cores became heavily loaded, users had to repartition the resources; often this meant moving tasks/code from one core to the other, which can affect memory maps, build/config scripts, etc.rErE}rE(jX/ - SMP BIOS schedules tasks to run on the less-loaded core to balance IPU usage. Without SMP BIOS, when one of the cores became heavily loaded, users had to repartition the resources; often this meant moving tasks/code from one core to the other, which can affect memory maps, build/config scripts, etc.jjEubeubaubj{)rE}rE(jX**Simpler system integration** - there's one fewer core to manage the memory map and resource allocation for. Without SMP BIOS, the single unicache needed to understand AMMU and cache needs for both cores, and often confusing and error-prone integration issue. jjEjjDjjj}rE(j]j]j]j]j]ujNjhj]rEj)rE}rE(jX**Simpler system integration** - there's one fewer core to manage the memory map and resource allocation for. Without SMP BIOS, the single unicache needed to understand AMMU and cache needs for both cores, and often confusing and error-prone integration issue.jjEjjDjjj}rE(j]j]j]j]j]ujKGj]rE(j)rE}rE(jX**Simpler system integration**j}rE(j]j]j]j]j]ujjEj]rEjXSimpler system integrationrErE}rE(jUjjEubajjubjX - there's one fewer core to manage the memory map and resource allocation for. Without SMP BIOS, the single unicache needed to understand AMMU and cache needs for both cores, and often confusing and error-prone integration issue.rErE}rF(jX - there's one fewer core to manage the memory map and resource allocation for. Without SMP BIOS, the single unicache needed to understand AMMU and cache needs for both cores, and often confusing and error-prone integration issue.jjEubeubaubeubeubj)rF}rF(jUjjDjjDjjj}rF(j]j]j]j]rFUbuild-questionsrFaj]rFhaujKMjhj]rF(j)rF}r F(jXBuild Questionsr FjjFjjDjjj}r F(j]j]j]j]j]ujKMjhj]r FjXBuild Questionsr FrF}rF(jj FjjFubaubj)rF}rF(jUjjFjjDjjj}rF(j]j]j]j]rFUbios-side-buildrFaj]rFhaujKPjhj]rF(j)rF}rF(jXBIOS-side BuildrFjjFjjDjjj}rF(j]j]j]j]j]ujKPjhj]rFjXBIOS-side BuildrFrF}rF(jjFjjFubaubj)rF}r F(jUjKjjFjjDjjj}r!F(j]r"FXhow do i change the memory map?r#Faj]j]j]r$FUhow-do-i-change-the-memory-mapr%Faj]ujKSjhj]r&F(j)r'F}r(F(jXHow do I change the Memory Map?r)FjjFjjDjjj}r*F(j]j]j]j]j]ujKSjhj]r+FjXHow do I change the Memory Map?r,Fr-F}r.F(jj)Fjj'Fubaubj)r/F}r0F(jXStandard techniques for changing the memory map of any BIOS executable generally apply (e.g. `creating your own custom platform `__, `creating an instance of an existing platform `__, etc). However when building an executable which is loaded by an HLOS, you also need to ensure the resource table is aligned with the memory map. The `IPC Resource customTable `__ article describes how to override the default resource table, which among other things, includes the memory map.jjFjjDjjj}r1F(j]j]j]j]j]ujKUjhj]r2F(jX]Standard techniques for changing the memory map of any BIOS executable generally apply (e.g. r3Fr4F}r5F(jX]Standard techniques for changing the memory map of any BIOS executable generally apply (e.g. jj/Fubj)r6F}r7F(jXr`creating your own custom platform `__j}r8F(UnameX!creating your own custom platformjXJhttp://rtsc.eclipse.org/docs-tip/Demo_of_the_RTSC_Platform_Wizard_in_CCSv4j]j]j]j]j]ujj/Fj]r9FjX!creating your own custom platformr:Fr;F}rF}r?F(jX, jj/Fubj)r@F}rAF(jXo`creating an instance of an existing platform `__j}rBF(UnameX,creating an instance of an existing platformjX<http://rtsc.eclipse.org/docs-tip/Using_Targets_and_Platformsj]j]j]j]j]ujj/Fj]rCFjX,creating an instance of an existing platformrDFrEF}rFF(jUjj@FubajjubjX, etc). However when building an executable which is loaded by an HLOS, you also need to ensure the resource table is aligned with the memory map. The rGFrHF}rIF(jX, etc). However when building an executable which is loaded by an HLOS, you also need to ensure the resource table is aligned with the memory map. The jj/Fubj)rJF}rKF(jXW`IPC Resource customTable `__j}rLF(UnameXIPC Resource customTablejX8index_Foundational_Components.html#resource-custom-tablej]j]j]j]j]ujj/Fj]rMFjXIPC Resource customTablerNFrOF}rPF(jUjjJFubajjubjXq article describes how to override the default resource table, which among other things, includes the memory map.rQFrRF}rSF(jXq article describes how to override the default resource table, which among other things, includes the memory map.jj/Fubeubj)rTF}rUF(jXjObviously be sure to also ensure changes to the memory map don't collide with memory usage on other cores.rVFjjFjjDjjj}rWF(j]j]j]j]j]ujKajhj]rXFjXjObviously be sure to also ensure changes to the memory map don't collide with memory usage on other cores.rYFrZF}r[F(jjVFjjTFubaubeubj)r\F}r]F(jUjjFjjDjjj}r^F(j]j]j]j]r_FUZwhy-are-the-peripherals-mapped-to-0x6xxx-xxxx-virtual-memory-for-ipu-cortex-m4-test-imagesr`Faj]raFh-aujKejhj]rbF(j)rcF}rdF(jX]Why are the peripherals mapped to 0x6XXX:XXXX virtual memory for IPU (Cortex-M4) test images?reFjj\FjjDjjj}rfF(j]j]j]j]j]ujKejhj]rgFjX]Why are the peripherals mapped to 0x6XXX:XXXX virtual memory for IPU (Cortex-M4) test images?rhFriF}rjF(jjeFjjcFubaubj)rkF}rlF(jXThe ARM Cortex-M4 memory map includes a bit-banding region of memory from 0x4000:0000 to 0x400F:FFFF and 0x4200:0000 to 0x43FF:FFFF. Here is a Cortex-M4 memory map picture from ARM:rmFjj\FjjDjjj}rnF(j]j]j]j]j]ujKgjhj]roFjXThe ARM Cortex-M4 memory map includes a bit-banding region of memory from 0x4000:0000 to 0x400F:FFFF and 0x4200:0000 to 0x43FF:FFFF. Here is a Cortex-M4 memory map picture from ARM:rpFrqF}rrF(jjmFjjkFubaubj)rsF}rtF(jXRhttp://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/CHDBIJJE.htmljj\FjjDjjj}ruF(j@jAj]j]j]j]j]ujMjhj]rvFjXRhttp://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/CHDBIJJE.htmlrwFrxF}ryF(jUjjsFubaubj)rzF}r{F(jXMany Vayu components running on the IPUs, including IPC, must access peripherals physically located in this bit-banding region. As a result, these accesses must be performed indirectly using a virtual memory address, mapped using the IPU's AMMU.r|Fjj\FjjDjjj}r}F(j]j]j]j]j]ujKojhj]r~FjXMany Vayu components running on the IPUs, including IPC, must access peripherals physically located in this bit-banding region. As a result, these accesses must be performed indirectly using a virtual memory address, mapped using the IPU's AMMU.rFrF}rF(jj|FjjzFubaubj)rF}rF(jXMany of the components aligned on mapping this memory using one Large AMMU page that maps 512M of physical memory beginning at 0x4000:0000 to virtual memory beginning at 0x6000:0000. Then the components (by default) access the peripherals using the 0x6XXX:XXXX address space.rFjj\FjjDjjj}rF(j]j]j]j]j]ujKtjhj]rFjXMany of the components aligned on mapping this memory using one Large AMMU page that maps 512M of physical memory beginning at 0x4000:0000 to virtual memory beginning at 0x6000:0000. Then the components (by default) access the peripherals using the 0x6XXX:XXXX address space.rFrF}rF(jjFjjFubaubjt)rF}rF(jUjj\FjjDjjwj}rF(jyX-j]j]j]j]j]ujKyjhj]rFj{)rF}rF(jXIPC specifics: jjFjjDjjj}rF(j]j]j]j]j]ujNjhj]rFj)rF}rF(jXIPC specifics:rFjjFjjDjjj}rF(j]j]j]j]j]ujKyj]rFjXIPC specifics:rFrF}rF(jjFjjFubaubaubaubj)rF}rF(jXIPC follows the convention of, by default, accessing memory physically located at 0x4XXX:XXXX using virtual memory at 0x6XXX:XXXX. You can see an example of this here - note the mailbox addresses configured here are in the 06XXX:XXXX range:rFjj\FjjDjjj}rF(j]j]j]j]j]ujK{jhj]rFjXIPC follows the convention of, by default, accessing memory physically located at 0x4XXX:XXXX using virtual memory at 0x6XXX:XXXX. You can see an example of this here - note the mailbox addresses configured here are in the 06XXX:XXXX range:rFrF}rF(jjFjjFubaubj)rF}rF(jXchttp://git.ti.com/cgit/cgit.cgi/ipc/ipcdev.git/tree/packages/ti/sdo/ipc/family/vayu/InterruptIpu.xsjj\FjjDjjj}rF(j@jAj]j]j]j]j]ujMjhj]rFjXchttp://git.ti.com/cgit/cgit.cgi/ipc/ipcdev.git/tree/packages/ti/sdo/ipc/family/vayu/InterruptIpu.xsrFrF}rF(jUjjFubaubj)rF}rF(jXrIn that same file, you can see that these addresses are configurable, and the default 0x6XXX:XXXX addresses are only used if other addresses haven't already been configured by the system integrator (e.g. in a .cfg script). Users can override these default mailbox addresses using the ti.sdo.ipc.family.vayu.InterruptIpu module's mailboxBaseAddr[] array, documented here:rFjj\FjjDjjj}rF(j]j]j]j]j]ujKjhj]rFjXrIn that same file, you can see that these addresses are configurable, and the default 0x6XXX:XXXX addresses are only used if other addresses haven't already been configured by the system integrator (e.g. in a .cfg script). Users can override these default mailbox addresses using the ti.sdo.ipc.family.vayu.InterruptIpu module's mailboxBaseAddr[] array, documented here:rFrF}rF(jjFjjFubaubj)rF}rF(jXhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/ti/sdo/ipc/family/vayu/InterruptIpu.html#metamailbox.Base.AddrrFjj\FjjDjjj}rF(j]j]j]j]j]ujKjhj]rFj)rF}rF(jjFj}rF(UrefurijFj]j]j]j]j]ujjFj]rFjXhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/ti/sdo/ipc/family/vayu/InterruptIpu.html#metamailbox.Base.AddrrFrF}rF(jUjjFubajjubaubeubeubj)rF}rF(jUjjFjjDjjj}rF(j]j]j]j]rFU linux-buildrFaj]rFhaujKjhj]rF(j)rF}rF(jX Linux BuildrFjjFjjDjjj}rF(j]j]j]j]j]ujKjhj]rFjX Linux BuildrFrF}rF(jjFjjFubaubj)rF}rF(jXFor details on the Linux build process see the `IPC Install Guide for Linux `__.jjFjjDjjj}rF(j]j]j]j]j]ujKjhj]rF(jX/For details on the Linux build process see the rFrF}rF(jX/For details on the Linux build process see the jjFubj)rF}rF(jXX`IPC Install Guide for Linux `__j}rF(UnameXIPC Install Guide for LinuxjX6index_Foundational_Components.html#linux-install-guidej]j]j]j]j]ujjFj]rFjXIPC Install Guide for LinuxrFrF}rF(jUjjFubajjubjX.rF}rF(jX.jjFubeubj)rF}rF(jUjjFjjDjjj}rF(j]j]j]j]rFUtry-cleaning-firstrFaj]rFj/aujKjhj]rF(j)rF}rF(jXTry Cleaning FirstrFjjFjjDjjj}rF(j]j]j]j]j]ujKjhj]rFjXTry Cleaning FirstrFrF}rF(jjFjjFubaubj)rF}rF(jXSometimes the generated autotools makefiles can get confused, especially if your often switching from one platform to another, between static and dynamic libraries, etc. And sometimes simply cleaning and retrying can help.rFjjFjjDjjj}rF(j]j]j]j]j]ujKjhj]rFjXSometimes the generated autotools makefiles can get confused, especially if your often switching from one platform to another, between static and dynamic libraries, etc. And sometimes simply cleaning and retrying can help.rFrF}rF(jjFjjFubaubj)rF}rF(jXp"make clean" does a 'light' cleaning, leaving the autotools-generated config files so you can just retry 'make':rFjjFjjDjjj}rF(j]j]j]j]j]ujKjhj]rFjXp"make clean" does a 'light' cleaning, leaving the autotools-generated config files so you can just retry 'make':rFrF}rF(jjFjjFubaubj)rF}rF(jX# make clean # # makejjFjjDjjj}rF(j@jAj]j]j]j]j]ujMjhj]rFjX# make clean # # makerFrG}rG(jUjjFubaubj)rG}rG(jXh"make distclean" does a more aggressive clean, requiring you to re-run the config before running 'make':rGjjFjjDjjj}rG(j]j]j]j]j]ujKjhj]rGjXh"make distclean" does a more aggressive clean, requiring you to re-run the config before running 'make':rGrG}r G(jjGjjGubaubj)r G}r G(jX1# make distclean # # make -f ipc-linux.mak # makejjFjjDjjj}r G(j@jAj]j]j]j]j]ujMjhj]r GjX1# make distclean # # make -f ipc-linux.mak # makerGrG}rG(jUjj Gubaubeubeubj)rG}rG(jUjjFjjDjjj}rG(j]j]j]j]rGU qnx-buildrGaj]rGj`aujKjhj]rG(j)rG}rG(jX QNX BuildrGjjGjjDjjj}rG(j]j]j]j]j]ujKjhj]rGjX QNX BuildrGrG}rG(jjGjjGubaubj)r G}r!G(jXFor details on the QNX build process see the `IPC Install Guide for QNX `__.jjGjjDjjj}r"G(j]j]j]j]j]ujKjhj]r#G(jX-For details on the QNX build process see the r$Gr%G}r&G(jX-For details on the QNX build process see the jj Gubj)r'G}r(G(jXT`IPC Install Guide for QNX `__j}r)G(UnameXIPC Install Guide for QNXjX4index_Foundational_Components.html#qnx-install-guidej]j]j]j]j]ujj Gj]r*GjXIPC Install Guide for QNXr+Gr,G}r-G(jUjj'GubajjubjX.r.G}r/G(jX.jj Gubeubj)r0G}r1G(jUjKjjGjjDjjj}r2G(j]r3Gj#Faj]j]j]r4GUid41r5Gaj]ujKjhj]r6G(j)r7G}r8G(jXHow do I change the Memory Map?r9Gjj0GjjDjjj}r:G(j]j]j]j]j]ujKjhj]r;GjXHow do I change the Memory Map?rG(jj9Gjj7Gubaubj)r?G}r@G(jXCFor the standpoint of the QNX OS, it owns all external memory by default. When the 'ipc' resource manager is launched and the slave cores are loaded, the resource table in each slave executable is read and interpreted. All resource entries of type CARVEOUT are automatically allocated from QNX-owned memory. Similarly, the first DEVMEM entry always corresponds to the vring memory used by MessageQ and rpmsg_rpc, and is also automatically allocated from QNX-owned memory, regardless of which physical memory address is specified in the resource table entry. If any other DEVMEM resource entry resides in external memory, QNX would need to be told to not use that particular range. This is usually done using the '-r' flag in the startup command in the 'build' file of the QNX IFS (refer to your QNX BSP documentation for more details):rAGjj0GjjDjjj}rBG(j]j]j]j]j]ujKjhj]rCGjXCFor the standpoint of the QNX OS, it owns all external memory by default. When the 'ipc' resource manager is launched and the slave cores are loaded, the resource table in each slave executable is read and interpreted. All resource entries of type CARVEOUT are automatically allocated from QNX-owned memory. Similarly, the first DEVMEM entry always corresponds to the vring memory used by MessageQ and rpmsg_rpc, and is also automatically allocated from QNX-owned memory, regardless of which physical memory address is specified in the resource table entry. If any other DEVMEM resource entry resides in external memory, QNX would need to be told to not use that particular range. This is usually done using the '-r' flag in the startup command in the 'build' file of the QNX IFS (refer to your QNX BSP documentation for more details):rDGrEG}rFG(jjAGjj?Gubaubj)rGG}rHG(jXAstartup-dra74x-vayu-evm -r0xBA300000,0x5A00000 -v -n852,668 -W -Gjj0GjjDjjj}rIG(j@jAj]j]j]j]j]ujMjhj]rJGjXAstartup-dra74x-vayu-evm -r0xBA300000,0x5A00000 -v -n852,668 -W -GrKGrLG}rMG(jUjjGGubaubj)rNG}rOG(jX{For example, the above '-r' flag would reserve 0x5A00000 bytes starting at physical address 0xBA300000 from being used by the QNX OS on the DRA74x. This technique is often used for the memory range used by shmemallocator (resource table entry PHYS_MEM_IOBUFS) and/or by SharedRegions. After modifying the startup flags, rebuild the QNX IFS and use the new one to boot your board.rPGjj0GjjDjjj}rQG(j]j]j]j]j]ujKjhj]rRGjX{For example, the above '-r' flag would reserve 0x5A00000 bytes starting at physical address 0xBA300000 from being used by the QNX OS on the DRA74x. This technique is often used for the memory range used by shmemallocator (resource table entry PHYS_MEM_IOBUFS) and/or by SharedRegions. After modifying the startup flags, rebuild the QNX IFS and use the new one to boot your board.rSGrTG}rUG(jjPGjjNGubaubeubj)rVG}rWG(jUjjGjjDjjj}rXG(j]j]j]j]rYGU4how-do-i-configure-the-memory-used-by-shmemallocatorrZGaj]r[GhaujKjhj]r\G(j)r]G}r^G(jX5How do I configure the memory used by shmemallocator?r_GjjVGjjDjjj}r`G(j]j]j]j]j]ujKjhj]raGjX5How do I configure the memory used by shmemallocator?rbGrcG}rdG(jj_Gjj]Gubaubj)reG}rfG(jXshmemallocator stands for "Shared Memory Allocator". It is a utility that is built alongside the core IPC driver whenever the IPC product is built. The user can optionally use this utility to allocate contiguous shared memory for exchanging data between the host and the slave cores. The memory it allocates from is defined in \qnx\src\ipc3x_dev\sharedmemallocator\resmgr\SharedMemoryAllocator.c thru some #define statements:jjVGjjDjjj}rgG(j]j]j]j]j]ujKjhj]rhGjXshmemallocator stands for "Shared Memory Allocator". It is a utility that is built alongside the core IPC driver whenever the IPC product is built. The user can optionally use this utility to allocate contiguous shared memory for exchanging data between the host and the slave cores. The memory it allocates from is defined in qnxsrcipc3x_devsharedmemallocatorresmgrSharedMemoryAllocator.c thru some #define statements:riGrjG}rkG(jXshmemallocator stands for "Shared Memory Allocator". It is a utility that is built alongside the core IPC driver whenever the IPC product is built. The user can optionally use this utility to allocate contiguous shared memory for exchanging data between the host and the slave cores. The memory it allocates from is defined in \qnx\src\ipc3x_dev\sharedmemallocator\resmgr\SharedMemoryAllocator.c thru some #define statements:jjeGubaubj)rlG}rmG(jXL#define SH_MEM_BLOCK1_START 0xBA300000 #define SH_MEM_BLOCK1_SIZE 0x5A00000jjVGjjDjjj}rnG(j@jAj]j]j]j]j]ujMjhj]roGjXL#define SH_MEM_BLOCK1_START 0xBA300000 #define SH_MEM_BLOCK1_SIZE 0x5A00000rpGrqG}rrG(jUjjlGubaubj)rsG}rtG(jX*Typically, even though the code base (as of IPC 3.35) supports up to two blocks, only block 1 is used when allocating memory using the function SHM_alloc(), as shown in the IPC examples. When adjusting this block, It is important that the memory matches a corresponding DEVMEM entry (PHYS_MEM_IOBUFS) in the resource table so that this memory is mapped to the slave core's MMU, and that the memory is reserved in the QNX IFS startup command as per `"How do I change the Memory Map?" `__.jjVGjjDjjj}ruG(j]j]j]j]j]ujKjhj]rvG(jXTypically, even though the code base (as of IPC 3.35) supports up to two blocks, only block 1 is used when allocating memory using the function SHM_alloc(), as shown in the IPC examples. When adjusting this block, It is important that the memory matches a corresponding DEVMEM entry (PHYS_MEM_IOBUFS) in the resource table so that this memory is mapped to the slave core's MMU, and that the memory is reserved in the QNX IFS startup command as per rwGrxG}ryG(jXTypically, even though the code base (as of IPC 3.35) supports up to two blocks, only block 1 is used when allocating memory using the function SHM_alloc(), as shown in the IPC examples. When adjusting this block, It is important that the memory matches a corresponding DEVMEM entry (PHYS_MEM_IOBUFS) in the resource table so that this memory is mapped to the slave core's MMU, and that the memory is reserved in the QNX IFS startup command as per jjsGubj)rzG}r{G(jXi`"How do I change the Memory Map?" `__j}r|G(UnameX!"How do I change the Memory Map?"jXAindex_Foundational_Components.html#how-do-i-change-the-memory-mapj]j]j]j]j]ujjsGj]r}GjX!"How do I change the Memory Map?"r~GrG}rG(jUjjzGubajjubjX.rG}rG(jX.jjsGubeubeubeubj)rG}rG(jUjjFjjDjjj}rG(j]j]j]j]rGUruntime-troubleshootingrGaj]rGhaujKjhj]rG(j)rG}rG(jXRuntime TroubleshootingrGjjGjjDjjj}rG(j]j]j]j]j]ujKjhj]rGjXRuntime TroubleshootingrGrG}rG(jjGjjGubaubj)rG}rG(jUjjGjjDjjj}rG(j]j]j]j]rGU-linux-spurious-msg-received-with-no-recepientrGaj]rGjaujKjhj]rG(j)rG}rG(jX/Linux spurious "msg received with no recepient"rGjjGjjDjjj}rG(j]j]j]j]j]ujKjhj]rGjX/Linux spurious "msg received with no recepient"rGrG}rG(jjGjjGubaubj)rG}rG(jXPWhen a Linux-loaded slave communicates to the Linux host, it sends a msg using an rpmsg "channel". Sometimes there's no one listening on that channel, for example if there are no host-side IPC applications running. When a host-side application calls Ipc_start(), these channels start to be monitored, but until then, no one's listening.rGjjGjjDjjj}rG(j]j]j]j]j]ujKjhj]rGjXPWhen a Linux-loaded slave communicates to the Linux host, it sends a msg using an rpmsg "channel". Sometimes there's no one listening on that channel, for example if there are no host-side IPC applications running. When a host-side application calls Ipc_start(), these channels start to be monitored, but until then, no one's listening.rGrG}rG(jjGjjGubaubj)rG}rG(jXiWhen, for example, a slave does a NameServer lookup, this query is often sent to all cores in the system. If there's no host-side application running, there's no one listening for these msgs, and when the underlying rpmsg driver detects an arriving msg that no one's listening for, it issues a dev_warn() call to report this, drops the message, and moves along.rGjjGjjDjjj}rG(j]j]j]j]j]ujKjhj]rGjXiWhen, for example, a slave does a NameServer lookup, this query is often sent to all cores in the system. If there's no host-side application running, there's no one listening for these msgs, and when the underlying rpmsg driver detects an arriving msg that no one's listening for, it issues a dev_warn() call to report this, drops the message, and moves along.rGrG}rG(jjGjjGubaubj)rG}rG(jXThese warnings are often benign, and sometimes just reflect chatter between the various slaves. Perhaps the dev_warn() should be changed to a dev_dbg().rGjjGjjDjjj}rG(j]j]j]j]j]ujKjhj]rGjXThese warnings are often benign, and sometimes just reflect chatter between the various slaves. Perhaps the dev_warn() should be changed to a dev_dbg().rGrG}rG(jjGjjGubaubj)rG}rG(jXAnd yes, that's a typo - 'recepient' is really spelled 'recipient'. Submit a patch and get your initials into the Linux kernel.  :)rGjjGjjDjjj}rG(j]j]j]j]j]ujKjhj]rGjXAnd yes, that's a typo - 'recepient' is really spelled 'recipient'. Submit a patch and get your initials into the Linux kernel.  :)rGrG}rG(jjGjjGubaubeubj)rG}rG(jUjjGjjDjjj}rG(j]j]j]j]rGUdisabling-auto-recoveryrGaj]rGjaujMjhj]rG(j)rG}rG(jXDisabling auto-recoveryrGjjGjjDjjj}rG(j]j]j]j]j]ujMjhj]rGjXDisabling auto-recoveryrGrG}rG(jjGjjGubaubj)rG}rG(jXWhen the HLOS detects a fault on a slave (e.g. an MMU fault), it reloads and restarts the slave. Sometimes, especially when debugging slave-side errors, it's useful to disable this feature so the state of the crashed slave isn't reset and can be examined.rGjjGjjDjjj}rG(j]j]j]j]j]ujMjhj]rGjXWhen the HLOS detects a fault on a slave (e.g. an MMU fault), it reloads and restarts the slave. Sometimes, especially when debugging slave-side errors, it's useful to disable this feature so the state of the crashed slave isn't reset and can be examined.rGrG}rG(jjGjjGubaubj)rG}rG(jUjKjjGjjDjjj}rG(j]rGXlinuxrGaj]j]j]rGUid42rGaj]ujM jhj]rG(j)rG}rG(jXLinuxrGjjGjjDjjj}rG(j]j]j]j]j]ujM jhj]rGjXLinuxrGrG}rG(jjGjjGubaubj)rG}rG(jXYou can disable recovery of a given remote processor using remoteproc's debugfs features. First, find the slave you want to disable (e.g. ``cat /debug/remoteproc/remoteproc0/name``) and then echo "disabled" to the "recovery" file.jjGjjDjjj}rG(j]j]j]j]j]ujM jhj]rG(jXYou can disable recovery of a given remote processor using remoteproc's debugfs features. First, find the slave you want to disable (e.g. rGrG}rG(jXYou can disable recovery of a given remote processor using remoteproc's debugfs features. First, find the slave you want to disable (e.g. jjGubj)rG}rG(jX*``cat /debug/remoteproc/remoteproc0/name``j}rG(j]j]j]j]j]ujjGj]rGjX&cat /debug/remoteproc/remoteproc0/namerGrG}rG(jUjjGubajjubjX2) and then echo "disabled" to the "recovery" file.rGrG}rG(jX2) and then echo "disabled" to the "recovery" file.jjGubeubj)rG}rG(jX>For example, if "remoteproc0" is the core you want to disable:rGjjGjjDjjj}rG(j]j]j]j]j]ujMjhj]rGjX>For example, if "remoteproc0" is the core you want to disable:rGrG}rH(jjGjjGubaubj)rH}rH(jX@target# echo "disabled" > /debug/remoteproc/remoteproc0/recoveryjjGjjDjjj}rH(j@jAj]j]j]j]j]ujM=jhj]rHjX@target# echo "disabled" > /debug/remoteproc/remoteproc0/recoveryrHrH}rH(jUjjHubaubeubj)rH}r H(jUjKjjGjjDjjj}r H(j]r HXqnxr Haj]j]j]r HUid43rHaj]ujMjhj]rH(j)rH}rH(jXQNXrHjjHjjDjjj}rH(j]j]j]j]j]ujMjhj]rHjXQNXrHrH}rH(jjHjjHubaubj)rH}rH(jXStarting in IPC 3.22, you can simply throw the '-d' option when launching the ipc resource manager to disable the recovery mechanism.rHjjHjjDjjj}rH(j]j]j]j]j]ujMjhj]rHjXStarting in IPC 3.22, you can simply throw the '-d' option when launching the ipc resource manager to disable the recovery mechanism.rHrH}rH(jjHjjHubaubj)r H}r!H(jXIf you are using IPC 3.21 or older, there are a couple of tricks to prevent the slaves from being automatically reloaded and restarted:r"HjjHjjDjjj}r#H(j]j]j]j]j]ujMjhj]r$HjXIf you are using IPC 3.21 or older, there are a couple of tricks to prevent the slaves from being automatically reloaded and restarted:r%Hr&H}r'H(jj"Hjj Hubaubjt)r(H}r)H(jUjjHjjDjjwj}r*H(jyX-j]j]j]j]j]ujM!jhj]r+H(j{)r,H}r-H(jXIf you have the QNX Momentics IDE installed, you can set a breakpoint on the entry of ipc_recover() in /qnx/src/ipc3x_dev/ti/syslink/build/Qnx/resmgr/syslink_main.c. This function is the callback that is invoked when an MMU fault occurs to perform the reload. Halting the host at that point would prevent it from reloading the DSP, and gives you time to inspect the DSP memory. This is nice because it does not necessitate a rebuild of IPC. jj(HjjDjjj}r.H(j]j]j]j]j]ujNjhj]r/Hj)r0H}r1H(jXIf you have the QNX Momentics IDE installed, you can set a breakpoint on the entry of ipc_recover() in /qnx/src/ipc3x_dev/ti/syslink/build/Qnx/resmgr/syslink_main.c. This function is the callback that is invoked when an MMU fault occurs to perform the reload. Halting the host at that point would prevent it from reloading the DSP, and gives you time to inspect the DSP memory. This is nice because it does not necessitate a rebuild of IPC.r2Hjj,HjjDjjj}r3H(j]j]j]j]j]ujM!j]r4HjXIf you have the QNX Momentics IDE installed, you can set a breakpoint on the entry of ipc_recover() in /qnx/src/ipc3x_dev/ti/syslink/build/Qnx/resmgr/syslink_main.c. This function is the callback that is invoked when an MMU fault occurs to perform the reload. Halting the host at that point would prevent it from reloading the DSP, and gives you time to inspect the DSP memory. This is nice because it does not necessitate a rebuild of IPC.r5Hr6H}r7H(jj2Hjj0Hubaubaubj{)r8H}r9H(jXIf you do not have access to the QNX debugger, you can rebuild IPC after commenting out the lines in ipc_recover(), and use the modified IPC resource manager binary for debugging. That would prevent it from reloading the DSP. jj(HjjDjjj}r:H(j]j]j]j]j]ujNjhj]r;Hj)rHjj8HjjDjjj}r?H(j]j]j]j]j]ujM*j]r@HjXIf you do not have access to the QNX debugger, you can rebuild IPC after commenting out the lines in ipc_recover(), and use the modified IPC resource manager binary for debugging. That would prevent it from reloading the DSP.rAHrBH}rCH(jj>HjjI(jUjj9IubajjubjX lad_dra7xx -l log.txt -p 777r?Ir@I}rAI(jX lad_dra7xx -l log.txt -p 777jj5Iubeubaubaubj)rBI}rCI(jXYou can also run both LAD and user application as root(su), thus not requiring permission to be properly set when starting LAD.rDIjjHjjDjjj}rEI(j]j]j]j]j]ujM~jhj]rFIjXYou can also run both LAD and user application as root(su), thus not requiring permission to be properly set when starting LAD.rGIrHI}rII(jjDIjjBIubaubeubj)rJI}rKI(jUjjrHjjDjjj}rLI(j]j]j]j]rMIU%lad-reports-gatemp-ti-dgate-not-foundrNIaj]rOIj'aujMjhj]rPI(j)rQI}rRI(jX'LAD reports \_GateMP_TI_dGate not foundrSIjjJIjjDjjj}rTI(j]j]j]j]j]ujMjhj]rUIjX&LAD reports _GateMP_TI_dGate not foundrVIrWI}rXI(jX'LAD reports \_GateMP_TI_dGate not foundrYIjjQIubaubj)rZI}r[I(jXkWhen the -g option is thrown, the LAD log may show an error about not finding the symbol \_GateMP_TI_dGate:jjJIjjDjjj}r\I(j]j]j]j]j]ujMjhj]r]IjXjWhen the -g option is thrown, the LAD log may show an error about not finding the symbol _GateMP_TI_dGate:r^Ir_I}r`I(jXkWhen the -g option is thrown, the LAD log may show an error about not finding the symbol \_GateMP_TI_dGate:jjZIubaubj)raI}rbI(jX[22.583839] NameServer_getRemote: value for GateMP:_GateMP_TI_dGate not found. [22.583852] GateMP_attach: failed to open default gate on procId 4 [22.583862] status = -5 [22.583871] DONEjjJIjjDjjj}rcI(j@jAj]j]j]j]j]ujMjhj]rdIjX[22.583839] NameServer_getRemote: value for GateMP:_GateMP_TI_dGate not found. [22.583852] GateMP_attach: failed to open default gate on procId 4 [22.583862] status = -5 [22.583871] DONEreIrfI}rgI(jUjjaIubaubj)rhI}riI(jXjThis is because LAD is looking for the default GateMP instance, and did not find it. On the DRA7xx, verifyrjIjjJIjjDjjj}rkI(j]j]j]j]j]ujMjhj]rlIjXjThis is because LAD is looking for the default GateMP instance, and did not find it. On the DRA7xx, verifyrmIrnI}roI(jjjIjjhIubaubj )rpI}rqI(jUjjJIjjDjj j}rrI(jU.j]j]j]jUj]j]jjujMjhj]rsI(j{)rtI}ruI(jXaSharedRegion 0 is defined on DSP1. GateMP implementation on the host requires use of SharedRegionjjpIjjDjjj}rvI(j]j]j]j]j]ujNjhj]rwIj)rxI}ryI(jXaSharedRegion 0 is defined on DSP1. GateMP implementation on the host requires use of SharedRegionrzIjjtIjjDjjj}r{I(j]j]j]j]j]ujMj]r|IjXaSharedRegion 0 is defined on DSP1. GateMP implementation on the host requires use of SharedRegionr}Ir~I}rI(jjzIjjxIubaubaubj{)rI}rI(jX#DSP1 is the owner of SharedRegion 0rIjjpIjjDjjj}rI(j]j]j]j]j]ujNjhj]rIj)rI}rI(jjIjjIjjDjjj}rI(j]j]j]j]j]ujMj]rIjX#DSP1 is the owner of SharedRegion 0rIrI}rI(jjIjjIubaubaubj{)rI}rI(jXTIpc_start() is called on DSP1. This ensures the default GateMP instance is created. jjpIjjDjjj}rI(j]j]j]j]j]ujNjhj]rIj)rI}rI(jXSIpc_start() is called on DSP1. This ensures the default GateMP instance is created.rIjjIjjDjjj}rI(j]j]j]j]j]ujMj]rIjXSIpc_start() is called on DSP1. This ensures the default GateMP instance is created.rIrI}rI(jjIjjIubaubaubeubjc)rI}rI(jUjjJIjjDjjfj}rI(j]j]j]j]j]ujMjhj]rIji)rI}rI(jUjlKjjIjjDjjj}rI(j]j]j]j]j]ujKjhj]ubaubeubeubj)rI}rI(jUjjDjjDjjj}rI(j]j]j]j]rIUhlos-loading-failuresrIaj]rIjMaujMjhj]rI(j)rI}rI(jXHLOS loading failuresrIjjIjjDjjj}rI(j]j]j]j]j]ujMjhj]rIjXHLOS loading failuresrIrI}rI(jjIjjIubaubj)rI}rI(jUjjIjjDjjj}rI(j]j]j]j]rIUbios-side-virtqueue-assertionsrIaj]rIjaujMjhj]rI(j)rI}rI(jXBIOS-side VirtQueue assertionsrIjjIjjDjjj}rI(j]j]j]j]j]ujMjhj]rIjXBIOS-side VirtQueue assertionsrIrI}rI(jjIjjIubaubj)rI}rI(jXThe slave loads ok, but communication fails, and in the slave trace output you find the following assert (line number and timestamp may vary):rIjjIjjDjjj}rI(j]j]j]j]j]ujMjhj]rIjXThe slave loads ok, but communication fails, and in the slave trace output you find the following assert (line number and timestamp may vary):rIrI}rI(jjIjjIubaubj)rI}rI(jX[ 0.000] [t=0x00d090ce] ti.ipc.family.vayu.VirtQueue: ERROR: "VirtQueue.c", line 296: [ 0.000] ti.ipc.family.vayu.VirtQueue: "VirtQueue.c", line 296: [ 0.000] xdc.runtime.Error.raise: terminating executionjjIjjDjjj}rI(j@jAj]j]j]j]j]ujMjhj]rIjX[ 0.000] [t=0x00d090ce] ti.ipc.family.vayu.VirtQueue: ERROR: "VirtQueue.c", line 296: [ 0.000] ti.ipc.family.vayu.VirtQueue: "VirtQueue.c", line 296: [ 0.000] xdc.runtime.Error.raise: terminating executionrIrI}rI(jUjjIubaubj)rI}rI(jXThis error often indicates a mismatch in VRING addresses between the HLOS side and the slave. Often this is because a `custom resource table `__ was provided and the VRING addresses specified don't match the HLOS-side addresses.jjIjjDjjj}rI(j]j]j]j]j]ujMjhj]rI(jXvThis error often indicates a mismatch in VRING addresses between the HLOS side and the slave. Often this is because a rIrI}rI(jXvThis error often indicates a mismatch in VRING addresses between the HLOS side and the slave. Often this is because a jjIubj)rI}rI(jXT`custom resource table `__j}rI(UnameXcustom resource tablejX8index_Foundational_Components.html#resource-custom-tablej]j]j]j]j]ujjIj]rIjXcustom resource tablerIrI}rI(jUjjIubajjubjXT was provided and the VRING addresses specified don't match the HLOS-side addresses.rIrI}rI(jXT was provided and the VRING addresses specified don't match the HLOS-side addresses.jjIubeubeubj)rI}rI(jUjjIjjDjjj}rI(j]j]j]j]rIUPqnx-ipc-driver-takes-a-long-time-to-load-the-slave-executable-s-when-g-is-thrownrIaj]rIjWaujMjhj]rI(j)rI}rI(jXTQNX IPC driver takes a long time to load the slave executable(s) when '-g' is thrownrIjjIjjDjjj}rI(j]j]j]j]j]ujMjhj]rIjXTQNX IPC driver takes a long time to load the slave executable(s) when '-g' is thrownrIrI}rI(jjIjjIubaubj)rI}rI(jXThe '-g' option to the IPC driver is used to enable optional support for GateMP on the host processor. During the setup of GateMP module, it polls the slave processors for the default gate instance, which is created by the owner of SharedRegion 0. If none of the cores loaded has created the default gate, the driver will continue polling and eventually timeout after 2 seconds, which means the loading procedure may be delayed by 2 seconds as a consequence. To better suit a given application, one can adjust the polling interval and the timeout duration in the file /qnx/src/ipc3x_dev/ti/syslink/ipc/hlos/knl/GateMP_daemon.c (this code excerpt may look slightly different depending on the version of IPC you are looking at, but the idea is the same):rIjjIjjDjjj}rI(j]j]j]j]j]ujMjhj]rIjXThe '-g' option to the IPC driver is used to enable optional support for GateMP on the host processor. During the setup of GateMP module, it polls the slave processors for the default gate instance, which is created by the owner of SharedRegion 0. If none of the cores loaded has created the default gate, the driver will continue polling and eventually timeout after 2 seconds, which means the loading procedure may be delayed by 2 seconds as a consequence. To better suit a given application, one can adjust the polling interval and the timeout duration in the file /qnx/src/ipc3x_dev/ti/syslink/ipc/hlos/knl/GateMP_daemon.c (this code excerpt may look slightly different depending on the version of IPC you are looking at, but the idea is the same):rIrI}rI(jjIjjIubaubj)rI}rI(jX// Timeout duration is SETUP_TIMEOUT * polling interval #define SETUP_TIMEOUT 2 Int GateMP_setup(Int32 * sr0ProcId) { ... UInt timeout = SETUP_TIMEOUT; ... if (status == GateMP_S_SUCCESS) { /* The default gate creator is the owner of SR0 */ while (((status = GateMP_openDefaultGate(&GateMP_module->defaultGate, &procId)) == GateMP_E_NOTFOUND) && (timeout > 0)) { sleep(1); // polling interval timeout--; } ... }jjIjjDjjj}rI(jjXcj@jAj]j]j]j}j]j]ujMjhj]rIjX// Timeout duration is SETUP_TIMEOUT * polling interval #define SETUP_TIMEOUT 2 Int GateMP_setup(Int32 * sr0ProcId) { ... UInt timeout = SETUP_TIMEOUT; ... if (status == GateMP_S_SUCCESS) { /* The default gate creator is the owner of SR0 */ while (((status = GateMP_openDefaultGate(&GateMP_module->defaultGate, &procId)) == GateMP_E_NOTFOUND) && (timeout > 0)) { sleep(1); // polling interval timeout--; } ... }rIrI}rI(jUjjIubaubj)rI}rI(jXIn the case where the owner of SharedRegion 0 is not being loaded by the IPC driver, reducing the timeout duration (SETUP_TIMEOUT) may be useful to reduce the delay that results when the driver cannot find the default gate.rIjjIjjDjjj}rI(j]j]j]j]j]ujMjhj]rIjXIn the case where the owner of SharedRegion 0 is not being loaded by the IPC driver, reducing the timeout duration (SETUP_TIMEOUT) may be useful to reduce the delay that results when the driver cannot find the default gate.rJrJ}rJ(jjIjjIubaubj)rJ}rJ(jXIn the case where the owner of SharedRegion 0 is indeed loaded by the IPC driver, using usleep() instead of sleep() to reduce the polling interval can be beneficial in cases where the initial poll happens before the slave core (owner of SR0) has even got to the point in its initialization to create the default gate. A faster polling rate would ensure that a second or a third poll is performed more quickly thereby giving a chance for the driver to move on. On the other hand, reducing the polling interval too much may cause the driver to swamp the slave cores with gate lookup requests, counterproductively slowing down the loading process. As a rule of thumb, it is recommended to keep the polling interval above 1 ms in modern platforms at the time of writing.rJjjIjjDjjj}rJ(j]j]j]j]j]ujMjhj]rJjXIn the case where the owner of SharedRegion 0 is indeed loaded by the IPC driver, using usleep() instead of sleep() to reduce the polling interval can be beneficial in cases where the initial poll happens before the slave core (owner of SR0) has even got to the point in its initialization to create the default gate. A faster polling rate would ensure that a second or a third poll is performed more quickly thereby giving a chance for the driver to move on. On the other hand, reducing the polling interval too much may cause the driver to swamp the slave cores with gate lookup requests, counterproductively slowing down the loading process. As a rule of thumb, it is recommended to keep the polling interval above 1 ms in modern platforms at the time of writing.rJr J}r J(jjJjjJubaubjc)r J}r J(jUjjIjjDjjfj}r J(j]j]j]j]j]ujMjhj]rJji)rJ}rJ(jUjlKjj JjjDjjj}rJ(j]j]j]j]j]ujKjhj]ubaubeubeubj)rJ}rJ(jUjjDjjDjjj}rJ(j]j]j]j]rJUdisabling-runtime-auto-suspendrJaj]rJjaujMjhj]rJ(j)rJ}rJ(jXDisabling runtime auto-suspendrJjjJjjDjjj}rJ(j]j]j]j]j]ujMjhj]rJjXDisabling runtime auto-suspendrJrJ}r J(jjJjjJubaubj)r!J}r"J(jXWhen the HLOS detects that there has been no communication with the slave for a defined amount of time and the slave is idled and in standby state, then it can initiate suspend of the slave. Sometimes, the slave may be performing some tasks that don't require communication with the HLOS and does not wish to enter suspend. Or, it may be useful to temporarily disable auto-suspend while debugging some errors.r#JjjJjjDjjj}r$J(j]j]j]j]j]ujMjhj]r%JjXWhen the HLOS detects that there has been no communication with the slave for a defined amount of time and the slave is idled and in standby state, then it can initiate suspend of the slave. Sometimes, the slave may be performing some tasks that don't require communication with the HLOS and does not wish to enter suspend. Or, it may be useful to temporarily disable auto-suspend while debugging some errors.r&Jr'J}r(J(jj#Jjj!Jubaubj)r)J}r*J(jUjKjjJjjDjjj}r+J(j]r,JXlinuxr-Jaj]j]j]r.JUid44r/Jaj]ujMjhj]r0J(j)r1J}r2J(jXLinuxr3Jjj)JjjDjjj}r4J(j]j]j]j]j]ujMjhj]r5JjXLinuxr6Jr7J}r8J(jj3Jjj1Jubaubj)r9J}r:J(jX%The runtime suspend feature can be enabled or disabled by writing 'auto' or 'on' to the device's 'control' power field. The default is enabled. First, find the slave you want to disable (e.g. ``cat /debug/remoteproc/remoteproc0/name``) and then echo "on" to the device's "control" power field.jj)JjjDjjj}r;J(j]j]j]j]j]ujMjhj]rJ}r?J(jXThe runtime suspend feature can be enabled or disabled by writing 'auto' or 'on' to the device's 'control' power field. The default is enabled. First, find the slave you want to disable (e.g. jj9Jubj)r@J}rAJ(jX*``cat /debug/remoteproc/remoteproc0/name``j}rBJ(j]j]j]j]j]ujj9Jj]rCJjX&cat /debug/remoteproc/remoteproc0/namerDJrEJ}rFJ(jUjj@JubajjubjX;) and then echo "on" to the device's "control" power field.rGJrHJ}rIJ(jX;) and then echo "on" to the device's "control" power field.jj9Jubeubj)rJJ}rKJ(jX>For example, if "remoteproc0" is the core you want to disable:rLJjj)JjjDjjj}rMJ(j]j]j]j]j]ujMjhj]rNJjX>For example, if "remoteproc0" is the core you want to disable:rOJrPJ}rQJ(jjLJjjJJubaubj)rRJ}rSJ(jXHtarget# echo "on" > /sys/bus/platform/devices/58820000.ipu/power/controljj)JjjDjjj}rTJ(j@jAj]j]j]j]j]ujM#jhj]rUJjXHtarget# echo "on" > /sys/bus/platform/devices/58820000.ipu/power/controlrVJrWJ}rXJ(jUjjRJubaubeubj)rYJ}rZJ(jUjjJjjDjjj}r[J(j]j]j]j]r\JUsys-biosr]Jaj]r^JjhaujMjhj]r_J(j)r`J}raJ(jXSYS/BIOSrbJjjYJjjDjjj}rcJ(j]j]j]j]j]ujMjhj]rdJjXSYS/BIOSreJrfJ}rgJ(jjbJjj`Jubaubj)rhJ}riJ(jXAlternatively, the slave can choose to deny the runtime suspend request, preventing suspend. To prevent the slave from suspending, add the `IpcPower_hibernateLock() `__ call to the slave software. When you wish to allow suspend again, call `IpcPower_hibernateUnlock() `__. As long as the lock is held, the slave will deny all suspend requests from the HLOS.jjYJjjDjjj}rjJ(j]j]j]j]j]ujMjhj]rkJ(jXAlternatively, the slave can choose to deny the runtime suspend request, preventing suspend. To prevent the slave from suspending, add the rlJrmJ}rnJ(jXAlternatively, the slave can choose to deny the runtime suspend request, preventing suspend. To prevent the slave from suspending, add the jjhJubj)roJ}rpJ(jX`IpcPower_hibernateLock() `__j}rqJ(UnameXIpcPower_hibernateLock()jXhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_ipc_power_8h.html#aef7ede8453ad5a6a52623188c412f2fcj]j]j]j]j]ujjhJj]rrJjXIpcPower_hibernateLock()rsJrtJ}ruJ(jUjjoJubajjubjXH call to the slave software. When you wish to allow suspend again, call rvJrwJ}rxJ(jXH call to the slave software. When you wish to allow suspend again, call jjhJubj)ryJ}rzJ(jX`IpcPower_hibernateUnlock() `__j}r{J(UnameXIpcPower_hibernateUnlock()jXhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_ipc_power_8h.html#a2aa7348faba4bccb24da503fed3274f9j]j]j]j]j]ujjhJj]r|JjXIpcPower_hibernateUnlock()r}Jr~J}rJ(jUjjyJubajjubjXV. As long as the lock is held, the slave will deny all suspend requests from the HLOS.rJrJ}rJ(jXV. As long as the lock is held, the slave will deny all suspend requests from the HLOS.jjhJubeubj)rJ}rJ(jXNIpcPower_hibernateLock(); ... // Perform tasks ... IpcPower_hibernateUnlock();jjYJjjDjjj}rJ(j@jAj]j]j]j]j]ujM2jhj]rJjXNIpcPower_hibernateLock(); ... // Perform tasks ... IpcPower_hibernateUnlock();rJrJ}rJ(jUjjJubaubj)rJ}rJ(jXMIn this case, it is not necessary to also disable auto-suspend from the HLOS.rJjjYJjjDjjj}rJ(j]j]j]j]j]ujMjhj]rJjXMIn this case, it is not necessary to also disable auto-suspend from the HLOS.rJrJ}rJ(jjJjjJubaubeubj)rJ}rJ(jUjKjjJjjDjjj}rJ(j]rJXqnxrJaj]j]j]rJUid45rJaj]ujMjhj]rJ(j)rJ}rJ(jXQNXrJjjJjjDjjj}rJ(j]j]j]j]j]ujMjhj]rJjXQNXrJrJ}rJ(jjJjjJubaubj)rJ}rJ(jX-Runtime auto-suspend is not supported in QNX.rJjjJjjDjjj}rJ(j]j]j]j]j]ujMjhj]rJjX-Runtime auto-suspend is not supported in QNX.rJrJ}rJ(jjJjjJubaubjc)rJ}rJ(jUjjJjjDjjfj}rJ(j]j]j]j]j]ujMjhj]rJji)rJ}rJ(jUjlKjjJjjDjjj}rJ(j]j]j]j]j]ujKjhj]ubaubeubeubj)rJ}rJ(jUjjDjjjjj}rJ(j]j]j]j]rJUfaq-for-keystone-devicesrJaj]rJjaujKjhj]rJ(j)rJ}rJ(jXFAQ For Keystone DevicesrJjjJjjjjj}rJ(j]j]j]j]j]ujKjhj]rJjXFAQ For Keystone DevicesrJrJ}rJ(jjJjjJubaubj7)rJ}rJ(jXDhttp://processors.wiki.ti.com/index.php/IPC_FAQ_for_Keystone_DevicesjjJjj:XJsource/rtos/PDK_Platform_Software/IPC/IPC_FAQ_for_Keystone_Devices.rst.incrJrJ}rJbjj>j}rJ(j@jAj]j]j]j]j]ujKjhj]rJjXDhttp://processors.wiki.ti.com/index.php/IPC_FAQ_for_Keystone_DevicesrJrJ}rJ(jUjjJubaubj)rJ}rJ(jUjKjjJjjJjjj}rJ(j]rJXoverviewrJaj]j]j]rJUid46rJaj]ujKjhj]rJ(j)rJ}rJ(jXOverviewrJjjJjjJjjj}rJ(j]j]j]j]j]ujKjhj]rJjXOverviewrJrJ}rJ(jjJjjJubaubj)rJ}rJ(jXThis wiki article is a collection of frequently asked questions (FAQ) on IPC on Keystone family of devices , along with some useful collateral and software reference links.rJjjJjjJjjj}rJ(j]j]j]j]j]ujKjhj]rJjXThis wiki article is a collection of frequently asked questions (FAQ) on IPC on Keystone family of devices , along with some useful collateral and software reference links.rJrJ}rJ(jjJjjJubaubjc)rJ}rJ(jUjjJjjJjjfj}rJ(j]j]j]j]j]ujK jhj]rJji)rJ}rJ(jUjlKjjJjjJjjj}rJ(j]j]j]j]j]ujKjhj]ubaubeubj)rJ}rJ(jUjjJjjJjjj}rJ(j]j]j]j]rJU?guide-on-building-and-running-the-ipc-examples-of-processor-sdkrJaj]rJhaujK jhj]rJ(j)rJ}rJ(jX?Guide on building and running the IPC examples of Processor SDKrJjjJjjJjjj}rJ(j]j]j]j]j]ujK jhj]rJjX?Guide on building and running the IPC examples of Processor SDKrJrJ}rJ(jjJjjJubaubjc)rJ}rJ(jUjjJjjJjjfj}rJ(j]j]j]j]j]ujKjhj]rJji)rJ}rJ(jXThis guide will give step by step instruction on how to bring up the target EVMs and how to run the run the IPC examples of processor SDK on target EVM.rJjlKjjJjjJjjj}rJ(j]j]j]j]j]ujKjhj]rKjXThis guide will give step by step instruction on how to bring up the target EVMs and how to run the run the IPC examples of processor SDK on target EVM.rKrK}rK(jjJjjJubaubaubjc)rK}rK(jUjjJjjJjjfj}rK(j]j]j]j]j]ujKjhj]rKji)rK}r K(jXkDownload the guide from :download:`Keystone II IPC Examples <../files/Guide_Keystone_II_IPC_examples_.zip>`jlKjjKjjJjjj}r K(j]j]j]j]j]ujKjhj]r K(jXDownload the guide from r Kr K}rK(jXDownload the guide from jjKubj )rK}rK(jXS:download:`Keystone II IPC Examples <../files/Guide_Keystone_II_IPC_examples_.zip>`rKjjKjjJjj j}rK(UreftypeXdownloadrKj j X,../files/Guide_Keystone_II_IPC_examples_.zipU refdomainUj]j]U refexplicitj]j]j]j j j X#Guide_Keystone_II_IPC_examples_.ziprKujKj]rKj)rK}rK(jjKj}rK(j]j]rK(j jKej]j]j]ujjKj]rKjXKeystone II IPC ExamplesrKrK}rK(jUjjKubajjubaubeubaubjc)rK}rK(jUjjJjjJjjfj}r K(j]j]j]j]j]ujKjhj]r!K(ji)r"K}r#K(jXThis guide will have steps onr$KjlKjjKjjJjjj}r%K(j]j]j]j]j]ujKjhj]r&KjXThis guide will have steps onr'Kr(K}r)K(jj$Kjj"Kubaubji)r*K}r+K(jX'1. Flashing the u-boot and boot u-boot.r,KjlKjjKjjJjjj}r-K(j]j]j]j]j]ujKjhj]r.KjX'1. Flashing the u-boot and boot u-boot.r/Kr0K}r1K(jj,Kjj*Kubaubji)r2K}r3K(jXS2. Flashing the UBIFS image ( Linux and root filesystem ) into NAND and boot Linux.r4KjlKjjKjjJjjj}r5K(j]j]j]j]j]ujKjhj]r6KjXS2. Flashing the UBIFS image ( Linux and root filesystem ) into NAND and boot Linux.r7Kr8K}r9K(jj4Kjj2Kubaubji)r:K}r;K(jX3. Building the IPC package.rKjX3. Building the IPC package.r?Kr@K}rAK(jjQ: Where do I look for the list of IPC API reference document?rkKjjYKjjJjUrubricrlKj}rmK(j]rnKUQ: Where do I look for the list of IPC API reference document?rrKrsK}rtK(jjkKjjiKubaubj)ruK}rvK(jX**Ans:**rwKjjYKjjJjjj}rxK(j]j]j]j]j]ujK'jhj]ryKj)rzK}r{K(jjwKj}r|K(j]j]j]j]j]ujjuKj]r}KjXAns:r~KrK}rK(jUjjzKubajjubaubj)rK}rK(jXxPlease visit : http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/index.htmljjYKjjJjjj}rK(j]j]j]j]j]ujK)jhj]rK(jXPlease visit : rKrK}rK(jXPlease visit : jjKubj)rK}rK(jXhhttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/index.htmlrKj}rK(UrefurijKj]j]j]j]j]ujjKj]rKjXhhttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/index.htmlrKrK}rK(jUjjKubajjubeubj)rK}rK(jX,The IPC product contains the following APIs:rKjjYKjjJjjj}rK(j]j]j]j]j]ujK,jhj]rKjX,The IPC product contains the following APIs:rKrK}rK(jjKjjKubaubj)rK}rK(jX#•GateMP (BIOS, Linux, QNX) •HeapBufMP (BIOS) •HeapMemMP (BIOS) •HeapMultiBufMP (BIOS) •Ipc (BIOS, Linux, QNX) •ListMP (BIOS) •MessageQ (BIOS, Linux, QNX) •MultiProc (BIOS, Linux, QNX) •NameServer (BIOS, Linux, QNX) •Notify (BIOS) •SharedRegion (BIOS) •IpcPower (BIOS)jjYKjjJjjj}rK(j@jAj]j]j]j]j]ujMxjhj]rKjX#•GateMP (BIOS, Linux, QNX) •HeapBufMP (BIOS) •HeapMemMP (BIOS) •HeapMultiBufMP (BIOS) •Ipc (BIOS, Linux, QNX) •ListMP (BIOS) •MessageQ (BIOS, Linux, QNX) •MultiProc (BIOS, Linux, QNX) •NameServer (BIOS, Linux, QNX) •Notify (BIOS) •SharedRegion (BIOS) •IpcPower (BIOS)rKrK}rK(jUjjKubaubj)rK}rK(jXSome environments also provide a "Multimedia RPC" interface. Currently this is limited to OMAP5 and DRA7XX devices running an HLOS.rKjjYKjjJjjj}rK(j]j]j]j]j]ujK=jhj]rKjXSome environments also provide a "Multimedia RPC" interface. Currently this is limited to OMAP5 and DRA7XX devices running an HLOS.rKrK}rK(jjKjjKubaubj)rK}rK(jX,•MmRpc (Linux, QNX) •MmServiceMgr (BIOS)jjYKjjJjjj}rK(j@jAj]j]j]j]j]ujMjhj]rKjX,•MmRpc (Linux, QNX) •MmServiceMgr (BIOS)rKrK}rK(jUjjKubaubjhK)rK}rK(jX5Q: How to re-build the IPC package and its libraries?rKjjYKjjJjjlKj}rK(j]rKU3q-how-to-re-build-the-ipc-package-and-its-librariesrKaj]j]j]j]rKhaujNjhj]rKjX5Q: How to re-build the IPC package and its libraries?rKrK}rK(jjKjjKubaubj)rK}rK(jX**Ans:**rKjjYKjjJjjj}rK(j]j]j]j]j]ujKHjhj]rKj)rK}rK(jjKj}rK(j]j]j]j]j]ujjKj]rKjXAns:rKrK}rK(jUjjKubajjubaubj)rK}rK(jXDActually, the user guide which comes along with the IPC package ( under docs folder) is sufficient to build the IPC package. However, we have extracted below steps from user guide. For building IPC package, you can use either Cygwin/Command-line utility in windows machine or Linux machine. This cannot be built through CCS.rKjjYKjjJjjj}rK(j]j]j]j]j]ujKJjhj]rKjXDActually, the user guide which comes along with the IPC package ( under docs folder) is sufficient to build the IPC package. However, we have extracted below steps from user guide. For building IPC package, you can use either Cygwin/Command-line utility in windows machine or Linux machine. This cannot be built through CCS.rKrK}rK(jjKjjKubaubjc)rK}rK(jUjjYKjjJjjfj}rK(j]j]j]j]j]ujKPjhj]rK(ji)rK}rK(jX_1. Install the mcsdk_bios_3_xx_xx_xx which will install the IPC package version, ipc_3_xx_xx_xxrKjlKjjKjjJjjj}rK(j]j]j]j]j]ujKQjhj]rKjX_1. Install the mcsdk_bios_3_xx_xx_xx which will install the IPC package version, ipc_3_xx_xx_xxrKrK}rK(jjKjjKubaubji)rK}rK(jX:2. Go to the directory where the IPC package is installed.rKjlKjjKjjJjjj}rK(j]j]j]j]j]ujKRjhj]rKjX:2. Go to the directory where the IPC package is installed.rKrK}rK(jjKjjKubaubji)rK}rK(jX[3. Open the products.mak file and make sure the following parameters are set appropriately.rKjlKjjKjjJjjj}rK(j]j]j]j]j]ujKTjhj]rKjX[3. Open the products.mak file and make sure the following parameters are set appropriately.rKrK}rK(jjKjjKubaubeubjc)rK}rK(jUjjYKjjJjjfj}rK(j]j]j]j]j]ujKVjhj]rKji)rK}rK(jX%For example:- ( For ipc-linux build )rKjlKjjKjjJjjj}rK(j]j]j]j]j]ujKVjhj]rKjX%For example:- ( For ipc-linux build )rKrK}rK(jjKjjKubaubaubj)rK}rK(jXFPLATFORM = TCI6638 DESTDIR = /opt/ti/ipc_3_xx_xx_xx/ipc_3_xx_xx_xx_libjjYKjjJjjj}rK(j@jAj]j]j]j]j]ujMjhj]rKjXFPLATFORM = TCI6638 DESTDIR = /opt/ti/ipc_3_xx_xx_xx/ipc_3_xx_xx_xx_librKrK}rK(jUjjKubaubj)rK}rK(jXXDC_INSTALL_DIR = /opt/ti/xdctools_3_xx_xx_xx BIOS_INSTALL_DIR = /opt/ti/bios_6_xx_xx_xx ti.targets.elf.C66 = /opt/ti/ccsv5/tools/compiler/C6000_7.4.5jjYKjjJjjj}rK(j@jAj]j]j]j]j]ujMjhj]rKjXXDC_INSTALL_DIR = /opt/ti/xdctools_3_xx_xx_xx BIOS_INSTALL_DIR = /opt/ti/bios_6_xx_xx_xx ti.targets.elf.C66 = /opt/ti/ccsv5/tools/compiler/C6000_7.4.5rLrL}rL(jUjjKubaubjc)rL}rL(jUjjYKjjJjjfj}rL(j]j]j]j]j]ujKcjhj]rL(ji)rL}rL(jX4. $cd /opt/ti/ ipc_3_xx_xx_xxr LjlKjjLjjJjjj}r L(j]j]j]j]j]ujKcjhj]r LjX4. $cd /opt/ti/ ipc_3_xx_xx_xxr Lr L}rL(jj LjjLubaubji)rL}rL(jX5. $make distcleanrLjlKjjLjjJjjj}rL(j]j]j]j]j]ujKdjhj]rLjX5. $make distcleanrLrL}rL(jjLjjLubaubji)rL}rL(jX"6. $make –f ipc-linux.mak configrLjlKjjLjjJjjj}rL(j]j]j]j]j]ujKejhj]rLjX"6. $make –f ipc-linux.mak configrLrL}rL(jjLjjLubaubji)rL}r L(jX7. $maker!LjlKjjLjjJjjj}r"L(j]j]j]j]j]ujKfjhj]r#LjX7. $maker$Lr%L}r&L(jj!LjjLubaubji)r'L}r(L(jX8. $make installr)LjlKjjLjjJjjj}r*L(j]j]j]j]j]ujKgjhj]r+LjX8. $make installr,Lr-L}r.L(jj)Ljj'Lubaubeubjc)r/L}r0L(jUjjYKjjJjjfj}r1L(j]j]j]j]j]ujKijhj]r2Lji)r3L}r4L(jUjlKjj/LjjJjjj}r5L(j]j]j]j]j]ujKjhj]ubaubjhK)r6L}r7L(jXeQ: Is there any simple example to demonstrate IPC methods like message Q or notify for Keystone-II ?r8LjjYKjjJjjlKj}r9L(j]r:LUaq-is-there-any-simple-example-to-demonstrate-ipc-methods-like-message-q-or-notify-for-keystone-iir;Laj]j]j]j]rLr?L}r@L(jj8Ljj6Lubaubj)rAL}rBL(jX**Ans:**rCLjjYKjjJjjj}rDL(j]j]j]j]j]ujKojhj]rELj)rFL}rGL(jjCLj}rHL(j]j]j]j]j]ujjALj]rILjXAns:rJLrKL}rLL(jUjjFLubajjubaubjc)rML}rNL(jUjjYKjjJjjfj}rOL(j]j]j]j]j]ujKqjhj]rPLji)rQL}rRL(jXWPlease look at the ex44_compute.zip in :~/ti/ipc_3_3x_xx_xx/examples/TCI6638_linux_elfrSLjlKjjMLjjJjjj}rTL(j]j]j]j]j]ujKrjhj]rULjXWPlease look at the ex44_compute.zip in :~/ti/ipc_3_3x_xx_xx/examples/TCI6638_linux_elfrVLrWL}rXL(jjSLjjQLubaubaubj)rYL}rZL(jX~/ti/ipc_3_3x_xx_xx/examples$ ls C6472_bios_elf C6A8149_bios_elf DRA7XX_android_elf DRA7XX_linux_elf makefile TCI6638_linux_elf TI814X_bios_elf C6678_bios_elf dosrc.bat DRA7XX_bios_elf DRA7XX_qnx_elf OMAPL138_linux_elf TDA3XX_bios_elfjjYKjjJjjj}r[L(j@jAj]j]j]j]j]ujMjhj]r\LjX~/ti/ipc_3_3x_xx_xx/examples$ ls C6472_bios_elf C6A8149_bios_elf DRA7XX_android_elf DRA7XX_linux_elf makefile TCI6638_linux_elf TI814X_bios_elf C6678_bios_elf dosrc.bat DRA7XX_bios_elf DRA7XX_qnx_elf OMAPL138_linux_elf TDA3XX_bios_elfr]Lr^L}r_L(jUjjYLubaubj)r`L}raL(jXPlease refer the readme.txt to run and build the example according to the target used. For K2, use the cluster ID as 0 instead of 18.rbLjjYKjjJjjj}rcL(j]j]j]j]j]ujKzjhj]rdLjXPlease refer the readme.txt to run and build the example according to the target used. For K2, use the cluster ID as 0 instead of 18.reLrfL}rgL(jjbLjj`Lubaubj )rhL}riL(jUjjYKjjJjj j}rjL(jU.j]j]j]jUj]j]jjujK}jhj]rkL(j{)rlL}rmL(jX?perl patchExec.pl 0 compute_dspN.xe66 compute_dspN_patched.xe66rnLjjhLjjJjjj}roL(j]j]j]j]j]ujNjhj]rpLj)rqL}rrL(jjnLjjlLjjJjjj}rsL(j]j]j]j]j]ujK}j]rtLjX?perl patchExec.pl 0 compute_dspN.xe66 compute_dspN_patched.xe66ruLrvL}rwL(jjnLjjqLubaubaubj{)rxL}ryL(jX&lad_tci6638 -r 8 -n 9 -b 0 -l log.txt jjhLjjJjjj}rzL(j]j]j]j]j]ujNjhj]r{Lj)r|L}r}L(jX%lad_tci6638 -r 8 -n 9 -b 0 -l log.txtr~LjjxLjjJjjj}rL(j]j]j]j]j]ujK~j]rLjX%lad_tci6638 -r 8 -n 9 -b 0 -l log.txtrLrL}rL(jj~Ljj|Lubaubaubeubjc)rL}rL(jUjjYKjjJjjfj}rL(j]j]j]j]j]ujKjhj]rLji)rL}rL(jUjlKjjLjjJjjj}rL(j]j]j]j]j]ujKjhj]ubaubjhK)rL}rL(jXjQ: For Keystone II, is there any CCS based examples to demonstrate a simple communication between ARM-DSP?rLjjYKjjJjjlKj}rL(j]rLUgq-for-keystone-ii-is-there-any-ccs-based-examples-to-demonstrate-a-simple-communication-between-arm-dsprLaj]j]j]j]rLhaujNjhj]rLjXjQ: For Keystone II, is there any CCS based examples to demonstrate a simple communication between ARM-DSP?rLrL}rL(jjLjjLubaubj)rL}rL(jX**Ans:**rLjjYKjjJjjj}rL(j]j]j]j]j]ujKjhj]rLj)rL}rL(jjLj}rL(j]j]j]j]j]ujjLj]rLjXAns:rLrL}rL(jUjjLubajjubaubj)rL}rL(jX'No. We have only Image Processing Demo.rLjjYKjjJjjj}rL(j]j]j]j]j]ujKjhj]rLjX'No. We have only Image Processing Demo.rLrL}rL(jjLjjLubaubj)rL}rL(jXIn MCSDK 3.x, the ARM core only runs Linux kernel and User Space applications. There isn't any Linux application example using CCS and if any, it will be using Linux commands.rLjjYKjjJjjj}rL(j]j]j]j]j]ujKjhj]rLjXIn MCSDK 3.x, the ARM core only runs Linux kernel and User Space applications. There isn't any Linux application example using CCS and if any, it will be using Linux commands.rLrL}rL(jjLjjLubaubjhK)rL}rL(jXQ: In IPC packages, there are lot of test example(sample.c) code given in the path: "~\ipc_3_3x_xx_xx\packages\ti\ipc\tests". But there is only command line option to build the whole IPC package. No option available to build the test examples individually. This is time consuming to build the whole IPC package. Customers were asking for CCS based environment to build and test as individual example for both DSP and ARM side.jjYKjjJjjlKj}rL(j]rLTq-in-ipc-packages-there-are-lot-of-test-examplesample-c-code-given-in-the-path-ipc-3-3x-xx-xxpackagestiipctests-but-there-is-only-command-line-option-to-build-the-whole-ipc-package-no-option-available-to-build-the-test-examples-individually-this-is-time-consuming-to-build-the-whole-ipc-package-customers-were-asking-for-ccs-based-environment-to-build-and-test-as-individual-example-for-both-dsp-and-arm-siderLaj]j]j]j]rLhaujNjhj]rLjXQ: In IPC packages, there are lot of test example(sample.c) code given in the path: "~ipc_3_3x_xx_xxpackagestiipctests". But there is only command line option to build the whole IPC package. No option available to build the test examples individually. This is time consuming to build the whole IPC package. Customers were asking for CCS based environment to build and test as individual example for both DSP and ARM side.rLrL}rL(jXQ: In IPC packages, there are lot of test example(sample.c) code given in the path: "~\ipc_3_3x_xx_xx\packages\ti\ipc\tests". But there is only command line option to build the whole IPC package. No option available to build the test examples individually. This is time consuming to build the whole IPC package. Customers were asking for CCS based environment to build and test as individual example for both DSP and ARM side.jjLubaubj)rL}rL(jX**Ans:**rLjjYKjjJjjj}rL(j]j]j]j]j]ujKjhj]rLj)rL}rL(jjLj}rL(j]j]j]j]j]ujjLj]rLjXAns:rLrL}rL(jUjjLubajjubaubj)rL}rL(jXThe IPC package has been developed to work on multiple platforms like Linux, Android, QNX and TI-RTOS(SYS/BIOS) so the command line build is selected which is common across all these platforms and we do not have CCS based projects for these examples.rLjjYKjjJjjj}rL(j]j]j]j]j]ujKjhj]rLjXThe IPC package has been developed to work on multiple platforms like Linux, Android, QNX and TI-RTOS(SYS/BIOS) so the command line build is selected which is common across all these platforms and we do not have CCS based projects for these examples.rLrL}rL(jjLjjLubaubjc)rL}rL(jUjjYKjjJjjfj}rL(j]j]j]j]j]ujKjhj]rLji)rL}rL(jUjlKjjLjjJjjj}rL(j]j]j]j]j]ujKjhj]ubaubjhK)rL}rL(jXQ: For keystone-II devices, where do I find the source code of the image processing demo and how to I re-build them? Using ARM core as a master, DSP cores as slaves.rLjjYKjjJjjlKj}rL(j]rLUq-for-keystone-ii-devices-where-do-i-find-the-source-code-of-the-image-processing-demo-and-how-to-i-re-build-them-using-arm-core-as-a-master-dsp-cores-as-slavesrLaj]j]j]j]rLhaujNjhj]rLjXQ: For keystone-II devices, where do I find the source code of the image processing demo and how to I re-build them? Using ARM core as a master, DSP cores as slaves.rLrL}rL(jjLjjLubaubj)rL}rL(jX**Ans:**rLjjYKjjJjjj}rL(j]j]j]j]j]ujKjhj]rLj)rL}rL(jjLj}rL(j]j]j]j]j]ujjLj]rLjXAns:rLrL}rL(jUjjLubajjubaubj)rL}rL(jXTested version : "mcsdk_bios_3_00_03_15". The Image processing demo was tested multiple times with this version and it works fine.rLjjYKjjJjjj}rL(j]j]j]j]j]ujKjhj]rLjXTested version : "mcsdk_bios_3_00_03_15". The Image processing demo was tested multiple times with this version and it works fine.rLrL}rL(jjLjjLubaubj)rL}rL(jXAThe image processing demo source code can be found in below path.rLjjYKjjJjjj}rL(j]j]j]j]j]ujKjhj]rLjXAThe image processing demo source code can be found in below path.rLrL}rL(jjLjjLubaubj)rL}rL(jXg**PATH:** C:\ti\mcsdk_bios_3_0x_0x_0x\demos\image_processing\ipc (master, slave and common directories)jjYKjjJjjj}rM(j]j]j]j]j]ujKjhj]rM(j)rM}rM(jX **PATH:**j}rM(j]j]j]j]j]ujjLj]rMjXPATH:rMrM}rM(jUjjMubajjubjXY C:timcsdk_bios_3_0x_0x_0xdemosimage_processingipc (master, slave and common directories)r Mr M}r M(jX^ C:\ti\mcsdk_bios_3_0x_0x_0x\demos\image_processing\ipc (master, slave and common directories)jjLubeubj)r M}r M(jXQ**Building Slave Code:** The project can be imported into CCS and can be rebuilt.jjYKjjJjjj}rM(j]j]j]j]j]ujKjhj]rM(j)rM}rM(jX**Building Slave Code:**j}rM(j]j]j]j]j]ujj Mj]rMjXBuilding Slave Code:rMrM}rM(jUjjMubajjubjX9 The project can be imported into CCS and can be rebuilt.rMrM}rM(jX9 The project can be imported into CCS and can be rebuilt.jj Mubeubj)rM}rM(jXS*For K2E:* “~\mcsdk_bios_3_0x_0x_0x\demos\image_processing\ipc\evm66ak2e\slave”jjYKjjJjjj}rM(j]j]j]j]j]ujKjhj]rM(jM)rM}rM(jX *For K2E:*j}r M(j]j]j]j]j]ujjMj]r!MjXFor K2E:r"Mr#M}r$M(jUjjMubajjUubjXC “~mcsdk_bios_3_0x_0x_0xdemosimage_processingipcevm66ak2eslave”r%Mr&M}r'M(jXI “~\mcsdk_bios_3_0x_0x_0x\demos\image_processing\ipc\evm66ak2e\slave”jjMubeubj)r(M}r)M(jXW*For K2K:* “~\mcsdk_bios_3_0x_0x_0x\demos\image_processing\ipc\evmtci6638k2k\slave”jjYKjjJjjj}r*M(j]j]j]j]j]ujKjhj]r+M(jM)r,M}r-M(jX *For K2K:*j}r.M(j]j]j]j]j]ujj(Mj]r/MjXFor K2K:r0Mr1M}r2M(jUjj,MubajjUubjXG “~mcsdk_bios_3_0x_0x_0xdemosimage_processingipcevmtci6638k2kslave”r3Mr4M}r5M(jXM “~\mcsdk_bios_3_0x_0x_0x\demos\image_processing\ipc\evmtci6638k2k\slave”jj(Mubeubj)r6M}r7M(jXW*For K2L:* “~\mcsdk_bios_3_0x_0x_0x\demos\image_processing\ipc\evmtci6630k2l\slave”jjYKjjJjjj}r8M(j]j]j]j]j]ujKjhj]r9M(jM)r:M}r;M(jX *For K2L:*j}rMr?M}r@M(jUjj:MubajjUubjXG “~mcsdk_bios_3_0x_0x_0xdemosimage_processingipcevmtci6630k2lslave”rAMrBM}rCM(jXM “~\mcsdk_bios_3_0x_0x_0x\demos\image_processing\ipc\evmtci6630k2l\slave”jj6Mubeubj)rDM}rEM(jX**Building Master Code:**rFMjjYKjjJjjj}rGM(j]j]j]j]j]ujKjhj]rHMj)rIM}rJM(jjFMj}rKM(j]j]j]j]j]ujjDMj]rLMjXBuilding Master Code:rMMrNM}rOM(jUjjIMubajjubaubj)rPM}rQM(jXIThis can be built in the linux environment using the makefile provided atrRMjjYKjjJjjj}rSM(j]j]j]j]j]ujKjhj]rTMjXIThis can be built in the linux environment using the makefile provided atrUMrVM}rWM(jjRMjjPMubaubj)rXM}rYM(jX(~\mcsdk_bios_3_0x_0x_0x\demos\image_processing\ipc\evm66ak2x\master\make ) which in turn uses the makefile located at ~\mcsdk_bios_3_0x_0x_0x\demos\image_processing\ipc\master\srcjjYKjjJjjj}rZM(j]j]j]j]j]ujKjhj]r[MjX(~mcsdk_bios_3_0x_0x_0xdemosimage_processingipcevm66ak2xmastermake ) which in turn uses the makefile located at ~mcsdk_bios_3_0x_0x_0xdemosimage_processingipcmastersrcr\Mr]M}r^M(jX(~\mcsdk_bios_3_0x_0x_0x\demos\image_processing\ipc\evm66ak2x\master\make ) which in turn uses the makefile located at ~\mcsdk_bios_3_0x_0x_0x\demos\image_processing\ipc\master\srcjjXMubaubjc)r_M}r`M(jUjjYKjjJjjfj}raM(j]j]j]j]j]ujKjhj]rbMji)rcM}rdM(jUjlKjj_MjjJjjj}reM(j]j]j]j]j]ujKjhj]ubaubjhK)rfM}rgM(jXPQ: How to import the slave code of Image processing demo and how do I build it?rhMjjYKjjJjjlKj}riM(j]rjMULqhow-to-import-the-slave-code-of-image-processing-demo-and-how-do-i-build-itrkMaj]j]j]j]rlMhaujNjhj]rmMjXPQ: How to import the slave code of Image processing demo and how do I build it?rnMroM}rpM(jjhMjjfMubaubj)rqM}rrM(jX**Ans:**rsMjjYKjjJjjj}rtM(j]j]j]j]j]ujKjhj]ruMj)rvM}rwM(jjsMj}rxM(j]j]j]j]j]ujjqMj]ryMjXAns:rzMr{M}r|M(jUjjvMubajjubaubj)r}M}r~M(jXRefer the screenshot below in which the correct path should be provided to pick up the project and its sources. Note that the option for “Copy projects into work space" should be unchecked.rMjjYKjjJjjj}rM(j]j]j]j]j]ujKjhj]rMjXRefer the screenshot below in which the correct path should be provided to pick up the project and its sources. Note that the option for “Copy projects into work space" should be unchecked.rMrM}rM(jjMjj}MubaubjR)rM}rM(jX#.. Image:: ../images/ImportPjt.jpg jjYKjjJjjZj}rM(UuriXrtos/../images/ImportPjt.jpgrMj]j]j]j]jX}rMU*jMsj]ujKjhj]ubjc)rM}rM(jUjjYKjjJjjfj}rM(j]j]j]j]j]ujKjhj]rMji)rM}rM(jUjlKjjMjjJjjj}rM(j]j]j]j]j]ujKjhj]ubaubj)rM}rM(jXIn the project explorer screen, check whether you are able to see the folders, slave --> src --> \*.c files.... Right click on the project and give build.jjYKjjJjjj}rM(j]j]j]j]j]ujKjhj]rMjXIn the project explorer screen, check whether you are able to see the folders, slave --> src --> *.c files.... Right click on the project and give build.rMrM}rM(jXIn the project explorer screen, check whether you are able to see the folders, slave --> src --> \*.c files.... Right click on the project and give build.jjMubaubjR)rM}rM(jX'.. Image:: ../images/Sourcefilepjt.jpg jjYKjjJjjZj}rM(UuriX rtos/../images/Sourcefilepjt.jpgrMj]j]j]j]jX}rMU*jMsj]ujKjhj]ubjhK)rM}rM(jXQ: After building the slave code of the Image processing demo using CCS, where it needs to be replaced in the linux file system?rMjjYKjjJjjlKj}rM(j]rMU}q-after-building-the-slave-code-of-the-image-processing-demo-using-ccs-where-it-needs-to-be-replaced-in-the-linux-file-systemrMaj]j]j]j]rMjDaujNjhj]rMjXQ: After building the slave code of the Image processing demo using CCS, where it needs to be replaced in the linux file system?rMrM}rM(jjMjjMubaubj)rM}rM(jX**Ans:**rMjjYKjjJjjj}rM(j]j]j]j]j]ujKjhj]rMj)rM}rM(jjMj}rM(j]j]j]j]j]ujjMj]rMjXAns:rMrM}rM(jUjjMubajjubaubj)rM}rM(jXTake the binary file, image_processing_evmtci66xxk2x_slave.out and replace it in the path target Linux filesystem, “/usr/share/matrix-gui-2.0/apps/demo_imageproc/bin/"rMjjYKjjJjjj}rM(j]j]j]j]j]ujKjhj]rMjXTake the binary file, image_processing_evmtci66xxk2x_slave.out and replace it in the path target Linux filesystem, “/usr/share/matrix-gui-2.0/apps/demo_imageproc/bin/"rMrM}rM(jjMjjMubaubjhK)rM}rM(jXQ:  While building the ARM(master) side code of Image processing demo, I see a compilation error message about Std.h as below when I make it with or without BUILD_LOCAL=true.rMjjYKjjJjjlKj}rM(j]rMUq-while-building-the-armmaster-side-code-of-image-processing-demo-i-see-a-compilation-error-message-about-std-h-as-below-when-i-make-it-with-or-without-build-localtruerMaj]j]j]j]rMjaujNjhj]rMjXQ:  While building the ARM(master) side code of Image processing demo, I see a compilation error message about Std.h as below when I make it with or without BUILD_LOCAL=true.rMrM}rM(jjMjjMubaubjc)rM}rM(jUjjYKjjJjjfj}rM(j]j]j]j]j]ujKjhj]rM(ji)rM}rM(jX*Error:*rMjlKjjMjjJjjj}rM(j]j]j]j]j]ujKjhj]rMjM)rM}rM(jjMj}rM(j]j]j]j]j]ujjMj]rMjXError:rMrM}rM(jUjjMubajjUubaubji)rM}rM(jX^***user@ubuntu:~/ti/mcsdk_bios_3_0x_0x_0x/demos/image_processing/ipc/evm66ak2x/master$*** makejlKjjMjjJjjj}rM(j]j]j]j]j]ujKjhj]rM(j)rM}rM(jXY***user@ubuntu:~/ti/mcsdk_bios_3_0x_0x_0x/demos/image_processing/ipc/evm66ak2x/master$***j}rM(j]j]j]j]j]ujjMj]rMjXU*user@ubuntu:~/ti/mcsdk_bios_3_0x_0x_0x/demos/image_processing/ipc/evm66ak2x/master$*rMrM}rM(jUjjMubajjubjX makerMrM}rM(jX makejjMubeubeubjc)rM}rM(jUjjYKjjJjjfj}rM(j]j]j]j]j]ujKjhj]rMji)rM}rM(jX*make[1]: Entering directory \`/home/user/ti/mcsdk_bios_3_0x_0x_0x/demos/image_processing/ipc/master/src' mcip_mem_mgmt.c:53:24: fatal error: ti/ipc/Std.h: No such file or directory #include  Compilation terminated.*jlKjjMjjJjjj}rM(j]j]j]j]j]ujKjhj]rMjM)rM}rM(jX*make[1]: Entering directory \`/home/user/ti/mcsdk_bios_3_0x_0x_0x/demos/image_processing/ipc/master/src' mcip_mem_mgmt.c:53:24: fatal error: ti/ipc/Std.h: No such file or directory #include  Compilation terminated.*j}rM(j]j]j]j]j]ujjMj]rMjXmake[1]: Entering directory `/home/user/ti/mcsdk_bios_3_0x_0x_0x/demos/image_processing/ipc/master/src' mcip_mem_mgmt.c:53:24: fatal error: ti/ipc/Std.h: No such file or directory #include  Compilation terminated.rMrM}rM(jUjjMubajjUubaubaubjc)rM}rM(jUjjYKjjJjjfj}rM(j]j]j]j]j]ujKjhj]rM(ji)rM}rM(jX**Ans:**rMjlKjjMjjJjjj}rM(j]j]j]j]j]ujKjhj]rMj)rM}rM(jjMj}rM(j]j]j]j]j]ujjMj]rNjXAns:rNrN}rN(jUjjMubajjubaubji)rN}rN(jXThere is an error in the Makefile. Make file needs to be updated for including the appropriate search path for "Std.h". You will find it at "../ti/ipc_3_3x_0x_0x/linux/includerNjlKjjMjjJjjj}rN(j]j]j]j]j]ujKjhj]rNjXThere is an error in the Makefile. Make file needs to be updated for including the appropriate search path for "Std.h". You will find it at "../ti/ipc_3_3x_0x_0x/linux/includer Nr N}r N(jjNjjNubaubeubj)r N}r N(jXoUpdate the Makefile located at "mcsdk_bios_3_0x_0x_0x\demos\image_processing\ipc\master\src\makefile" as below,jjYKjjJjjj}rN(j]j]j]j]j]ujKjhj]rNjXiUpdate the Makefile located at "mcsdk_bios_3_0x_0x_0xdemosimage_processingipcmastersrcmakefile" as below,rNrN}rN(jXoUpdate the Makefile located at "mcsdk_bios_3_0x_0x_0x\demos\image_processing\ipc\master\src\makefile" as below,jj Nubaubjc)rN}rN(jUjjYKjjJjjfj}rN(j]j]j]j]j]ujKjhj]rNji)rN}rN(jX*For example:*rNjlKjjNjjJjjj}rN(j]j]j]j]j]ujKjhj]rNjM)rN}rN(jjNj}rN(j]j]j]j]j]ujjNj]rNjX For example:r Nr!N}r"N(jUjjNubajjUubaubaubj)r#N}r$N(jXIPC_INSTALL_DIR := /opt/ti/ipc_3_xx_0x_0x CFLAGS  := -Wall -I$(COMMON_INC) -I$(MASTER_INC) -I$(IPC_INSTALL_DIR)/linux/include -I$(IPC_INSTALL_DIR)/packages -D_GNU_SOURCEjjYKjjJjjj}r%N(j@jAj]j]j]j]j]ujMHjhj]r&NjXIPC_INSTALL_DIR := /opt/ti/ipc_3_xx_0x_0x CFLAGS  := -Wall -I$(COMMON_INC) -I$(MASTER_INC) -I$(IPC_INSTALL_DIR)/linux/include -I$(IPC_INSTALL_DIR)/packages -D_GNU_SOURCEr'Nr(N}r)N(jUjj#NubaubjhK)r*N}r+N(jXnQ: While building the ARM(master) side code of Image processing demo, I see a linker error message like below.r,NjjYKjjJjjlKj}r-N(j]r.NUiq-while-building-the-armmaster-side-code-of-image-processing-demo-i-see-a-linker-error-message-like-belowr/Naj]j]j]j]r0NjaujNjhj]r1NjXnQ: While building the ARM(master) side code of Image processing demo, I see a linker error message like below.r2Nr3N}r4N(jj,Njj*Nubaubjc)r5N}r6N(jUjjYKjjJjjfj}r7N(j]j]j]j]j]ujMjhj]r8N(ji)r9N}r:N(jX*Error:*r;NjlKjj5NjjJjjj}rN}r?N(jj;Nj}r@N(j]j]j]j]j]ujj9Nj]rANjXError:rBNrCN}rDN(jUjj>NubajjUubaubji)rEN}rFN(jX*/usr/bin/ld: skipping incompatible /opt/ti/ipc_3_35_01_07/examples/TCI6638_linux_elf /ex44_compute_bkp/lib//libtitransportrpmsg.a when searching for -ltitransportrpmsg /usr/bin/ld: cannot find –ltitransportrpmsg*rGNjlKjj5NjjJjjj}rHN(j]j]j]j]j]ujM jhj]rINjM)rJN}rKN(jjGNj}rLN(j]j]j]j]j]ujjENj]rMNjX/usr/bin/ld: skipping incompatible /opt/ti/ipc_3_35_01_07/examples/TCI6638_linux_elf /ex44_compute_bkp/lib//libtitransportrpmsg.a when searching for -ltitransportrpmsg /usr/bin/ld: cannot find –ltitransportrpmsgrNNrON}rPN(jUjjJNubajjUubaubji)rQN}rRN(jX$usr/bin/ld: cannot find -ltiipcutilsrSNjlKjj5NjjJjjj}rTN(j]j]j]j]j]ujM jhj]rUNjX$usr/bin/ld: cannot find -ltiipcutilsrVNrWN}rXN(jjSNjjQNubaubji)rYN}rZN(jX*collect2: error: ld returned 1 exit statusr[NjlKjj5NjjJjjj}r\N(j]j]j]j]j]ujMjhj]r]NjX*collect2: error: ld returned 1 exit statusr^Nr_N}r`N(jj[NjjYNubaubji)raN}rbN(jX>make: \**\* [../../master/image_processing_master.out] Error 1jlKjj5NjjJjjj}rcN(j]j]j]j]j]ujMjhj]rdNjX<make: *** [../../master/image_processing_master.out] Error 1reNrfN}rgN(jX>make: \**\* [../../master/image_processing_master.out] Error 1jjaNubaubji)rhN}riN(jXRroot@e2e:/opt/ti/mcsdk_bios_3_0x_xx_xx/demos/image_processing/ipc/master/src#\ * *jlKjj5NjjJjjj}rjN(j]j]j]j]j]ujMjhj]rkN(j)rlN}rmN(jXroot@e2ej}rnN(UrefuriXmailto:root@e2ej]j]j]j]j]ujjhNj]roNjXroot@e2erpNrqN}rrN(jUjjlNubajjubjXH:/opt/ti/mcsdk_bios_3_0x_xx_xx/demos/image_processing/ipc/master/src#* *rsNrtN}ruN(jXJ:/opt/ti/mcsdk_bios_3_0x_xx_xx/demos/image_processing/ipc/master/src#\ * *jjhNubeubeubjc)rvN}rwN(jUjjYKjjJjjfj}rxN(j]j]j]j]j]ujMjhj]ryN(ji)rzN}r{N(jX**Ans:**r|NjlKjjvNjjJjjj}r}N(j]j]j]j]j]ujMjhj]r~Nj)rN}rN(jj|Nj}rN(j]j]j]j]j]ujjzNj]rNjXAns:rNrN}rN(jUjjNubajjubaubji)rN}rN(jXFor these errors, please make sure you already built the Whole IPC package and installed the libraries such as transportrpmsg in a destination directory. This destination directory should be given in the makefile to find those libraries.rNjlKjjvNjjJjjj}rN(j]j]j]j]j]ujMjhj]rNjXFor these errors, please make sure you already built the Whole IPC package and installed the libraries such as transportrpmsg in a destination directory. This destination directory should be given in the makefile to find those libraries.rNrN}rN(jjNjjNubaubeubjc)rN}rN(jUjjYKjjJjjfj}rN(j]j]j]j]j]ujMjhj]rNji)rN}rN(jXlFor example, in the makefile located at mcsdk_bios_3_0x_xx_xx\demos\image_processing\ipc\master\src\makefilejlKjjNjjJjjj}rN(j]j]j]j]j]ujMjhj]rNjXfFor example, in the makefile located at mcsdk_bios_3_0x_xx_xxdemosimage_processingipcmastersrcmakefilerNrN}rN(jXlFor example, in the makefile located at mcsdk_bios_3_0x_xx_xx\demos\image_processing\ipc\master\src\makefilejjNubaubaubj)rN}rN(jXIPC_INSTALL_DIR := /opt/ti/ipc_3_3x_xx_xx #The location where the libraries are installed after building the IPC package SIPC_LINUX_DIR := /opt/ti/ipc_3_3x_xx_xx/IPC_Linux_librariesjjYKjjJjjj}rN(j@jAj]j]j]j]j]ujMfjhj]rNjXIPC_INSTALL_DIR := /opt/ti/ipc_3_3x_xx_xx #The location where the libraries are installed after building the IPC package SIPC_LINUX_DIR := /opt/ti/ipc_3_3x_xx_xx/IPC_Linux_librariesrNrN}rN(jUjjNubaubj)rN}rN(jXVCROSS_COMPILE ?= arm-linux-gnueabihf- CC  := $(CROSS_COMPILE)gcc CFLAGS  := -Wall -I$(COMMON_INC) -I$(MASTER_INC) -I$(IPC_INSTALL_DIR)/linux/include -I$(IPC_INSTALL_DIR)/packages -D_GNU_SOURCE LFLAGS  := -lpthread -L$(SIPC_LINUX_DIR)/ -ltitransportrpmsg -L$(SIPC_LINUX_DIR)/ -ltiipc -L$(SIPC_LINUX_DIR)/ -ltiipcutilsjjYKjjJjjj}rN(j@jAj]j]j]j]j]ujMmjhj]rNjXVCROSS_COMPILE ?= arm-linux-gnueabihf- CC  := $(CROSS_COMPILE)gcc CFLAGS  := -Wall -I$(COMMON_INC) -I$(MASTER_INC) -I$(IPC_INSTALL_DIR)/linux/include -I$(IPC_INSTALL_DIR)/packages -D_GNU_SOURCE LFLAGS  := -lpthread -L$(SIPC_LINUX_DIR)/ -ltitransportrpmsg -L$(SIPC_LINUX_DIR)/ -ltiipc -L$(SIPC_LINUX_DIR)/ -ltiipcutilsrNrN}rN(jUjjNubaubjc)rN}rN(jUjjYKjjJjjfj}rN(j]j]j]j]j]ujM*jhj]rNji)rN}rN(jUjlKjjNjjJjjj}rN(j]j]j]j]j]ujKjhj]ubaubjhK)rN}rN(jXQ: The Image processing demo does not work on the version of MCSDK, V3.0x.xx.x on both the K2H and K2E EVMs. The earlier version of MCSDK works on both the EVMs. Will it be fixed on next version?rNjjYKjjJjjlKj}rN(j]rNUq-the-image-processing-demo-does-not-work-on-the-version-of-mcsdk-v3-0x-xx-x-on-both-the-k2h-and-k2e-evms-the-earlier-version-of-mcsdk-works-on-both-the-evms-will-it-be-fixed-on-next-versionrNaj]j]j]j]rNjwaujNjhj]rNjXQ: The Image processing demo does not work on the version of MCSDK, V3.0x.xx.x on both the K2H and K2E EVMs. The earlier version of MCSDK works on both the EVMs. Will it be fixed on next version?rNrN}rN(jjNjjNubaubj)rN}rN(jX**Ans:**rNjjYKjjJjjj}rN(j]j]j]j]j]ujM1jhj]rNj)rN}rN(jjNj}rN(j]j]j]j]j]ujjNj]rNjXAns:rNrN}rN(jUjjNubajjubaubjc)rN}rN(jUjjYKjjJjjfj}rN(j]j]j]j]j]ujM3jhj]rNji)rN}rN(jXGMake sure the u-boot environments is set as below to work on MCSDK 3.x.rNjlKjjNjjJjjj}rN(j]j]j]j]j]ujM4jhj]rNjXGMake sure the u-boot environments is set as below to work on MCSDK 3.x.rNrN}rN(jjNjjNubaubaubj)rN}rN(jXNu-boot# env default –f –a u-boot# setenv mem_reserve 1536M u-boot# saveenvjjYKjjJjjj}rN(j@jAj]j]j]j]j]ujMjhj]rNjXNu-boot# env default –f –a u-boot# setenv mem_reserve 1536M u-boot# saveenvrNrN}rN(jUjjNubaubjc)rN}rN(jUjjYKjjJjjfj}rN(j]j]j]j]j]ujM<jhj]rNji)rN}rN(jUjlKjjNjjJjjj}rN(j]j]j]j]j]ujKjhj]ubaubjhK)rN}rN(jX:Q: How to build and run the qmssIpcBenchmark on C6678 EVM?rNjjYKjjJjjlKj}rN(j]rNU8q-how-to-build-and-run-the-qmssipcbenchmark-on-c6678-evmrNaj]j]j]j]rNhdaujNjhj]rNjX:Q: How to build and run the qmssIpcBenchmark on C6678 EVM?rNrN}rN(jjNjjNubaubj)rN}rN(jX**Ans:**rNjjYKjjJjjj}rN(j]j]j]j]j]ujMAjhj]rNj)rN}rN(jjNj}rN(j]j]j]j]j]ujjNj]rNjXAns:rNrN}rN(jUjjNubajjubaubj)rN}rN(jX**Hardware set up:**rNjjYKjjJjjj}rN(j]j]j]j]j]ujMCjhj]rNj)rN}rN(jjNj}rN(j]j]j]j]j]ujjNj]rNjXHardware set up:rNrO}rO(jUjjNubajjubaubj)rO}rO(jX]Set the boot mode dip switch to no boot/EMIF16 mode, Connect power and emulator to C6678 EVM.jjYKjjJjjj}rO(j@jAj]j]j]j]j]ujMjhj]rOjX]Set the boot mode dip switch to no boot/EMIF16 mode, Connect power and emulator to C6678 EVM.rOrO}rO(jUjjOubaubj)r O}r O(jXy**Software setup:** 1. After power ON the EVM, create and launch the target configuration file(.ccxml) for CCS debugging.jjYKjjJjjj}r O(j]j]j]j]j]ujMIjhj]r O(j)r O}rO(jX**Software setup:**j}rO(j]j]j]j]j]ujj Oj]rOjXSoftware setup:rOrO}rO(jUjj OubajjubjXf 1. After power ON the EVM, create and launch the target configuration file(.ccxml) for CCS debugging.rOrO}rO(jXf 1. After power ON the EVM, create and launch the target configuration file(.ccxml) for CCS debugging.jj Oubeubj )rO}rO(jUjjYKjjJjj j}rO(jU.jO3Kj]j]j]jUj]j]jjujMMjhj]rO(j{)rO}rO(jX Group Core 0 and Core 1 in CCS. jjOjjJjjj}rO(j]j]j]j]j]ujNjhj]rOj)rO}r O(jXGroup Core 0 and Core 1 in CCS.r!OjjOjjJjjj}r"O(j]j]j]j]j]ujMMj]r#OjXGroup Core 0 and Core 1 in CCS.r$Or%O}r&O(jj!OjjOubaubaubj{)r'O}r(O(jX%Connect to both cores via the group. jjOjjJjjj}r)O(j]j]j]j]j]ujNjhj]r*Oj)r+O}r,O(jX$Connect to both cores via the group.r-Ojj'OjjJjjj}r.O(j]j]j]j]j]ujMOj]r/OjX$Connect to both cores via the group.r0Or1O}r2O(jj-Ojj+Oubaubaubeubj)r3O}r4O(jX-4. Load the evmc66xxl.gel to initialize the DDR. The GEL can be found in the "CCS install dir"\ccsv5\ccs_base_x.x.x.xxxxx\emulation\boards\evmc66xxl\gel directory. Once loaded execute the default setup script on each core. In the CCS menu go to Scripts->EVMC6678L Init Functions->Global_Default_Setup.jjYKjjJjjj}r5O(j]j]j]j]j]ujMQjhj]r6OjX'4. Load the evmc66xxl.gel to initialize the DDR. The GEL can be found in the "CCS install dir"ccsv5ccs_base_x.x.x.xxxxxemulationboardsevmc66xxlgel directory. Once loaded execute the default setup script on each core. In the CCS menu go to Scripts->EVMC6678L Init Functions->Global_Default_Setup.r7Or8O}r9O(jX-4. Load the evmc66xxl.gel to initialize the DDR. The GEL can be found in the "CCS install dir"\ccsv5\ccs_base_x.x.x.xxxxx\emulation\boards\evmc66xxl\gel directory. Once loaded execute the default setup script on each core. In the CCS menu go to Scripts->EVMC6678L Init Functions->Global_Default_Setup.jj3Oubaubj)r:O}r;O(jX5. Highlighting the Group in the CCS Debug window, load transport\ipc\examples\qmssIpcBenchmark\Debug\qmssIpcBenchmark_c66xx.out on each corejjYKjjJjjj}rOr?O}r@O(jX5. Highlighting the Group in the CCS Debug window, load transport\ipc\examples\qmssIpcBenchmark\Debug\qmssIpcBenchmark_c66xx.out on each corejj:Oubaubj)rAO}rBO(jXN6. Highlighting the Group in CCS Debug window, run the program in CCS on both cores simultaneously, qmssIpcBenchmark_c66xx will send messageQ messages between the cores via the QMSS transport. The messages will be used to measure the transport's performance. The test will be complete after the throughput (msg/s) has been calculated.rCOjjYKjjJjjj}rDO(j]j]j]j]j]ujM\jhj]rEOjXN6. Highlighting the Group in CCS Debug window, run the program in CCS on both cores simultaneously, qmssIpcBenchmark_c66xx will send messageQ messages between the cores via the QMSS transport. The messages will be used to measure the transport's performance. The test will be complete after the throughput (msg/s) has been calculated.rFOrGO}rHO(jjCOjjAOubaubjR)rIO}rJO(jX".. Image:: ../images/Qmss_IPC.png jjYKjjJjjZj}rKO(UuriXrtos/../images/Qmss_IPC.pngrLOj]j]j]j]jX}rMOU*jLOsj]ujMcjhj]ubjhK)rNO}rOO(jXrQ: How can I build the qmssIpcbenchmark of pdk_C6678_1_1_2_x pdk_C6678_1_1_2_x with release build configuration ?rPOjjYKjjJjjlKj}rQO(j]rROUnq-how-can-i-build-the-qmssipcbenchmark-of-pdk-c6678-1-1-2-x-pdk-c6678-1-1-2-x-with-release-build-configurationrSOaj]j]j]j]rTOh}aujNjhj]rUOjXrQ: How can I build the qmssIpcbenchmark of pdk_C6678_1_1_2_x pdk_C6678_1_1_2_x with release build configuration ?rVOrWO}rXO(jjPOjjNOubaubj)rYO}rZO(jX**Ans:**r[OjjYKjjJjjj}r\O(j]j]j]j]j]ujMhjhj]r]Oj)r^O}r_O(jj[Oj}r`O(j]j]j]j]j]ujjYOj]raOjXAns:rbOrcO}rdO(jUjj^Oubajjubaubjc)reO}rfO(jUjjYKjjJjjfj}rgO(j]j]j]j]j]ujMjjhj]rhO(ji)riO}rjO(jXActually the option, "-mo -o3 -q -k -eo.o" works for building the IPC-QMSS transport library in release mode and the option "-mo -g -q -k -eo.o" works for building the IPC-QMSS transport library in debug mode.rkOjlKjjeOjjJjjj}rlO(j]j]j]j]j]ujMljhj]rmOjXActually the option, "-mo -o3 -q -k -eo.o" works for building the IPC-QMSS transport library in release mode and the option "-mo -g -q -k -eo.o" works for building the IPC-QMSS transport library in debug mode.rnOroO}rpO(jjkOjjiOubaubji)rqO}rrO(jXBut the common.bld script of IPC doesnot create a "release" folder. By default it always creates the "debug" folder and dumps all the binaries.rsOjlKjjeOjjJjjj}rtO(j]j]j]j]j]ujMojhj]ruOjXBut the common.bld script of IPC doesnot create a "release" folder. By default it always creates the "debug" folder and dumps all the binaries.rvOrwO}rxO(jjsOjjqOubaubji)ryO}rzO(jXBy tweaking the common.bld, release folder can be made and hence the the IPC - qmssIpcBenchmark project can be built in release mode.r{OjlKjjeOjjJjjj}r|O(j]j]j]j]j]ujMqjhj]r}OjXBy tweaking the common.bld, release folder can be made and hence the the IPC - qmssIpcBenchmark project can be built in release mode.r~OrO}rO(jj{OjjyOubaubji)rO}rO(jX!**How to change the Common.bld:**rOjlKjjeOjjJjjj}rO(j]j]j]j]j]ujMrjhj]rOj)rO}rO(jjOj}rO(j]j]j]j]j]ujjOj]rOjXHow to change the Common.bld:rOrO}rO(jUjjOubajjubaubji)rO}rO(jX1. Go to C:\ti\ipc_3_00_xx_xx\packages\ti\sdo\ipc\build\Common.bld ( Note: Go to the IPC version you use for building the transport library. Here, it refers to IPC version : 3.00.4.29)jlKjjeOjjJjjj}rO(j]j]j]j]j]ujMujhj]rOjX1. Go to C:tiipc_3_00_xx_xxpackagestisdoipcbuildCommon.bld ( Note: Go to the IPC version you use for building the transport library. Here, it refers to IPC version : 3.00.4.29)rOrO}rO(jX1. Go to C:\ti\ipc_3_00_xx_xx\packages\ti\sdo\ipc\build\Common.bld ( Note: Go to the IPC version you use for building the transport library. Here, it refers to IPC version : 3.00.4.29)jjOubaubji)rO}rO(jX 2. ModifyrOjlKjjeOjjJjjj}rO(j]j]j]j]j]ujMvjhj]rOjX 2. ModifyrOrO}rO(jjOjjOubaubji)rO}rO(jX#Line No:88 profiles[0] = "release";rOjlKjjeOjjJjjj}rO(j]j]j]j]j]ujMwjhj]rOjX#Line No:88 profiles[0] = "release";rOrO}rO(jjOjjOubaubji)rO}rO(jX-Line No: 99 var libPath = "lib/ipc/release/";rOjlKjjeOjjJjjj}rO(j]j]j]j]j]ujMxjhj]rOjX-Line No: 99 var libPath = "lib/ipc/release/";rOrO}rO(jjOjjOubaubji)rO}rO(jX3. Build with option : -mo -o3 -q -k -eo.o in config.bld of transport library located at "..\ti\pdk_C6678_1_1_2_x\packages\ti\transport\ipc\qmss\transports"jlKjjeOjjJjjj}rO(j]j]j]j]j]ujM{jhj]rOjX3. Build with option : -mo -o3 -q -k -eo.o in config.bld of transport library located at "..tipdk_C6678_1_1_2_xpackagestitransportipcqmsstransports"rOrO}rO(jX3. Build with option : -mo -o3 -q -k -eo.o in config.bld of transport library located at "..\ti\pdk_C6678_1_1_2_x\packages\ti\transport\ipc\qmss\transports"jjOubaubji)rO}rO(jX&4. Now build qmssIpcBenchmark project.rOjlKjjeOjjJjjj}rO(j]j]j]j]j]ujM|jhj]rOjX&4. Now build qmssIpcBenchmark project.rOrO}rO(jjOjjOubaubji)rO}rO(jXGScreenshot of the successful release build of qmssIpcBenchmark project.rOjlKjjeOjjJjjj}rO(j]j]j]j]j]ujM~jhj]rOjXGScreenshot of the successful release build of qmssIpcBenchmark project.rOrO}rO(jjOjjOubaubeubjR)rO}rO(jX*.. Image:: ../images/QMSSIPC_project1.png jjYKjjJjjZj}rO(UuriX#rtos/../images/QMSSIPC_project1.pngrOj]j]j]j]jX}rOU*jOsj]ujMjhj]ubjc)rO}rO(jUjjYKjjJjjfj}rO(j]j]j]j]j]ujMjhj]rOji)rO}rO(jUjlKjjOjjJjjj}rO(j]j]j]j]j]ujKjhj]ubaubjhK)rO}rO(jXoQ: How to re-build the IPC - QMSS transport library and generate “ti.transport.ipc.qmss.transports.ae66” ?rOjjYKjjJjjlKj}rO(j]rOUcq-how-to-re-build-the-ipc-qmss-transport-library-and-generate-ti-transport-ipc-qmss-transports-ae66rOaj]j]j]j]rOjaujNjhj]rOjXoQ: How to re-build the IPC - QMSS transport library and generate “ti.transport.ipc.qmss.transports.ae66” ?rOrO}rO(jjOjjOubaubj)rO}rO(jX**Ans:**rOjjYKjjJjjj}rO(j]j]j]j]j]ujMjhj]rOj)rO}rO(jjOj}rO(j]j]j]j]j]ujjOj]rOjXAns:rOrO}rO(jUjjOubajjubaubj)rO}rO(jXgAfter installing PDK, go to path “~\ti\pdk_C6678_1_1_2_x\packages\ti\transport\ipc\qmss\transports”jjYKjjJjjj}rO(j]j]j]j]j]ujMjhj]rOjX_After installing PDK, go to path “~tipdk_C6678_1_1_2_xpackagestitransportipcqmsstransports”rOrO}rO(jXgAfter installing PDK, go to path “~\ti\pdk_C6678_1_1_2_x\packages\ti\transport\ipc\qmss\transports”jjOubaubj)rO}rO(jX1. [Optional - Required for debug single stepping] Modify the transports config.bld file C66LE/BE.ccOpts.prefix to remove optimization and add symbolic debugrOjjYKjjJjjj}rO(j]j]j]j]j]ujMjhj]rOjX1. [Optional - Required for debug single stepping] Modify the transports config.bld file C66LE/BE.ccOpts.prefix to remove optimization and add symbolic debugrOrO}rO(jjOjjOubaubj)rO}rO(jX4From: "-mo -o3 -q -k -eo.o" To: "-mo -g -q -k -eo.o"jjYKjjJjjj}rO(j@jAj]j]j]j]j]ujMjhj]rOjX4From: "-mo -o3 -q -k -eo.o" To: "-mo -g -q -k -eo.o"rOrO}rO(jUjjOubaubj)rO}rO(jX2. From a command prompt navigate to the pdk\packages\ti\transport\ipc\(qmss or srio) directory 3 Configure the XDCPATH environment variable with the BIOS and IPC install locations:jjYKjjJjjj}rO(j]j]j]j]j]ujMjhj]rOjX2. From a command prompt navigate to the pdkpackagestitransportipc(qmss or srio) directory 3 Configure the XDCPATH environment variable with the BIOS and IPC install locations:rPrP}rP(jX2. From a command prompt navigate to the pdk\packages\ti\transport\ipc\(qmss or srio) directory 3 Configure the XDCPATH environment variable with the BIOS and IPC install locations:jjOubaubj)rP}rP(jX`set XDCPATH=c:\ti\bios_w_xx_yy_zz\packages\ set XDCPATH=%XDCPATH%;c:\ti\ipc_w_xx_yy_zz\packages\jjYKjjJjjj}rP(j@jAj]j]j]j]j]ujMjhj]rPjX`set XDCPATH=c:\ti\bios_w_xx_yy_zz\packages\ set XDCPATH=%XDCPATH%;c:\ti\ipc_w_xx_yy_zz\packages\rPrP}r P(jUjjPubaubj)r P}r P(jX4 Configure the XDCCGROOT environment variable with the compiler install path (Using CGT 7.2.4 installed as part of CCS as an example)r PjjYKjjJjjj}r P(j]j]j]j]j]ujMjhj]rPjX4 Configure the XDCCGROOT environment variable with the compiler install path (Using CGT 7.2.4 installed as part of CCS as an example)rPrP}rP(jj Pjj Pubaubj)rP}rP(jX4set XDCCGROOT=c:\ti\ccsv5\tools\compiler\c6000_7.2.4jjYKjjJjjj}rP(j@jAj]j]j]j]j]ujMjhj]rPjX4set XDCCGROOT=c:\ti\ccsv5\tools\compiler\c6000_7.2.4rPrP}rP(jUjjPubaubj)rP}rP(jX'5 Add the XDC Tools to your system PATHrPjjYKjjJjjj}rP(j]j]j]j]j]ujMjhj]rPjX'5 Add the XDC Tools to your system PATHrPrP}r P(jjPjjPubaubj)r!P}r"P(jX*set PATH=%PATH%;c:\ti\xdctools_w_xx_yy_zz\jjYKjjJjjj}r#P(j@jAj]j]j]j]j]ujMjhj]r$PjX*set PATH=%PATH%;c:\ti\xdctools_w_xx_yy_zz\r%Pr&P}r'P(jUjj!Pubaubj)r(P}r)P(jX6 Clean the transportr*PjjYKjjJjjj}r+P(j]j]j]j]j]ujMjhj]r,PjX6 Clean the transportr-Pr.P}r/P(jj*Pjj(Pubaubj)r0P}r1P(jX>xdc clean -PR .jjYKjjJjjj}r2P(j@jAj]j]j]j]j]ujMjhj]r3PjX>xdc clean -PR .r4Pr5P}r6P(jUjj0Pubaubj)r7P}r8P(jX7 Build the transportr9PjjYKjjJjjj}r:P(j]j]j]j]j]ujMjhj]r;PjX7 Build the transportrP(jj9Pjj7Pubaubj)r?P}r@P(jX >xdc -PR .jjYKjjJjjj}rAP(j@jAj]j]j]j]j]ujMjhj]rBPjX >xdc -PR .rCPrDP}rEP(jUjj?Pubaubj)rFP}rGP(jXIf we try this option, we should be able to build in releasemode. Note: To allow single-step debug of the IPC and BIOS source rebuild the example projects with the following command added to the example's .cfg file BIOS.libType = BIOS.LibType_Debug; <--- here.rHPjjYKjjJjjj}rIP(j]j]j]j]j]ujMjhj]rJPjXIf we try this option, we should be able to build in releasemode. Note: To allow single-step debug of the IPC and BIOS source rebuild the example projects with the following command added to the example's .cfg file BIOS.libType = BIOS.LibType_Debug; <--- here.rKPrLP}rMP(jjHPjjFPubaubjR)rNP}rOP(jX+.. Image:: ../images/Qmss_transports.png jjYKjXainternal padding after source/rtos/PDK_Platform_Software/IPC/IPC_FAQ_for_Keystone_Devices.rst.incrPPjjZj}rQP(UuriX"rtos/../images/Qmss_transports.pngrRPj]j]j]j]jX}rSPU*jRPsj]ujMjhj]ubeubeubeubj)rTP}rUP(jUjjjjjjj}rVP(j]j]j]j]rWPUipc-install-guidesrXPaj]rYPjaujKjhj]rZP(j)r[P}r\P(jXIPC Install Guidesr]PjjTPjjjjj}r^P(j]j]j]j]j]ujKjhj]r_PjXIPC Install Guidesr`PraP}rbP(jj]Pjj[Pubaubj)rcP}rdP(jXThe IPC package now comes bundled with Processor SDK RTOS and can be built using the top-level makefile located in the Processor SDK RTOS folder. These install guides have been kept here for those using older, legacy versions of IPC.rePjjTPjjjjj}rfP(j]j]j]j]j]ujKjhj]rgPjXThe IPC package now comes bundled with Processor SDK RTOS and can be built using the top-level makefile located in the Processor SDK RTOS folder. These install guides have been kept here for those using older, legacy versions of IPC.rhPriP}rjP(jjePjjcPubaubj)rkP}rlP(jUjjTPjjjjj}rmP(j]j]j]j]rnPUbios-install-guideroPaj]rpPh)aujKjhj]rqP(j)rrP}rsP(jXBIOS Install GuidertPjjkPjjjjj}ruP(j]j]j]j]j]ujKjhj]rvPjXBIOS Install GuiderwPrxP}ryP(jjtPjjrPubaubj7)rzP}r{P(jX>http://processors.wiki.ti.com/index.php/IPC_Install_Guide_BIOSjjkPjj:XDsource/rtos/PDK_Platform_Software/IPC/IPC_Install_Guide_BIOS.rst.incr|Pr}P}r~Pbjj>j}rP(j@jAj]j]j]j]j]ujKjhj]rPjX>http://processors.wiki.ti.com/index.php/IPC_Install_Guide_BIOSrPrP}rP(jUjjzPubaubj)rP}rP(jUjKjjkPjj}Pjjj}rP(j]rPX introductionrPaj]j]j]rPUid47rPaj]ujKjhj]rP(j)rP}rP(jX IntroductionrPjjPjj}Pjjj}rP(j]j]j]j]j]ujKjhj]rPjX IntroductionrPrP}rP(jjPjjPubaubj)rP}rP(jXInter/Intra Processor Communication (IPC) is a product designed to enable communication between processors in a multi-processor environment. Features of IPC include message passing, multi-processor gates, shared memory primitives, and more.rPjjPjj}Pjjj}rP(j]j]j]j]j]ujKjhj]rPjXInter/Intra Processor Communication (IPC) is a product designed to enable communication between processors in a multi-processor environment. Features of IPC include message passing, multi-processor gates, shared memory primitives, and more.rPrP}rP(jjPjjPubaubj)rP}rP(jX<IPC is designed for use with processors running SYS/BIOS applications. This is typically an ARM or DSP. IPC includes support for High Level Operating Systems (HLOS) like Linux, as well as the SYS/BIOS RTOS. The breadth of IPC features supported in an HLOS environment is reduced in an effort to simplify the product.rPjjPjj}Pjjj}rP(j]j]j]j]j]ujK jhj]rPjX<IPC is designed for use with processors running SYS/BIOS applications. This is typically an ARM or DSP. IPC includes support for High Level Operating Systems (HLOS) like Linux, as well as the SYS/BIOS RTOS. The breadth of IPC features supported in an HLOS environment is reduced in an effort to simplify the product.rPrP}rP(jjPjjPubaubeubj)rP}rP(jUjKjjkPjj}Pjjj}rP(j]rPXinstallrPaj]j]j]rPUinstallrPaj]ujKjhj]rP(j)rP}rP(jXInstallrPjjPjj}Pjjj}rP(j]j]j]j]j]ujKjhj]rPjXInstallrPrP}rP(jjPjjPubaubj)rP}rP(jXhIPC is often distributed and installed within a larger SDK. In those cases, no installation is required.rPjjPjj}Pjjj}rP(j]j]j]j]j]ujKjhj]rPjXhIPC is often distributed and installed within a larger SDK. In those cases, no installation is required.rPrP}rP(jjPjjPubaubj)rP}rP(jXOutside of an SDK, `IPC can be downloaded here `__, and is released as a zip file. To install, simply extract the file.jjPjj}Pjjj}rP(j]j]j]j]j]ujKjhj]rP(jXOutside of an SDK, rPrP}rP(jXOutside of an SDK, jjPubj)rP}rP(jXr`IPC can be downloaded here `__j}rP(UnameXIPC can be downloaded herejXQhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/index.htmlj]j]j]j]j]ujjPj]rPjXIPC can be downloaded hererPrP}rP(jUjjPubajjubjXE, and is released as a zip file. To install, simply extract the file.rPrP}rP(jXE, and is released as a zip file. To install, simply extract the file.jjPubeubj)rP}rP(jX"buildhost$ unzip ipc_.zipjjPjj}Pjjj}rP(j@jAj]j]j]j]j]ujM-jhj]rPjX"buildhost$ unzip ipc_.ziprPrP}rP(jUjjPubaubj)rP}rP(jX}This will extract the IPC product in a directory with its product name and version information (e.g. **c:/ti/ipc_**)jjPjj}Pjjj}rP(j]j]j]j]j]ujKjhj]rP(jXeThis will extract the IPC product in a directory with its product name and version information (e.g. rPrP}rP(jXeThis will extract the IPC product in a directory with its product name and version information (e.g. jjPubj)rP}rP(jX**c:/ti/ipc_**j}rP(j]j]j]j]j]ujjPj]rPjXc:/ti/ipc_rPrP}rP(jUjjPubajjubjX)rP}rP(jX)jjPubeubj)rP}rP(jXE- This document assumes the IPC install path to be the user's home directory on a Linux host machine (**/home/**) or the user's main drive on a Windows host machine (**C:\\**). The variable **IPC_INSTALL_DIR** will be used throughout the document. If IPC was installed at a different location, make appropriate changes to commands. - Some customers find value in archiving the released sources in a configuration management system. This can help in identifying any changes made to the original sources - often useful when updating to newer releases.jjPjNjjj}rP(j]j]j]j]j]ujNjhj]rPjt)rP}rP(jUj}rP(jyX-j]j]j]j]j]ujjPj]rP(j{)rP}rP(jXOThis document assumes the IPC install path to be the user's home directory on a Linux host machine (**/home/**) or the user's main drive on a Windows host machine (**C:\\**). The variable **IPC_INSTALL_DIR** will be used throughout the document. If IPC was installed at a different location, make appropriate changes to commands.j}rP(j]j]j]j]j]ujjPj]rPj)rP}rP(jXOThis document assumes the IPC install path to be the user's home directory on a Linux host machine (**/home/**) or the user's main drive on a Windows host machine (**C:\\**). The variable **IPC_INSTALL_DIR** will be used throughout the document. If IPC was installed at a different location, make appropriate changes to commands.jjPjj}Pjjj}rP(j]j]j]j]j]ujK#j]rP(jXdThis document assumes the IPC install path to be the user's home directory on a Linux host machine (rPrP}rP(jXdThis document assumes the IPC install path to be the user's home directory on a Linux host machine (jjPubj)rP}rP(jX**/home/**j}rP(j]j]j]j]j]ujjPj]rPjX /home/rPrP}rP(jUjjPubajjubjX6) or the user's main drive on a Windows host machine (rPrP}rQ(jX6) or the user's main drive on a Windows host machine (jjPubj)rQ}rQ(jX**C:\\**j}rQ(j]j]j]j]j]ujjPj]rQjXC:\rQrQ}rQ(jUjjQubajjubjX). The variable rQr Q}r Q(jX). The variable jjPubj)r Q}r Q(jX**IPC_INSTALL_DIR**j}r Q(j]j]j]j]j]ujjPj]rQjXIPC_INSTALL_DIRrQrQ}rQ(jUjj QubajjubjXz will be used throughout the document. If IPC was installed at a different location, make appropriate changes to commands.rQrQ}rQ(jXz will be used throughout the document. If IPC was installed at a different location, make appropriate changes to commands.jjPubeubajjubj{)rQ}rQ(jXSome customers find value in archiving the released sources in a configuration management system. This can help in identifying any changes made to the original sources - often useful when updating to newer releases.j}rQ(j]j]j]j]j]ujjPj]rQj)rQ}rQ(jXSome customers find value in archiving the released sources in a configuration management system. This can help in identifying any changes made to the original sources - often useful when updating to newer releases.rQjjQjj}Pjjj}rQ(j]j]j]j]j]ujK)j]rQjXSome customers find value in archiving the released sources in a configuration management system. This can help in identifying any changes made to the original sources - often useful when updating to newer releases.rQrQ}r Q(jjQjjQubaubajjubejjwubaubeubj)r!Q}r"Q(jUjKjjkPjj}Pjjj}r#Q(j]r$QXbuildr%Qaj]j]j]r&QUid48r'Qaj]ujK/jhj]r(Q(j)r)Q}r*Q(jXBuildr+Qjj!Qjj}Pjjj}r,Q(j]j]j]j]j]ujK/jhj]r-QjXBuildr.Qr/Q}r0Q(jj+Qjj)Qubaubj)r1Q}r2Q(jXThe IPC product often comes with prebuilt libraries, so rebuilding them isn't necessary. The IPC product downloads contain prebuilt libraries, and when provided with an SDK, IPC is typically rebuilt to contain only libraries appropriate for the SDK.r3Qjj!Qjj}Pjjj}r4Q(j]j]j]j]j]ujK1jhj]r5QjXThe IPC product often comes with prebuilt libraries, so rebuilding them isn't necessary. The IPC product downloads contain prebuilt libraries, and when provided with an SDK, IPC is typically rebuilt to contain only libraries appropriate for the SDK.r6Qr7Q}r8Q(jj3Qjj1Qubaubj)r9Q}r:Q(jXHowever, if you want to rebuild its libraries, IPC provides GNU makefile(s) at the base of the product. This section describes the steps required to rebuild the IPC libraries.r;Qjj!Qjj}Pjjj}rQr?Q}r@Q(jj;Qjj9Qubaubj)rAQ}rBQ(jXGNU make version 3.81 or greater is required. The XDC tools (provided with most SDKs and CCS distributions) includes a pre-compiled version of GNU make 3.81 in $(XDC_INSTALL_DIR)/gmake.jj!Qjj}Pjjj}rCQ(j]j]j]j]j]ujNjhj]rDQj)rEQ}rFQ(jXGNU make version 3.81 or greater is required. The XDC tools (provided with most SDKs and CCS distributions) includes a pre-compiled version of GNU make 3.81 in $(XDC_INSTALL_DIR)/gmake.rGQjjAQjj}Pjjj}rHQ(j]j]j]j]j]ujK;j]rIQjXGNU make version 3.81 or greater is required. The XDC tools (provided with most SDKs and CCS distributions) includes a pre-compiled version of GNU make 3.81 in $(XDC_INSTALL_DIR)/gmake.rJQrKQ}rLQ(jjGQjjEQubaubaubj)rMQ}rNQ(jUjKjj!Qjj}Pjjj}rOQ(j]rPQX products.makrQQaj]j]j]rRQU products-makrSQaj]ujK@jhj]rTQ(j)rUQ}rVQ(jX products.makrWQjjMQjj}Pjjj}rXQ(j]j]j]j]j]ujK@jhj]rYQjX products.makrZQr[Q}r\Q(jjWQjjUQubaubj)r]Q}r^Q(jXIPC contains a **products.mak** file at the root of the product that specifies the necessary paths and options to build IPC for the various OS support.jjMQjj}Pjjj}r_Q(j]j]j]j]j]ujKBjhj]r`Q(jXIPC contains a raQrbQ}rcQ(jXIPC contains a jj]Qubj)rdQ}reQ(jX**products.mak**j}rfQ(j]j]j]j]j]ujj]Qj]rgQjX products.makrhQriQ}rjQ(jUjjdQubajjubjXx file at the root of the product that specifies the necessary paths and options to build IPC for the various OS support.rkQrlQ}rmQ(jXx file at the root of the product that specifies the necessary paths and options to build IPC for the various OS support.jj]Qubeubj)rnQ}roQ(jX6Edit **products.mak** and set the following variables:rpQjjMQjj}Pjjj}rqQ(j]j]j]j]j]ujKFjhj]rrQ(jXEdit rsQrtQ}ruQ(jXEdit jjnQubj)rvQ}rwQ(jX**products.mak**j}rxQ(j]j]j]j]j]ujjnQj]ryQjX products.makrzQr{Q}r|Q(jUjjvQubajjubjX! and set the following variables:r}Qr~Q}rQ(jX! and set the following variables:jjnQubeubj)rQ}rQ(jXYPlease make sure the complete path is specified. (e.g) Don't use ~ in the path specified.rQjjMQjj}Pjjj}rQ(j]j]j]j]j]ujNjhj]rQj)rQ}rQ(jjQjjQjj}Pjjj}rQ(j]j]j]j]j]ujKIj]rQjXYPlease make sure the complete path is specified. (e.g) Don't use ~ in the path specified.rQrQ}rQ(jjQjjQubaubaubjt)rQ}rQ(jUjjMQjj}Pjjwj}rQ(jyX-j]j]j]j]j]ujKKjhj]rQ(j{)rQ}rQ(jX8**XDC_INSTALL_DIR** - Path to TI's XDCTools installationrQjjQjj}Pjjj}rQ(j]j]j]j]j]ujNjhj]rQj)rQ}rQ(jjQjjQjj}Pjjj}rQ(j]j]j]j]j]ujKKj]rQ(j)rQ}rQ(jX**XDC_INSTALL_DIR**j}rQ(j]j]j]j]j]ujjQj]rQjXXDC_INSTALL_DIRrQrQ}rQ(jUjjQubajjubjX% - Path to TI's XDCTools installationrQrQ}rQ(jX% - Path to TI's XDCTools installationjjQubeubaubj{)rQ}rQ(jX9**BIOS_INSTALL_DIR** - Path to TI's SYS/BIOS installationrQjjQjj}Pjjj}rQ(j]j]j]j]j]ujNjhj]rQj)rQ}rQ(jjQjjQjj}Pjjj}rQ(j]j]j]j]j]ujKLj]rQ(j)rQ}rQ(jX**BIOS_INSTALL_DIR**j}rQ(j]j]j]j]j]ujjQj]rQjXBIOS_INSTALL_DIRrQrQ}rQ(jUjjQubajjubjX% - Path to TI's SYS/BIOS installationrQrQ}rQ(jX% - Path to TI's SYS/BIOS installationjjQubeubaubj{)rQ}rQ(jX**ti.targets.** - Path to TI toolchain for the device. - Set only the variables to the targets your device supports to minimize build time. jjQjNjjj}rQ(j]j]j]j]j]ujNjhj]rQ(j)rQ}rQ(jXU**ti.targets.** - Path to TI toolchain for the device.jjQjj}Pjjj}rQ(j]j]j]j]j]ujKMj]rQ(j)rQ}rQ(jX.**ti.targets.**j}rQ(j]j]j]j]j]ujjQj]rQjX*ti.targets.rQrQ}rQ(jUjjQubajjubjX' - Path to TI toolchain for the device.rQrQ}rQ(jX' - Path to TI toolchain for the device.jjQubeubjt)rQ}rQ(jUj}rQ(jyX-j]j]j]j]j]ujjQj]rQj{)rQ}rQ(jXSSet only the variables to the targets your device supports to minimize build time. j}rQ(j]j]j]j]j]ujjQj]rQj)rQ}rQ(jXRSet only the variables to the targets your device supports to minimize build time.rQjjQjj}Pjjj}rQ(j]j]j]j]j]ujKPj]rQjXRSet only the variables to the targets your device supports to minimize build time.rQrQ}rQ(jjQjjQubaubajjubajjwubeubj{)rQ}rQ(jX**gnu.targets.arm.** - Path to GNU toolchain for the device. - Set only the variables to the targets your device supports to minimize build time. jjQjNjjj}rQ(j]j]j]j]j]ujNjhj]rQ(j)rQ}rQ(jX[**gnu.targets.arm.** - Path to GNU toolchain for the device.jjQjj}Pjjj}rQ(j]j]j]j]j]ujKSj]rQ(j)rQ}rQ(jX3**gnu.targets.arm.**j}rQ(j]j]j]j]j]ujjQj]rQjX/gnu.targets.arm.rQrQ}rQ(jUjjQubajjubjX( - Path to GNU toolchain for the device.rQrQ}rQ(jX( - Path to GNU toolchain for the device.jjQubeubjt)rQ}rQ(jUj}rQ(jyX-j]j]j]j]j]ujjQj]rQj{)rQ}rQ(jXSSet only the variables to the targets your device supports to minimize build time. j}rQ(j]j]j]j]j]ujjQj]rQj)rQ}rQ(jXRSet only the variables to the targets your device supports to minimize build time.rQjjQjj}Pjjj}rQ(j]j]j]j]j]ujKVj]rQjXRSet only the variables to the targets your device supports to minimize build time.rQrQ}rQ(jjQjjQubaubajjubajjwubeubj{)rQ}rQ(jX**PLATFORM** - (Optional) platform for which to build executables - Introduced in IPC 3.10. Prior releases build executables for **all** platforms based on that targets/toolchains set above - If not set, only libraries will be built (not executables) jjQjNjjj}rQ(j]j]j]j]j]ujNjhj]rQ(j)rQ}rQ(jXA**PLATFORM** - (Optional) platform for which to build executablesjjQjj}Pjjj}rR(j]j]j]j]j]ujKYj]rR(j)rR}rR(jX **PLATFORM**j}rR(j]j]j]j]j]ujjQj]rRjXPLATFORMrRrR}rR(jUjjRubajjubjX5 - (Optional) platform for which to build executablesr Rr R}r R(jX5 - (Optional) platform for which to build executablesjjQubeubjt)r R}r R(jUj}rR(jyX-j]j]j]j]j]ujjQj]rR(j{)rR}rR(jXyIntroduced in IPC 3.10. Prior releases build executables for **all** platforms based on that targets/toolchains set abovej}rR(j]j]j]j]j]ujj Rj]rRj)rR}rR(jXyIntroduced in IPC 3.10. Prior releases build executables for **all** platforms based on that targets/toolchains set abovejjRjj}Pjjj}rR(j]j]j]j]j]ujK[j]rR(jX=Introduced in IPC 3.10. Prior releases build executables for rRrR}rR(jX=Introduced in IPC 3.10. Prior releases build executables for jjRubj)rR}rR(jX**all**j}rR(j]j]j]j]j]ujjRj]rRjXallrRr R}r!R(jUjjRubajjubjX5 platforms based on that targets/toolchains set abover"Rr#R}r$R(jX5 platforms based on that targets/toolchains set abovejjRubeubajjubj{)r%R}r&R(jX;If not set, only libraries will be built (not executables) j}r'R(j]j]j]j]j]ujj Rj]r(Rj)r)R}r*R(jX:If not set, only libraries will be built (not executables)r+Rjj%Rjj}Pjjj}r,R(j]j]j]j]j]ujK]j]r-RjX:If not set, only libraries will be built (not executables)r.Rr/R}r0R(jj+Rjj)Rubaubajjubejjwubeubeubj)r1R}r2R(jXbThe versions used during validation can be found in the IPC Release Notes provided in the product.jjMQjj}Pjjj}r3R(j]j]j]j]j]ujNjhj]r4Rj)r5R}r6R(jXbThe versions used during validation can be found in the IPC Release Notes provided in the product.r7Rjj1Rjj}Pjjj}r8R(j]j]j]j]j]ujK`j]r9RjXbThe versions used during validation can be found in the IPC Release Notes provided in the product.r:Rr;R}rR(jUjKjj!Qjj}Pjjj}r?R(j]r@RX ipc-bios.makrARaj]j]j]rBRU ipc-bios-makrCRaj]ujKdjhj]rDR(j)rER}rFR(jX ipc-bios.makrGRjj=Rjj}Pjjj}rHR(j]j]j]j]j]ujKdjhj]rIRjX ipc-bios.makrJRrKR}rLR(jjGRjjERubaubj)rMR}rNR(jX^IPC is built with a GNU makefile. After editing **products.mak**, issue the following command:jj=Rjj}Pjjj}rOR(j]j]j]j]j]ujKfjhj]rPR(jX0IPC is built with a GNU makefile. After editing rQRrRR}rSR(jX0IPC is built with a GNU makefile. After editing jjMRubj)rTR}rUR(jX**products.mak**j}rVR(j]j]j]j]j]ujjMRj]rWRjX products.makrXRrYR}rZR(jUjjTRubajjubjX, issue the following command:r[Rr\R}r]R(jX, issue the following command:jjMRubeubj)r^R}r_R(jX$ make -f ipc-bios.mak alljj=Rjj}Pjjj}r`R(j@jAj]j]j]j]j]ujM{jhj]raRjX$ make -f ipc-bios.mak allrbRrcR}rdR(jUjj^Rubaubj)reR}rfR(jXLBased on the number of targets you're building for, this may take some time.rgRjj=Rjj}Pjjj}rhR(j]j]j]j]j]ujKmjhj]riRjXLBased on the number of targets you're building for, this may take some time.rjRrkR}rlR(jjgRjjeRubaubeubeubj)rmR}rnR(jUjKjjkPjj}Pjjj}roR(j]rpRXexamplesrqRaj]j]j]rrRUexamplesrsRaj]ujKqjhj]rtR(j)ruR}rvR(jXExamplesrwRjjmRjj}Pjjj}rxR(j]j]j]j]j]ujKqjhj]ryRjXExamplesrzRr{R}r|R(jjwRjjuRubaubj)r}R}r~R(jX!The IPC product contains an examples/archive directory with device-specific examples. Once identifying your device, the examples can be unzipped anywhere on your build host. Typically once unzipped, the user edits the example's individual **products.mak** file and simply invokes **make**.jjmRjj}Pjjj}rR(j]j]j]j]j]ujKsjhj]rR(jXThe IPC product contains an examples/archive directory with device-specific examples. Once identifying your device, the examples can be unzipped anywhere on your build host. Typically once unzipped, the user edits the example's individual rRrR}rR(jXThe IPC product contains an examples/archive directory with device-specific examples. Once identifying your device, the examples can be unzipped anywhere on your build host. Typically once unzipped, the user edits the example's individual jj}Rubj)rR}rR(jX**products.mak**j}rR(j]j]j]j]j]ujj}Rj]rRjX products.makrRrR}rR(jUjjRubajjubjX file and simply invokes rRrR}rR(jX file and simply invokes jj}Rubj)rR}rR(jX**make**j}rR(j]j]j]j]j]ujj}Rj]rRjXmakerRrR}rR(jUjjRubajjubjX.rR}rR(jX.jj}Rubeubj)rR}rR(jXA common place to unzip the examples is into the **IPC_INSTALL_DIR/examples/** directory. Each example's **products.mak** file is smart enough to look up two directories (in this case, into **IPC_INSTALL_DIR**) for a master **products.mak** file, and if found it uses those variables. This technique enables users to set the dependency variables in one place, namely **IPC_INSTALL_DIR/products.mak**.jjmRjj}Pjjj}rR(j]j]j]j]j]ujNjhj]rRj)rR}rR(jXA common place to unzip the examples is into the **IPC_INSTALL_DIR/examples/** directory. Each example's **products.mak** file is smart enough to look up two directories (in this case, into **IPC_INSTALL_DIR**) for a master **products.mak** file, and if found it uses those variables. This technique enables users to set the dependency variables in one place, namely **IPC_INSTALL_DIR/products.mak**.jjRjj}Pjjj}rR(j]j]j]j]j]ujKzj]rR(jX1A common place to unzip the examples is into the rRrR}rR(jX1A common place to unzip the examples is into the jjRubj)rR}rR(jX**IPC_INSTALL_DIR/examples/**j}rR(j]j]j]j]j]ujjRj]rRjXIPC_INSTALL_DIR/examples/rRrR}rR(jUjjRubajjubjX directory. Each example's rRrR}rR(jX directory. Each example's jjRubj)rR}rR(jX**products.mak**j}rR(j]j]j]j]j]ujjRj]rRjX products.makrRrR}rR(jUjjRubajjubjXE file is smart enough to look up two directories (in this case, into rRrR}rR(jXE file is smart enough to look up two directories (in this case, into jjRubj)rR}rR(jX**IPC_INSTALL_DIR**j}rR(j]j]j]j]j]ujjRj]rRjXIPC_INSTALL_DIRrRrR}rR(jUjjRubajjubjX) for a master rRrR}rR(jX) for a master jjRubj)rR}rR(jX**products.mak**j}rR(j]j]j]j]j]ujjRj]rRjX products.makrRrR}rR(jUjjRubajjubjX file, and if found it uses those variables. This technique enables users to set the dependency variables in one place, namely rRrR}rR(jX file, and if found it uses those variables. This technique enables users to set the dependency variables in one place, namely jjRubj)rR}rR(jX **IPC_INSTALL_DIR/products.mak**j}rR(j]j]j]j]j]ujjRj]rRjXIPC_INSTALL_DIR/products.makrRrR}rR(jUjjRubajjubjX.rR}rR(jX.jjRubeubaubj)rR}rR(jXEEach example contains a **readme.txt** with example-specific details.rRjjmRjj}Pjjj}rR(j]j]j]j]j]ujKjhj]rR(jXEach example contains a rRrR}rR(jXEach example contains a jjRubj)rR}rR(jX**readme.txt**j}rR(j]j]j]j]j]ujjRj]rRjX readme.txtrRrR}rR(jUjjRubajjubjX with example-specific details.rRrR}rR(jX with example-specific details.jjRubeubeubj)rR}rR(jUjKjjkPjj}Pjjj}rR(j]rRXsee alsorRaj]j]j]rRUsee-alsorRaj]ujKjhj]rR(j)rR}rR(jXSee AlsorRjjRjj}Pjjj}rR(j]j]j]j]j]ujKjhj]rRjXSee AlsorRrR}rR(jjRjjRubaubjt)rR}rR(jUjjRjj}Pjjwj}rR(jyX-j]j]j]j]j]ujKjhj]rR(j{)rR}rR(jX8`IPC 3.x `__rRjjRjj}Pjjj}rR(j]j]j]j]j]ujNjhj]rRj)rR}rR(jjRjjRjj}Pjjj}rS(j]j]j]j]j]ujKj]rSj)rS}rS(jjRj}rS(UnameXIPC 3.xjX*index_Foundational_Components.html#ipc-3-xj]j]j]j]j]ujjRj]rSjXIPC 3.xrSrS}rS(jUjjSubajjubaubaubj{)r S}r S(jXG`IPC Users Guide `__r SjjRjj}Pjjj}r S(j]j]j]j]j]ujNjhj]r Sj)rS}rS(jj Sjj Sjj}Pjjj}rS(j]j]j]j]j]ujKj]rSj)rS}rS(jj Sj}rS(UnameXIPC Users GuidejX1index_Foundational_Components.html#ipc-user-guidej]j]j]j]j]ujjSj]rSjXIPC Users GuiderSrS}rS(jUjjSubajjubaubaubj{)rS}rS(jX<`IPC 3.x FAQ `__rSjjRjj}Pjjj}rS(j]j]j]j]j]ujNjhj]rSj)rS}rS(jjSjjSjj}Pjjj}r S(j]j]j]j]j]ujKj]r!Sj)r"S}r#S(jjSj}r$S(UnameX IPC 3.x FAQjX*index_Foundational_Components.html#ipc-faqj]j]j]j]j]ujjSj]r%SjX IPC 3.x FAQr&Sr'S}r(S(jUjj"Subajjubaubaubj{)r)S}r*S(jXT`IPC Install Guide Linux `__r+SjjRjj}Pjjj}r,S(j]j]j]j]j]ujNjhj]r-Sj)r.S}r/S(jj+Sjj)Sjj}Pjjj}r0S(j]j]j]j]j]ujKj]r1Sj)r2S}r3S(jj+Sj}r4S(UnameXIPC Install Guide LinuxjX6index_Foundational_Components.html#linux-install-guidej]j]j]j]j]ujj.Sj]r5SjXIPC Install Guide Linuxr6Sr7S}r8S(jUjj2Subajjubaubaubj{)r9S}r:S(jXS`IPC Install Guide QNX `__ jjRjX[internal padding after source/rtos/PDK_Platform_Software/IPC/IPC_Install_Guide_BIOS.rst.incr;Sjjj}rS}r?S(jXP`IPC Install Guide QNX `__r@Sjj9Sjj}Pjjj}rAS(j]j]j]j]j]ujKj]rBSj)rCS}rDS(jj@Sj}rES(UnameXIPC Install Guide QNXjX4index_Foundational_Components.html#qnx-install-guidej]j]j]j]j]ujj>Sj]rFSjXIPC Install Guide QNXrGSrHS}rIS(jUjjCSubajjubaubaubeubeubeubj)rJS}rKS(jUjjTPjjjjj}rLS(j]j]j]j]rMSUlinux-install-guiderNSaj]rOSheaujKjhj]rPS(j)rQS}rRS(jXLinux Install GuiderSSjjJSjjjjj}rTS(j]j]j]j]j]ujKjhj]rUSjXLinux Install GuiderVSrWS}rXS(jjSSjjQSubaubj7)rYS}rZS(jX?http://processors.wiki.ti.com/index.php/IPC_Install_Guide_LinuxjjJSjj:XEsource/rtos/PDK_Platform_Software/IPC/IPC_Install_Guide_Linux.rst.incr[Sr\S}r]Sbjj>j}r^S(j@jAj]j]j]j]j]ujKjhj]r_SjX?http://processors.wiki.ti.com/index.php/IPC_Install_Guide_Linuxr`SraS}rbS(jUjjYSubaubj)rcS}rdS(jUjKjjJSjj\Sjjj}reS(j]rfSX introductionrgSaj]j]j]rhSUid49riSaj]ujKjhj]rjS(j)rkS}rlS(jX IntroductionrmSjjcSjj\Sjjj}rnS(j]j]j]j]j]ujKjhj]roSjX IntroductionrpSrqS}rrS(jjmSjjkSubaubj)rsS}rtS(jXInter/Intra Processor Communication (IPC) is a product designed to enable communication between processors in a multi-processor environment. Features of IPC include message passing, multi-processor gates, shared memory primitives, and more.ruSjjcSjj\Sjjj}rvS(j]j]j]j]j]ujKjhj]rwSjXInter/Intra Processor Communication (IPC) is a product designed to enable communication between processors in a multi-processor environment. Features of IPC include message passing, multi-processor gates, shared memory primitives, and more.rxSryS}rzS(jjuSjjsSubaubj)r{S}r|S(jX<IPC is designed for use with processors running SYS/BIOS applications. This is typically an ARM or DSP. IPC includes support for High Level Operating Systems (HLOS) like Linux, as well as the SYS/BIOS RTOS. The breadth of IPC features supported in an HLOS environment is reduced in an effort to simplify the product.r}SjjcSjj\Sjjj}r~S(j]j]j]j]j]ujK jhj]rSjX<IPC is designed for use with processors running SYS/BIOS applications. This is typically an ARM or DSP. IPC includes support for High Level Operating Systems (HLOS) like Linux, as well as the SYS/BIOS RTOS. The breadth of IPC features supported in an HLOS environment is reduced in an effort to simplify the product.rSrS}rS(jj}Sjj{Subaubeubj)rS}rS(jUjKjjJSjj\Sjjj}rS(j]rSjPaj]j]j]rSUid50rSaj]ujKjhj]rS(j)rS}rS(jXInstallrSjjSjj\Sjjj}rS(j]j]j]j]j]ujKjhj]rSjXInstallrSrS}rS(jjSjjSubaubj)rS}rS(jXhIPC is often distributed and installed within a larger SDK. In those cases, no installation is required.rSjjSjj\Sjjj}rS(j]j]j]j]j]ujKjhj]rSjXhIPC is often distributed and installed within a larger SDK. In those cases, no installation is required.rSrS}rS(jjSjjSubaubj)rS}rS(jXOutside of an SDK, `IPC can be downloaded here `__, and is released as a zip file. To install, simply extract the file.jjSjj\Sjjj}rS(j]j]j]j]j]ujKjhj]rS(jXOutside of an SDK, rSrS}rS(jXOutside of an SDK, jjSubj)rS}rS(jXr`IPC can be downloaded here `__j}rS(UnameXIPC can be downloaded herejXQhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/index.htmlj]j]j]j]j]ujjSj]rSjXIPC can be downloaded hererSrS}rS(jUjjSubajjubjXE, and is released as a zip file. To install, simply extract the file.rSrS}rS(jXE, and is released as a zip file. To install, simply extract the file.jjSubeubj)rS}rS(jX"buildhost$ unzip ipc_.zipjjSjj\Sjjj}rS(j@jAj]j]j]j]j]ujMjhj]rSjX"buildhost$ unzip ipc_.ziprSrS}rS(jUjjSubaubj)rS}rS(jX}This will extract the IPC product in a directory with its product name and version information (e.g. **c:/ti/ipc_**)jjSjj\Sjjj}rS(j]j]j]j]j]ujKjhj]rS(jXeThis will extract the IPC product in a directory with its product name and version information (e.g. rSrS}rS(jXeThis will extract the IPC product in a directory with its product name and version information (e.g. jjSubj)rS}rS(jX**c:/ti/ipc_**j}rS(j]j]j]j]j]ujjSj]rSjXc:/ti/ipc_rSrS}rS(jUjjSubajjubjX)rS}rS(jX)jjSubeubj)rS}rS(jXE- This document assumes the IPC install path to be the user's home directory on a Linux host machine (**/home/**) or the user's main drive on a Windows host machine (**C:\\**). The variable **IPC_INSTALL_DIR** will be used throughout the document. If IPC was installed at a different location, make appropriate changes to commands. - Some customers find value in archiving the released sources in a configuration management system. This can help in identifying any changes made to the original sources - often useful when updating to newer releases.jjSjNjjj}rS(j]j]j]j]j]ujNjhj]rSjt)rS}rS(jUj}rS(jyX-j]j]j]j]j]ujjSj]rS(j{)rS}rS(jXOThis document assumes the IPC install path to be the user's home directory on a Linux host machine (**/home/**) or the user's main drive on a Windows host machine (**C:\\**). The variable **IPC_INSTALL_DIR** will be used throughout the document. If IPC was installed at a different location, make appropriate changes to commands.j}rS(j]j]j]j]j]ujjSj]rSj)rS}rS(jXOThis document assumes the IPC install path to be the user's home directory on a Linux host machine (**/home/**) or the user's main drive on a Windows host machine (**C:\\**). The variable **IPC_INSTALL_DIR** will be used throughout the document. If IPC was installed at a different location, make appropriate changes to commands.jjSjj\Sjjj}rS(j]j]j]j]j]ujK$j]rS(jXdThis document assumes the IPC install path to be the user's home directory on a Linux host machine (rSrS}rS(jXdThis document assumes the IPC install path to be the user's home directory on a Linux host machine (jjSubj)rS}rS(jX**/home/**j}rS(j]j]j]j]j]ujjSj]rSjX /home/rSrS}rS(jUjjSubajjubjX6) or the user's main drive on a Windows host machine (rSrS}rS(jX6) or the user's main drive on a Windows host machine (jjSubj)rS}rS(jX**C:\\**j}rS(j]j]j]j]j]ujjSj]rSjXC:\rSrS}rS(jUjjSubajjubjX). The variable rSrS}rS(jX). The variable jjSubj)rS}rS(jX**IPC_INSTALL_DIR**j}rS(j]j]j]j]j]ujjSj]rSjXIPC_INSTALL_DIRrSrS}rS(jUjjSubajjubjXz will be used throughout the document. If IPC was installed at a different location, make appropriate changes to commands.rSrS}rS(jXz will be used throughout the document. If IPC was installed at a different location, make appropriate changes to commands.jjSubeubajjubj{)rS}rS(jXSome customers find value in archiving the released sources in a configuration management system. This can help in identifying any changes made to the original sources - often useful when updating to newer releases.j}rS(j]j]j]j]j]ujjSj]rSj)rS}rS(jXSome customers find value in archiving the released sources in a configuration management system. This can help in identifying any changes made to the original sources - often useful when updating to newer releases.rSjjSjj\Sjjj}rS(j]j]j]j]j]ujK*j]rSjXSome customers find value in archiving the released sources in a configuration management system. This can help in identifying any changes made to the original sources - often useful when updating to newer releases.rSrS}rS(jjSjjSubaubajjubejjwubaubeubj)rS}rT(jUjKjjJSjj\Sjjj}rT(j]rTXbuildrTaj]j]j]rTUid51rTaj]ujK0jhj]rT(j)rT}rT(jXBuildr TjjSjj\Sjjj}r T(j]j]j]j]j]ujK0jhj]r TjXBuildr Tr T}rT(jj TjjTubaubj)rT}rT(jXThe IPC product often comes with prebuilt SYS/BIOS-side libraries, so rebuilding them isn't necessary. The Linux-side user libraries may also be provided prebuilt, but customers often want to change the configuration (e.g. static, dynamic).rTjjSjj\Sjjj}rT(j]j]j]j]j]ujK2jhj]rTjXThe IPC product often comes with prebuilt SYS/BIOS-side libraries, so rebuilding them isn't necessary. The Linux-side user libraries may also be provided prebuilt, but customers often want to change the configuration (e.g. static, dynamic).rTrT}rT(jjTjjTubaubj)rT}rT(jXhIPC provides GNU makefile(s) to rebuild all its libraries at the base of the product, details are below.rTjjSjj\Sjjj}rT(j]j]j]j]j]ujK7jhj]rTjXhIPC provides GNU makefile(s) to rebuild all its libraries at the base of the product, details are below.rTrT}rT(jjTjjTubaubj)rT}r T(jXGNU make version 3.81 or greater is required. The XDC tools (provided with most SDKs and CCS distributions) includes a pre-compiled version of GNU make 3.81 in $(XDC_INSTALL_DIR)/gmake.jjSjj\Sjjj}r!T(j]j]j]j]j]ujNjhj]r"Tj)r#T}r$T(jXGNU make version 3.81 or greater is required. The XDC tools (provided with most SDKs and CCS distributions) includes a pre-compiled version of GNU make 3.81 in $(XDC_INSTALL_DIR)/gmake.r%TjjTjj\Sjjj}r&T(j]j]j]j]j]ujK;j]r'TjXGNU make version 3.81 or greater is required. The XDC tools (provided with most SDKs and CCS distributions) includes a pre-compiled version of GNU make 3.81 in $(XDC_INSTALL_DIR)/gmake.r(Tr)T}r*T(jj%Tjj#Tubaubaubj)r+T}r,T(jUjKjjSjj\Sjjj}r-T(j]r.TjQQaj]j]j]r/TUid52r0Taj]ujK@jhj]r1T(j)r2T}r3T(jX products.makr4Tjj+Tjj\Sjjj}r5T(j]j]j]j]j]ujK@jhj]r6TjX products.makr7Tr8T}r9T(jj4Tjj2Tubaubj)r:T}r;T(jXIPC contains a **products.mak** file at the root of the product that specifies the necessary paths and options to build IPC for the various OS support.jj+Tjj\Sjjj}rTr?T}r@T(jXIPC contains a jj:Tubj)rAT}rBT(jX**products.mak**j}rCT(j]j]j]j]j]ujj:Tj]rDTjX products.makrETrFT}rGT(jUjjATubajjubjXx file at the root of the product that specifies the necessary paths and options to build IPC for the various OS support.rHTrIT}rJT(jXx file at the root of the product that specifies the necessary paths and options to build IPC for the various OS support.jj:Tubeubj)rKT}rLT(jX6Edit **products.mak** and set the following variables:rMTjj+Tjj\Sjjj}rNT(j]j]j]j]j]ujKFjhj]rOT(jXEdit rPTrQT}rRT(jXEdit jjKTubj)rST}rTT(jX**products.mak**j}rUT(j]j]j]j]j]ujjKTj]rVTjX products.makrWTrXT}rYT(jUjjSTubajjubjX! and set the following variables:rZTr[T}r\T(jX! and set the following variables:jjKTubeubjt)r]T}r^T(jUjj+Tjj\Sjjwj}r_T(jyX-j]j]j]j]j]ujKHjhj]r`T(j{)raT}rbT(jXVariables used by **both Linux-side and BIOS-side** build scripts - **PLATFORM** - (Optional) Device to build for - To find the supported list of platforms, run: **./configure --help** - If not set, Linux libraries and executables for all supported platforms will be built. - If not set, BIOS libraries for all toolchains specified (see below) will be built, but no BIOS-side executables will be built. - BIOS-side builds started leveraging this variable in IPC 3.10. Prior releases built BIOS-side executables for **all** supported platforms based on that targets/toolchains set above (which can take a while!) jj]TjNjjj}rcT(j]j]j]j]j]ujNjhj]rdT(j)reT}rfT(jXAVariables used by **both Linux-side and BIOS-side** build scriptsrgTjjaTjj\Sjjj}rhT(j]j]j]j]j]ujKHj]riT(jXVariables used by rjTrkT}rlT(jXVariables used by jjeTubj)rmT}rnT(jX!**both Linux-side and BIOS-side**j}roT(j]j]j]j]j]ujjeTj]rpTjXboth Linux-side and BIOS-siderqTrrT}rsT(jUjjmTubajjubjX build scriptsrtTruT}rvT(jX build scriptsjjeTubeubjt)rwT}rxT(jUj}ryT(jyX-j]j]j]j]j]ujjaTj]rzTj{)r{T}r|T(jXG**PLATFORM** - (Optional) Device to build for - To find the supported list of platforms, run: **./configure --help** - If not set, Linux libraries and executables for all supported platforms will be built. - If not set, BIOS libraries for all toolchains specified (see below) will be built, but no BIOS-side executables will be built. - BIOS-side builds started leveraging this variable in IPC 3.10. Prior releases built BIOS-side executables for **all** supported platforms based on that targets/toolchains set above (which can take a while!) j}r}T(j]j]j]j]j]ujjwTj]r~T(j)rT}rT(jX-**PLATFORM** - (Optional) Device to build forrTjj{Tjj\Sjjj}rT(j]j]j]j]j]ujKJj]rT(j)rT}rT(jX **PLATFORM**j}rT(j]j]j]j]j]ujjTj]rTjXPLATFORMrTrT}rT(jUjjTubajjubjX! - (Optional) Device to build forrTrT}rT(jX! - (Optional) Device to build forjjTubeubjt)rT}rT(jUj}rT(jyX-j]j]j]j]j]ujj{Tj]rT(j{)rT}rT(jXDTo find the supported list of platforms, run: **./configure --help**j}rT(j]j]j]j]j]ujjTj]rTj)rT}rT(jXDTo find the supported list of platforms, run: **./configure --help**jjTjj\Sjjj}rT(j]j]j]j]j]ujKLj]rT(jX.To find the supported list of platforms, run: rTrT}rT(jX.To find the supported list of platforms, run: jjTubj)rT}rT(jX**./configure --help**j}rT(j]j]j]j]j]ujjTj]rTjX./configure --helprTrT}rT(jUjjTubajjubeubajjubj{)rT}rT(jXVIf not set, Linux libraries and executables for all supported platforms will be built.j}rT(j]j]j]j]j]ujjTj]rTj)rT}rT(jXVIf not set, Linux libraries and executables for all supported platforms will be built.rTjjTjj\Sjjj}rT(j]j]j]j]j]ujKNj]rTjXVIf not set, Linux libraries and executables for all supported platforms will be built.rTrT}rT(jjTjjTubaubajjubj{)rT}rT(jX[If not set, BIOS libraries for all toolchains specified (see below) will be built, but no BIOS-side executables will be built. - BIOS-side builds started leveraging this variable in IPC 3.10. Prior releases built BIOS-side executables for **all** supported platforms based on that targets/toolchains set above (which can take a while!) j}rT(j]j]j]j]j]ujjTj]rT(j)rT}rT(jX~If not set, BIOS libraries for all toolchains specified (see below) will be built, but no BIOS-side executables will be built.rTjjTjj\Sjjj}rT(j]j]j]j]j]ujKPj]rTjX~If not set, BIOS libraries for all toolchains specified (see below) will be built, but no BIOS-side executables will be built.rTrT}rT(jjTjjTubaubjt)rT}rT(jUj}rT(jyX-j]j]j]j]j]ujjTj]rTj{)rT}rT(jXBIOS-side builds started leveraging this variable in IPC 3.10. Prior releases built BIOS-side executables for **all** supported platforms based on that targets/toolchains set above (which can take a while!) j}rT(j]j]j]j]j]ujjTj]rTj)rT}rT(jXBIOS-side builds started leveraging this variable in IPC 3.10. Prior releases built BIOS-side executables for **all** supported platforms based on that targets/toolchains set above (which can take a while!)jjTjj\Sjjj}rT(j]j]j]j]j]ujKTj]rT(jXnBIOS-side builds started leveraging this variable in IPC 3.10. Prior releases built BIOS-side executables for rTrT}rT(jXnBIOS-side builds started leveraging this variable in IPC 3.10. Prior releases built BIOS-side executables for jjTubj)rT}rT(jX**all**j}rT(j]j]j]j]j]ujjTj]rTjXallrTrT}rT(jUjjTubajjubjXY supported platforms based on that targets/toolchains set above (which can take a while!)rTrT}rT(jXY supported platforms based on that targets/toolchains set above (which can take a while!)jjTubeubajjubajjwubejjubejjwubejjubajjwubeubj{)rT}rT(jXVariables used by **Linux-side** build scripts - **TOOLCHAIN_INSTALL_DIR** - Path to the devices ARM Linux cross-compiler toolchain - **TOOLCHAIN_LONGNAME** - Long name of the devices toolchain (e.g. arm-none-linux-gnueabi) - **KERNEL_INSTALL_DIR** - Location of your Linux kernel installation - In old releases, this variable was optional, and only needed for platforms that support the MmRpc API (e.g. OMAP5, DRA7XX). In IPC 3.00.04, 3.10.02, and 3.20+, all platforms began requiring this variable to interrogate your kernel's version (via KERNEL_INSTALL_DIR/linux/version.h) and accommodate different kernels. - **DRM_PREFIX** - (Optional) Location of your libdrm installation, used by some MmRpc tests - This is only used by MmRpc tests, and therefore only should be set for platforms that support the MmRpc API - If set, additional MmRpc tests may be built. - **CMEM_INSTALL_DIR** - (Optional) Path to TI Linux Utils package to locate the pre-built `CMEM `__ libraries used by some MessageQ tests - If set, additional test applications for select platforms may be built. jj]TjNjjj}rT(j]j]j]j]j]ujNjhj]rT(j)rT}rT(jX.Variables used by **Linux-side** build scriptsjjTjj\Sjjj}rT(j]j]j]j]j]ujKYj]rT(jXVariables used by rTrT}rT(jXVariables used by jjTubj)rT}rT(jX**Linux-side**j}rT(j]j]j]j]j]ujjTj]rTjX Linux-siderTrT}rT(jUjjTubajjubjX build scriptsrTrT}rT(jX build scriptsjjTubeubjt)rT}rT(jUj}rT(jyX-j]j]j]j]j]ujjTj]rT(j{)rT}rT(jXR**TOOLCHAIN_INSTALL_DIR** - Path to the devices ARM Linux cross-compiler toolchainj}rT(j]j]j]j]j]ujjTj]rTj)rT}rT(jXR**TOOLCHAIN_INSTALL_DIR** - Path to the devices ARM Linux cross-compiler toolchainjjTjj\Sjjj}rT(j]j]j]j]j]ujK[j]rT(j)rT}rT(jX**TOOLCHAIN_INSTALL_DIR**j}rT(j]j]j]j]j]ujjTj]rTjXTOOLCHAIN_INSTALL_DIRrTrT}rT(jUjjTubajjubjX9 - Path to the devices ARM Linux cross-compiler toolchainrTrT}rT(jX9 - Path to the devices ARM Linux cross-compiler toolchainjjTubeubajjubj{)rU}rU(jXY**TOOLCHAIN_LONGNAME** - Long name of the devices toolchain (e.g. arm-none-linux-gnueabi)j}rU(j]j]j]j]j]ujjTj]rUj)rU}rU(jXY**TOOLCHAIN_LONGNAME** - Long name of the devices toolchain (e.g. arm-none-linux-gnueabi)jjUjj\Sjjj}rU(j]j]j]j]j]ujK]j]rU(j)rU}r U(jX**TOOLCHAIN_LONGNAME**j}r U(j]j]j]j]j]ujjUj]r UjXTOOLCHAIN_LONGNAMEr Ur U}rU(jUjjUubajjubjXC - Long name of the devices toolchain (e.g. arm-none-linux-gnueabi)rUrU}rU(jXC - Long name of the devices toolchain (e.g. arm-none-linux-gnueabi)jjUubeubajjubj{)rU}rU(jX**KERNEL_INSTALL_DIR** - Location of your Linux kernel installation - In old releases, this variable was optional, and only needed for platforms that support the MmRpc API (e.g. OMAP5, DRA7XX). In IPC 3.00.04, 3.10.02, and 3.20+, all platforms began requiring this variable to interrogate your kernel's version (via KERNEL_INSTALL_DIR/linux/version.h) and accommodate different kernels. j}rU(j]j]j]j]j]ujjTj]rU(j)rU}rU(jXC**KERNEL_INSTALL_DIR** - Location of your Linux kernel installationjjUjj\Sjjj}rU(j]j]j]j]j]ujK_j]rU(j)rU}rU(jX**KERNEL_INSTALL_DIR**j}rU(j]j]j]j]j]ujjUj]rUjXKERNEL_INSTALL_DIRrUrU}r U(jUjjUubajjubjX- - Location of your Linux kernel installationr!Ur"U}r#U(jX- - Location of your Linux kernel installationjjUubeubjt)r$U}r%U(jUj}r&U(jyX-j]j]j]j]j]ujjUj]r'Uj{)r(U}r)U(jX=In old releases, this variable was optional, and only needed for platforms that support the MmRpc API (e.g. OMAP5, DRA7XX). In IPC 3.00.04, 3.10.02, and 3.20+, all platforms began requiring this variable to interrogate your kernel's version (via KERNEL_INSTALL_DIR/linux/version.h) and accommodate different kernels. j}r*U(j]j]j]j]j]ujj$Uj]r+Uj)r,U}r-U(jX<In old releases, this variable was optional, and only needed for platforms that support the MmRpc API (e.g. OMAP5, DRA7XX). In IPC 3.00.04, 3.10.02, and 3.20+, all platforms began requiring this variable to interrogate your kernel's version (via KERNEL_INSTALL_DIR/linux/version.h) and accommodate different kernels.r.Ujj(Ujj\Sjjj}r/U(j]j]j]j]j]ujKbj]r0UjX<In old releases, this variable was optional, and only needed for platforms that support the MmRpc API (e.g. OMAP5, DRA7XX). In IPC 3.00.04, 3.10.02, and 3.20+, all platforms began requiring this variable to interrogate your kernel's version (via KERNEL_INSTALL_DIR/linux/version.h) and accommodate different kernels.r1Ur2U}r3U(jj.Ujj,Uubaubajjubajjwubejjubj{)r4U}r5U(jX**DRM_PREFIX** - (Optional) Location of your libdrm installation, used by some MmRpc tests - This is only used by MmRpc tests, and therefore only should be set for platforms that support the MmRpc API - If set, additional MmRpc tests may be built. j}r6U(j]j]j]j]j]ujjTj]r7U(j)r8U}r9U(jXZ**DRM_PREFIX** - (Optional) Location of your libdrm installation, used by some MmRpc testsjj4Ujj\Sjjj}r:U(j]j]j]j]j]ujKij]r;U(j)rU(j]j]j]j]j]ujj8Uj]r?UjX DRM_PREFIXr@UrAU}rBU(jUjj`__ libraries used by some MessageQ tests - If set, additional test applications for select platforms may be built. j}rdU(j]j]j]j]j]ujjTj]reU(j)rfU}rgU(jX**CMEM_INSTALL_DIR** - (Optional) Path to TI Linux Utils package to locate the pre-built `CMEM `__ libraries used by some MessageQ testsjjbUjj\Sjjj}rhU(j]j]j]j]j]ujKpj]riU(j)rjU}rkU(jX**CMEM_INSTALL_DIR**j}rlU(j]j]j]j]j]ujjfUj]rmUjXCMEM_INSTALL_DIRrnUroU}rpU(jUjjjUubajjubjXE - (Optional) Path to TI Linux Utils package to locate the pre-built rqUrrU}rsU(jXE - (Optional) Path to TI Linux Utils package to locate the pre-built jjfUubj)rtU}ruU(jXG`CMEM `__j}rvU(UnameXCMEMjX<http://processors.wiki.ti.com/index.php/Linux_Utils_Overviewj]j]j]j]j]ujjfUj]rwUjXCMEMrxUryU}rzU(jUjjtUubajjubjX& libraries used by some MessageQ testsr{Ur|U}r}U(jX& libraries used by some MessageQ testsjjfUubeubjt)r~U}rU(jUj}rU(jyX-j]j]j]j]j]ujjbUj]rUj{)rU}rU(jXHIf set, additional test applications for select platforms may be built. j}rU(j]j]j]j]j]ujj~Uj]rUj)rU}rU(jXGIf set, additional test applications for select platforms may be built.rUjjUjj\Sjjj}rU(j]j]j]j]j]ujKuj]rUjXGIf set, additional test applications for select platforms may be built.rUrU}rU(jjUjjUubaubajjubajjwubejjubejjwubeubj{)rU}rU(jXVariables used by **BIOS-side** build scripts - **XDC_INSTALL_DIR** - Path to TI's XDCTools installation (e.g. **c:/ti/xdctools_**) - **BIOS_INSTALL_DIR** - Path to TI's SYS/BIOS installation (e.g. **c:/ti/bios_**) - **ti.targets.** - Path to TI toolchain for the device. (e.g. **c:/ti/CCS/ccsbase/tools/compiler/c6000_**) - Set only the variables to the targets your device supports to minimize build time. jj]TjNjjj}rU(j]j]j]j]j]ujNjhj]rU(j)rU}rU(jX-Variables used by **BIOS-side** build scriptsjjUjj\Sjjj}rU(j]j]j]j]j]ujKxj]rU(jXVariables used by rUrU}rU(jXVariables used by jjUubj)rU}rU(jX **BIOS-side**j}rU(j]j]j]j]j]ujjUj]rUjX BIOS-siderUrU}rU(jUjjUubajjubjX build scriptsrUrU}rU(jX build scriptsjjUubeubjt)rU}rU(jUj}rU(jyX-j]j]j]j]j]ujjUj]rU(j{)rU}rU(jX\**XDC_INSTALL_DIR** - Path to TI's XDCTools installation (e.g. **c:/ti/xdctools_**)j}rU(j]j]j]j]j]ujjUj]rUj)rU}rU(jX\**XDC_INSTALL_DIR** - Path to TI's XDCTools installation (e.g. **c:/ti/xdctools_**)jjUjj\Sjjj}rU(j]j]j]j]j]ujKzj]rU(j)rU}rU(jX**XDC_INSTALL_DIR**j}rU(j]j]j]j]j]ujjUj]rUjXXDC_INSTALL_DIRrUrU}rU(jUjjUubajjubjX, - Path to TI's XDCTools installation (e.g. rUrU}rU(jX, - Path to TI's XDCTools installation (e.g. jjUubj)rU}rU(jX**c:/ti/xdctools_**j}rU(j]j]j]j]j]ujjUj]rUjXc:/ti/xdctools_rUrU}rU(jUjjUubajjubjX)rU}rU(jX)jjUubeubajjubj{)rU}rU(jXY**BIOS_INSTALL_DIR** - Path to TI's SYS/BIOS installation (e.g. **c:/ti/bios_**)j}rU(j]j]j]j]j]ujjUj]rUj)rU}rU(jXY**BIOS_INSTALL_DIR** - Path to TI's SYS/BIOS installation (e.g. **c:/ti/bios_**)jjUjj\Sjjj}rU(j]j]j]j]j]ujK|j]rU(j)rU}rU(jX**BIOS_INSTALL_DIR**j}rU(j]j]j]j]j]ujjUj]rUjXBIOS_INSTALL_DIRrUrU}rU(jUjjUubajjubjX, - Path to TI's SYS/BIOS installation (e.g. rUrU}rU(jX, - Path to TI's SYS/BIOS installation (e.g. jjUubj)rU}rU(jX**c:/ti/bios_**j}rU(j]j]j]j]j]ujjUj]rUjXc:/ti/bios_rUrU}rU(jUjjUubajjubjX)rU}rU(jX)jjUubeubajjubj{)rU}rU(jX**ti.targets.** - Path to TI toolchain for the device. (e.g. **c:/ti/CCS/ccsbase/tools/compiler/c6000_**) - Set only the variables to the targets your device supports to minimize build time. j}rU(j]j]j]j]j]ujjUj]rU(j)rU}rU(jX**ti.targets.** - Path to TI toolchain for the device. (e.g. **c:/ti/CCS/ccsbase/tools/compiler/c6000_**)jjUjj\Sjjj}rU(j]j]j]j]j]ujK~j]rU(j)rU}rU(jX.**ti.targets.**j}rU(j]j]j]j]j]ujjUj]rUjX*ti.targets.rUrU}rU(jUjjUubajjubjX. - Path to TI toolchain for the device. (e.g. rUrU}rU(jX. - Path to TI toolchain for the device. (e.g. jjUubj)rU}rU(jX4**c:/ti/CCS/ccsbase/tools/compiler/c6000_**j}rU(j]j]j]j]j]ujjUj]rUjX0c:/ti/CCS/ccsbase/tools/compiler/c6000_rUrU}rU(jUjjUubajjubjX)rU}rU(jX)jjUubeubjt)rU}rU(jUj}rU(jyX-j]j]j]j]j]ujjUj]rUj{)rU}rU(jXSSet only the variables to the targets your device supports to minimize build time. j}rU(j]j]j]j]j]ujjUj]rUj)rV}rV(jXRSet only the variables to the targets your device supports to minimize build time.rVjjUjj\Sjjj}rV(j]j]j]j]j]ujKj]rVjXRSet only the variables to the targets your device supports to minimize build time.rVrV}rV(jjVjjVubaubajjubajjwubejjubejjwubeubeubj)rV}r V(jXmThe specific versions of dependent components can be found in the IPC Release Notes, provided in the product.jj+Tjj\Sjjj}r V(j]j]j]j]j]ujNjhj]r Vj)r V}r V(jXmThe specific versions of dependent components can be found in the IPC Release Notes, provided in the product.rVjjVjj\Sjjj}rV(j]j]j]j]j]ujKj]rVjXmThe specific versions of dependent components can be found in the IPC Release Notes, provided in the product.rVrV}rV(jjVjj Vubaubaubeubj)rV}rV(jUjjSjj\Sjjj}rV(j]j]j]j]rVU ipc-linux-makrVaj]rVhOaujKjhj]rV(j)rV}rV(jX ipc-linux.makrVjjVjj\Sjjj}rV(j]j]j]j]j]ujKjhj]rVjX ipc-linux.makr Vr!V}r"V(jjVjjVubaubj)r#V}r$V(jXThe Linux-side build is provided as a GNU Autotools (Autoconf, Automake, Libtool) project. If you are familiar with Autoconf GNU projects, you can proceed with using the **./configure** script directly to cross-compile the Linux user libraries and tests.jjVjj\Sjjj}r%V(j]j]j]j]j]ujKjhj]r&V(jXThe Linux-side build is provided as a GNU Autotools (Autoconf, Automake, Libtool) project. If you are familiar with Autoconf GNU projects, you can proceed with using the r'Vr(V}r)V(jXThe Linux-side build is provided as a GNU Autotools (Autoconf, Automake, Libtool) project. If you are familiar with Autoconf GNU projects, you can proceed with using the jj#Vubj)r*V}r+V(jX**./configure**j}r,V(j]j]j]j]j]ujj#Vj]r-VjX ./configurer.Vr/V}r0V(jUjj*VubajjubjXE script directly to cross-compile the Linux user libraries and tests.r1Vr2V}r3V(jXE script directly to cross-compile the Linux user libraries and tests.jj#Vubeubj)r4V}r5V(jXFor those that require some assistance, the IPC package provides a GNU makefile (**ipc-linux.mak**) to configure the Linux-side build, using the options and component paths set in the **products.mak** file. To configure the build using these files, issue the following command:jjVjj\Sjjj}r6V(j]j]j]j]j]ujKjhj]r7V(jXQFor those that require some assistance, the IPC package provides a GNU makefile (r8Vr9V}r:V(jXQFor those that require some assistance, the IPC package provides a GNU makefile (jj4Vubj)r;V}rVjX ipc-linux.makr?Vr@V}rAV(jUjj;VubajjubjXV) to configure the Linux-side build, using the options and component paths set in the rBVrCV}rDV(jXV) to configure the Linux-side build, using the options and component paths set in the jj4Vubj)rEV}rFV(jX**products.mak**j}rGV(j]j]j]j]j]ujj4Vj]rHVjX products.makrIVrJV}rKV(jUjjEVubajjubjXM file. To configure the build using these files, issue the following command:rLVrMV}rNV(jXM file. To configure the build using these files, issue the following command:jj4Vubeubj)rOV}rPV(jX( make -f ipc-linux.mak configjjVjj\Sjjj}rQV(j@jAj]j]j]j]j]ujM:jhj]rRVjX( make -f ipc-linux.mak configrSVrTV}rUV(jUjjOVubaubj)rVV}rWV(jXThere are few additional target goals provided in the ipc-linux.mak file for commonly used configurations. These goals include:rXVjjVjj\Sjjj}rYV(j]j]j]j]j]ujKjhj]rZVjXThere are few additional target goals provided in the ipc-linux.mak file for commonly used configurations. These goals include:r[Vr\V}r]V(jjXVjjVVubaubjt)r^V}r_V(jUjjVjj\Sjjwj}r`V(jyX-j]j]j]j]j]ujKjhj]raV(j{)rbV}rcV(jXconfig - (Default) Configure both static and shared (dynamic) Linux IPC user libraries. Executables (e.g. lad and tests) link against the shared libraries.jj^Vjj\Sjjj}rdV(j]j]j]j]j]ujNjhj]reVj)rfV}rgV(jXconfig - (Default) Configure both static and shared (dynamic) Linux IPC user libraries. Executables (e.g. lad and tests) link against the shared libraries.rhVjjbVjj\Sjjj}riV(j]j]j]j]j]ujKj]rjVjXconfig - (Default) Configure both static and shared (dynamic) Linux IPC user libraries. Executables (e.g. lad and tests) link against the shared libraries.rkVrlV}rmV(jjhVjjfVubaubaubj{)rnV}roV(jX@config-static - Configure static only libraries and executables.rpVjj^Vjj\Sjjj}rqV(j]j]j]j]j]ujNjhj]rrVj)rsV}rtV(jjpVjjnVjj\Sjjj}ruV(j]j]j]j]j]ujKj]rvVjX@config-static - Configure static only libraries and executables.rwVrxV}ryV(jjpVjjsVubaubaubj{)rzV}r{V(jXKconfig-shared - Configure shared (dynamic) only libraries and executables. jj^Vjj\Sjjj}r|V(j]j]j]j]j]ujNjhj]r}Vj)r~V}rV(jXJconfig-shared - Configure shared (dynamic) only libraries and executables.rVjjzVjj\Sjjj}rV(j]j]j]j]j]ujKj]rVjXJconfig-shared - Configure shared (dynamic) only libraries and executables.rVrV}rV(jjVjj~Vubaubaubeubj)rV}rV(jXOnce the 'config' is complete, and the autotools-generated Makefile has been created, you can build the Linux side of IPC by issuing the following:rVjjVjj\Sjjj}rV(j]j]j]j]j]ujKjhj]rVjXOnce the 'config' is complete, and the autotools-generated Makefile has been created, you can build the Linux side of IPC by issuing the following:rVrV}rV(jjVjjVubaubj)rV}rV(jX makejjVjj\Sjjj}rV(j@jAj]j]j]j]j]ujMLjhj]rVjX makerVrV}rV(jUjjVubaubj)rV}rV(jXYou can also specify a PLATFORM to (re)configure for on the command line which overrides any options set in the products.mak file as follows:rVjjVjj\Sjjj}rV(j]j]j]j]j]ujKjhj]rVjXYou can also specify a PLATFORM to (re)configure for on the command line which overrides any options set in the products.mak file as follows:rVrV}rV(jjVjjVubaubj)rV}rV(jXK make -f ipc-linux.mak config PLATFORM=omapl138 makejjVjj\Sjjj}rV(j@jAj]j]j]j]j]ujMSjhj]rVjXK make -f ipc-linux.mak config PLATFORM=omapl138 makerVrV}rV(jUjjVubaubj)rV}rV(jXxNote that before reconfiguring for a new Linux toolchain or platform, the autotools-generated files should be clean(ed):rVjjVjj\Sjjj}rV(j]j]j]j]j]ujKjhj]rVjXxNote that before reconfiguring for a new Linux toolchain or platform, the autotools-generated files should be clean(ed):rVrV}rV(jjVjjVubaubj)rV}rV(jX make distcleanjjVjj\Sjjj}rV(j@jAj]j]j]j]j]ujM[jhj]rVjX make distcleanrVrV}rV(jUjjVubaubjc)rV}rV(jUjjVjj\Sjjfj}rV(j]j]j]j]j]ujKjhj]rVji)rV}rV(jUjlKjjVjj\Sjjj}rV(j]j]j]j]j]ujKjhj]ubaubeubj)rV}rV(jUjKjjSjj\Sjjj}rV(j]rVjARaj]j]j]rVUid53rVaj]ujKjhj]rV(j)rV}rV(jX ipc-bios.makrVjjVjj\Sjjj}rV(j]j]j]j]j]ujKjhj]rVjX ipc-bios.makrVrV}rV(jjVjjVubaubj)rV}rV(jXpThe SYS/BIOS-side IPC is built with a GNU makefile. After editing **products.mak**, issue the following command:jjVjj\Sjjj}rV(j]j]j]j]j]ujKjhj]rV(jXBThe SYS/BIOS-side IPC is built with a GNU makefile. After editing rVrV}rV(jXBThe SYS/BIOS-side IPC is built with a GNU makefile. After editing jjVubj)rV}rV(jX**products.mak**j}rV(j]j]j]j]j]ujjVj]rVjX products.makrVrV}rV(jUjjVubajjubjX, issue the following command:rVrV}rV(jX, issue the following command:jjVubeubj)rV}rV(jX$ make -f ipc-bios.mak alljjVjj\Sjjj}rV(j@jAj]j]j]j]j]ujMgjhj]rVjX$ make -f ipc-bios.mak allrVrV}rV(jUjjVubaubj)rV}rV(jXLBased on the number of targets you're building for, this may take some time.rVjjVjj\Sjjj}rV(j]j]j]j]j]ujKjhj]rVjXLBased on the number of targets you're building for, this may take some time.rVrV}rV(jjVjjVubaubj)rV}rV(jXThe BIOS-side libraries often come pre-built, so in many cases, rebuilding the BIOS-side is not necessary. Some reasons you may want to rebuild:jjVjj\Sjjj}rV(j]j]j]j]j]ujNjhj]rVj)rV}rV(jXThe BIOS-side libraries often come pre-built, so in many cases, rebuilding the BIOS-side is not necessary. Some reasons you may want to rebuild:rVjjVjj\Sjjj}rV(j]j]j]j]j]ujKj]rVjXThe BIOS-side libraries often come pre-built, so in many cases, rebuilding the BIOS-side is not necessary. Some reasons you may want to rebuild:rVrV}rV(jjVjjVubaubaubjt)rV}rV(jUjjVjj\Sjjwj}rV(jyX-j]j]j]j]j]ujKjhj]rV(j{)rV}rV(jXOYour distribution of IPC **didn't** come with the necessary pre-built librariesjjVjj\Sjjj}rV(j]j]j]j]j]ujNjhj]rVj)rV}rV(jXOYour distribution of IPC **didn't** come with the necessary pre-built librariesjjVjj\Sjjj}rV(j]j]j]j]j]ujKj]rW(jXYour distribution of IPC rWrW}rW(jXYour distribution of IPC jjVubj)rW}rW(jX **didn't**j}rW(j]j]j]j]j]ujjVj]rWjXdidn'trWr W}r W(jUjjWubajjubjX, come with the necessary pre-built librariesr Wr W}r W(jX, come with the necessary pre-built librariesjjVubeubaubj{)rW}rW(jXKYou intend to run the 'test' executables (which often don't come pre-built)jjVjj\Sjjj}rW(j]j]j]j]j]ujNjhj]rWj)rW}rW(jXKYou intend to run the 'test' executables (which often don't come pre-built)rWjjWjj\Sjjj}rW(j]j]j]j]j]ujKj]rWjXKYou intend to run the 'test' executables (which often don't come pre-built)rWrW}rW(jjWjjWubaubaubj{)rW}rW(jX:You want to use a specific toolchain or dependency versionrWjjVjj\Sjjj}rW(j]j]j]j]j]ujNjhj]rWj)rW}r W(jjWjjWjj\Sjjj}r!W(j]j]j]j]j]ujKj]r"WjX:You want to use a specific toolchain or dependency versionr#Wr$W}r%W(jjWjjWubaubaubj{)r&W}r'W(jX-You want to tune some of the compile options jjVjj\Sjjj}r(W(j]j]j]j]j]ujNjhj]r)Wj)r*W}r+W(jX,You want to tune some of the compile optionsr,Wjj&Wjj\Sjjj}r-W(j]j]j]j]j]ujKj]r.WjX,You want to tune some of the compile optionsr/Wr0W}r1W(jj,Wjj*Wubaubaubeubeubeubj)r2W}r3W(jUjKjjJSjj\Sjjj}r4W(j]r5WXrunr6Waj]j]j]r7WUid54r8Waj]ujKjhj]r9W(j)r:W}r;W(jXRunrWjXRunr?Wr@W}rAW(jj`__.jjaWjj\Sjjj}rrW(j]j]j]j]j]ujKjhj]rsW(jX3The kernel for the OMAP-L138, can be obtained from rtWruW}rvW(jX3The kernel for the OMAP-L138, can be obtained from jjpWubj)rwW}rxW(jXH`Gitorious linux-davinci project `__j}ryW(UnameXGitorious linux-davinci projectjX"http://gitorious.org/linux-davincij]j]j]j]j]ujjpWj]rzWjXGitorious linux-davinci projectr{Wr|W}r}W(jUjjwWubajjubjX.r~W}rW(jX.jjpWubeubj)rW}rW(jXZThe patches apply to the following commit id: **595ab716fc6e648b7dc79a58a01917ebb67b9508**jjaWjj\Sjjj}rW(j]j]j]j]j]ujKjhj]rW(jX.The patches apply to the following commit id: rWrW}rW(jX.The patches apply to the following commit id: jjWubj)rW}rW(jX,**595ab716fc6e648b7dc79a58a01917ebb67b9508**j}rW(j]j]j]j]j]ujjWj]rWjX(595ab716fc6e648b7dc79a58a01917ebb67b9508rWrW}rW(jUjjWubajjubeubj)rW}rW(jXqThe specific patches needed for this kernel can be found in the **linux/patches/3.8.0** of your IPC installation.jjaWjj\Sjjj}rW(j]j]j]j]j]ujKjhj]rW(jX@The specific patches needed for this kernel can be found in the rWrW}rW(jX@The specific patches needed for this kernel can be found in the jjWubj)rW}rW(jX**linux/patches/3.8.0**j}rW(j]j]j]j]j]ujjWj]rWjXlinux/patches/3.8.0rWrW}rW(jUjjWubajjubjX of your IPC installation.rWrW}rW(jX of your IPC installation.jjWubeubj)rW}rW(jXuOnce the patches are applied, there are a few key config parameters needed for rpmsg and socket driver to build/work.rWjjaWjj\Sjjj}rW(j]j]j]j]j]ujKjhj]rWjXuOnce the patches are applied, there are a few key config parameters needed for rpmsg and socket driver to build/work.rWrW}rW(jjWjjWubaubj)rW}rW(jXCONFIG_REMOTEPROC=m CONFIG_DA8XX_REMOTEPROC=m CONFIG_RPMSG=m CONFIG_VIRTIO=m It is also recommended to compile a Linux kernel with the debugfs facilityrWjjaWjj\Sjjj}rW(j]j]j]j]j]ujKjhj]rWjXCONFIG_REMOTEPROC=m CONFIG_DA8XX_REMOTEPROC=m CONFIG_RPMSG=m CONFIG_VIRTIO=m It is also recommended to compile a Linux kernel with the debugfs facilityrWrW}rW(jjWjjWubaubj)rW}rW(jX3CONFIG_DEBUG_FS=y Re-build the kernel. For example:rWjjaWjj\Sjjj}rW(j]j]j]j]j]ujKjhj]rWjX3CONFIG_DEBUG_FS=y Re-build the kernel. For example:rWrW}rW(jjWjjWubaubj)rW}rW(jXFbuildhost$ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabi- uImagejjaWjj\Sjjj}rW(j@jAj]j]j]j]j]ujMjhj]rWjXFbuildhost$ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabi- uImagerWrW}rW(jUjjWubaubj)rW}rW(jXmYou will also need to re-build the kernel modules and install them on your target's file system. For example:rWjjaWjj\Sjjj}rW(j]j]j]j]j]ujMjhj]rWjXmYou will also need to re-build the kernel modules and install them on your target's file system. For example:rWrW}rW(jjWjjWubaubj)rW}rW(jXbuildhost$ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabi- modules buildhost$ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabi- INSTALL_MOD_PATH= modules_installjjaWjj\Sjjj}rW(j@jAj]j]j]j]j]ujMjhj]rWjXbuildhost$ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabi- modules buildhost$ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabi- INSTALL_MOD_PATH= modules_installrWrW}rW(jUjjWubaubeubeubj)rW}rW(jUjj2Wjj\Sjjj}rW(j]j]j]j]rWUkernel-boot-up-parametersrWaj]rWjvaujM jhj]rW(j)rW}rW(jXKernel Boot-up ParametersrWjjWjj\Sjjj}rW(j]j]j]j]j]ujM jhj]rWjXKernel Boot-up ParametersrWrW}rW(jjWjjWubaubj)rW}rW(jXIPC requires an argument to be passed to the Linux kernel during boot up to properly run the tests. The remote processor(s) (rproc) memory location needs to be set.rWjjWjj\Sjjj}rW(j]j]j]j]j]ujM jhj]rWjXIPC requires an argument to be passed to the Linux kernel during boot up to properly run the tests. The remote processor(s) (rproc) memory location needs to be set.rWrW}rW(jjWjjWubaubjt)rW}rW(jUjjWjj\Sjjwj}rW(jyX-j]j]j]j]j]ujMjhj]rWj{)rW}rW(jX For example, jjWjj\Sjjj}rW(j]j]j]j]j]ujNjhj]rWj)rW}rW(jX For example,rWjjWjj\Sjjj}rW(j]j]j]j]j]ujMj]rWjX For example,rWrW}rW(jjWjjWubaubaubaubj)rW}rW(jXnbootargs console=ttyS2,115200n8 root=/dev/nfs nfsroot=HOST:nfs_root,nolock rw ip=dhcp rproc_mem=16M@0xC3000000jjWjj\Sjjj}rW(j@jAj]j]j]j]j]ujMjhj]rWjXnbootargs console=ttyS2,115200n8 root=/dev/nfs nfsroot=HOST:nfs_root,nolock rw ip=dhcp rproc_mem=16M@0xC3000000rWrW}rW(jUjjWubaubj)rW}rW(jX*This is just an example, bootargs may vary depending on available setup* Depending on the memory map used in the final system configuration, the memory to be reserved for rproc usage may differ.jjWjj\Sjjj}rW(j]j]j]j]j]ujMjhj]rW(jM)rW}rX(jXI*This is just an example, bootargs may vary depending on available setup*j}rX(j]j]j]j]j]ujjWj]rXjXGThis is just an example, bootargs may vary depending on available setuprXrX}rX(jUjjWubajjUubjXz Depending on the memory map used in the final system configuration, the memory to be reserved for rproc usage may differ.rXrX}rX(jXz Depending on the memory map used in the final system configuration, the memory to be reserved for rproc usage may differ.jjWubeubeubj)r X}r X(jUjj2Wjj\Sjjj}r X(j]j]j]j]r XUinstalling-testsr Xaj]rXj{aujMjhj]rX(j)rX}rX(jXInstalling TestsrXjj Xjj\Sjjj}rX(j]j]j]j]j]ujMjhj]rXjXInstalling TestsrXrX}rX(jjXjjXubaubj)rX}rX(jXTo assemble the IPC test executables and libraries into a directory structure suitable for running on the target's file-system, issue the following command in the IPC install directory:rXjj Xjj\Sjjj}rX(j]j]j]j]j]ujMjhj]rXjXTo assemble the IPC test executables and libraries into a directory structure suitable for running on the target's file-system, issue the following command in the IPC install directory:rXrX}rX(jjXjjXubaubj)r X}r!X(jX6buildhost$ make install prefix=/usrjj Xjj\Sjjj}r"X(j@jAj]j]j]j]j]ujMjhj]r#XjX6buildhost$ make install prefix=/usrr$Xr%X}r&X(jUjj Xubaubj)r'X}r(X(jX*Depending on you target's filesystem directory privileges, you may be required to run **sudo make install** to properly install the files *jj Xjj\Sjjj}r)X(j]j]j]j]j]ujM&jhj]r*X(jM)r+X}r,X(jXl*Depending on you target's filesystem directory privileges, you may be required to run **sudo make install**j}r-X(j]j]j]j]j]ujj'Xj]r.XjXjDepending on you target's filesystem directory privileges, you may be required to run **sudo make install*r/Xr0X}r1X(jUjj+XubajjUubjX to properly install the files *r2Xr3X}r4X(jX to properly install the files *jj'Xubeubj)r5X}r6X(jXThe test executables and libraries will be installed in the location path set by the **prefix** variable. If you are installing directly on a host mounted Network Filesystem(NFS), make sure to specify **usr** at the end of the **prefix** variable path. As with other variables, you can override this on the command line: :: buildhost$ sudo make install prefix=/usrjj Xjj\Sjjj}r7X(j]j]j]j]j]ujNjhj]r8X(j)r9X}r:X(jXCThe test executables and libraries will be installed in the location path set by the **prefix** variable. If you are installing directly on a host mounted Network Filesystem(NFS), make sure to specify **usr** at the end of the **prefix** variable path. As with other variables, you can override this on the command line: ::jj5Xjj\Sjjj}r;X(j]j]j]j]j]ujM+j]rX}r?X(jXUThe test executables and libraries will be installed in the location path set by the jj9Xubj)r@X}rAX(jX **prefix**j}rBX(j]j]j]j]j]ujj9Xj]rCXjXprefixrDXrEX}rFX(jUjj@XubajjubjXj variable. If you are installing directly on a host mounted Network Filesystem(NFS), make sure to specify rGXrHX}rIX(jXj variable. If you are installing directly on a host mounted Network Filesystem(NFS), make sure to specify jj9Xubj)rJX}rKX(jX**usr**j}rLX(j]j]j]j]j]ujj9Xj]rMXjXusrrNXrOX}rPX(jUjjJXubajjubjX at the end of the rQXrRX}rSX(jX at the end of the jj9Xubj)rTX}rUX(jX **prefix**j}rVX(j]j]j]j]j]ujj9Xj]rWXjXprefixrXXrYX}rZX(jUjjTXubajjubjXS variable path. As with other variables, you can override this on the command line:r[Xr\X}r]X(jXS variable path. As with other variables, you can override this on the command line:jj9Xubeubj)r^X}r_X(jX;buildhost$ sudo make install prefix=/usrjj5Xjjj}r`X(j@jAj]j]j]j]j]ujMj]raXjX;buildhost$ sudo make install prefix=/usrrbXrcX}rdX(jUjj^Xubaubeubjc)reX}rfX(jUjj Xjj\Sjjfj}rgX(j]j]j]j]j]ujM4jhj]rhXji)riX}rjX(jUjlKjjeXjj\Sjjj}rkX(j]j]j]j]j]ujKjhj]ubaubj)rlX}rmX(jX The remote processor's applications will be loaded via the remote_proc kernel module but they need to reside on the devices target filesystem in **/lib/firmware** directory. The location of the remote core application within the IPC product various based on device.jj Xjj\Sjjj}rnX(j]j]j]j]j]ujM6jhj]roX(jXThe remote processor's applications will be loaded via the remote_proc kernel module but they need to reside on the devices target filesystem in rpXrqX}rrX(jXThe remote processor's applications will be loaded via the remote_proc kernel module but they need to reside on the devices target filesystem in jjlXubj)rsX}rtX(jX**/lib/firmware**j}ruX(j]j]j]j]j]ujjlXj]rvXjX /lib/firmwarerwXrxX}ryX(jUjjsXubajjubjXg directory. The location of the remote core application within the IPC product various based on device.rzXr{X}r|X(jXg directory. The location of the remote core application within the IPC product various based on device.jjlXubeubj)r}X}r~X(jUjj Xjj\Sjjj}rX(j]j]j]j]rXUslave-binariesrXaj]rXhaujM<jhj]rX(j)rX}rX(jXSlave BinariesrXjj}Xjj\Sjjj}rX(j]j]j]j]j]ujM<jhj]rXjXSlave BinariesrXrX}rX(jjXjjXubaubj)rX}rX(jXThe slave-side test binaries, once built, are found in your IPC_INSTALL_DIR/packages/ti/ipc/tests/bin/_ directory.rXjj}Xjj\Sjjj}rX(j]j]j]j]j]ujM>jhj]rXjXThe slave-side test binaries, once built, are found in your IPC_INSTALL_DIR/packages/ti/ipc/tests/bin/_ directory.rXrX}rX(jjXjjXubaubj)rX}rX(jXCopy the appropriate slave-side executable onto the devices target filesystem into the **/lib/firmware** directory. For example, OMAP-L138 developers would do this:jj}Xjj\Sjjj}rX(j]j]j]j]j]ujMAjhj]rX(jXWCopy the appropriate slave-side executable onto the devices target filesystem into the rXrX}rX(jXWCopy the appropriate slave-side executable onto the devices target filesystem into the jjXubj)rX}rX(jX**/lib/firmware**j}rX(j]j]j]j]j]ujjXj]rXjX /lib/firmwarerXrX}rX(jUjjXubajjubjX< directory. For example, OMAP-L138 developers would do this:rXrX}rX(jX< directory. For example, OMAP-L138 developers would do this:jjXubeubj)rX}rX(jXxbuildhost$ cp IPC_INSTALL_DIR/packages/ti/ipc/tests/bin/ti_platforms_evmOMAPL138_DSP/ /lib/firmware/.jj}Xjj\Sjjj}rX(j@jAj]j]j]j]j]ujMjhj]rXjXxbuildhost$ cp IPC_INSTALL_DIR/packages/ti/ipc/tests/bin/ti_platforms_evmOMAPL138_DSP/ /lib/firmware/.rXrX}rX(jUjjXubaubeubj)rX}rX(jUjj Xjj\Sjjj}rX(j]j]j]j]rXUipc-daemons-and-driversrXaj]rXh(aujMJjhj]rX(j)rX}rX(jXIPC Daemons and DriversrXjjXjj\Sjjj}rX(j]j]j]j]j]ujMJjhj]rXjXIPC Daemons and DriversrXrX}rX(jjXjjXubaubj)rX}rX(jXIPC provides system-wide services across multiple applications, and utilizes low-level system hardware (e.g. interrupts and shared memory). To facilitate these services, IPC uses a user-space daemon (LAD) and several kernel device drivers.rXjjXjj\Sjjj}rX(j]j]j]j]j]ujMLjhj]rXjXIPC provides system-wide services across multiple applications, and utilizes low-level system hardware (e.g. interrupts and shared memory). To facilitate these services, IPC uses a user-space daemon (LAD) and several kernel device drivers.rXrX}rX(jjXjjXubaubjhK)rX}rX(jXLADrXjjXjj\SjjlKj}rX(j]rXUladrXaj]j]j]j]rXhaujNjhj]rXjXLADrXrX}rX(jjXjjXubaubj)rX}rX(jXESystem-wide IPC state is managed by a user-space daemon (LAD). This daemon is specific to a given device, and is named lad_. It will reside on the target's filesystem (typically in /usr/bin/) after following the `#Installing Tests `__ section. To run LAD, execute:jjXjj\Sjjj}rX(j]j]j]j]j]ujMTjhj]rX(jXSystem-wide IPC state is managed by a user-space daemon (LAD). This daemon is specific to a given device, and is named lad_. It will reside on the target's filesystem (typically in /usr/bin/) after following the rXrX}rX(jXSystem-wide IPC state is managed by a user-space daemon (LAD). This daemon is specific to a given device, and is named lad_. It will reside on the target's filesystem (typically in /usr/bin/) after following the jjXubj)rX}rX(jXK`#Installing Tests `__j}rX(UnameX#Installing TestsjX3index_Foundational_Components.html#installing-testsj]j]j]j]j]ujjXj]rXjX#Installing TestsrXrX}rX(jUjjXubajjubjX section. To run LAD, execute:rXrX}rX(jX section. To run LAD, execute:jjXubeubj)rX}rX(jXtarget# /usr/bin/lad_jjXjj\Sjjj}rX(j@jAj]j]j]j]j]ujMjhj]rXjXtarget# /usr/bin/lad_rXrX}rX(jUjjXubaubj)rX}rX(jXBThis forks the LAD daemon and leaves it running in the background.rXjjXjj\Sjjj}rX(j]j]j]j]j]ujM^jhj]rXjXBThis forks the LAD daemon and leaves it running in the background.rXrX}rX(jjXjjXubaubj)rX}rX(jX:LAD takes an optional argument to indicate a filename into which log statements should be emitted. This file will be created in the **/tmp/LAD/** directory. How to specify the filename varies based on your IPC release. For example, to instruct LAD to emit log statements into a 'lad.txt' file, start LAD like this:jjXjj\Sjjj}rX(j]j]j]j]j]ujM`jhj]rX(jXLAD takes an optional argument to indicate a filename into which log statements should be emitted. This file will be created in the rXrX}rX(jXLAD takes an optional argument to indicate a filename into which log statements should be emitted. This file will be created in the jjXubj)rX}rX(jX **/tmp/LAD/**j}rX(j]j]j]j]j]ujjXj]rXjX /tmp/LAD/rXrX}rX(jUjjXubajjubjX directory. How to specify the filename varies based on your IPC release. For example, to instruct LAD to emit log statements into a 'lad.txt' file, start LAD like this:rXrX}rX(jX directory. How to specify the filename varies based on your IPC release. For example, to instruct LAD to emit log statements into a 'lad.txt' file, start LAD like this:jjXubeubjt)rX}rY(jUjjXjj\Sjjwj}rY(jyX-j]j]j]j]j]ujMfjhj]rYj{)rY}rY(jXReleases before IPC 3.21: jjXjj\Sjjj}rY(j]j]j]j]j]ujNjhj]rYj)rY}rY(jXReleases before IPC 3.21:r YjjYjj\Sjjj}r Y(j]j]j]j]j]ujMfj]r YjXReleases before IPC 3.21:r Yr Y}rY(jj YjjYubaubaubaubj)rY}rY(jX%target# /usr/bin/lad_ lad.txtjjXjj\Sjjj}rY(j@jAj]j]j]j]j]ujM jhj]rYjX%target# /usr/bin/lad_ lad.txtrYrY}rY(jUjjYubaubjt)rY}rY(jUjjXjj\Sjjwj}rY(jyX-j]j]j]j]j]ujMljhj]rYj{)rY}rY(jXIPC 3.21 and after: jjYjj\Sjjj}rY(j]j]j]j]j]ujNjhj]rYj)rY}rY(jXIPC 3.21 and after:r YjjYjj\Sjjj}r!Y(j]j]j]j]j]ujMlj]r"YjXIPC 3.21 and after:r#Yr$Y}r%Y(jj YjjYubaubaubaubj)r&Y}r'Y(jX(target# /usr/bin/lad_ -l lad.txtjjXjj\Sjjj}r(Y(j@jAj]j]j]j]j]ujMjhj]r)YjX(target# /usr/bin/lad_ -l lad.txtr*Yr+Y}r,Y(jUjj&Yubaubjc)r-Y}r.Y(jUjjXjj\Sjjfj}r/Y(j]j]j]j]j]ujMrjhj]r0Yji)r1Y}r2Y(jUjlKjj-Yjj\Sjjj}r3Y(j]j]j]j]j]ujKjhj]ubaubjhK)r4Y}r5Y(jXDriversr6YjjXjj\SjjlKj}r7Y(j]r8YUdriversr9Yaj]j]j]j]r:YjaujNjhj]r;YjXDriversrY(jj6Yjj4Yubaubj)r?Y}r@Y(jX;The kernel drivers/modules added by the Linux patches must be inserted into the kernel for IPC applications to run correctly. Refer to the `#Configuring Kernel `__ section. The required modules must be configured, built and loaded onto the target's filesystem.jjXjj\Sjjj}rAY(j]j]j]j]j]ujMwjhj]rBY(jXThe kernel drivers/modules added by the Linux patches must be inserted into the kernel for IPC applications to run correctly. Refer to the rCYrDY}rEY(jXThe kernel drivers/modules added by the Linux patches must be inserted into the kernel for IPC applications to run correctly. Refer to the jj?Yubj)rFY}rGY(jXO`#Configuring Kernel `__j}rHY(UnameX#Configuring KerneljX5index_Foundational_Components.html#configuring-kernelj]j]j]j]j]ujj?Yj]rIYjX#Configuring KernelrJYrKY}rLY(jUjjFYubajjubjXa section. The required modules must be configured, built and loaded onto the target's filesystem.rMYrNY}rOY(jXa section. The required modules must be configured, built and loaded onto the target's filesystem.jj?Yubeubj)rPY}rQY(jX\Prior to loading the modules, a directory (/debug) must be created at the root of your devices filesystem. This directory will be mounted as a debugfs (debug filesystem) which the kernel modules will use to provide details about the slaves (e.g. running state, trace output, etc). If the /debug directory doesn't exist, simply create it as follows:rRYjjXjj\Sjjj}rSY(j]j]j]j]j]ujM}jhj]rTYjX\Prior to loading the modules, a directory (/debug) must be created at the root of your devices filesystem. This directory will be mounted as a debugfs (debug filesystem) which the kernel modules will use to provide details about the slaves (e.g. running state, trace output, etc). If the /debug directory doesn't exist, simply create it as follows:rUYrVY}rWY(jjRYjjPYubaubj)rXY}rYY(jXtarget# mkdir /debugjjXjj\Sjjj}rZY(j@jAj]j]j]j]j]ujM'jhj]r[YjXtarget# mkdir /debugr\Yr]Y}r^Y(jUjjXYubaubjhK)r_Y}r`Y(jX OMAP-L138raYjjXjj\SjjlKj}rbY(j]rcYU omap-l138-1rdYaj]j]j]j]reYh1aujNjhj]rfYjX OMAP-L138rgYrhY}riY(jjaYjj_Yubaubj)rjY}rkY(jXfOn OMAP-L138, the kernel modules can be loaded with the following command on the target's file-system:rlYjjXjj\Sjjj}rmY(j]j]j]j]j]ujMjhj]rnYjXfOn OMAP-L138, the kernel modules can be loaded with the following command on the target's file-system:roYrpY}rqY(jjlYjjjYubaubj)rrY}rsY(jXtarget# depmod -a target# mount -t debugfs none /debug target# modprobe remoteproc target# modprobe da8xx_remoteproc da8xx_fw_name=messageq_single.xe674 target# modprobe virtio_rpmsg_bus target# modprobe rpmsg_protojjXjj\Sjjj}rtY(j@jAj]j]j]j]j]ujM1jhj]ruYjXtarget# depmod -a target# mount -t debugfs none /debug target# modprobe remoteproc target# modprobe da8xx_remoteproc da8xx_fw_name=messageq_single.xe674 target# modprobe virtio_rpmsg_bus target# modprobe rpmsg_protorvYrwY}rxY(jUjjrYubaubj)ryY}rzY(jX`The kernel modules can be unloaded by issuing the following command on the target's file-system:r{YjjXjj\Sjjj}r|Y(j]j]j]j]j]ujMjhj]r}YjX`The kernel modules can be unloaded by issuing the following command on the target's file-system:r~YrY}rY(jj{YjjyYubaubj)rY}rY(jXtarget# umount /debug target# rmmod rpmsg_proto target# rmmod virtio_rpmsg_bus target# rmmod da8xx_remoteproc target# rmmod remoteprocjjXjj\Sjjj}rY(j@jAj]j]j]j]j]ujM=jhj]rYjXtarget# umount /debug target# rmmod rpmsg_proto target# rmmod virtio_rpmsg_bus target# rmmod da8xx_remoteproc target# rmmod remoteprocrYrY}rY(jUjjYubaubjhK)rY}rY(jXOMAP54XXrYjjXjj\SjjlKj}rY(j]rYUomap54xxrYaj]j]j]j]rYj aujNjhj]rYjXOMAP54XXrYrY}rY(jjYjjYubaubj)rY}rY(jXeOn OMAP54XX, the kernel modules can be loaded with the following command on the target's file-system:rYjjXjj\Sjjj}rY(j]j]j]j]j]ujMjhj]rYjXeOn OMAP54XX, the kernel modules can be loaded with the following command on the target's file-system:rYrY}rY(jjYjjYubaubj)rY}rY(jXtarget# depmod -a target# mount -t debugfs none /debug target# modprobe remoteproc target# modprobe omap_remoteproc target# modprobe virtio_rpmsg_bus target# modprobe rpmsg_protojjXjj\Sjjj}rY(j@jAj]j]j]j]j]ujMKjhj]rYjXtarget# depmod -a target# mount -t debugfs none /debug target# modprobe remoteproc target# modprobe omap_remoteproc target# modprobe virtio_rpmsg_bus target# modprobe rpmsg_protorYrY}rY(jUjjYubaubeubj)rY}rY(jUjKjj Xjj\Sjjj}rY(j]rYXrunning test applicationsrYaj]j]j]rYUrunning-test-applicationsrYaj]ujMjhj]rY(j)rY}rY(jXRunning Test ApplicationsrYjjYjj\Sjjj}rY(j]j]j]j]j]ujMjhj]rYjXRunning Test ApplicationsrYrY}rY(jjYjjYubaubj)rY}rY(jXThe test applications are already on the target's filesystem in /usr/bin assuming the `#Installing Tests `__ section has been followed.jjYjj\Sjjj}rY(j]j]j]j]j]ujMjhj]rY(jXVThe test applications are already on the target's filesystem in /usr/bin assuming the rYrY}rY(jXVThe test applications are already on the target's filesystem in /usr/bin assuming the jjYubj)rY}rY(jXK`#Installing Tests `__j}rY(UnameX#Installing TestsjX3index_Foundational_Components.html#installing-testsj]j]j]j]j]ujjYj]rYjX#Installing TestsrYrY}rY(jUjjYubajjubjX section has been followed.rYrY}rY(jX section has been followed.jjYubeubj)rY}rY(jXPTo run the test application's, execute the following on the target's filesystem:rYjjYjj\Sjjj}rY(j]j]j]j]j]ujMjhj]rYjXPTo run the test application's, execute the following on the target's filesystem:rYrY}rY(jjYjjYubaubj)rY}rY(jX%target# /usr/bin/MessageQApp_jjYjj\Sjjj}rY(j@jAj]j]j]j]j]ujM^jhj]rYjX%target# /usr/bin/MessageQApp_rYrY}rY(jUjjYubaubjhK)rY}rY(jX OMAP-L138rYjjYjj\SjjlKj}rY(j]rYU omap-l138-2rYaj]j]j]j]rYh2aujNjhj]rYjX OMAP-L138rYrY}rY(jjYjjYubaubj)rY}rY(jX0The expected output on the Linux-side should be:rYjjYjj\Sjjj}rY(j]j]j]j]j]ujMjhj]rYjX0The expected output on the Linux-side should be:rYrY}rY(jjYjjYubaubj)rY}rY(jXUsing numLoops: 100; procId : 1 Entered MessageQApp_execute Local MessageQId: 0x1 Remote queueId [0x10000] Exchanging 100 messages with remote processor DSP... MessageQ_get #0 Msg = 0x15328 Exchanged 1 messages with remote processor DSP MessageQ_get #1 Msg = 0x15328 ... ... Exchanged 99 messages with remote processor DSP MessageQ_get #99 Msg = 0x15328 Exchanged 100 messages with remote processor DSP Sample application successfully completed! Leaving MessageQApp_executejjYjj\Sjjj}rY(j@jAj]j]j]j]j]ujMgjhj]rYjXUsing numLoops: 100; procId : 1 Entered MessageQApp_execute Local MessageQId: 0x1 Remote queueId [0x10000] Exchanging 100 messages with remote processor DSP... MessageQ_get #0 Msg = 0x15328 Exchanged 1 messages with remote processor DSP MessageQ_get #1 Msg = 0x15328 ... ... Exchanged 99 messages with remote processor DSP MessageQ_get #99 Msg = 0x15328 Exchanged 100 messages with remote processor DSP Sample application successfully completed! Leaving MessageQApp_executerYrY}rY(jUjjYubaubj)rY}rY(jXfThe output on the remote processor, can be obtained by running the following on the target filesystem:rYjjYjj\Sjjj}rY(j]j]j]j]j]ujMjhj]rYjXfThe output on the remote processor, can be obtained by running the following on the target filesystem:rYrY}rY(jjYjjYubaubj)rY}rY(jX0target# cat /debug/remoteproc/remoteproc0/trace0jjYjj\Sjjj}rY(j@jAj]j]j]j]j]ujM|jhj]rYjX0target# cat /debug/remoteproc/remoteproc0/trace0rYrY}rY(jUjjYubaubj)rY}rY(jX6The expected output on the remote processor should be:rYjjYjj\Sjjj}rY(j]j]j]j]j]ujMjhj]rYjX6The expected output on the remote processor should be:rZrZ}rZ(jjYjjYubaubj)rZ}rZ(jX3 Resource entries at 0xc3100000 messageq_single.c:main: MultiProc id = 1 registering rpmsg-proto service on 61 with HOST tsk1Fxn: created MessageQ: SLAVE_DSP; QueueID: 0x10000 Awaiting sync message from host... [t=0x00000001:67984156] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_send: no object for endpoint: 53 [t=0x00000001:67f626ed] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_send: no object for endpoint: 53 Received msg from (procId:remoteQueueId): 0x0:0x1 payload: 8 bytes; loops: 100 with printing. Got msg #0 (40 bytes) from procId 0 Sending msg Id #0 to procId 0 Got msg #1 (40 bytes) from procId 0 Sending msg Id #1 to procId 0 ... ... Got msg #98 (40 bytes) from procId 0 Sending msg Id #98 to procId 0 Got msg #99 (40 bytes) from procId 0 Sending msg Id #99 to procId 0 Awaiting sync message from host... [t=0x00000015:7b46c4c2] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_send: no object for endpoint: 53 [t=0x00000015:7b6315fb] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_send: no object for endpoint: 53jjYjj\Sjjj}rZ(j@jAj]j]j]j]j]ujMjhj]rZjX3 Resource entries at 0xc3100000 messageq_single.c:main: MultiProc id = 1 registering rpmsg-proto service on 61 with HOST tsk1Fxn: created MessageQ: SLAVE_DSP; QueueID: 0x10000 Awaiting sync message from host... [t=0x00000001:67984156] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_send: no object for endpoint: 53 [t=0x00000001:67f626ed] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_send: no object for endpoint: 53 Received msg from (procId:remoteQueueId): 0x0:0x1 payload: 8 bytes; loops: 100 with printing. Got msg #0 (40 bytes) from procId 0 Sending msg Id #0 to procId 0 Got msg #1 (40 bytes) from procId 0 Sending msg Id #1 to procId 0 ... ... Got msg #98 (40 bytes) from procId 0 Sending msg Id #98 to procId 0 Got msg #99 (40 bytes) from procId 0 Sending msg Id #99 to procId 0 Awaiting sync message from host... [t=0x00000015:7b46c4c2] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_send: no object for endpoint: 53 [t=0x00000015:7b6315fb] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_send: no object for endpoint: 53rZrZ}r Z(jUjjZubaubeubeubeubj)r Z}r Z(jUjKjjJSjj\Sjjj}r Z(j]r ZjRaj]j]j]rZUid55rZaj]ujMjhj]rZ(j)rZ}rZ(jXSee AlsorZjj Zjj\Sjjj}rZ(j]j]j]j]j]ujMjhj]rZjXSee AlsorZrZ}rZ(jjZjjZubaubjt)rZ}rZ(jUjj Zjj\Sjjwj}rZ(jyX-j]j]j]j]j]ujMjhj]rZ(j{)rZ}rZ(jX8`IPC 3.x `__rZjjZjj\Sjjj}r Z(j]j]j]j]j]ujNjhj]r!Zj)r"Z}r#Z(jjZjjZjj\Sjjj}r$Z(j]j]j]j]j]ujMj]r%Zj)r&Z}r'Z(jjZj}r(Z(UnameXIPC 3.xjX*index_Foundational_Components.html#ipc-3-xj]j]j]j]j]ujj"Zj]r)ZjXIPC 3.xr*Zr+Z}r,Z(jUjj&Zubajjubaubaubj{)r-Z}r.Z(jXG`IPC Users Guide `__r/ZjjZjj\Sjjj}r0Z(j]j]j]j]j]ujNjhj]r1Zj)r2Z}r3Z(jj/Zjj-Zjj\Sjjj}r4Z(j]j]j]j]j]ujMj]r5Zj)r6Z}r7Z(jj/Zj}r8Z(UnameXIPC Users GuidejX1index_Foundational_Components.html#ipc-user-guidej]j]j]j]j]ujj2Zj]r9ZjXIPC Users Guider:Zr;Z}rZ(jX<`IPC 3.x FAQ `__r?ZjjZjj\Sjjj}r@Z(j]j]j]j]j]ujNjhj]rAZj)rBZ}rCZ(jj?Zjj=Zjj\Sjjj}rDZ(j]j]j]j]j]ujMj]rEZj)rFZ}rGZ(jj?Zj}rHZ(UnameX IPC 3.x FAQjX*index_Foundational_Components.html#ipc-faqj]j]j]j]j]ujjBZj]rIZjX IPC 3.x FAQrJZrKZ}rLZ(jUjjFZubajjubaubaubj{)rMZ}rNZ(jXP`IPC Install Guide QNX `__rOZjjZjj\Sjjj}rPZ(j]j]j]j]j]ujNjhj]rQZj)rRZ}rSZ(jjOZjjMZjj\Sjjj}rTZ(j]j]j]j]j]ujMj]rUZj)rVZ}rWZ(jjOZj}rXZ(UnameXIPC Install Guide QNXjX4index_Foundational_Components.html#qnx-install-guidej]j]j]j]j]ujjRZj]rYZjXIPC Install Guide QNXrZZr[Z}r\Z(jUjjVZubajjubaubaubj{)r]Z}r^Z(jXU`IPC Install Guide BIOS `__ jjZjX\internal padding after source/rtos/PDK_Platform_Software/IPC/IPC_Install_Guide_Linux.rst.incr_Zjjj}r`Z(j]j]j]j]j]ujNjhj]raZj)rbZ}rcZ(jXR`IPC Install Guide BIOS `__rdZjj]Zjj\Sjjj}reZ(j]j]j]j]j]ujMj]rfZj)rgZ}rhZ(jjdZj}riZ(UnameXIPC Install Guide BIOSjX5index_Foundational_Components.html#bios-install-guidej]j]j]j]j]ujjbZj]rjZjXIPC Install Guide BIOSrkZrlZ}rmZ(jUjjgZubajjubaubaubeubeubeubj)rnZ}roZ(jUjjTPjjjjj}rpZ(j]j]j]j]rqZUqnx-install-guiderrZaj]rsZjbaujKjhj]rtZ(j)ruZ}rvZ(jXQNX Install GuiderwZjjnZjjjjj}rxZ(j]j]j]j]j]ujKjhj]ryZjXQNX Install GuiderzZr{Z}r|Z(jjwZjjuZubaubj7)r}Z}r~Z(jX=http://processors.wiki.ti.com/index.php/IPC_Install_Guide_QNXjjnZjj:XCsource/rtos/PDK_Platform_Software/IPC/IPC_Install_Guide_QNX.rst.incrZrZ}rZbjj>j}rZ(j@jAj]j]j]j]j]ujKjhj]rZjX=http://processors.wiki.ti.com/index.php/IPC_Install_Guide_QNXrZrZ}rZ(jUjj}Zubaubj)rZ}rZ(jUjKjjnZjjZjjj}rZ(j]rZX introductionrZaj]j]j]rZUid56rZaj]ujKjhj]rZ(j)rZ}rZ(jX IntroductionrZjjZjjZjjj}rZ(j]j]j]j]j]ujKjhj]rZjX IntroductionrZrZ}rZ(jjZjjZubaubj)rZ}rZ(jXInter/Intra Processor Communication (IPC) is a product designed to enable communication between processors in a multi-processor environment. Features of IPC include message passing, multi-processor gates, shared memory primitives, and more.rZjjZjjZjjj}rZ(j]j]j]j]j]ujKjhj]rZjXInter/Intra Processor Communication (IPC) is a product designed to enable communication between processors in a multi-processor environment. Features of IPC include message passing, multi-processor gates, shared memory primitives, and more.rZrZ}rZ(jjZjjZubaubj)rZ}rZ(jX<IPC is designed for use with processors running SYS/BIOS applications. This is typically an ARM or DSP. IPC includes support for High Level Operating Systems (HLOS) like Linux, as well as the SYS/BIOS RTOS. The breadth of IPC features supported in an HLOS environment is reduced in an effort to simplify the product.rZjjZjjZjjj}rZ(j]j]j]j]j]ujK jhj]rZjX<IPC is designed for use with processors running SYS/BIOS applications. This is typically an ARM or DSP. IPC includes support for High Level Operating Systems (HLOS) like Linux, as well as the SYS/BIOS RTOS. The breadth of IPC features supported in an HLOS environment is reduced in an effort to simplify the product.rZrZ}rZ(jjZjjZubaubeubj)rZ}rZ(jUjKjjnZjjZjjj}rZ(j]rZXinstallrZaj]j]j]rZUid57rZaj]ujKjhj]rZ(j)rZ}rZ(jXInstallrZjjZjjZjjj}rZ(j]j]j]j]j]ujKjhj]rZjXInstallrZrZ}rZ(jjZjjZubaubj)rZ}rZ(jXhIPC is often distributed and installed within a larger SDK. In those cases, no installation is required.rZjjZjjZjjj}rZ(j]j]j]j]j]ujKjhj]rZjXhIPC is often distributed and installed within a larger SDK. In those cases, no installation is required.rZrZ}rZ(jjZjjZubaubj)rZ}rZ(jXOutside of an SDK, `IPC can be downloaded here `__, and is released as a zip file. To install, simply extract the file.jjZjjZjjj}rZ(j]j]j]j]j]ujKjhj]rZ(jXOutside of an SDK, rZrZ}rZ(jXOutside of an SDK, jjZubj)rZ}rZ(jXr`IPC can be downloaded here `__j}rZ(UnameXIPC can be downloaded herejXQhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/index.htmlj]j]j]j]j]ujjZj]rZjXIPC can be downloaded hererZrZ}rZ(jUjjZubajjubjXE, and is released as a zip file. To install, simply extract the file.rZrZ}rZ(jXE, and is released as a zip file. To install, simply extract the file.jjZubeubj)rZ}rZ(jX"buildhost$ unzip ipc_.zipjjZjjZjjj}rZ(j@jAj]j]j]j]j]ujMjhj]rZjX"buildhost$ unzip ipc_.ziprZrZ}rZ(jUjjZubaubj)rZ}rZ(jX}This will extract the IPC product in a directory with its product name and version information (e.g. **c:/ti/ipc_**)jjZjjZjjj}rZ(j]j]j]j]j]ujKjhj]rZ(jXeThis will extract the IPC product in a directory with its product name and version information (e.g. rZrZ}rZ(jXeThis will extract the IPC product in a directory with its product name and version information (e.g. jjZubj)rZ}rZ(jX**c:/ti/ipc_**j}rZ(j]j]j]j]j]ujjZj]rZjXc:/ti/ipc_rZrZ}rZ(jUjjZubajjubjX)rZ}rZ(jX)jjZubeubj)rZ}rZ(jXE- This document assumes the IPC install path to be the user's home directory on a Linux host machine (**/home/**) or the user's main drive on a Windows host machine (**C:\\**). The variable **IPC_INSTALL_DIR** will be used throughout the document. If IPC was installed at a different location, make appropriate changes to commands. - Some customers find value in archiving the released sources in a configuration management system. This can help in identifying any changes made to the original sources - often useful when updating to newer releases.jjZjNjjj}rZ(j]j]j]j]j]ujNjhj]rZjt)rZ}rZ(jUj}rZ(jyX-j]j]j]j]j]ujjZj]rZ(j{)rZ}rZ(jXOThis document assumes the IPC install path to be the user's home directory on a Linux host machine (**/home/**) or the user's main drive on a Windows host machine (**C:\\**). The variable **IPC_INSTALL_DIR** will be used throughout the document. If IPC was installed at a different location, make appropriate changes to commands.j}rZ(j]j]j]j]j]ujjZj]rZj)rZ}rZ(jXOThis document assumes the IPC install path to be the user's home directory on a Linux host machine (**/home/**) or the user's main drive on a Windows host machine (**C:\\**). The variable **IPC_INSTALL_DIR** will be used throughout the document. If IPC was installed at a different location, make appropriate changes to commands.jjZjjZjjj}rZ(j]j]j]j]j]ujK$j]rZ(jXdThis document assumes the IPC install path to be the user's home directory on a Linux host machine (rZrZ}rZ(jXdThis document assumes the IPC install path to be the user's home directory on a Linux host machine (jjZubj)rZ}rZ(jX**/home/**j}rZ(j]j]j]j]j]ujjZj]rZjX /home/rZrZ}r[(jUjjZubajjubjX6) or the user's main drive on a Windows host machine (r[r[}r[(jX6) or the user's main drive on a Windows host machine (jjZubj)r[}r[(jX**C:\\**j}r[(j]j]j]j]j]ujjZj]r[jXC:\r[r [}r [(jUjj[ubajjubjX). The variable r [r [}r [(jX). The variable jjZubj)r[}r[(jX**IPC_INSTALL_DIR**j}r[(j]j]j]j]j]ujjZj]r[jXIPC_INSTALL_DIRr[r[}r[(jUjj[ubajjubjXz will be used throughout the document. If IPC was installed at a different location, make appropriate changes to commands.r[r[}r[(jXz will be used throughout the document. If IPC was installed at a different location, make appropriate changes to commands.jjZubeubajjubj{)r[}r[(jXSome customers find value in archiving the released sources in a configuration management system. This can help in identifying any changes made to the original sources - often useful when updating to newer releases.j}r[(j]j]j]j]j]ujjZj]r)r[}r[(jXSome customers find value in archiving the released sources in a configuration management system. This can help in identifying any changes made to the original sources - often useful when updating to newer releases.r[jj[jjZjjj}r[(j]j]j]j]j]ujK*j]r [jXSome customers find value in archiving the released sources in a configuration management system. This can help in identifying any changes made to the original sources - often useful when updating to newer releases.r![r"[}r#[(jj[jj[ubaubajjubejjwubaubeubj)r$[}r%[(jUjKjjnZjjZjjj}r&[(j]r'[Xbuildr([aj]j]j]r)[Uid58r*[aj]ujK0jhj]r+[(j)r,[}r-[(jXBuildr.[jj$[jjZjjj}r/[(j]j]j]j]j]ujK0jhj]r0[jXBuildr1[r2[}r3[(jj.[jj,[ubaubj)r4[}r5[(jXThe IPC product often comes with prebuilt SYS/BIOS-side libraries, so rebuilding them isn't necessary. The QNX-side libraries/binaries may also be provided prebuilt by SDK programs, but the standalone IPC release does not currently pre-build them.r6[jj$[jjZjjj}r7[(j]j]j]j]j]ujK2jhj]r8[jXThe IPC product often comes with prebuilt SYS/BIOS-side libraries, so rebuilding them isn't necessary. The QNX-side libraries/binaries may also be provided prebuilt by SDK programs, but the standalone IPC release does not currently pre-build them.r9[r:[}r;[(jj6[jj4[ubaubj)r<[}r=[(jXhIPC provides GNU makefile(s) to rebuild all its libraries at the base of the product, details are below.r>[jj$[jjZjjj}r?[(j]j]j]j]j]ujK7jhj]r@[jXhIPC provides GNU makefile(s) to rebuild all its libraries at the base of the product, details are below.rA[rB[}rC[(jj>[jj<[ubaubj)rD[}rE[(jXGNU make version 3.81 or greater is required. The XDC tools (provided with most SDKs and CCS distributions) includes a pre-compiled version of GNU make 3.81 in $(XDC_INSTALL_DIR)/gmake.jj$[jjZjjj}rF[(j]j]j]j]j]ujNjhj]rG[j)rH[}rI[(jXGNU make version 3.81 or greater is required. The XDC tools (provided with most SDKs and CCS distributions) includes a pre-compiled version of GNU make 3.81 in $(XDC_INSTALL_DIR)/gmake.rJ[jjD[jjZjjj}rK[(j]j]j]j]j]ujK;j]rL[jXGNU make version 3.81 or greater is required. The XDC tools (provided with most SDKs and CCS distributions) includes a pre-compiled version of GNU make 3.81 in $(XDC_INSTALL_DIR)/gmake.rM[rN[}rO[(jjJ[jjH[ubaubaubj)rP[}rQ[(jUjKjj$[jjZjjj}rR[(j]rS[X products.makrT[aj]j]j]rU[Uid59rV[aj]ujK@jhj]rW[(j)rX[}rY[(jX products.makrZ[jjP[jjZjjj}r[[(j]j]j]j]j]ujK@jhj]r\[jX products.makr][r^[}r_[(jjZ[jjX[ubaubj)r`[}ra[(jXIPC contains a **products.mak** file at the root of the product that specifies the necessary paths and options to build IPC for the various OS support.jjP[jjZjjj}rb[(j]j]j]j]j]ujKBjhj]rc[(jXIPC contains a rd[re[}rf[(jXIPC contains a jj`[ubj)rg[}rh[(jX**products.mak**j}ri[(j]j]j]j]j]ujj`[j]rj[jX products.makrk[rl[}rm[(jUjjg[ubajjubjXx file at the root of the product that specifies the necessary paths and options to build IPC for the various OS support.rn[ro[}rp[(jXx file at the root of the product that specifies the necessary paths and options to build IPC for the various OS support.jj`[ubeubj)rq[}rr[(jX6Edit **products.mak** and set the following variables:rs[jjP[jjZjjj}rt[(j]j]j]j]j]ujKFjhj]ru[(jXEdit rv[rw[}rx[(jXEdit jjq[ubj)ry[}rz[(jX**products.mak**j}r{[(j]j]j]j]j]ujjq[j]r|[jX products.makr}[r~[}r[(jUjjy[ubajjubjX! and set the following variables:r[r[}r[(jX! and set the following variables:jjq[ubeubjt)r[}r[(jUjjP[jjZjjwj}r[(jyX-j]j]j]j]j]ujKHjhj]r[(j{)r[}r[(jXVariables used by both QNX and BIOS - **PLATFORM** - Device to build for - QNX started using this variable in IPC 3.20. Prior releases required setting "DEVICE" for QNX and "PLATFORM" for BIOS. The two variables were consolidated in IPC 3.20. - BIOS started leveraging this variable in IPC 3.10. Prior releases built BIOS-side executables for **all** supported platforms based on that targets/toolchains set above (which can take a while!) jj[jNjjj}r[(j]j]j]j]j]ujNjhj]r[(j)r[}r[(jX#Variables used by both QNX and BIOSr[jj[jjZjjj}r[(j]j]j]j]j]ujKHj]r[jX#Variables used by both QNX and BIOSr[r[}r[(jj[jj[ubaubjt)r[}r[(jUj}r[(jyX-j]j]j]j]j]ujj[j]r[j{)r[}r[(jX**PLATFORM** - Device to build for - QNX started using this variable in IPC 3.20. Prior releases required setting "DEVICE" for QNX and "PLATFORM" for BIOS. The two variables were consolidated in IPC 3.20. - BIOS started leveraging this variable in IPC 3.10. Prior releases built BIOS-side executables for **all** supported platforms based on that targets/toolchains set above (which can take a while!) j}r[(j]j]j]j]j]ujj[j]r[(j)r[}r[(jX"**PLATFORM** - Device to build forjj[jjZjjj}r[(j]j]j]j]j]ujKJj]r[(j)r[}r[(jX **PLATFORM**j}r[(j]j]j]j]j]ujj[j]r[jXPLATFORMr[r[}r[(jUjj[ubajjubjX - Device to build forr[r[}r[(jX - Device to build forjj[ubeubjt)r[}r[(jUj}r[(jyX-j]j]j]j]j]ujj[j]r[(j{)r[}r[(jXQNX started using this variable in IPC 3.20. Prior releases required setting "DEVICE" for QNX and "PLATFORM" for BIOS. The two variables were consolidated in IPC 3.20.j}r[(j]j]j]j]j]ujj[j]r[j)r[}r[(jXQNX started using this variable in IPC 3.20. Prior releases required setting "DEVICE" for QNX and "PLATFORM" for BIOS. The two variables were consolidated in IPC 3.20.r[jj[jjZjjj}r[(j]j]j]j]j]ujKLj]r[jXQNX started using this variable in IPC 3.20. Prior releases required setting "DEVICE" for QNX and "PLATFORM" for BIOS. The two variables were consolidated in IPC 3.20.r[r[}r[(jj[jj[ubaubajjubj{)r[}r[(jXBIOS started leveraging this variable in IPC 3.10. Prior releases built BIOS-side executables for **all** supported platforms based on that targets/toolchains set above (which can take a while!) j}r[(j]j]j]j]j]ujj[j]r[j)r[}r[(jXBIOS started leveraging this variable in IPC 3.10. Prior releases built BIOS-side executables for **all** supported platforms based on that targets/toolchains set above (which can take a while!)jj[jjZjjj}r[(j]j]j]j]j]ujKOj]r[(jXbBIOS started leveraging this variable in IPC 3.10. Prior releases built BIOS-side executables for r[r[}r[(jXbBIOS started leveraging this variable in IPC 3.10. Prior releases built BIOS-side executables for jj[ubj)r[}r[(jX**all**j}r[(j]j]j]j]j]ujj[j]r[jXallr[r[}r[(jUjj[ubajjubjXY supported platforms based on that targets/toolchains set above (which can take a while!)r[r[}r[(jXY supported platforms based on that targets/toolchains set above (which can take a while!)jj[ubeubajjubejjwubejjubajjwubeubj{)r[}r[(jXQNX - **QNX_INSTALL_DIR** - Path to your QNX installation directory. - **DESTDIR** - Path to which target binaries will be exported when running the 'make install' goal. - **DEVICE** - (only required for releases prior to IPC 3.20) Device to build for jj[jNjjj}r[(j]j]j]j]j]ujNjhj]r[(j)r[}r[(jXQNXr[jj[jjZjjj}r[(j]j]j]j]j]ujKTj]r[jXQNXr[r[}r[(jj[jj[ubaubjt)r[}r[(jUj}r[(jyX-j]j]j]j]j]ujj[j]r[(j{)r[}r[(jX>**QNX_INSTALL_DIR** - Path to your QNX installation directory.r[j}r[(j]j]j]j]j]ujj[j]r[j)r[}r[(jj[jj[jjZjjj}r[(j]j]j]j]j]ujKVj]r[(j)r[}r[(jX**QNX_INSTALL_DIR**j}r[(j]j]j]j]j]ujj[j]r[jXQNX_INSTALL_DIRr[r[}r[(jUjj[ubajjubjX+ - Path to your QNX installation directory.r[r[}r[(jX+ - Path to your QNX installation directory.jj[ubeubajjubj{)r[}r[(jXb**DESTDIR** - Path to which target binaries will be exported when running the 'make install' goal.j}r[(j]j]j]j]j]ujj[j]r[j)r[}r[(jXb**DESTDIR** - Path to which target binaries will be exported when running the 'make install' goal.jj[jjZjjj}r[(j]j]j]j]j]ujKWj]r[(j)r[}r[(jX **DESTDIR**j}r[(j]j]j]j]j]ujj[j]r[jXDESTDIRr[r[}r[(jUjj[ubajjubjXW - Path to which target binaries will be exported when running the 'make install' goal.r\r\}r\(jXW - Path to which target binaries will be exported when running the 'make install' goal.jj[ubeubajjubj{)r\}r\(jXP**DEVICE** - (only required for releases prior to IPC 3.20) Device to build for j}r\(j]j]j]j]j]ujj[j]r\j)r\}r\(jXO**DEVICE** - (only required for releases prior to IPC 3.20) Device to build forjj\jjZjjj}r \(j]j]j]j]j]ujKYj]r \(j)r \}r \(jX **DEVICE**j}r \(j]j]j]j]j]ujj\j]r\jXDEVICEr\r\}r\(jUjj \ubajjubjXE - (only required for releases prior to IPC 3.20) Device to build forr\r\}r\(jXE - (only required for releases prior to IPC 3.20) Device to build forjj\ubeubajjubejjwubeubj{)r\}r\(jXSYS/BIOS - **XDC_INSTALL_DIR** - Path to TI's XDCTools installation - **BIOS_INSTALL_DIR** - Path to TI's SYS/BIOS installation - **ti.targets.** - Path to TI toolchain for the device. - Set only the variables to the targets your device supports to minimize build time. - **gnu.targets.arm.** - Path to GNU toolchain for the device. - Set only the variables to the targets your device supports to minimize build time. jj[jNjjj}r\(j]j]j]j]j]ujNjhj]r\(j)r\}r\(jXSYS/BIOSr\jj\jjZjjj}r\(j]j]j]j]j]ujK\j]r\jXSYS/BIOSr\r\}r \(jj\jj\ubaubjt)r!\}r"\(jUj}r#\(jyX-j]j]j]j]j]ujj\j]r$\(j{)r%\}r&\(jX8**XDC_INSTALL_DIR** - Path to TI's XDCTools installationr'\j}r(\(j]j]j]j]j]ujj!\j]r)\j)r*\}r+\(jj'\jj%\jjZjjj}r,\(j]j]j]j]j]ujK^j]r-\(j)r.\}r/\(jX**XDC_INSTALL_DIR**j}r0\(j]j]j]j]j]ujj*\j]r1\jXXDC_INSTALL_DIRr2\r3\}r4\(jUjj.\ubajjubjX% - Path to TI's XDCTools installationr5\r6\}r7\(jX% - Path to TI's XDCTools installationjj*\ubeubajjubj{)r8\}r9\(jX9**BIOS_INSTALL_DIR** - Path to TI's SYS/BIOS installationr:\j}r;\(j]j]j]j]j]ujj!\j]r<\j)r=\}r>\(jj:\jj8\jjZjjj}r?\(j]j]j]j]j]ujK_j]r@\(j)rA\}rB\(jX**BIOS_INSTALL_DIR**j}rC\(j]j]j]j]j]ujj=\j]rD\jXBIOS_INSTALL_DIRrE\rF\}rG\(jUjjA\ubajjubjX% - Path to TI's SYS/BIOS installationrH\rI\}rJ\(jX% - Path to TI's SYS/BIOS installationjj=\ubeubajjubj{)rK\}rL\(jX**ti.targets.** - Path to TI toolchain for the device. - Set only the variables to the targets your device supports to minimize build time. j}rM\(j]j]j]j]j]ujj!\j]rN\(j)rO\}rP\(jXU**ti.targets.** - Path to TI toolchain for the device.jjK\jjZjjj}rQ\(j]j]j]j]j]ujK`j]rR\(j)rS\}rT\(jX.**ti.targets.**j}rU\(j]j]j]j]j]ujjO\j]rV\jX*ti.targets.rW\rX\}rY\(jUjjS\ubajjubjX' - Path to TI toolchain for the device.rZ\r[\}r\\(jX' - Path to TI toolchain for the device.jjO\ubeubjt)r]\}r^\(jUj}r_\(jyX-j]j]j]j]j]ujjK\j]r`\j{)ra\}rb\(jXSSet only the variables to the targets your device supports to minimize build time. j}rc\(j]j]j]j]j]ujj]\j]rd\j)re\}rf\(jXRSet only the variables to the targets your device supports to minimize build time.rg\jja\jjZjjj}rh\(j]j]j]j]j]ujKcj]ri\jXRSet only the variables to the targets your device supports to minimize build time.rj\rk\}rl\(jjg\jje\ubaubajjubajjwubejjubj{)rm\}rn\(jX**gnu.targets.arm.** - Path to GNU toolchain for the device. - Set only the variables to the targets your device supports to minimize build time. j}ro\(j]j]j]j]j]ujj!\j]rp\(j)rq\}rr\(jX[**gnu.targets.arm.** - Path to GNU toolchain for the device.jjm\jjZjjj}rs\(j]j]j]j]j]ujKfj]rt\(j)ru\}rv\(jX3**gnu.targets.arm.**j}rw\(j]j]j]j]j]ujjq\j]rx\jX/gnu.targets.arm.ry\rz\}r{\(jUjju\ubajjubjX( - Path to GNU toolchain for the device.r|\r}\}r~\(jX( - Path to GNU toolchain for the device.jjq\ubeubjt)r\}r\(jUj}r\(jyX-j]j]j]j]j]ujjm\j]r\j{)r\}r\(jXSSet only the variables to the targets your device supports to minimize build time. j}r\(j]j]j]j]j]ujj\j]r\j)r\}r\(jXRSet only the variables to the targets your device supports to minimize build time.r\jj\jjZjjj}r\(j]j]j]j]j]ujKij]r\jXRSet only the variables to the targets your device supports to minimize build time.r\r\}r\(jj\jj\ubaubajjubajjwubejjubejjwubeubeubj)r\}r\(jXbThe versions used during validation can be found in the IPC Release Notes provided in the product.jjP[jjZjjj}r\(j]j]j]j]j]ujNjhj]r\j)r\}r\(jXbThe versions used during validation can be found in the IPC Release Notes provided in the product.r\jj\jjZjjj}r\(j]j]j]j]j]ujKmj]r\jXbThe versions used during validation can be found in the IPC Release Notes provided in the product.r\r\}r\(jj\jj\ubaubaubjhK)r\}r\(jX ipc-qnx.makr\jjP[jjZjjlKj}r\(j]r\U ipc-qnx-makr\aj]j]j]j]r\hzaujNjhj]r\jX ipc-qnx.makr\r\}r\(jj\jj\ubaubj)r\}r\(jXThe QNX-side build is performed using QNX makefiles. To build using the components paths set in the **products.mak** file, issue the following command:jjP[jjZjjj}r\(j]j]j]j]j]ujKsjhj]r\(jXdThe QNX-side build is performed using QNX makefiles. To build using the components paths set in the r\r\}r\(jXdThe QNX-side build is performed using QNX makefiles. To build using the components paths set in the jj\ubj)r\}r\(jX**products.mak**j}r\(j]j]j]j]j]ujj\j]r\jX products.makr\r\}r\(jUjj\ubajjubjX# file, issue the following command:r\r\}r\(jX# file, issue the following command:jj\ubeubj)r\}r\(jX# make -f ipc-qnx.mak alljjP[jjZjjj}r\(j@jAj]j]j]j]j]ujM"jhj]r\jX# make -f ipc-qnx.mak allr\r\}r\(jUjj\ubaubeubj)r\}r\(jUjKjj$[jjZjjj}r\(j]r\X ipc-bios.makr\aj]j]j]r\Uid60r\aj]ujK|jhj]r\(j)r\}r\(jX ipc-bios.makr\jj\jjZjjj}r\(j]j]j]j]j]ujK|jhj]r\jX ipc-bios.makr\r\}r\(jj\jj\ubaubj)r\}r\(jXpThe SYS/BIOS-side IPC is built with a GNU makefile. After editing **products.mak**, issue the following command:jj\jjZjjj}r\(j]j]j]j]j]ujK~jhj]r\(jXBThe SYS/BIOS-side IPC is built with a GNU makefile. After editing r\r\}r\(jXBThe SYS/BIOS-side IPC is built with a GNU makefile. After editing jj\ubj)r\}r\(jX**products.mak**j}r\(j]j]j]j]j]ujj\j]r\jX products.makr\r\}r\(jUjj\ubajjubjX, issue the following command:r\r\}r\(jX, issue the following command:jj\ubeubj)r\}r\(jX$ make -f ipc-bios.mak alljj\jjZjjj}r\(j@jAj]j]j]j]j]ujM,jhj]r\jX$ make -f ipc-bios.mak allr\r\}r\(jUjj\ubaubj)r\}r\(jXLBased on the number of targets you're building for, this may take some time.r\jj\jjZjjj}r\(j]j]j]j]j]ujKjhj]r\jXLBased on the number of targets you're building for, this may take some time.r\r\}r\(jj\jj\ubaubj)r\}r\(jX **Note for Windows users:** If you are building with a Windows host machine and it has the QNX tools installed, you will instead need to run the following in a separate command prompt window (cmd.exe) to build the SYS/BIOS side outside of the QNX build environment:jj\jjZjjj}r\(j]j]j]j]j]ujKjhj]r\(j)r\}r\(jX**Note for Windows users:**j}r\(j]j]j]j]j]ujj\j]r\jXNote for Windows users:r\r\}r\(jUjj\ubajjubjX If you are building with a Windows host machine and it has the QNX tools installed, you will instead need to run the following in a separate command prompt window (cmd.exe) to build the SYS/BIOS side outside of the QNX build environment:r\r\}r\(jX If you are building with a Windows host machine and it has the QNX tools installed, you will instead need to run the following in a separate command prompt window (cmd.exe) to build the SYS/BIOS side outside of the QNX build environment:jj\ubeubj)r\}r\(jX set PATH=C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem \gmake -f ipc-bios.mak alljj\jjZjjj}r\(j@jAj]j]j]j]j]ujM8jhj]r\jX set PATH=C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem \gmake -f ipc-bios.mak allr]r]}r](jUjj\ubaubj)r]}r](jXwhere should be replaced with the installation directory of your XDC tools, same as the path you have used in products.mak.r]jj\jjZjjj}r](j]j]j]j]j]ujKjhj]r]jXwhere should be replaced with the installation directory of your XDC tools, same as the path you have used in products.mak.r]r ]}r ](jj]jj]ubaubeubeubj)r ]}r ](jUjKjjnZjjZjjj}r ](j]r]Xrunr]aj]j]j]r]Uid61r]aj]ujKjhj]r](j)r]}r](jXRunr]jj ]jjZjjj}r](j]j]j]j]j]ujKjhj]r]jXRunr]r]}r](jj]jj]ubaubj)r]}r](jXThe IPC product provides a way to install (copy) the necessary IPC executables and libraries onto the device's target file-system to simplify the execution of the applications. The details can vary across OS's, so this description has been separated into OS-specific sections.r]jj ]jjZjjj}r](j]j]j]j]j]ujKjhj]r]jXThe IPC product provides a way to install (copy) the necessary IPC executables and libraries onto the device's target file-system to simplify the execution of the applications. The details can vary across OS's, so this description has been separated into OS-specific sections.r ]r!]}r"](jj]jj]ubaubj)r#]}r$](jUjj ]jjZjjj}r%](j]j]j]j]r&]Uconfiguring-the-bspr']aj]r(]j aujKjhj]r)](j)r*]}r+](jXConfiguring the BSPr,]jj#]jjZjjj}r-](j]j]j]j]j]ujKjhj]r.]jXConfiguring the BSPr/]r0]}r1](jj,]jj*]ubaubj)r2]}r3](jX4Some of the provided IPC tests that use a utility called SharedMemoryAllocator require a carveout to be created in the QNX-owned memory. To reserve this memory, you must make the following change in the file \src\hardware\startup\boards\\build in the QNX BSP. E.g.jj#]jjZjjj}r4](j]j]j]j]j]ujKjhj]r5]jX.Some of the provided IPC tests that use a utility called SharedMemoryAllocator require a carveout to be created in the QNX-owned memory. To reserve this memory, you must make the following change in the file srchardwarestartupboardsbuild in the QNX BSP. E.g.r6]r7]}r8](jX4Some of the provided IPC tests that use a utility called SharedMemoryAllocator require a carveout to be created in the QNX-owned memory. To reserve this memory, you must make the following change in the file \src\hardware\startup\boards\\build in the QNX BSP. E.g.jj2]ubaubj)r9]}r:](jX:startup-omap5432uevm -r 0xBA300000,0x5A00000 -vvvvv -P2 -Wjj#]jjZjjj}r;](j@jAj]j]j]j]j]ujMSjhj]r<]jX:startup-omap5432uevm -r 0xBA300000,0x5A00000 -vvvvv -P2 -Wr=]r>]}r?](jUjj9]ubaubj)r@]}rA](jXhSave the file, then rebuild the QNX OS image (ifs-*.bin) and replace your existing one with the new one.jj#]jjZjjj}rB](j]j]j]j]j]ujKjhj]rC](jX2Save the file, then rebuild the QNX OS image (ifs-rD]rE]}rF](jX2Save the file, then rebuild the QNX OS image (ifs-jj@]ubj )rG]}rH](jX*j}rI](j]rJ]Uid63rK]aj]j]j]j]UrefidUid62rL]ujj@]j]rM]jX*rN]}rO](jUjjG]ubajj ubjX5.bin) and replace your existing one with the new one.rP]rQ]}rR](jX5.bin) and replace your existing one with the new one.jj@]ubeubeubj)rS]}rT](jUjj ]jjZjjj}rU](j]j]j]j]rV]Uinstalling-tests-in-qnxrW]aj]rX]h aujKjhj]rY](j)rZ]}r[](jXInstalling Tests in QNXr\]jjS]jjZjjj}r]](j]j]j]j]j]ujKjhj]r^]jXInstalling Tests in QNXr_]r`]}ra](jj\]jjZ]ubaubj)rb]}rc](jXTo assemble the IPC resource manager, shared libraries and test executables into a directory structure suitable for running on the device's file-system, issue the following command in the IPC_INSTALL_DIR directory:rd]jjS]jjZjjj}re](j]j]j]j]j]ujKjhj]rf]jXTo assemble the IPC resource manager, shared libraries and test executables into a directory structure suitable for running on the device's file-system, issue the following command in the IPC_INSTALL_DIR directory:rg]rh]}ri](jjd]jjb]ubaubj)rj]}rk](jX&buildhost$ make -f ipc-qnx.mak installjjS]jjZjjj}rl](j@jAj]j]j]j]j]ujMbjhj]rm]jX&buildhost$ make -f ipc-qnx.mak installrn]ro]}rp](jUjjj]ubaubj)rq]}rr](jXThis will install the binaries into the directory specified by DESTDIR in products.mak. It this assumed that DESTDIR is a directory visible to the target filesystem. If not, you should copy its contents to such a location (e.g. onto an SD card that can be accessed by the EVM).rs]jjS]jjZjjj}rt](j]j]j]j]j]ujKjhj]ru]jXThis will install the binaries into the directory specified by DESTDIR in products.mak. It this assumed that DESTDIR is a directory visible to the target filesystem. If not, you should copy its contents to such a location (e.g. onto an SD card that can be accessed by the EVM).rv]rw]}rx](jjs]jjq]ubaubj)ry]}rz](jXgWhen building in Windows, some users might get build messages that report a version mismatch in cygwin:r{]jjS]jjZjjj}r|](j]j]j]j]j]ujKjhj]r}]jXgWhen building in Windows, some users might get build messages that report a version mismatch in cygwin:r~]r]}r](jj{]jjy]ubaubj)r]}r](jX}C:/QNX650/host/win32/x86/usr/bin/make -j 1 -Cle.v7 -fMakefile install 1 [main] ? (5984) C:\QNX650\host\win32\x86\usr\photon\bin\find.exe: *** fa tal error - system shared memory version mismatch detected - 0x8A88009C/0x2D1E009C. This problem is probably due to using incompatible versions of the cygwin DLL. Search for cygwin1.dll using the Windows Start->Find/Search facility and delete all but the most recent version. The most recent version *should* reside in x:\cygwin\bin, where 'x' is the drive on which you have installed the cygwin distribution. Rebooting is also suggested if you are unable to find another cygwin DLL.jjS]jjZjjj}r](j@jAj]j]j]j]j]ujMnjhj]r]jX}C:/QNX650/host/win32/x86/usr/bin/make -j 1 -Cle.v7 -fMakefile install 1 [main] ? (5984) C:\QNX650\host\win32\x86\usr\photon\bin\find.exe: *** fa tal error - system shared memory version mismatch detected - 0x8A88009C/0x2D1E009C. This problem is probably due to using incompatible versions of the cygwin DLL. Search for cygwin1.dll using the Windows Start->Find/Search facility and delete all but the most recent version. The most recent version *should* reside in x:\cygwin\bin, where 'x' is the drive on which you have installed the cygwin distribution. Rebooting is also suggested if you are unable to find another cygwin DLL.r]r]}r](jUjj]ubaubj)r]}r](jXFBased on what we observed the binaries are still exported correctly despite the messages. If you do want to eliminate them, you should replace the file cygwin1.dll in \host\win32\x86\usr\photon\bin with the newest cygwin1.dll you can find on your host machine (do a search on your PC's filesystem in Windows).jjS]jjZjjj}r](j]j]j]j]j]ujKjhj]r]jX@Based on what we observed the binaries are still exported correctly despite the messages. If you do want to eliminate them, you should replace the file cygwin1.dll in hostwin32x86usrphotonbin with the newest cygwin1.dll you can find on your host machine (do a search on your PC's filesystem in Windows).r]r]}r](jXFBased on what we observed the binaries are still exported correctly despite the messages. If you do want to eliminate them, you should replace the file cygwin1.dll in \host\win32\x86\usr\photon\bin with the newest cygwin1.dll you can find on your host machine (do a search on your PC's filesystem in Windows).jj]ubaubj)r]}r](jXHSome of the tests rely on corresponding remote core applications to be run on the slave processor(s). The remote processor's applications are loaded when launching the resource manager. See section `#IPC_resource_manager `__ for details on launching the resource manager.jjS]jjZjjj}r](j]j]j]j]j]ujKjhj]r](jXSome of the tests rely on corresponding remote core applications to be run on the slave processor(s). The remote processor's applications are loaded when launching the resource manager. See section r]r]}r](jXSome of the tests rely on corresponding remote core applications to be run on the slave processor(s). The remote processor's applications are loaded when launching the resource manager. See section jj]ubj)r]}r](jXS`#IPC_resource_manager `__j}r](UnameX#IPC_resource_managerjX7index_Foundational_Components.html#ipc-resource-managerj]j]j]j]j]ujj]j]r]jX#IPC_resource_managerr]r]}r](jUjj]ubajjubjX/ for details on launching the resource manager.r]r]}r](jX/ for details on launching the resource manager.jj]ubeubj)r]}r](jX[The location of the remote core applications within the IPC product varies based on device.r]jjS]jjZjjj}r](j]j]j]j]j]ujKjhj]r]jX[The location of the remote core applications within the IPC product varies based on device.r]r]}r](jj]jj]ubaubj)r]}r](jUjjS]jjZjjj}r](j]j]j]j]r]U#installing-remote-core-applicationsr]aj]r]j-aujKjhj]r](j)r]}r](jX#Installing remote core applicationsr]jj]jjZjjj}r](j]j]j]j]j]ujKjhj]r]jX#Installing remote core applicationsr]r]}r](jj]jj]ubaubj)r]}r](jXRemote core applications can be found in /packages/ti/ipc/tests/bin/ti_platform__\* directories.jj]jjZjjj}r](j]j]j]j]j]ujKjhj]r]jXRemote core applications can be found in /packages/ti/ipc/tests/bin/ti_platform__* directories.r]r]}r](jXRemote core applications can be found in /packages/ti/ipc/tests/bin/ti_platform__\* directories.jj]ubaubj)r]}r](jXFor example, you can copy the messageq_single.xem4 for OMAP54xx uEVM's IPU onto the device's target filesystem into the **bin** directory as follows:jj]jjZjjj}r](j]j]j]j]j]ujKjhj]r](jXxFor example, you can copy the messageq_single.xem4 for OMAP54xx uEVM's IPU onto the device's target filesystem into the r]r]}r](jXxFor example, you can copy the messageq_single.xem4 for OMAP54xx uEVM's IPU onto the device's target filesystem into the jj]ubj)r]}r](jX**bin**j}r](j]j]j]j]j]ujj]j]r]jXbinr]r]}r](jUjj]ubajjubjX directory as follows:r]r]}r](jX directory as follows:jj]ubeubj)r]}r](jXbuildhost$ copy /packages/ti/ipc/tests/bin/ti_platform_omap54xx_ipu/messageq_single.xem4 /armle-v7/binjj]jjZjjj}r](j@jAj]j]j]j]j]ujMjhj]r]jXbuildhost$ copy /packages/ti/ipc/tests/bin/ti_platform_omap54xx_ipu/messageq_single.xem4 /armle-v7/binr]r]}r](jUjj]ubaubj)r]}r](jX'ti_platform_omap54xx_ipu' indicates the platform is 'omap54xx' and the remote core name is 'IPU'. You only need to copy the binaries relevant to your platform.r]jj]jjZjjj}r](j]j]j]j]j]ujKjhj]r]jX'ti_platform_omap54xx_ipu' indicates the platform is 'omap54xx' and the remote core name is 'IPU'. You only need to copy the binaries relevant to your platform.r]r]}r](jj]jj]ubaubeubeubj)r]}r](jUjj ]jjZjjj}r](j]j]j]j]r]Uipc-resource-managerr]aj]r]haujKjhj]r](j)r]}r](jXIPC resource managerr]jj]jjZjjj}r](j]j]j]j]j]ujKjhj]r]jXIPC resource managerr]r]}r](jj]jj]ubaubj)r]}r](jXdMuch of the functionality of IPC is provided by the resource manager. It can be launched as follows:r]jj]jjZjjj}r](j]j]j]j]j]ujKjhj]r]jXdMuch of the functionality of IPC is provided by the resource manager. It can be launched as follows:r]r]}r](jj]jj]ubaubj)r]}r](jXtarget# cd /armle-v7/bin target# export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/armle-v7/usr/lib target# ipc ...jj]jjZjjj}r](j@jAj]j]j]j]j]ujMjhj]r]jXtarget# cd /armle-v7/bin target# export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/armle-v7/usr/lib target# ipc ...r]r]}r](jUjj]ubaubj)r]}r](jX  should correspond to the name of the remote core on which you want the remote executable to be loaded. As a rule of thumb, it is the capitalized version of the core name specified by the name of the directory from which the executable was copied in the `#Installing remote core applications `__ section. For example, if the executable is copied from "ti_platform_omap54xx\_**ipu**/test_omx_ipu_omap5.xem4", then you should load it as follows:jj]jjZjjj}r](j]j]j]j]j]ujKjhj]r](jX should correspond to the name of the remote core on which you want the remote executable to be loaded. As a rule of thumb, it is the capitalized version of the core name specified by the name of the directory from which the executable was copied in the r^r^}r^(jX should correspond to the name of the remote core on which you want the remote executable to be loaded. As a rule of thumb, it is the capitalized version of the core name specified by the name of the directory from which the executable was copied in the jj]ubj)r^}r^(jXq`#Installing remote core applications `__j}r^(UnameX$#Installing remote core applicationsjXFindex_Foundational_Components.html#installing-remote-core-applicationsj]j]j]j]j]ujj]j]r^jX$#Installing remote core applicationsr^r^}r ^(jUjj^ubajjubjX section. For example, if the executable is copied from "ti_platform_omap54xx_**ipu**/test_omx_ipu_omap5.xem4", then you should load it as follows:r ^r ^}r ^(jX section. For example, if the executable is copied from "ti_platform_omap54xx\_**ipu**/test_omx_ipu_omap5.xem4", then you should load it as follows:jj]ubeubj)r ^}r^(jX'target# ipc IPU test_omx_ipu_omap5.xem4jj]jjZjjj}r^(j@jAj]j]j]j]j]ujMjhj]r^jX'target# ipc IPU test_omx_ipu_omap5.xem4r^r^}r^(jUjj ^ubaubj)r^}r^(jXThe resource manager will register devices in the pathname space for communicating with the IPC. Communication with the IPC is only possible once the needed devices are registered. The following devices are registered by default when the IPC resource manager is launched:r^jj]jjZjjj}r^(j]j]j]j]j]ujM jhj]r^jXThe resource manager will register devices in the pathname space for communicating with the IPC. Communication with the IPC is only possible once the needed devices are registered. The following devices are registered by default when the IPC resource manager is launched:r^r^}r^(jj^jj^ubaubjy )r^}r^(jUjj]jjZjj j}r^(j]j]j]j]j]ujNjhj]r^j~ )r ^}r!^(jUj}r"^(j]j]j]j]j]UcolsKujj^j]r#^(j )r$^}r%^(jUj}r&^(j]j]j]j]j]UcolwidthK ujj ^j]jj ubj )r'^}r(^(jUj}r)^(j]j]j]j]j]UcolwidthK?ujj ^j]jj ubj )r*^}r+^(jUj}r,^(j]j]j]j]j]ujj ^j]r-^j )r.^}r/^(jUj}r0^(j]j]j]j]j]ujj*^j]r1^(j )r2^}r3^(jUj}r4^(j]j]j]j]j]ujj.^j]r5^j)r6^}r7^(jXDevicer8^jj2^jjZjjj}r9^(j]j]j]j]j]ujMj]r:^jXDevicer;^r<^}r=^(jj8^jj6^ubaubajj ubj )r>^}r?^(jUj}r@^(j]j]j]j]j]ujj.^j]rA^j)rB^}rC^(jX DescriptionrD^jj>^jjZjjj}rE^(j]j]j]j]j]ujMj]rF^jX DescriptionrG^rH^}rI^(jjD^jjB^ubaubajj ubejj ubajj ubj )rJ^}rK^(jUj}rL^(j]j]j]j]j]ujj ^j]rM^(j )rN^}rO^(jUj}rP^(j]j]j]j]j]ujjJ^j]rQ^(j )rR^}rS^(jUj}rT^(j]j]j]j]j]ujjN^j]rU^j)rV^}rW^(jX /dev/tiipcrX^jjR^jjZjjj}rY^(j]j]j]j]j]ujMj]rZ^jX /dev/tiipcr[^r\^}r]^(jjX^jjV^ubaubajj ubj )r^^}r_^(jUj}r`^(j]j]j]j]j]ujjN^j]ra^j)rb^}rc^(jX8Provides the "ti-ipc" protocol. Needed by MessageQ APIs.rd^jj^^jjZjjj}re^(j]j]j]j]j]ujMj]rf^jX8Provides the "ti-ipc" protocol. Needed by MessageQ APIs.rg^rh^}ri^(jjd^jjb^ubaubajj ubejj ubj )rj^}rk^(jUj}rl^(j]j]j]j]j]ujjJ^j]rm^(j )rn^}ro^(jUj}rp^(j]j]j]j]j]ujjj^j]rq^j)rr^}rs^(jX/dev/ipcrt^jjn^jjZjjj}ru^(j]j]j]j]j]ujMj]rv^jX/dev/ipcrw^rx^}ry^(jjt^jjr^ubaubajj ubj )rz^}r{^(jUj}r|^(j]j]j]j]j]ujjj^j]r}^j)r~^}r^(jX=Provides the HWSpinLock functionality. Needed by GateMP APIs.r^jjz^jjZjjj}r^(j]j]j]j]j]ujMj]r^jX=Provides the HWSpinLock functionality. Needed by GateMP APIs.r^r^}r^(jj^jj~^ubaubajj ubejj ubejj ubejj ubaubj)r^}r^(jXAdditionally, more devices may be registered by the remote core firmware if using the "rpmsg-rpc" protocol. In that case, the name that appears in the pathname space is specified by the remote core firmware.r^jj]jjZjjj}r^(j]j]j]j]j]ujMjhj]r^jXAdditionally, more devices may be registered by the remote core firmware if using the "rpmsg-rpc" protocol. In that case, the name that appears in the pathname space is specified by the remote core firmware.r^r^}r^(jj^jj^ubaubj)r^}r^(jXLater, when you are done running applications that use IPC and no longer need the resource manager, it can be terminated as follows:r^jj]jjZjjj}r^(j]j]j]j]j]ujMjhj]r^jXLater, when you are done running applications that use IPC and no longer need the resource manager, it can be terminated as follows:r^r^}r^(jj^jj^ubaubj)r^}r^(jXTtarget# cd /armle-v7/bin target# slay ipcjj]jjZjjj}r^(j@jAj]j]j]j]j]ujMjhj]r^jXTtarget# cd /armle-v7/bin target# slay ipcr^r^}r^(jUjj^ubaubeubj)r^}r^(jUjKjj ]jjZjjj}r^(j]r^jYaj]j]j]r^Uid64r^aj]ujM%jhj]r^(j)r^}r^(jXRunning Test Applicationsr^jj^jjZjjj}r^(j]j]j]j]j]ujM%jhj]r^jXRunning Test Applicationsr^r^}r^(jj^jj^ubaubj)r^}r^(jX$The QNX-side of the test applications are already on the target's filesystem in /armle-v7/bin and /armle-v7/bin/tests, assuming the `#Installing Tests in QNX `__ and `#IPC resource manager `__ sections have been followed and that the resource manager has loaded the remote core(s) with the executable corresponding to the test you'd like to run.jj^jjZjjj}r^(j]j]j]j]j]ujM'jhj]r^(jXThe QNX-side of the test applications are already on the target's filesystem in /armle-v7/bin and /armle-v7/bin/tests, assuming the r^r^}r^(jXThe QNX-side of the test applications are already on the target's filesystem in /armle-v7/bin and /armle-v7/bin/tests, assuming the jj^ubj)r^}r^(jXY`#Installing Tests in QNX `__j}r^(UnameX#Installing Tests in QNXjX:index_Foundational_Components.html#installing-tests-in-qnxj]j]j]j]j]ujj^j]r^jX#Installing Tests in QNXr^r^}r^(jUjj^ubajjubjX and r^r^}r^(jX and jj^ubj)r^}r^(jXS`#IPC resource manager `__j}r^(UnameX#IPC resource managerjX7index_Foundational_Components.html#ipc-resource-managerj]j]j]j]j]ujj^j]r^jX#IPC resource managerr^r^}r^(jUjj^ubajjubjX sections have been followed and that the resource manager has loaded the remote core(s) with the executable corresponding to the test you'd like to run.r^r^}r^(jX sections have been followed and that the resource manager has loaded the remote core(s) with the executable corresponding to the test you'd like to run.jj^ubeubj)r^}r^(jXITo find out the syntax to use for running the test (say MessageQApp), runr^jj^jjZjjj}r^(j]j]j]j]j]ujM/jhj]r^jXITo find out the syntax to use for running the test (say MessageQApp), runr^r^}r^(jj^jj^ubaubj)r^}r^(jXatarget# cd /armle-v7/bin/tests target# use MessageQAppjj^jjZjjj}r^(j@jAj]j]j]j]j]ujMjhj]r^jXatarget# cd /armle-v7/bin/tests target# use MessageQAppr^r^}r^(jUjj^ubaubj)r^}r^(jXATo run a test application, execute it on the target's filesystem:r^jj^jjZjjj}r^(j]j]j]j]j]ujM7jhj]r^jXATo run a test application, execute it on the target's filesystem:r^r^}r^(jj^jj^ubaubj)r^}r^(jXbtarget# cd /armle-v7/bin/tests target# ./MessageQApp 10jj^jjZjjj}r^(j@jAj]j]j]j]j]ujMjhj]r^jXbtarget# cd /armle-v7/bin/tests target# ./MessageQApp 10r^r^}r^(jUjj^ubaubj)r^}r^(jXGHere is a list of the main tests that are available in the IPC product:r^jj^jjZjjj}r^(j]j]j]j]j]ujM>jhj]r^jXGHere is a list of the main tests that are available in the IPC product:r^r^}r^(jj^jj^ubaubjt)r^}r^(jUjj^jjZjjwj}r^(jyX-j]j]j]j]j]ujM@jhj]r^(j{)r^}r^(jXMessageQApp: Test that creates a single thread that sends messages from host to remote core using MessageQ - messageq_single.x\* need to be loaded by the resource manager jj^jNjjj}r^(j]j]j]j]j]ujNjhj]r^(j)r^}r^(jXjMessageQApp: Test that creates a single thread that sends messages from host to remote core using MessageQr^jj^jjZjjj}r^(j]j]j]j]j]ujM@j]r^jXjMessageQApp: Test that creates a single thread that sends messages from host to remote core using MessageQr^r^}r^(jj^jj^ubaubjt)r^}r^(jUj}r^(jyX-j]j]j]j]j]ujj^j]r_j{)r_}r_(jX>messageq_single.x\* need to be loaded by the resource manager j}r_(j]j]j]j]j]ujj^j]r_j)r_}r_(jX=messageq_single.x\* need to be loaded by the resource managerjj_jjZjjj}r_(j]j]j]j]j]ujMCj]r_jX<messageq_single.x* need to be loaded by the resource managerr _r _}r _(jX=messageq_single.x\* need to be loaded by the resource managerjj_ubaubajjubajjwubeubj{)r _}r _(jXMessageQMulti: Test that creates multiple threads which send messages from host to remote core using MessageQ - messageq_multi.x\* need to be loaded by the resource manager jj^jNjjj}r_(j]j]j]j]j]ujNjhj]r_(j)r_}r_(jXmMessageQMulti: Test that creates multiple threads which send messages from host to remote core using MessageQr_jj _jjZjjj}r_(j]j]j]j]j]ujMEj]r_jXmMessageQMulti: Test that creates multiple threads which send messages from host to remote core using MessageQr_r_}r_(jj_jj_ubaubjt)r_}r_(jUj}r_(jyX-j]j]j]j]j]ujj _j]r_j{)r_}r_(jX=messageq_multi.x\* need to be loaded by the resource manager j}r_(j]j]j]j]j]ujj_j]r_j)r _}r!_(jX<messageq_multi.x\* need to be loaded by the resource managerjj_jjZjjj}r"_(j]j]j]j]j]ujMHj]r#_jX;messageq_multi.x* need to be loaded by the resource managerr$_r%_}r&_(jX<messageq_multi.x\* need to be loaded by the resource managerjj _ubaubajjubajjwubeubj{)r'_}r(_(jXmmrpc_test: Test that exercises MMRPC - test_omx_ipu_.x\* need to be loaded by the resource manager - Aside from the IPC resource manager, this test also needs the shmemallocator resource manager to be launched beforehand: jj^jNjjj}r)_(j]j]j]j]j]ujNjhj]r*_(j)r+_}r,_(jX%mmrpc_test: Test that exercises MMRPCr-_jj'_jjZjjj}r._(j]j]j]j]j]ujMJj]r/_jX%mmrpc_test: Test that exercises MMRPCr0_r1_}r2_(jj-_jj+_ubaubjt)r3_}r4_(jUj}r5_(jyX-j]j]j]j]j]ujj'_j]r6_(j{)r7_}r8_(jXEtest_omx_ipu_.x\* need to be loaded by the resource managerj}r9_(j]j]j]j]j]ujj3_j]r:_j)r;_}r<_(jXEtest_omx_ipu_.x\* need to be loaded by the resource managerjj7_jjZjjj}r=_(j]j]j]j]j]ujMLj]r>_jXDtest_omx_ipu_.x* need to be loaded by the resource managerr?_r@_}rA_(jXEtest_omx_ipu_.x\* need to be loaded by the resource managerjj;_ubaubajjubj{)rB_}rC_(jXyAside from the IPC resource manager, this test also needs the shmemallocator resource manager to be launched beforehand: j}rD_(j]j]j]j]j]ujj3_j]rE_j)rF_}rG_(jXxAside from the IPC resource manager, this test also needs the shmemallocator resource manager to be launched beforehand:rH_jjB_jjZjjj}rI_(j]j]j]j]j]ujMNj]rJ_jXxAside from the IPC resource manager, this test also needs the shmemallocator resource manager to be launched beforehand:rK_rL_}rM_(jjH_jjF_ubaubajjubejjwubeubeubj)rN_}rO_(jXtarget# cd /armle-v7/bin target# shmemallocator target# cd tests target# mmrpc_test 1jj^jjZjjj}rP_(j@jAj]j]j]j]j]ujMjhj]rQ_jXtarget# cd /armle-v7/bin target# shmemallocator target# cd tests target# mmrpc_test 1rR_rS_}rT_(jUjjN_ubaubjhK)rU_}rV_(jXExpected outputrW_jj^jjZjjlKj}rX_(j]rY_Uexpected-outputrZ_aj]j]j]j]r[_haujNjhj]r\_jXExpected outputr]_r^_}r__(jjW_jjU_ubaubj)r`_}ra_(jXeTo give you an idea, the expected output for MessageQApp on the QNX-side should look similar to this:rb_jj^jjZjjj}rc_(j]j]j]j]j]ujM[jhj]rd_jXeTo give you an idea, the expected output for MessageQApp on the QNX-side should look similar to this:re_rf_}rg_(jjb_jj`_ubaubj)rh_}ri_(jX'Using numLoops: 10; procId : 1 Entered MessageQApp_execute Local MessageQId: 0x1 Remote queueId [0x10000] Exchanging 10 messages with remote processor IPU... MessageQ_get #0 Msg = 0x11c9f0 Exchanged 1 messages with remote processor IPU MessageQ_get #1 Msg = 0x11c9f0 Exchanged 2 messages with remote processor IPU MessageQ_get #2 Msg = 0x11c9f0 ... ... Exchanged 9 messages with remote processor IPU MessageQ_get #9 Msg = 0x11c9f0 Exchanged 10 messages with remote processor IPU Sample application successfully completed! Leaving MessageQApp_executejj^jjZjjj}rj_(j@jAj]j]j]j]j]ujM jhj]rk_jX'Using numLoops: 10; procId : 1 Entered MessageQApp_execute Local MessageQId: 0x1 Remote queueId [0x10000] Exchanging 10 messages with remote processor IPU... MessageQ_get #0 Msg = 0x11c9f0 Exchanged 1 messages with remote processor IPU MessageQ_get #1 Msg = 0x11c9f0 Exchanged 2 messages with remote processor IPU MessageQ_get #2 Msg = 0x11c9f0 ... ... Exchanged 9 messages with remote processor IPU MessageQ_get #9 Msg = 0x11c9f0 Exchanged 10 messages with remote processor IPU Sample application successfully completed! Leaving MessageQApp_executerl_rm_}rn_(jUjjh_ubaubj)ro_}rp_(jXeThe output on the remote processor can be obtained by running the following on the target filesystem:rq_jj^jjZjjj}rr_(j]j]j]j]j]ujMrjhj]rs_jXeThe output on the remote processor can be obtained by running the following on the target filesystem:rt_ru_}rv_(jjq_jjo_ubaubj)rw_}rx_(jXtarget# cat /dev/ipc-trace/IPUjj^jjZjjj}ry_(j@jAj]j]j]j]j]ujM jhj]rz_jXtarget# cat /dev/ipc-trace/IPUr{_r|_}r}_(jUjjw_ubaubj)r~_}r_(jXHThe expected output on the remote processor should look similar to this:r_jj^jjZjjj}r_(j]j]j]j]j]ujMyjhj]r_jXHThe expected output on the remote processor should look similar to this:r_r_}r_(jj_jj~_ubaubj)r_}r_(jX[0][ 0.000] 16 Resource entries at 0x3000 [0][ 0.000] messageq_single.c:main: MultiProc id = 1 [0][ 0.000] [t=0x006c565d] ti.ipc.transports.TransportVirtioSetup: TransportVirtio Setup_attach: remoteProcId: 0 [0][ 0.000] registering rpmsg-proto:rpmsg-proto service on 61 with HOST [0][ 0.000] [t=0x0072625b] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_create: endPt c reated: 61 [0][ 0.000] [t=0x0073e8d9] ti.ipc.rpmsg.MessageQCopy: callback_availBufReady: virt Queue_toHost kicked [0][ 0.000] [t=0x00753771] ti.ipc.rpmsg.MessageQCopy: callback_availBufReady: virt Queue_fromHost kicked [0][ 0.000] [t=0x0076cb49] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_swiFxn: [0][ 0.000] Received msg: from: 0x5a, to: 0x35, dataLen: 72 [0][ 0.000] [t=0x007872e9] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_send: no object for endpoint: 53 [0][ 0.000] tsk1Fxn: created MessageQ: SLAVE_CORE0; QueueID: 0x10000 [0][ 0.000] Awaiting sync message from host... [0][ 51.992] [t=0x0c475268] ti.ipc.rpmsg.MessageQCopy: callback_availBufReady: virt Queue_fromHost kicked [0][ 51.992] [t=0x0c48eb28] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_swiFxn: [0][ 51.993] Received msg: from: 0x400, to: 0x3d, dataLen: 176 [0][ 51.993] [t=0x0c4ad220] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_send: calling c allback with data len: 176, from: 1024 [0][ 51.993] [0][ 52.995] [t=0x0c873ded] ti.ipc.rpmsg.MessageQCopy: callback_availBufReady: virt Queue_fromHost kicked [0][ 52.996] [t=0x0c88b029] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_swiFxn: [0][ 52.996] Received msg: from: 0x406, to: 0x3d, dataLen: 40 [0][ 52.996] [t=0x0c8a8a87] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_send: calling c allback with data len: 40, from: 1030 [0][ 52.996] [0][ 52.996] Received msg from (procId:remoteQueueId): 0x0:0x1 [0][ 52.996] payload: 8 bytes; loops: 10 with printing. [0][ 52.997] [t=0x0c8eab7e] ti.ipc.rpmsg.MessageQCopy: callback_availBufReady: virt Queue_fromHost kicked [0][ 52.997] [t=0x0c9031bc] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_swiFxn: [0][ 52.997] Received msg: from: 0x406, to: 0x3d, dataLen: 40 [0][ 52.997] [t=0x0c9208fa] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_send: calling c allback with data len: 40, from: 1030 [0][ 52.997] [0][ 52.997] Got msg #0 (40 bytes) from procId 0 [0][ 52.997] Sending msg Id #0 to procId 0 [0][ 52.998] [t=0x0c959f33] ti.ipc.rpmsg.MessageQCopy: callback_availBufReady: virt Queue_fromHost kicked [0][ 52.998] [t=0x0c971df7] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_swiFxn: [0][ 52.998] Received msg: from: 0x406, to: 0x3d, dataLen: 40 [0][ 52.998] [t=0x0c98f3e7] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_send: calling c allback with data len: 40, from: 1030 [0][ 52.998] [0][ 52.999] Got msg #1 (40 bytes) from procId 0 [0][ 52.999] Sending msg Id #1 to procId 0 [0][ 52.999] [t=0x0c9c7a00] ti.ipc.rpmsg.MessageQCopy: callback_availBufReady: virt Queue_fromHost kicked [0][ 52.999] [t=0x0c9df7fc] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_swiFxn: [0][ 52.999] Received msg: from: 0x406, to: 0x3d, dataLen: 40 [0][ 52.999] [t=0x0c9fce5a] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_send: calling c allback with data len: 40, from: 1030 [0][ 52.999] [0][ 53.000] Got msg #2 (40 bytes) from procId 0 [0][ 53.000] Sending msg Id #2 to procId 0 [0][ 53.000] [t=0x0ca36e79] ti.ipc.rpmsg.MessageQCopy: callback_availBufReady: virt Queue_fromHost kicked [0][ 53.000] [t=0x0ca4ea95] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_swiFxn: [0][ 53.000] Received msg: from: 0x406, to: 0x3d, dataLen: 40 [0][ 53.001] [t=0x0ca6c975] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_send: calling c allback with data len: 40, from: 1030 [0][ 53.001] [0][ 53.001] Got msg #3 (40 bytes) from procId 0 [0][ 53.001] Sending msg Id #3 to procId 0 ... ... [0][ 53.007] Got msg #8 (40 bytes) from procId 0 [0][ 53.007] Sending msg Id #8 to procId 0 [0][ 53.007] [t=0x0cccd3d7] ti.ipc.rpmsg.MessageQCopy: callback_availBufReady: virt Queue_fromHost kicked [0][ 53.007] [t=0x0cce50ed] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_swiFxn: [0][ 53.007] Received msg: from: 0x406, to: 0x3d, dataLen: 40 [0][ 53.007] [t=0x0cd027bd] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_send: calling c allback with data len: 40, from: 1030 [0][ 53.007] [0][ 53.008] Got msg #9 (40 bytes) from procId 0 [0][ 53.008] Sending msg Id #9 to procId 0 [0][ 53.008] Awaiting sync message from host...jj^jjZjjj}r_(j@jAj]j]j]j]j]ujM&jhj]r_jX[0][ 0.000] 16 Resource entries at 0x3000 [0][ 0.000] messageq_single.c:main: MultiProc id = 1 [0][ 0.000] [t=0x006c565d] ti.ipc.transports.TransportVirtioSetup: TransportVirtio Setup_attach: remoteProcId: 0 [0][ 0.000] registering rpmsg-proto:rpmsg-proto service on 61 with HOST [0][ 0.000] [t=0x0072625b] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_create: endPt c reated: 61 [0][ 0.000] [t=0x0073e8d9] ti.ipc.rpmsg.MessageQCopy: callback_availBufReady: virt Queue_toHost kicked [0][ 0.000] [t=0x00753771] ti.ipc.rpmsg.MessageQCopy: callback_availBufReady: virt Queue_fromHost kicked [0][ 0.000] [t=0x0076cb49] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_swiFxn: [0][ 0.000] Received msg: from: 0x5a, to: 0x35, dataLen: 72 [0][ 0.000] [t=0x007872e9] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_send: no object for endpoint: 53 [0][ 0.000] tsk1Fxn: created MessageQ: SLAVE_CORE0; QueueID: 0x10000 [0][ 0.000] Awaiting sync message from host... [0][ 51.992] [t=0x0c475268] ti.ipc.rpmsg.MessageQCopy: callback_availBufReady: virt Queue_fromHost kicked [0][ 51.992] [t=0x0c48eb28] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_swiFxn: [0][ 51.993] Received msg: from: 0x400, to: 0x3d, dataLen: 176 [0][ 51.993] [t=0x0c4ad220] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_send: calling c allback with data len: 176, from: 1024 [0][ 51.993] [0][ 52.995] [t=0x0c873ded] ti.ipc.rpmsg.MessageQCopy: callback_availBufReady: virt Queue_fromHost kicked [0][ 52.996] [t=0x0c88b029] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_swiFxn: [0][ 52.996] Received msg: from: 0x406, to: 0x3d, dataLen: 40 [0][ 52.996] [t=0x0c8a8a87] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_send: calling c allback with data len: 40, from: 1030 [0][ 52.996] [0][ 52.996] Received msg from (procId:remoteQueueId): 0x0:0x1 [0][ 52.996] payload: 8 bytes; loops: 10 with printing. [0][ 52.997] [t=0x0c8eab7e] ti.ipc.rpmsg.MessageQCopy: callback_availBufReady: virt Queue_fromHost kicked [0][ 52.997] [t=0x0c9031bc] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_swiFxn: [0][ 52.997] Received msg: from: 0x406, to: 0x3d, dataLen: 40 [0][ 52.997] [t=0x0c9208fa] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_send: calling c allback with data len: 40, from: 1030 [0][ 52.997] [0][ 52.997] Got msg #0 (40 bytes) from procId 0 [0][ 52.997] Sending msg Id #0 to procId 0 [0][ 52.998] [t=0x0c959f33] ti.ipc.rpmsg.MessageQCopy: callback_availBufReady: virt Queue_fromHost kicked [0][ 52.998] [t=0x0c971df7] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_swiFxn: [0][ 52.998] Received msg: from: 0x406, to: 0x3d, dataLen: 40 [0][ 52.998] [t=0x0c98f3e7] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_send: calling c allback with data len: 40, from: 1030 [0][ 52.998] [0][ 52.999] Got msg #1 (40 bytes) from procId 0 [0][ 52.999] Sending msg Id #1 to procId 0 [0][ 52.999] [t=0x0c9c7a00] ti.ipc.rpmsg.MessageQCopy: callback_availBufReady: virt Queue_fromHost kicked [0][ 52.999] [t=0x0c9df7fc] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_swiFxn: [0][ 52.999] Received msg: from: 0x406, to: 0x3d, dataLen: 40 [0][ 52.999] [t=0x0c9fce5a] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_send: calling c allback with data len: 40, from: 1030 [0][ 52.999] [0][ 53.000] Got msg #2 (40 bytes) from procId 0 [0][ 53.000] Sending msg Id #2 to procId 0 [0][ 53.000] [t=0x0ca36e79] ti.ipc.rpmsg.MessageQCopy: callback_availBufReady: virt Queue_fromHost kicked [0][ 53.000] [t=0x0ca4ea95] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_swiFxn: [0][ 53.000] Received msg: from: 0x406, to: 0x3d, dataLen: 40 [0][ 53.001] [t=0x0ca6c975] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_send: calling c allback with data len: 40, from: 1030 [0][ 53.001] [0][ 53.001] Got msg #3 (40 bytes) from procId 0 [0][ 53.001] Sending msg Id #3 to procId 0 ... ... [0][ 53.007] Got msg #8 (40 bytes) from procId 0 [0][ 53.007] Sending msg Id #8 to procId 0 [0][ 53.007] [t=0x0cccd3d7] ti.ipc.rpmsg.MessageQCopy: callback_availBufReady: virt Queue_fromHost kicked [0][ 53.007] [t=0x0cce50ed] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_swiFxn: [0][ 53.007] Received msg: from: 0x406, to: 0x3d, dataLen: 40 [0][ 53.007] [t=0x0cd027bd] ti.ipc.rpmsg.MessageQCopy: MessageQCopy_send: calling c allback with data len: 40, from: 1030 [0][ 53.007] [0][ 53.008] Got msg #9 (40 bytes) from procId 0 [0][ 53.008] Sending msg Id #9 to procId 0 [0][ 53.008] Awaiting sync message from host...r_r_}r_(jUjj_ubaubeubj)r_}r_(jUjj ]jjZjjj}r_(j]j]j]j]r_Urunning-standalone-examplesr_aj]r_haujMjhj]r_(j)r_}r_(jXRunning standalone examplesr_jj_jjZjjj}r_(j]j]j]j]j]ujMjhj]r_jXRunning standalone examplesr_r_}r_(jj_jj_ubaubj)r_}r_(jXaOn some platforms, there are standalone examples provided to illustrate how to use specific features in IPC. These standalone examples are designed to be easily rebuilt outside of the IPC product, and represent a good starting point for development. If available, the examples are located in \examples\archive\.jj_jjZjjj}r_(j]j]j]j]j]ujMjhj]r_jX^On some platforms, there are standalone examples provided to illustrate how to use specific features in IPC. These standalone examples are designed to be easily rebuilt outside of the IPC product, and represent a good starting point for development. If available, the examples are located in examplesarchive.r_r_}r_(jXaOn some platforms, there are standalone examples provided to illustrate how to use specific features in IPC. These standalone examples are designed to be easily rebuilt outside of the IPC product, and represent a good starting point for development. If available, the examples are located in \examples\archive\.jj_ubaubj)r_}r_(jXTo use the examples, unzip the example you want in a working directory of your choice. Update the products.mak file in the example's directory with the installation locations of the various dependent components. Then build it. E.g.:r_jj_jjZjjj}r_(j]j]j]j]j]ujMjhj]r_jXTo use the examples, unzip the example you want in a working directory of your choice. Update the products.mak file in the example's directory with the installation locations of the various dependent components. Then build it. E.g.:r_r_}r_(jj_jj_ubaubj)r_}r_(jX|buildhost$ unzip ex02_messageq.zip buildhost$ cd ex02_messageq buildhost$ make clean buildhost$ make buildhost$ make installjj_jjZjjj}r_(j@jAj]j]j]j]j]ujMjhj]r_jX|buildhost$ unzip ex02_messageq.zip buildhost$ cd ex02_messageq buildhost$ make clean buildhost$ make buildhost$ make installr_r_}r_(jUjj_ubaubj)r_}r_(jXThis would produce the host and remote core binaries in an 'install' subdirectory. **Tip**: Alternatively, for convenience, you can also extract and rebuild all examples available for your platform at once with this series of commands:jj_jjZjjj}r_(j]j]j]j]j]ujMjhj]r_(jXSThis would produce the host and remote core binaries in an 'install' subdirectory. r_r_}r_(jXSThis would produce the host and remote core binaries in an 'install' subdirectory. jj_ubj)r_}r_(jX**Tip**j}r_(j]j]j]j]j]ujj_j]r_jXTipr_r_}r_(jUjj_ubajjubjX: Alternatively, for convenience, you can also extract and rebuild all examples available for your platform at once with this series of commands:r_r_}r_(jX: Alternatively, for convenience, you can also extract and rebuild all examples available for your platform at once with this series of commands:jj_ubeubj)r_}r_(jXhbuildhost$ cd /examples buildhost$ make extract buildhost$ make buildhost$ make installjj_jjZjjj}r_(j@jAj]j]j]j]j]ujMjhj]r_jXhbuildhost$ cd /examples buildhost$ make extract buildhost$ make buildhost$ make installr_r_}r_(jUjj_ubaubj)r_}r_(jX Next step is to copy the content of the 'install' subdirectory into a location accessible by your target board (e.g. SD card). Run the example on the target using IPC by loading the remote cores like you would with the test applications, then run the example. E.g.:r_jj_jjZjjj}r_(j]j]j]j]j]ujMjhj]r_jX Next step is to copy the content of the 'install' subdirectory into a location accessible by your target board (e.g. SD card). Run the example on the target using IPC by loading the remote cores like you would with the test applications, then run the example. E.g.:r_r_}r_(jj_jj_ubaubj)r_}r_(jXtarget# ipc IPU ex02_messageq/debug/server_ipu.xem4 DSP ex02_messageq/debug/server_dsp.xe64T target# cd ex02_messageq/debug/ target# app_host IPUjj_jjZjjj}r_(j@jAj]j]j]j]j]ujMjhj]r_jXtarget# ipc IPU ex02_messageq/debug/server_ipu.xem4 DSP ex02_messageq/debug/server_dsp.xe64T target# cd ex02_messageq/debug/ target# app_host IPUr_r_}r_(jUjj_ubaubeubj)r_}r_(jUjj ]jjZjjj}r_(j]j]j]j]r_Uadvanced-topicsr_aj]r_h|aujMjhj]r_(j)r_}r_(jXAdvanced topicsr_jj_jjZjjj}r_(j]j]j]j]j]ujMjhj]r_jXAdvanced topicsr_r_}r_(jj_jj_ubaubj)r_}r_(jUjj_jjZjjj}r_(j]j]j]j]r_UKload-and-unload-individual-cores-while-ipc-is-running-ipc-3-23-01-and-abover_aj]r_jGaujMjhj]r_(j)r_}r_(jXMLoad and unload individual cores while IPC is running (IPC 3.23.01 and above)r_jj_jjZjjj}r_(j]j]j]j]j]ujMjhj]r_jXMLoad and unload individual cores while IPC is running (IPC 3.23.01 and above)r_r_}r_(jj_jj_ubaubj)r_}r_(jXIn some applications, there may be a need to load or unload cores after the IPC resource manager is already up and running -- e.g. change the DSP executable while keeping the IPU running.r_jj_jjZjjj}r_(j]j]j]j]j]ujMjhj]r_jXIn some applications, there may be a need to load or unload cores after the IPC resource manager is already up and running -- e.g. change the DSP executable while keeping the IPU running.r_r_}r_(jj_jj_ubaubj)r_}r`(jXzIn order to load and start a core with an executable, you can do the following after having launched the resource manager:r`jj_jjZjjj}r`(j]j]j]j]j]ujMjhj]r`jXzIn order to load and start a core with an executable, you can do the following after having launched the resource manager:r`r`}r`(jj`jj_ubaubj)r`}r`(jXqtarget# echo > /dev/ipc-file/ target# echo 1 > /dev/ipc-state/jj_jjZjjj}r `(j@jAj]j]j]j]j]ujMjhj]r `jXqtarget# echo > /dev/ipc-file/ target# echo 1 > /dev/ipc-state/r `r `}r `(jUjj`ubaubj)r`}r`(jXThe first command sets the filename of an executable to be loaded, and the second command loads and starts the core with that executable.r`jj_jjZjjj}r`(j]j]j]j]j]ujMjhj]r`jXThe first command sets the filename of an executable to be loaded, and the second command loads and starts the core with that executable.r`r`}r`(jj`jj`ubaubj)r`}r`(jX5To stop and unload a core, use the following command:r`jj_jjZjjj}r`(j]j]j]j]j]ujMjhj]r`jX5To stop and unload a core, use the following command:r`r`}r`(jj`jj`ubaubj)r`}r`(jX+target# echo 0 > /dev/ipc-state/jj_jjZjjj}r `(j@jAj]j]j]j]j]ujMjhj]r!`jX+target# echo 0 > /dev/ipc-state/r"`r#`}r$`(jUjj`ubaubj)r%`}r&`(jX:Keep in mind that this simply puts the core into reset. If there is any on-going communication between the given core and the others, it is the responsibility of the user application to clean up and terminate IPC on the slave before unloading a core, thus to avoid causing any memory leaks or communication errors.r'`jj_jjZjjj}r(`(j]j]j]j]j]ujMjhj]r)`jX:Keep in mind that this simply puts the core into reset. If there is any on-going communication between the given core and the others, it is the responsibility of the user application to clean up and terminate IPC on the slave before unloading a core, thus to avoid causing any memory leaks or communication errors.r*`r+`}r,`(jj'`jj%`ubaubeubj)r-`}r.`(jUjj_jjZjjj}r/`(j]j]j]j]r0`U7inspect-the-state-of-a-slave-core-ipc-3-23-01-and-abover1`aj]r2`haujM jhj]r3`(j)r4`}r5`(jX9Inspect the state of a slave core (IPC 3.23.01 and above)r6`jj-`jjZjjj}r7`(j]j]j]j]j]ujM jhj]r8`jX9Inspect the state of a slave core (IPC 3.23.01 and above)r9`r:`}r;`(jj6`jj4`ubaubj)r<`}r=`(jXgTo find out the state of a slave core (whether it is running or in reset), issue the following command:r>`jj-`jjZjjj}r?`(j]j]j]j]j]ujM"jhj]r@`jXgTo find out the state of a slave core (whether it is running or in reset), issue the following command:rA`rB`}rC`(jj>`jj<`ubaubj)rD`}rE`(jX&target# cat /dev/ipc-state/jj-`jjZjjj}rF`(j@jAj]j]j]j]j]ujMjhj]rG`jX&target# cat /dev/ipc-state/rH`rI`}rJ`(jUjjD`ubaubeubj)rK`}rL`(jUjj_jjZjjj}rM`(j]j]j]j]rN`UtracingrO`aj]rP`jaujM*jhj]rQ`(j)rR`}rS`(jXTracingrT`jjK`jjZjjj}rU`(j]j]j]j]j]ujM*jhj]rV`jXTracingrW`rX`}rY`(jjT`jjR`ubaubj)rZ`}r[`(jXWhen an issue arises, sometimes it is useful to see the output of internal traces from IPC. This section talks about how to view IPC trace from both the host and the slave cores on the QNX command prompt.r\`jjK`jjZjjj}r]`(j]j]j]j]j]ujM,jhj]r^`jXWhen an issue arises, sometimes it is useful to see the output of internal traces from IPC. This section talks about how to view IPC trace from both the host and the slave cores on the QNX command prompt.r_`r``}ra`(jj\`jjZ`ubaubjhK)rb`}rc`(jXHost-side trace outputrd`jjK`jjZjjlKj}re`(j]rf`Uhost-side-trace-outputrg`aj]j]j]j]rh`hlaujNjhj]ri`jXHost-side trace outputrj`rk`}rl`(jjd`jjb`ubaubjhK)rm`}rn`(jX2Trace from IPC user libraries (IPC 3.35 and above)ro`jjK`jjZjjlKj}rp`(j]rq`U0trace-from-ipc-user-libraries-ipc-3-35-and-aboverr`aj]j]j]j]rs`jPaujNjhj]rt`jX2Trace from IPC user libraries (IPC 3.35 and above)ru`rv`}rw`(jjo`jjm`ubaubj)rx`}ry`(jXTrace output from the IPC user libraries is controlled using the environment variable *IPC_DEBUG*, when launching an application that uses IPC. E.g.:jjK`jjZjjj}rz`(j]j]j]j]j]ujM6jhj]r{`(jXVTrace output from the IPC user libraries is controlled using the environment variable r|`r}`}r~`(jXVTrace output from the IPC user libraries is controlled using the environment variable jjx`ubjM)r`}r`(jX *IPC_DEBUG*j}r`(j]j]j]j]j]ujjx`j]r`jX IPC_DEBUGr`r`}r`(jUjj`ubajjUubjX4, when launching an application that uses IPC. E.g.:r`r`}r`(jX4, when launching an application that uses IPC. E.g.:jjx`ubeubj)r`}r`(jX"target# IPC_DEBUG= app_hostjjK`jjZjjj}r`(j@jAj]j]j]j]j]ujMjhj]r`jX"target# IPC_DEBUG= app_hostr`r`}r`(jUjj`ubaubj)r`}r`(jXSwhere can be set to a value between 1 and 3, with 3 being the most verbose.r`jjK`jjZjjj}r`(j]j]j]j]j]ujM>jhj]r`jXSwhere can be set to a value between 1 and 3, with 3 being the most verbose.r`r`}r`(jj`jj`ubaubjhK)r`}r`(jX4Trace from IPC resource manager (IPC 3.35 and above)r`jjK`jjZjjlKj}r`(j]r`U2trace-from-ipc-resource-manager-ipc-3-35-and-abover`aj]j]j]j]r`haujNjhj]r`jX4Trace from IPC resource manager (IPC 3.35 and above)r`r`}r`(jj`jj`ubaubj)r`}r`(jXfTo show the trace output of the IPC resource manager in the QNX system log, run the following command:r`jjK`jjZjjj}r`(j]j]j]j]j]ujMDjhj]r`jXfTo show the trace output of the IPC resource manager in the QNX system log, run the following command:r`r`}r`(jj`jj`ubaubj)r`}r`(jXtarget# sloginfo -m42jjK`jjZjjj}r`(j@jAj]j]j]j]j]ujMjhj]r`jXtarget# sloginfo -m42r`r`}r`(jUjj`ubaubj)r`}r`(jXThe verbosity of the trace can be controlled using the environment variable *IPC_DEBUG_SLOG_LEVEL* when launching the IPC resource manager. E.g.:jjK`jjZjjj}r`(j]j]j]j]j]ujMKjhj]r`(jXLThe verbosity of the trace can be controlled using the environment variable r`r`}r`(jXLThe verbosity of the trace can be controlled using the environment variable jj`ubjM)r`}r`(jX*IPC_DEBUG_SLOG_LEVEL*j}r`(j]j]j]j]j]ujj`j]r`jXIPC_DEBUG_SLOG_LEVELr`r`}r`(jUjj`ubajjUubjX/ when launching the IPC resource manager. E.g.:r`r`}r`(jX/ when launching the IPC resource manager. E.g.:jj`ubeubj)r`}r`(jXRtarget# IPC_DEBUG_SLOG_LEVEL= ipc DSP1 ex02_messageq/debug/server_dsp1.xe66jjK`jjZjjj}r`(j@jAj]j]j]j]j]ujMjhj]r`jXRtarget# IPC_DEBUG_SLOG_LEVEL= ipc DSP1 ex02_messageq/debug/server_dsp1.xe66r`r`}r`(jUjj`ubaubj)r`}r`(jXkwhere can be set to a value between 0 and 7, with 7 being the most verbose. The default level is 2.r`jjK`jjZjjj}r`(j]j]j]j]j]ujMSjhj]r`jXkwhere can be set to a value between 0 and 7, with 7 being the most verbose. The default level is 2.r`r`}r`(jj`jj`ubaubjc)r`}r`(jUjjK`jjZjjfj}r`(j]j]j]j]j]ujMVjhj]r`ji)r`}r`(jUjlKjj`jjZjjj}r`(j]j]j]j]j]ujKjhj]ubaubjhK)r`}r`(jXSlave-side trace outputr`jjK`jjZjjlKj}r`(j]r`Uslave-side-trace-outputr`aj]j]j]j]r`hFaujNjhj]r`jXSlave-side trace outputr`r`}r`(jj`jj`ubaubj)r`}r`(jXZTo show all trace output (including IPC's) on a given slave core, simply run the followingr`jjK`jjZjjj}r`(j]j]j]j]j]ujM[jhj]r`jXZTo show all trace output (including IPC's) on a given slave core, simply run the followingr`r`}r`(jj`jj`ubaubj)r`}r`(jX&target# cat /dev/ipc-trace/jjK`jjZjjj}r`(j@jAj]j]j]j]j]ujM jhj]r`jX&target# cat /dev/ipc-trace/r`r`}r`(jUjj`ubaubj)r`}r`(jXwhere corresponds to the name of the slave core which trace output you are interested in (e.g. DSP1, IPU1 or IPU2 for DRA7xx)r`jjK`jjZjjj}r`(j]j]j]j]j]ujMbjhj]r`jXwhere corresponds to the name of the slave core which trace output you are interested in (e.g. DSP1, IPU1 or IPU2 for DRA7xx)r`r`}r`(jj`jj`ubaubj)r`}r`(jXNote that older versions of IPC may use a slightly different path that is based on the MultiProc id of the core of interest: /dev/ipc-trace.r`jjK`jjZjjj}r`(j]j]j]j]j]ujMejhj]r`jXNote that older versions of IPC may use a slightly different path that is based on the MultiProc id of the core of interest: /dev/ipc-trace.rara}ra(jj`jj`ubaubeubj)ra}ra(jUjj_jjZjjj}ra(j]j]j]j]raUBbuilding-the-ipc-resource-manager-in-debug-mode-ipc-3-35-and-aboveraaj]rahaujMjjhj]r a(j)r a}r a(jXDBuilding the IPC resource manager in debug mode (IPC 3.35 and above)r ajjajjZjjj}r a(j]j]j]j]j]ujMjjhj]rajXDBuilding the IPC resource manager in debug mode (IPC 3.35 and above)rara}ra(jj ajj aubaubj)ra}ra(jXAWhen debugging an issue, the user may wish to have the ability to step through the source code in the IPC resource manager. For this to happen, the IPC resource manager needs to be built in debug mode with debug symbols. Adding IPC_DEBUG=1 to the file /qnx/Makefile and rebuilding IPC would do the trick:rajjajjZjjj}ra(j]j]j]j]j]ujMljhj]rajXAWhen debugging an issue, the user may wish to have the ability to step through the source code in the IPC resource manager. For this to happen, the IPC resource manager needs to be built in debug mode with debug symbols. Adding IPC_DEBUG=1 to the file /qnx/Makefile and rebuilding IPC would do the trick:rara}ra(jjajjaubaubj)ra}ra(jX~ipc3x_dev: utils @cd src/ipc3x_dev; \ make IPC_PLATFORM=$(IPC_PLATFORM) SMP=1 QNX_CFLAGS=$(QNX_CFLAGS) IPC_DEBUG=1jjajjZjjj}ra(j@jAj]j]j]j]j]ujMjhj]rajX~ipc3x_dev: utils @cd src/ipc3x_dev; \ make IPC_PLATFORM=$(IPC_PLATFORM) SMP=1 QNX_CFLAGS=$(QNX_CFLAGS) IPC_DEBUG=1rara}r a(jUjjaubaubj)r!a}r"a(jXAtarget# make -f ipc-qnx.mak clean target# make -f ipc-qnx.mak alljjajjZjjj}r#a(j@jAj]j]j]j]j]ujM#jhj]r$ajXAtarget# make -f ipc-qnx.mak clean target# make -f ipc-qnx.mak allr%ar&a}r'a(jUjj!aubaubeubeubeubj)r(a}r)a(jUjKjjnZjjZjjj}r*a(j]r+aXsee alsor,aaj]j]j]r-aUid65r.aaj]ujM~jhj]r/a(j)r0a}r1a(jXSee Alsor2ajj(ajjZjjj}r3a(j]j]j]j]j]ujM~jhj]r4ajXSee Alsor5ar6a}r7a(jj2ajj0aubaubjt)r8a}r9a(jUjj(ajjZjjwj}r:a(jyX-j]j]j]j]j]ujMjhj]r;a(j{)r`__r>ajj8ajjZjjj}r?a(j]j]j]j]j]ujNjhj]r@aj)rAa}rBa(jj>ajjaj}rGa(UnameXIPC 3.xjX*index_Foundational_Components.html#ipc-3-xj]j]j]j]j]ujjAaj]rHajXIPC 3.xrIarJa}rKa(jUjjEaubajjubaubaubj{)rLa}rMa(jXG`IPC Users Guide `__rNajj8ajjZjjj}rOa(j]j]j]j]j]ujNjhj]rPaj)rQa}rRa(jjNajjLajjZjjj}rSa(j]j]j]j]j]ujMj]rTaj)rUa}rVa(jjNaj}rWa(UnameXIPC Users GuidejX1index_Foundational_Components.html#ipc-user-guidej]j]j]j]j]ujjQaj]rXajXIPC Users GuiderYarZa}r[a(jUjjUaubajjubaubaubj{)r\a}r]a(jX<`IPC 3.x FAQ `__r^ajj8ajjZjjj}r_a(j]j]j]j]j]ujNjhj]r`aj)raa}rba(jj^ajj\ajjZjjj}rca(j]j]j]j]j]ujMj]rdaj)rea}rfa(jj^aj}rga(UnameX IPC 3.x FAQjX*index_Foundational_Components.html#ipc-faqj]j]j]j]j]ujjaaj]rhajX IPC 3.x FAQriarja}rka(jUjjeaubajjubaubaubj{)rla}rma(jXT`IPC Install Guide Linux `__rnajj8ajjZjjj}roa(j]j]j]j]j]ujNjhj]rpaj)rqa}rra(jjnajjlajjZjjj}rsa(j]j]j]j]j]ujMj]rtaj)rua}rva(jjnaj}rwa(UnameXIPC Install Guide LinuxjX6index_Foundational_Components.html#linux-install-guidej]j]j]j]j]ujjqaj]rxajXIPC Install Guide Linuxryarza}r{a(jUjjuaubajjubaubaubj{)r|a}r}a(jXU`IPC Install Guide BIOS `__ jj8ajXZinternal padding after source/rtos/PDK_Platform_Software/IPC/IPC_Install_Guide_QNX.rst.incr~ajjj}ra(j]j]j]j]j]ujNjhj]raj)ra}ra(jXR`IPC Install Guide BIOS `__rajj|ajjZjjj}ra(j]j]j]j]j]ujMj]raj)ra}ra(jjaj}ra(UnameXIPC Install Guide BIOSjX5index_Foundational_Components.html#bios-install-guidej]j]j]j]j]ujjaj]rajXIPC Install Guide BIOSrara}ra(jUjjaubajjubaubaubeubeubeubeubeubjjjjj}ra(j]j]j]j]raUti-sdo-ipc-packageraaj]rahaujK/jhj]ra(j)ra}ra(jXTI SDO IPC Packagerajjjjjjj}ra(j]j]j]j]j]ujK/jhj]rajXTI SDO IPC Packagerara}ra(jjajjaubaubj7)ra}ra(jXNhttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/The_ti.sdo.ipc_Packagejjjj:XDsource/rtos/PDK_Platform_Software/IPC/The_ti.sdo.ipc_Package.rst.incrara}rabjj>j}ra(j@jAj]j]j]j]j]ujKjhj]rajXNhttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/The_ti.sdo.ipc_Packagerara}ra(jUjjaubaubj)ra}ra(jX.. |ipcSdoRun_Img1| Image:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/files.html jjjjajjHj}ra(j]j]j]j]j]raXipcSdoRun_Img1raaujKjhj]raj)ra}ra(jjaj}ra(UrefuriXhhttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/files.htmlraj]j]j]j]j]ujjaj]rajR)ra}ra(jXImage:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/files.htmlraj}ra(UuriXrtos/../images/Book_run.pngraj]j]j]j]jX}raU*jasj]Ualtjaujjaj]jjZubajjubaubj)ra}ra(jUjKjjjjajjj}ra(j]raX introductionraaj]j]j]raU introductionraaj]ujKjhj]ra(j)ra}ra(jX Introductionrajjajjajjj}ra(j]j]j]j]j]ujKjhj]rajX Introductionrara}ra(jjajjaubaubj)ra}ra(jX;This page introduces the modules in the ti.sdo.ipc package.rajjajjajjj}ra(j]j]j]j]j]ujKjhj]rajX;This page introduces the modules in the ti.sdo.ipc package.rara}ra(jjajjaubaubj)ra}ra(jXThis package is not used on HLOS-based cores. Although this is a BIOS-only package, note that the BIOS-side of a HLOS<->BIOS IPC-using application will need to bring in a subset of these packages into the BIOS-side configuration scripts.jjajjajjj}ra(j]j]j]j]j]ujNjhj]raj)ra}ra(jXThis package is not used on HLOS-based cores. Although this is a BIOS-only package, note that the BIOS-side of a HLOS<->BIOS IPC-using application will need to bring in a subset of these packages into the BIOS-side configuration scripts.rajjajjajjj}ra(j]j]j]j]j]ujK j]rajXThis package is not used on HLOS-based cores. Although this is a BIOS-only package, note that the BIOS-side of a HLOS<->BIOS IPC-using application will need to bring in a subset of these packages into the BIOS-side configuration scripts.rara}ra(jjajjaubaubaubj)ra}ra(jX`The ``ti.sdo.ipc`` package contains the following modules that you may use in your applications:rajjajjajjj}ra(j]j]j]j]j]ujKjhj]ra(jXThe rara}ra(jXThe jjaubj)ra}ra(jX``ti.sdo.ipc``j}ra(j]j]j]j]j]ujjaj]rajX ti.sdo.ipcrara}ra(jUjjaubajjubjXN package contains the following modules that you may use in your applications:rara}ra(jXN package contains the following modules that you may use in your applications:jjaubeubj3)ra}ra(jUjjajjajj6j}ra(j]j]j]j]j]ujNjhj]rajy )ra}ra(jUj}ra(j]j]j]j]j]ujjaj]raj~ )ra}ra(jUj}ra(j]j]j]j]j]UcolsKujjaj]ra(j )ra}ra(jUj}ra(j]j]j]j]j]UcolwidthKujjaj]jj ubj )ra}ra(jUj}ra(j]j]j]j]j]UcolwidthK$ujjaj]jj ubj )ra}ra(jUj}ra(j]j]j]j]j]UcolwidthK"ujjaj]jj ubj )rb}rb(jUj}rb(j]j]j]j]j]ujjaj]rbj )rb}rb(jUj}rb(j]j]j]j]j]ujjbj]rb(j )rb}r b(jUj}r b(j]j]j]j]j]ujjbj]r bj)r b}r b(jXModulerbjjbjjajjj}rb(j]j]j]j]j]ujKj]rbjXModulerbrb}rb(jjbjj bubaubajj ubj )rb}rb(jUj}rb(j]j]j]j]j]ujjbj]rbj)rb}rb(jX Module Pathrbjjbjjajjj}rb(j]j]j]j]j]ujKj]rbjX Module Pathrbrb}rb(jjbjjbubaubajj ubj )r b}r!b(jUj}r"b(j]j]j]j]j]ujjbj]r#bj)r$b}r%b(jX Descriptionr&bjj bjjajjj}r'b(j]j]j]j]j]ujKj]r(bjX Descriptionr)br*b}r+b(jj&bjj$bubaubajj ubejj ubajj ubj )r,b}r-b(jUj}r.b(j]j]j]j]j]ujjaj]r/b(j )r0b}r1b(jUj}r2b(j]j]j]j]j]ujj,bj]r3b(j )r4b}r5b(jUj}r6b(j]j]j]j]j]ujj0bj]r7bj)r8b}r9b(jXG`GateMP Module `__r:bjj4bjjajjj}r;b(j]j]j]j]j]ujKj]rb(jj:bj}r?b(UnameX GateMP ModulejX0index_Foundational_Components.html#gatemp-modulej]j]j]j]j]ujj8bj]r@bjX GateMP ModulerAbrBb}rCb(jUjj=bubajjubaubajj ubj )rDb}rEb(jUj}rFb(j]j]j]j]j]ujj0bj]rGbj)rHb}rIb(jXGateMPrJbjjDbjjajjj}rKb(j]j]j]j]j]ujKj]rLbjXGateMPrMbrNb}rOb(jjJbjjHbubaubajj ubj )rPb}rQb(jUj}rRb(j]j]j]j]j]ujj0bj]rSbj)rTb}rUb(jXManages gates for mutual exclusion of shared resources by multiple processors and threads. See `GateMP Module `__jjPbjjajjj}rVb(j]j]j]j]j]ujKj]rWb(jX_Manages gates for mutual exclusion of shared resources by multiple processors and threads. See rXbrYb}rZb(jX_Manages gates for mutual exclusion of shared resources by multiple processors and threads. See jjTbubj)r[b}r\b(jXG`GateMP Module `__j}r]b(UnameX GateMP ModulejX0index_Foundational_Components.html#gatemp-modulej]j]j]j]j]ujjTbj]r^bjX GateMP Moduler_br`b}rab(jUjj[bubajjubeubajj ubejj ubj )rbb}rcb(jUj}rdb(j]j]j]j]j]ujj,bj]reb(j )rfb}rgb(jUj}rhb(j]j]j]j]j]ujjbbj]ribj)rjb}rkb(jXJ`HeapBufMP Module `__rlbjjfbjjajjj}rmb(j]j]j]j]j]ujKj]rnbj)rob}rpb(jjlbj}rqb(UnameXHeapBufMP ModulejX0index_Foundational_Components.html#heapmp-modulej]j]j]j]j]ujjjbj]rrbjXHeapBufMP Modulersbrtb}rub(jUjjobubajjubaubajj ubj )rvb}rwb(jUj}rxb(j]j]j]j]j]ujjbbj]rybj)rzb}r{b(jXti.sdo.ipc.heaps.HeapBufMPr|bjjvbjjajjj}r}b(j]j]j]j]j]ujKj]r~bjXti.sdo.ipc.heaps.HeapBufMPrbrb}rb(jj|bjjzbubaubajj ubj )rb}rb(jUj}rb(j]j]j]j]j]ujjbbj]rbj)rb}rb(jXFixed-sized shared memory Heaps. Similar to SYS/BIOS's ti.sysbios.heaps.HeapBuf module, but with some configuration differences. See `HeapMP Module `__jjbjjajjj}rb(j]j]j]j]j]ujKj]rb(jXFixed-sized shared memory Heaps. Similar to SYS/BIOS's ti.sysbios.heaps.HeapBuf module, but with some configuration differences. See rbrb}rb(jXFixed-sized shared memory Heaps. Similar to SYS/BIOS's ti.sysbios.heaps.HeapBuf module, but with some configuration differences. See jjbubj)rb}rb(jXG`HeapMP Module `__j}rb(UnameX HeapMP ModulejX0index_Foundational_Components.html#heapmp-modulej]j]j]j]j]ujjbj]rbjX HeapMP Modulerbrb}rb(jUjjbubajjubeubajj ubejj ubj )rb}rb(jUj}rb(j]j]j]j]j]ujj,bj]rb(j )rb}rb(jUj}rb(j]j]j]j]j]ujjbj]rbj)rb}rb(jXJ`HeapMemMP Module `__rbjjbjjajjj}rb(j]j]j]j]j]ujK&j]rbj)rb}rb(jjbj}rb(UnameXHeapMemMP ModulejX0index_Foundational_Components.html#heapmp-modulej]j]j]j]j]ujjbj]rbjXHeapMemMP Modulerbrb}rb(jUjjbubajjubaubajj ubj )rb}rb(jUj}rb(j]j]j]j]j]ujjbj]rbj)rb}rb(jXti.sdo.ipc.heaps.HeapMemMPrbjjbjjajjj}rb(j]j]j]j]j]ujK&j]rbjXti.sdo.ipc.heaps.HeapMemMPrbrb}rb(jjbjjbubaubajj ubj )rb}rb(jUj}rb(j]j]j]j]j]ujjbj]rbj)rb}rb(jXoVariable-sized shared memory Heaps. See `HeapMP Module `__jjbjjajjj}rb(j]j]j]j]j]ujK&j]rb(jX(Variable-sized shared memory Heaps. See rbrb}rb(jX(Variable-sized shared memory Heaps. See jjbubj)rb}rb(jXG`HeapMP Module `__j}rb(UnameX HeapMP ModulejX0index_Foundational_Components.html#heapmp-modulej]j]j]j]j]ujjbj]rbjX HeapMP Modulerbrb}rb(jUjjbubajjubeubajj ubejj ubj )rb}rb(jUj}rb(j]j]j]j]j]ujj,bj]rb(j )rb}rb(jUj}rb(j]j]j]j]j]ujjbj]rbj)rb}rb(jXN`HeapMultiBufMP Module `__rbjjbjjajjj}rb(j]j]j]j]j]ujK-j]rbj)rb}rb(jjbj}rb(UnameXHeapMultiBufMP ModulejX0index_Foundational_Components.html#heapmp-modulej]j]j]j]j]ujjbj]rbjXHeapMultiBufMP Modulerbrb}rb(jUjjbubajjubaubajj ubj )rb}rb(jUj}rb(j]j]j]j]j]ujjbj]rbj)rb}rb(jXti.sdo.ipc.heaps.HeapMultiBufMPrbjjbjjajjj}rb(j]j]j]j]j]ujK-j]rbjXti.sdo.ipc.heaps.HeapMultiBufMPrbrb}rb(jjbjjbubaubajj ubj )rb}rb(jUj}rb(j]j]j]j]j]ujjbj]rbj)rb}rb(jXuMultiple fixed-sized shared memory Heaps. See `HeapMP Module `__jjbjjajjj}rb(j]j]j]j]j]ujK-j]rb(jX.Multiple fixed-sized shared memory Heaps. See rbrb}rb(jX.Multiple fixed-sized shared memory Heaps. See jjbubj)rb}rb(jXG`HeapMP Module `__j}rb(UnameX HeapMP ModulejX0index_Foundational_Components.html#heapmp-modulej]j]j]j]j]ujjbj]rbjX HeapMP Modulerbrb}rb(jUjjbubajjubeubajj ubejj ubj )rb}rb(jUj}rb(j]j]j]j]j]ujj,bj]rb(j )rb}rb(jUj}rb(j]j]j]j]j]ujjbj]rbj)rc}rc(jXA`Ipc Module `__rcjjbjjajjj}rc(j]j]j]j]j]ujK4j]rcj)rc}rc(jjcj}rc(UnameX Ipc ModulejX-index_Foundational_Components.html#ipc-modulej]j]j]j]j]ujjcj]rcjX Ipc Moduler cr c}r c(jUjjcubajjubaubajj ubj )r c}r c(jUj}rc(j]j]j]j]j]ujjbj]rcj)rc}rc(jXti.sdo.ipc.Ipcrcjj cjjajjj}rc(j]j]j]j]j]ujK4j]rcjXti.sdo.ipc.Ipcrcrc}rc(jjcjjcubaubajj ubj )rc}rc(jUj}rc(j]j]j]j]j]ujjbj]rcj)rc}rc(jXProvides Ipc_start() function and allows startup sequence configuration. See `IPC Module `__jjcjjajjj}rc(j]j]j]j]j]ujK4j]rc(jXMProvides Ipc_start() function and allows startup sequence configuration. See r cr!c}r"c(jXMProvides Ipc_start() function and allows startup sequence configuration. See jjcubj)r#c}r$c(jXA`IPC Module `__j}r%c(UnameX IPC ModulejX-index_Foundational_Components.html#ipc-modulej]j]j]j]j]ujjcj]r&cjX IPC Moduler'cr(c}r)c(jUjj#cubajjubeubajj ubejj ubj )r*c}r+c(jUj}r,c(j]j]j]j]j]ujj,bj]r-c(j )r.c}r/c(jUj}r0c(j]j]j]j]j]ujj*cj]r1cj)r2c}r3c(jXG`ListMP Module `__r4cjj.cjjajjj}r5c(j]j]j]j]j]ujKc}r?c(jUj}r@c(j]j]j]j]j]ujj*cj]rAcj)rBc}rCc(jXti.sdo.ipc.ListMPrDcjj>cjjajjj}rEc(j]j]j]j]j]ujK`__jjJcjjajjj}rPc(j]j]j]j]j]ujK`__j}rWc(UnameX ListMP ModulejX0index_Foundational_Components.html#listmp-modulej]j]j]j]j]ujjNcj]rXcjX ListMP ModulerYcrZc}r[c(jUjjUcubajjubeubajj ubejj ubj )r\c}r]c(jUj}r^c(j]j]j]j]j]ujj,bj]r_c(j )r`c}rac(jUj}rbc(j]j]j]j]j]ujj\cj]rccj)rdc}rec(jXK`MessageQ Module `__rfcjj`cjjajjj}rgc(j]j]j]j]j]ujKEj]rhcj)ric}rjc(jjfcj}rkc(UnameXMessageQ ModulejX2index_Foundational_Components.html#messageq-modulej]j]j]j]j]ujjdcj]rlcjXMessageQ Modulermcrnc}roc(jUjjicubajjubaubajj ubj )rpc}rqc(jUj}rrc(j]j]j]j]j]ujj\cj]rscj)rtc}ruc(jXti.sdo.ipc.MessageQrvcjjpcjjajjj}rwc(j]j]j]j]j]ujKEj]rxcjXti.sdo.ipc.MessageQrycrzc}r{c(jjvcjjtcubaubajj ubj )r|c}r}c(jUj}r~c(j]j]j]j]j]ujj\cj]rcj)rc}rc(jXoVariable size messaging module. See `MessageQ Module `__jj|cjjajjj}rc(j]j]j]j]j]ujKEj]rc(jX$Variable size messaging module. See rcrc}rc(jX$Variable size messaging module. See jjcubj)rc}rc(jXK`MessageQ Module `__j}rc(UnameXMessageQ ModulejX2index_Foundational_Components.html#messageq-modulej]j]j]j]j]ujjcj]rcjXMessageQ Modulercrc}rc(jUjjcubajjubeubajj ubejj ubj )rc}rc(jUj}rc(j]j]j]j]j]ujj,bj]rc(j )rc}rc(jUj}rc(j]j]j]j]j]ujjcj]rcj)rc}rc(jX TransportShmrcjjcjjajjj}rc(j]j]j]j]j]ujKLj]rcjX TransportShmrcrc}rc(jjcjjcubaubajj ubj )rc}rc(jUj}rc(j]j]j]j]j]ujjcj]rcj)rc}rc(jX"ti.sdo.ipc.transports.TransportShmrcjjcjjajjj}rc(j]j]j]j]j]ujKLj]rcjX"ti.sdo.ipc.transports.TransportShmrcrc}rc(jjcjjcubaubajj ubj )rc}rc(jUj}rc(j]j]j]j]j]ujjcj]rcj)rc}rc(jXTransport used by MessageQ for remote communication with other processors via shared memory. See `MessageQ Module `__jjcjjajjj}rc(j]j]j]j]j]ujKLj]rc(jXaTransport used by MessageQ for remote communication with other processors via shared memory. See rcrc}rc(jXaTransport used by MessageQ for remote communication with other processors via shared memory. See jjcubj)rc}rc(jXK`MessageQ Module `__j}rc(UnameXMessageQ ModulejX2index_Foundational_Components.html#messageq-modulej]j]j]j]j]ujjcj]rcjXMessageQ Modulercrc}rc(jUjjcubajjubeubajj ubejj ubj )rc}rc(jUj}rc(j]j]j]j]j]ujj,bj]rc(j )rc}rc(jUj}rc(j]j]j]j]j]ujjcj]rcj)rc}rc(jXG`Notify Module `__rcjjcjjajjj}rc(j]j]j]j]j]ujKUj]rcj)rc}rc(jjcj}rc(UnameX Notify ModulejX0index_Foundational_Components.html#notify-modulej]j]j]j]j]ujjcj]rcjX Notify Modulercrc}rc(jUjjcubajjubaubajj ubj )rc}rc(jUj}rc(j]j]j]j]j]ujjcj]rcj)rc}rc(jXti.sdo.ipc.Notifyrcjjcjjajjj}rc(j]j]j]j]j]ujKUj]rcjXti.sdo.ipc.Notifyrcrc}rc(jjcjjcubaubajj ubj )rc}rc(jUj}rc(j]j]j]j]j]ujjcj]rcj)rc}rc(jXsLow-level interrupt mux/demuxer module. See `Notify Module `__jjcjjajjj}rc(j]j]j]j]j]ujKUj]rc(jX,Low-level interrupt mux/demuxer module. See rcrc}rc(jX,Low-level interrupt mux/demuxer module. See jjcubj)rc}rc(jXG`Notify Module `__j}rc(UnameX Notify ModulejX0index_Foundational_Components.html#notify-modulej]j]j]j]j]ujjcj]rcjX Notify Modulercrc}rc(jUjjcubajjubeubajj ubejj ubj )rc}rc(jUj}rc(j]j]j]j]j]ujj,bj]rc(j )rc}rc(jUj}rc(j]j]j]j]j]ujjcj]rcj)rc}rc(jXNotifyDriverShmrcjjcjjajjj}rc(j]j]j]j]j]ujK\j]rcjXNotifyDriverShmrcrc}rc(jjcjjcubaubajj ubj )rc}rc(jUj}rd(j]j]j]j]j]ujjcj]rdj)rd}rd(jX)ti.sdo.ipc.notifyDrivers. NotifyDriverShmrdjjcjjajjj}rd(j]j]j]j]j]ujK\j]rdjX)ti.sdo.ipc.notifyDrivers. NotifyDriverShmrdrd}r d(jjdjjdubaubajj ubj )r d}r d(jUj}r d(j]j]j]j]j]ujjcj]r dj)rd}rd(jXShared memory notification driver used by the Notify module to communicate between a pair of processors. See `Notify Module `__jj djjajjj}rd(j]j]j]j]j]ujK\j]rd(jXmShared memory notification driver used by the Notify module to communicate between a pair of processors. See rdrd}rd(jXmShared memory notification driver used by the Notify module to communicate between a pair of processors. See jjdubj)rd}rd(jXG`Notify Module `__j}rd(UnameX Notify ModulejX0index_Foundational_Components.html#notify-modulej]j]j]j]j]ujjdj]rdjX Notify Modulerdrd}rd(jUjjdubajjubeubajj ubejj ubj )rd}rd(jUj}rd(j]j]j]j]j]ujj,bj]rd(j )r d}r!d(jUj}r"d(j]j]j]j]j]ujjdj]r#dj)r$d}r%d(jXT`SharedRegion Module `__r&djj djjajjj}r'd(j]j]j]j]j]ujKej]r(dj)r)d}r*d(jj&dj}r+d(UnameXSharedRegion ModulejX7index_Foundational_Components.html#shared-region-modulej]j]j]j]j]ujj$dj]r,djXSharedRegion Moduler-dr.d}r/d(jUjj)dubajjubaubajj ubj )r0d}r1d(jUj}r2d(j]j]j]j]j]ujjdj]r3dj)r4d}r5d(jXti.sdo.ipc.SharedRegionr6djj0djjajjj}r7d(j]j]j]j]j]ujKej]r8djXti.sdo.ipc.SharedRegionr9dr:d}r;d(jj6djj4dubaubajj ubj )rd(j]j]j]j]j]ujjdj]r?dj)r@d}rAd(jXMaintains shared memory for multiple shared regions. See `SharedRegion Module `__jj`__j}rId(UnameXSharedRegion ModulejX7index_Foundational_Components.html#shared-region-modulej]j]j]j]j]ujj@dj]rJdjXSharedRegion ModulerKdrLd}rMd(jUjjGdubajjubeubajj ubejj ubejj ubejj ubajj ubaubj)rNd}rOd(jXAdditional modules in the subfolders of the ti.sdo.ipc package contain specific implementations of gates, heaps, notify drivers, transports, and various device family-specific modules.rPdjjajjajjj}rQd(j]j]j]j]j]ujKmjhj]rRdjXAdditional modules in the subfolders of the ti.sdo.ipc package contain specific implementations of gates, heaps, notify drivers, transports, and various device family-specific modules.rSdrTd}rUd(jjPdjjNdubaubj)rVd}rWd(jXwIn addition, the ti.sdo.ipc package defines the following interfaces that you may implement as your own custom modules:rXdjjajjajjj}rYd(j]j]j]j]j]ujKpjhj]rZdjXwIn addition, the ti.sdo.ipc package defines the following interfaces that you may implement as your own custom modules:r[dr\d}r]d(jjXdjjVdubaubj3)r^d}r_d(jUjjajjajj6j}r`d(j]j]j]j]j]ujNjhj]radjy )rbd}rcd(jUj}rdd(j]j]j]j]j]ujj^dj]redj~ )rfd}rgd(jUj}rhd(j]j]j]j]j]UcolsKujjbdj]rid(j )rjd}rkd(jUj}rld(j]j]j]j]j]UcolwidthKujjfdj]jj ubj )rmd}rnd(jUj}rod(j]j]j]j]j]UcolwidthK*ujjfdj]jj ubj )rpd}rqd(jUj}rrd(j]j]j]j]j]ujjfdj]rsdj )rtd}rud(jUj}rvd(j]j]j]j]j]ujjpdj]rwd(j )rxd}ryd(jUj}rzd(j]j]j]j]j]ujjtdj]r{dj)r|d}r}d(jXModuler~djjxdjjajjj}rd(j]j]j]j]j]ujKsj]rdjXModulerdrd}rd(jj~djj|dubaubajj ubj )rd}rd(jUj}rd(j]j]j]j]j]ujjtdj]rdj)rd}rd(jX Module Pathrdjjdjjajjj}rd(j]j]j]j]j]ujKsj]rdjX Module Pathrdrd}rd(jjdjjdubaubajj ubejj ubajj ubj )rd}rd(jUj}rd(j]j]j]j]j]ujjfdj]rd(j )rd}rd(jUj}rd(j]j]j]j]j]ujjdj]rd(j )rd}rd(jUj}rd(j]j]j]j]j]ujjdj]rdj)rd}rd(jXIGateMPSupportrdjjdjjajjj}rd(j]j]j]j]j]ujKuj]rdjXIGateMPSupportrdrd}rd(jjdjjdubaubajj ubj )rd}rd(jUj}rd(j]j]j]j]j]ujjdj]rdj)rd}rd(jX$ti.sdo.ipc.interfaces.IGateMPSupportrdjjdjjajjj}rd(j]j]j]j]j]ujKuj]rdjX$ti.sdo.ipc.interfaces.IGateMPSupportrdrd}rd(jjdjjdubaubajj ubejj ubj )rd}rd(jUj}rd(j]j]j]j]j]ujjdj]rd(j )rd}rd(jUj}rd(j]j]j]j]j]ujjdj]rdj)rd}rd(jX IInterruptrdjjdjjajjj}rd(j]j]j]j]j]ujKwj]rdjX IInterruptrdrd}rd(jjdjjdubaubajj ubj )rd}rd(jUj}rd(j]j]j]j]j]ujjdj]rdj)rd}rd(jX#ti.sdo.ipc.notifyDrivers.IInterruptrdjjdjjajjj}rd(j]j]j]j]j]ujKwj]rdjX#ti.sdo.ipc.notifyDrivers.IInterruptrdrd}rd(jjdjjdubaubajj ubejj ubj )rd}rd(jUj}rd(j]j]j]j]j]ujjdj]rd(j )rd}rd(jUj}rd(j]j]j]j]j]ujjdj]rdj)rd}rd(jXIMessageQTransportrdjjdjjajjj}rd(j]j]j]j]j]ujKyj]rdjXIMessageQTransportrdrd}rd(jjdjjdubaubajj ubj )rd}rd(jUj}rd(j]j]j]j]j]ujjdj]rdj)rd}rd(jX(ti.sdo.ipc.interfaces.IMessageQTransportrdjjdjjajjj}rd(j]j]j]j]j]ujKyj]rdjX(ti.sdo.ipc.interfaces.IMessageQTransportrdrd}rd(jjdjjdubaubajj ubejj ubj )rd}rd(jUj}rd(j]j]j]j]j]ujjdj]rd(j )rd}rd(jUj}rd(j]j]j]j]j]ujjdj]rdj)rd}rd(jX INotifyDriverrdjjdjjajjj}rd(j]j]j]j]j]ujK{j]rdjX INotifyDriverrdrd}rd(jjdjjdubaubajj ubj )rd}rd(jUj}rd(j]j]j]j]j]ujjdj]rdj)rd}rd(jX#ti.sdo.ipc.interfaces.INotifyDriverrdjjdjjajjj}rd(j]j]j]j]j]ujK{j]rejX#ti.sdo.ipc.interfaces.INotifyDriverrere}re(jjdjjdubaubajj ubejj ubj )re}re(jUj}re(j]j]j]j]j]ujjdj]re(j )re}r e(jUj}r e(j]j]j]j]j]ujjej]r ej)r e}r e(jX INotifySetuprejjejjajjj}re(j]j]j]j]j]ujK}j]rejX INotifySetuprere}re(jjejj eubaubajj ubj )re}re(jUj}re(j]j]j]j]j]ujjej]rej)re}re(jX"ti.sdo.ipc.interfaces.INotifySetuprejjejjajjj}re(j]j]j]j]j]ujK}j]rejX"ti.sdo.ipc.interfaces.INotifySetuprere}re(jjejjeubaubajj ubejj ubejj ubejj ubajj ubaubj)r e}r!e(jXxThe ``/packages/ti/sdo/ipc`` directory contains the following packages that you may need to know about:r"ejjajjajjj}r#e(j]j]j]j]j]ujKjhj]r$e(jXThe r%er&e}r'e(jXThe jj eubj)r(e}r)e(jX)``/packages/ti/sdo/ipc``j}r*e(j]j]j]j]j]ujj ej]r+ejX%/packages/ti/sdo/ipcr,er-e}r.e(jUjj(eubajjubjXK directory contains the following packages that you may need to know about:r/er0e}r1e(jXK directory contains the following packages that you may need to know about:jj eubeubj3)r2e}r3e(jUjjajNjj6j}r4e(j]j]j]j]j]ujNjhj]r5ejt)r6e}r7e(jUj}r8e(jyX-j]j]j]j]j]ujj2ej]r9e(j{)r:e}r;e(jX **examples.** Contains examples.rej)r?e}r@e(jj/packages/ti/ipc/``. These header files offer a common API for both SYS/BIOS and HLOS users of IPC.jjejjajjj}re(j]j]j]j]j]ujKjhj]re(jXBIOS applications that use modules in the ti.sdo.ipc or ti.sdo.utils package should include the common header files provided in rere}re(jXBIOS applications that use modules in the ti.sdo.ipc or ti.sdo.utils package should include the common header files provided in jjeubj)re}re(jX&``/packages/ti/ipc/``j}re(j]j]j]j]j]ujjej]rejX"/packages/ti/ipc/rere}re(jUjjeubajjubjXP. These header files offer a common API for both SYS/BIOS and HLOS users of IPC.rere}re(jXP. These header files offer a common API for both SYS/BIOS and HLOS users of IPC.jjeubeubj)re}re(jXThe following example C code includes header files applications may need to use. Depending on the APIs used in your application code, you may need to include different XDC, IPC, and SYS/BIOS header files.rejjejjajjj}re(j]j]j]j]j]ujKjhj]rejXThe following example C code includes header files applications may need to use. Depending on the APIs used in your application code, you may need to include different XDC, IPC, and SYS/BIOS header files.rere}re(jjejjeubaubj)re}re(jX#include #include /* ---- XDC.RUNTIME module Headers */ #include #include #include /* ----- IPC module Headers */ #include #include #include #include #include /* ---- BIOS6 module Headers */ #include #include /* ---- Get globals from .cfg Header */ #include jjejjajjj}re(j@jAj]j]j]j]j]ujMjhj]rejX#include #include /* ---- XDC.RUNTIME module Headers */ #include #include #include /* ----- IPC module Headers */ #include #include #include #include #include /* ---- BIOS6 module Headers */ #include #include /* ---- Get globals from .cfg Header */ #include rere}re(jUjjeubaubj)re}re(jXNote that the appropriate include file location has changed from previous versions of IPC. The XDCtools-generated header files are still available in ``/packages/ti/sdo/ipc/``, but these should not directly be included in runtime .c code. You should search your applications for "ti/sdo/ipc" and "ti/sdo/utils" and change the header file references found as needed. Additional changes to API calls will be needed.jjejjajjj}re(j]j]j]j]j]ujKjhj]re(jXNote that the appropriate include file location has changed from previous versions of IPC. The XDCtools-generated header files are still available in rere}re(jXNote that the appropriate include file location has changed from previous versions of IPC. The XDCtools-generated header files are still available in jjeubj)re}re(jX*``/packages/ti/sdo/ipc/``j}re(j]j]j]j]j]ujjej]rejX&/packages/ti/sdo/ipc/rere}re(jUjjeubajjubjX, but these should not directly be included in runtime .c code. You should search your applications for "ti/sdo/ipc" and "ti/sdo/utils" and change the header file references found as needed. Additional changes to API calls will be needed.rere}re(jX, but these should not directly be included in runtime .c code. You should search your applications for "ti/sdo/ipc" and "ti/sdo/utils" and change the header file references found as needed. Additional changes to API calls will be needed.jjeubeubj)re}re(jXT|ipcSdoRun_Img1| Documentation for all common-header APIs is provided in Doxygen format in your IPC installation at ``/docs/doxygen/html/index.html``. The latest version of that documentation is available `online `__.jjejjajjj}rf(j]j]j]j]j]ujKjhj]rf(j)rf}rf(jjajjejNjjj}rf(Urefurijaj]j]j]j]j]ujNjhj]rfjR)rf}rf(jjajjfjNjjZj}rf(UuriXrtos/../images/Book_run.pngr fj]j]j]j]jX}r fU*j fsj]UaltjaujNj]ubaubjXd Documentation for all common-header APIs is provided in Doxygen format in your IPC installation at r fr f}r f(jXd Documentation for all common-header APIs is provided in Doxygen format in your IPC installation at jjeubj)rf}rf(jX2``/docs/doxygen/html/index.html``j}rf(j]j]j]j]j]ujjej]rfjX./docs/doxygen/html/index.htmlrfrf}rf(jUjjfubajjubjX8. The latest version of that documentation is available rfrf}rf(jX8. The latest version of that documentation is available jjeubj)rf}rf(jXu`online `__j}rf(UnameXonlinejXhhttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/files.htmlj]j]j]j]j]ujjej]rfjXonlinerfrf}rf(jUjjfubajjubjX.rf}r f(jX.jjeubeubeubj)r!f}r"f(jUjjajjajjj}r#f(j]j]j]j]r$fU#standard-ipc-function-call-sequencer%faj]r&fhaujKjhj]r'f(j)r(f}r)f(jX#Standard IPC Function Call Sequencer*fjj!fjjajjj}r+f(j]j]j]j]j]ujKjhj]r,fjX#Standard IPC Function Call Sequencer-fr.f}r/f(jj*fjj(fubaubj)r0f}r1f(jXvFor instance-based modules in IPC, the standard IPC methodology when creating object dynamically (that is, in C code) is to have the creator thread first initialize a *MODULE*\ \_Params structure to its default values via a *MODULE*\ \_Params_init() function. The creator thread can then set individual parameter fields in this structure as needed. After setting up the *MODULE*\ \_Params structure, the creator thread calls the *MODULE*\ \_create() function to creates the instance and initializes any shared memory used by the instance. If the instance is to be opened remotely, a unique name must be supplied in the parameters.jj!fjjajjj}r2f(j]j]j]j]j]ujKjhj]r3f(jXFor instance-based modules in IPC, the standard IPC methodology when creating object dynamically (that is, in C code) is to have the creator thread first initialize a r4fr5f}r6f(jXFor instance-based modules in IPC, the standard IPC methodology when creating object dynamically (that is, in C code) is to have the creator thread first initialize a jj0fubjM)r7f}r8f(jX*MODULE*j}r9f(j]j]j]j]j]ujj0fj]r:fjXMODULEr;frfr?f}r@f(jX1\ \_Params structure to its default values via a jj0fubjM)rAf}rBf(jX*MODULE*j}rCf(j]j]j]j]j]ujj0fj]rDfjXMODULErEfrFf}rGf(jUjjAfubajjUubjX_Params_init() function. The creator thread can then set individual parameter fields in this structure as needed. After setting up the rHfrIf}rJf(jX\ \_Params_init() function. The creator thread can then set individual parameter fields in this structure as needed. After setting up the jj0fubjM)rKf}rLf(jX*MODULE*j}rMf(j]j]j]j]j]ujj0fj]rNfjXMODULErOfrPf}rQf(jUjjKfubajjUubjX0_Params structure, the creator thread calls the rRfrSf}rTf(jX3\ \_Params structure, the creator thread calls the jj0fubjM)rUf}rVf(jX*MODULE*j}rWf(j]j]j]j]j]ujj0fj]rXfjXMODULErYfrZf}r[f(jUjjUfubajjUubjX_create() function to creates the instance and initializes any shared memory used by the instance. If the instance is to be opened remotely, a unique name must be supplied in the parameters.r\fr]f}r^f(jX\ \_create() function to creates the instance and initializes any shared memory used by the instance. If the instance is to be opened remotely, a unique name must be supplied in the parameters.jj0fubeubj)r_f}r`f(jXOther threads can access this instance via the *MODULE\_*\ open() function, which returns a handle with access to the instance. The name that was used for instance creation must be used in the *MODULE*\ \_open() function.jj!fjjajjj}raf(j]j]j]j]j]ujKjhj]rbf(jX/Other threads can access this instance via the rcfrdf}ref(jX/Other threads can access this instance via the jj_fubjM)rff}rgf(jX *MODULE\_*j}rhf(j]j]j]j]j]ujj_fj]rifjXMODULE_rjfrkf}rlf(jUjjffubajjUubjXopen() function, which returns a handle with access to the instance. The name that was used for instance creation must be used in the rmfrnf}rof(jX\ open() function, which returns a handle with access to the instance. The name that was used for instance creation must be used in the jj_fubjM)rpf}rqf(jX*MODULE*j}rrf(j]j]j]j]j]ujj_fj]rsfjXMODULErtfruf}rvf(jUjjpfubajjUubjX_open() function.rwfrxf}ryf(jX\ \_open() function.jj_fubeubj)rzf}r{f(jXIn most cases, MODULE_open() functions must be called in the context of a Task. This is because the thread running the MODULE_open() function needs to be able to block (to pend on a Semaphore in this case) while waiting for the remote processor to respond. The response from the remote processor triggers a hardware interrupt, which then posts a Semaphore to allow to Task to resume execution. The exception to this rule is that MODULE_open() functions do not need to be able to block when opening an instance on the local processor.r|fjj!fjjajjj}r}f(j]j]j]j]j]ujKjhj]r~fjXIn most cases, MODULE_open() functions must be called in the context of a Task. This is because the thread running the MODULE_open() function needs to be able to block (to pend on a Semaphore in this case) while waiting for the remote processor to respond. The response from the remote processor triggers a hardware interrupt, which then posts a Semaphore to allow to Task to resume execution. The exception to this rule is that MODULE_open() functions do not need to be able to block when opening an instance on the local processor.rfrf}rf(jj|fjjzfubaubj)rf}rf(jXWhen the threads have finished using an instance, all threads that called *MODULE\_*\ open() must call *MODULE*\ \_close(). Then, the thread that called *MODULE*\ \_create() can call *MODULE*\ \_delete() to free the memory used by the instance.jj!fjjajjj}rf(j]j]j]j]j]ujKjhj]rf(jXJWhen the threads have finished using an instance, all threads that called rfrf}rf(jXJWhen the threads have finished using an instance, all threads that called jjfubjM)rf}rf(jX *MODULE\_*j}rf(j]j]j]j]j]ujjfj]rfjXMODULE_rfrf}rf(jUjjfubajjUubjXopen() must call rfrf}rf(jX\ open() must call jjfubjM)rf}rf(jX*MODULE*j}rf(j]j]j]j]j]ujjfj]rfjXMODULErfrf}rf(jUjjfubajjUubjX'_close(). Then, the thread that called rfrf}rf(jX*\ \_close(). Then, the thread that called jjfubjM)rf}rf(jX*MODULE*j}rf(j]j]j]j]j]ujjfj]rfjXMODULErfrf}rf(jUjjfubajjUubjX_create() can call rfrf}rf(jX\ \_create() can call jjfubjM)rf}rf(jX*MODULE*j}rf(j]j]j]j]j]ujjfj]rfjXMODULErfrf}rf(jUjjfubajjUubjX2_delete() to free the memory used by the instance.rfrf}rf(jX5\ \_delete() to free the memory used by the instance.jjfubeubj)rf}rf(jXNote that *all* threads that opened an instance must close that instance before the thread that created it can delete it. Also, a thread that calls *MODULE*\ \_create() cannot call *MODULE*\ \_close(). Likewise, a thread that calls *MODULE\_*\ open() cannot call *MODULE*\ \_delete().jj!fjjajjj}rf(j]j]j]j]j]ujKjhj]rf(jX Note that rfrf}rf(jX Note that jjfubjM)rf}rf(jX*all*j}rf(j]j]j]j]j]ujjfj]rfjXallrfrf}rf(jUjjfubajjUubjX threads that opened an instance must close that instance before the thread that created it can delete it. Also, a thread that calls rfrf}rf(jX threads that opened an instance must close that instance before the thread that created it can delete it. Also, a thread that calls jjfubjM)rf}rf(jX*MODULE*j}rf(j]j]j]j]j]ujjfj]rfjXMODULErfrf}rf(jUjjfubajjUubjX_create() cannot call rfrf}rf(jX\ \_create() cannot call jjfubjM)rf}rf(jX*MODULE*j}rf(j]j]j]j]j]ujjfj]rfjXMODULErfrf}rf(jUjjfubajjUubjX(_close(). Likewise, a thread that calls rfrf}rf(jX+\ \_close(). Likewise, a thread that calls jjfubjM)rf}rf(jX *MODULE\_*j}rf(j]j]j]j]j]ujjfj]rfjXMODULE_rfrf}rf(jUjjfubajjUubjXopen() cannot call rfrf}rf(jX\ open() cannot call jjfubjM)rf}rf(jX*MODULE*j}rf(j]j]j]j]j]ujjfj]rfjXMODULErfrf}rf(jUjjfubajjUubjX _delete().rfrf}rf(jX \ \_delete().jjfubeubeubj)rf}rf(jUjjajjajjj}rf(j]j]j]j]rfUerror-handling-in-ipcrfaj]rfjaujKjhj]rf(j)rf}rf(jXError Handling in IPCrfjjfjjajjj}rf(j]j]j]j]j]ujKjhj]rfjXError Handling in IPCrfrf}rf(jjfjjfubaubj)rf}rf(jXMany of the APIs provided by IPC return an integer as a status code. Your application can test the status value returned against any of the provided status constants. For example:rfjjfjjajjj}rf(j]j]j]j]j]ujKjhj]rfjXMany of the APIs provided by IPC return an integer as a status code. Your application can test the status value returned against any of the provided status constants. For example:rfrf}rg(jjfjjfubaubj)rg}rg(jXMessageQ_Msg msg; MessageQ_Handle messageQ; Int status; ... status = MessageQ_get(messageQ, &msg, MessageQ_FOREVER); if (status < 0) { System_abort("Should not happen\n"); }jjfjjajjj}rg(j@jAj]j]j]j]j]ujM8jhj]rgjXMessageQ_Msg msg; MessageQ_Handle messageQ; Int status; ... status = MessageQ_get(messageQ, &msg, MessageQ_FOREVER); if (status < 0) { System_abort("Should not happen\n"); }rgrg}rg(jUjjgubaubj)rg}r g(jXStatus constants have the following format: ``MODULE_[S|E]_CONDITION``. For example, Ipc_S_SUCCESS, MessageQ_E_FAIL, and SharedRegion_E_MEMORY are status codes that may be returned by functions in the corresponding modules. Success codes always have values greater or equal to zero. For example, Ipc_S_SUCCESS=0 and Ipc_S_ALREADYSETUP=1; both are success codes. Failure codes always have values less than zero. Therefore, the presence of an error can be detected by simply checking whether the return value is negative.jjfjjajjj}r g(j]j]j]j]j]ujKjhj]r g(jX,Status constants have the following format: r gr g}rg(jX,Status constants have the following format: jjgubj)rg}rg(jX``MODULE_[S|E]_CONDITION``j}rg(j]j]j]j]j]ujjgj]rgjXMODULE_[S|E]_CONDITIONrgrg}rg(jUjjgubajjubjX. For example, Ipc_S_SUCCESS, MessageQ_E_FAIL, and SharedRegion_E_MEMORY are status codes that may be returned by functions in the corresponding modules. Success codes always have values greater or equal to zero. For example, Ipc_S_SUCCESS=0 and Ipc_S_ALREADYSETUP=1; both are success codes. Failure codes always have values less than zero. Therefore, the presence of an error can be detected by simply checking whether the return value is negative.rgrg}rg(jX. For example, Ipc_S_SUCCESS, MessageQ_E_FAIL, and SharedRegion_E_MEMORY are status codes that may be returned by functions in the corresponding modules. Success codes always have values greater or equal to zero. For example, Ipc_S_SUCCESS=0 and Ipc_S_ALREADYSETUP=1; both are success codes. Failure codes always have values less than zero. Therefore, the presence of an error can be detected by simply checking whether the return value is negative.jjgubeubj)rg}rg(jXOther APIs provided by IPC return a handle to a created object. If the handle is NULL, an error occurred when creating the object. For example:rgjjfjjajjj}rg(j]j]j]j]j]ujKjhj]rgjXOther APIs provided by IPC return a handle to a created object. If the handle is NULL, an error occurred when creating the object. For example:rgrg}r g(jjgjjgubaubj)r!g}r"g(jX{messageQ = MessageQ_create(DSP_MESSAGEQNAME, NULL); if (messageQ == NULL) { System_abort("MessageQ_create failed\n"); }jjfjjajjj}r#g(j@jAj]j]j]j]j]ujMQjhj]r$gjX{messageQ = MessageQ_create(DSP_MESSAGEQNAME, NULL); if (messageQ == NULL) { System_abort("MessageQ_create failed\n"); }r%gr&g}r'g(jUjj!gubaubj)r(g}r)g(jXNRefer to the Doxygen documentation for status codes returned by IPC functions.r*gjjfjjajjj}r+g(j]j]j]j]j]ujM jhj]r,gjXNRefer to the Doxygen documentation for status codes returned by IPC functions.r-gr.g}r/g(jj*gjj(gubaubeubeubj)r0g}r1g(jUjjjjjjj}r2g(j]j]j]j]r3gU ipc-moduler4gaj]r5gjaujK3jhj]r6g(j)r7g}r8g(jX IPC Moduler9gjj0gjjjjj}r:g(j]j]j]j]j]ujK3jhj]r;gjX IPC Modulerg(jj9gjj7gubaubj7)r?g}r@g(jXBhttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/Ipc_Modulejj0gjj:X8source/rtos/PDK_Platform_Software/IPC/IPC_Module.rst.incrAgrBg}rCgbjj>j}rDg(j@jAj]j]j]j]j]ujKjhj]rEgjXBhttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/Ipc_ModulerFgrGg}rHg(jUjj?gubaubj)rIg}rJg(jX.. |ipcCfg_Ipc_Img1| Image:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/index.html#ti/sdo/ipc/Ipc.html jj0gjjBgjjHj}rKg(j]j]j]j]j]rLgXipcCfg_Ipc_Img1rMgaujKjhj]rNgj)rOg}rPg(jjMgj}rQg(UrefuriXvhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/index.html#ti/sdo/ipc/Ipc.htmlrRgj]j]j]j]j]ujjIgj]rSgjR)rTg}rUg(jXImage:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/index.html#ti/sdo/ipc/Ipc.htmlrVgj}rWg(UuriXrtos/../images/Book_cfg.pngrXgj]j]j]j]jX}rYgU*jXgsj]UaltjMgujjOgj]jjZubajjubaubj)rZg}r[g(jX.. |ipcCfg_Ipc_Img2| Image:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.html jj0gjjBgjjHj}r\g(j]j]j]j]j]r]gXipcCfg_Ipc_Img2r^gaujKjhj]r_gj)r`g}rag(jj^gj}rbg(UrefuriXhhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlrcgj]j]j]j]j]ujjZgj]rdgjR)reg}rfg(jXImage:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlrggj}rhg(UuriXrtos/../images/Book_cfg.pngrigj]j]j]j]jX}rjgU*jigsj]Ualtj^gujj`gj]jjZubajjubaubj)rkg}rlg(jX.. |ipcRun_Ipc_Img1| Image:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_ipc_8h.html jj0gjjBgjjHj}rmg(j]j]j]j]j]rngXipcRun_Ipc_Img1rogaujK jhj]rpgj)rqg}rrg(jjogj}rsg(UrefuriXjhttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_ipc_8h.htmlrtgj]j]j]j]j]ujjkgj]rugjR)rvg}rwg(jXImage:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_ipc_8h.htmlrxgj}ryg(UuriXrtos/../images/Book_run.pngrzgj]j]j]j]jX}r{gU*jzgsj]Ualtjogujjqgj]jjZubajjubaubj)r|g}r}g(jX.. |ipcRun_Ipc_Img2| Image:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_ipc_8h.html jj0gjjBgjjHj}r~g(j]j]j]j]j]rgXipcRun_Ipc_Img2rgaujK jhj]rgj)rg}rg(jjgj}rg(UrefuriXjhttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_ipc_8h.htmlrgj]j]j]j]j]ujj|gj]rgjR)rg}rg(jXImage:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_ipc_8h.htmlrgj}rg(UuriXrtos/../images/Book_run.pngrgj]j]j]j]jX}rgU*jgsj]Ualtjgujjgj]jjZubajjubaubjc)rg}rg(jUjj0gjjBgjjfj}rg(j]j]j]j]j]ujKjhj]rgji)rg}rg(jUjlKjjgjjBgjjj}rg(j]j]j]j]j]ujKjhj]ubaubj3)rg}rg(jUjj0gjjBgjj6j}rg(j]j]j]j]j]ujNjhj]rgjy )rg}rg(jUj}rg(j]j]j]j]j]ujjgj]rgj~ )rg}rg(jUj}rg(j]j]j]j]j]UcolsKujjgj]rg(j )rg}rg(jUj}rg(j]j]j]j]j]UcolwidthKujjgj]jj ubj )rg}rg(jUj}rg(j]j]j]j]j]UcolwidthKujjgj]jj ubj )rg}rg(jUj}rg(j]j]j]j]j]ujjgj]rgj )rg}rg(jUj}rg(j]j]j]j]j]ujjgj]rgj )rg}rg(jUj}rg(j]UmorecolsKj]j]j]j]ujjgj]rgj)rg}rg(jXAPI Reference LinksrgjjgjjBgjjj}rg(j]j]j]j]j]ujKj]rgjXAPI Reference Linksrgrg}rg(jjgjjgubaubajj ubajj ubajj ubj )rg}rg(jUj}rg(j]j]j]j]j]ujjgj]rgj )rg}rg(jUj}rg(j]j]j]j]j]ujjgj]rg(j )rg}rg(jUj}rg(j]j]j]j]j]ujjgj]rgj)rg}rg(jX|ipcCfg_Ipc_Img1|rgjjgjjBgjjj}rg(j]j]j]j]j]ujKj]rgj)rg}rg(jjMgjjgjNjjj}rg(UrefurijRgj]j]j]j]j]ujNj]rgjR)rg}rg(jjVgjjgjNjjZj}rg(UuriXrtos/../images/Book_cfg.pngrgj]j]j]j]jX}rgU*jgsj]UaltjMgujNj]ubaubaubajj ubj )rg}rg(jUj}rg(j]j]j]j]j]ujjgj]rgj)rg}rg(jX|ipcRun_Ipc_Img1|rgjjgjjBgjjj}rg(j]j]j]j]j]ujKj]rgj)rg}rg(jjogjjgjNjjj}rg(Urefurijtgj]j]j]j]j]ujNj]rgjR)rg}rg(jjxgjjgjNjjZj}rg(UuriXrtos/../images/Book_run.pngrgj]j]j]j]jX}rgU*jgsj]UaltjogujNj]ubaubaubajj ubejj ubajj ubejj ubajj ubaubj)rg}rg(jXThe main purpose of the Ipc module is to initialize the various subsystems of IPC. All applications that use IPC modules must call the Ipc_start() API, which does the following:rgjj0gjjBgjjj}rg(j]j]j]j]j]ujKjhj]rgjXThe main purpose of the Ipc module is to initialize the various subsystems of IPC. All applications that use IPC modules must call the Ipc_start() API, which does the following:rgrg}rg(jjgjjgubaubjt)rg}rg(jUjj0gjjBgjjwj}rg(jyX-j]j]j]j]j]ujKjhj]rg(j{)rg}rg(jX7Initializes a number of objects and modules used by IPCrgjjgjjBgjjj}rg(j]j]j]j]j]ujNjhj]rgj)rg}rg(jjgjjgjjBgjjj}rg(j]j]j]j]j]ujKj]rgjX7Initializes a number of objects and modules used by IPCrgrg}rg(jjgjjgubaubaubj{)rg}rg(jX?Synchronizes multiple processors so they can boot in any order jjgjjBgjjj}rh(j]j]j]j]j]ujNjhj]rhj)rh}rh(jX>Synchronizes multiple processors so they can boot in any orderrhjjgjjBgjjj}rh(j]j]j]j]j]ujKj]rhjX>Synchronizes multiple processors so they can boot in any orderrhrh}r h(jjhjjhubaubaubeubj)r h}r h(jXAn application that uses IPC APIs--such as MessageQ--must include the Ipc module header file and call Ipc_start() before any calls to IPC modules. Here is a BIOS-side example:r hjj0gjjBgjjj}r h(j]j]j]j]j]ujKjhj]rhjXAn application that uses IPC APIs--such as MessageQ--must include the Ipc module header file and call Ipc_start() before any calls to IPC modules. Here is a BIOS-side example:rhrh}rh(jj hjj hubaubj)rh}rh(jX #include int main(int argc, char* argv[]) { Int status; /* Call Ipc_start() */ status = Ipc_start(); if (status < 0) { System_abort("Ipc_start failed\n"); } BIOS_start(); return (0); }jj0gjjBgjjj}rh(jjXcj@jAj]j]j]j}j]j]ujK jhj]rhjX #include int main(int argc, char* argv[]) { Int status; /* Call Ipc_start() */ status = Ipc_start(); if (status < 0) { System_abort("Ipc_start failed\n"); } BIOS_start(); return (0); }rhrh}rh(jUjjhubaubjc)rh}rh(jUjj0gjjBgjjfj}rh(j]j]j]j]j]ujK2jhj]rhji)rh}rh(jUjlKjjhjjBgjjj}rh(j]j]j]j]j]ujKjhj]ubaubj)r h}r!h(jX9By default, the BIOS implementation of Ipc_start() internally calls Notify_start() if it has not already been called, then loops through the defined SharedRegions so that it can set up the HeapMemMP and GateMP instances used internally by the IPC modules. It also sets up MessageQ transports to remote processors.r"hjj0gjjBgjjj}r#h(j]j]j]j]j]ujK4jhj]r$hjX9By default, the BIOS implementation of Ipc_start() internally calls Notify_start() if it has not already been called, then loops through the defined SharedRegions so that it can set up the HeapMemMP and GateMP instances used internally by the IPC modules. It also sets up MessageQ transports to remote processors.r%hr&h}r'h(jj"hjj hubaubj)r(h}r)h(jXThe SharedRegion with an index of 0 (zero) is often used by BIOS-side IPC_start() to create resource management tables for internal use by other IPC modules. Thus SharedRegion "0" must be accessible by all processors. See SharedRegion Module for more about the SharedRegion module.r*hjj0gjjBgjjj}r+h(j]j]j]j]j]ujK8jhj]r,hjXThe SharedRegion with an index of 0 (zero) is often used by BIOS-side IPC_start() to create resource management tables for internal use by other IPC modules. Thus SharedRegion "0" must be accessible by all processors. See SharedRegion Module for more about the SharedRegion module.r-hr.h}r/h(jj*hjj(hubaubj)r0h}r1h(jUjj0gjjBgjjj}r2h(j]j]j]j]r3hU'ipc-module-configuration-bios-side-onlyr4haj]r5hjaujK=jhj]r6h(j)r7h}r8h(jX)Ipc Module Configuration (BIOS-side only)r9hjj0hjjBgjjj}r:h(j]j]j]j]j]ujK=jhj]r;hjX)Ipc Module Configuration (BIOS-side only)rh(jj9hjj7hubaubj)r?h}r@h(jXSIn an XDCtools configuration file, you configure the Ipc module for use as follows:rAhjj0hjjBgjjj}rBh(j]j]j]j]j]ujK>jhj]rChjXSIn an XDCtools configuration file, you configure the Ipc module for use as follows:rDhrEh}rFh(jjAhjj?hubaubj)rGh}rHh(jX&Ipc = xdc.useModule('ti.sdo.ipc.Ipc');jj0hjjBgjjj}rIh(j@jAj]j]j]j]j]ujMjhj]rJhjX&Ipc = xdc.useModule('ti.sdo.ipc.Ipc');rKhrLh}rMh(jUjjGhubaubj)rNh}rOh(jXYou can configure what the Ipc_start() API will do--which modules it will start and which objects it will create--by using the Ipc.setEntryMeta method in the configuration file to set the following properties:rPhjj0hjjBgjjj}rQh(j]j]j]j]j]ujKEjhj]rRhjXYou can configure what the Ipc_start() API will do--which modules it will start and which objects it will create--by using the Ipc.setEntryMeta method in the configuration file to set the following properties:rShrTh}rUh(jjPhjjNhubaubjt)rVh}rWh(jUjj0hjjBgjjwj}rXh(jyX-j]j]j]j]j]ujKHjhj]rYh(j{)rZh}r[h(jXW**setupNotify.** If set to false, the Notify module is not set up. The default is true.r\hjjVhjjBgjjj}r]h(j]j]j]j]j]ujNjhj]r^hj)r_h}r`h(jj\hjjZhjjBgjjj}rah(j]j]j]j]j]ujKHj]rbh(j)rch}rdh(jX**setupNotify.**j}reh(j]j]j]j]j]ujj_hj]rfhjX setupNotify.rghrhh}rih(jUjjchubajjubjXG If set to false, the Notify module is not set up. The default is true.rjhrkh}rlh(jXG If set to false, the Notify module is not set up. The default is true.jj_hubeubaubj{)rmh}rnh(jX**setupMessageQ.** If set to false, the MessageQ transport instances to remote processors are not set up and the MessageQ module does not attach to remote processors. The default is true. jjVhjjBgjjj}roh(j]j]j]j]j]ujNjhj]rphj)rqh}rrh(jX**setupMessageQ.** If set to false, the MessageQ transport instances to remote processors are not set up and the MessageQ module does not attach to remote processors. The default is true.jjmhjjBgjjj}rsh(j]j]j]j]j]ujKIj]rth(j)ruh}rvh(jX**setupMessageQ.**j}rwh(j]j]j]j]j]ujjqhj]rxhjXsetupMessageQ.ryhrzh}r{h(jUjjuhubajjubjX If set to false, the MessageQ transport instances to remote processors are not set up and the MessageQ module does not attach to remote processors. The default is true.r|hr}h}r~h(jX If set to false, the MessageQ transport instances to remote processors are not set up and the MessageQ module does not attach to remote processors. The default is true.jjqhubeubaubeubj)rh}rh(jXFor example, the following statements from the notify example configuration turn off the setup of the MessageQ transports and connections to remote processors:rhjj0hjjBgjjj}rh(j]j]j]j]j]ujKLjhj]rhjXFor example, the following statements from the notify example configuration turn off the setup of the MessageQ transports and connections to remote processors:rhrh}rh(jjhjjhubaubj)rh}rh(jX/* To avoid wasting shared memory for MessageQ transports */ for (var i = 0; i < MultiProc.numProcessors; i++) { Ipc.setEntryMeta({ remoteProcId: i, setupMessageQ: false, }); }jj0hjjBgjjj}rh(jjXcj@jAj]j]j]j}j]j]ujKNjhj]rhjX/* To avoid wasting shared memory for MessageQ transports */ for (var i = 0; i < MultiProc.numProcessors; i++) { Ipc.setEntryMeta({ remoteProcId: i, setupMessageQ: false, }); }rhrh}rh(jUjjhubaubj)rh}rh(jXsYou can configure how the IPC module synchronizes processors by configuring the Ipc.procSync property. For example:rhjj0hjjBgjjj}rh(j]j]j]j]j]ujKXjhj]rhjXsYou can configure how the IPC module synchronizes processors by configuring the Ipc.procSync property. For example:rhrh}rh(jjhjjhubaubj)rh}rh(jX Ipc.procSync = Ipc.ProcSync_ALL;jj0hjjBgjjj}rh(j@jAj]j]j]j]j]ujMjhj]rhjX Ipc.procSync = Ipc.ProcSync_ALL;rhrh}rh(jUjjhubaubj)rh}rh(jXThe options are:rhjj0hjjBgjjj}rh(j]j]j]j]j]ujK_jhj]rhjXThe options are:rhrh}rh(jjhjjhubaubjt)rh}rh(jUjj0hjjBgjjwj}rh(jyX-j]j]j]j]j]ujKajhj]rh(j{)rh}rh(jXeIpc.ProcSync_ALL. If you use this option, the Ipc_start() API automatically attaches to and synchronizes all remote processors. If you use this option, your application should never call Ipc_attach(). Use this option if all IPC processors on a device start up at the same time and connections should be established between every possible pair of processors.jjhjjBgjjj}rh(j]j]j]j]j]ujNjhj]rhj)rh}rh(jXeIpc.ProcSync_ALL. If you use this option, the Ipc_start() API automatically attaches to and synchronizes all remote processors. If you use this option, your application should never call Ipc_attach(). Use this option if all IPC processors on a device start up at the same time and connections should be established between every possible pair of processors.rhjjhjjBgjjj}rh(j]j]j]j]j]ujKaj]rhjXeIpc.ProcSync_ALL. If you use this option, the Ipc_start() API automatically attaches to and synchronizes all remote processors. If you use this option, your application should never call Ipc_attach(). Use this option if all IPC processors on a device start up at the same time and connections should be established between every possible pair of processors.rhrh}rh(jjhjjhubaubaubj{)rh}rh(jXIpc.ProcSync_PAIR. (Default) If you use this option, you must explicitly call Ipc_attach() to attach to a specific remote processor. If you use this option, Ipc_start() performs system-wide IPC initialization, but does not make connections to remote processors. Use this option if any or all of the following are true: - You need to control when synchronization with each remote processor occurs. - Useful work can be done while trying to synchronize with a remote processor by yielding a thread after each attempt to Ipc_attach() to the processor. - Connections to some remote processors are unnecessary and should be made selectively to save memory. - Ipc.ProcSync_NONE. If you use this option, Ipc_start() doesn't synchronize any processors before setting up the objects needed by other modules. Use this option with caution. It is intended for use in cases where the application performs its own synchronization and you want to avoid a potential deadlock situation with the IPC synchronization. If you use the ProcSync_NONE option, Ipc_start() works exactly as it does with ProcSync_PAIR. : However, in this case, Ipc_attach() does not synchronize with the remote processor. As with other ProcSync options, Ipc_attach() still sets up access to GateMP, SharedRegion, Notify, NameServer, and MessageQ transports, so your application must still call Ipc_attach() for each remote processor that will be accessed. Note that an Ipc_attach() call for a remote processor whose ID is less than the local processor's ID must occur after the corresponding remote processor has called Ipc_attach() to the local processor. For example, processor #2 can call Ipc_attach(1) only after processor #1 has called Ipc_attach(2).: jjhjjBgjjj}rh(j]j]j]j]j]ujNjhj]rh(j)rh}rh(jXIpc.ProcSync_PAIR. (Default) If you use this option, you must explicitly call Ipc_attach() to attach to a specific remote processor.rhjjhjjBgjjj}rh(j]j]j]j]j]ujKdj]rhjXIpc.ProcSync_PAIR. (Default) If you use this option, you must explicitly call Ipc_attach() to attach to a specific remote processor.rhrh}rh(jjhjjhubaubj3)rh}rh(jUj}rh(j]j]j]j]j]ujjhj]rhj)rh}rh(jXIf you use this option, Ipc_start() performs system-wide IPC initialization, but does not make connections to remote processors. Use this option if any or all of the following are true: - You need to control when synchronization with each remote processor occurs. - Useful work can be done while trying to synchronize with a remote processor by yielding a thread after each attempt to Ipc_attach() to the processor. - Connections to some remote processors are unnecessary and should be made selectively to save memory. - Ipc.ProcSync_NONE. If you use this option, Ipc_start() doesn't synchronize any processors before setting up the objects needed by other modules.rhjjhjjBgjjj}rh(j]j]j]j]j]ujKfj]rhjXIf you use this option, Ipc_start() performs system-wide IPC initialization, but does not make connections to remote processors. Use this option if any or all of the following are true: - You need to control when synchronization with each remote processor occurs. - Useful work can be done while trying to synchronize with a remote processor by yielding a thread after each attempt to Ipc_attach() to the processor. - Connections to some remote processors are unnecessary and should be made selectively to save memory. - Ipc.ProcSync_NONE. If you use this option, Ipc_start() doesn't synchronize any processors before setting up the objects needed by other modules.rhrh}rh(jjhjjhubaubajj6ubj)rh}rh(jXUse this option with caution. It is intended for use in cases where the application performs its own synchronization and you want to avoid a potential deadlock situation with the IPC synchronization.rhjjhjjBgjjj}rh(j]j]j]j]j]ujKmj]rhjXUse this option with caution. It is intended for use in cases where the application performs its own synchronization and you want to avoid a potential deadlock situation with the IPC synchronization.rhrh}rh(jjhjjhubaubj)rh}rh(jXIf you use the ProcSync_NONE option, Ipc_start() works exactly as it does with ProcSync_PAIR. : However, in this case, Ipc_attach() does not synchronize with the remote processor. As with other ProcSync options, Ipc_attach() still sets up access to GateMP, SharedRegion, Notify, NameServer, and MessageQ transports, so your application must still call Ipc_attach() for each remote processor that will be accessed. Note that an Ipc_attach() call for a remote processor whose ID is less than the local processor's ID must occur after the corresponding remote processor has called Ipc_attach() to the local processor. For example, processor #2 can call Ipc_attach(1) only after processor #1 has called Ipc_attach(2).:rhjjhjjBgjjj}rh(j]j]j]j]j]ujKpj]rhjXIf you use the ProcSync_NONE option, Ipc_start() works exactly as it does with ProcSync_PAIR. : However, in this case, Ipc_attach() does not synchronize with the remote processor. As with other ProcSync options, Ipc_attach() still sets up access to GateMP, SharedRegion, Notify, NameServer, and MessageQ transports, so your application must still call Ipc_attach() for each remote processor that will be accessed. Note that an Ipc_attach() call for a remote processor whose ID is less than the local processor's ID must occur after the corresponding remote processor has called Ipc_attach() to the local processor. For example, processor #2 can call Ipc_attach(1) only after processor #1 has called Ipc_attach(2).:rhrh}rh(jjhjjhubaubeubeubj)rh}rh(jXYou can configure a function to perform custom actions in addition to the default actions performed when attaching to or detaching from a remote processor. These functions run near the end of Ipc_attach() and near the beginning of Ipc_detach(), respectively. Such functions must be non-blocking and must run to completion. The following example configures two attach functions and two detach functions. Each set of functions will be passed a different argument:rhjj0hjjBgjjj}rh(j]j]j]j]j]ujKxjhj]rhjXYou can configure a function to perform custom actions in addition to the default actions performed when attaching to or detaching from a remote processor. These functions run near the end of Ipc_attach() and near the beginning of Ipc_detach(), respectively. Such functions must be non-blocking and must run to completion. The following example configures two attach functions and two detach functions. Each set of functions will be passed a different argument:rhrh}rh(jjhjjhubaubj)rh}rh(jXvar Ipc = xdc.useModule('ti.sdo.ipc.Ipc'); var fxn = new Ipc.UserFxn; fxn.attach = '&userAttachFxn1'; fxn.detach = '&userDetachFxn1'; Ipc.addUserFxn(fxn, 0x1); fxn.attach = '&userAttachFxn2'; fxn.detach = '&userDetachFxn2'; Ipc.addUserFxn(fxn, 0x2);jj0hjjBgjjj}rh(j@jAj]j]j]j]j]ujMjhj]rhjXvar Ipc = xdc.useModule('ti.sdo.ipc.Ipc'); var fxn = new Ipc.UserFxn; fxn.attach = '&userAttachFxn1'; fxn.detach = '&userDetachFxn1'; Ipc.addUserFxn(fxn, 0x1); fxn.attach = '&userAttachFxn2'; fxn.detach = '&userDetachFxn2'; Ipc.addUserFxn(fxn, 0x2);rhrh}rh(jUjjhubaubj)rh}rh(jX|ipcCfg_Ipc_Img2| The latest version of the IPC module configuration documentation is available `here `_jj0hjjBgjjj}rh(j]j]j]j]j]ujKjhj]rh(j)rh}rh(jj^gjjhjNjjj}rh(Urefurijcgj]j]j]j]j]ujNjhj]rhjR)rh}rh(jjggjjhjNjjZj}rh(UuriXrtos/../images/Book_cfg.pngrhj]j]j]j]jX}rhU*jhsj]Ualtj^gujNj]ubaubjXO The latest version of the IPC module configuration documentation is available rhrh}rh(jXO The latest version of the IPC module configuration documentation is available jjhubj)rh}rh(jXr`here `_j}rh(Unameh@jXhhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlrhj]j]j]j]j]ujjhj]rijXhereriri}ri(jUjjhubajjubj)ri}ri(jXk jKjjhjj j}ri(Urefurijhj]riUhereriaj]j]j]j]r ih@auj]ubeubeubj)r i}r i(jUjj0gjjBgjjj}r i(j]j]j]j]r iUipc-module-apisriaj]rij?aujKjhj]ri(j)ri}ri(jXIpc Module APIsrijj ijjBgjjj}ri(j]j]j]j]j]ujKjhj]rijXIpc Module APIsriri}ri(jjijjiubaubj)ri}ri(jXIn addition to the Ipc_start() API, which all applications that use IPC modules are required to call, the Ipc module also provides the following APIs for processor synchronization:rijj ijjBgjjj}ri(j]j]j]j]j]ujKjhj]rijXIn addition to the Ipc_start() API, which all applications that use IPC modules are required to call, the Ipc module also provides the following APIs for processor synchronization:riri}r i(jjijjiubaubjt)r!i}r"i(jUjj ijjBgjjwj}r#i(jyX-j]j]j]j]j]ujKjhj]r$i(j{)r%i}r&i(jXDIpc_attach() Creates a connection to the specified remote processor.r'ijj!ijjBgjjj}r(i(j]j]j]j]j]ujNjhj]r)ij)r*i}r+i(jj'ijj%ijjBgjjj}r,i(j]j]j]j]j]ujKj]r-ijXDIpc_attach() Creates a connection to the specified remote processor.r.ir/i}r0i(jj'ijj*iubaubaubj{)r1i}r2i(jXGIpc_detach() Deletes the connection to the specified remote processor. jj!ijjBgjjj}r3i(j]j]j]j]j]ujNjhj]r4ij)r5i}r6i(jXFIpc_detach() Deletes the connection to the specified remote processor.r7ijj1ijjBgjjj}r8i(j]j]j]j]j]ujKj]r9ijXFIpc_detach() Deletes the connection to the specified remote processor.r:ir;i}ri(jXEYou must call Ipc_start() on a processor before calling Ipc_attach().r?ijj ijjBgjjj}r@i(j]j]j]j]j]ujKjhj]rAijXEYou must call Ipc_start() on a processor before calling Ipc_attach().rBirCi}rDi(jj?ijj=iubaubj)rEi}rFi(jX9Call Ipc_attach() to the processor that owns shared memory region 0--usually the processor with an id of 0--before making a connection to any other remote processor. For example, if there are three processors configured with MultiProc, processor 1 should attach to processor 0 before it can attach to processor 2.jj ijjBgjjj}rGi(j]j]j]j]j]ujNjhj]rHij)rIi}rJi(jX9Call Ipc_attach() to the processor that owns shared memory region 0--usually the processor with an id of 0--before making a connection to any other remote processor. For example, if there are three processors configured with MultiProc, processor 1 should attach to processor 0 before it can attach to processor 2.rKijjEijjBgjjj}rLi(j]j]j]j]j]ujKj]rMijX9Call Ipc_attach() to the processor that owns shared memory region 0--usually the processor with an id of 0--before making a connection to any other remote processor. For example, if there are three processors configured with MultiProc, processor 1 should attach to processor 0 before it can attach to processor 2.rNirOi}rPi(jjKijjIiubaubaubj)rQi}rRi(jXUse these functions unless you are using the Ipc.ProcSync_ALL configuration setting. With that option, Ipc_start() automatically attaches to and synchronizes all remote processors, and your application should never call Ipc_attach().rSijj ijjBgjjj}rTi(j]j]j]j]j]ujKjhj]rUijXUse these functions unless you are using the Ipc.ProcSync_ALL configuration setting. With that option, Ipc_start() automatically attaches to and synchronizes all remote processors, and your application should never call Ipc_attach().rVirWi}rXi(jjSijjQiubaubj)rYi}rZi(jXThe Ipc.ProcSync_PAIR configuration option expects that your application will call Ipc_attach() for each remote processor with which it should be able to communicate.r[ijj ijjBgjjj}r\i(j]j]j]j]j]ujKjhj]r]ijXThe Ipc.ProcSync_PAIR configuration option expects that your application will call Ipc_attach() for each remote processor with which it should be able to communicate.r^ir_i}r`i(jj[ijjYiubaubj)rai}rbi(jXIn ARM-Linux/DSP-RTOS scenario, Linux application gets the IPC configuration from LAD which has Ipc.ProcSync_ALL configured. DSP has Ipc.ProcSync_PAIR configured.jj ijjBgjjj}rci(j]j]j]j]j]ujNjhj]rdij)rei}rfi(jXIn ARM-Linux/DSP-RTOS scenario, Linux application gets the IPC configuration from LAD which has Ipc.ProcSync_ALL configured. DSP has Ipc.ProcSync_PAIR configured.rgijjaijjBgjjj}rhi(j]j]j]j]j]ujKj]riijXIn ARM-Linux/DSP-RTOS scenario, Linux application gets the IPC configuration from LAD which has Ipc.ProcSync_ALL configured. DSP has Ipc.ProcSync_PAIR configured.rjirki}rli(jjgijjeiubaubaubj)rmi}rni(jXProcessor synchronization means that one processor waits until the other processor signals that a particular module is ready for use. Within Ipc_attach(), this is done for the GateMP, SharedRegion (region 0), and Notify modules and the MessageQ transports.roijj ijjBgjjj}rpi(j]j]j]j]j]ujKjhj]rqijXProcessor synchronization means that one processor waits until the other processor signals that a particular module is ready for use. Within Ipc_attach(), this is done for the GateMP, SharedRegion (region 0), and Notify modules and the MessageQ transports.rrirsi}rti(jjoijjmiubaubj)rui}rvi(jXYou can call the Ipc_detach() API to delete internal instances created by Ipc_attach() and to free the memory used by these instances.rwijj ijjBgjjj}rxi(j]j]j]j]j]ujKjhj]ryijXYou can call the Ipc_detach() API to delete internal instances created by Ipc_attach() and to free the memory used by these instances.rzir{i}r|i(jjwijjuiubaubj)r}i}r~i(jX|ipcRun_Ipc_Img2| The latest version of the IPC module run-time API documentation is available `online `_jj ijjBgjjj}ri(j]j]j]j]j]ujKjhj]ri(j)ri}ri(jjgjj}ijNjjj}ri(Urefurijgj]j]j]j]j]ujNjhj]rijR)ri}ri(jjgjjijNjjZj}ri(UuriXrtos/../images/Book_run.pngrij]j]j]j]jX}riU*jisj]UaltjgujNj]ubaubjXN The latest version of the IPC module run-time API documentation is available riri}ri(jXN The latest version of the IPC module run-time API documentation is available jj}iubj)ri}ri(jXv`online `_j}ri(UnamehjXjhttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_ipc_8h.htmlrij]j]j]j]j]ujj}ij]rijXonlineriri}ri(jUjjiubajjubj)ri}ri(jXm jKjj}ijj j}ri(Urefurijij]riUonlineriaj]j]riXonlineriaj]j]uj]ubeubeubeubj)ri}ri(jUjjjjjjj}ri(j]j]j]j]riUmessageq-moduleriaj]rij2aujK7jhj]ri(j)ri}ri(jXMessageQ Modulerijjijjjjj}ri(j]j]j]j]j]ujK7jhj]rijXMessageQ Moduleriri}ri(jjijjiubaubj7)ri}ri(jXGhttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/MessageQ_Modulejjijj:X=source/rtos/PDK_Platform_Software/IPC/MessageQ_Module.rst.incriri}ribjj>j}ri(j@jAj]j]j]j]j]ujKjhj]rijXGhttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/MessageQ_Moduleriri}ri(jUjjiubaubj)ri}ri(jX.. |msgCfg_Img1| Image:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.html jjijjijjHj}ri(j]j]j]j]j]riX msgCfg_Img1riaujKjhj]rij)ri}ri(jjij}ri(UrefuriXhhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlrij]j]j]j]j]ujjij]rijR)ri}ri(jXImage:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlrij}ri(UuriXrtos/../images/Book_cfg.pngrij]j]j]j]jX}riU*jisj]Ualtjiujjij]jjZubajjubaubj)ri}ri(jX.. |msgCfg_Img2| Image:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.html jjijjijjHj}ri(j]j]j]j]j]riX msgCfg_Img2riaujKjhj]rij)ri}ri(jjij}ri(UrefuriXhhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlrij]j]j]j]j]ujjij]rijR)ri}ri(jXImage:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlrij}ri(UuriXrtos/../images/Book_cfg.pngrij]j]j]j]jX}riU*jisj]Ualtjiujjij]jjZubajjubaubj)ri}ri(jX.. |msgRun_Img1| Image:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_message_q_8h.html jjijjijjHj}ri(j]j]j]j]j]riX msgRun_Img1riaujK jhj]rij)ri}ri(jjij}ri(UrefuriXphttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_message_q_8h.htmlrij]j]j]j]j]ujjij]rijR)ri}ri(jXImage:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_message_q_8h.htmlrij}ri(UuriXrtos/../images/Book_run.pngrij]j]j]j]jX}riU*jisj]Ualtjiujjij]jjZubajjubaubj)ri}ri(jX.. |msgRun_Img2| Image:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_message_q_8h.html jjijjijjHj}ri(j]j]j]j]j]riX msgRun_Img2riaujK jhj]rij)ri}ri(jjij}ri(UrefuriXphttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_message_q_8h.htmlrij]j]j]j]j]ujjij]rijR)ri}ri(jXImage:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_message_q_8h.htmlrij}ri(UuriXrtos/../images/Book_run.pngrij]j]j]j]jX}riU*jisj]Ualtjiujjij]jjZubajjubaubjc)ri}ri(jUjjijjijjfj}ri(j]j]j]j]j]ujKjhj]riji)ri}ri(jUjlKjjijjijjj}ri(j]j]j]j]j]ujKjhj]ubaubj3)rj}rj(jUjjijjijj6j}rj(j]j]j]j]j]ujNjhj]rjjy )rj}rj(jUj}rj(j]j]j]j]j]ujjjj]rjj~ )rj}r j(jUj}r j(j]j]j]j]j]UcolsKujjjj]r j(j )r j}r j(jUj}rj(j]j]j]j]j]UcolwidthKujjjj]jj ubj )rj}rj(jUj}rj(j]j]j]j]j]UcolwidthKujjjj]jj ubj )rj}rj(jUj}rj(j]j]j]j]j]ujjjj]rjj )rj}rj(jUj}rj(j]j]j]j]j]ujjjj]rjj )rj}rj(jUj}rj(j]UmorecolsKj]j]j]j]ujjjj]rjj)rj}rj(jXAPI Reference Linksr jjjjjjijjj}r!j(j]j]j]j]j]ujKj]r"jjXAPI Reference Linksr#jr$j}r%j(jj jjjjubaubajj ubajj ubajj ubj )r&j}r'j(jUj}r(j(j]j]j]j]j]ujjjj]r)jj )r*j}r+j(jUj}r,j(j]j]j]j]j]ujj&jj]r-j(j )r.j}r/j(jUj}r0j(j]j]j]j]j]ujj*jj]r1jj)r2j}r3j(jX |msgCfg_Img1|r4jjj.jjjijjj}r5j(j]j]j]j]j]ujKj]r6jj)r7j}r8j(jjijj2jjNjjj}r9j(Urefurijij]j]j]j]j]ujNj]r:jjR)r;j}rjj]j]j]j]jX}r?jU*j>jsj]UaltjiujNj]ubaubaubajj ubj )r@j}rAj(jUj}rBj(j]j]j]j]j]ujj*jj]rCjj)rDj}rEj(jX |msgRun_Img1|rFjjj@jjjijjj}rGj(j]j]j]j]j]ujKj]rHjj)rIj}rJj(jjijjDjjNjjj}rKj(Urefurijij]j]j]j]j]ujNj]rLjjR)rMj}rNj(jjijjIjjNjjZj}rOj(UuriXrtos/../images/Book_run.pngrPjj]j]j]j]jX}rQjU*jPjsj]UaltjiujNj]ubaubaubajj ubejj ubajj ubejj ubajj ubaubj)rRj}rSj(jXThe MessageQ module supports the structured sending and receiving of variable length messages. It is OS independent and works with any threading model. For each MessageQ you create, there is a single reader and may be multiple writers.rTjjjijjijjj}rUj(j]j]j]j]j]ujKjhj]rVjjXThe MessageQ module supports the structured sending and receiving of variable length messages. It is OS independent and works with any threading model. For each MessageQ you create, there is a single reader and may be multiple writers.rWjrXj}rYj(jjTjjjRjubaubj)rZj}r[j(jXMessageQ is the recommended messaging API for most applications. It can be used for both homogeneous and heterogeneous multi-processor messaging, along with single-processor messaging between threads.r\jjjijjijjj}r]j(j]j]j]j]j]ujKjhj]r^jjXMessageQ is the recommended messaging API for most applications. It can be used for both homogeneous and heterogeneous multi-processor messaging, along with single-processor messaging between threads.r_jr`j}raj(jj\jjjZjubaubj)rbj}rcj(jXZThe MessageQ module in IPC is similar in functionality to the MSGQ module in DSP/BIOS 5.x.rdjjjijjijjj}rej(j]j]j]j]j]ujNjhj]rfjj)rgj}rhj(jjdjjjbjjjijjj}rij(j]j]j]j]j]ujK"j]rjjjXZThe MessageQ module in IPC is similar in functionality to the MSGQ module in DSP/BIOS 5.x.rkjrlj}rmj(jjdjjjgjubaubaubj)rnj}roj(jX6The following are key features of the MessageQ module:rpjjjijjijjj}rqj(j]j]j]j]j]ujK$jhj]rrjjX6The following are key features of the MessageQ module:rsjrtj}ruj(jjpjjjnjubaubjt)rvj}rwj(jUjjijjijjwj}rxj(jyX-j]j]j]j]j]ujK&jhj]ryj(j{)rzj}r{j(jXWWriters and readers can be relocated to another processor with no runtime code changes.r|jjjvjjjijjj}r}j(j]j]j]j]j]ujNjhj]r~jj)rj}rj(jj|jjjzjjjijjj}rj(j]j]j]j]j]ujK&j]rjjXWWriters and readers can be relocated to another processor with no runtime code changes.rjrj}rj(jj|jjjjubaubaubj{)rj}rj(jX-Timeouts are allowed when receiving messages.rjjjvjjjijjj}rj(j]j]j]j]j]ujNjhj]rjj)rj}rj(jjjjjjjjijjj}rj(j]j]j]j]j]ujK'j]rjjX-Timeouts are allowed when receiving messages.rjrj}rj(jjjjjjubaubaubj{)rj}rj(jX0Readers can determine the writer and reply back.rjjjvjjjijjj}rj(j]j]j]j]j]ujNjhj]rjj)rj}rj(jjjjjjjjijjj}rj(j]j]j]j]j]ujK(j]rjjX0Readers can determine the writer and reply back.rjrj}rj(jjjjjjubaubaubj{)rj}rj(jX>Receiving a message is deterministic when the timeout is zero.rjjjvjjjijjj}rj(j]j]j]j]j]ujNjhj]rjj)rj}rj(jjjjjjjjijjj}rj(j]j]j]j]j]ujK)j]rjjX>Receiving a message is deterministic when the timeout is zero.rjrj}rj(jjjjjjubaubaubj{)rj}rj(jX)Messages can reside on any message queue.rjjjvjjjijjj}rj(j]j]j]j]j]ujNjhj]rjj)rj}rj(jjjjjjjjijjj}rj(j]j]j]j]j]ujK*j]rjjX)Messages can reside on any message queue.rjrj}rj(jjjjjjubaubaubj{)rj}rj(jX(Supports zero-copy transfers (BIOS only)rjjjvjjjijjj}rj(j]j]j]j]j]ujNjhj]rjj)rj}rj(jjjjjjjjijjj}rj(j]j]j]j]j]ujK+j]rjjX(Supports zero-copy transfers (BIOS only)rjrj}rj(jjjjjjubaubaubj{)rj}rj(jX:Messages can be sent and received from any type of thread.rjjjvjjjijjj}rj(j]j]j]j]j]ujNjhj]rjj)rj}rj(jjjjjjjjijjj}rj(j]j]j]j]j]ujK,j]rjjX:Messages can be sent and received from any type of thread.rjrj}rj(jjjjjjubaubaubj{)rj}rj(jXFThe notification mechanism is specified by the application (BIOS only)rjjjvjjjijjj}rj(j]j]j]j]j]ujNjhj]rjj)rj}rj(jjjjjjjjijjj}rj(j]j]j]j]j]ujK-j]rjjXFThe notification mechanism is specified by the application (BIOS only)rjrj}rj(jjjjjjubaubaubj{)rj}rj(jXAllows QoS (quality of service) on message buffer pools. For example, using specific buffer pools for specific message queues. (BIOS only) jjvjjjijjj}rj(j]j]j]j]j]ujNjhj]rjj)rj}rj(jXAllows QoS (quality of service) on message buffer pools. For example, using specific buffer pools for specific message queues. (BIOS only)rjjjjjjijjj}rj(j]j]j]j]j]ujK.j]rjjXAllows QoS (quality of service) on message buffer pools. For example, using specific buffer pools for specific message queues. (BIOS only)rjrj}rj(jjjjjjubaubaubeubj)rj}rj(jX8Messages are sent and received via a message queue. A reader is a thread that gets (reads) messages from a message queue. A writer is a thread that puts (writes) a message to a message queue. Each message queue has one reader and can have many writers. A thread may read from or write to multiple message queues.rjjjijjijjj}rj(j]j]j]j]j]ujK0jhj]rjjX8Messages are sent and received via a message queue. A reader is a thread that gets (reads) messages from a message queue. A writer is a thread that puts (writes) a message to a message queue. Each message queue has one reader and can have many writers. A thread may read from or write to multiple message queues.rjrj}rj(jjjjjjubaubjt)rj}rj(jUjjijjijjwj}rj(jyX-j]j]j]j]j]ujK5jhj]rj(j{)rj}rj(jXu**Reader.** The single reader thread calls MessageQ_create(), MessageQ_get(), MessageQ_free(), and MessageQ_delete().rjjjjjjijjj}rj(j]j]j]j]j]ujNjhj]rjj)rj}rj(jjjjjjjjijjj}rj(j]j]j]j]j]ujK5j]rj(j)rj}rj(jX **Reader.**j}rj(j]j]j]j]j]ujjjj]rjjXReader.rjrk}rk(jUjjjubajjubjXj The single reader thread calls MessageQ_create(), MessageQ_get(), MessageQ_free(), and MessageQ_delete().rkrk}rk(jXj The single reader thread calls MessageQ_create(), MessageQ_get(), MessageQ_free(), and MessageQ_delete().jjjubeubaubj{)rk}rk(jXi**Writer.** Writer threads call MessageQ_open(), MessageQ_alloc(), MessageQ_put(), and MessageQ_close(). jjjjjijjj}rk(j]j]j]j]j]ujNjhj]rkj)r k}r k(jXh**Writer.** Writer threads call MessageQ_open(), MessageQ_alloc(), MessageQ_put(), and MessageQ_close().jjkjjijjj}r k(j]j]j]j]j]ujK6j]r k(j)r k}rk(jX **Writer.**j}rk(j]j]j]j]j]ujj kj]rkjXWriter.rkrk}rk(jUjj kubajjubjX] Writer threads call MessageQ_open(), MessageQ_alloc(), MessageQ_put(), and MessageQ_close().rkrk}rk(jX] Writer threads call MessageQ_open(), MessageQ_alloc(), MessageQ_put(), and MessageQ_close().jj kubeubaubeubj)rk}rk(jXgThe following figure shows the flow in which applications typically use the main runtime MessageQ APIs:rkjjijjijjj}rk(j]j]j]j]j]ujK8jhj]rkjXgThe following figure shows the flow in which applications typically use the main runtime MessageQ APIs:rkrk}rk(jjkjjkubaubjR)rk}r k(jX).. Image:: ../images/IpcUG_ipc_2_3_1.png jjijjijjZj}r!k(UuriX"rtos/../images/IpcUG_ipc_2_3_1.pngr"kj]j]j]j]jX}r#kU*j"ksj]ujK;jhj]ubj)r$k}r%k(jXConceptually, the reader thread creates and owns the message queue. Writer threads then open a created message queue to get access to them.r&kjjijjijjj}r'k(j]j]j]j]j]ujKk(j]j]j]j]j]ujK@jhj]r?kjX}On BIOS-based systems, you can configure a number of module-wide properties for MessageQ in your XDCtools configuration file.r@krAk}rBk(jj=kjj;kubaubj)rCk}rDk(jX|msgCfg_Img2| A snapshot of the MessageQ module configuration documentation is available `online `_.jj,kjjijjj}rEk(j]j]j]j]j]ujKBjhj]rFk(j)rGk}rHk(jjijjCkjNjjj}rIk(Urefurijij]j]j]j]j]ujNjhj]rJkjR)rKk}rLk(jjijjGkjNjjZj}rMk(UuriXrtos/../images/Book_cfg.pngrNkj]j]j]j]jX}rOkU*jNksj]UaltjiujNj]ubaubjXL A snapshot of the MessageQ module configuration documentation is available rPkrQk}rRk(jXL A snapshot of the MessageQ module configuration documentation is available jjCkubj)rSk}rTk(jXt`online `_j}rUk(UnamejijXhhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlrVkj]j]j]j]j]ujjCkj]rWkjXonlinerXkrYk}rZk(jUjjSkubajjubj)r[k}r\k(jXk jKjjCkjj j}r]k(UrefurijVkj]r^kUid1r_kaj]j]r`kjiaj]j]uj]ubjX.rak}rbk(jX.jjCkubeubj)rck}rdk(jXHTo configure the MessageQ module, you must enable the module as follows:rekjj,kjjijjj}rfk(j]j]j]j]j]ujKEjhj]rgkjXHTo configure the MessageQ module, you must enable the module as follows:rhkrik}rjk(jjekjjckubaubj)rkk}rlk(jX4var MessageQ = xdc.useModule('ti.sdo.ipc.MessageQ');jj,kjjijjj}rmk(j@jAj]j]j]j]j]ujM\jhj]rnkjX4var MessageQ = xdc.useModule('ti.sdo.ipc.MessageQ');rokrpk}rqk(jUjjkkubaubj)rrk}rsk(jXqSome example Module-wide configuration properties you can set follow; refer to the IPC documentation for details.rtkjj,kjjijjj}ruk(j]j]j]j]j]ujKKjhj]rvkjXqSome example Module-wide configuration properties you can set follow; refer to the IPC documentation for details.rwkrxk}ryk(jjtkjjrkubaubj)rzk}r{k(jX// Maximum length of MessageQ names MessageQ.maxNameLen = 32; // Max number of MessageQs that can be dynamically created MessageQ.maxRuntimeEntries = 10;jj,kjjijjj}r|k(j@jAj]j]j]j]j]ujMbjhj]r}kjX// Maximum length of MessageQ names MessageQ.maxNameLen = 32; // Max number of MessageQs that can be dynamically created MessageQ.maxRuntimeEntries = 10;r~krk}rk(jUjjzkubaubeubj)rk}rk(jUjjijjijjj}rk(j]j]j]j]rkUcreating-a-messageq-objectrkaj]rkjaujKVjhj]rk(j)rk}rk(jXCreating a MessageQ Objectrkjjkjjijjj}rk(j]j]j]j]j]ujKVjhj]rkjXCreating a MessageQ Objectrkrk}rk(jjkjjkubaubj)rk}rk(jXYou can create message queues dynamically. Static creation is not supported. A MessageQ object is not a shared resource. That is, it resides on the processor, within the process, that creates it.rkjjkjjijjj}rk(j]j]j]j]j]ujKWjhj]rkjXYou can create message queues dynamically. Static creation is not supported. A MessageQ object is not a shared resource. That is, it resides on the processor, within the process, that creates it.rkrk}rk(jjkjjkubaubj)rk}rk(jXThe reader thread creates a message queue. To create a MessageQ object dynamically, use the MessageQ_create() C API, which has the following syntax:rkjjkjjijjj}rk(j]j]j]j]j]ujKZjhj]rkjXThe reader thread creates a message queue. To create a MessageQ object dynamically, use the MessageQ_create() C API, which has the following syntax:rkrk}rk(jjkjjkubaubj)rk}rk(jXFMessageQ_Handle MessageQ_create(String name, MessageQ_Params *params);jjkjjijjj}rk(j@jAj]j]j]j]j]ujMrjhj]rkjXFMessageQ_Handle MessageQ_create(String name, MessageQ_Params *params);rkrk}rk(jUjjkubaubj)rk}rk(jX?When you create a queue, you specify a name string. This name will be needed by the MessageQ_open() function, which is called by threads on the same or remote processors that want to send messages to the created message queue. While the name is not required (that is, it can be NULL), an unnamed queue cannot be opened.rkjjkjjijjj}rk(j]j]j]j]j]ujKajhj]rkjX?When you create a queue, you specify a name string. This name will be needed by the MessageQ_open() function, which is called by threads on the same or remote processors that want to send messages to the created message queue. While the name is not required (that is, it can be NULL), an unnamed queue cannot be opened.rkrk}rk(jjkjjkubaubj)rk}rk(jXTAn ISync handle is associated with the message queue via the synchronizer parameter.rkjjkjjijjj}rk(j]j]j]j]j]ujKejhj]rkjXTAn ISync handle is associated with the message queue via the synchronizer parameter.rkrk}rk(jjkjjkubaubj)rk}rk(jX`If the call is successful, the MessageQ_Handle is returned. If the call fails, NULL is returned.rkjjkjjijjj}rk(j]j]j]j]j]ujKgjhj]rkjX`If the call is successful, the MessageQ_Handle is returned. If the call fails, NULL is returned.rkrk}rk(jjkjjkubaubj)rk}rk(jXYou initialize the params struct by using the MessageQ_Params_init() function, which initializes the params structure with the default values. A NULL value for params can be passed into the create call, which results in the defaults being used. The default synchronizer is SyncSem.rkjjkjjijjj}rk(j]j]j]j]j]ujKijhj]rkjXYou initialize the params struct by using the MessageQ_Params_init() function, which initializes the params structure with the default values. A NULL value for params can be passed into the create call, which results in the defaults being used. The default synchronizer is SyncSem.rkrk}rk(jjkjjkubaubj)rk}rk(jXOThe following code creates a MessageQ object using SyncSem as the synchronizer.rkjjkjjijjj}rk(j]j]j]j]j]ujKljhj]rkjXOThe following code creates a MessageQ object using SyncSem as the synchronizer.rkrk}rk(jjkjjkubaubj)rk}rk(jX<MessageQ_Handle messageQ; MessageQ_Params messageQParams; SyncSem_Handle syncSemHandle; ... syncSemHandle = SyncSem_create(NULL, NULL); MessageQ_Params_init(&messageQParams); messageQParams.synchronizer = SyncSem_Handle_upCast(syncSemHandle); messageQ = MessageQ_create(CORE0_MESSAGEQNAME, &messageQParams);jjkjjijjj}rk(j@jAj]j]j]j]j]ujMjhj]rkjX<MessageQ_Handle messageQ; MessageQ_Params messageQParams; SyncSem_Handle syncSemHandle; ... syncSemHandle = SyncSem_create(NULL, NULL); MessageQ_Params_init(&messageQParams); messageQParams.synchronizer = SyncSem_Handle_upCast(syncSemHandle); messageQ = MessageQ_create(CORE0_MESSAGEQNAME, &messageQParams);rkrk}rk(jUjjkubaubj)rk}rk(jXcIn this example, the CORE0_MESSAGEQNAME constant may be defined in header shared by multiple cores.rkjjkjjijjj}rk(j]j]j]j]j]ujK{jhj]rkjXcIn this example, the CORE0_MESSAGEQNAME constant may be defined in header shared by multiple cores.rkrk}rk(jjkjjkubaubj)rk}rk(jX|msgRun_Img2| A snapshot of the MessageQ module run-time API documentation is available `online `_.jjkjjijjj}rk(j]j]j]j]j]ujK}jhj]rk(j)rk}rk(jjijjkjNjjj}rk(Urefurijij]j]j]j]j]ujNjhj]rkjR)rk}rk(jjijjkjNjjZj}rk(UuriXrtos/../images/Book_run.pngrkj]j]j]j]jX}rkU*jksj]UaltjiujNj]ubaubjXK A snapshot of the MessageQ module run-time API documentation is available rkrk}rk(jXK A snapshot of the MessageQ module run-time API documentation is available jjkubj)rk}rk(jX|`online `_j}rk(UnameXonlinerkjXphttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_message_q_8h.htmlrkj]j]j]j]j]ujjkj]rkjXonlinerkrk}rk(jUjjkubajjubj)rk}rk(jXs jKjjkjj j}rk(Urefurijkj]rkUid2rkaj]j]rkjkaj]j]uj]ubjX.rk}rk(jX.jjkubeubeubj)rk}rl(jUjjijjijjj}rl(j]j]j]j]rlUopening-a-message-queuerlaj]rlhWaujKjhj]rl(j)rl}rl(jXOpening a Message Queuerljjkjjijjj}r l(j]j]j]j]j]ujKjhj]r ljXOpening a Message Queuer lr l}r l(jjljjlubaubj)rl}rl(jXWriter threads open a created message queue to get access to them. In order to obtain a handle to a message queue that has been created, a writer thread must call MessageQ_open(), which has the following syntax.rljjkjjijjj}rl(j]j]j]j]j]ujKjhj]rljXWriter threads open a created message queue to get access to them. In order to obtain a handle to a message queue that has been created, a writer thread must call MessageQ_open(), which has the following syntax.rlrl}rl(jjljjlubaubj)rl}rl(jX:Int MessageQ_open(String name, MessageQ_QueueId *queueId);jjkjjijjj}rl(j@jAj]j]j]j]j]ujMjhj]rljX:Int MessageQ_open(String name, MessageQ_QueueId *queueId);rlrl}rl(jUjjlubaubj)rl}rl(jXThis function expects a name, which must match with the name of the created object. Internally MessageQ calls NameServer_get() to find the 32-bit queueId associated with the created message queue. NameServer looks both locally and remotely.rljjkjjijjj}r l(j]j]j]j]j]ujKjhj]r!ljXThis function expects a name, which must match with the name of the created object. Internally MessageQ calls NameServer_get() to find the 32-bit queueId associated with the created message queue. NameServer looks both locally and remotely.r"lr#l}r$l(jjljjlubaubj)r%l}r&l(jXIf no matching name is found on any processor, MessageQ_open() returns MessageQ_E_NOTFOUND. If the open is successful, the Queue ID is filled in and MessageQ_S_SUCCESS is returned.r'ljjkjjijjj}r(l(j]j]j]j]j]ujKjhj]r)ljXIf no matching name is found on any processor, MessageQ_open() returns MessageQ_E_NOTFOUND. If the open is successful, the Queue ID is filled in and MessageQ_S_SUCCESS is returned.r*lr+l}r,l(jj'ljj%lubaubj)r-l}r.l(jXFThe following code opens the MessageQ object created by the processor.r/ljjkjjijjj}r0l(j]j]j]j]j]ujKjhj]r1ljXFThe following code opens the MessageQ object created by the processor.r2lr3l}r4l(jj/ljj-lubaubj)r5l}r6l(jXMessageQ_QueueId remoteQueueId; Int status; ... /* Open the remote message queue. Spin until it is ready. */ do { status = MessageQ_open(CORE0_MESSAGEQNAME, &remoteQueueId); } while (status < 0);jjkjjijjj}r7l(j@jAj]j]j]j]j]ujMjhj]r8ljXMessageQ_QueueId remoteQueueId; Int status; ... /* Open the remote message queue. Spin until it is ready. */ do { status = MessageQ_open(CORE0_MESSAGEQNAME, &remoteQueueId); } while (status < 0);r9lr:l}r;l(jUjj5lubaubeubj)rl(j]j]j]j]r?lUallocating-a-messager@laj]rAlhaujKjhj]rBl(j)rCl}rDl(jXAllocating a MessagerEljjmr?m}r@m(jj;mjj9mubaubj)rAm}rBm(jX\There can be multiple senders to a single message queue. MessageQ handles the thread safety.rCmjjljjijjj}rDm(j]j]j]j]j]ujMjhj]rEmjX\There can be multiple senders to a single message queue. MessageQ handles the thread safety.rFmrGm}rHm(jjCmjjAmubaubj)rIm}rJm(jXBefore you send a message, you can use the MessageQ_setMsgId() function to assign a numeric value to the message that can be checked by the receiving thread.rKmjjljjijjj}rLm(j]j]j]j]j]ujM jhj]rMmjXBefore you send a message, you can use the MessageQ_setMsgId() function to assign a numeric value to the message that can be checked by the receiving thread.rNmrOm}rPm(jjKmjjImubaubj)rQm}rRm(jXY/* Increment...the remote side will check this */ msgId++; MessageQ_setMsgId(msg, msgId);jjljjijjj}rSm(j@jAj]j]j]j]j]ujM7jhj]rTmjXY/* Increment...the remote side will check this */ msgId++; MessageQ_setMsgId(msg, msgId);rUmrVm}rWm(jUjjQmubaubj)rXm}rYm(jXQYou can use the MessageQ_setMsgPri() function to set the priority of the message.rZmjjljjijjj}r[m(j]j]j]j]j]ujM(jhj]r\mjXQYou can use the MessageQ_setMsgPri() function to set the priority of the message.r]mr^m}r_m(jjZmjjXmubaubeubj)r`m}ram(jUjjijjijjj}rbm(j]j]j]j]rcmUreceiving-a-messagerdmaj]remjsaujM+jhj]rfm(j)rgm}rhm(jXReceiving a Messagerimjj`mjjijjj}rjm(j]j]j]j]j]ujM+jhj]rkmjXReceiving a Messagerlmrmm}rnm(jjimjjgmubaubj)rom}rpm(jXCTo receive a message, a reader thread calls the MessageQ_get() API.rqmjj`mjjijjj}rrm(j]j]j]j]j]ujM,jhj]rsmjXCTo receive a message, a reader thread calls the MessageQ_get() API.rtmrum}rvm(jjqmjjomubaubj)rwm}rxm(jXyInt MessageQ_get(MessageQ_Handle handle, MessageQ_Msg *msg, UInt timeout)jj`mjjijjj}rym(j@jAj]j]j]j]j]ujMCjhj]rzmjXyInt MessageQ_get(MessageQ_Handle handle, MessageQ_Msg *msg, UInt timeout)r{mr|m}r}m(jUjjwmubaubj)r~m}rm(jX{If a message is present, it returned by this function. In this case the ISync's wait() function is not called. For example:rmjj`mjjijjj}rm(j]j]j]j]j]ujM4jhj]rmjX{If a message is present, it returned by this function. In this case the ISync's wait() function is not called. For example:rmrm}rm(jjmjj~mubaubj)rm}rm(jX/* Get a message */ status = MessageQ_get(messageQ, &msg, MessageQ_FOREVER); if (status < 0) { System_abort("Should not happen; timeout is forever\n"); }jj`mjjijjj}rm(j@jAj]j]j]j]j]ujMLjhj]rmjX/* Get a message */ status = MessageQ_get(messageQ, &msg, MessageQ_FOREVER); if (status < 0) { System_abort("Should not happen; timeout is forever\n"); }rmrm}rm(jUjjmubaubj)rm}rm(jXIf no message is present and no error occurs, this function blocks while waiting for the timeout period for the message to arrive. If the timeout period expires, MessageQ_E_FAIL is returned. If an error occurs, the msg argument will be unchanged.rmjj`mjjijjj}rm(j]j]j]j]j]ujM?jhj]rmjXIf no message is present and no error occurs, this function blocks while waiting for the timeout period for the message to arrive. If the timeout period expires, MessageQ_E_FAIL is returned. If an error occurs, the msg argument will be unchanged.rmrm}rm(jjmjjmubaubj)rm}rm(jXwAfter receiving a message, you can use the following APIs to get information about the message from the message header:rmjj`mjjijjj}rm(j]j]j]j]j]ujMBjhj]rmjXwAfter receiving a message, you can use the following APIs to get information about the message from the message header:rmrm}rm(jjmjjmubaubjt)rm}rm(jUjj`mjjijjwj}rm(jyX-j]j]j]j]j]ujMDjhj]rmj{)rm}rm(jXOMessageQ_getMsgId() gets the ID value set by MessageQ_setMsgId(). For example: jjmjjijjj}rm(j]j]j]j]j]ujNjhj]rmj)rm}rm(jXNMessageQ_getMsgId() gets the ID value set by MessageQ_setMsgId(). For example:rmjjmjjijjj}rm(j]j]j]j]j]ujMDj]rmjXNMessageQ_getMsgId() gets the ID value set by MessageQ_setMsgId(). For example:rmrm}rm(jjmjjmubaubaubaubj)rm}rm(jX/* Get the id and increment it to send back */ msgId = MessageQ_getMsgId(msg); msgId += NUMCLIENTS; MessageQ_setMsgId(msg, msgId);jj`mjjijjj}rm(j@jAj]j]j]j]j]ujM[jhj]rmjX/* Get the id and increment it to send back */ msgId = MessageQ_getMsgId(msg); msgId += NUMCLIENTS; MessageQ_setMsgId(msg, msgId);rmrm}rm(jUjjmubaubjt)rm}rm(jUjj`mjjijjwj}rm(jyX-j]j]j]j]j]ujMMjhj]rm(j{)rm}rm(jXCMessageQ_getMsgPri() gets the priority set by MessageQ_setMsgPri().rmjjmjjijjj}rm(j]j]j]j]j]ujNjhj]rmj)rm}rm(jjmjjmjjijjj}rm(j]j]j]j]j]ujMMj]rmjXCMessageQ_getMsgPri() gets the priority set by MessageQ_setMsgPri().rmrm}rm(jjmjjmubaubaubj{)rm}rm(jX<MessageQ_getMsgSize() gets the size of the message in bytes.rmjjmjjijjj}rm(j]j]j]j]j]ujNjhj]rmj)rm}rm(jjmjjmjjijjj}rm(j]j]j]j]j]ujMNj]rmjX<MessageQ_getMsgSize() gets the size of the message in bytes.rmrm}rm(jjmjjmubaubaubj{)rm}rm(jXXMessageQ_getReplyQueue() gets the ID of the queue provided by MessageQ_setReplyQueue(). jjmjjijjj}rm(j]j]j]j]j]ujNjhj]rmj)rm}rm(jXWMessageQ_getReplyQueue() gets the ID of the queue provided by MessageQ_setReplyQueue().rmjjmjjijjj}rm(j]j]j]j]j]ujMOj]rmjXWMessageQ_getReplyQueue() gets the ID of the queue provided by MessageQ_setReplyQueue().rmrm}rm(jjmjjmubaubaubeubeubj)rm}rm(jUjjijjijjj}rm(j]j]j]j]rmUdeleting-a-messageq-objectrmaj]rmjaujMRjhj]rm(j)rm}rm(jXDeleting a MessageQ Objectrmjjmjjijjj}rm(j]j]j]j]j]ujMRjhj]rmjXDeleting a MessageQ Objectrmrm}rm(jjmjjmubaubj)rm}rm(jXMessageQ_delete() frees a MessageQ object stored in local memory. If any messages are still on the internal linked lists, they will be freed. The contents of the handle are nulled out by the function to prevent use after deleting.rmjjmjjijjj}rm(j]j]j]j]j]ujMSjhj]rmjXMessageQ_delete() frees a MessageQ object stored in local memory. If any messages are still on the internal linked lists, they will be freed. The contents of the handle are nulled out by the function to prevent use after deleting.rmrm}rm(jjmjjmubaubj)rm}rm(jX.Void MessageQ_delete(MessageQ_Handle *handle);jjmjjijjj}rm(j@jAj]j]j]j]j]ujMkjhj]rmjX.Void MessageQ_delete(MessageQ_Handle *handle);rmrm}rm(jUjjmubaubj)rm}rm(jX5The queue array entry is set to NULL to allow re-use.rmjjmjjijjj}rm(j]j]j]j]j]ujMZjhj]rmjX5The queue array entry is set to NULL to allow re-use.rmrn}rn(jjmjjmubaubj)rn}rn(jXwOnce a message queue is deleted, no messages should be sent to it. A MessageQ_close() is recommended, but not required.rnjjmjjijjj}rn(j]j]j]j]j]ujM\jhj]rnjXwOnce a message queue is deleted, no messages should be sent to it. A MessageQ_close() is recommended, but not required.rnrn}r n(jjnjjnubaubeubj)r n}r n(jUjjijjijjj}r n(j]j]j]j]r nUmessage-prioritiesrnaj]rnhLaujM_jhj]rn(j)rn}rn(jXMessage Prioritiesrnjj njjijjj}rn(j]j]j]j]j]ujM_jhj]rnjXMessage Prioritiesrnrn}rn(jjnjjnubaubj)rn}rn(jX6MessageQ supports three message priorities as follows:rnjj njjijjj}rn(j]j]j]j]j]ujM`jhj]rnjX6MessageQ supports three message priorities as follows:rnrn}r n(jjnjjnubaubjt)r!n}r"n(jUjj njjijjwj}r#n(jyX-j]j]j]j]j]ujMbjhj]r$n(j{)r%n}r&n(jXMessageQ_NORMALPRI = 0r'njj!njjijjj}r(n(j]j]j]j]j]ujNjhj]r)nj)r*n}r+n(jj'njj%njjijjj}r,n(j]j]j]j]j]ujMbj]r-njXMessageQ_NORMALPRI = 0r.nr/n}r0n(jj'njj*nubaubaubj{)r1n}r2n(jXMessageQ_HIGHPRI = 1r3njj!njjijjj}r4n(j]j]j]j]j]ujNjhj]r5nj)r6n}r7n(jj3njj1njjijjj}r8n(j]j]j]j]j]ujMcj]r9njXMessageQ_HIGHPRI = 1r:nr;n}rn(jXMessageQ_URGENTPRI = 3 jj!njjijjj}r?n(j]j]j]j]j]ujNjhj]r@nj)rAn}rBn(jXMessageQ_URGENTPRI = 3rCnjj=njjijjj}rDn(j]j]j]j]j]ujMdj]rEnjXMessageQ_URGENTPRI = 3rFnrGn}rHn(jjCnjjAnubaubaubeubj)rIn}rJn(jXjYou can set the priority level for a message before sending it by using the MessageQ_setMsgPri() function:rKnjj njjijjj}rLn(j]j]j]j]j]ujMfjhj]rMnjXjYou can set the priority level for a message before sending it by using the MessageQ_setMsgPri() function:rNnrOn}rPn(jjKnjjInubaubj)rQn}rRn(jXdVoid MessageQ_setMsgPri(MessageQ_Msg msg, MessageQ_Priority priority)jj njjijjj}rSn(j@jAj]j]j]j]j]ujM}jhj]rTnjXdVoid MessageQ_setMsgPri(MessageQ_Msg msg, MessageQ_Priority priority)rUnrVn}rWn(jUjjQnubaubj)rXn}rYn(jXAInternally a MessageQ object maintains two linked lists: normal and high-priority. A normal priority message is placed onto the "normal" linked list in FIFO manner. A high priority message is placed onto the "high-priority" linked list in FIFO manner. An urgent message is placed at the beginning of the high linked list.rZnjj njjijjj}r[n(j]j]j]j]j]ujMmjhj]r\njXAInternally a MessageQ object maintains two linked lists: normal and high-priority. A normal priority message is placed onto the "normal" linked list in FIFO manner. A high priority message is placed onto the "high-priority" linked list in FIFO manner. An urgent message is placed at the beginning of the high linked list.r]nr^n}r_n(jjZnjjXnubaubj)r`n}ran(jXtSince multiple urgent messages may be sent before a message is read, the order of urgent messages is not guaranteed.rbnjj njjijjj}rcn(j]j]j]j]j]ujNjhj]rdnj)ren}rfn(jjbnjj`njjijjj}rgn(j]j]j]j]j]ujMtj]rhnjXtSince multiple urgent messages may be sent before a message is read, the order of urgent messages is not guaranteed.rinrjn}rkn(jjbnjjenubaubaubj)rln}rmn(jXWhen getting a message, the reader checks the high priority linked list first. If a message is present on that list, it is returned. If not, the normal priority linked list is checked. If a message is present there, it is returned. Otherwise the synchronizer's wait function is called.rnnjj njjijjj}ron(j]j]j]j]j]ujMvjhj]rpnjXWhen getting a message, the reader checks the high priority linked list first. If a message is present on that list, it is returned. If not, the normal priority linked list is checked. If a message is present there, it is returned. Otherwise the synchronizer's wait function is called.rqnrrn}rsn(jjnnjjlnubaubj)rtn}run(jXThe MessageQ priority feature is enabled by the selecting different MessageQ transports. Some MessageQ implementations (e.g. Linux) may not support multiple transports and therefore may not support this feature.jj njjijjj}rvn(j]j]j]j]j]ujNjhj]rwnj)rxn}ryn(jXThe MessageQ priority feature is enabled by the selecting different MessageQ transports. Some MessageQ implementations (e.g. Linux) may not support multiple transports and therefore may not support this feature.rznjjtnjjijjj}r{n(j]j]j]j]j]ujM{j]r|njXThe MessageQ priority feature is enabled by the selecting different MessageQ transports. Some MessageQ implementations (e.g. Linux) may not support multiple transports and therefore may not support this feature.r}nr~n}rn(jjznjjxnubaubaubeubj)rn}rn(jUjjijjijjj}rn(j]j]j]j]rnU thread-synchronization-bios-onlyrnaj]rnh3aujMjhj]rn(j)rn}rn(jX"Thread Synchronization (BIOS only)rnjjnjjijjj}rn(j]j]j]j]j]ujMjhj]rnjX"Thread Synchronization (BIOS only)rnrn}rn(jjnjjnubaubj)rn}rn(jXMessageQ supports reads and writes of different thread models. It can work with threading models that include SYS/BIOS's Hwi, Swi, and Task threads.rnjjnjjijjj}rn(j]j]j]j]j]ujMjhj]rnjXMessageQ supports reads and writes of different thread models. It can work with threading models that include SYS/BIOS's Hwi, Swi, and Task threads.rnrn}rn(jjnjjnubaubj)rn}rn(jX5This flexibility is accomplished by using an implementation of the xdc.runtime.knl.ISync interface. The creator of the message queue must also create an object of the desired ISync implementation and assign that object as the "synchronizer" of the MessageQ. Each message queue has its own synchronizer object.rnjjnjjijjj}rn(j]j]j]j]j]ujMjhj]rnjX5This flexibility is accomplished by using an implementation of the xdc.runtime.knl.ISync interface. The creator of the message queue must also create an object of the desired ISync implementation and assign that object as the "synchronizer" of the MessageQ. Each message queue has its own synchronizer object.rnrn}rn(jjnjjnubaubj)rn}rn(jXsAn ISync object has two main functions: signal() and wait(). Whenever MessageQ_put() is called, the signal() function of the ISync implementation is called. If MessageQ_get() is called when there are no messages on the queue, the wait() function of the ISync implementation is called. The timeout passed into the MessageQ_get() is directly passed to the ISync wait() API.rnjjnjjijjj}rn(j]j]j]j]j]ujMjhj]rnjXsAn ISync object has two main functions: signal() and wait(). Whenever MessageQ_put() is called, the signal() function of the ISync implementation is called. If MessageQ_get() is called when there are no messages on the queue, the wait() function of the ISync implementation is called. The timeout passed into the MessageQ_get() is directly passed to the ISync wait() API.rnrn}rn(jjnjjnubaubj)rn}rn(jXSince ISync implementations must be binary, the reader thread must drain the MessageQ of all messages before waiting for another signal.rnjjnjjijjj}rn(j]j]j]j]j]ujNjhj]rnj)rn}rn(jjnjjnjjijjj}rn(j]j]j]j]j]ujMj]rnjXSince ISync implementations must be binary, the reader thread must drain the MessageQ of all messages before waiting for another signal.rnrn}rn(jjnjjnubaubaubj)rn}rn(jXpFor example, if the reader is a SYS/BIOS Swi, the instance could be a SyncSwi. When a MessageQ_put() is called, the Swi_post() API would be called. The Swi would run and it must call MessageQ_get() until no messages are returned. If the Swi does not get all the messages, the Swi will not run again, or at least will not run until a new message is placed on the queue.rnjjnjjijjj}rn(j]j]j]j]j]ujMjhj]rnjXpFor example, if the reader is a SYS/BIOS Swi, the instance could be a SyncSwi. When a MessageQ_put() is called, the Swi_post() API would be called. The Swi would run and it must call MessageQ_get() until no messages are returned. If the Swi does not get all the messages, the Swi will not run again, or at least will not run until a new message is placed on the queue.rnrn}rn(jjnjjnubaubj)rn}rn(jXThe calls to ISync functions occurs directly in MessageQ_put() when the call occurs on the same processor where the queue was created. In the remote case, the transport calls MessageQ_put(), which is then a local put, and the signal function is called.rnjjnjjijjj}rn(j]j]j]j]j]ujMjhj]rnjXThe calls to ISync functions occurs directly in MessageQ_put() when the call occurs on the same processor where the queue was created. In the remote case, the transport calls MessageQ_put(), which is then a local put, and the signal function is called.rnrn}rn(jjnjjnubaubj)rn}rn(jXJThe following are ISync implementations provided by XDCtools and SYS/BIOS:rnjjnjjijjj}rn(j]j]j]j]j]ujMjhj]rnjXJThe following are ISync implementations provided by XDCtools and SYS/BIOS:rnrn}rn(jjnjjnubaubjt)rn}rn(jUjjnjjijjwj}rn(jyX-j]j]j]j]j]ujMjhj]rn(j{)rn}rn(jX}**xdc.runtime.knl.SyncNull.** The signal() and wait() functions do nothing. Basically this implementation allows for polling.rnjjnjjijjj}rn(j]j]j]j]j]ujNjhj]rnj)rn}rn(jjnjjnjjijjj}rn(j]j]j]j]j]ujMj]rn(j)rn}rn(jX**xdc.runtime.knl.SyncNull.**j}rn(j]j]j]j]j]ujjnj]rnjXxdc.runtime.knl.SyncNull.rnrn}rn(jUjjnubajjubjX` The signal() and wait() functions do nothing. Basically this implementation allows for polling.rnrn}rn(jX` The signal() and wait() functions do nothing. Basically this implementation allows for polling.jjnubeubaubj{)rn}rn(jX**xdc.runtime.knl.SyncSemThread.** An implementation built using the xdc.runtime.knl.Semaphore module, which is a binary semaphore.rnjjnjjijjj}rn(j]j]j]j]j]ujNjhj]rnj)rn}rn(jjnjjnjjijjj}rn(j]j]j]j]j]ujMj]rn(j)rn}rn(jX"**xdc.runtime.knl.SyncSemThread.**j}rn(j]j]j]j]j]ujjnj]rnjXxdc.runtime.knl.SyncSemThread.rnrn}rn(jUjjnubajjubjXa An implementation built using the xdc.runtime.knl.Semaphore module, which is a binary semaphore.rnrn}rn(jXa An implementation built using the xdc.runtime.knl.Semaphore module, which is a binary semaphore.jjnubeubaubj{)rn}rn(jXz**xdc.runtime.knl.SyncGeneric.xdc.** This implementation allows you to use custom signal() and wait() functions as needed.rnjjnjjijjj}rn(j]j]j]j]j]ujNjhj]rnj)rn}rn(jjnjjnjjijjj}rn(j]j]j]j]j]ujMj]rn(j)rn}rn(jX$**xdc.runtime.knl.SyncGeneric.xdc.**j}ro(j]j]j]j]j]ujjnj]rojX xdc.runtime.knl.SyncGeneric.xdc.roro}ro(jUjjnubajjubjXV This implementation allows you to use custom signal() and wait() functions as needed.roro}ro(jXV This implementation allows you to use custom signal() and wait() functions as needed.jjnubeubaubj{)ro}r o(jX**ti.sysbios.syncs.SyncSem.** An implementation built using the ti.sysbios.ipc.Semaphore module. The signal() function runs a Semaphore_post(). The wait() function runs a Semaphore_pend().r ojjnjjijjj}r o(j]j]j]j]j]ujNjhj]r oj)r o}ro(jj ojjojjijjj}ro(j]j]j]j]j]ujMj]ro(j)ro}ro(jX**ti.sysbios.syncs.SyncSem.**j}ro(j]j]j]j]j]ujj oj]rojXti.sysbios.syncs.SyncSem.roro}ro(jUjjoubajjubjX An implementation built using the ti.sysbios.ipc.Semaphore module. The signal() function runs a Semaphore_post(). The wait() function runs a Semaphore_pend().roro}ro(jX An implementation built using the ti.sysbios.ipc.Semaphore module. The signal() function runs a Semaphore_post(). The wait() function runs a Semaphore_pend().jj oubeubaubj{)ro}ro(jX**ti.sysbios.syncs.SyncSwi.** An implementation built using the ti.sysbios.knl.Swi module. The signal() function runs a Swi_post(). The wait() function does nothing and returns FALSE if the timeout elapses.rojjnjjijjj}ro(j]j]j]j]j]ujNjhj]roj)r o}r!o(jjojjojjijjj}r"o(j]j]j]j]j]ujMj]r#o(j)r$o}r%o(jX**ti.sysbios.syncs.SyncSwi.**j}r&o(j]j]j]j]j]ujj oj]r'ojXti.sysbios.syncs.SyncSwi.r(or)o}r*o(jUjj$oubajjubjX An implementation built using the ti.sysbios.knl.Swi module. The signal() function runs a Swi_post(). The wait() function does nothing and returns FALSE if the timeout elapses.r+or,o}r-o(jX An implementation built using the ti.sysbios.knl.Swi module. The signal() function runs a Swi_post(). The wait() function does nothing and returns FALSE if the timeout elapses.jj oubeubaubj{)r.o}r/o(jX **ti.sysbios.syncs.SyncEvent.** An implementation built using the ti.sysbios.ipc.Event module. The signal() function runs an Event_post(). The wait() function does nothing and returns FALSE if the timeout elapses. This implementation allows waiting on multiple events. jjnjjijjj}r0o(j]j]j]j]j]ujNjhj]r1oj)r2o}r3o(jX **ti.sysbios.syncs.SyncEvent.** An implementation built using the ti.sysbios.ipc.Event module. The signal() function runs an Event_post(). The wait() function does nothing and returns FALSE if the timeout elapses. This implementation allows waiting on multiple events.jj.ojjijjj}r4o(j]j]j]j]j]ujMj]r5o(j)r6o}r7o(jX**ti.sysbios.syncs.SyncEvent.**j}r8o(j]j]j]j]j]ujj2oj]r9ojXti.sysbios.syncs.SyncEvent.r:or;o}ro}r?o(jX An implementation built using the ti.sysbios.ipc.Event module. The signal() function runs an Event_post(). The wait() function does nothing and returns FALSE if the timeout elapses. This implementation allows waiting on multiple events.jj2oubeubaubeubj)r@o}rAo(jXThe following code from the "message" example creates a SyncSem instance and assigns it to the synchronizer field in the MessageQ_Params structure before creating the MessageQ instance:rBojjnjjijjj}rCo(j]j]j]j]j]ujMjhj]rDojXThe following code from the "message" example creates a SyncSem instance and assigns it to the synchronizer field in the MessageQ_Params structure before creating the MessageQ instance:rEorFo}rGo(jjBojj@oubaubj)rHo}rIo(jX#include ... MessageQ_Params messageQParams; SyncSem_Handle syncSemHandle; /* Create a message queue using SyncSem as synchronizer */ syncSemHandle = SyncSem_create(NULL, NULL); MessageQ_Params_init(&messageQParams); messageQParams.synchronizer = SyncSem_Handle_upCast(syncSemHandle); messageQ = MessageQ_create(CORE1_MESSAGEQNAME, &messageQParams, NULL);jjnjjijjj}rJo(j@jAj]j]j]j]j]ujMjhj]rKojX#include ... MessageQ_Params messageQParams; SyncSem_Handle syncSemHandle; /* Create a message queue using SyncSem as synchronizer */ syncSemHandle = SyncSem_create(NULL, NULL); MessageQ_Params_init(&messageQParams); messageQParams.synchronizer = SyncSem_Handle_upCast(syncSemHandle); messageQ = MessageQ_create(CORE1_MESSAGEQNAME, &messageQParams, NULL);rLorMo}rNo(jUjjHoubaubeubj)rOo}rPo(jUjjijjijjj}rQo(j]j]j]j]rRoU replyqueuerSoaj]rTohaujMjhj]rUo(j)rVo}rWo(jX ReplyQueuerXojjOojjijjj}rYo(j]j]j]j]j]ujMjhj]rZojX ReplyQueuer[or\o}r]o(jjXojjVoubaubj)r^o}r_o(jX(For some applications, doing a MessageQ_open() on a queue is not realistic. For example, a server may not want to open all the clients' queues for sending responses. To support this use case, the message sender can embed a reply queueId in the message using the MessageQ_setReplyQueue() function.r`ojjOojjijjj}rao(j]j]j]j]j]ujMjhj]rbojX(For some applications, doing a MessageQ_open() on a queue is not realistic. For example, a server may not want to open all the clients' queues for sending responses. To support this use case, the message sender can embed a reply queueId in the message using the MessageQ_setReplyQueue() function.rcordo}reo(jj`ojj^oubaubj)rfo}rgo(jX_Void MessageQ_setReplyQueue(MessageQ_Handle handle, MessageQ_Msg msg)jjOojjijjj}rho(j@jAj]j]j]j]j]ujMjhj]riojX_Void MessageQ_setReplyQueue(MessageQ_Handle handle, MessageQ_Msg msg)rjorko}rlo(jUjjfoubaubj)rmo}rno(jXIThis API stores the message queue's queueId into fields in the MsgHeader.roojjOojjijjj}rpo(j]j]j]j]j]ujMjhj]rqojXIThis API stores the message queue's queueId into fields in the MsgHeader.rrorso}rto(jjoojjmoubaubj)ruo}rvo(jXDThe MessageQ_getReplyQueue() function does the reverse. For example:rwojjOojjijjj}rxo(j]j]j]j]j]ujMjhj]ryojXDThe MessageQ_getReplyQueue() function does the reverse. For example:rzor{o}r|o(jjwojjuoubaubj)r}o}r~o(jXMessageQ_QueueId replyQueue; MessageQ_Msg msg; ... /* Use the embedded reply destination */ replyMessageQ = MessageQ_getReplyQueue(msg); if (replyMessageQ == MessageQ_INVALIDMESSAGEQ) { System_abort("Invalid reply queue\n"); }jjOojjijjj}ro(j@jAj]j]j]j]j]ujMjhj]rojXMessageQ_QueueId replyQueue; MessageQ_Msg msg; ... /* Use the embedded reply destination */ replyMessageQ = MessageQ_getReplyQueue(msg); if (replyMessageQ == MessageQ_INVALIDMESSAGEQ) { System_abort("Invalid reply queue\n"); }roro}ro(jUjj}oubaubj)ro}ro(jX_The MessageQ_QueueId value returned by this function can then be used in a MessageQ_put() call.rojjOojjijjj}ro(j]j]j]j]j]ujMjhj]rojX_The MessageQ_QueueId value returned by this function can then be used in a MessageQ_put() call.roro}ro(jjojjoubaubj)ro}ro(jXQThe queue that is embedded in the message does not have to be the sender's queue.rojjOojjijjj}ro(j]j]j]j]j]ujMjhj]rojXQThe queue that is embedded in the message does not have to be the sender's queue.roro}ro(jjojjoubaubeubj)ro}ro(jUjjijjijjj}ro(j]j]j]j]roU-remote-communication-via-transports-bios-onlyroaj]rohUaujMjhj]ro(j)ro}ro(jX/Remote Communication via Transports (BIOS only)rojjojjijjj}ro(j]j]j]j]j]ujMjhj]rojX/Remote Communication via Transports (BIOS only)roro}ro(jjojjoubaubj)ro}ro(jXvMessageQ is designed to support multiple processors. To allow this, different transports can be plugged into MessageQ.rojjojjijjj}ro(j]j]j]j]j]ujMjhj]rojXvMessageQ is designed to support multiple processors. To allow this, different transports can be plugged into MessageQ.roro}ro(jjojjoubaubj)ro}ro(jXIn a multi-processor system, MessageQ communicates with other processors via ti.sdo.ipc.interfaces.IMessageQTransport instances. There can be up to two IMessageQTransport instances for each processor to which communication is desired. One can be a normal-priority transport and the other for handling high-priority messages. This is done via the priority parameter in the transport create() function. If there is only one register to a remote processor (either normal or high), all messages go via that transport.rojjojjijjj}ro(j]j]j]j]j]ujMjhj]rojXIn a multi-processor system, MessageQ communicates with other processors via ti.sdo.ipc.interfaces.IMessageQTransport instances. There can be up to two IMessageQTransport instances for each processor to which communication is desired. One can be a normal-priority transport and the other for handling high-priority messages. This is done via the priority parameter in the transport create() function. If there is only one register to a remote processor (either normal or high), all messages go via that transport.roro}ro(jjojjoubaubj)ro}ro(jXThere can be different transports on a processor. For example, there may be a shared memory transport to processor A and an sRIO one to processor B.rojjojjijjj}ro(j]j]j]j]j]ujMjhj]rojXThere can be different transports on a processor. For example, there may be a shared memory transport to processor A and an sRIO one to processor B.roro}ro(jjojjoubaubj)ro}ro(jXWhen your application calls Ipc_start(), the default transport instance used by MessageQ is created automatically. Internally, transport instances are responsible for registering themselves with MessageQ via the MessageQ_registerTransport() function.rojjojjijjj}ro(j]j]j]j]j]ujMjhj]rojXWhen your application calls Ipc_start(), the default transport instance used by MessageQ is created automatically. Internally, transport instances are responsible for registering themselves with MessageQ via the MessageQ_registerTransport() function.roro}ro(jjojjoubaubj)ro}ro(jXIPC provides an implementation of the IMessageQTransport interface called ti.sdo.ipc.transports.TransportShm (shared memory). You can write other implementations to meet your needs.rojjojjijjj}ro(j]j]j]j]j]ujMjhj]rojXIPC provides an implementation of the IMessageQTransport interface called ti.sdo.ipc.transports.TransportShm (shared memory). You can write other implementations to meet your needs.roro}ro(jjojjoubaubj)ro}ro(jX When a transport is created via a transport-specific create() call, a remote processor ID (defined via the MultiProc module) is specified. This ID denotes which processor this instance communicates with. Additionally there are configuration properties for the transport--such as the message priority handled--that can be defined in a Params structure. The transport takes these pieces of information and registers itself with MessageQ. MessageQ now knows which transport to call when sending a message to a remote processor.rojjojjijjj}ro(j]j]j]j]j]ujMjhj]rojX When a transport is created via a transport-specific create() call, a remote processor ID (defined via the MultiProc module) is specified. This ID denotes which processor this instance communicates with. Additionally there are configuration properties for the transport--such as the message priority handled--that can be defined in a Params structure. The transport takes these pieces of information and registers itself with MessageQ. MessageQ now knows which transport to call when sending a message to a remote processor.roro}ro(jjojjoubaubj)ro}ro(jXHTrying to send to a processor that has no transport results in an error.rojjojjijjj}ro(j]j]j]j]j]ujMjhj]rojXHTrying to send to a processor that has no transport results in an error.roro}ro(jjojjoubaubj)ro}ro(jUjjojjijjj}ro(j]j]j]j]roU custom-transport-implementationsroaj]roh'aujMjhj]ro(j)ro}ro(jX Custom Transport Implementationsrojjojjijjj}ro(j]j]j]j]j]ujMjhj]rojX Custom Transport Implementationsroro}ro(jjojjoubaubj)ro}ro(jXTransports can register and unregister themselves dynamically. That is, if the transport instance is deleted, it should unregister with MessageQ.rojjojjijjj}ro(j]j]j]j]j]ujMjhj]rojXTransports can register and unregister themselves dynamically. That is, if the transport instance is deleted, it should unregister with MessageQ.roro}ro(jjojjoubaubj)ro}ro(jXWhen receiving a message, transports need to form the MessageQ_QueueId that allows them to call MessageQ_put(). This is accomplished via the MessageQ_getDstQueue() API.rojjojjijjj}ro(j]j]j]j]j]ujMjhj]rojXWhen receiving a message, transports need to form the MessageQ_QueueId that allows them to call MessageQ_put(). This is accomplished via the MessageQ_getDstQueue() API.roro}ro(jjojjoubaubj)ro}ro(jX7MessageQ_QueueId MessageQ_getDstQueue(MessageQ_Msg msg)jjojjijjj}ro(j@jAj]j]j]j]j]ujMjhj]rojX7MessageQ_QueueId MessageQ_getDstQueue(MessageQ_Msg msg)roro}rp(jUjjoubaubeubeubj)rp}rp(jUjKjjijjijjj}rp(j]rpX%sample runtime program flow (dynamic)rpaj]j]j]rpU#sample-runtime-program-flow-dynamicrpaj]ujMjhj]rp(j)r p}r p(jX%Sample Runtime Program Flow (Dynamic)r pjjpjjijjj}r p(j]j]j]j]j]ujMjhj]r pjX%Sample Runtime Program Flow (Dynamic)rprp}rp(jj pjj pubaubj)rp}rp(jX1The following figure shows the typical sequence of events when using a MessageQ. A message queue is created by a Task. An open on the same processor then occurs. Assume there is one message in the system. The opener allocates the message and sends it to the created message queue, which gets and frees it.rpjjpjjijjj}rp(j]j]j]j]j]ujMjhj]rpjX1The following figure shows the typical sequence of events when using a MessageQ. A message queue is created by a Task. An open on the same processor then occurs. Assume there is one message in the system. The opener allocates the message and sends it to the created message queue, which gets and frees it.rprp}rp(jjpjjpubaubjR)rp}rp(jX*.. Image:: ../images/IpcUG_ipc_2_3_2.png jjpjXTinternal padding after source/rtos/PDK_Platform_Software/IPC/MessageQ_Module.rst.incrpjjZj}rp(UuriX"rtos/../images/IpcUG_ipc_2_3_2.pngrpj]j]j]j]jX}rpU*jpsj]ujMjhj]ubeubeubj)rp}r p(jUjjjjjjj}r!p(j]j]j]j]r"pU listmp-moduler#paj]r$phaujK;jhj]r%p(j)r&p}r'p(jX ListMP Moduler(pjjpjjjjj}r)p(j]j]j]j]j]ujK;jhj]r*pjX ListMP Moduler+pr,p}r-p(jj(pjj&pubaubj7)r.p}r/p(jXEhttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/ListMP_Modulejjpjj:X;source/rtos/PDK_Platform_Software/IPC/ListMP_Module.rst.incr0pr1p}r2pbjj>j}r3p(j@jAj]j]j]j]j]ujKjhj]r4pjXEhttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/ListMP_Moduler5pr6p}r7p(jUjj.pubaubj)r8p}r9p(jX.. |lmpCfg_Img1| Image:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.html jjpjj1pjjHj}r:p(j]j]j]j]j]r;pX lmpCfg_Img1rp}r?p(jjpj]jjZubajjubaubj)rIp}rJp(jX.. |lmpRun_Img1| Image:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_list_m_p_8h.html jjpjj1pjjHj}rKp(j]j]j]j]j]rLpX lmpRun_Img1rMpaujKjhj]rNpj)rOp}rPp(jjMpj}rQp(UrefuriXohttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_list_m_p_8h.htmlrRpj]j]j]j]j]ujjIpj]rSpjR)rTp}rUp(jXImage:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_list_m_p_8h.htmlrVpj}rWp(UuriXrtos/../images/Book_run.pngrXpj]j]j]j]jX}rYpU*jXpsj]UaltjMpujjOpj]jjZubajjubaubjc)rZp}r[p(jUjjpjj1pjjfj}r\p(j]j]j]j]j]ujK jhj]r]pji)r^p}r_p(jUjlKjjZpjj1pjjj}r`p(j]j]j]j]j]ujKjhj]ubaubj3)rap}rbp(jUjjpjj1pjj6j}rcp(j]j]j]j]j]ujNjhj]rdpjy )rep}rfp(jUj}rgp(j]j]j]j]j]ujjapj]rhpj~ )rip}rjp(jUj}rkp(j]j]j]j]j]UcolsKujjepj]rlp(j )rmp}rnp(jUj}rop(j]j]j]j]j]UcolwidthKujjipj]jj ubj )rpp}rqp(jUj}rrp(j]j]j]j]j]UcolwidthKujjipj]jj ubj )rsp}rtp(jUj}rup(j]j]j]j]j]ujjipj]rvpj )rwp}rxp(jUj}ryp(j]j]j]j]j]ujjspj]rzpj )r{p}r|p(jUj}r}p(j]UmorecolsKj]j]j]j]ujjwpj]r~pj)rp}rp(jXAPI Reference Linksrpjj{pjj1pjjj}rp(j]j]j]j]j]ujK j]rpjXAPI Reference Linksrprp}rp(jjpjjpubaubajj ubajj ubajj ubj )rp}rp(jUj}rp(j]j]j]j]j]ujjipj]rpj )rp}rp(jUj}rp(j]j]j]j]j]ujjpj]rp(j )rp}rp(jUj}rp(j]j]j]j]j]ujjpj]rpj)rp}rp(jX |lmpCfg_Img1|rpjjpjj1pjjj}rp(j]j]j]j]j]ujKj]rpj)rp}rp(jjqjj8qjj1pjjj}r?q(j]j]j]j]j]ujNjhj]r@qj)rAq}rBq(jj>qjj**ListMP_putTail().** Put an element at the end of the ListMP.rqjj8qjj1pjjj}rq(j]j]j]j]j]ujNjhj]rqj)rq}rq(jjqjjqjj1pjjj}rq(j]j]j]j]j]ujKWj]rq(j)rq}rq(jX**ListMP_putTail().**j}rq(j]j]j]j]j]ujjqj]rqjXListMP_putTail().rqrq}rq(jUjjqubajjubjX) Put an element at the end of the ListMP.rqrq}rq(jX) Put an element at the end of the ListMP.jjqubeubaubj{)rq}rq(jXO**ListMP_remove().** Remove the current element from the middle of the ListMP. jj8qjj1pjjj}rq(j]j]j]j]j]ujNjhj]rqj)rq}rq(jXN**ListMP_remove().** Remove the current element from the middle of the ListMP.jjqjj1pjjj}rq(j]j]j]j]j]ujKXj]rq(j)rq}rq(jX**ListMP_remove().**j}rq(j]j]j]j]j]ujjqj]rqjXListMP_remove().rqrq}rq(jUjjqubajjubjX: Remove the current element from the middle of the ListMP.rqrq}rq(jX: Remove the current element from the middle of the ListMP.jjqubeubaubeubj)rq}rq(jXXThis example prints a "flag" field from the list elements in a ListMP instance in order:rqjjpjj1pjjj}rq(j]j]j]j]j]ujKZjhj]rqjXXThis example prints a "flag" field from the list elements in a ListMP instance in order:rqrq}rq(jjqjjqubaubj)rq}rq(jXSystem_printf("On the List: "); testElem = NULL; while ((testElem = ListMP_next(handle, (ListMP_Elem *)testElem)) != NULL) { System_printf("%d ", testElem->flag); }jjpjj1pjjj}rq(j@jAj]j]j]j]j]ujMujhj]rqjXSystem_printf("On the List: "); testElem = NULL; while ((testElem = ListMP_next(handle, (ListMP_Elem *)testElem)) != NULL) { System_printf("%d ", testElem->flag); }rqrq}rq(jUjjqubaubj)rq}rq(jX4This example prints the same items in reverse order:rqjjpjj1pjjj}rq(j]j]j]j]j]ujKdjhj]rqjX4This example prints the same items in reverse order:rqrq}rq(jjqjjqubaubj)rq}rq(jXSystem_printf("in reverse: "); elem = NULL; while ((elem = ListMP_prev(handle, elem)) != NULL) { System_printf("%d ", ((Tester *)elem)->flag); }jjpjj1pjjj}rq(j@jAj]j]j]j]j]ujMjhj]rrjXSystem_printf("in reverse: "); elem = NULL; while ((elem = ListMP_prev(handle, elem)) != NULL) { System_printf("%d ", ((Tester *)elem)->flag); }rrrr}rr(jUjjqubaubj)rr}rr(jX6This example determines if a ListMP instance is empty:rrjjpjj1pjjj}rr(j]j]j]j]j]ujKnjhj]rrjX6This example determines if a ListMP instance is empty:r rr r}r r(jjrjjrubaubj)r r}r r(jXRif (ListMP_empty(handle1) == TRUE) { System_printf("Yes, handle1 is empty\n"); }jjpjj1pjjj}rr(j@jAj]j]j]j]j]ujMjhj]rrjXRif (ListMP_empty(handle1) == TRUE) { System_printf("Yes, handle1 is empty\n"); }rrrr}rr(jUjj rubaubj)rr}rr(jXDThis example places a sequence of even numbers in a ListMP instance:rrjjpjj1pjjj}rr(j]j]j]j]j]ujKvjhj]rrjXDThis example places a sequence of even numbers in a ListMP instance:rrrr}rr(jjrjjrubaubj)rr}rr(jXt/* Add 0, 2, 4, 6, 8 */ for (i = 0; i < COUNT; i = i + 2) { ListMP_putTail(handle1, (ListMP_Elem *)&(buf[i])); }jjpjj1pjjj}rr(j@jAj]j]j]j]j]ujMjhj]rrjXt/* Add 0, 2, 4, 6, 8 */ for (i = 0; i < COUNT; i = i + 2) { ListMP_putTail(handle1, (ListMP_Elem *)&(buf[i])); }rrr r}r!r(jUjjrubaubj)r"r}r#r(jX?The instance state information contains a pointer to the head of the linked-list, which is stored in shared memory. Other attributes of the instance stored in shared memory include the version, status, and the size of the shared address. Other processors can obtain a handle to the linked list by calling ListMP_open().r$rjjpjj1pjjj}r%r(j]j]j]j]j]ujKjhj]r&rjX?The instance state information contains a pointer to the head of the linked-list, which is stored in shared memory. Other attributes of the instance stored in shared memory include the version, status, and the size of the shared address. Other processors can obtain a handle to the linked list by calling ListMP_open().r'rr(r}r)r(jj$rjj"rubaubj)r*r}r+r(jXThe following figure shows local memory and shared memory for processors Proc 0 and Proc 1, in which Proc 0 calls ListMP_create() and Proc 1 calls ListMP_open().r,rjjpjj1pjjj}r-r(j]j]j]j]j]ujKjhj]r.rjXThe following figure shows local memory and shared memory for processors Proc 0 and Proc 1, in which Proc 0 calls ListMP_create() and Proc 1 calls ListMP_open().r/rr0r}r1r(jj,rjj*rubaubjR)r2r}r3r(jX*.. Image:: ../images/IpcUG_ipc_2_4_1.png jjpjj1pjjZj}r4r(UuriX"rtos/../images/IpcUG_ipc_2_4_1.pngr5rj]j]j]j]jX}r6rU*j5rsj]ujKjhj]ubj)r7r}r8r(jXThe cache alignment used by the list is taken from the SharedRegion on a per-region basis. The alignment must be the same across all processors and should be the worst-case cache line boundary.r9rjjpjj1pjjj}r:r(j]j]j]j]j]ujKjhj]r;rjXThe cache alignment used by the list is taken from the SharedRegion on a per-region basis. The alignment must be the same across all processors and should be the worst-case cache line boundary.rr(jj9rjj7rubaubeubj)r?r}r@r(jUjjjjjjj}rAr(j]j]j]j]rBrU heapmp-modulerCraj]rDrj$aujK?jhj]rEr(j)rFr}rGr(jX HeapMP ModulerHrjj?rjjjjj}rIr(j]j]j]j]j]ujK?jhj]rJrjX HeapMP ModulerKrrLr}rMr(jjHrjjFrubaubj7)rNr}rOr(jXFhttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/HeapMP_Modulesjj?rjj:X<source/rtos/PDK_Platform_Software/IPC/HeapMP_Modules.rst.incrPrrQr}rRrbjj>j}rSr(j@jAj]j]j]j]j]ujKjhj]rTrjXFhttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/HeapMP_ModulesrUrrVr}rWr(jUjjNrubaubj)rXr}rYr(jX.. |hmpCfg_Img1| Image:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.html jj?rjjQrjjHj}rZr(j]j]j]j]j]r[rX hmpCfg_Img1r\raujKjhj]r]rj)r^r}r_r(jj\rj}r`r(UrefuriXhhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlrarj]j]j]j]j]ujjXrj]rbrjR)rcr}rdr(jXImage:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlrerj}rfr(UuriXrtos/../images/Book_cfg.pngrgrj]j]j]j]jX}rhrU*jgrsj]Ualtj\rujj^rj]jjZubajjubaubj)rir}rjr(jX.. |hmpCfg_Img2| Image:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.html jj?rjjQrjjHj}rkr(j]j]j]j]j]rlrX hmpCfg_Img2rmraujKjhj]rnrj)ror}rpr(jjmrj}rqr(UrefuriXhhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlrrrj]j]j]j]j]ujjirj]rsrjR)rtr}rur(jXImage:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlrvrj}rwr(UuriXrtos/../images/Book_cfg.pngrxrj]j]j]j]jX}ryrU*jxrsj]Ualtjmrujjorj]jjZubajjubaubj)rzr}r{r(jX.. |hmpCfg_Img3| Image:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.html jj?rjjQrjjHj}r|r(j]j]j]j]j]r}rX hmpCfg_Img3r~raujK jhj]rrj)rr}rr(jj~rj}rr(UrefuriXhhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlrrj]j]j]j]j]ujjzrj]rrjR)rr}rr(jXImage:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlrrj}rr(UuriXrtos/../images/Book_cfg.pngrrj]j]j]j]jX}rrU*jrsj]Ualtj~rujjrj]jjZubajjubaubj)rr}rr(jX.. |hmpRun_Img1| Image:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_heap_buf_m_p_8h.html jj?rjjQrjjHj}rr(j]j]j]j]j]rrX hmpRun_Img1rraujK jhj]rrj)rr}rr(jjrj}rr(UrefuriXshttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_heap_buf_m_p_8h.htmlrrj]j]j]j]j]ujjrj]rrjR)rr}rr(jXImage:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_heap_buf_m_p_8h.htmlrrj}rr(UuriXrtos/../images/Book_run.pngrrj]j]j]j]jX}rrU*jrsj]Ualtjrujjrj]jjZubajjubaubj)rr}rr(jX.. |hmpRun_Img2| Image:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_heap_mem_m_p_8h.html jj?rjjQrjjHj}rr(j]j]j]j]j]rrX hmpRun_Img2rraujKjhj]rrj)rr}rr(jjrj}rr(UrefuriXshttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_heap_mem_m_p_8h.htmlrrj]j]j]j]j]ujjrj]rrjR)rr}rr(jXImage:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_heap_mem_m_p_8h.htmlrrj}rr(UuriXrtos/../images/Book_run.pngrrj]j]j]j]jX}rrU*jrsj]Ualtjrujjrj]jjZubajjubaubj)rr}rr(jX.. |hmpRun_Img3| Image:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_heap_multi_buf_m_p_8h.html jj?rjjQrjjHj}rr(j]j]j]j]j]rrX hmpRun_Img3rraujKjhj]rrj)rr}rr(jjrj}rr(UrefuriXyhttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_heap_multi_buf_m_p_8h.htmlrrj]j]j]j]j]ujjrj]rrjR)rr}rr(jXImage:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_heap_multi_buf_m_p_8h.htmlrrj}rr(UuriXrtos/../images/Book_run.pngrrj]j]j]j]jX}rrU*jrsj]Ualtjrujjrj]jjZubajjubaubjc)rr}rr(jUjj?rjjQrjjfj}rr(j]j]j]j]j]ujKjhj]rrji)rr}rr(jUjlKjjrjjQrjjj}rr(j]j]j]j]j]ujKjhj]ubaubj3)rr}rr(jUjj?rjjQrjj6j}rr(j]j]j]j]j]ujNjhj]rrjy )rr}rr(jUj}rr(j]j]j]j]j]ujjrj]rrj~ )rr}rr(jUj}rr(j]j]j]j]j]UcolsKujjrj]rr(j )rr}rr(jUj}rr(j]j]j]j]j]UcolwidthKujjrj]jj ubj )rr}rr(jUj}rr(j]j]j]j]j]UcolwidthKujjrj]jj ubj )rr}rr(jUj}rr(j]j]j]j]j]UcolwidthKujjrj]jj ubj )rr}rr(jUj}rr(j]j]j]j]j]ujjrj]rrj )rr}rr(jUj}rr(j]j]j]j]j]ujjrj]rrj )rr}rr(jUj}rr(j]UmorecolsKj]j]j]j]ujjrj]rrj)rr}rr(jXAPI Reference LinksrrjjrjjQrjjj}rr(j]j]j]j]j]ujKj]rrjXAPI Reference Linksrrrr}rr(jjrjjrubaubajj ubajj ubajj ubj )rr}rr(jUj}rr(j]j]j]j]j]ujjrj]rr(j )rr}rr(jUj}rr(j]j]j]j]j]ujjrj]rr(j )rr}rr(jUj}rr(j]j]j]j]j]ujjrj]rrj)rr}rr(jX |hmpCfg_Img1|rrjjrjjQrjjj}rr(j]j]j]j]j]ujKj]rrj)rr}rs(jj\rjjrjNjjj}rs(Urefurijarj]j]j]j]j]ujNj]rsjR)rs}rs(jjerjjrjNjjZj}rs(UuriXrtos/../images/Book_cfg.pngrsj]j]j]j]jX}rsU*jssj]Ualtj\rujNj]ubaubaubajj ubj )rs}r s(jUj}r s(j]j]j]j]j]ujjrj]r sj)r s}r s(jX |hmpRun_Img1|rsjjsjjQrjjj}rs(j]j]j]j]j]ujKj]rsj)rs}rs(jjrjj sjNjjj}rs(Urefurijrj]j]j]j]j]ujNj]rsjR)rs}rs(jjrjjsjNjjZj}rs(UuriXrtos/../images/Book_run.pngrsj]j]j]j]jX}rsU*jssj]UaltjrujNj]ubaubaubajj ubj )rs}rs(jUj}rs(j]j]j]j]j]ujjrj]rsj)rs}rs(jXHeapBufr sjjsjjQrjjj}r!s(j]j]j]j]j]ujKj]r"sjXHeapBufr#sr$s}r%s(jj sjjsubaubajj ubejj ubj )r&s}r's(jUj}r(s(j]j]j]j]j]ujjrj]r)s(j )r*s}r+s(jUj}r,s(j]j]j]j]j]ujj&sj]r-sj)r.s}r/s(jX |hmpCfg_Img2|r0sjj*sjjQrjjj}r1s(j]j]j]j]j]ujKj]r2sj)r3s}r4s(jjmrjj.sjNjjj}r5s(Urefurijrrj]j]j]j]j]ujNj]r6sjR)r7s}r8s(jjvrjj3sjNjjZj}r9s(UuriXrtos/../images/Book_cfg.pngr:sj]j]j]j]jX}r;sU*j:ssj]UaltjmrujNj]ubaubaubajj ubj )rs(j]j]j]j]j]ujj&sj]r?sj)r@s}rAs(jX |hmpRun_Img2|rBsjj`_.jj?rjjQrjjj}rs(j]j]j]j]j]ujK"jhj]rs(jXCThe ti.sdo.ipc.heaps package provides three implementations of the rsrs}rs(jXCThe ti.sdo.ipc.heaps package provides three implementations of the jjsubj)rs}rs(jXZ`xdc.runtime.IHeap interface `_j}rs(UnameXxdc.runtime.IHeap interfacejX9http://rtsc.eclipse.org/docs-tip/Using_xdc.runtime_Memoryrsj]j]j]j]j]ujjsj]rsjXxdc.runtime.IHeap interfacersrs}rs(jUjjsubajjubj)rs}rs(jX< jKjjsjj j}rs(Urefurijsj]rsUxdc-runtime-iheap-interfacersaj]j]j]j]rshauj]ubjX.rs}rs(jX.jjsubeubjt)rs}rs(jUjj?rjjQrjjwj}rs(jyX-j]j]j]j]j]ujK%jhj]rs(j{)rs}rs(jX(**HeapBufMP.** Fixed-size memory manager. All buffers allocated from a HeapBufMP instance are of the same size. There can be multiple instances of HeapBufMP that manage different sizes. The ti.sdo.ipc.heaps.HeapBufMP module is modeled after SYS/BIOS 6's HeapBuf module (ti.sysbios.heaps.HeapBuf).jjsjjQrjjj}rs(j]j]j]j]j]ujNjhj]rsj)rs}rs(jX(**HeapBufMP.** Fixed-size memory manager. All buffers allocated from a HeapBufMP instance are of the same size. There can be multiple instances of HeapBufMP that manage different sizes. The ti.sdo.ipc.heaps.HeapBufMP module is modeled after SYS/BIOS 6's HeapBuf module (ti.sysbios.heaps.HeapBuf).jjsjjQrjjj}rs(j]j]j]j]j]ujK%j]rs(j)rs}rs(jX**HeapBufMP.**j}rs(j]j]j]j]j]ujjsj]rsjX HeapBufMP.rsrs}rs(jUjjsubajjubjX Fixed-size memory manager. All buffers allocated from a HeapBufMP instance are of the same size. There can be multiple instances of HeapBufMP that manage different sizes. The ti.sdo.ipc.heaps.HeapBufMP module is modeled after SYS/BIOS 6's HeapBuf module (ti.sysbios.heaps.HeapBuf).rsrs}rs(jX Fixed-size memory manager. All buffers allocated from a HeapBufMP instance are of the same size. There can be multiple instances of HeapBufMP that manage different sizes. The ti.sdo.ipc.heaps.HeapBufMP module is modeled after SYS/BIOS 6's HeapBuf module (ti.sysbios.heaps.HeapBuf).jjsubeubaubj{)rs}rs(jX**HeapMultiBufMP.** Each instance supports up to 8 different fixed sizes of buffers. When an allocation request is made, the HeapMultiBufMP instance searches the different buckets to find the smallest one that satisfies the request. If that bucket is empty, the allocation fails. The ti.sdo.ipc.heaps.HeapMultiBufMP module is modeled after SYS/BIOS 6's HeapMultiBuf module (ti.sysbios.heaps.HeapMultiBuf).jjsjjQrjjj}rs(j]j]j]j]j]ujNjhj]rsj)rs}rs(jX**HeapMultiBufMP.** Each instance supports up to 8 different fixed sizes of buffers. When an allocation request is made, the HeapMultiBufMP instance searches the different buckets to find the smallest one that satisfies the request. If that bucket is empty, the allocation fails. The ti.sdo.ipc.heaps.HeapMultiBufMP module is modeled after SYS/BIOS 6's HeapMultiBuf module (ti.sysbios.heaps.HeapMultiBuf).jjsjjQrjjj}rs(j]j]j]j]j]ujK(j]rs(j)rs}rs(jX**HeapMultiBufMP.**j}rs(j]j]j]j]j]ujjsj]rsjXHeapMultiBufMP.rsrs}rs(jUjjsubajjubjX Each instance supports up to 8 different fixed sizes of buffers. When an allocation request is made, the HeapMultiBufMP instance searches the different buckets to find the smallest one that satisfies the request. If that bucket is empty, the allocation fails. The ti.sdo.ipc.heaps.HeapMultiBufMP module is modeled after SYS/BIOS 6's HeapMultiBuf module (ti.sysbios.heaps.HeapMultiBuf).rsrs}rs(jX Each instance supports up to 8 different fixed sizes of buffers. When an allocation request is made, the HeapMultiBufMP instance searches the different buckets to find the smallest one that satisfies the request. If that bucket is empty, the allocation fails. The ti.sdo.ipc.heaps.HeapMultiBufMP module is modeled after SYS/BIOS 6's HeapMultiBuf module (ti.sysbios.heaps.HeapMultiBuf).jjsubeubaubj{)rs}rs(jX**HeapMemMP.** Variable-size memory manager. HeapMemMP manages a single buffer in shared memory from which blocks of user-specified length are allocated and freed. The ti.sdo.ipc.heaps.HeapMemMP module is modeled after SYS/BIOS 6's HeapMem module (ti.sysbios.heaps.HeapMem). jjsjjQrjjj}rs(j]j]j]j]j]ujNjhj]rsj)rs}rs(jX**HeapMemMP.** Variable-size memory manager. HeapMemMP manages a single buffer in shared memory from which blocks of user-specified length are allocated and freed. The ti.sdo.ipc.heaps.HeapMemMP module is modeled after SYS/BIOS 6's HeapMem module (ti.sysbios.heaps.HeapMem).jjsjjQrjjj}rs(j]j]j]j]j]ujK+j]rs(j)rs}rs(jX**HeapMemMP.**j}rs(j]j]j]j]j]ujjsj]rsjX HeapMemMP.rsrs}rs(jUjjsubajjubjX Variable-size memory manager. HeapMemMP manages a single buffer in shared memory from which blocks of user-specified length are allocated and freed. The ti.sdo.ipc.heaps.HeapMemMP module is modeled after SYS/BIOS 6's HeapMem module (ti.sysbios.heaps.HeapMem).rsrs}rs(jX Variable-size memory manager. HeapMemMP manages a single buffer in shared memory from which blocks of user-specified length are allocated and freed. The ti.sdo.ipc.heaps.HeapMemMP module is modeled after SYS/BIOS 6's HeapMem module (ti.sysbios.heaps.HeapMem).jjsubeubaubeubj)rs}rs(jXoThe main addition to these modules is the use of shared memory and the management of multi-processor exclusion.rsjj?rjjQrjjj}rs(j]j]j]j]j]ujK.jhj]rsjXoThe main addition to these modules is the use of shared memory and the management of multi-processor exclusion.rsrs}rs(jjsjjsubaubj)rs}rs(jXThe SharedRegion modules, and therefore the MessageQ module and other IPC modules that use SharedRegion, use a HeapMemMP instance internally.rsjj?rjjQrjjj}rs(j]j]j]j]j]ujK0jhj]rsjXThe SharedRegion modules, and therefore the MessageQ module and other IPC modules that use SharedRegion, use a HeapMemMP instance internally.rsrs}rs(jjsjjsubaubj)rs}rs(jXiThe following subsections use "Heap*MP" to refer to the HeapBufMP, HeapMultiBufMP, and HeapMemMP modules.rsjj?rjjQrjjj}rs(j]j]j]j]j]ujK2jhj]rsjXiThe following subsections use "Heap*MP" to refer to the HeapBufMP, HeapMultiBufMP, and HeapMemMP modules.rsrs}rs(jjsjjsubaubj)rs}rs(jXThese Heap*MP Modules are only available on SYS/BIOS-based cores, they are not available when running an HLOS (e.g. Linux). As an HLOS shared memory solution, many Linux SDKs are recommending/providing CMEM. There are limitations (e.g. you cannot alloc on HLOS and free on RTOS), but these are in line with using the HLOS as a master (owning all resources) and RTOS as a slave (using resources provided by the master).jj?rjjQrjjj}rs(j]j]j]j]j]ujNjhj]rsj)rs}rs(jXThese Heap*MP Modules are only available on SYS/BIOS-based cores, they are not available when running an HLOS (e.g. Linux). As an HLOS shared memory solution, many Linux SDKs are recommending/providing CMEM. There are limitations (e.g. you cannot alloc on HLOS and free on RTOS), but these are in line with using the HLOS as a master (owning all resources) and RTOS as a slave (using resources provided by the master).rsjjsjjQrjjj}rs(j]j]j]j]j]ujK5j]rsjXThese Heap*MP Modules are only available on SYS/BIOS-based cores, they are not available when running an HLOS (e.g. Linux). As an HLOS shared memory solution, many Linux SDKs are recommending/providing CMEM. There are limitations (e.g. you cannot alloc on HLOS and free on RTOS), but these are in line with using the HLOS as a master (owning all resources) and RTOS as a slave (using resources provided by the master).rtrt}rt(jjsjjsubaubaubj)rt}rt(jUjj?rjjQrjjj}rt(j]j]j]j]rtUconfiguring-a-heap-mp-modulertaj]rtj}aujK;jhj]r t(j)r t}r t(jXConfiguring a Heap*MP Moduler tjjtjjQrjjj}r t(j]j]j]j]j]ujK;jhj]rtjXConfiguring a Heap*MP Modulertrt}rt(jj tjj tubaubj)rt}rt(jXIn addition to configuring Heap*MP instances, you can set module-wide configuration properties. For example, the maxNameLen property lets you set the maximum length of heap names. The track[Max]Allocs module configuration property enables/disables tracking memory allocation statistics.rtjjtjjQrjjj}rt(j]j]j]j]j]ujKt}r?t(jX.Both processors must have the same endianness.r@tjj:tjjQrjjj}rAt(j]j]j]j]j]ujKGj]rBtjX.Both processors must have the same endianness.rCtrDt}rEt(jj@tjj>tubaubaubeubeubj)rFt}rGt(jUjj?rjjQrjjj}rHt(j]j]j]j]rItUcreating-a-heap-mp-instancerJtaj]rKthaujKJjhj]rLt(j)rMt}rNt(jXCreating a Heap*MP InstancerOtjjFtjjQrjjj}rPt(j]j]j]j]j]ujKJjhj]rQtjXCreating a Heap*MP InstancerRtrSt}rTt(jjOtjjMtubaubj)rUt}rVt(jXHeaps can be created dynamically. You use the Heap*MP_create() functions to dynamically create Heap*MP instances. As with other IPC modules, before creating a Heap*MP instance, you initialize a Heap*MP_Params structure and set fields in the structure to the desired values. When you create a heap, the shared memory is initialized and the Heap*MP object is created in local memory. Only the actual buffers and some shared information reside in shared memory.rWtjjFtjjQrjjj}rXt(j]j]j]j]j]ujKKjhj]rYtjXHeaps can be created dynamically. You use the Heap*MP_create() functions to dynamically create Heap*MP instances. As with other IPC modules, before creating a Heap*MP instance, you initialize a Heap*MP_Params structure and set fields in the structure to the desired values. When you create a heap, the shared memory is initialized and the Heap*MP object is created in local memory. Only the actual buffers and some shared information reside in shared memory.rZtr[t}r\t(jjWtjjUtubaubj)r]t}r^t(jXThe following code example initializes a HeapBufMP_Params structure and sets fields in it. It then creates and registers an instance of the HeapBufMP module.r_tjjFtjjQrjjj}r`t(j]j]j]j]j]ujKPjhj]ratjXThe following code example initializes a HeapBufMP_Params structure and sets fields in it. It then creates and registers an instance of the HeapBufMP module.rbtrct}rdt(jj_tjj]tubaubj)ret}rft(jXj/* Create the heap that will be used to allocate messages. */ HeapBufMP_Params_init(&heapBufMPParams); heapBufMPParams.regionId = 0; /* use default region */ heapBufMPParams.name = "myHeap"; heapBufMPParams.align = 256; heapBufMPParams.numBlocks = 40; heapBufMPParams.blockSize = 1024; heapBufMPParams.gate = NULL; /* use system gate */ heapHandle = HeapBufMP_create(&heapBufMPParams); if (heapHandle == NULL) { System_abort("HeapBufMP_create failed\n"); } /* Register this heap with MessageQ */ MessageQ_registerHeap(HeapBufMP_Handle_upCast(heapHandle), HEAPID);jjFtjjQrjjj}rgt(j@jAj]j]j]j]j]ujMjhj]rhtjXj/* Create the heap that will be used to allocate messages. */ HeapBufMP_Params_init(&heapBufMPParams); heapBufMPParams.regionId = 0; /* use default region */ heapBufMPParams.name = "myHeap"; heapBufMPParams.align = 256; heapBufMPParams.numBlocks = 40; heapBufMPParams.blockSize = 1024; heapBufMPParams.gate = NULL; /* use system gate */ heapHandle = HeapBufMP_create(&heapBufMPParams); if (heapHandle == NULL) { System_abort("HeapBufMP_create failed\n"); } /* Register this heap with MessageQ */ MessageQ_registerHeap(HeapBufMP_Handle_upCast(heapHandle), HEAPID);ritrjt}rkt(jUjjetubaubj)rlt}rmt(jXThe parameters for the various Heap*MP implementations vary. For example, when you create a HeapBufMP instance, you can configure the following parameters after initializing the HeapBufMP_Params structure:rntjjFtjjQrjjj}rot(j]j]j]j]j]ujKejhj]rptjXThe parameters for the various Heap*MP implementations vary. For example, when you create a HeapBufMP instance, you can configure the following parameters after initializing the HeapBufMP_Params structure:rqtrrt}rst(jjntjjltubaubjt)rtt}rut(jUjjFtjjQrjjwj}rvt(jyX-j]j]j]j]j]ujKhjhj]rwt(j{)rxt}ryt(jXf**regionId.** The index corresponding to the shared region from which shared memory will be allocated.rztjjttjjQrjjj}r{t(j]j]j]j]j]ujNjhj]r|tj)r}t}r~t(jjztjjxtjjQrjjj}rt(j]j]j]j]j]ujKhj]rt(j)rt}rt(jX **regionId.**j}rt(j]j]j]j]j]ujj}tj]rtjX regionId.rtrt}rt(jUjjtubajjubjXY The index corresponding to the shared region from which shared memory will be allocated.rtrt}rt(jXY The index corresponding to the shared region from which shared memory will be allocated.jj}tubeubaubj{)rt}rt(jX@**name.** A name of the heap instance for NameServer (optional).rtjjttjjQrjjj}rt(j]j]j]j]j]ujNjhj]rtj)rt}rt(jjtjjtjjQrjjj}rt(j]j]j]j]j]ujKij]rt(j)rt}rt(jX **name.**j}rt(j]j]j]j]j]ujjtj]rtjXname.rtrt}rt(jUjjtubajjubjX7 A name of the heap instance for NameServer (optional).rtrt}rt(jX7 A name of the heap instance for NameServer (optional).jjtubeubaubj{)rt}rt(jX.**align.** Requested alignment for each block.rtjjttjjQrjjj}rt(j]j]j]j]j]ujNjhj]rtj)rt}rt(jjtjjtjjQrjjj}rt(j]j]j]j]j]ujKjj]rt(j)rt}rt(jX **align.**j}rt(j]j]j]j]j]ujjtj]rtjXalign.rtrt}rt(jUjjtubajjubjX$ Requested alignment for each block.rtrt}rt(jX$ Requested alignment for each block.jjtubeubaubj{)rt}rt(jX+**numBlocks.** Number of fixed size blocks.rtjjttjjQrjjj}rt(j]j]j]j]j]ujNjhj]rtj)rt}rt(jjtjjtjjQrjjj}rt(j]j]j]j]j]ujKkj]rt(j)rt}rt(jX**numBlocks.**j}rt(j]j]j]j]j]ujjtj]rtjX numBlocks.rtrt}rt(jUjjtubajjubjX Number of fixed size blocks.rtrt}rt(jX Number of fixed size blocks.jjtubeubaubj{)rt}rt(jX3**blockSize.** Size of the blocks in this instance.rtjjttjjQrjjj}rt(j]j]j]j]j]ujNjhj]rtj)rt}rt(jjtjjtjjQrjjj}rt(j]j]j]j]j]ujKlj]rt(j)rt}rt(jX**blockSize.**j}rt(j]j]j]j]j]ujjtj]rtjX blockSize.rtrt}rt(jUjjtubajjubjX% Size of the blocks in this instance.rtrt}rt(jX% Size of the blocks in this instance.jjtubeubaubj{)rt}rt(jX7**gate.** A multiprocessor gate for context protection.rtjjttjjQrjjj}rt(j]j]j]j]j]ujNjhj]rtj)rt}rt(jjtjjtjjQrjjj}rt(j]j]j]j]j]ujKmj]rt(j)rt}rt(jX **gate.**j}rt(j]j]j]j]j]ujjtj]rtjXgate.rtrt}rt(jUjjtubajjubjX. A multiprocessor gate for context protection.rtrt}rt(jX. A multiprocessor gate for context protection.jjtubeubaubj{)rt}rt(jX\**exact.** Only allocate a block if the requested size is an exact match. Default is false. jjttjjQrjjj}rt(j]j]j]j]j]ujNjhj]rtj)rt}rt(jX[**exact.** Only allocate a block if the requested size is an exact match. Default is false.jjtjjQrjjj}rt(j]j]j]j]j]ujKnj]rt(j)rt}rt(jX **exact.**j}rt(j]j]j]j]j]ujjtj]rtjXexact.rtrt}rt(jUjjtubajjubjXQ Only allocate a block if the requested size is an exact match. Default is false.rtrt}rt(jXQ Only allocate a block if the requested size is an exact match. Default is false.jjtubeubaubeubj)rt}rt(jXoOf these parameters, the ones that are common to all three Heap*MP implementations are gate, name and regionId.rtjjFtjjQrjjj}rt(j]j]j]j]j]ujKpjhj]rujXoOf these parameters, the ones that are common to all three Heap*MP implementations are gate, name and regionId.ruru}ru(jjtjjtubaubeubj)ru}ru(jUjj?rjjQrjjj}ru(j]j]j]j]ruUopening-a-heap-mp-instanceruaj]r uhpaujKsjhj]r u(j)r u}r u(jXOpening a Heap*MP Instancer ujjujjQrjjj}ru(j]j]j]j]j]ujKsjhj]rujXOpening a Heap*MP Instanceruru}ru(jj ujj uubaubj)ru}ru(jX'Once a Heap*MP instance is created on a processor, the heap can be opened on another processor to obtain a local handle to the same shared instance. In order for a remote processor to obtain a handle to a Heap*MP that has been created, the remote processor needs to open it using Heap*MP_open().rujjujjQrjjj}ru(j]j]j]j]j]ujKtjhj]rujX'Once a Heap*MP instance is created on a processor, the heap can be opened on another processor to obtain a local handle to the same shared instance. In order for a remote processor to obtain a handle to a Heap*MP that has been created, the remote processor needs to open it using Heap*MP_open().ruru}ru(jjujjuubaubj)ru}ru(jXThe Heap*MP modules use a NameServer instance to allow a remote processor to address the local Heap*MP instance using a user-configurable string value as an identifier. The Heap*MP name is the sole parameter needed to identify an instance.rujjujjQrjjj}ru(j]j]j]j]j]ujKwjhj]rujXThe Heap*MP modules use a NameServer instance to allow a remote processor to address the local Heap*MP instance using a user-configurable string value as an identifier. The Heap*MP name is the sole parameter needed to identify an instance.r ur!u}r"u(jjujjuubaubj)r#u}r$u(jXThe heap must be created before it can be opened. An open call matches the call's version number with the creator's version number in order to ensure compatibility. For example:r%ujjujjQrjjj}r&u(j]j]j]j]j]ujKzjhj]r'ujXThe heap must be created before it can be opened. An open call matches the call's version number with the creator's version number in order to ensure compatibility. For example:r(ur)u}r*u(jj%ujj#uubaubj)r+u}r,u(jX HeapBufMP_Handle heapHandle; ...r-ujjujjQrjjj}r.u(j]j]j]j]j]ujK}jhj]r/ujX HeapBufMP_Handle heapHandle; ...r0ur1u}r2u(jj-ujj+uubaubj)r3u}r4u(jX/* Open heap created by other processor. Loop until open. */ do { status = HeapBufMP_open("myHeap", &heapHandle); } while (status < 0); /* Register this heap with MessageQ */ MessageQ_registerHeap(HeapBufMP_Handle_upCast(heapHandle), HEAPID);jjujjQrjjj}r5u(j@jAj]j]j]j]j]ujM)jhj]r6ujX/* Open heap created by other processor. Loop until open. */ do { status = HeapBufMP_open("myHeap", &heapHandle); } while (status < 0); /* Register this heap with MessageQ */ MessageQ_registerHeap(HeapBufMP_Handle_upCast(heapHandle), HEAPID);r7ur8u}r9u(jUjj3uubaubeubj)r:u}r;u(jUjj?rjjQrjjj}ruaj]r?uj(aujKjhj]r@u(j)rAu}rBu(jXClosing a Heap*MP InstancerCujj:ujjQrjjj}rDu(j]j]j]j]j]ujKjhj]rEujXClosing a Heap*MP InstancerFurGu}rHu(jjCujjAuubaubj)rIu}rJu(jXHeap*MP_close() frees an opened Heap*MP instance stored in local memory. Heap*MP_close() may only be used to finalize instances that were opened with Heap*MP_open() by this thread. For example:rKujj:ujjQrjjj}rLu(j]j]j]j]j]ujKjhj]rMujXHeap*MP_close() frees an opened Heap*MP instance stored in local memory. Heap*MP_close() may only be used to finalize instances that were opened with Heap*MP_open() by this thread. For example:rNurOu}rPu(jjKujjIuubaubj)rQu}rRu(jXHeapBufMP_close(&heapHandle);jj:ujjQrjjj}rSu(j@jAj]j]j]j]j]ujM8jhj]rTujXHeapBufMP_close(&heapHandle);rUurVu}rWu(jUjjQuubaubj)rXu}rYu(jXTNever call Heap*MP_close() if some other thread has already called Heap*MP_delete().rZujj:ujjQrjjj}r[u(j]j]j]j]j]ujKjhj]r\ujXTNever call Heap*MP_close() if some other thread has already called Heap*MP_delete().r]ur^u}r_u(jjZujjXuubaubeubj)r`u}rau(jUjj?rjjQrjjj}rbu(j]j]j]j]rcuUdeleting-a-heap-mp-instancerduaj]reuh_aujKjhj]rfu(j)rgu}rhu(jXDeleting a Heap*MP Instanceriujj`ujjQrjjj}rju(j]j]j]j]j]ujKjhj]rkujXDeleting a Heap*MP Instancerlurmu}rnu(jjiujjguubaubj)rou}rpu(jXOThe Heap*MP creator thread can use Heap*MP_delete() to free a Heap*MP object stored in local memory and to flag the shared memory to indicate that the heap is no longer initialized. Heap*MP_delete() may not be used to finalize a heap using a handle acquired using Heap*MP_open()--Heap*MP_close() should be used by such threads instead.rqujj`ujjQrjjj}rru(j]j]j]j]j]ujKjhj]rsujXOThe Heap*MP creator thread can use Heap*MP_delete() to free a Heap*MP object stored in local memory and to flag the shared memory to indicate that the heap is no longer initialized. Heap*MP_delete() may not be used to finalize a heap using a handle acquired using Heap*MP_open()--Heap*MP_close() should be used by such threads instead.rturuu}rvu(jjqujjouubaubeubj)rwu}rxu(jUjj?rjjQrjjj}ryu(j]j]j]j]rzuUallocating-memory-from-the-heapr{uaj]r|uh"aujKjhj]r}u(j)r~u}ru(jXAllocating Memory from the HeaprujjwujjQrjjj}ru(j]j]j]j]j]ujKjhj]rujXAllocating Memory from the Heapruru}ru(jjujj~uubaubj)ru}ru(jXPThe HeapBufMP_alloc() function obtains the first buffer off the heap's freeList.rujjwujjQrjjj}ru(j]j]j]j]j]ujKjhj]rujXPThe HeapBufMP_alloc() function obtains the first buffer off the heap's freeList.ruru}ru(jjujjuubaubj)ru}ru(jXThe HeapMultiBufMP_alloc() function searches through the buckets to find the smallest size that honors the requested size. It obtains the first block on that bucket.rujjwujjQrjjj}ru(j]j]j]j]j]ujKjhj]rujXThe HeapMultiBufMP_alloc() function searches through the buckets to find the smallest size that honors the requested size. It obtains the first block on that bucket.ruru}ru(jjujjuubaubj)ru}ru(jXIf the "exact" field in the Heap*BufMP_Params structure was true when the heap was created, the alloc only returns the block if the blockSize for a bucket is the exact size requested. If no exact size is found, an allocation error is returned.rujjwujjQrjjj}ru(j]j]j]j]j]ujKjhj]rujXIf the "exact" field in the Heap*BufMP_Params structure was true when the heap was created, the alloc only returns the block if the blockSize for a bucket is the exact size requested. If no exact size is found, an allocation error is returned.ruru}ru(jjujjuubaubj)ru}ru(jX_The HeapMemMP_alloc() function allocates a block of memory of the requested size from the heap.rujjwujjQrjjj}ru(j]j]j]j]j]ujKjhj]rujX_The HeapMemMP_alloc() function allocates a block of memory of the requested size from the heap.ruru}ru(jjujjuubaubj)ru}ru(jXFor all of these allocation functions, the cache coherency of the message is managed by the SharedRegion module that manages the shared memory region used for the heap.rujjwujjQrjjj}ru(j]j]j]j]j]ujKjhj]rujXFor all of these allocation functions, the cache coherency of the message is managed by the SharedRegion module that manages the shared memory region used for the heap.ruru}ru(jjujjuubaubeubj)ru}ru(jUjj?rjjQrjjj}ru(j]j]j]j]ruUfreeing-memory-to-the-heapruaj]ruhaujKjhj]ru(j)ru}ru(jXFreeing Memory to the HeaprujjujjQrjjj}ru(j]j]j]j]j]ujKjhj]rujXFreeing Memory to the Heapruru}ru(jjujjuubaubj)ru}ru(jXFThe HeapBufMP_free() function returns an allocated buffer to its heap.rujjujjQrjjj}ru(j]j]j]j]j]ujKjhj]rujXFThe HeapBufMP_free() function returns an allocated buffer to its heap.ruru}ru(jjujjuubaubj)ru}ru(jXThe HeapMultiBufMP_free() function searches through the buckets to determine on which bucket the block should be returned. This is determined by the same algorithm as the HeapMultiBufMP_alloc() function, namely the smallest blockSize that the block can fit into.rujjujjQrjjj}ru(j]j]j]j]j]ujKjhj]rujXThe HeapMultiBufMP_free() function searches through the buckets to determine on which bucket the block should be returned. This is determined by the same algorithm as the HeapMultiBufMP_alloc() function, namely the smallest blockSize that the block can fit into.ruru}ru(jjujjuubaubj)ru}ru(jXIf the "exact" field in the Heap*BufMP_Params structure was true when the heap was created, and the size of the block to free does not match any bucket's blockSize, an assert is raised.rujjujjQrjjj}ru(j]j]j]j]j]ujKjhj]rujXIf the "exact" field in the Heap*BufMP_Params structure was true when the heap was created, and the size of the block to free does not match any bucket's blockSize, an assert is raised.ruru}ru(jjujjuubaubj)ru}ru(jXPThe HeapMemMP_free() function returns the allocated block of memory to its heap.rujjujjQrjjj}ru(j]j]j]j]j]ujKjhj]rujXPThe HeapMemMP_free() function returns the allocated block of memory to its heap.ruru}ru(jjujjuubaubj)ru}ru(jXhFor all of these deallocation functions, cache coherency is managed by the corresponding Heap*MP module.rujjujjQrjjj}ru(j]j]j]j]j]ujKjhj]rujXhFor all of these deallocation functions, cache coherency is managed by the corresponding Heap*MP module.ruru}ru(jjujjuubaubeubj)ru}ru(jUjj?rjjQrjjj}ru(j]j]j]j]ruUquerying-heap-statisticsruaj]ruhaujKjhj]ru(j)ru}ru(jXQuerying Heap StatisticsrujjujjQrjjj}ru(j]j]j]j]j]ujKjhj]rujXQuerying Heap Statisticsruru}ru(jjujjuubaubj)ru}ru(jX|Both heap modules support use of the xdc.runtime.Memory module's Memory_getStats() and Memory_query() functions on the heap.rujjujjQrjjj}ru(j]j]j]j]j]ujKjhj]rujX|Both heap modules support use of the xdc.runtime.Memory module's Memory_getStats() and Memory_query() functions on the heap.ruru}ru(jjujjuubaubj)ru}ru(jXIn addition, the Heap*MP modules provide the Heap*MP_getStats(), Heap*MP_getExtendedStats(), and Heap*MP_isBlocking() functions to enable you to gather information about a heap.rujjujjQrjjj}ru(j]j]j]j]j]ujKjhj]rvjXIn addition, the Heap*MP modules provide the Heap*MP_getStats(), Heap*MP_getExtendedStats(), and Heap*MP_isBlocking() functions to enable you to gather information about a heap.rvrv}rv(jjujjuubaubj)rv}rv(jXIBy default, allocation tracking is often disabled in shared-heap modules for performance reasons. You can set the HeapBufMP.trackAllocs and HeapMultiBufMP.trackMaxAllocs configuration properties to true in order to turn on allocation tracking for their respective modules. Refer to the CDOC documentation for further information.rvjjujjQrjjj}rv(j]j]j]j]j]ujKjhj]rvjXIBy default, allocation tracking is often disabled in shared-heap modules for performance reasons. You can set the HeapBufMP.trackAllocs and HeapMultiBufMP.trackMaxAllocs configuration properties to true in order to turn on allocation tracking for their respective modules. Refer to the CDOC documentation for further information.r vr v}r v(jjvjjvubaubj)r v}r v(jXSample Runtime Program Flow The following diagram shows the program flow for a two-processor (or two-thread) application. This application creates a Heap*MP instance dynamically.rvjjujjQrjjj}rv(j]j]j]j]j]ujKjhj]rvjXSample Runtime Program Flow The following diagram shows the program flow for a two-processor (or two-thread) application. This application creates a Heap*MP instance dynamically.rvrv}rv(jjvjj vubaubjR)rv}rv(jX(.. Image:: ../images/heapmp_bigfig.png jjujXSinternal padding after source/rtos/PDK_Platform_Software/IPC/HeapMP_Modules.rst.incrvjjZj}rv(UuriX rtos/../images/heapmp_bigfig.pngrvj]j]j]j]jX}rvU*jvsj]ujKjhj]ubeubeubj)rv}rv(jUjjjjjjj}rv(j]j]j]j]rvU gatemp-modulervaj]rvhaujKCjhj]r v(j)r!v}r"v(jX GateMP Moduler#vjjvjjjjj}r$v(j]j]j]j]j]ujKCjhj]r%vjX GateMP Moduler&vr'v}r(v(jj#vjj!vubaubj7)r)v}r*v(jXEhttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/GateMP_Modulejjvjj:X;source/rtos/PDK_Platform_Software/IPC/GateMP_Module.rst.incr+vr,v}r-vbjj>j}r.v(j@jAj]j]j]j]j]ujKjhj]r/vjXEhttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/GateMP_Moduler0vr1v}r2v(jUjj)vubaubj)r3v}r4v(jX.. |gpmCfg_Img1| Image:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.html jjvjj,vjjHj}r5v(j]j]j]j]j]r6vX gpmCfg_Img1r7vaujKjhj]r8vj)r9v}r:v(jj7vj}r;v(UrefuriXhhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlrv}r?v(jXImage:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlr@vj}rAv(UuriXrtos/../images/Book_cfg.pngrBvj]j]j]j]jX}rCvU*jBvsj]Ualtj7vujj9vj]jjZubajjubaubj)rDv}rEv(jX.. |gmpRun_Img1| Image:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_gate_m_p_8h.html jjvjj,vjjHj}rFv(j]j]j]j]j]rGvX gmpRun_Img1rHvaujKjhj]rIvj)rJv}rKv(jjHvj}rLv(UrefuriXohttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_gate_m_p_8h.htmlrMvj]j]j]j]j]ujjDvj]rNvjR)rOv}rPv(jXImage:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_gate_m_p_8h.htmlrQvj}rRv(UuriXrtos/../images/Book_run.pngrSvj]j]j]j]jX}rTvU*jSvsj]UaltjHvujjJvj]jjZubajjubaubj)rUv}rVv(jX.. |gmpRun_Img2| Image:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_gate_m_p_8h.html jjvjj,vjjHj}rWv(j]j]j]j]j]rXvX gmpRun_Img2rYvaujK jhj]rZvj)r[v}r\v(jjYvj}r]v(UrefuriXohttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_gate_m_p_8h.htmlr^vj]j]j]j]j]ujjUvj]r_vjR)r`v}rav(jXImage:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_gate_m_p_8h.htmlrbvj}rcv(UuriXrtos/../images/Book_run.pngrdvj]j]j]j]jX}revU*jdvsj]UaltjYvujj[vj]jjZubajjubaubjc)rfv}rgv(jUjjvjj,vjjfj}rhv(j]j]j]j]j]ujK jhj]rivji)rjv}rkv(jUjlKjjfvjj,vjjj}rlv(j]j]j]j]j]ujKjhj]ubaubj3)rmv}rnv(jUjjvjj,vjj6j}rov(j]j]j]j]j]ujNjhj]rpvjy )rqv}rrv(jUj}rsv(j]j]j]j]j]ujjmvj]rtvj~ )ruv}rvv(jUj}rwv(j]j]j]j]j]UcolsKujjqvj]rxv(j )ryv}rzv(jUj}r{v(j]j]j]j]j]UcolwidthKujjuvj]jj ubj )r|v}r}v(jUj}r~v(j]j]j]j]j]UcolwidthKujjuvj]jj ubj )rv}rv(jUj}rv(j]j]j]j]j]ujjuvj]rvj )rv}rv(jUj}rv(j]j]j]j]j]ujjvj]rvj )rv}rv(jUj}rv(j]UmorecolsKj]j]j]j]ujjvj]rvj)rv}rv(jXAPI Reference Linksrvjjvjj,vjjj}rv(j]j]j]j]j]ujKj]rvjXAPI Reference Linksrvrv}rv(jjvjjvubaubajj ubajj ubajj ubj )rv}rv(jUj}rv(j]j]j]j]j]ujjuvj]rvj )rv}rv(jUj}rv(j]j]j]j]j]ujjvj]rv(j )rv}rv(jUj}rv(j]j]j]j]j]ujjvj]rvj)rv}rv(jX |gpmCfg_Img1|rvjjvjj,vjjj}rv(j]j]j]j]j]ujKj]rvj)rv}rv(jj7vjjvjNjjj}rv(Urefurijwr?w}r@w(jj;wjj9wubaubj)rAw}rBw(jXA gate can be configured to implement local protection at various levels. This is done via the params.localProtect configuration property (BIOS-only). The options for params.localProtect are as follows:rCwjjvjj,vjjj}rDw(j]j]j]j]j]ujKAjhj]rEwjXA gate can be configured to implement local protection at various levels. This is done via the params.localProtect configuration property (BIOS-only). The options for params.localProtect are as follows:rFwrGw}rHw(jjCwjjAwubaubjt)rIw}rJw(jUjjvjj,vjjwj}rKw(jyX-j]j]j]j]j]ujKEjhj]rLw(j{)rMw}rNw(jXGateMP_LocalProtect_NONE. Uses the XDCtools GateNull implementation, which does not offer any local context protection. For example, you might use this option for a single-threaded local application that still needs remote protection.jjIwjj,vjjj}rOw(j]j]j]j]j]ujNjhj]rPwj)rQw}rRw(jXGateMP_LocalProtect_NONE. Uses the XDCtools GateNull implementation, which does not offer any local context protection. For example, you might use this option for a single-threaded local application that still needs remote protection.rSwjjMwjj,vjjj}rTw(j]j]j]j]j]ujKEj]rUwjXGateMP_LocalProtect_NONE. Uses the XDCtools GateNull implementation, which does not offer any local context protection. For example, you might use this option for a single-threaded local application that still needs remote protection.rVwrWw}rXw(jjSwjjQwubaubaubj{)rYw}rZw(jXlGateMP_LocalProtect_INTERRUPT. Uses the SYS/BIOS GateHwi implementation, which disables hardware interrupts.r[wjjIwjj,vjjj}r\w(j]j]j]j]j]ujNjhj]r]wj)r^w}r_w(jj[wjjYwjj,vjjj}r`w(j]j]j]j]j]ujKGj]rawjXlGateMP_LocalProtect_INTERRUPT. Uses the SYS/BIOS GateHwi implementation, which disables hardware interrupts.rbwrcw}rdw(jj[wjj^wubaubaubj{)rew}rfw(jXjGateMP_LocalProtect_TASKLET. Uses the SYS/BIOS GateSwi implementation, which disables software interrupts.rgwjjIwjj,vjjj}rhw(j]j]j]j]j]ujNjhj]riwj)rjw}rkw(jjgwjjewjj,vjjj}rlw(j]j]j]j]j]ujKHj]rmwjXjGateMP_LocalProtect_TASKLET. Uses the SYS/BIOS GateSwi implementation, which disables software interrupts.rnwrow}rpw(jjgwjjjwubaubaubj{)rqw}rrw(jXGateMP_LocalProtect_THREAD. Uses the SYS/BIOS GateMutexPri implementation, which is based on Semaphores. This option may use a different gate than the following option on some operating systems. When using SYS/BIOS, they are equivalent.jjIwjj,vjjj}rsw(j]j]j]j]j]ujNjhj]rtwj)ruw}rvw(jXGateMP_LocalProtect_THREAD. Uses the SYS/BIOS GateMutexPri implementation, which is based on Semaphores. This option may use a different gate than the following option on some operating systems. When using SYS/BIOS, they are equivalent.rwwjjqwjj,vjjj}rxw(j]j]j]j]j]ujKIj]rywjXGateMP_LocalProtect_THREAD. Uses the SYS/BIOS GateMutexPri implementation, which is based on Semaphores. This option may use a different gate than the following option on some operating systems. When using SYS/BIOS, they are equivalent.rzwr{w}r|w(jjwwjjuwubaubaubj{)r}w}r~w(jXjGateMP_LocalProtect_PROCESS. Uses the SYS/BIOS GateMutexPri implementation, which is based on Semaphores. jjIwjj,vjjj}rw(j]j]j]j]j]ujNjhj]rwj)rw}rw(jXiGateMP_LocalProtect_PROCESS. Uses the SYS/BIOS GateMutexPri implementation, which is based on Semaphores.rwjj}wjj,vjjj}rw(j]j]j]j]j]ujKKj]rwjXiGateMP_LocalProtect_PROCESS. Uses the SYS/BIOS GateMutexPri implementation, which is based on Semaphores.rwrw}rw(jjwjjwubaubaubeubj)rw}rw(jXThis property is currently ignored (as of IPC 3.23) on non-BIOS OSes. A thread-level mutex is used for local protection independent of this property setting.rwjjvjj,vjjj}rw(j]j]j]j]j]ujKMjhj]rwjXThis property is currently ignored (as of IPC 3.23) on non-BIOS OSes. A thread-level mutex is used for local protection independent of this property setting.rwrw}rw(jjwjjwubaubj)rw}rw(jXHOther fields you are required to set in the GateMP_Params structure are:rwjjvjj,vjjj}rw(j]j]j]j]j]ujKPjhj]rwjXHOther fields you are required to set in the GateMP_Params structure are:rwrw}rw(jjwjjwubaubjt)rw}rw(jUjjvjj,vjjwj}rw(jyX-j]j]j]j]j]ujKRjhj]rw(j{)rw}rw(jX&name. The name of the GateMP instance.rwjjwjj,vjjj}rw(j]j]j]j]j]ujNjhj]rwj)rw}rw(jjwjjwjj,vjjj}rw(j]j]j]j]j]ujKRj]rwjX&name. The name of the GateMP instance.rwrw}rw(jjwjjwubaubaubj{)rw}rw(jXhregionId. The ID of the SharedRegion to use for shared memory used by this GateMP instance (BIOS-only). jjwjj,vjjj}rw(j]j]j]j]j]ujNjhj]rwj)rw}rw(jXgregionId. The ID of the SharedRegion to use for shared memory used by this GateMP instance (BIOS-only).rwjjwjj,vjjj}rw(j]j]j]j]j]ujKSj]rwjXgregionId. The ID of the SharedRegion to use for shared memory used by this GateMP instance (BIOS-only).rwrw}rw(jjwjjwubaubaubeubj)rw}rw(jX|gmpRun_Img2| The latest version of the GateMP module run-time API documentation is available `online `_jjvjj,vjjj}rw(j]j]j]j]j]ujKUjhj]rw(j)rw}rw(jjYvjjwjNjjj}rw(Urefurij^vj]j]j]j]j]ujNjhj]rwjR)rw}rw(jjbvjjwjNjjZj}rw(UuriXrtos/../images/Book_run.pngrwj]j]j]j]jX}rwU*jwsj]UaltjYvujNj]ubaubjXQ The latest version of the GateMP module run-time API documentation is available rwrw}rw(jXQ The latest version of the GateMP module run-time API documentation is available jjwubj)rw}rw(jX{`online `_j}rw(UnameXonlinerwjXohttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_gate_m_p_8h.htmlrwj]j]j]j]j]ujjwj]rwjXonlinerwrw}rw(jUjjwubajjubj)rw}rw(jXr jKjjwjj j}rw(Urefurijwj]rwUid3rwaj]j]rwjwaj]j]uj]ubeubeubj)rw}rw(jUjjvjj,vjjj}rw(j]j]j]j]rwUopening-a-gatemp-instancerwaj]rwhmaujKYjhj]rw(j)rw}rw(jXOpening a GateMP Instancerwjjwjj,vjjj}rw(j]j]j]j]j]ujKYjhj]rwjXOpening a GateMP Instancerwrw}rw(jjwjjwubaubj)rw}rw(jXOnce an instance is created on a processor, the gate can be opened on another processor to obtain a local handle to the same instance.rwjjwjj,vjjj}rw(j]j]j]j]j]ujKZjhj]rwjXOnce an instance is created on a processor, the gate can be opened on another processor to obtain a local handle to the same instance.rwrw}rw(jjwjjwubaubj)rw}rw(jXThe GateMP module uses a NameServer instance to allow a remote processor to address the local GateMP instance using a user-configurable string value as an identifier rather than a potentially dynamic address value.rwjjwjj,vjjj}rw(j]j]j]j]j]ujK\jhj]rwjXThe GateMP module uses a NameServer instance to allow a remote processor to address the local GateMP instance using a user-configurable string value as an identifier rather than a potentially dynamic address value.rwrw}rw(jjwjjwubaubj)rw}rw(jXkstatus = GateMP_open("myGate", &gateHandle); if (status < 0) { System_printf("GateMP_open failed\n"); }jjwjj,vjjj}rw(j@jAj]j]j]j]j]ujMjhj]rwjXkstatus = GateMP_open("myGate", &gateHandle); if (status < 0) { System_printf("GateMP_open failed\n"); }rwrw}rw(jUjjwubaubeubj)rw}rw(jUjjvjj,vjjj}rw(j]j]j]j]rwUclosing-a-gatemp-instancerwaj]rwh[aujKgjhj]rx(j)rx}rx(jXClosing a GateMP Instancerxjjwjj,vjjj}rx(j]j]j]j]j]ujKgjhj]rxjXClosing a GateMP Instancerxrx}rx(jjxjjxubaubj)r x}r x(jX<GateMP_close() frees a GateMP object stored in local memory.r xjjwjj,vjjj}r x(j]j]j]j]j]ujKhjhj]r xjX<GateMP_close() frees a GateMP object stored in local memory.rxrx}rx(jj xjj xubaubj)rx}rx(jXTGateMP_close() should never be called on an instance whose creator has been deleted.rxjjwjj,vjjj}rx(j]j]j]j]j]ujKjjhj]rxjXTGateMP_close() should never be called on an instance whose creator has been deleted.rxrx}rx(jjxjjxubaubeubj)rx}rx(jUjjvjj,vjjj}rx(j]j]j]j]rxUdeleting-a-gatemp-instancerxaj]rxjaujKmjhj]rx(j)r x}r!x(jXDeleting a GateMP Instancer"xjjxjj,vjjj}r#x(j]j]j]j]j]ujKmjhj]r$xjXDeleting a GateMP Instancer%xr&x}r'x(jj"xjj xubaubj)r(x}r)x(jXGateMP_delete() frees a GateMP object stored in local memory and flags the shared memory to indicate that the gate is no longer initialized.r*xjjxjj,vjjj}r+x(j]j]j]j]j]ujKnjhj]r,xjXGateMP_delete() frees a GateMP object stored in local memory and flags the shared memory to indicate that the gate is no longer initialized.r-xr.x}r/x(jj*xjj(xubaubj)r0x}r1x(jXA thread may not use GateMP_delete() if it acquired the handle to the gate using GateMP_open(). Such threads should call GateMP_close() instead.r2xjjxjj,vjjj}r3x(j]j]j]j]j]ujKpjhj]r4xjXA thread may not use GateMP_delete() if it acquired the handle to the gate using GateMP_open(). Such threads should call GateMP_close() instead.r5xr6x}r7x(jj2xjj0xubaubeubj)r8x}r9x(jUjjvjj,vjjj}r:x(j]j]j]j]r;xUentering-a-gatemp-instancerx(j)r?x}r@x(jXEntering a GateMP InstancerAxjj8xjj,vjjj}rBx(j]j]j]j]j]ujKsjhj]rCxjXEntering a GateMP InstancerDxrEx}rFx(jjAxjj?xubaubj)rGx}rHx(jXEither the GateMP creator or opener may call GateMP_enter() to enter a gate. While it is necessary for the opener to wait for a gate to be created to enter a created gate, it isn't necessary for a creator to wait for a gate to be opened before entering it.rIxjj8xjj,vjjj}rJx(j]j]j]j]j]ujKtjhj]rKxjXEither the GateMP creator or opener may call GateMP_enter() to enter a gate. While it is necessary for the opener to wait for a gate to be created to enter a created gate, it isn't necessary for a creator to wait for a gate to be opened before entering it.rLxrMx}rNx(jjIxjjGxubaubj)rOx}rPx(jXGateMP_enter() enters the caller's local gate. The local gate (if supplied) blocks if entered on the local processor. If entered by the remote processor, GateMP_enter() spins until the remote processor has left the gate.rQxjj8xjj,vjjj}rRx(j]j]j]j]j]ujKxjhj]rSxjXGateMP_enter() enters the caller's local gate. The local gate (if supplied) blocks if entered on the local processor. If entered by the remote processor, GateMP_enter() spins until the remote processor has left the gate.rTxrUx}rVx(jjQxjjOxubaubj)rWx}rXx(jXNo matter what the params.localProtection configuration property is set to, after GateMP_enter() returns, the caller has exclusive access to the data protected by this gate.rYxjj8xjj,vjjj}rZx(j]j]j]j]j]ujK{jhj]r[xjXNo matter what the params.localProtection configuration property is set to, after GateMP_enter() returns, the caller has exclusive access to the data protected by this gate.r\xr]x}r^x(jjYxjjWxubaubj)r_x}r`x(jX8A thread may reenter a gate without blocking or failing.raxjj8xjj,vjjj}rbx(j]j]j]j]j]ujK~jhj]rcxjX8A thread may reenter a gate without blocking or failing.rdxrex}rfx(jjaxjj_xubaubj)rgx}rhx(jXGateMP_enter() returns a "key" that is used by GateMP_leave() to leave this gate; this value is used to restore thread preemption to the state that existed just prior to entering this gate.rixjj8xjj,vjjj}rjx(j]j]j]j]j]ujKjhj]rkxjXGateMP_enter() returns a "key" that is used by GateMP_leave() to leave this gate; this value is used to restore thread preemption to the state that existed just prior to entering this gate.rlxrmx}rnx(jjixjjgxubaubj)rox}rpx(jX?IArg key; /* Enter the gate */ key = GateMP_enter(gateHandle);jj8xjj,vjjj}rqx(j@jAj]j]j]j]j]ujMjhj]rrxjX?IArg key; /* Enter the gate */ key = GateMP_enter(gateHandle);rsxrtx}rux(jUjjoxubaubeubj)rvx}rwx(jUjjvjj,vjjj}rxx(j]j]j]j]ryxUleaving-a-gatemp-instancerzxaj]r{xjaujKjhj]r|x(j)r}x}r~x(jXLeaving a GateMP Instancerxjjvxjj,vjjj}rx(j]j]j]j]j]ujKjhj]rxjXLeaving a GateMP Instancerxrx}rx(jjxjj}xubaubj)rx}rx(jXdGateMP_leave() may only called by a thread that has previously entered this gate via GateMP_enter().rxjjvxjj,vjjj}rx(j]j]j]j]j]ujKjhj]rxjXdGateMP_leave() may only called by a thread that has previously entered this gate via GateMP_enter().rxrx}rx(jjxjjxubaubj)rx}rx(jXAfter this method returns, the caller must not access the data structure protected by this gate (unless the caller has entered the gate more than once and other calls to leave remain to balance the number of previous calls to enter).rxjjvxjj,vjjj}rx(j]j]j]j]j]ujKjhj]rxjXAfter this method returns, the caller must not access the data structure protected by this gate (unless the caller has entered the gate more than once and other calls to leave remain to balance the number of previous calls to enter).rxrx}rx(jjxjjxubaubj)rx}rx(jX>IArg key; /* Leave the gate */ GateMP_leave(gateHandle, key);jjvxjj,vjjj}rx(j@jAj]j]j]j]j]ujMjhj]rxjX>IArg key; /* Leave the gate */ GateMP_leave(gateHandle, key);rxrx}rx(jUjjxubaubeubj)rx}rx(jUjjvjj,vjjj}rx(j]j]j]j]rxUquerying-a-gatemp-instancerxaj]rxjaujKjhj]rx(j)rx}rx(jXQuerying a GateMP Instancerxjjxjj,vjjj}rx(j]j]j]j]j]ujKjhj]rxjXQuerying a GateMP Instancerxrx}rx(jjxjjxubaubj)rx}rx(jXGateMP_query() returns TRUE if a gate has a given quality, and FALSE otherwise, including cases when the gate does not recognize the constant describing the quality. The qualities you can query are:rxjjxjj,vjjj}rx(j]j]j]j]j]ujKjhj]rxjXGateMP_query() returns TRUE if a gate has a given quality, and FALSE otherwise, including cases when the gate does not recognize the constant describing the quality. The qualities you can query are:rxrx}rx(jjxjjxubaubjt)rx}rx(jUjjxjj,vjjwj}rx(jyX-j]j]j]j]j]ujKjhj]rx(j{)rx}rx(jXIGateMP_Q_BLOCKING. If GateMP_Q__BLOCKING is FALSE, the gate never blocks.rxjjxjj,vjjj}rx(j]j]j]j]j]ujNjhj]rxj)rx}rx(jjxjjxjj,vjjj}rx(j]j]j]j]j]ujKj]rxjXIGateMP_Q_BLOCKING. If GateMP_Q__BLOCKING is FALSE, the gate never blocks.rxrx}rx(jjxjjxubaubaubj{)rx}rx(jXGateMP_Q_PREEMPTING. If GateMP_Q_PREEMPTING is FALSE, the gate does not allow other threads to preempt the thread that has already entered the gate. jjxjj,vjjj}rx(j]j]j]j]j]ujNjhj]rxj)rx}rx(jXGateMP_Q_PREEMPTING. If GateMP_Q_PREEMPTING is FALSE, the gate does not allow other threads to preempt the thread that has already entered the gate.rxjjxjj,vjjj}rx(j]j]j]j]j]ujKj]rxjXGateMP_Q_PREEMPTING. If GateMP_Q_PREEMPTING is FALSE, the gate does not allow other threads to preempt the thread that has already entered the gate.rxrx}rx(jjxjjxubaubaubeubeubj)rx}rx(jUjjvjj,vjjj}rx(j]j]j]j]rxUnameserver-interactionrxaj]rxhaujKjhj]rx(j)rx}rx(jXNameServer Interactionrxjjxjj,vjjj}rx(j]j]j]j]j]ujKjhj]rxjXNameServer Interactionrxrx}rx(jjxjjxubaubj)rx}rx(jXThe GateMP module uses a ti.sdo.utils.NameServer instance to store instance information when an instance is created and the name parameter is non-NULL. The length of this name is limited to 16 characters (by default) including the null terminator ('\0'). This length can be increased by configuring the GateMP.maxNameLen module configuration property. If a name is supplied, it must be unique for all GateMP instances.jjxjj,vjjj}rx(j]j]j]j]j]ujKjhj]rxjXThe GateMP module uses a ti.sdo.utils.NameServer instance to store instance information when an instance is created and the name parameter is non-NULL. The length of this name is limited to 16 characters (by default) including the null terminator ('0'). This length can be increased by configuring the GateMP.maxNameLen module configuration property. If a name is supplied, it must be unique for all GateMP instances.rxrx}rx(jXThe GateMP module uses a ti.sdo.utils.NameServer instance to store instance information when an instance is created and the name parameter is non-NULL. The length of this name is limited to 16 characters (by default) including the null terminator ('\0'). This length can be increased by configuring the GateMP.maxNameLen module configuration property. If a name is supplied, it must be unique for all GateMP instances.jjxubaubj)rx}rx(jXOther modules can use GateMP instances to protect access to their shared memory resources. For example, the NameServer name tables are protected by setting the "gate" property of the ti.sdo.utils.NameServer module.rxjjxjj,vjjj}rx(j]j]j]j]j]ujKjhj]rxjXOther modules can use GateMP instances to protect access to their shared memory resources. For example, the NameServer name tables are protected by setting the "gate" property of the ti.sdo.utils.NameServer module.rxrx}rx(jjxjjxubaubj)rx}rx(jX;These examples set the "gate" property for various modules:rxjjxjj,vjjj}rx(j]j]j]j]j]ujKjhj]rxjX;These examples set the "gate" property for various modules:rxrx}rx(jjxjjxubaubj)rx}rx(jXVheapBufMPParams.gate = GateMP_getDefaultRemote(); listMPParams.gate = gateHandle;jjxjj,vjjj}rx(j@jAj]j]j]j]j]ujMjhj]rxjXVheapBufMPParams.gate = GateMP_getDefaultRemote(); listMPParams.gate = gateHandle;rxrx}rx(jUjjxubaubeubj)rx}rx(jUjKjjvjj,vjjj}rx(j]rxjpaj]j]j]ryUid4ryaj]ujKjhj]ry(j)ry}ry(jX%Sample Runtime Program Flow (Dynamic)ryjjxjj,vjjj}ry(j]j]j]j]j]ujKjhj]ryjX%Sample Runtime Program Flow (Dynamic)ryr y}r y(jjyjjyubaubj)r y}r y(jXThe following diagram shows the program flow for a two-processor (or two-thread) application. This application creates a Gate dynamically.r yjjxjj,vjjj}ry(j]j]j]j]j]ujKjhj]ryjXThe following diagram shows the program flow for a two-processor (or two-thread) application. This application creates a Gate dynamically.ryry}ry(jj yjj yubaubjR)ry}ry(jX+.. Image:: ../images/IpcUG_ipc_2_6_1.png jjxjXRinternal padding after source/rtos/PDK_Platform_Software/IPC/GateMP_Module.rst.incryjjZj}ry(UuriX"rtos/../images/IpcUG_ipc_2_6_1.pngryj]j]j]j]jX}ryU*jysj]ujKjhj]ubeubeubj)ry}ry(jUjjjjjjj}ry(j]j]j]j]ryU&gatemp-support-for-uio-and-misc-driverryaj]ryj1aujKGjhj]ry(j)r y}r!y(jX&GateMP Support for UIO and Misc Driverr"yjjyjjjjj}r#y(j]j]j]j]j]ujKGjhj]r$yjX&GateMP Support for UIO and Misc Driverr%yr&y}r'y(jj"yjj yubaubj7)r(y}r)y(jXRhttp://processors.wiki.ti.com/index.php/IPC_GateMP_Support_for_UIO_and_Misc_Driverjjyjj:XXsource/rtos/PDK_Platform_Software/IPC/IPC_GateMP_Support_for_UIO_and_Misc_Driver.rst.incr*yr+y}r,ybjj>j}r-y(j@jAj]j]j]j]j]ujKjhj]r.yjXRhttp://processors.wiki.ti.com/index.php/IPC_GateMP_Support_for_UIO_and_Misc_Driverr/yr0y}r1y(jUjj(yubaubj)r2y}r3y(jUjKjjyjj+yjjj}r4y(j]r5yjaaj]j]j]r6yUid5r7yaj]ujKjhj]r8y(j)r9y}r:y(jX Introductionr;yjj2yjj+yjjj}ryr?y}r@y(jj;yjj9yubaubj)rAy}rBy(jXStarting in IPC 3.42, the GateMP module added support for accessing device memory without using /dev/mem. Instead of accessing /dev/mem, a uio driver for Shared Region 0 access and a misc driver to expose a hwspinlock user interface can be used. These drivers are added in the Android SDK and GLSDK kernels. This feature was added because in some environments, /dev/mem may not be accessible to the LAD.rCyjj2yjj+yjjj}rDy(j]j]j]j]j]ujKjhj]rEyjXStarting in IPC 3.42, the GateMP module added support for accessing device memory without using /dev/mem. Instead of accessing /dev/mem, a uio driver for Shared Region 0 access and a misc driver to expose a hwspinlock user interface can be used. These drivers are added in the Android SDK and GLSDK kernels. This feature was added because in some environments, /dev/mem may not be accessible to the LAD.rFyrGy}rHy(jjCyjjAyubaubj)rIy}rJy(jXThere is no change to how LAD is launched in this case, and if the uio and misc driver are not available in the kernel, it will fall back to using /dev/mem.jj2yjj+yjjj}rKy(j]j]j]j]j]ujNjhj]rLyj)rMy}rNy(jXThere is no change to how LAD is launched in this case, and if the uio and misc driver are not available in the kernel, it will fall back to using /dev/mem.rOyjjIyjj+yjjj}rPy(j]j]j]j]j]ujKj]rQyjXThere is no change to how LAD is launched in this case, and if the uio and misc driver are not available in the kernel, it will fall back to using /dev/mem.rRyrSy}rTy(jjOyjjMyubaubaubj)rUy}rVy(jX'This applies only to Linux/Android IPC.rWyjj2yjj+yjjj}rXy(j]j]j]j]j]ujNjhj]rYyj)rZy}r[y(jjWyjjUyjj+yjjj}r\y(j]j]j]j]j]ujKj]r]yjX'This applies only to Linux/Android IPC.r^yr_y}r`y(jjWyjjZyubaubaubeubj)ray}rby(jUjKjjyjj+yjjj}rcy(j]rdyj1aj]j]j]reyUconfigrfyaj]ujKjhj]rgy(j)rhy}riy(jXConfigrjyjjayjj+yjjj}rky(j]j]j]j]j]ujKjhj]rlyjXConfigrmyrny}roy(jjjyjjhyubaubj)rpy}rqy(jXWEnable the uio and misc drivers in the kernel by enabling the following config options:rryjjayjj+yjjj}rsy(j]j]j]j]j]ujKjhj]rtyjXWEnable the uio and misc drivers in the kernel by enabling the following config options:ruyrvy}rwy(jjryjjpyubaubj)rxy}ryy(jXCONFIG_HWSPINLOCK_USER=y CONFIG_UIO=y CONFIG_UIO_PDRV_GENIRQ=y Update your dts file to define the hwspinlocks being used by the misc driver. Must start from hwspinlock "0" and go up sequentially:rzyjjayjj+yjjj}r{y(j]j]j]j]j]ujKjhj]r|yjXCONFIG_HWSPINLOCK_USER=y CONFIG_UIO=y CONFIG_UIO_PDRV_GENIRQ=y Update your dts file to define the hwspinlocks being used by the misc driver. Must start from hwspinlock "0" and go up sequentially:r}yr~y}ry(jjzyjjxyubaubj)ry}ry(jXgatemp { compatible = "hwspinlock-user"; hwlocks = <&hwspinlock 0>, <&hwspinlock 1>, <&hwspinlock 2>, <&hwspinlock 3>, <&hwspinlock 4>, <&hwspinlock 5>, <&hwspinlock 6>, <&hwspinlock 7>, <&hwspinlock 8>, <&hwspinlock 9>; };jjayjj+yjjj}ry(j@jAj]j]j]j]j]ujMRjhj]ryjXgatemp { compatible = "hwspinlock-user"; hwlocks = <&hwspinlock 0>, <&hwspinlock 1>, <&hwspinlock 2>, <&hwspinlock 3>, <&hwspinlock 4>, <&hwspinlock 5>, <&hwspinlock 6>, <&hwspinlock 7>, <&hwspinlock 8>, <&hwspinlock 9>; };ryry}ry(jUjjyubaubj)ry}ry(jXThe hwspinlock configuration in the dts file MUST match the BIOS-side IPC HWSpinlock configuration. Configuration the BIOS-side IPC module by adding the following to your cfg file (where is equal to the number of spinlocks in the dts listing):ryjjayjj+yjjj}ry(j]j]j]j]j]ujK2jhj]ryjXThe hwspinlock configuration in the dts file MUST match the BIOS-side IPC HWSpinlock configuration. Configuration the BIOS-side IPC module by adding the following to your cfg file (where is equal to the number of spinlocks in the dts listing):ryry}ry(jjyjjyubaubj)ry}ry(jXavar HWSpinlock = xdc.useModule(‘ti.sdo.ipc.gates.GateHWSpinlock’); HWSpinlock.numLocks = ;jjayjj+yjjj}ry(j@jAj]j]j]j]j]ujMgjhj]ryjXavar HWSpinlock = xdc.useModule(‘ti.sdo.ipc.gates.GateHWSpinlock’); HWSpinlock.numLocks = ;ryry}ry(jUjjyubaubj)ry}ry(jXUpdate your dts file to add the UIO-based node for Shared Region 0 (modify address and size so that it matches the Shared Region 0 definition in the remote core image):ryjjayjj+yjjj}ry(j]j]j]j]j]ujK; };jjayjj+yjjj}ry(j@jAj]j]j]j]j]ujMrjhj]ryjXQsr0 { compatible = "generic-uio"; reg = <0xbfd00000 0x100000>; };ryry}ry(jUjjyubaubj)ry}ry(jXKernel 4.4-based releases:ryjjayjj+yjjj}ry(j]j]j]j]j]ujKIjhj]ryjXKernel 4.4-based releases:ryry}ry(jjyjjyubaubj)ry}ry(jXYsr0 { compatible = "generic-uio"; reg = <0x0 0xbfb00000 0x0 0x100000>; };jjayjj+yjjj}ry(j@jAj]j]j]j]j]ujM{jhj]ryjXYsr0 { compatible = "generic-uio"; reg = <0x0 0xbfb00000 0x0 0x100000>; };ryry}ry(jUjjyubaubj)ry}ry(jXMake sure that the "compatible" property in the sr0 dts node matches the UIO’s of_id string defined in the kernel command line.jjayjj+yjjj}ry(j]j]j]j]j]ujNjhj]ryj)ry}ry(jXMake sure that the "compatible" property in the sr0 dts node matches the UIO’s of_id string defined in the kernel command line.ryjjyjj+yjjj}ry(j]j]j]j]j]ujKSj]ryjXMake sure that the "compatible" property in the sr0 dts node matches the UIO’s of_id string defined in the kernel command line.ryry}ry(jjyjjyubaubaubj)ry}ry(jX4Append the following to the kernel's CONFIG_CMDLINE:ryjjayjj+yjjj}ry(j]j]j]j]j]ujKVjhj]ryjX4Append the following to the kernel's CONFIG_CMDLINE:ryry}ry(jjyjjyubaubj)ry}ry(jX!uio_pdrv_genirq.of_id=generic-uiojjayjj+yjjj}ry(j@jAj]j]j]j]j]ujMjhj]ryjX!uio_pdrv_genirq.of_id=generic-uioryry}ry(jUjjyubaubj)ry}ry(jX For example:ryjjayjj+yjjj}ry(j]j]j]j]j]ujK\jhj]ryjX For example:ryry}ry(jjyjjyubaubj)ry}ry(jXCONFIG_CMDLINE="root=/dev/mmcblk0p2 rw console=ttyS0,119200 androidboot.console=ttyS0 init=/init rootfstype=ext4 rootwait drm.rnodes=1 snd.slots_reserved=1,1 androidboot.selinux=permissive androidboot.hardware=jacinto6evmboard uio_pdrv_genirq.of_id=generic-uio"jjayjj+yjjj}ry(j@jAj]j]j]j]j]ujMjhj]ryjXCONFIG_CMDLINE="root=/dev/mmcblk0p2 rw console=ttyS0,119200 androidboot.console=ttyS0 init=/init rootfstype=ext4 rootwait drm.rnodes=1 snd.slots_reserved=1,1 androidboot.selinux=permissive androidboot.hardware=jacinto6evmboard uio_pdrv_genirq.of_id=generic-uio"ryry}ry(jUjjyubaubj)ry}ry(jXChanges for the command line are already present in the Android 6AM.1.0 release. For GLSDK, the command line comes from the bootargs set in the uenv.txt file in the boot partition.jjayjj+yjjj}ry(j]j]j]j]j]ujNjhj]ryj)ry}ry(jXChanges for the command line are already present in the Android 6AM.1.0 release. For GLSDK, the command line comes from the bootargs set in the uenv.txt file in the boot partition.ryjjyjj+yjjj}ry(j]j]j]j]j]ujKcj]ryjXChanges for the command line are already present in the Android 6AM.1.0 release. For GLSDK, the command line comes from the bootargs set in the uenv.txt file in the boot partition.ryry}ry(jjyjjyubaubaubj)ry}ry(jX?Also, specific owner/group must be set for the following files:ryjjayjj+yjjj}ry(j]j]j]j]j]ujKgjhj]ryjX?Also, specific owner/group must be set for the following files:ryry}ry(jjyjjyubaubjt)ry}ry(jUjjayjj+yjjwj}ry(jyX-j]j]j]j]j]ujKijhj]ry(j{)ry}ry(jX /dev/uio0rzjjyjj+yjjj}rz(j]j]j]j]j]ujNjhj]rzj)rz}rz(jjzjjyjj+yjjj}rz(j]j]j]j]j]ujKij]rzjX /dev/uio0rzrz}r z(jjzjjzubaubaubj{)r z}r z(jX/dev/hwspinlockr zjjyjj+yjjj}r z(j]j]j]j]j]ujNjhj]rzj)rz}rz(jj zjj zjj+yjjj}rz(j]j]j]j]j]ujKjj]rzjX/dev/hwspinlockrzrz}rz(jj zjjzubaubaubj{)rz}rz(jX%**Android:** /data/lad, /data/lad/LADrzjjyjj+yjjj}rz(j]j]j]j]j]ujNjhj]rzj)rz}rz(jjzjjzjj+yjjj}rz(j]j]j]j]j]ujKkj]rz(j)rz}r z(jX **Android:**j}r!z(j]j]j]j]j]ujjzj]r"zjXAndroid:r#zr$z}r%z(jUjjzubajjubjX /data/lad, /data/lad/LADr&zr'z}r(z(jX /data/lad, /data/lad/LADjjzubeubaubj{)r)z}r*z(jX**Linux:** /tmp/LAD jjyjXointernal padding after source/rtos/PDK_Platform_Software/IPC/IPC_GateMP_Support_for_UIO_and_Misc_Driver.rst.incr+zjjj}r,z(j]j]j]j]j]ujNjhj]r-zj)r.z}r/z(jX**Linux:** /tmp/LADjj)zjj+yjjj}r0z(j]j]j]j]j]ujKlj]r1z(j)r2z}r3z(jX **Linux:**j}r4z(j]j]j]j]j]ujj.zj]r5zjXLinux:r6zr7z}r8z(jUjj2zubajjubjX /tmp/LADr9zr:z}r;z(jX /tmp/LADjj.zubeubaubeubeubeubj)rz(j]j]j]j]r?zU notify-moduler@zaj]rAzhaujKKjhj]rBz(j)rCz}rDz(jX Notify ModulerEzjjj}rPz(j@jAj]j]j]j]j]ujKjhj]rQzjXEhttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/Notify_ModulerRzrSz}rTz(jUjjKzubaubj)rUz}rVz(jX.. |notCfg_Img1| Image:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.html jjjhj]r){jXA specific event may be disabled or enabled using Notify_disableEvent() and Notify_enableEvent(). All notifications on an entire interrupt line may be disabled or restored using Notify_disable() and Notify_restore() calls. Notify_disable() does not alter the state of individual events. Instead, it just disables the ability of the Notify module to receive events on the specified interrupt line.r*{r+{}r,{(jj'{jj%{ubaubj)r-{}r.{(jX`"Loopback" mode, which is enabled by default, allows notifications to be registered and sent locally. This is accomplished by supplying the processor's own MultiProc ID to Notify APIs. Line ID 0 (zero) is always used for local notifications. It is important to be aware of some subtle (but important) differences between remote and local notifications:r/{jj{(jXLoopback callback functions execute in the context of the same thread that called Notify_sendEvent(). This is in contrast to callback functions called due to another processor's sent notification--such "remote" callback functions execute in an ISR context.r?{j}r@{(j]j]j]j]j]ujj9{j]rA{j)rB{}rC{(jj?{jj={jjNzjjj}rD{(j]j]j]j]j]ujKBj]rE{jXLoopback callback functions execute in the context of the same thread that called Notify_sendEvent(). This is in contrast to callback functions called due to another processor's sent notification--such "remote" callback functions execute in an ISR context.rF{rG{}rH{(jj?{jjB{ubaubajjubj{)rI{}rJ{(jX=Loopback callback functions execute with interrupts disabled.rK{j}rL{(j]j]j]j]j]ujj9{j]rM{j)rN{}rO{(jjK{jjI{jjNzjjj}rP{(j]j]j]j]j]ujKCj]rQ{jX=Loopback callback functions execute with interrupts disabled.rR{rS{}rT{(jjK{jjN{ubaubajjubj{)rU{}rV{(jX9Disabling the local interrupt line causes all notifications that are sent to the local processor to be lost. By contrast, a notification sent to an enabled event on a remote processor that has called Notify_disableEvent() results in a pending notification until the disabled processor has called Notify_restore().rW{j}rX{(j]j]j]j]j]ujj9{j]rY{j)rZ{}r[{(jjW{jjU{jjNzjjj}r\{(j]j]j]j]j]ujKDj]r]{jX9Disabling the local interrupt line causes all notifications that are sent to the local processor to be lost. By contrast, a notification sent to an enabled event on a remote processor that has called Notify_disableEvent() results in a pending notification until the disabled processor has called Notify_restore().r^{r_{}r`{(jjW{jjZ{ubaubajjubj{)ra{}rb{(jXLocal notifications do not support events of different priorities. By contrast, Notify driver implementations may correlate event IDs with varying priorities. j}rc{(j]j]j]j]j]ujj9{j]rd{j)re{}rf{(jXLocal notifications do not support events of different priorities. By contrast, Notify driver implementations may correlate event IDs with varying priorities.rg{jja{jjNzjjj}rh{(j]j]j]j]j]ujKEj]ri{jXLocal notifications do not support events of different priorities. By contrast, Notify driver implementations may correlate event IDs with varying priorities.rj{rk{}rl{(jjg{jje{ubaubajjubejjwubaubj)rm{}rn{(jX[The Notify Module is only supported in SYS/BIOS environments. It is not provided on HLOS's.ro{jjj}r{(j@jAj]j]j]j]j]ujKjhj]r{jXKhttp://processors.wiki.ti.com/index.php/IPC_Users_Guide/SharedRegion_Moduler{r{}r{(jUjj{ubaubj)r{}r{(jX.. |srmCfg_Img1| Image:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.html jjjj{jjHj}r{(j]j]j]j]j]r{X srmCfg_Img1r{aujKjhj]r{j)r{}r{(jj{j}r{(UrefuriXhhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlr{j]j]j]j]j]ujj{j]r{jR)r{}r{(jXImage:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlr{j}r{(UuriXrtos/../images/Book_cfg.pngr{j]j]j]j]jX}r{U*j{sj]Ualtj{ujj{j]jjZubajjubaubjj)r{}r{(jX.. |srmRun_Img1| Image:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_multi_proc_8h.html jjjj{jjHj}r{(j]j]j]j]j]r{X srmRun_Img1r{aujK jhj]r{j)r{}r{(jj{j}r{(UrefuriXqhttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_multi_proc_8h.htmlr{j]j]j]j]j]ujj{j]r{jR)r{}r{(jXImage:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_multi_proc_8h.htmlr{j}r{(UuriXrtos/../images/Book_run.pngr{j]j]j]j]jX}r{U*j{sj]Ualtj{ujj{j]jjZubajjubaubj)r{}r{(jX.. |srmRun_Img2| Image:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_multi_proc_8h.html jjjj{jjHj}r{(j]j]j]j]j]r{X srmRun_Img2r{aujK jhj]r{j)r{}r{(jj{j}r{(UrefuriXqhttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_multi_proc_8h.htmlr{j]j]j]j]j]ujj{j]r{jR)r{}r{(jXImage:: ../images/Book_run.png :target: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_multi_proc_8h.htmlr{j}r{(UuriXrtos/../images/Book_run.pngr{j]j]j]j]jX}r{U*j{sj]Ualtj{ujj{j]jjZubajjubaubjc)r{}r{(jUjjjj{jjfj}r{(j]j]j]j]j]ujKjhj]r{ji)r{}r{(jUjlKjj{jj{jjj}r{(j]j]j]j]j]ujKjhj]ubaubj3)r{}r{(jUjjjj{jj6j}r{(j]j]j]j]j]ujNjhj]r{jy )r{}r{(jUj}r{(j]j]j]j]j]ujj{j]r{j~ )r{}r{(jUj}r{(j]j]j]j]j]UcolsKujj{j]r{(j )r{}r{(jUj}r{(j]j]j]j]j]UcolwidthKujj{j]jj ubj )r{}r{(jUj}r{(j]j]j]j]j]UcolwidthKujj{j]jj ubj )r{}r{(jUj}r{(j]j]j]j]j]ujj{j]r{j )r{}r{(jUj}r{(j]j]j]j]j]ujj{j]r{j )r{}r{(jUj}r{(j]UmorecolsKj]j]j]j]ujj{j]r{j)r{}r{(jXAPI Reference Linksr{jj{jj{jjj}r{(j]j]j]j]j]ujKj]r{jXAPI Reference Linksr{r{}r{(jj{jj{ubaubajj ubajj ubajj ubj )r{}r{(jUj}r{(j]j]j]j]j]ujj{j]r{j )r{}r{(jUj}r{(j]j]j]j]j]ujj{j]r{(j )r{}r{(jUj}r{(j]j]j]j]j]ujj{j]r{j)r{}r{(jX |srmCfg_Img1|r{jj{jj{jjj}r{(j]j]j]j]j]ujKj]r|j)r|}r|(jj{jj{jNjjj}r|(Urefurij{j]j]j]j]j]ujNj]r|jR)r|}r|(jj{jj|jNjjZj}r|(UuriXrtos/../images/Book_cfg.pngr|j]j]j]j]jX}r |U*j|sj]Ualtj{ujNj]ubaubaubajj ubj )r |}r |(jUj}r |(j]j]j]j]j]ujj{j]r |j)r|}r|(jX |srmRun_Img1|r|jj |jj{jjj}r|(j]j]j]j]j]ujKj]r|j)r|}r|(jj{jj|jNjjj}r|(Urefurij{j]j]j]j]j]ujNj]r|jR)r|}r|(jj{jj|jNjjZj}r|(UuriXrtos/../images/Book_run.pngr|j]j]j]j]jX}r|U*j|sj]Ualtj{ujNj]ubaubaubajj ubejj ubajj ubejj ubajj ubaubj)r|}r|(jXThe SharedRegion module is designed to be used in a multi-processor environment where there are memory regions that are shared and accessed across different processors. In an environment with shared memory regions, a common problem is that these shared regions are memory mapped to different address spaces on different processors. This is shown in the following figure. The shared memory region "DDR2" is mapped into Proc0's local memory space at base address 0x80000000 and Proc1's local memory space at base address 0x90000000. Therefore, the pointers in "DDR2" need to be translated in order for them to be portable between Proc0 and Proc1. The local memory regions for Proc0 and Proc1 are not shared thus they do not need to be added to the SharedRegion module.r|jjjj{jjj}r|(j]j]j]j]j]ujKjhj]r |jXThe SharedRegion module is designed to be used in a multi-processor environment where there are memory regions that are shared and accessed across different processors. In an environment with shared memory regions, a common problem is that these shared regions are memory mapped to different address spaces on different processors. This is shown in the following figure. The shared memory region "DDR2" is mapped into Proc0's local memory space at base address 0x80000000 and Proc1's local memory space at base address 0x90000000. Therefore, the pointers in "DDR2" need to be translated in order for them to be portable between Proc0 and Proc1. The local memory regions for Proc0 and Proc1 are not shared thus they do not need to be added to the SharedRegion module.r!|r"|}r#|(jj|jj|ubaubjR)r$|}r%|(jX).. image:: ../images/IpcUG_ipc_2_8_1.png jjjj{jjZj}r&|(UuriX"rtos/../images/IpcUG_ipc_2_8_1.pngr'|j]j]j]j]jX}r(|U*j'|sj]ujKjhj]ubj)r)|}r*|(jXlOn systems where address translation is not required, translation is a noop, so performance is not affected.r+|jjjj{jjj}r,|(j]j]j]j]j]ujKjhj]r-|jXlOn systems where address translation is not required, translation is a noop, so performance is not affected.r.|r/|}r0|(jj+|jj)|ubaubj)r1|}r2|(jXThe SharedRegion module itself does not use any shared memory, because all of its state is stored locally. The APIs use the system gate for thread protection.r3|jjjj{jjj}r4|(j]j]j]j]j]ujKjhj]r5|jXThe SharedRegion module itself does not use any shared memory, because all of its state is stored locally. The APIs use the system gate for thread protection.r6|r7|}r8|(jj3|jj1|ubaubj)r9|}r:|(jXBThis module creates a shared memory region lookup table. The lookup table contains the processor's view of every shared region in the system. In cases where a processor cannot view a certain shared memory region, that shared memory region should be left invalid for that processor. Each processor has its own lookup table.r;|jjjj{jjj}r<|(j]j]j]j]j]ujK!jhj]r=|jXBThis module creates a shared memory region lookup table. The lookup table contains the processor's view of every shared region in the system. In cases where a processor cannot view a certain shared memory region, that shared memory region should be left invalid for that processor. Each processor has its own lookup table.r>|r?|}r@|(jj;|jj9|ubaubj)rA|}rB|(jXEach processor's view of a particular shared memory region can be determined by the same region ID across all lookup tables. At runtime, this table, along with the shared region pointer, is used to do a quick address translation.rC|jjjj{jjj}rD|(j]j]j]j]j]ujK#jhj]rE|jXEach processor's view of a particular shared memory region can be determined by the same region ID across all lookup tables. At runtime, this table, along with the shared region pointer, is used to do a quick address translation.rF|rG|}rH|(jjC|jjA|ubaubj)rI|}rJ|(jXMThe lookup table contains the following information about each shared region:rK|jjjj{jjj}rL|(j]j]j]j]j]ujK%jhj]rM|jXMThe lookup table contains the following information about each shared region:rN|rO|}rP|(jjK|jjI|ubaubj3)rQ|}rR|(jUjjjNjj6j}rS|(j]j]j]j]j]ujNjhj]rT|jt)rU|}rV|(jUj}rW|(jyX-j]j]j]j]j]ujjQ|j]rX|(j{)rY|}rZ|(jX{base. The base address of the region. This may be different on different processors, depending on their addressing schemes.r[|j}r\|(j]j]j]j]j]ujjU|j]r]|j)r^|}r_|(jj[|jjY|jj{jjj}r`|(j]j]j]j]j]ujK'j]ra|jX{base. The base address of the region. This may be different on different processors, depending on their addressing schemes.rb|rc|}rd|(jj[|jj^|ubaubajjubj{)re|}rf|(jXWlen. The length of the region. This should be should be the same across all processors.rg|j}rh|(j]j]j]j]j]ujjU|j]ri|j)rj|}rk|(jjg|jje|jj{jjj}rl|(j]j]j]j]j]ujK(j]rm|jXWlen. The length of the region. This should be should be the same across all processors.rn|ro|}rp|(jjg|jjj|ubaubajjubj{)rq|}rr|(jXownerProcId. MultiProc ID of the processor that manages this region. If an owner is specified, the owner creates a HeapMemMP instance at runtime. The other cores open the same HeapMemMP instance.rs|j}rt|(j]j]j]j]j]ujjU|j]ru|j)rv|}rw|(jjs|jjq|jj{jjj}rx|(j]j]j]j]j]ujK)j]ry|jXownerProcId. MultiProc ID of the processor that manages this region. If an owner is specified, the owner creates a HeapMemMP instance at runtime. The other cores open the same HeapMemMP instance.rz|r{|}r||(jjs|jjv|ubaubajjubj{)r}|}r~|(jX^isValid. Boolean to specify whether the region is valid (accessible) or not on this processor.r|j}r|(j]j]j]j]j]ujjU|j]r|j)r|}r|(jj|jj}|jj{jjj}r|(j]j]j]j]j]ujK*j]r|jX^isValid. Boolean to specify whether the region is valid (accessible) or not on this processor.r|r|}r|(jj|jj|ubaubajjubj{)r|}r|(jXacacheEnable. Boolean to specify whether a cache is enabled for the region on the local processor.r|j}r|(j]j]j]j]j]ujjU|j]r|j)r|}r|(jj|jj|jj{jjj}r|(j]j]j]j]j]ujK+j]r|jXacacheEnable. Boolean to specify whether a cache is enabled for the region on the local processor.r|r|}r|(jj|jj|ubaubajjubj{)r|}r|(jX}cacheLineSize. The cache line size for the region. It is crucial that the value specified here be the same on all processors.r|j}r|(j]j]j]j]j]ujjU|j]r|j)r|}r|(jj|jj|jj{jjj}r|(j]j]j]j]j]ujK,j]r|jX}cacheLineSize. The cache line size for the region. It is crucial that the value specified here be the same on all processors.r|r|}r|(jj|jj|ubaubajjubj{)r|}r|(jXCcreateHeap. Boolean to specify if a heap is created for the region.r|j}r|(j]j]j]j]j]ujjU|j]r|j)r|}r|(jj|jj|jj{jjj}r|(j]j]j]j]j]ujK-j]r|jXCcreateHeap. Boolean to specify if a heap is created for the region.r|r|}r|(jj|jj|ubaubajjubj{)r|}r|(jX+name. The name associated with the region. j}r|(j]j]j]j]j]ujjU|j]r|j)r|}r|(jX*name. The name associated with the region.r|jj|jj{jjj}r|(j]j]j]j]j]ujK.j]r|jX*name. The name associated with the region.r|r|}r|(jj|jj|ubaubajjubejjwubaubj)r|}r|(jX The maximum number of entries in the lookup table is statically configurable using the SharedRegion.numEntries property. Entries can be added during static configuration or at runtime. When you add or remove an entry in one processor's table, you must update all of the remaining processors' tables to keep them consistent. The larger the maximum number of entries, the longer it will take to traverse the lookup table when searching for the index. Therefore, keep the lookup table small for better performance and footprint.r|jjjj{jjj}r|(j]j]j]j]j]ujK0jhj]r|jX The maximum number of entries in the lookup table is statically configurable using the SharedRegion.numEntries property. Entries can be added during static configuration or at runtime. When you add or remove an entry in one processor's table, you must update all of the remaining processors' tables to keep them consistent. The larger the maximum number of entries, the longer it will take to traverse the lookup table when searching for the index. Therefore, keep the lookup table small for better performance and footprint.r|r|}r|(jj|jj|ubaubj)r|}r|(jXBecause each processor stores information about the caching of a shared memory region in the SharedRegion lookup table, other modules can (and do) make use of this caching information to maintain coherency and alignment when using items stored in shared memory.r|jjjj{jjj}r|(j]j]j]j]j]ujK2jhj]r|jXBecause each processor stores information about the caching of a shared memory region in the SharedRegion lookup table, other modules can (and do) make use of this caching information to maintain coherency and alignment when using items stored in shared memory.r|r|}r|(jj|jj|ubaubj)r|}r|(jXDIn order to use the SharedRegion module, the following must be true:r|jjjj{jjj}r|(j]j]j]j]j]ujK4jhj]r|jXDIn order to use the SharedRegion module, the following must be true:r|r|}r|(jj|jj|ubaubj3)r|}r|(jUjjjNjj6j}r|(j]j]j]j]j]ujNjhj]r|jt)r|}r|(jUj}r|(jyX-j]j]j]j]j]ujj|j]r|(j{)r|}r|(jXHThe SharedRegion.numEntries property must be the same on all processors.r|j}r|(j]j]j]j]j]ujj|j]r|j)r|}r|(jj|jj|jj{jjj}r|(j]j]j]j]j]ujK6j]r|jXHThe SharedRegion.numEntries property must be the same on all processors.r|r|}r|(jj|jj|ubaubajjubj{)r|}r|(jX3The size of a SharedRegion pointer is 32-bits wide.r|j}r|(j]j]j]j]j]ujj|j]r|j)r|}r|(jj|jj|jj{jjj}r|(j]j]j]j]j]ujK7j]r|jX3The size of a SharedRegion pointer is 32-bits wide.r|r|}r|(jj|jj|ubaubajjubj{)r|}r|(jX]The SharedRegion lookup table must contain at least 1 entry for address translation to occur.r|j}r|(j]j]j]j]j]ujj|j]r|j)r|}r|(jj|jj|jj{jjj}r|(j]j]j]j]j]ujK8j]r|jX]The SharedRegion lookup table must contain at least 1 entry for address translation to occur.r|r|}r|(jj|jj|ubaubajjubj{)r|}r|(jXVShared memory regions must not overlap each other from a single processor's viewpoint.r|j}r}(j]j]j]j]j]ujj|j]r}j)r}}r}(jj|jj|jj{jjj}r}(j]j]j]j]j]ujK9j]r}jXVShared memory regions must not overlap each other from a single processor's viewpoint.r}r}}r}(jj|jj}ubaubajjubj{)r }}r }(jXCRegions are not allowed to overlap from a single processor's view. j}r }(j]j]j]j]j]ujj|j]r }j)r }}r}(jXBRegions are not allowed to overlap from a single processor's view.r}jj }jj{jjj}r}(j]j]j]j]j]ujK:j]r}jXBRegions are not allowed to overlap from a single processor's view.r}r}}r}(jj}jj }ubaubajjubejjwubaubj)r}}r}(jX+The SharedRegion with an index of 0 (zero) is used by IPC_start() to create resource management tables for internal use by other IPC modules. Thus SharedRegion "0" must be accessible by all processors. Your applications can also make use of SharedRegion "0", but must be aware of memory limitations.r}jjjj{jjj}r}(j]j]j]j]j]ujK}}r?}(jj:}jj8}ubaubj)r@}}rA}(jX For example:rB}jj}jj{jjj}rC}(j]j]j]j]j]ujKEjhj]rD}jX For example:rE}rF}}rG}(jjB}jj@}ubaubj)rH}}rI}(jXvar SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion'); SharedRegion.cacheLineSize = 32; SharedRegion.numEntries = 4; SharedRegion.translate = true;jj}jj{jjj}rJ}(j@jAj]j]j]j]j]ujM< jhj]rK}jXvar SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion'); SharedRegion.cacheLineSize = 32; SharedRegion.numEntries = 4; SharedRegion.translate = true;rL}rM}}rN}(jUjjH}ubaubj)rO}}rP}(jXrThen, use the SharedRegion.setEntryMeta() method in the configuration file to specify the parameters of the entry.rQ}jj}jj{jjj}rR}(j]j]j]j]j]ujKNjhj]rS}jXrThen, use the SharedRegion.setEntryMeta() method in the configuration file to specify the parameters of the entry.rT}rU}}rV}(jjQ}jjO}ubaubj)rW}}rX}(jX,var SHAREDMEM = 0x0C000000; var SHAREDMEMSIZE = 0x00200000; SharedRegion.setEntryMeta(0, { base: SHAREDMEM, len: SHAREDMEMSIZE, ownerProcId: 0, isValid: true, cacheEnable: true, cacheLineSize: 128, createHeap: true, name: "internal_shared_mem" });jj}jj{jjj}rY}(j@jAj]j]j]j]j]ujME jhj]rZ}jX,var SHAREDMEM = 0x0C000000; var SHAREDMEMSIZE = 0x00200000; SharedRegion.setEntryMeta(0, { base: SHAREDMEM, len: SHAREDMEMSIZE, ownerProcId: 0, isValid: true, cacheEnable: true, cacheLineSize: 128, createHeap: true, name: "internal_shared_mem" });r[}r\}}r]}(jUjjW}ubaubj)r^}}r_}(jXIf, during static configuration, you don't know the base address for every processor, you should set the "isValid" field for an entry for which you don't yet know the base address to "false". Storing this information will allow it to be completed at runtime.r`}jj}jj{jjj}ra}(j]j]j]j]j]ujK`jhj]rb}jXIf, during static configuration, you don't know the base address for every processor, you should set the "isValid" field for an entry for which you don't yet know the base address to "false". Storing this information will allow it to be completed at runtime.rc}rd}}re}(jj`}jj^}ubaubj)rf}}rg}(jXThe following figure shows the configuration of a SharedRegion table for the system in the following figure. This system has seven processors and two shared memory regions. Region 0 ("ext") is accessible by all processors. Region 1 ("local") is accessible only by processors 1 to 6.rh}jj}jj{jjj}ri}(j]j]j]j]j]ujKbjhj]rj}jXThe following figure shows the configuration of a SharedRegion table for the system in the following figure. This system has seven processors and two shared memory regions. Region 0 ("ext") is accessible by all processors. Region 1 ("local") is accessible only by processors 1 to 6.rk}rl}}rm}(jjh}jjf}ubaubjR)rn}}ro}(jX).. image:: ../images/IpcUG_ipc_2_8_2.png jj}jj{jjZj}rp}(UuriX"rtos/../images/IpcUG_ipc_2_8_2.pngrq}j]j]j]j]jX}rr}U*jq}sj]ujKejhj]ubj)rs}}rt}(jXbIf the "createHeap" field is set to true, a HeapMemMP instance is created within the SharedRegion.ru}jj}jj{jjj}rv}(j]j]j]j]j]ujKfjhj]rw}jXbIf the "createHeap" field is set to true, a HeapMemMP instance is created within the SharedRegion.rx}ry}}rz}(jju}jjs}ubaubj)r{}}r|}(jX|srmCfg_Img2| The latest version of the SharedRegion module configuration documentation is available `online `__.jj}jj{jjj}r}}(j]j]j]j]j]ujKhjhj]r~}(j)r}}r}(jjjj{}jNjjj}r}(UrefuriXhhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlr}j]j]j]j]j]ujNjhj]r}jR)r}}r}(jXImage:: ../images/Book_cfg.png :target: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/indexChrome.htmlr}jj}jNjjZj}r}(UuriXrtos/../images/Book_cfg.pngr}j]j]j]j]jX}r}U*j}sj]UaltjujNj]ubaubjXX The latest version of the SharedRegion module configuration documentation is available r}r}}r}(jXX The latest version of the SharedRegion module configuration documentation is available jj{}ubj)r}}r}(jX`online `__j}r}(UnameXonlinejXhttp://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/index.html#ti/sdo/ipc/SharedRegion.htmlj]j]j]j]j]ujj{}j]r}jXonliner}r}}r}(jUjj}ubajjubjX.r}}r}(jX.jj{}ubeubeubj)r}}r}(jUjjjj{jjj}r}(j]j]j]j]r}U#modifying-table-entries-dynamicallyr}aj]r}haujKljhj]r}(j)r}}r}(jX#Modifying Table Entries Dynamicallyr}jj}jj{jjj}r}(j]j]j]j]j]ujKljhj]r}jX#Modifying Table Entries Dynamicallyr}r}}r}(jj}jj}ubaubj)r}}r}(jXIn the application's C code, a shared memory region can be modified in the SharedRegion table by calling SharedRegion_setEntry().r}jj}jj{jjj}r}(j]j]j]j]j]ujKnjhj]r}jXIn the application's C code, a shared memory region can be modified in the SharedRegion table by calling SharedRegion_setEntry().r}r}}r}(jj}jj}ubaubj)r}}r}(jXTypically, applications configure SharedRegion table entries statically as described in the previous section, and only modify the table entries dynamically in applications where it is possible for shared memory region availability to change dynamically.r}jj}jj{jjj}r}(j]j]j]j]j]ujKpjhj]r}jXTypically, applications configure SharedRegion table entries statically as described in the previous section, and only modify the table entries dynamically in applications where it is possible for shared memory region availability to change dynamically.r}r}}r}(jj}jj}ubaubj)r}}r}(jX)The call to SharedRegion_setEntry() must specify all the fields in the SharedRegion_Entry structure. The index specified must be the same across all processors for the same shared memory region. The index also must be smaller than the maxNumEntries property, otherwise an assert will be triggered.r}jj}jj{jjj}r}(j]j]j]j]j]ujKrjhj]r}jX)The call to SharedRegion_setEntry() must specify all the fields in the SharedRegion_Entry structure. The index specified must be the same across all processors for the same shared memory region. The index also must be smaller than the maxNumEntries property, otherwise an assert will be triggered.r}r}}r}(jj}jj}ubaubj)r}}r}(jXtypedef struct SharedRegion_Entry { Ptr base; SizeT len; UInt16 ownerProcId; Bool isValid; Bool cacheEnable; SizeT cacheLineSize; Bool createHeap; String name; } SharedRegion_Entry;jj}jj{jjj}r}(j@jAj]j]j]j]j]ujMi jhj]r}jXtypedef struct SharedRegion_Entry { Ptr base; SizeT len; UInt16 ownerProcId; Bool isValid; Bool cacheEnable; SizeT cacheLineSize; Bool createHeap; String name; } SharedRegion_Entry;r}r}}r}(jUjj}ubaubj)r}}r}(jXYou can use SharedRegion_getEntry() to fill the fields in a SharedRegion_Entry structure. Then, you can modify fields in the structure and call SharedRegion_setEntry() to write the modified fields back to the SharedRegion table.r}jj}jj{jjj}r}(j]j]j]j]j]ujKjhj]r}jXYou can use SharedRegion_getEntry() to fill the fields in a SharedRegion_Entry structure. Then, you can modify fields in the structure and call SharedRegion_setEntry() to write the modified fields back to the SharedRegion table.r}r}}r}(jj}jj}ubaubj)r}}r}(jXIf you want to reuse an index location in the SharedRegion table, you can call SharedRegion_clear() on all processors to erase the existing entry at that index location.r}jj}jj{jjj}r}(j]j]j]j]j]ujKjhj]r}jXIf you want to reuse an index location in the SharedRegion table, you can call SharedRegion_clear() on all processors to erase the existing entry at that index location.r}r}}r}(jj}jj}ubaubj)r}}r}(jX|srmRun_Img2| The latest version of the SharedRegion module run-time API documentation is available `online `__.jj}jj{jjj}r}(j]j]j]j]j]ujKjhj]r}(j)r}}r}(jj{jj}jNjjj}r}(Urefurij{j]j]j]j]j]ujNjhj]r}jR)r}}r}(jj{jj}jNjjZj}r}(UuriXrtos/../images/Book_run.pngr}j]j]j]j]jX}r}U*j}sj]Ualtj{ujNj]ubaubjXW The latest version of the SharedRegion module run-time API documentation is available r}r}}r}(jXW The latest version of the SharedRegion module run-time API documentation is available jj}ubj)r}}r}(jX`online `__j}r}(UnameXonlinejXthttp://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/doxygen/html/_shared_region_8h.htmlj]j]j]j]j]ujj}j]r}jXonliner}r}}r}(jUjj}ubajjubjX.r}}r}(jX.jj}ubeubeubj)r}}r}(jUjjjj{jjj}r}(j]j]j]j]r}Uusing-memory-in-a-shared-regionr}aj]r}haujKjhj]r}(j)r}}r}(jXUsing Memory in a Shared Regionr}jj}jj{jjj}r}(j]j]j]j]j]ujKjhj]r}jXUsing Memory in a Shared Regionr}r}}r}(jj}jj}ubaubj)r}}r}(jXNote that the SharedRegion with an index of 0 (zero) is used by IPC_start() to create resource management tables for internal use by the GateMP, NameServer, and Notify modules. Thus SharedRegion "0" must be accessible by all processors.r}jj}jj{jjj}r}(j]j]j]j]j]ujKjhj]r~jXNote that the SharedRegion with an index of 0 (zero) is used by IPC_start() to create resource management tables for internal use by the GateMP, NameServer, and Notify modules. Thus SharedRegion "0" must be accessible by all processors.r~r~}r~(jj}jj}ubaubj)r~}r~(jX2This example allocates memory from a SharedRegion:r~jj}jj{jjj}r~(j]j]j]j]j]ujKjhj]r~jX2This example allocates memory from a SharedRegion:r ~r ~}r ~(jj~jj~ubaubj)r ~}r ~(jXObuf = Memory_alloc(SharedRegion_getHeap(0), sizeof(Tester) * COUNT, 128, NULL);jj}jj{jjj}r~(j@jAj]j]j]j]j]ujM jhj]r~jXObuf = Memory_alloc(SharedRegion_getHeap(0), sizeof(Tester) * COUNT, 128, NULL);r~r~}r~(jUjj ~ubaubeubj)r~}r~(jUjjjj{jjj}r~(j]j]j]j]r~U)getting-information-about-a-shared-regionr~aj]r~haujKjhj]r~(j)r~}r~(jX)Getting Information About a Shared Regionr~jj~jj{jjj}r~(j]j]j]j]j]ujKjhj]r~jX)Getting Information About a Shared Regionr~r ~}r!~(jj~jj~ubaubj)r"~}r#~(jXThe shared region pointer (SRPtr) is a 32-bit portable pointer composed of an ID and offset. The most significant bits of a SRPtr are used for the ID. The ID corresponds to the index of the entry in the lookup table. The offset is the offset from the base of the shared memory region. The maximum number of table entries in the lookup table determines the number of bits to be used for the ID. An increase in the id means the range of the offset would decrease. The ID is limited to 16-bits.r$~jj~jj{jjj}r%~(j]j]j]j]j]ujKjhj]r&~jXThe shared region pointer (SRPtr) is a 32-bit portable pointer composed of an ID and offset. The most significant bits of a SRPtr are used for the ID. The ID corresponds to the index of the entry in the lookup table. The offset is the offset from the base of the shared memory region. The maximum number of table entries in the lookup table determines the number of bits to be used for the ID. An increase in the id means the range of the offset would decrease. The ID is limited to 16-bits.r'~r(~}r)~(jj$~jj"~ubaubj)r*~}r+~(jXYHere is sample code for getting the SRPtr and then getting the real address pointer back.r,~jj~jj{jjj}r-~(j]j]j]j]j]ujKjhj]r.~jXYHere is sample code for getting the SRPtr and then getting the real address pointer back.r/~r0~}r1~(jj,~jj*~ubaubj)r2~}r3~(jX$SharedRegion_SRPtr srptr; UInt16 id;r4~jj~jj{jjj}r5~(j]j]j]j]j]ujKjhj]r6~jX$SharedRegion_SRPtr srptr; UInt16 id;r7~r8~}r9~(jj4~jj2~ubaubj)r:~}r;~(jX // Get the id of the address if id is not already known. id = SharedRegion_getId(addr); // Get the shared region pointer for the address srptr = SharedRegion_getSRPtr(addr, id); // Get the address back from the shared region pointer addr = SharedRegion_getPtr(srptr);jj~jj{jjj}r<~(j@jAj]j]j]j]j]ujM jhj]r=~jX // Get the id of the address if id is not already known. id = SharedRegion_getId(addr); // Get the shared region pointer for the address srptr = SharedRegion_getSRPtr(addr, id); // Get the address back from the shared region pointer addr = SharedRegion_getPtr(srptr);r>~r?~}r@~(jUjj:~ubaubj)rA~}rB~(jXIn addition, you can use the SharedRegion_getIdByName() function to pass the name of a SharedRegion and receive the ID number of the region.rC~jj~jj{jjj}rD~(j]j]j]j]j]ujKjhj]rE~jXIn addition, you can use the SharedRegion_getIdByName() function to pass the name of a SharedRegion and receive the ID number of the region.rF~rG~}rH~(jjC~jjA~ubaubj)rI~}rJ~(jXjYou can use SharedRegion_getHeap() to get a handle to the heap associated with a region using the heap ID.rK~jj~jj{jjj}rL~(j]j]j]j]j]ujKjhj]rM~jXjYou can use SharedRegion_getHeap() to get a handle to the heap associated with a region using the heap ID.rN~rO~}rP~(jjK~jjI~ubaubj)rQ~}rR~(jXYou can retrieve a specific shared region's cache configuration from the SharedRegion table by using SharedRegion_isCacheEnabled() and SharedRegion_getCacheLineSize().rS~jj~jj{jjj}rT~(j]j]j]j]j]ujKjhj]rU~jXYou can retrieve a specific shared region's cache configuration from the SharedRegion table by using SharedRegion_isCacheEnabled() and SharedRegion_getCacheLineSize().rV~rW~}rX~(jjS~jjQ~ubaubj)rY~}rZ~(jXHThe SharedRegion Module is only supported in SYS/BIOS environments. It is not provided on HLOS's. For HLOS environments, we suggest using native shared memory APIs when available, for example ION on Android. Other alternatives include CMEM (for Linux) and the QNX-specific SharedMemoryAlloctor, provided in IPC's qnx/ directory.r[~jj~jj{jjj}r\~(j]j]j]j]j]ujNjhj]r]~j)r^~}r_~(jj[~jjY~jj{jjj}r`~(j]j]j]j]j]ujKj]ra~jXHThe SharedRegion Module is only supported in SYS/BIOS environments. It is not provided on HLOS's. For HLOS environments, we suggest using native shared memory APIs when available, for example ION on Android. Other alternatives include CMEM (for Linux) and the QNX-specific SharedMemoryAlloctor, provided in IPC's qnx/ directory.rb~rc~}rd~(jj[~jj^~ubaubaubeubeubjj{jjHj}re~(j]j]j]j]j]rf~jaujKjhj]rg~j)rh~}ri~(jjj}rj~(Urefurij}j]j]j]j]j]ujjj]rk~jR)rl~}rm~(jj}j}rn~(UuriXrtos/../images/Book_cfg.pngro~j]j]j]j]jX}rp~U*jo~sj]Ualtjujjh~j]jjZubajjubaubj j j_j[jmrjirj~rjzrjKjFj\rjXrj; j7 jrjrjrjrjrjrjMpjIpjYvjUvjHvjDvjjzjfzj j ja j] jjX/Duplicate implicit target name: "introduction".r?r@}rA(jUjj;ubajjubaubjs~)rB}rC(jUjj jj jjv~j}rD(j]UlevelKj]j]rEj aUsourcej j]j]UlineKUtypej~ujKjhj]rFj)rG}rH(jX/Duplicate implicit target name: "introduction".j}rI(j]j]j]j]j]ujjBj]rJjX/Duplicate implicit target name: "introduction".rKrL}rM(jUjjGubajjubaubjs~)rN}rO(jUjj jj jjv~j}rP(j]UlevelKj]rQj aj]rRj aUsourcej j]j]UlineKUtypejx~ujKjhj]rSj)rT}rU(jX0Inline emphasis start-string without end-string.j}rV(j]j]j]j]j]ujjNj]rWjX0Inline emphasis start-string without end-string.rXrY}rZ(jUjjTubajjubaubjs~)r[}r\(jUjjjjjjv~j}r](j]UlevelKj]j]r^jNaUsourcejj]j]UlineKUtypejx~ujKMjhj]r_j)r`}ra(jX)Duplicate explicit target name: "online".j}rb(j]j]j]j]j]ujj[j]rcjX)Duplicate explicit target name: "online".rdre}rf(jUjj`ubajjubaubjs~)rg}rh(jUjjRjjjjv~j}ri(j]UlevelKj]j]rjjaUsourcejj]j]UlineKUtypejx~ujKsjhj]rkj)rl}rm(jX)Duplicate explicit target name: "online".j}rn(j]j]j]j]j]ujjgj]rojX)Duplicate explicit target name: "online".rprq}rr(jUjjlubajjubaubjs~)rs}rt(jUjjjjjjv~j}ru(j]UlevelKj]j]Usourcejj]j]UlineM(Utypej~ujM*jhj]rvj)rw}rx(jX`Possible incomplete section title. Treating the overline as ordinary text because it's so short.j}ry(j]j]j]j]j]ujjsj]rzjX`Possible incomplete section title. Treating the overline as ordinary text because it's so short.r{r|}r}(jUjjwubajjubaubjs~)r~}r(jUj}r(j]UlevelKj]j]Usourcejj]j]UlineM,Utypej~ujjj]rj)r}r(jX`Blank line missing before literal block (after the "::")? Interpreted as a definition list item.j}r(j]j]j]j]j]ujj~j]rjX`Blank line missing before literal block (after the "::")? Interpreted as a definition list item.rr}r(jUjjubajjubajjv~ubjs~)r}r(jUjjQjjNjjv~j}r(j]UlevelKj]j]UsourcejNj]j]UlineKUtypej~ujKjhj]rj)r}r(jXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.j}r(j]j]j]j]j]ujjj]rjXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rr}r(jUjjubajjubaubjs~)r}r(jUjjQjjNjjv~j}r(j]UlevelKj]j]UsourcejNj]j]UlineKUtypej~ujKjhj]rj)r}r(jXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.j}r(j]j]j]j]j]ujjj]rjXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rr}r(jUjjubajjubaubjs~)r}r(jUjjQjjNjjv~j}r(j]UlevelKj]j]UsourcejNj]j]UlineK&Utypej~ujK&jhj]rj)r}r(jXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.j}r(j]j]j]j]j]ujjj]rjXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rr}r(jUjjubajjubaubjs~)r}r(jUjjQjjNjjv~j}r(j]UlevelKj]j]UsourcejNj]j]UlineK-Utypej~ujK-jhj]rj)r}r(jXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.j}r(j]j]j]j]j]ujjj]rjXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rr}r(jUjjubajjubaubjs~)r}r(jUjjjjjjv~j}r(j]UlevelKj]j]rjaUsourcejj]j]UlineKUtypej~ujKjhj]rj)r}r(jX/Duplicate implicit target name: "introduction".j}r(j]j]j]j]j]ujjj]rjX/Duplicate implicit target name: "introduction".rr}r(jUjjubajjubaubjs~)r}r(jUjjjjjjv~j}r(j]UlevelKj]j]rjaUsourcejj]j]UlineKUtypej~ujKjhj]rj)r}r(jX:Duplicate implicit target name: "transport configuration".j}r(j]j]j]j]j]ujjj]rjX:Duplicate implicit target name: "transport configuration".rr}r(jUjjubajjubaubjs~)r}r(jUjjjjjjv~j}r(j]UlevelKj]j]rjaUsourcejj]j]UlineKUtypej~ujKjhj]rj)r}r(jX=Duplicate implicit target name: "sys/bios dsp transportsrio".j}r(j]j]j]j]j]ujjj]rjX=Duplicate implicit target name: "sys/bios dsp transportsrio".rr}r(jUjjubajjubaubjs~)r}r(jUjjjjjjv~j}r(j]UlevelKj]j]rjaUsourcejj]j]UlineMUtypej~ujMjhj]rj)r}r(jX:Duplicate implicit target name: "arm linux transportsrio".j}r(j]j]j]j]j]ujjj]rjX:Duplicate implicit target name: "arm linux transportsrio".rr}r(jUjjubajjubaubjs~)r}r(jUjjjjjjv~j}r(j]UlevelKj]j]rj aUsourcejj]j]UlineMUtypej~ujMjhj]rj)r}r(jXEDuplicate implicit target name: "srio serdes and lane configuration".j}r(j]j]j]j]j]ujjj]rjXEDuplicate implicit target name: "srio serdes and lane configuration".rr}r(jUjjubajjubaubjs~)r}r(jUjjB jjjjv~j}r(j]UlevelKj]j]rjG aUsourcejj]j]UlineM%Utypej~ujM%jhj]rj)r}r(jX'Duplicate implicit target name: "apis".j}r(j]j]j]j]j]ujjj]rjX'Duplicate implicit target name: "apis".rr}r(jUjjubajjubaubjs~)r}r(jUjj` jjjjv~j}r(j]UlevelKj]j]rje aUsourcejj]j]UlineM/Utypej~ujM/jhj]rj)r}r(jX=Duplicate implicit target name: "sys/bios dsp transportqmss".j}r(j]j]j]j]j]ujjj]rjX=Duplicate implicit target name: "sys/bios dsp transportqmss".rr}r(jUjjubajjubaubjs~)r }r (jUjjo jjjjv~j}r (j]UlevelKj]j]r ju aUsourcejj]j]UlineM2Utypej~ujM2jhj]r j)r}r(jX'Duplicate implicit target name: "apis".j}r(j]j]j]j]j]ujj j]rjX'Duplicate implicit target name: "apis".rr}r(jUjjubajjubaubjs~)r}r(jUjj jjjjv~j}r(j]UlevelKj]j]rj aUsourcejj]j]UlineM;Utypej~ujM;jhj]rj)r}r(jX:Duplicate implicit target name: "arm linux transportqmss".j}r(j]j]j]j]j]ujjj]rjX:Duplicate implicit target name: "arm linux transportqmss".rr}r (jUjjubajjubaubjs~)r!}r"(jUjj jjjjv~j}r#(j]UlevelKj]j]r$j aUsourcejj]j]UlineMJUtypej~ujMJjhj]r%j)r&}r'(jX'Duplicate implicit target name: "apis".j}r((j]j]j]j]j]ujj!j]r)jX'Duplicate implicit target name: "apis".r*r+}r,(jUjj&ubajjubaubjs~)r-}r.(jUjj jjjjv~j}r/(j]UlevelKj]j]r0j aUsourcejj]j]UlineMWUtypej~ujMWjhj]r1j)r2}r3(jX=Duplicate implicit target name: "sys/bios dsp transportsrio".j}r4(j]j]j]j]j]ujj-j]r5jX=Duplicate implicit target name: "sys/bios dsp transportsrio".r6r7}r8(jUjj2ubajjubaubjs~)r9}r:(jUjj"jjjjv~j}r;(j]UlevelKj]j]r<j"aUsourcejj]j]UlineMUtypej~ujMjhj]r=j)r>}r?(jX9Duplicate implicit target name: "recompiling on windows".j}r@(j]j]j]j]j]ujj9j]rAjX9Duplicate implicit target name: "recompiling on windows".rBrC}rD(jUjj>ubajjubaubjs~)rE}rF(jUjj##jjjjv~j}rG(j]UlevelKj]j]rHj(#aUsourcejj]j]UlineMUtypej~ujMjhj]rIj)rJ}rK(jX7Duplicate implicit target name: "recompiling on linux".j}rL(j]j]j]j]j]ujjEj]rMjX7Duplicate implicit target name: "recompiling on linux".rNrO}rP(jUjjJubajjubaubjs~)rQ}rR(jUjj#jjjjv~j}rS(j]UlevelKj]j]rTj#aUsourcejj]j]UlineMUtypej~ujMjhj]rUj)rV}rW(jXDDuplicate implicit target name: "recompiling through yocto/bitbake".j}rX(j]j]j]j]j]ujjQj]rYjXDDuplicate implicit target name: "recompiling through yocto/bitbake".rZr[}r\(jUjjVubajjubaubjs~)r]}r^(jUjj#jjjjv~j}r_(j]UlevelKj]j]r`j#aUsourcejj]j]UlineM(Utypej~ujM(jhj]raj)rb}rc(jXEDuplicate implicit target name: "recompiling through git repository".j}rd(j]j]j]j]j]ujj]j]rejXEDuplicate implicit target name: "recompiling through git repository".rfrg}rh(jUjjbubajjubaubjs~)ri}rj(jUjj$jjjjv~j}rk(j]UlevelKj]j]rlj$aUsourcejj]j]UlineMSUtypej~ujMSjhj]rmj)rn}ro(jX=Duplicate implicit target name: "sys/bios dsp transportsrio".j}rp(j]j]j]j]j]ujjij]rqjX=Duplicate implicit target name: "sys/bios dsp transportsrio".rrrs}rt(jUjjnubajjubaubjs~)ru}rv(jUjjC%jjjjv~j}rw(j]UlevelKj]j]rxjI%aUsourcejj]j]UlineMwUtypej~ujMwjhj]ryj)rz}r{(jX:Duplicate implicit target name: "arm linux transportsrio".j}r|(j]j]j]j]j]ujjuj]r}jX:Duplicate implicit target name: "arm linux transportsrio".r~r}r(jUjjzubajjubaubjs~)r}r(jUjj%jjjjv~j}r(j]UlevelKj]j]rj%aUsourcejj]j]UlineMUtypej~ujMjhj]rj)r}r(jX=Duplicate implicit target name: "sys/bios dsp transportqmss".j}r(j]j]j]j]j]ujjj]rjX=Duplicate implicit target name: "sys/bios dsp transportqmss".rr}r(jUjjubajjubaubjs~)r}r(jUjjm&jjjjv~j}r(j]UlevelKj]j]rjs&aUsourcejj]j]UlineMUtypej~ujMjhj]rj)r}r(jX:Duplicate implicit target name: "arm linux transportqmss".j}r(j]j]j]j]j]ujjj]rjX:Duplicate implicit target name: "arm linux transportqmss".rr}r(jUjjubajjubaubjs~)r}r(jUjj(jj'jjv~j}r(j]UlevelKj]j]rj(aUsourcej'j]j]UlineK Utypej~ujK jhj]rj)r}r(jX(Duplicate implicit target name: "build".j}r(j]j]j]j]j]ujjj]rjX(Duplicate implicit target name: "build".rr}r(jUjjubajjubaubjs~)r}r(jUjj-(jj'jjv~j}r(j]UlevelKj]j]Usourcej'j]j]UlineK=Utypej~ujK?jhj]rj)r}r(jX`Possible incomplete section title. Treating the overline as ordinary text because it's so short.j}r(j]j]j]j]j]ujjj]rjX`Possible incomplete section title. Treating the overline as ordinary text because it's so short.rr}r(jUjjubajjubaubjs~)r}r(jUj}r(j]UlevelKj]j]Usourcej'j]j]UlineK@Utypej~ujj(j]rj)r}r(jX`Blank line missing before literal block (after the "::")? Interpreted as a definition list item.j}r(j]j]j]j]j]ujjj]rjX`Blank line missing before literal block (after the "::")? Interpreted as a definition list item.rr}r(jUjjubajjubajjv~ubjs~)r}r(jUjjE)jj'jjv~j}r(j]UlevelKj]j]rjK)aUsourcej'j]j]UlineKUtypej~ujKjhj]rj)r}r(jX(Duplicate implicit target name: "build".j}r€(j]j]j]j]j]ujjj]rÀjX(Duplicate implicit target name: "build".rĀrŀ}rƀ(jUjjubajjubaubjs~)rǀ}rȀ(jUjj)jj'jjv~j}rɀ(j]UlevelKj]j]rʀj)aUsourcej'j]j]UlineKUtypej~ujKjhj]rˀj)r̀}r̀(jX&Duplicate implicit target name: "run".j}r΀(j]j]j]j]j]ujjǀj]rπjX&Duplicate implicit target name: "run".rЀrр}rҀ(jUjj̀ubajjubaubjs~)rӀ}rԀ(jUjjo*jj'jjv~j}rՀ(j]UlevelKj]j]rրjt*aUsourcej'j]j]UlineKUtypej~ujKjhj]r׀j)r؀}rـ(jX&Duplicate implicit target name: "qnx".j}rڀ(j]j]j]j]j]ujjӀj]rۀjX&Duplicate implicit target name: "qnx".r܀r݀}rހ(jUjj؀ubajjubaubjs~)r߀}r(jUjj/jj/jjv~j}r(j]UlevelKj]j]rj/aUsourcej/j]j]UlineKUtypej~ujKjhj]rj)r}r(jX/Duplicate implicit target name: "introduction".j}r(j]j]j]j]j]ujj߀j]rjX/Duplicate implicit target name: "introduction".rr}r(jUjjubajjubaubjs~)r}r(jUjj1jj/jjv~j}r(j]UlevelKj]j]rj 1aUsourcej/j]j]UlineKGUtypej~ujKGjhj]rj)r}r(jX(Duplicate implicit target name: "linux".j}r(j]j]j]j]j]ujjj]rjX(Duplicate implicit target name: "linux".rr}r(jUjjubajjubaubjs~)r}r(jUjj$1jj/jjv~j}r(j]UlevelKj]j]rj*1aUsourcej/j]j]UlineKQUtypej~ujKQjhj]rj)r}r(jX&Duplicate implicit target name: "qnx".j}r(j]j]j]j]j]ujjj]rjX&Duplicate implicit target name: "qnx".rr}r(jUjjubajjubaubjs~)r}r(jUjjv1jjo1jjv~j}r(j]UlevelKj]j]rj|1aUsourcejo1j]j]UlineKUtypej~ujKjhj]rj)r}r (jX/Duplicate implicit target name: "introduction".j}r (j]j]j]j]j]ujjj]r jX/Duplicate implicit target name: "introduction".r r }r(jUjjubajjubaubjs~)r}r(jUjj1jjo1jjv~j}r(j]UlevelKj]j]rj1aUsourcejo1j]j]UlineKUtypej~ujKjhj]rj)r}r(jX)Duplicate implicit target name: "config".j}r(j]j]j]j]j]ujjj]rjX)Duplicate implicit target name: "config".rr}r(jUjjubajjubaubjs~)r}r(jUj}r(j]UlevelKj]j]Usourcejj]j]UlineKUtypej~ujjH3j]rj)r}r (jX:Enumerated list start value not ordinal-1: "2" (ordinal 2)j}r!(j]j]j]j]j]ujjj]r"jX:Enumerated list start value not ordinal-1: "2" (ordinal 2)r#r$}r%(jUjjubajjubajjv~ubjs~)r&}r'(jUj}r((j]UlevelKj]j]Usourcejj]j]UlineKUtypej~ujj|3j]r)j)r*}r+(jX:Enumerated list start value not ordinal-1: "4" (ordinal 4)j}r,(j]j]j]j]j]ujj&j]r-jX:Enumerated list start value not ordinal-1: "4" (ordinal 4)r.r/}r0(jUjj*ubajjubajjv~ubjs~)r1}r2(jUj}r3(j]UlevelKj]j]Usourcejj]j]UlineKUtypej~ujj3j]r4j)r5}r6(jX:Enumerated list start value not ordinal-1: "6" (ordinal 6)j}r7(j]j]j]j]j]ujj1j]r8jX:Enumerated list start value not ordinal-1: "6" (ordinal 6)r9r:}r;(jUjj5ubajjubajjv~ubjs~)r<}r=(jUjj3jj3jjv~j}r>(j]UlevelKj]j]r?j3aUsourcej3j]j]UlineKUtypej~ujKjhj]r@j)rA}rB(jX+Duplicate implicit target name: "overview".j}rC(j]j]j]j]j]ujj<j]rDjX+Duplicate implicit target name: "overview".rErF}rG(jUjjAubajjubaubjs~)rH}rI(jUjjSDjjjjv~j}rJ(j]UlevelKj]j]rKjDaUsourcejj]j]UlineKUtypej~ujKjhj]rLj)rM}rN(jX:Duplicate explicit target name: "ipc lld for am65x/j721e".j}rO(j]j]j]j]j]ujjHj]rPjX:Duplicate explicit target name: "ipc lld for am65x/j721e".rQrR}rS(jUjjMubajjubaubjs~)rT}rU(jUjj0GjjDjjv~j}rV(j]UlevelKj]j]rWj5GaUsourcejDj]j]UlineKUtypej~ujKjhj]rXj)rY}rZ(jXBDuplicate implicit target name: "how do i change the memory map?".j}r[(j]j]j]j]j]ujjTj]r\jXBDuplicate implicit target name: "how do i change the memory map?".r]r^}r_(jUjjYubajjubaubjs~)r`}ra(jUjjGjjDjjv~j}rb(j]UlevelKj]j]rcjGaUsourcejDj]j]UlineM Utypej~ujM jhj]rdj)re}rf(jX(Duplicate implicit target name: "linux".j}rg(j]j]j]j]j]ujj`j]rhjX(Duplicate implicit target name: "linux".rirj}rk(jUjjeubajjubaubjs~)rl}rm(jUjjHjjDjjv~j}rn(j]UlevelKj]j]rojHaUsourcejDj]j]UlineMUtypej~ujMjhj]rpj)rq}rr(jX&Duplicate implicit target name: "qnx".j}rs(j]j]j]j]j]ujjlj]rtjX&Duplicate implicit target name: "qnx".rurv}rw(jUjjqubajjubaubjs~)rx}ry(jUjj)JjjDjjv~j}rz(j]UlevelKj]j]r{j/JaUsourcejDj]j]UlineMUtypej~ujMjhj]r|j)r}}r~(jX(Duplicate implicit target name: "linux".j}r(j]j]j]j]j]ujjxj]rjX(Duplicate implicit target name: "linux".rr}r(jUjj}ubajjubaubjs~)r}r(jUjjJjjDjjv~j}r(j]UlevelKj]j]rjJaUsourcejDj]j]UlineMUtypej~ujMjhj]rj)r}r(jX&Duplicate implicit target name: "qnx".j}r(j]j]j]j]j]ujjj]rjX&Duplicate implicit target name: "qnx".rr}r(jUjjubajjubaubjs~)r}r(jUjjJjjJjjv~j}r(j]UlevelKj]j]rjJaUsourcejJj]j]UlineKUtypej~ujKjhj]rj)r}r(jX+Duplicate implicit target name: "overview".j}r(j]j]j]j]j]ujjj]rjX+Duplicate implicit target name: "overview".rr}r(jUjjubajjubaubjs~)r}r(jUjjYKjjJjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineKUtypej~ujMMjhj]rj)r}r(jX:Enumerated list start value not ordinal-1: "2" (ordinal 2)j}r(j]j]j]j]j]ujjj]rjX:Enumerated list start value not ordinal-1: "2" (ordinal 2)rr}r(jUjjubajjubaubjs~)r}r(jUjjYKjjJjjv~j}r(j]UlevelKj]j]UsourcejJj]j]UlineMkUtypejx~ujM~jhj]rj)r}r(jX%Line block ends without a blank line.j}r(j]j]j]j]j]ujjj]rjX%Line block ends without a blank line.rr}r(jUjjubajjubaubjs~)r}r(jUjjPjj}Pjjv~j}r(j]UlevelKj]j]rjPaUsourcej}Pj]j]UlineKUtypej~ujKjhj]rj)r}r(jX/Duplicate implicit target name: "introduction".j}r(j]j]j]j]j]ujjj]rjX/Duplicate implicit target name: "introduction".rr}r(jUjjubajjubaubjs~)r}r(jUjj!Qjj}Pjjv~j}r(j]UlevelKj]j]rj'QaUsourcej}Pj]j]UlineK/Utypej~ujK/jhj]rj)rÁ}rā(jX(Duplicate implicit target name: "build".j}rŁ(j]j]j]j]j]ujjj]rƁjX(Duplicate implicit target name: "build".rǁrȁ}rɁ(jUjjÁubajjubaubjs~)rʁ}rˁ(jUjjcSjj\Sjjv~j}ŕ(j]UlevelKj]j]ŕjiSaUsourcej\Sj]j]UlineKUtypej~ujKjhj]r΁j)rρ}rЁ(jX/Duplicate implicit target name: "introduction".j}rс(j]j]j]j]j]ujjʁj]rҁjX/Duplicate implicit target name: "introduction".rӁrԁ}rՁ(jUjjρubajjubaubjs~)rց}rׁ(jUjjSjj\Sjjv~j}r؁(j]UlevelKj]j]rفjSaUsourcej\Sj]j]UlineKUtypej~ujKjhj]rځj)rہ}r܁(jX*Duplicate implicit target name: "install".j}r݁(j]j]j]j]j]ujjցj]rށjX*Duplicate implicit target name: "install".r߁r}r(jUjjہubajjubaubjs~)r}r(jUjjSjj\Sjjv~j}r(j]UlevelKj]j]rjTaUsourcej\Sj]j]UlineK0Utypej~ujK0jhj]rj)r}r(jX(Duplicate implicit target name: "build".j}r(j]j]j]j]j]ujjj]rjX(Duplicate implicit target name: "build".rr}r(jUjjubajjubaubjs~)r}r(jUjj+Tjj\Sjjv~j}r(j]UlevelKj]j]rj0TaUsourcej\Sj]j]UlineK@Utypej~ujK@jhj]rj)r}r(jX/Duplicate implicit target name: "products.mak".j}r(j]j]j]j]j]ujjj]rjX/Duplicate implicit target name: "products.mak".rr}r(jUjjubajjubaubjs~)r}r(jUjjVjj\Sjjv~j}r(j]UlevelKj]j]rjVaUsourcej\Sj]j]UlineKUtypej~ujKjhj]rj)r}r(jX/Duplicate implicit target name: "ipc-bios.mak".j}r(j]j]j]j]j]ujjj]rjX/Duplicate implicit target name: "ipc-bios.mak".rr}r(jUjjubajjubaubjs~)r}r(jUjj2Wjj\Sjjv~j}r(j]UlevelKj]j]r j8WaUsourcej\Sj]j]UlineKUtypej~ujKjhj]r j)r }r (jX&Duplicate implicit target name: "run".j}r (j]j]j]j]j]ujjj]rjX&Duplicate implicit target name: "run".rr}r(jUjj ubajjubaubjs~)r}r(jUjj Zjj\Sjjv~j}r(j]UlevelKj]j]rjZaUsourcej\Sj]j]UlineMUtypej~ujMjhj]rj)r}r(jX+Duplicate implicit target name: "see also".j}r(j]j]j]j]j]ujjj]rjX+Duplicate implicit target name: "see also".rr}r(jUjjubajjubaubjs~)r}r(jUjjZjjZjjv~j}r (j]UlevelKj]j]r!jZaUsourcejZj]j]UlineKUtypej~ujKjhj]r"j)r#}r$(jX/Duplicate implicit target name: "introduction".j}r%(j]j]j]j]j]ujjj]r&jX/Duplicate implicit target name: "introduction".r'r(}r)(jUjj#ubajjubaubjs~)r*}r+(jUjjZjjZjjv~j}r,(j]UlevelKj]j]r-jZaUsourcejZj]j]UlineKUtypej~ujKjhj]r.j)r/}r0(jX*Duplicate implicit target name: "install".j}r1(j]j]j]j]j]ujj*j]r2jX*Duplicate implicit target name: "install".r3r4}r5(jUjj/ubajjubaubjs~)r6}r7(jUjj$[jjZjjv~j}r8(j]UlevelKj]j]r9j*[aUsourcejZj]j]UlineK0Utypej~ujK0jhj]r:j)r;}r<(jX(Duplicate implicit target name: "build".j}r=(j]j]j]j]j]ujj6j]r>jX(Duplicate implicit target name: "build".r?r@}rA(jUjj;ubajjubaubjs~)rB}rC(jUjjP[jjZjjv~j}rD(j]UlevelKj]j]rEjV[aUsourcejZj]j]UlineK@Utypej~ujK@jhj]rFj)rG}rH(jX/Duplicate implicit target name: "products.mak".j}rI(j]j]j]j]j]ujjBj]rJjX/Duplicate implicit target name: "products.mak".rKrL}rM(jUjjGubajjubaubjs~)rN}rO(jUjj\jjZjjv~j}rP(j]UlevelKj]j]rQj\aUsourcejZj]j]UlineK|Utypej~ujK|jhj]rRj)rS}rT(jX/Duplicate implicit target name: "ipc-bios.mak".j}rU(j]j]j]j]j]ujjNj]rVjX/Duplicate implicit target name: "ipc-bios.mak".rWrX}rY(jUjjSubajjubaubjs~)rZ}r[(jUjj ]jjZjjv~j}r\(j]UlevelKj]j]r]j]aUsourcejZj]j]UlineKUtypej~ujKjhj]r^j)r_}r`(jX&Duplicate implicit target name: "run".j}ra(j]j]j]j]j]ujjZj]rbjX&Duplicate implicit target name: "run".rcrd}re(jUjj_ubajjubaubjs~)rf}rg(jUjj#]jjZjjv~j}rh(j]UlevelKj]rijL]aj]rjjK]aUsourcejZj]j]UlineKUtypejx~ujKjhj]rkj)rl}rm(jX0Inline emphasis start-string without end-string.j}rn(j]j]j]j]j]ujjfj]rojX0Inline emphasis start-string without end-string.rprq}rr(jUjjlubajjubaubjs~)rs}rt(jUjj^jjZjjv~j}ru(j]UlevelKj]j]rvj^aUsourcejZj]j]UlineM%Utypej~ujM%jhj]rwj)rx}ry(jX<Duplicate implicit target name: "running test applications".j}rz(j]j]j]j]j]ujjsj]r{jX<Duplicate implicit target name: "running test applications".r|r}}r~(jUjjxubajjubaubjs~)r}r(jUjj(ajjZjjv~j}r(j]UlevelKj]j]rj.aaUsourcejZj]j]UlineM~Utypej~ujM~jhj]rj)r}r(jX+Duplicate implicit target name: "see also".j}r(j]j]j]j]j]ujjj]rjX+Duplicate implicit target name: "see also".rr}r(jUjjubajjubaubjs~)r}r(jUjj)r}r(jUjKjj)r}r(jUjhjjjjj}r(j]j]j]j]rUbootraj]rjaujKjhj]r(j)r}r(jXBootrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXBootrr}r(jjjjubaubj)r}r(jX.. _FC-Boot-label:jjjjjj j}r(j]j]j]j]j]jU fc-boot-labelrujM:jhj]ubjj)r}r(jUjKjjjj:Xsource/rtos/Boot.rst.incrr}rbjjj}r(j]rX boot modesraj]j]j]rU boot-modesraj]ujKjhj]r(j)r}r(jX Boot Modesrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjX Boot Modesrr}r(jjjjubaubj)r}r(jUjjjjjjj}r(j]j]j]j]rUmmcsdraj]rj3aujKjhj]r(j)r}r(jXMMCSDrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXMMCSDrr‚}rÂ(jjjjubaubj)rĂ}rł(jXiMMCSD bootloader is required to boot target using an SD card containing bootloader and application images. When the board is powered ON the ROM bootloader detects the MMCSD bootloader image and loads it to the internal memory.The bootloader initializes the board, copies the application image from SD card to the DDR memory and gives control to the application.rƂjjjjjjj}rǂ(j]j]j]j]j]ujKjhj]rȂjXiMMCSD bootloader is required to boot target using an SD card containing bootloader and application images. When the board is powered ON the ROM bootloader detects the MMCSD bootloader image and loads it to the internal memory.The bootloader initializes the board, copies the application image from SD card to the DDR memory and gives control to the application.rɂrʂ}r˂(jjƂjjĂubaubeubj)r̂}r͂(jUjjjjjjj}r΂(j]j]j]j]rςUqspirЂaj]rтhaujKjhj]r҂(j)rӂ}rԂ(jXQSPIrՂjĵjjjjj}rւ(j]j]j]j]j]ujKjhj]rׂjXQSPIr؂rق}rڂ(jjՂjjӂubaubj)rۂ}r܂(jXkA flash device interfaced with QSPI is flashed with QSPI bootloader and application images. When the board is powered ON the ROM bootloader detects the bootloader image from flash device and loads it to the internal memory. The Bootloader initializes the board, copies the application image from QSPI device to the DDR memory and gives control to the application.r݂jĵjjjjj}rނ(j]j]j]j]j]ujKjhj]r߂jXkA flash device interfaced with QSPI is flashed with QSPI bootloader and application images. When the board is powered ON the ROM bootloader detects the bootloader image from flash device and loads it to the internal memory. The Bootloader initializes the board, copies the application image from QSPI device to the DDR memory and gives control to the application.rr}r(jj݂jjۂubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rUuartraj]rjaujK%jhj]r(j)r}r(jXUARTrjjjjjjj}r(j]j]j]j]j]ujK%jhj]rjXUARTrr}r(jjjjubaubj)r}r(jXcA Serial connection is used for transferring the bootloader binary from PC to target board through XMODEM protocol. The bootloader on execution prompts for application image to transfer through XMODEM. On providing the path, the application binary is transferred through serial connection to DDR memory and the control is passed to application to execute.rjjjjjjj}r(j]j]j]j]j]ujK'jhj]rjXcA Serial connection is used for transferring the bootloader binary from PC to target board through XMODEM protocol. The bootloader on execution prompts for application image to transfer through XMODEM. On providing the path, the application binary is transferred through serial connection to DDR memory and the control is passed to application to execute.rr}r(jjjjubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rU mcspi-spiraj]rjaujK/jhj]r(j)r}r(jX MCSPI/SPIrjjjjjjj}r(j]j]j]j]j]ujK/jhj]rjX MCSPI/SPIrr}r(jjjjubaubj)r }r (jXtA SPI flash device flashed with MCSPI/SPI bootloader and application images is used for booting the board. When the board is powered ON the ROM bootloader detects the bootloader image from flash device and loads it to the internal memory. The Bootloader initializes the board, copies the application image from flash to the DDR memory and gives control to the application.r jjjjjjj}r (j]j]j]j]j]ujK1jhj]r jXtA SPI flash device flashed with MCSPI/SPI bootloader and application images is used for booting the board. When the board is powered ON the ROM bootloader detects the bootloader image from flash device and loads it to the internal memory. The Bootloader initializes the board, copies the application image from flash to the DDR memory and gives control to the application.rr}r(jj jj ubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rUnandraj]rh5aujK9jhj]r(j)r}r(jXNANDrjjjjjjj}r(j]j]j]j]j]ujK9jhj]rjXNANDrr}r(jjjjubaubj)r }r!(jX^NAND flash with bootloader and and application images is used for booting the board. When the board is powered ON the ROM bootloader detects the bootloader image from flash device and loads it to the internal memory. The bootloader initializes the board, copies the application image from flash to the DDR memory and gives control to the application.r"jjjjjjj}r#(j]j]j]j]j]ujK;jhj]r$jX^NAND flash with bootloader and and application images is used for booting the board. When the board is powered ON the ROM bootloader detects the bootloader image from flash device and loads it to the internal memory. The bootloader initializes the board, copies the application image from flash to the DDR memory and gives control to the application.r%r&}r'(jj"jj ubaubj)r(}r)(jXFor information on boot mode setting, see the applicable `EVM Hardware User Guide `__r*jjjjjjj}r+(j]j]j]j]j]ujNjhj]r,j)r-}r.(jj*jj(jjjjj}r/(j]j]j]j]j]ujKCj]r0(jX9For information on boot mode setting, see the applicable r1r2}r3(jX9For information on boot mode setting, see the applicable jj-ubj)r4}r5(jXZ`EVM Hardware User Guide `__j}r6(UnameXEVM Hardware User GuidejX<index_release_specific.html#supported-platforms-and-versionsj]j]j]j]j]ujj-j]r7jXEVM Hardware User Guider8r9}r:(jUjj4ubajjubeubaubeubeubj)r;}r<(jUjjjjjjj}r=(j]j]j]j]r>U platformsr?aj]r@jqaujKGjhj]rA(j)rB}rC(jX PlatformsrDjj;jjjjj}rE(j]j]j]j]j]ujKGjhj]rFjX PlatformsrGrH}rI(jjDjjBubaubj)rJ}rK(jUjj;jjjjj}rL(j]j]j]j]rMU am335x-am437xrNaj]rOhaujKJjhj]rP(j)rQ}rR(jX AM335x/AM437xrSjjJjjjjj}rT(j]j]j]j]j]ujKJjhj]rUjX AM335x/AM437xrVrW}rX(jjSjjQubaubj7)rY}rZ(jXMhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_BOOT_AM335x/AM437xjjJjj:X\source/rtos/PDK_Platform_Software/Boot_Board_and_EVM_Abstractions/BOOT_AM335x_AM437x.rst.incr[r\}r]bjj>j}r^(j@jAj]j]j]j]j]ujKjhj]r_jXMhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_BOOT_AM335x/AM437xr`ra}rb(jUjjYubaubj)rc}rd(jUjKjjJjj\jjj}re(j]rfXoverviewrgaj]j]j]rhUid67riaj]ujKjhj]rj(j)rk}rl(jXOverviewrmjjcjj\jjj}rn(j]j]j]j]j]ujKjhj]rojXOverviewrprq}rr(jjmjjkubaubj)rs}rt(jXBootloader supports power-on-reset bootstraps for the board. It initializes board, loads application from the memory device to DDR and transfers control to application. Section provides additional details including flashing and booting instructions across different media.rujjcjj\jjj}rv(j]j]j]j]j]ujKjhj]rwjXBootloader supports power-on-reset bootstraps for the board. It initializes board, loads application from the memory device to DDR and transfers control to application. Section provides additional details including flashing and booting instructions across different media.rxry}rz(jjujjsubaubeubj)r{}r|(jUjjJjj\jjj}r}(j]j]j]j]r~Usource-referenceraj]rhEaujK jhj]r(j)r}r(jXSource Referencerjj{jj\jjj}r(j]j]j]j]j]ujK jhj]rjXSource Referencerr}r(jjjjubaubj)r}r(jX5< BASE_DIR = PDK_INSTALL_DIR\packages\ti\starterware>jj{jj\jjj}r(j@jAj]j]j]j]j]ujMjhj]rjX5< BASE_DIR = PDK_INSTALL_DIR\packages\ti\starterware>rr}r(jUjjubaubj)r}r(jUjj{jj\jjj}r(j]j]j]j]rU(bootloader-build-files-for-am335x-am437xraj]rh]aujKjhj]r(j)r}r(jX(Bootloader build files for AM335x/AM437xrjjjj\jjj}r(j]j]j]j]j]ujKjhj]rjX(Bootloader build files for AM335x/AM437xrr}r(jjjjubaubj)r}r(jX**Source files:**rjjjj\jjj}r(j]j]j]j]j]ujKjhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX Source files:rr}r(jUjjubajjubaubjt)r}r(jUjjjj\jjwj}r(jyX-j]j]j]j]j]ujKjhj]r(j{)r}r(jXM**BASE_DIR/bootloader/src**: Common source files for bootloader functionalityjjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXM**BASE_DIR/bootloader/src**: Common source files for bootloader functionalityjjjj\jjj}r(j]j]j]j]j]ujKj]r(j)r}r(jX**BASE_DIR/bootloader/src**j}r(j]j]j]j]j]ujjj]rjXBASE_DIR/bootloader/srcrr}r(jUjjubajjubjX2: Common source files for bootloader functionalityrr}r(jX2: Common source files for bootloader functionalityjjubeubaubj{)rƒ}rÃ(jXx**BASE_DIR/bootloader/src/**: Files specific to device to initialize platform features like PLL, pinmux and DDR jjjj\jjj}ră(j]j]j]j]j]ujNjhj]rŃj)rƃ}rǃ(jXw**BASE_DIR/bootloader/src/**: Files specific to device to initialize platform features like PLL, pinmux and DDRjjƒjj\jjj}rȃ(j]j]j]j]j]ujKj]rɃ(j)rʃ}r˃(jX$**BASE_DIR/bootloader/src/**j}r̃(j]j]j]j]j]ujjƃj]r̓jX BASE_DIR/bootloader/src/r΃rσ}rЃ(jUjjʃubajjubjXS: Files specific to device to initialize platform features like PLL, pinmux and DDRrуr҃}rӃ(jXS: Files specific to device to initialize platform features like PLL, pinmux and DDRjjƃubeubaubeubj)rԃ}rՃ(jX**Build Files:**rփjjjj\jjj}r׃(j]j]j]j]j]ujKjhj]r؃j)rك}rڃ(jjփj}rۃ(j]j]j]j]j]ujjԃj]r܃jX Build Files:r݃rރ}r߃(jUjjكubajjubaubjt)r}r(jUjjjj\jjwj}r(jyX-j]j]j]j]j]ujKjhj]r(j{)r}r(jXp**BASE_DIR/build/makerules/rules_a8.mk**: Common Compiler flags used for A8 cores. Applies to AMIC110 and AM335xjjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXp**BASE_DIR/build/makerules/rules_a8.mk**: Common Compiler flags used for A8 cores. Applies to AMIC110 and AM335xjjjj\jjj}r(j]j]j]j]j]ujKj]r(j)r}r(jX(**BASE_DIR/build/makerules/rules_a8.mk**j}r(j]j]j]j]j]ujjj]rjX$BASE_DIR/build/makerules/rules_a8.mkrr}r(jUjjubajjubjXH: Common Compiler flags used for A8 cores. Applies to AMIC110 and AM335xrr}r(jXH: Common Compiler flags used for A8 cores. Applies to AMIC110 and AM335xjjubeubaubj{)r}r(jXl**BASE_DIR/build/makerules/rules_a9.mk**: Common Compiler flags used for A9 cores. Applies to AM437x devicesjjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXl**BASE_DIR/build/makerules/rules_a9.mk**: Common Compiler flags used for A9 cores. Applies to AM437x devicesjjjj\jjj}r(j]j]j]j]j]ujK!j]r(j)r}r(jX(**BASE_DIR/build/makerules/rules_a9.mk**j}r(j]j]j]j]j]ujjj]rjX$BASE_DIR/build/makerules/rules_a9.mkrr}r(jUjjubajjubjXD: Common Compiler flags used for A9 cores. Applies to AM437x devicesrr}r(jXD: Common Compiler flags used for A9 cores. Applies to AM437x devicesjjubeubaubj{)r}r (jXg**BASE_DIR/build/makerules/platform.mk**: Global settings for all components for a particular platform.jjjj\jjj}r (j]j]j]j]j]ujNjhj]r j)r }r (jXg**BASE_DIR/build/makerules/platform.mk**: Global settings for all components for a particular platform.jjjj\jjj}r(j]j]j]j]j]ujK#j]r(j)r}r(jX(**BASE_DIR/build/makerules/platform.mk**j}r(j]j]j]j]j]ujj j]rjX$BASE_DIR/build/makerules/platform.mkrr}r(jUjjubajjubjX?: Global settings for all components for a particular platform.rr}r(jX?: Global settings for all components for a particular platform.jj ubeubaubj{)r}r(jX[**BASE_DIR/build/makerules/components.mk**: Specific settings for components in starterwarejjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX[**BASE_DIR/build/makerules/components.mk**: Specific settings for components in starterwarejjjj\jjj}r (j]j]j]j]j]ujK%j]r!(j)r"}r#(jX***BASE_DIR/build/makerules/components.mk**j}r$(j]j]j]j]j]ujjj]r%jX&BASE_DIR/build/makerules/components.mkr&r'}r((jUjj"ubajjubjX1: Specific settings for components in starterwarer)r*}r+(jX1: Specific settings for components in starterwarejjubeubaubj{)r,}r-(jXP**BASE_DIR/build/makerules/build_cfg.mk**: Flags to enable features in the buildjjjj\jjj}r.(j]j]j]j]j]ujNjhj]r/j)r0}r1(jXP**BASE_DIR/build/makerules/build_cfg.mk**: Flags to enable features in the buildjj,jj\jjj}r2(j]j]j]j]j]ujK'j]r3(j)r4}r5(jX)**BASE_DIR/build/makerules/build_cfg.mk**j}r6(j]j]j]j]j]ujj0j]r7jX%BASE_DIR/build/makerules/build_cfg.mkr8r9}r:(jUjj4ubajjubjX': Flags to enable features in the buildr;r<}r=(jX': Flags to enable features in the buildjj0ubeubaubj{)r>}r?(jX**BASE_DIR/bootloader/Makefile**: Makefile for bootloader that provides list of source files and library to create bootloader binary. jjjj\jjj}r@(j]j]j]j]j]ujNjhj]rAj)rB}rC(jX**BASE_DIR/bootloader/Makefile**: Makefile for bootloader that provides list of source files and library to create bootloader binary.jj>jj\jjj}rD(j]j]j]j]j]ujK)j]rE(j)rF}rG(jX **BASE_DIR/bootloader/Makefile**j}rH(j]j]j]j]j]ujjBj]rIjXBASE_DIR/bootloader/MakefilerJrK}rL(jUjjFubajjubjXe: Makefile for bootloader that provides list of source files and library to create bootloader binary.rMrN}rO(jXe: Makefile for bootloader that provides list of source files and library to create bootloader binary.jjBubeubaubeubj)rP}rQ(jX**Boot and flashing tools:**rRjjjj\jjj}rS(j]j]j]j]j]ujK-jhj]rTj)rU}rV(jjRj}rW(j]j]j]j]j]ujjPj]rXjXBoot and flashing tools:rYrZ}r[(jUjjUubajjubaubjt)r\}r](jUjjjj\jjwj}r^(jyX-j]j]j]j]j]ujK/jhj]r_j{)r`}ra(jXy**BASE_DIR/tools Contains tools to create boot images and flashing tools to program the boot binary on the boot media.** jj\jj\jjj}rb(j]j]j]j]j]ujNjhj]rcj)rd}re(jXx**BASE_DIR/tools Contains tools to create boot images and flashing tools to program the boot binary on the boot media.**rfjj`jj\jjj}rg(j]j]j]j]j]ujK/j]rhj)ri}rj(jjfj}rk(j]j]j]j]j]ujjdj]rljXtBASE_DIR/tools Contains tools to create boot images and flashing tools to program the boot binary on the boot media.rmrn}ro(jUjjiubajjubaubaubaubjc)rp}rq(jUjjjj\jjfj}rr(j]j]j]j]j]ujK2jhj]rsji)rt}ru(jUjlKjjpjj\jjj}rv(j]j]j]j]j]ujKjhj]ubaubeubeubj)rw}rx(jUjKjjJjj\jjj}ry(j]rzXbootloader execution sequencer{aj]j]j]r|Ubootloader-execution-sequencer}aj]ujK5jhj]r~(j)r}r(jXBootloader execution sequencerjjwjj\jjj}r(j]j]j]j]j]ujK5jhj]rjXBootloader execution sequencerr}r(jjjjubaubj)r}r(jXThe Processor SDK RTOS boot loader uses a two stage boot process. The different stages of the application boot sequence using Processor SDK RTOS bootloader are shown below:rjjwjj\jjj}r(j]j]j]j]j]ujK7jhj]rjXThe Processor SDK RTOS boot loader uses a two stage boot process. The different stages of the application boot sequence using Processor SDK RTOS bootloader are shown below:rr}r(jjjjubaubj)r}r(jUjjwjj\jjj}r(j]j]j]j]rU boot-sequenceraj]rhQaujKjhj]r(j{)r}r(jXPower on Resetrjjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj\jjj}r(j]j]j]j]j]ujK>j]rjXPower on Resetrr}r(jjjjubaubaubj{)r}r(jXROM Bootloader (RBL) - Platform configuration and initialization. - DPLL and clock settings for MPU, I2C, MMCSD, USB, SPI, QSPI, Ethernet etc. - Checks Sysboot pins and choose booting device - If no valid bootloader found on booting device, RBL checks for next booting device. The sequence depends on RBL execution flow and Sysboot pins. - RBL gets image size and load address by checking TI Image Header appended on bootloader binary(.bin). Check `binary formats `__. - Loads the binary to internal OCMC memory at the Load address fetched from TI Image Header - Passes control to Secondary Bootloader(SBL) jjjNjjj}r(j]j]j]j]j]ujNjhj]r(j)r}r(jXROM Bootloader (RBL)rjjjj\jjj}r(j]j]j]j]j]ujK?j]rjXROM Bootloader (RBL)rr}r(jjjjubaubjt)r}r(jUj}r(jyX-j]j]j]j]j]ujjj]r(j{)r}r(jX}Platform configuration and initialization. - DPLL and clock settings for MPU, I2C, MMCSD, USB, SPI, QSPI, Ethernet etc. j}r(j]j]j]j]j]ujjj]r(j)r„}rÄ(jX*Platform configuration and initialization.rĄjjjj\jjj}rń(j]j]j]j]j]ujKAj]rƄjX*Platform configuration and initialization.rDŽrȄ}rɄ(jjĄjj„ubaubjt)rʄ}r˄(jUj}r̄(jyX-j]j]j]j]j]ujjj]r̈́j{)r΄}rτ(jXKDPLL and clock settings for MPU, I2C, MMCSD, USB, SPI, QSPI, Ethernet etc. j}rЄ(j]j]j]j]j]ujjʄj]rфj)r҄}rӄ(jXJDPLL and clock settings for MPU, I2C, MMCSD, USB, SPI, QSPI, Ethernet etc.rԄjj΄jj\jjj}rՄ(j]j]j]j]j]ujKCj]rքjXJDPLL and clock settings for MPU, I2C, MMCSD, USB, SPI, QSPI, Ethernet etc.rׄr؄}rل(jjԄjj҄ubaubajjubajjwubejjubj{)rڄ}rۄ(jXChecks Sysboot pins and choose booting device - If no valid bootloader found on booting device, RBL checks for next booting device. The sequence depends on RBL execution flow and Sysboot pins. j}r܄(j]j]j]j]j]ujjj]r݄(j)rބ}r߄(jX-Checks Sysboot pins and choose booting devicerjjڄjj\jjj}r(j]j]j]j]j]ujKFj]rjX-Checks Sysboot pins and choose booting devicerr}r(jjjjބubaubjt)r}r(jUj}r(jyX-j]j]j]j]j]ujjڄj]rj{)r}r(jXIf no valid bootloader found on booting device, RBL checks for next booting device. The sequence depends on RBL execution flow and Sysboot pins. j}r(j]j]j]j]j]ujjj]rj)r}r(jXIf no valid bootloader found on booting device, RBL checks for next booting device. The sequence depends on RBL execution flow and Sysboot pins.rjjjj\jjj}r(j]j]j]j]j]ujKHj]rjXIf no valid bootloader found on booting device, RBL checks for next booting device. The sequence depends on RBL execution flow and Sysboot pins.rr}r(jjjjubaubajjubajjwubejjubj{)r}r(jXRBL gets image size and load address by checking TI Image Header appended on bootloader binary(.bin). Check `binary formats `__.j}r(j]j]j]j]j]ujjj]rj)r}r(jXRBL gets image size and load address by checking TI Image Header appended on bootloader binary(.bin). Check `binary formats `__.jjjj\jjj}r(j]j]j]j]j]ujKLj]r(jXlRBL gets image size and load address by checking TI Image Header appended on bootloader binary(.bin). Check rr}r(jXlRBL gets image size and load address by checking TI Image Header appended on bootloader binary(.bin). Check jjubj)r}r(jXP`binary formats `__j}r(UnameXbinary formatsjX;index_Foundational_Components.html#tools-and-binary-formatsj]j]j]j]j]ujjj]rjXbinary formatsrr}r(jUjjubajjubjX.r}r (jX.jjubeubajjubj{)r }r (jXYLoads the binary to internal OCMC memory at the Load address fetched from TI Image Headerj}r (j]j]j]j]j]ujjj]r j)r}r(jXYLoads the binary to internal OCMC memory at the Load address fetched from TI Image Headerrjj jj\jjj}r(j]j]j]j]j]ujKOj]rjXYLoads the binary to internal OCMC memory at the Load address fetched from TI Image Headerrr}r(jjjjubaubajjubj{)r}r(jX,Passes control to Secondary Bootloader(SBL) j}r(j]j]j]j]j]ujjj]rj)r}r(jX+Passes control to Secondary Bootloader(SBL)rjjjj\jjj}r(j]j]j]j]j]ujKQj]rjX+Passes control to Secondary Bootloader(SBL)rr }r!(jjjjubaubajjubejjwubeubj{)r"}r#(jXSecondary Bootloader(SBL) - Configure PLL and Initialize DDR - Configure PRCM and PinMux  for Boot Peripherals - Copies application image to DDR - Passes execution control to Application jjjNjjj}r$(j]j]j]j]j]ujNjhj]r%(j)r&}r'(jXSecondary Bootloader(SBL)r(jj"jj\jjj}r)(j]j]j]j]j]ujKSj]r*jXSecondary Bootloader(SBL)r+r,}r-(jj(jj&ubaubjt)r.}r/(jUj}r0(jyX-j]j]j]j]j]ujj"j]r1(j{)r2}r3(jX Configure PLL and Initialize DDRr4j}r5(j]j]j]j]j]ujj.j]r6j)r7}r8(jj4jj2jj\jjj}r9(j]j]j]j]j]ujKUj]r:jX Configure PLL and Initialize DDRr;r<}r=(jj4jj7ubaubajjubj{)r>}r?(jX0Configure PRCM and PinMux  for Boot Peripheralsr@j}rA(j]j]j]j]j]ujj.j]rBj)rC}rD(jj@jj>jj\jjj}rE(j]j]j]j]j]ujKVj]rFjX0Configure PRCM and PinMux  for Boot PeripheralsrGrH}rI(jj@jjCubaubajjubj{)rJ}rK(jXCopies application image to DDRrLj}rM(j]j]j]j]j]ujj.j]rNj)rO}rP(jjLjjJjj\jjj}rQ(j]j]j]j]j]ujKWj]rRjXCopies application image to DDRrSrT}rU(jjLjjOubaubajjubj{)rV}rW(jX(Passes execution control to Application j}rX(j]j]j]j]j]ujj.j]rYj)rZ}r[(jX'Passes execution control to Applicationr\jjVjj\jjj}r](j]j]j]j]j]ujKXj]r^jX'Passes execution control to Applicationr_r`}ra(jj\jjZubaubajjubejjwubeubj{)rb}rc(jXApplication execution jjjj\jjj}rd(j]j]j]j]j]ujNjhj]rej)rf}rg(jXApplication executionrhjjbjj\jjj}ri(j]j]j]j]j]ujKZj]rjjXApplication executionrkrl}rm(jjhjjfubaubaubeubeubeubj)rn}ro(jUjKjjJjj\jjj}rp(j]rqXtools and binary formatsrraj]j]j]rsUtools-and-binary-formatsrtaj]ujK]jhj]ru(j)rv}rw(jXTools and Binary formatsrxjjnjj\jjj}ry(j]j]j]j]j]ujK]jhj]rzjXTools and Binary formatsr{r|}r}(jjxjjvubaubjy )r~}r(jUjjnjj\jj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujj~j]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX Binary formatrjjjj\jjj}r(j]j]j]j]j]ujK`j]rjX Binary formatrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX Requirementrjjjj\jjj}r(j]j]j]j]j]ujK`j]rjX Requirementrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXDetailsrjjjj\jjj}r(j]j]j]j]j]ujK`j]rjXDetailsrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]r…j)rÅ}rą(jX.binrŅjjjj\jjj}rƅ(j]j]j]j]j]ujKbj]rDžjX.binrȅrɅ}rʅ(jjŅjjÅubaubajj ubj )r˅}r̅(jUj}rͅ(j]j]j]j]j]ujjj]r΅(j)rυ}rЅ(jXQSPI bootloader,rхjj˅jj\jjj}r҅(j]j]j]j]j]ujKbj]rӅjXQSPI bootloader,rԅrՅ}rօ(jjхjjυubaubj)rׅ}r؅(jXUART bootloader and apprمjj˅jj\jjj}rڅ(j]j]j]j]j]ujKdj]rۅjXUART bootloader and appr܅r݅}rޅ(jjمjjׅubaubejj ubj )r߅}r(jUj}r(j]j]j]j]j]ujjj]r(j)r}r(jXaQSPI bootloader binary should in .bin format and Application binary should be in \_ti.bin format.jj߅jj\jjj}r(j]j]j]j]j]ujKbj]rjX`QSPI bootloader binary should in .bin format and Application binary should be in _ti.bin format.rr}r(jXaQSPI bootloader binary should in .bin format and Application binary should be in \_ti.bin format.jjubaubj)r}r(jXVUART bootloader and applications are loaded in .bin format through XMODEM in terminal.rjj߅jj\jjj}r(j]j]j]j]j]ujKij]rjXVUART bootloader and applications are loaded in .bin format through XMODEM in terminal.rr}r(jjjjubaubejj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX\_ti.binjjjj\jjj}r(j]j]j]j]j]ujKoj]rjX_ti.binrr}r(jX\_ti.binjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j)r}r(jXMMCSD bootloader and app,rjjjj\jjj}r(j]j]j]j]j]ujKoj]r jXMMCSD bootloader and app,r r }r (jjjjubaubj)r }r(jXNAND bootloader and app,rjjjj\jjj}r(j]j]j]j]j]ujKrj]rjXNAND bootloader and app,rr}r(jjjj ubaubj)r}r(jXMCSPI boot loader and app,rjjjj\jjj}r(j]j]j]j]j]ujKuj]rjXMCSPI boot loader and app,rr}r(jjjjubaubj)r}r(jX QSPI app.rjjjj\jjj}r (j]j]j]j]j]ujKxj]r!jX QSPI app.r"r#}r$(jjjjubaubejj ubj )r%}r&(jUj}r'(j]j]j]j]j]ujjj]r((j)r)}r*(jX.bin binaries are converted to \_ti.bin format by adding Image size(4bytes) and Image load address(4bytes) as image header. Refer to Image format section in Initialization chapter of `AM437x TRM`_jj%jj\jjj}r+(j]j]j]j]j]ujKoj]r,(jX.bin binaries are converted to _ti.bin format by adding Image size(4bytes) and Image load address(4bytes) as image header. Refer to Image format section in Initialization chapter of r-r.}r/(jX.bin binaries are converted to \_ti.bin format by adding Image size(4bytes) and Image load address(4bytes) as image header. Refer to Image format section in Initialization chapter of jj)ubj)r0}r1(jX `AM437x TRM`_jKjj)jjj}r2(UnameX AM437x TRMjX.http://www.ti.com/lit/ug/spruhl7h/spruhl7h.pdfr3j]j]j]j]j]uj]r4jX AM437x TRMr5r6}r7(jUjj0ubaubeubj)r8}r9(jXeMMCSD, NAND and MCSPI boot loaders and application binaries should be appended with ti image header.r:jj%jj\jjj}r;(j]j]j]j]j]ujK}j]r<jXeMMCSD, NAND and MCSPI boot loaders and application binaries should be appended with ti image header.r=r>}r?(jj:jj8ubaubejj ubejj ubejj ubejj ubaubj)r@}rA(jX>.. _AM437x TRM: http://www.ti.com/lit/ug/spruhl7h/spruhl7h.pdfjKjjnjj\jj j}rB(jj3j]rCU am437x-trmrDaj]j]j]j]rEhaujM jhj]ubjc)rF}rG(jUjjnjj\jjfj}rH(j]j]j]j]j]ujKjhj]rIji)rJ}rK(jUjlKjjFjj\jjj}rL(j]j]j]j]j]ujKjhj]ubaubj)rM}rN(jX**TI Boot image**rOjjnjj\jjj}rP(j]j]j]j]j]ujKjhj]rQj)rR}rS(jjOj}rT(j]j]j]j]j]ujjMj]rUjX TI Boot imagerVrW}rX(jUjjRubajjubaubjy )rY}rZ(jUjjnjj\jj j}r[(j]j]j]j]j]ujNjhj]r\j~ )r]}r^(jUj}r_(j]j]j]j]j]UcolsKujjYj]r`(j )ra}rb(jUj}rc(j]j]j]j]j]UcolwidthK ujj]j]jj ubj )rd}re(jUj}rf(j]j]j]j]j]UcolwidthKujj]j]jj ubj )rg}rh(jUj}ri(j]j]j]j]j]ujj]j]rjj )rk}rl(jUj}rm(j]j]j]j]j]ujjgj]rn(j )ro}rp(jUj}rq(j]j]j]j]j]ujjkj]rrj)rs}rt(jXOffsetrujjojj\jjj}rv(j]j]j]j]j]ujKj]rwjXOffsetrxry}rz(jjujjsubaubajj ubj )r{}r|(jUj}r}(j]j]j]j]j]ujjkj]r~j)r}r(jX Binary valuerjj{jj\jjj}r(j]j]j]j]j]ujKj]rjX Binary valuerr}r(jjjjubaubajj ubejj ubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj]j]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX 0x00000000rjjjj\jjj}r(j]j]j]j]j]ujKj]rjX 0x00000000rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX**Size**rjjjj\jjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXSizerr}r(jUjjubajjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX 0x00000004rjjjj\jjj}r(j]j]j]j]j]ujKj]rjX 0x00000004rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX**Entry Point (Location)**rjjjj\jjj}r†(j]j]j]j]j]ujKj]rÆj)rĆ}rņ(jjj}rƆ(j]j]j]j]j]ujjj]rdžjXEntry Point (Location)rȆrɆ}rʆ(jUjjĆubajjubaubajj ubejj ubj )rˆ}r̆(jUj}r͆(j]j]j]j]j]ujjj]rΆ(j )rφ}rІ(jUj}rц(j]j]j]j]j]ujjˆj]r҆j)rӆ}rԆ(jX 0x00000008rՆjjφjj\jjj}rֆ(j]j]j]j]j]ujKj]r׆jX 0x00000008r؆rن}rچ(jjՆjjӆubaubajj ubj )rۆ}r܆(jUj}r݆(j]j]j]j]j]ujjˆj]rކj)r߆}r(jX**Binary (.bin)**rjjۆjj\jjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujj߆j]rjX Binary (.bin)rr}r(jUjjubajjubaubajj ubejj ubejj ubejj ubaubj)r}r(jXi- For bootloader, the entry point is usually 0x402f0000 - For app, the entry point is usually 0x80000000.jjnjNjjj}r(j]j]j]j]j]ujNjhj]rjt)r}r(jUj}r(jyX-j]j]j]j]j]ujjj]r(j{)r}r(jX5For bootloader, the entry point is usually 0x402f0000rj}r(j]j]j]j]j]ujjj]rj)r}r(jjjjjj\jjj}r(j]j]j]j]j]ujKj]rjX5For bootloader, the entry point is usually 0x402f0000rr}r(jjjjubaubajjubj{)r}r(jX/For app, the entry point is usually 0x80000000.rj}r(j]j]j]j]j]ujjj]rj)r}r(jjjjjj\jjj}r(j]j]j]j]j]ujKj]rjX/For app, the entry point is usually 0x80000000.rr }r (jjjjubaubajjubejjwubaubj)r }r (jUjjnjj\jjj}r (j]j]j]j]rU"binary-format-conversion-procedureraj]rjdaujKjhj]r(j)r}r(jX"Binary format conversion procedurerjj jj\jjj}r(j]j]j]j]j]ujKjhj]rjX"Binary format conversion procedurerr}r(jjjjubaubj)r}r(jXThe GCC tool chain, referred as GCC_TOOLCHAIN_PATH below, is installed during the Processor-SDK RTOS installation. For example, Processor-SDK RTOS 6.3 has gcc-arm-none-eabi-7-2018-q2-update.rjj jj\jjj}r(j]j]j]j]j]ujKjhj]rjXThe GCC tool chain, referred as GCC_TOOLCHAIN_PATH below, is installed during the Processor-SDK RTOS installation. For example, Processor-SDK RTOS 6.3 has gcc-arm-none-eabi-7-2018-q2-update.rr }r!(jjjjubaubj)r"}r#(jUjj jj\jjj}r$(j]j]j]j]r%U!binary-format-conversion-in-linuxr&aj]r'jaujKjhj]r((j)r)}r*(jX!Binary format conversion in Linuxr+jj"jj\jjj}r,(j]j]j]j]j]ujKjhj]r-jX!Binary format conversion in Linuxr.r/}r0(jj+jj)ubaubj )r1}r2(jUjj"jj\jj j}r3(jU)j]j]j]jUj]j]jjujKjhj]r4j{)r5}r6(jXTo convert from .out -> .bin jj1jj\jjj}r7(j]j]j]j]j]ujNjhj]r8j)r9}r:(jXTo convert from .out -> .binr;jj5jj\jjj}r<(j]j]j]j]j]ujKj]r=jXTo convert from .out -> .binr>r?}r@(jj;jj9ubaubaubaubj)rA}rB(jX\/bin/arm-none-eabi-objcopy -O binary .out .binjj"jj\jjj}rC(j@jAj]j]j]j]j]ujM3 jhj]rDjX\/bin/arm-none-eabi-objcopy -O binary .out .binrErF}rG(jUjjAubaubj )rH}rI(jUjj"jj\jj j}rJ(jU)jO3Kj]j]j]jUj]j]jjujKjhj]rKj{)rL}rM(jX5Build tiimage.out. Go to starterware/tools/ti_image/ jjHjj\jjj}rN(j]j]j]j]j]ujNjhj]rOj)rP}rQ(jX4Build tiimage.out. Go to starterware/tools/ti_image/rRjjLjj\jjj}rS(j]j]j]j]j]ujKj]rTjX4Build tiimage.out. Go to starterware/tools/ti_image/rUrV}rW(jjRjjPubaubaubaubj)rX}rY(jXgcc tiimage.c –o tiimage.outjj"jj\jjj}rZ(j@jAj]j]j]j]j]ujM9 jhj]r[jXgcc tiimage.c –o tiimage.outr\r]}r^(jUjjXubaubj )r_}r`(jUjj"jj\jj j}ra(jU)jO3Kj]j]j]jUj]j]jjujKjhj]rbj{)rc}rd(jX!To convert from .bin -> \_ti.bin jj_jj\jjj}re(j]j]j]j]j]ujNjhj]rfj)rg}rh(jX To convert from .bin -> \_ti.binjjcjj\jjj}ri(j]j]j]j]j]ujKj]rjjXTo convert from .bin -> _ti.binrkrl}rm(jX To convert from .bin -> \_ti.binjjgubaubaubaubj)rn}ro(jXLtiimage.out NONE .bin _ti.binjj"jj\jjj}rp(j@jAj]j]j]j]j]ujM? jhj]rqjXLtiimage.out NONE .bin _ti.binrrrs}rt(jUjjnubaubeubj)ru}rv(jUjj jj\jjj}rw(j]j]j]j]rxU#binary-format-conversion-in-windowsryaj]rzjlaujKjhj]r{(j)r|}r}(jX#Binary format conversion in Windowsr~jjujj\jjj}r(j]j]j]j]j]ujKjhj]rjX#Binary format conversion in Windowsrr}r(jj~jj|ubaubj )r}r(jUjjujj\jj j}r(jU)j]j]j]jUj]j]jjujKjhj]rj{)r}r(jXTo convert from .out -> .bin jjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXTo convert from .out -> .binrjjjj\jjj}r(j]j]j]j]j]ujKj]rjXTo convert from .out -> .binrr}r(jjjjubaubaubaubj)r}r(jX\/bin/arm-none-eabi-objcopy -O binary .out .binjjujj\jjj}r(j@jAj]j]j]j]j]ujMG jhj]rjX\/bin/arm-none-eabi-objcopy -O binary .out .binrr}r(jUjjubaubj)r}r(jXn2) To convert from .bin -> \_ti.bin. tiimage.exe is provided as prebuilt binary in starterware/tools/ti_image.jjujj\jjj}r(j]j]j]j]j]ujKjhj]rjXm2) To convert from .bin -> _ti.bin. tiimage.exe is provided as prebuilt binary in starterware/tools/ti_image.rr}r(jXn2) To convert from .bin -> \_ti.bin. tiimage.exe is provided as prebuilt binary in starterware/tools/ti_image.jjubaubj)r}r(jXLtiimage.exe NONE .bin _ti.binjjujj\jjj}r(j@jAj]j]j]j]j]ujMN jhj]rjXLtiimage.exe NONE .bin _ti.binrr}r(jUjjubaubjc)r}r(jUjjujj\jjfj}r(j]j]j]j]j]ujKjhj]rji)r}r(jUjlKjjjj\jjj}r(j]j]j]j]j]ujKjhj]ubaubeubeubeubj)r}r(jUjjJjj\jjj}r(j]j]j]j]rUboot-modes-supportedraj]rjKaujKjhj]r(j)r}r(jXBoot Modes supportedrjjjj\jjj}r(j]j]j]j]j]ujKjhj]rjXBoot Modes supportedrr}r(jjjjubaubj)r}r(jX]Following are the Boot Modes supported through AM335x/AM437x bootloader for the various EVMs.rjjjj\jjj}r‡(j]j]j]j]j]ujKjhj]rÇjX]Following are the Boot Modes supported through AM335x/AM437x bootloader for the various EVMs.rćrŇ}rƇ(jjjjubaubjy )rLJ}rȇ(jUjjjj\jj j}rɇ(j]j]j]j]j]ujNjhj]rʇj~ )rˇ}ṙ(jUj}r͇(j]j]j]j]j]UcolsKujjLJj]r·(j )rχ}rЇ(jUj}rч(j]j]j]j]j]UcolwidthK ujjˇj]jj ubj )r҇}rӇ(jUj}rԇ(j]j]j]j]j]UcolwidthK ujjˇj]jj ubj )rՇ}rև(jUj}rׇ(j]j]j]j]j]UcolwidthK ujjˇj]jj ubj )r؇}rه(jUj}rڇ(j]j]j]j]j]UcolwidthK ujjˇj]jj ubj )rۇ}r܇(jUj}r݇(j]j]j]j]j]UcolwidthK ujjˇj]jj ubj )rއ}r߇(jUj}r(j]j]j]j]j]UcolwidthK ujjˇj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjˇj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX **MMCSD**rjjjj\jjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXMMCSDrr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX**NAND**rjjjj\jjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXNANDr r }r (jUjjubajjubaubajj ubj )r }r (jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX **McSPI**rjj jj\jjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXMcSPIrr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r }r!(jX**QSPI**r"jjjj\jjj}r#(j]j]j]j]j]ujKj]r$j)r%}r&(jj"j}r'(j]j]j]j]j]ujj j]r(jXQSPIr)r*}r+(jUjj%ubajjubaubajj ubj )r,}r-(jUj}r.(j]j]j]j]j]ujjj]r/j)r0}r1(jX**UART**r2jj,jj\jjj}r3(j]j]j]j]j]ujKj]r4j)r5}r6(jj2j}r7(j]j]j]j]j]ujj0j]r8jXUARTr9r:}r;(jUjj5ubajjubaubajj ubejj ubj )r<}r=(jUj}r>(j]j]j]j]j]ujjj]r?(j )r@}rA(jUj}rB(j]j]j]j]j]ujj<j]rCj)rD}rE(jX**AM335x GPEVM**rFjj@jj\jjj}rG(j]j]j]j]j]ujKj]rHj)rI}rJ(jjFj}rK(j]j]j]j]j]ujjDj]rLjX AM335x GPEVMrMrN}rO(jUjjIubajjubaubajj ubj )rP}rQ(jUj}rR(j]j]j]j]j]ujj<j]rSj)rT}rU(jXYESrVjjPjj\jjj}rW(j]j]j]j]j]ujKj]rXjXYESrYrZ}r[(jjVjjTubaubajj ubj )r\}r](jUj}r^(j]j]j]j]j]ujj<j]r_j)r`}ra(jXYESrbjj\jj\jjj}rc(j]j]j]j]j]ujKj]rdjXYESrerf}rg(jjbjj`ubaubajj ubj )rh}ri(jUj}rj(j]j]j]j]j]ujj<j]rkj)rl}rm(jXYESrnjjhjj\jjj}ro(j]j]j]j]j]ujKj]rpjXYESrqrr}rs(jjnjjlubaubajj ubj )rt}ru(jUj}rv(j]j]j]j]j]ujj<j]rwj)rx}ry(jXNOrzjjtjj\jjj}r{(j]j]j]j]j]ujKj]r|jXNOr}r~}r(jjzjjxubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj<j]rj)r}r(jXYESrjjjj\jjj}r(j]j]j]j]j]ujKj]rjXYESrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX**AM335x ICEv2**rjjjj\jjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX AM335x ICEv2rr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXYESrjjjj\jjj}r(j]j]j]j]j]ujKj]rjXYESrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXNOrjjjj\jjj}r(j]j]j]j]j]ujKj]rjXNOrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXYESrjjjj\jjj}r(j]j]j]j]j]ujKj]rjXYESrrˆ}rÈ(jjjjubaubajj ubj )rĈ}rň(jUj}rƈ(j]j]j]j]j]ujjj]rLjj)rȈ}rɈ(jXNOrʈjjĈjj\jjj}rˈ(j]j]j]j]j]ujKj]r̈jXNOr͈rΈ}rψ(jjʈjjȈubaubajj ubj )rЈ}rш(jUj}r҈(j]j]j]j]j]ujjj]rӈj)rԈ}rՈ(jXNOrֈjjЈjj\jjj}r׈(j]j]j]j]j]ujKj]r؈jXNOrوrڈ}rۈ(jjֈjjԈubaubajj ubejj ubj )r܈}r݈(jUj}rވ(j]j]j]j]j]ujjj]r߈(j )r}r(jUj}r(j]j]j]j]j]ujj܈j]rj)r}r(jX**AM335x StarterKi t**rjjjj\jjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXAM335x StarterKi trr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj܈j]rj)r}r(jXYESrjjjj\jjj}r(j]j]j]j]j]ujKj]rjXYESrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj܈j]rj)r}r(jXNOrjjjj\jjj}r(j]j]j]j]j]ujKj]rjXNOrr}r(jjjjubaubajj ubj )r}r (jUj}r (j]j]j]j]j]ujj܈j]r j)r }r (jXNOrjjjj\jjj}r(j]j]j]j]j]ujKj]rjXNOrr}r(jjjj ubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj܈j]rj)r}r(jXNOrjjjj\jjj}r(j]j]j]j]j]ujKj]rjXNOrr}r(jjjjubaubajj ubj )r }r!(jUj}r"(j]j]j]j]j]ujj܈j]r#j)r$}r%(jXYESr&jj jj\jjj}r'(j]j]j]j]j]ujKj]r(jXYESr)r*}r+(jj&jj$ubaubajj ubejj ubj )r,}r-(jUj}r.(j]j]j]j]j]ujjj]r/(j )r0}r1(jUj}r2(j]j]j]j]j]ujj,j]r3j)r4}r5(jX**AM335x BeagleBon eBlack**r6jj0jj\jjj}r7(j]j]j]j]j]ujKj]r8j)r9}r:(jj6j}r;(j]j]j]j]j]ujj4j]r<jXAM335x BeagleBon eBlackr=r>}r?(jUjj9ubajjubaubajj ubj )r@}rA(jUj}rB(j]j]j]j]j]ujj,j]rCj)rD}rE(jXYESrFjj@jj\jjj}rG(j]j]j]j]j]ujKj]rHjXYESrIrJ}rK(jjFjjDubaubajj ubj )rL}rM(jUj}rN(j]j]j]j]j]ujj,j]rOj)rP}rQ(jXNOrRjjLjj\jjj}rS(j]j]j]j]j]ujKj]rTjXNOrUrV}rW(jjRjjPubaubajj ubj )rX}rY(jUj}rZ(j]j]j]j]j]ujj,j]r[j)r\}r](jXNOr^jjXjj\jjj}r_(j]j]j]j]j]ujKj]r`jXNOrarb}rc(jj^jj\ubaubajj ubj )rd}re(jUj}rf(j]j]j]j]j]ujj,j]rgj)rh}ri(jXNOrjjjdjj\jjj}rk(j]j]j]j]j]ujKj]rljXNOrmrn}ro(jjjjjhubaubajj ubj )rp}rq(jUj}rr(j]j]j]j]j]ujj,j]rsj)rt}ru(jXYESrvjjpjj\jjj}rw(j]j]j]j]j]ujKj]rxjXYESryrz}r{(jjvjjtubaubajj ubejj ubj )r|}r}(jUj}r~(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujj|j]rj)r}r(jX**AMIC110 ICE**rjjjj\jjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX AMIC110 ICErr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj|j]rj)r}r(jXNOrjjjj\jjj}r(j]j]j]j]j]ujKj]rjXNOrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj|j]rj)r}r(jXNOrjjjj\jjj}r(j]j]j]j]j]ujKj]rjXNOrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj|j]rj)r}r(jXYESrjjjj\jjj}r(j]j]j]j]j]ujKj]rjXYESrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj|j]rj)r}r(jXNOrjjjj\jjj}r(j]j]j]j]j]ujKj]rjXNOrr}r(jjjjubaubajj ubj )r}r(jUj}r‰(j]j]j]j]j]ujj|j]rÉj)rĉ}rʼn(jXYESrƉjjjj\jjj}rlj(j]j]j]j]j]ujKj]rȉjXYESrɉrʉ}rˉ(jjƉjjĉubaubajj ubejj ubj )r̉}r͉(jUj}rΉ(j]j]j]j]j]ujjj]rω(j )rЉ}rщ(jUj}r҉(j]j]j]j]j]ujj̉j]rӉj)rԉ}rՉ(jX**AM437x GPEVM**r։jjЉjj\jjj}r׉(j]j]j]j]j]ujKj]r؉j)rى}rډ(jj։j}rۉ(j]j]j]j]j]ujjԉj]r܉jX AM437x GPEVMr݉rމ}r߉(jUjjىubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj̉j]rj)r}r(jXYESrjjjj\jjj}r(j]j]j]j]j]ujKj]rjXYESrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj̉j]rj)r}r(jXNOrjjjj\jjj}r(j]j]j]j]j]ujKj]rjXNOrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj̉j]rj)r}r(jXNOrjjjj\jjj}r(j]j]j]j]j]ujKj]rjXNOrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj̉j]rj)r}r (jXNOr jjjj\jjj}r (j]j]j]j]j]ujKj]r jXNOr r}r(jj jjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj̉j]rj)r}r(jXYESrjjjj\jjj}r(j]j]j]j]j]ujKj]rjXYESrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r }r!(jUj}r"(j]j]j]j]j]ujjj]r#j)r$}r%(jX**AM437x IDK**r&jj jj\jjj}r'(j]j]j]j]j]ujKj]r(j)r)}r*(jj&j}r+(j]j]j]j]j]ujj$j]r,jX AM437x IDKr-r.}r/(jUjj)ubajjubaubajj ubj )r0}r1(jUj}r2(j]j]j]j]j]ujjj]r3j)r4}r5(jXYESr6jj0jj\jjj}r7(j]j]j]j]j]ujKj]r8jXYESr9r:}r;(jj6jj4ubaubajj ubj )r<}r=(jUj}r>(j]j]j]j]j]ujjj]r?j)r@}rA(jXNOrBjj<jj\jjj}rC(j]j]j]j]j]ujKj]rDjXNOrErF}rG(jjBjj@ubaubajj ubj )rH}rI(jUj}rJ(j]j]j]j]j]ujjj]rKj)rL}rM(jXNOrNjjHjj\jjj}rO(j]j]j]j]j]ujKj]rPjXNOrQrR}rS(jjNjjLubaubajj ubj )rT}rU(jUj}rV(j]j]j]j]j]ujjj]rWj)rX}rY(jXYESrZjjTjj\jjj}r[(j]j]j]j]j]ujKj]r\jXYESr]r^}r_(jjZjjXubaubajj ubj )r`}ra(jUj}rb(j]j]j]j]j]ujjj]rcj)rd}re(jXNOrfjj`jj\jjj}rg(j]j]j]j]j]ujKj]rhjXNOrirj}rk(jjfjjdubaubajj ubejj ubj )rl}rm(jUj}rn(j]j]j]j]j]ujjj]ro(j )rp}rq(jUj}rr(j]j]j]j]j]ujjlj]rsj)rt}ru(jX**AM437x StarterKi t**rvjjpjj\jjj}rw(j]j]j]j]j]ujKj]rxj)ry}rz(jjvj}r{(j]j]j]j]j]ujjtj]r|jXAM437x StarterKi tr}r~}r(jUjjyubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjlj]rj)r}r(jXYESrjjjj\jjj}r(j]j]j]j]j]ujKj]rjXYESrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjlj]rj)r}r(jXNOrjjjj\jjj}r(j]j]j]j]j]ujKj]rjXNOrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjlj]rj)r}r(jXNOrjjjj\jjj}r(j]j]j]j]j]ujKj]rjXNOrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjlj]rj)r}r(jXNOrjjjj\jjj}r(j]j]j]j]j]ujKj]rjXNOrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjlj]rj)r}r(jXNOrjjjj\jjj}r(j]j]j]j]j]ujKj]rjXNOrr}r(jjjjubaubajj ubejj ubejj ubejj ubaubjc)r}r(jUjjjj\jjfj}r(j]j]j]j]j]ujKjhj]rji)r}r(jUjlKjjjj\jjj}rŠ(j]j]j]j]j]ujKjhj]ubaubeubj)rÊ}rĊ(jUjjJjj\jjj}rŊ(j]j]j]j]rƊUbuilding-the-bootloaderrNJaj]rȊhaujKjhj]rɊ(j)rʊ}rˊ(jXBuilding the Bootloaderr̊jjÊjj\jjj}r͊(j]j]j]j]j]ujKjhj]rΊjXBuilding the BootloaderrϊrЊ}rъ(jj̊jjʊubaubj )rҊ}rӊ(jUjjÊjj\jj# j}rԊ(j]j]j]j]j]ujNjhj]rՊ(j& )r֊}r׊(jX**Pre-requisite:** Setup SDK build environment as described in article `Setup_Environment `__ jjҊjj\jj) j}r؊(j]j]j]j]j]ujKj]rي(j, )rڊ}rۊ(jXF**Pre-requisite:** Setup SDK build environment as described in articler܊jj֊jj\jj0 j}r݊(j]j]j]j]j]ujKj]rފ(j)rߊ}r(jX**Pre-requisite:**j}r(j]j]j]j]j]ujjڊj]rjXPre-requisite:rr}r(jUjjߊubajjubjX4 Setup SDK build environment as described in articlerr}r(jX4 Setup SDK build environment as described in articlejjڊubeubj6 )r}r(jUj}r(j]j]j]j]j]ujj֊j]rj)r}r(jX=`Setup_Environment `__rjjjj\jjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(UnameXSetup_EnvironmentjX%index_overview.html#setup-environmentj]j]j]j]j]ujjj]rjXSetup_Environmentrr}r(jUjjubajjubaubajjQ ubeubj& )r}r(jXChange working directory to the packages/ti/starterware directory cd /pdk__/packages/ti/starterware jjҊjj\jj) j}r(j]j]j]j]j]ujKjhj]r(j, )r}r(jXAChange working directory to the packages/ti/starterware directoryrjjjj\jj0 j}r(j]j]j]j]j]ujKj]rjXAChange working directory to the packages/ti/starterware directoryrr}r(jjjjubaubj6 )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r }r (jXDcd /pdk__/packages/ti/starterwarer jjjj\jjj}r (j]j]j]j]j]ujKj]r jXDcd /pdk__/packages/ti/starterwarerr}r(jj jj ubaubajjQ ubeubeubj)r}r(jXNOTE: For the starterware build targets below, the parallel make option (-j) is not supported. Please ensure that the below are built without parallel make option.rjjÊjj\jjj}r(j]j]j]j]j]ujKjhj]rjXNOTE: For the starterware build targets below, the parallel make option (-j) is not supported. Please ensure that the below are built without parallel make option.rr}r(jjjjubaubj)r}r(jUjjÊjj\jjj}r(j]j]j]j]rUnormal-operation-of-bootloaderraj]rh\aujKjhj]r(j)r }r!(jXNormal Operation of Bootloader:r"jjjj\jjj}r#(j]j]j]j]j]ujKjhj]r$jXNormal Operation of Bootloader:r%r&}r'(jj"jj ubaubj)r(}r)(jXBootloading an application from flash into DDR memory as in case of TI evaluation platforms is described as normal operation mode for the bootloader. This is the default behavior of the bootloader and can be built using the following command in starterware.r*jjjj\jjj}r+(j]j]j]j]j]ujKjhj]r,jXBootloading an application from flash into DDR memory as in case of TI evaluation platforms is described as normal operation mode for the bootloader. This is the default behavior of the bootloader and can be built using the following command in starterware.r-r.}r/(jj*jj(ubaubj)r0}r1(jXigmake bootloader BUILDCFG=boot BOOTMODE= PLATFORM= PROFILE= -s KW_BUILD=nojjjj\jjj}r2(j@jAj]j]j]j]j]ujM jhj]r3jXigmake bootloader BUILDCFG=boot BOOTMODE= PLATFORM= PROFILE= -s KW_BUILD=nor4r5}r6(jUjj0ubaubjt)r7}r8(jUjjjj\jjwj}r9(jyX-j]j]j]j]j]ujMjhj]r:(j{)r;}r<(jXcBOOT_MODE: mcspi, nand, qspi, mmcsd, uart (Check supported boot modes for your evaluation platform)jj7jj\jjj}r=(j]j]j]j]j]ujNjhj]r>j)r?}r@(jXcBOOT_MODE: mcspi, nand, qspi, mmcsd, uart (Check supported boot modes for your evaluation platform)rAjj;jj\jjj}rB(j]j]j]j]j]ujMj]rCjXcBOOT_MODE: mcspi, nand, qspi, mmcsd, uart (Check supported boot modes for your evaluation platform)rDrE}rF(jjAjj?ubaubaubj{)rG}rH(jX_EVM: am335x-evm (for all AM335x/AMIC110 based boards), am43xx-evm (for all AM43xx based boards)rIjj7jj\jjj}rJ(j]j]j]j]j]ujNjhj]rKj)rL}rM(jjIjjGjj\jjj}rN(j]j]j]j]j]ujMj]rOjX_EVM: am335x-evm (for all AM335x/AMIC110 based boards), am43xx-evm (for all AM43xx based boards)rPrQ}rR(jjIjjLubaubaubj{)rS}rT(jXBUILD_PROFILE: debug, release jj7jj\jjj}rU(j]j]j]j]j]ujNjhj]rVj)rW}rX(jXBUILD_PROFILE: debug, releaserYjjSjj\jjj}rZ(j]j]j]j]j]ujMj]r[jXBUILD_PROFILE: debug, releaser\r]}r^(jjYjjWubaubaubeubeubj)r_}r`(jUjjÊjj\jjj}ra(j]j]j]j]rbUadditional-build-optionsrcaj]rdjaujM jhj]re(j)rf}rg(jXAdditional Build Optionsrhjj_jj\jjj}ri(j]j]j]j]j]ujM jhj]rjjXAdditional Build Optionsrkrl}rm(jjhjjfubaubj)rn}ro(jXYThe build options listed below are currently supported only for AMIC110/AM335x ICE Users.rpjj_jj\jjj}rq(j]j]j]j]j]ujM jhj]rrjXYThe build options listed below are currently supported only for AMIC110/AM335x ICE Users.rsrt}ru(jjpjjnubaubjt)rv}rw(jUjj_jj\jjwj}rx(jyX-j]j]j]j]j]ujMjhj]ryj{)rz}r{(jX$**DDR less Application boot setup** jjvjj\jjj}r|(j]j]j]j]j]ujNjhj]r}j)r~}r(jX#**DDR less Application boot setup**rjjzjj\jjj}r(j]j]j]j]j]ujMj]rj)r}r(jjj}r(j]j]j]j]j]ujj~j]rjXDDR less Application boot setuprr}r(jUjjubajjubaubaubaubj)r}r(jXgmake bootloader BUILDCFG=boot BOOTMODE=mcspi PLATFORM=amic110-ddrless PROFILE=debug -s KW_BUILD=no USE_DDR=no gmake bootloader BUILDCFG=boot BOOTMODE=mcspi PLATFORM=amic110-ddrless PROFILE=release -s KW_BUILD=no USE_DDR=nojj_jj\jjj}r(j@jAj]j]j]j]j]ujM jhj]rjXgmake bootloader BUILDCFG=boot BOOTMODE=mcspi PLATFORM=amic110-ddrless PROFILE=debug -s KW_BUILD=no USE_DDR=no gmake bootloader BUILDCFG=boot BOOTMODE=mcspi PLATFORM=amic110-ddrless PROFILE=release -s KW_BUILD=no USE_DDR=norr}r(jUjjubaubj)r}r(jXThis option builds an ultra light weight (<10 KB) bootloader for cost optimized application that doesn't use external DDR memory.rjj_jj\jjj}r(j]j]j]j]j]ujMjhj]rjXThis option builds an ultra light weight (<10 KB) bootloader for cost optimized application that doesn't use external DDR memory.rr}r(jjjjubaubjt)r}r(jUjj_jj\jjwj}r(jyX-j]j]j]j]j]ujMjhj]rj{)r}r(jX**PRU/ICSS Enable in SBL** jjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX**PRU/ICSS Enable in SBL**rjjjj\jjj}r(j]j]j]j]j]ujMj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXPRU/ICSS Enable in SBLrr}r(jUjjubajjubaubaubaubj)r}r(jXgmake bootloader BUILDCFG=boot BOOTMODE=mcspi PLATFORM=am335x-evm PROFILE=debug -s KW_BUILD=no ENABLE_PRU=yes gmake bootloader BUILDCFG=boot BOOTMODE=mcspi PLATFORM=am335x-evm PROFILE=release -s KW_BUILD=no ENABLE_PRU=yesjj_jj\jjj}r(j@jAj]j]j]j]j]ujM jhj]rjXgmake bootloader BUILDCFG=boot BOOTMODE=mcspi PLATFORM=am335x-evm PROFILE=debug -s KW_BUILD=no ENABLE_PRU=yes gmake bootloader BUILDCFG=boot BOOTMODE=mcspi PLATFORM=am335x-evm PROFILE=release -s KW_BUILD=no ENABLE_PRU=yesrr}r(jUjjubaubj)r}r(jXThis feature is required in application that need to quick wake up of ICSS/PRU cores. The PRU cores can be woken up and loaded from the SBL by combining the ENABLE_PRU and BIN_LOAD arguments.rjj_jj\jjj}r(j]j]j]j]j]ujMjhj]rjXThis feature is required in application that need to quick wake up of ICSS/PRU cores. The PRU cores can be woken up and loaded from the SBL by combining the ENABLE_PRU and BIN_LOAD arguments.rr}r(jjjjubaubjt)r}r(jUjj_jj\jjwj}r(jyX-j]j]j]j]j]ujM#jhj]rj{)r}r(jX(**Load additional binaries from flash** jjjj\jjj}r‹(j]j]j]j]j]ujNjhj]rËj)rċ}rŋ(jX'**Load additional binaries from flash**rƋjjjj\jjj}rNj(j]j]j]j]j]ujM#j]rȋj)rɋ}rʋ(jjƋj}rˋ(j]j]j]j]j]ujjċj]r̋jX#Load additional binaries from flashr͋r΋}rϋ(jUjjɋubajjubaubaubaubj)rЋ}rы(jXgmake bootloader BUILDCFG=boot BOOTMODE=mcspi PLATFORM=am335x-evm PROFILE=debug -s KW_BUILD=no BIN_LOAD=yes gmake bootloader BUILDCFG=boot BOOTMODE=mcspi PLATFORM=am335x-evm PROFILE=release -s KW_BUILD=no BIN_LOAD=yesjj_jj\jjj}rҋ(j@jAj]j]j]j]j]ujM jhj]rӋjXgmake bootloader BUILDCFG=boot BOOTMODE=mcspi PLATFORM=am335x-evm PROFILE=debug -s KW_BUILD=no BIN_LOAD=yes gmake bootloader BUILDCFG=boot BOOTMODE=mcspi PLATFORM=am335x-evm PROFILE=release -s KW_BUILD=no BIN_LOAD=yesrԋrՋ}r֋(jUjjЋubaubj)r׋}r؋(jXThe location of binaries in offset is configured using sbl_flash_offset_cfg.h in the bootloader source. Users are required to use TIIMAGE tool to append an header to the binary so that the bootloader knows the location and size of the binary to be loaded.rًjj_jj\jjj}rڋ(j]j]j]j]j]ujM*jhj]rۋjXThe location of binaries in offset is configured using sbl_flash_offset_cfg.h in the bootloader source. Users are required to use TIIMAGE tool to append an header to the binary so that the bootloader knows the location and size of the binary to be loaded.r܋r݋}rދ(jjًjj׋ubaubeubj)rߋ}r(jUjjÊjj\jjj}r(j]j]j]j]rU3special-build-option-for-industrial-ddrless-bootingraj]rhaujM0jhj]r(j)r}r(jX3Special Build Option for Industrial DDRless Bootingrjjߋjj\jjj}r(j]j]j]j]j]ujM0jhj]rjX3Special Build Option for Industrial DDRless Bootingrr}r(jjjjubaubj)r}r(jXThe AMIC110 DDRLESS platform provides a superset flag to enable all the above features and build the bootloader. The superset build is invoked using **BUILD_ICSS_DDRLESS_BOOT=yes** as shown below:jjߋjj\jjj}r(j]j]j]j]j]ujM2jhj]r(jXThe AMIC110 DDRLESS platform provides a superset flag to enable all the above features and build the bootloader. The superset build is invoked using rr}r(jXThe AMIC110 DDRLESS platform provides a superset flag to enable all the above features and build the bootloader. The superset build is invoked using jjubj)r}r(jX**BUILD_ICSS_DDRLESS_BOOT=yes**j}r(j]j]j]j]j]ujjj]rjXBUILD_ICSS_DDRLESS_BOOT=yesrr}r(jUjjubajjubjX as shown below:rr}r(jX as shown below:jjubeubj)r}r(jXgmake bootloader BUILDCFG=boot BOOTMODE=mcspi PLATFORM=amic110-ddrless PROFILE=debug -s KW_BUILD=no BUILD_ICSS_DDRLESS_BOOT=yes gmake bootloader BUILDCFG=boot BOOTMODE=mcspi PLATFORM=amic110-ddrless PROFILE=release -s KW_BUILD=no BUILD_ICSS_DDRLESS_BOOT=yesjjߋjj\jjj}r(j@jAj]j]j]j]j]ujM jhj]rjXgmake bootloader BUILDCFG=boot BOOTMODE=mcspi PLATFORM=amic110-ddrless PROFILE=debug -s KW_BUILD=no BUILD_ICSS_DDRLESS_BOOT=yes gmake bootloader BUILDCFG=boot BOOTMODE=mcspi PLATFORM=amic110-ddrless PROFILE=release -s KW_BUILD=no BUILD_ICSS_DDRLESS_BOOT=yesrr}r(jUjjubaubj)r}r(jXPrebuilt binaries inside the Processor SDK RTOS for AMIC110-DDRLESS will be configured using this option to allow for testing of cost optimized industrial use case.rjjߋjj\jjj}r (j]j]j]j]j]ujM<jhj]r jXPrebuilt binaries inside the Processor SDK RTOS for AMIC110-DDRLESS will be configured using this option to allow for testing of cost optimized industrial use case.r r }r (jjjjubaubjc)r}r(jUjjߋjj\jjfj}r(j]j]j]j]j]ujM@jhj]rji)r}r(jUjlKjjjj\jjj}r(j]j]j]j]j]ujKjhj]ubaubeubeubj)r}r(jUjjJjj\jjj}r(j]j]j]j]rUboot-mode-settingsraj]rhaujMCjhj]r(j)r}r(jXBoot Mode settingsrjjjj\jjj}r(j]j]j]j]j]ujMCjhj]r jXBoot Mode settingsr!r"}r#(jjjjubaubj)r$}r%(jXBoot mode settings for supported AM335x and AM437x boards can be found in the applicable `EVM Hardware User's Guide `__.jjjj\jjj}r&(j]j]j]j]j]ujMEjhj]r'(jXYBoot mode settings for supported AM335x and AM437x boards can be found in the applicable r(r)}r*(jXYBoot mode settings for supported AM335x and AM437x boards can be found in the applicable jj$ubj)r+}r,(jX\`EVM Hardware User's Guide `__j}r-(UnameXEVM Hardware User's GuidejX<index_release_specific.html#supported-platforms-and-versionsj]j]j]j]j]ujj$j]r.jXEVM Hardware User's Guider/r0}r1(jUjj+ubajjubjX.r2}r3(jX.jj$ubeubeubj)r4}r5(jUjKjjJjj\jjj}r6(j]r7jaj]j]j]r8Uid68r9aj]ujMIjhj]r:(j)r;}r<(jX Boot Modesr=jj4jj\jjj}r>(j]j]j]j]j]ujMIjhj]r?jX Boot Modesr@rA}rB(jj=jj;ubaubj)rC}rD(jUjKjj4jj\jjj}rE(j]rFXbooting via sd cardrGaj]j]j]rHUbooting-via-sd-cardrIaj]ujMLjhj]rJ(j)rK}rL(jXBooting Via SD CardrMjjCjj\jjj}rN(j]j]j]j]j]ujMLjhj]rOjXBooting Via SD CardrPrQ}rR(jjMjjKubaubj)rS}rT(jX(Booting from SD Card involves two steps.rUjjCjj\jjj}rV(j]j]j]j]j]ujMNjhj]rWjX(Booting from SD Card involves two steps.rXrY}rZ(jjUjjSubaubj )r[}r\(jUjjCjj\jj j}r](jU.j]j]j]jUj]j]jjujMPjhj]r^(j{)r_}r`(jXPreparing SD card.rajj[jj\jjj}rb(j]j]j]j]j]ujNjhj]rcj)rd}re(jjajj_jj\jjj}rf(j]j]j]j]j]ujMPj]rgjXPreparing SD card.rhri}rj(jjajjdubaubaubj{)rk}rl(jXBooting target. jj[jj\jjj}rm(j]j]j]j]j]ujNjhj]rnj)ro}rp(jXBooting target.rqjjkjj\jjj}rr(j]j]j]j]j]ujMQj]rsjXBooting target.rtru}rv(jjqjjoubaubaubeubj)rw}rx(jUjjCjj\jjj}ry(j]j]j]j]rzUpreparing-sd-cardr{aj]r|jaujMTjhj]r}(j)r~}r(jXPreparing SD cardrjjwjj\jjj}r(j]j]j]j]j]ujMTjhj]rjXPreparing SD cardrr}r(jjjj~ubaubj )r}r(jUjjwjj\jj j}r(jU.j]j]j]jUj]j]jjujMVjhj]r(j{)r}r(jXTo boot target the SD card should be bootable. Follow the steps at `Creating bootable SD card in windows `__ or `Creating bootable SD card in Linux `__.jjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXTo boot target the SD card should be bootable. Follow the steps at `Creating bootable SD card in windows `__ or `Creating bootable SD card in Linux `__.jjjj\jjj}r(j]j]j]j]j]ujMVj]r(jXCTo boot target the SD card should be bootable. Follow the steps at rr}r(jXCTo boot target the SD card should be bootable. Follow the steps at jjubj)r}r(jX]`Creating bootable SD card in windows `__j}r(UnameX$Creating bootable SD card in windowsjX2index_overview.html#windows-sd-card-creation-guidej]j]j]j]j]ujjj]rjX$Creating bootable SD card in windowsrr}r(jUjjubajjubjX or rr}r(jX or jjubj)r}r(jXY`Creating bootable SD card in Linux `__j}r(UnameX"Creating bootable SD card in LinuxjX0index_overview.html#linux-sd-card-creation-guidej]j]j]j]j]ujjj]rjX"Creating bootable SD card in Linuxrr}r(jUjjubajjubjX.r}r(jX.jjubeubaubj{)r}r(jXrDelete the "*MLO*" and "*app*" in the bootable SD card which are created in the process of making the SD bootable.jjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXrDelete the "*MLO*" and "*app*" in the bootable SD card which are created in the process of making the SD bootable.jjjj\jjj}r(j]j]j]j]j]ujMYj]r(jX Delete the "rr}r(jX Delete the "jjubjM)r}r(jX*MLO*j}r(j]j]j]j]j]ujjj]rjXMLOrr}r(jUjjubajjUubjX" and "rr}r(jX" and "jjubjM)r}r(jX*app*j}r(j]j]j]j]j]ujjj]rjXapprrŒ}rÌ(jUjjubajjUubjXU" in the bootable SD card which are created in the process of making the SD bootable.rČrŌ}rƌ(jXU" in the bootable SD card which are created in the process of making the SD bootable.jjubeubaubj{)rnj}rȌ(jXBootloader images with ti header (_ti.bin)should be renamed to "*MLO*". Bootloader images are located at *jjjj\jjj}rɌ(j]j]j]j]j]ujNjhj]rʌj)rˌ}ř(jXBootloader images with ti header (_ti.bin)should be renamed to "*MLO*". Bootloader images are located at *jjnjjj\jjj}r͌(j]j]j]j]j]ujM[j]rΌ(jXRBootloader images with ti header (_ti.bin)should be renamed to "rόrЌ}rь(jXRBootloader images with ti header (_ti.bin)should be renamed to "jjˌubjM)rҌ}rӌ(jX*MLO*j}rԌ(j]j]j]j]j]ujjˌj]rՌjXMLOr֌r׌}r،(jUjjҌubajjUubjX$". Bootloader images are located at rٌrڌ}rی(jX$". Bootloader images are located at jjˌubjM)r܌}r݌(jXL*r}r(jX>jjˌubeubaubj{)r}r(jXhSimilarly the converted application binary image has to be renamed to "*app*" from "*_ti.bin*"jjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXhSimilarly the converted application binary image has to be renamed to "*app*" from "*_ti.bin*"jjjj\jjj}r(j]j]j]j]j]ujM^j]r(jXGSimilarly the converted application binary image has to be renamed to "rr}r(jXGSimilarly the converted application binary image has to be renamed to "jjubjM)r}r(jX*app*j}r(j]j]j]j]j]ujjj]rjXapprr}r(jUjjubajjUubjX" from "rr}r(jX" from "jjubjM)r}r(jX*_ti.bin*j}r(j]j]j]j]j]ujjj]rjX_ti.binrr}r(jUjjubajjUubjX"r}r(jX"jjubeubaubj{)r}r(jXYCopy both the boot loader image "*MLO*" and the application image "*app*" to the SD card.jjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXYCopy both the boot loader image "*MLO*" and the application image "*app*" to the SD card.jjjj\jjj}r (j]j]j]j]j]ujM`j]r (jX!Copy both the boot loader image "r r }r (jX!Copy both the boot loader image "jjubjM)r}r(jX*MLO*j}r(j]j]j]j]j]ujjj]rjXMLOrr}r(jUjjubajjUubjX" and the application image "rr}r(jX" and the application image "jjubjM)r}r(jX*app*j}r(j]j]j]j]j]ujjj]rjXapprr}r(jUjjubajjUubjX" to the SD card.rr }r!(jX" to the SD card.jjubeubaubj{)r"}r#(jX(The SD card is ready for use on target. jjjj\jjj}r$(j]j]j]j]j]ujNjhj]r%j)r&}r'(jX'The SD card is ready for use on target.r(jj"jj\jjj}r)(j]j]j]j]j]ujMbj]r*jX'The SD card is ready for use on target.r+r,}r-(jj(jj&ubaubaubeubeubj)r.}r/(jUjjCjj\jjj}r0(j]j]j]j]r1Ubooting-targetr2aj]r3haujMejhj]r4(j)r5}r6(jXBooting targetr7jj.jj\jjj}r8(j]j]j]j]j]ujMejhj]r9jXBooting targetr:r;}r<(jj7jj5ubaubj )r=}r>(jUjj.jj\jj j}r?(jU.j]j]j]jUj]j]jjujMgjhj]r@(j{)rA}rB(jXInsert SD card to the base board SD slot. Connect a UART cable to a host running a serial terminal application (teraterm/hyperterminal) with 115200 baud, 8bit, No parity and 1 STOP bit configuration.jj=jj\jjj}rC(j]j]j]j]j]ujNjhj]rDj)rE}rF(jXInsert SD card to the base board SD slot. Connect a UART cable to a host running a serial terminal application (teraterm/hyperterminal) with 115200 baud, 8bit, No parity and 1 STOP bit configuration.rGjjAjj\jjj}rH(j]j]j]j]j]ujMgj]rIjXInsert SD card to the base board SD slot. Connect a UART cable to a host running a serial terminal application (teraterm/hyperterminal) with 115200 baud, 8bit, No parity and 1 STOP bit configuration.rJrK}rL(jjGjjEubaubaubj{)rM}rN(jX<Configure the board for SD Boot mode #. SD instance 0 (on base board) is available in all profiles. #. SD instance 0 boot mode needs to appropriately set. For SD boot to be selected first, SD boot should appear first in the boot device list in the boot mode. If any other boot mode is selected, even if a SD boot card is inserted, and does not appear first in the list, the first available sane boot image (like NAND or SPI etc) is booted and SD is not selected. Only if no sane boot image is found in the first devices, SD boot image will be selected. jj=jNjjj}rO(j]j]j]j]j]ujNjhj]rP(j)rQ}rR(jX$Configure the board for SD Boot moderSjjMjj\jjj}rT(j]j]j]j]j]ujMjj]rUjX$Configure the board for SD Boot moderVrW}rX(jjSjjQubaubj )rY}rZ(jUj}r[(jU.j]j]j]jUj]j]jjujjMj]r\(j{)r]}r^(jX;SD instance 0 (on base board) is available in all profiles.r_j}r`(j]j]j]j]j]ujjYj]raj)rb}rc(jj_jj]jj\jjj}rd(j]j]j]j]j]ujMlj]rejX;SD instance 0 (on base board) is available in all profiles.rfrg}rh(jj_jjbubaubajjubj{)ri}rj(jXSD instance 0 boot mode needs to appropriately set. For SD boot to be selected first, SD boot should appear first in the boot device list in the boot mode. If any other boot mode is selected, even if a SD boot card is inserted, and does not appear first in the list, the first available sane boot image (like NAND or SPI etc) is booted and SD is not selected. Only if no sane boot image is found in the first devices, SD boot image will be selected. j}rk(j]j]j]j]j]ujjYj]rlj)rm}rn(jXSD instance 0 boot mode needs to appropriately set. For SD boot to be selected first, SD boot should appear first in the boot device list in the boot mode. If any other boot mode is selected, even if a SD boot card is inserted, and does not appear first in the list, the first available sane boot image (like NAND or SPI etc) is booted and SD is not selected. Only if no sane boot image is found in the first devices, SD boot image will be selected.rojjijj\jjj}rp(j]j]j]j]j]ujMmj]rqjXSD instance 0 boot mode needs to appropriately set. For SD boot to be selected first, SD boot should appear first in the boot device list in the boot mode. If any other boot mode is selected, even if a SD boot card is inserted, and does not appear first in the list, the first available sane boot image (like NAND or SPI etc) is booted and SD is not selected. Only if no sane boot image is found in the first devices, SD boot image will be selected.rrrs}rt(jjojjmubaubajjubejj ubeubj{)ru}rv(jXDOnce SD boot image is chosen, the *MLO* is first detected and copied and executed from the OCMC0 RAM. The *MLO* then copies the application image (*app*) from the card to the SDRAM and passes the control to the application. If the process is successful, messages identifying board and SoC will appear on the serial console. jj=jj\jjj}rw(j]j]j]j]j]ujNjhj]rxj)ry}rz(jXCOnce SD boot image is chosen, the *MLO* is first detected and copied and executed from the OCMC0 RAM. The *MLO* then copies the application image (*app*) from the card to the SDRAM and passes the control to the application. If the process is successful, messages identifying board and SoC will appear on the serial console.jjujj\jjj}r{(j]j]j]j]j]ujMuj]r|(jX"Once SD boot image is chosen, the r}r~}r(jX"Once SD boot image is chosen, the jjyubjM)r}r(jX*MLO*j}r(j]j]j]j]j]ujjyj]rjXMLOrr}r(jUjjubajjUubjXC is first detected and copied and executed from the OCMC0 RAM. The rr}r(jXC is first detected and copied and executed from the OCMC0 RAM. The jjyubjM)r}r(jX*MLO*j}r(j]j]j]j]j]ujjyj]rjXMLOrr}r(jUjjubajjUubjX$ then copies the application image (rr}r(jX$ then copies the application image (jjyubjM)r}r(jX*app*j}r(j]j]j]j]j]ujjyj]rjXapprr}r(jUjjubajjUubjX) from the card to the SDRAM and passes the control to the application. If the process is successful, messages identifying board and SoC will appear on the serial console.rr}r(jX) from the card to the SDRAM and passes the control to the application. If the process is successful, messages identifying board and SoC will appear on the serial console.jjyubeubaubeubj)r}r(jX9After this the application will take control and execute.rjj.jj\jjj}r(j]j]j]j]j]ujM{jhj]rjX9After this the application will take control and execute.rr}r(jjjjubaubj)r}r(jXx**NOTE:** If board has boot mode selection pins, choose proper boot mode selection pins from hardware reference manuals.jj.jj\jjj}r(j]j]j]j]j]ujM}jhj]r(j)r}r(jX **NOTE:**j}r(j]j]j]j]j]ujjj]rjXNOTE:rr}r(jUjjubajjubjXo If board has boot mode selection pins, choose proper boot mode selection pins from hardware reference manuals.rr}r(jXo If board has boot mode selection pins, choose proper boot mode selection pins from hardware reference manuals.jjubeubjc)r}r(jUjj.jj\jjfj}r(j]j]j]j]j]ujMjhj]rji)r}r(jX]If the boards have no boot mode selection pins and a valid boot image is present on McSPI flash, booting will happen from McSPI flash. Erase McSPI flash in such cases to boot from SD card. Refer to `Booting Via McSPI `__ for how to rease McSPI flash. The boot sequence depends on ROM bootloader.jlKjjjj\jjj}r(j]j]j]j]j]ujMjhj]r(jXIf the boards have no boot mode selection pins and a valid boot image is present on McSPI flash, booting will happen from McSPI flash. Erase McSPI flash in such cases to boot from SD card. Refer to rr}r(jXIf the boards have no boot mode selection pins and a valid boot image is present on McSPI flash, booting will happen from McSPI flash. Erase McSPI flash in such cases to boot from SD card. Refer to jjubj)r}r(jXL`Booting Via McSPI `__j}r(UnameXBooting Via McSPIjX4index_Foundational_Components.html#booting-via-mcspij]j]j]j]j]ujjj]rjXBooting Via McSPIrÍrč}rō(jUjjubajjubjXK for how to rease McSPI flash. The boot sequence depends on ROM bootloader.rƍrǍ}rȍ(jXK for how to rease McSPI flash. The boot sequence depends on ROM bootloader.jjubeubaubeubeubj)rɍ}rʍ(jUjKjj4jj\jjj}rˍ(j]r̍Xbooting via qspir͍aj]j]j]r΍Ubooting-via-qspirύaj]ujMjhj]rЍ(j)rэ}rҍ(jXBooting Via QSPIrӍjjɍjj\jjj}rԍ(j]j]j]j]j]ujMjhj]rՍjXBooting Via QSPIr֍r׍}r؍(jjӍjjэubaubj)rٍ}rڍ(jX+Booting from QSPI flash involves two steps-rۍjjɍjj\jjj}r܍(j]j]j]j]j]ujMjhj]rݍjX+Booting from QSPI flash involves two steps-rލrߍ}r(jjۍjjٍubaubj )r}r(jUjjɍjj\jj j}r(jU.j]j]j]jUj]j]jjujMjhj]r(j{)r}r(jXPreparing Flash Devicerjjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj\jjj}r(j]j]j]j]j]ujMj]rjXPreparing Flash Devicerr}r(jjjjubaubaubj{)r}r(jXBooting target. jjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXBooting target.rjjjj\jjj}r(j]j]j]j]j]ujMj]rjXBooting target.rr}r(jjjjubaubaubeubj)r}r(jUjKjjɍjj\jjj}r(j]rXpreparing flash deviceraj]j]j]rUpreparing-flash-deviceraj]ujMjhj]r(j)r}r(jXPreparing Flash Devicerjjjj\jjj}r(j]j]j]j]j]ujMjhj]r jXPreparing Flash Devicer r }r (jjjjubaubj)r }r(jXOProcedure relies on contents being copied to SD card. Additional details below:rjjjj\jjj}r(j]j]j]j]j]ujMjhj]rjXOProcedure relies on contents being copied to SD card. Additional details below:rr}r(jjjj ubaubj )r}r(jUjjjj\jj j}r(jU.j]j]j]jUj]j]jjujMjhj]r(j{)r}r(jXeCopy bootloader image(bootloader_boot_qspi_a9host_debug.bin rename) and app image("_ti.bin") into the SD card. The file names have to be renamed in such a way that the length of name is less than 9 characters. Any file name less than 9 characters can be used. Rename the bootloader file to 'boot' and application image to 'app' with no extensions.jjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXeCopy bootloader image(bootloader_boot_qspi_a9host_debug.bin rename) and app image("_ti.bin") into the SD card. The file names have to be renamed in such a way that the length of name is less than 9 characters. Any file name less than 9 characters can be used. Rename the bootloader file to 'boot' and application image to 'app' with no extensions.rjjjj\jjj}r (j]j]j]j]j]ujMj]r!jXeCopy bootloader image(bootloader_boot_qspi_a9host_debug.bin rename) and app image("_ti.bin") into the SD card. The file names have to be renamed in such a way that the length of name is less than 9 characters. Any file name less than 9 characters can be used. Rename the bootloader file to 'boot' and application image to 'app' with no extensions.r"r#}r$(jjjjubaubaubj{)r%}r&(jX Copy the 'config' file into the SD card which will contain the names of the image to be flashed and the offset. A sample config file can be found at * directory*. Do not change name of the **config** file. **NOTE:** "config" file can be used without any modifications if bootloader and application images are renamed to "boot" and "app". **NOTE:** Do not rename bootloader to be copied to SD card as "*MLO*", as MMCSD bootloader expects "*MLO*" and "*app*" to boot.jjjj\jjj}r'(j]j]j]j]j]ujNjhj]r(j)r)}r*(jX Copy the 'config' file into the SD card which will contain the names of the image to be flashed and the offset. A sample config file can be found at * directory*. Do not change name of the **config** file. **NOTE:** "config" file can be used without any modifications if bootloader and application images are renamed to "boot" and "app". **NOTE:** Do not rename bootloader to be copied to SD card as "*MLO*", as MMCSD bootloader expects "*MLO*" and "*app*" to boot.jj%jj\jjj}r+(j]j]j]j]j]ujMj]r,(jXCopy the 'config' file into the SD card which will contain the names of the image to be flashed and the offset. A sample config file can be found at r-r.}r/(jXCopy the 'config' file into the SD card which will contain the names of the image to be flashed and the offset. A sample config file can be found at jj)ubjM)r0}r1(jXH* directory*j}r2(j]j]j]j]j]ujj)j]r3jXF directoryr4r5}r6(jUjj0ubajjUubjX. Do not change name of the r7r8}r9(jX. Do not change name of the jj)ubj)r:}r;(jX **config**j}r<(j]j]j]j]j]ujj)j]r=jXconfigr>r?}r@(jUjj:ubajjubjX file. rArB}rC(jX file. jj)ubj)rD}rE(jX **NOTE:**j}rF(j]j]j]j]j]ujj)j]rGjXNOTE:rHrI}rJ(jUjjDubajjubjX{ "config" file can be used without any modifications if bootloader and application images are renamed to "boot" and "app". rKrL}rM(jX{ "config" file can be used without any modifications if bootloader and application images are renamed to "boot" and "app". jj)ubj)rN}rO(jX **NOTE:**j}rP(j]j]j]j]j]ujj)j]rQjXNOTE:rRrS}rT(jUjjNubajjubjX6 Do not rename bootloader to be copied to SD card as "rUrV}rW(jX6 Do not rename bootloader to be copied to SD card as "jj)ubjM)rX}rY(jX*MLO*j}rZ(j]j]j]j]j]ujj)j]r[jXMLOr\r]}r^(jUjjXubajjUubjX ", as MMCSD bootloader expects "r_r`}ra(jX ", as MMCSD bootloader expects "jj)ubjM)rb}rc(jX*MLO*j}rd(j]j]j]j]j]ujj)j]rejXMLOrfrg}rh(jUjjbubajjUubjX" and "rirj}rk(jX" and "jj)ubjM)rl}rm(jX*app*j}rn(j]j]j]j]j]ujj)j]rojXapprprq}rr(jUjjlubajjUubjX " to boot.rsrt}ru(jX " to boot.jj)ubeubaubj{)rv}rw(jXNow SD card contains 1)boot 2)app 3)config files. config file contains the address of boot image as **0x0** and app image as **0x80000**. Insert it into the SD card slot.jjjj\jjj}rx(j]j]j]j]j]ujNjhj]ryj)rz}r{(jXNow SD card contains 1)boot 2)app 3)config files. config file contains the address of boot image as **0x0** and app image as **0x80000**. Insert it into the SD card slot.jjvjj\jjj}r|(j]j]j]j]j]ujMj]r}(jXdNow SD card contains 1)boot 2)app 3)config files. config file contains the address of boot image as r~r}r(jXdNow SD card contains 1)boot 2)app 3)config files. config file contains the address of boot image as jjzubj)r}r(jX**0x0**j}r(j]j]j]j]j]ujjzj]rjX0x0rr}r(jUjjubajjubjX and app image as rr}r(jX and app image as jjzubj)r}r(jX **0x80000**j}r(j]j]j]j]j]ujjzj]rjX0x80000rr}r(jUjjubajjubjX". Insert it into the SD card slot.rr}r(jX". Insert it into the SD card slot.jjzubeubaubj{)r}r(jXConnect the board with CCS and load the prebuilt qspi flash writer application from **jjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXConnect the board with CCS and load the prebuilt qspi flash writer application from **jjjj\jjj}r(j]j]j]j]j]ujMj]r(jXTConnect the board with CCS and load the prebuilt qspi flash writer application from rr}r(jXTConnect the board with CCS and load the prebuilt qspi flash writer application from jjubjM)r}r(jXV**j}r(j]j]j]j]j]ujjj]rjXTrr}r(jUjjubajjUubeubaubj{)r}r(jXKRun the QSPI flash writer application. Following logs expected on console. jjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXJRun the QSPI flash writer application. Following logs expected on console.rjjjj\jjj}r(j]j]j]j]j]ujMj]rjXJRun the QSPI flash writer application. Following logs expected on console.rr}r(jjjjubaubaubeubj)r}r(jXsStarterWare QSPI Flash Writer!! BOARDInit status [0x0] SoC  : [AM43XX] Core  : [A9] Board Detected  : [IDKEVM] Base Board Revision  : [UNKNOWN] Daughter Card Revision: [UNKNOWN] Copying boot to QSPI Flash Copying app to QSPI Flash Changing read to quad mode Read mode has been changed to Quad mode SUCCESS!!! Flashing completedjjjj\jjj}r(j@jAj]j]j]j]j]ujM>!jhj]rjXsStarterWare QSPI Flash Writer!! BOARDInit status [0x0] SoC  : [AM43XX] Core  : [A9] Board Detected  : [IDKEVM] Base Board Revision  : [UNKNOWN] Daughter Card Revision: [UNKNOWN] Copying boot to QSPI Flash Copying app to QSPI Flash Changing read to quad mode Read mode has been changed to Quad mode SUCCESS!!! Flashing completedrr}r(jUjjubaubeubj)r}r(jUjjɍjj\jjj}r(j]j]j]j]rUbooting-the-targetraj]rh+aujMjhj]r(j)r}rŽ(jXBooting the target.rÎjjjj\jjj}rĎ(j]j]j]j]j]ujMjhj]rŎjXBooting the target.rƎrǎ}rȎ(jjÎjjubaubj )rɎ}rʎ(jUjjjj\jj j}rˎ(jU.j]j]j]jUj]j]jjujMjhj]r̎(j{)r͎}rΎ(jXConnect UART cable to a host running serial terminal application (teraterm/hyperterminal) with 115200 baud, 8bit, No parity and 1 STOP bit configuration.jjɎjj\jjj}rώ(j]j]j]j]j]ujNjhj]rЎj)rю}rҎ(jXConnect UART cable to a host running serial terminal application (teraterm/hyperterminal) with 115200 baud, 8bit, No parity and 1 STOP bit configuration.rӎjj͎jj\jjj}rԎ(j]j]j]j]j]ujMj]rՎjXConnect UART cable to a host running serial terminal application (teraterm/hyperterminal) with 115200 baud, 8bit, No parity and 1 STOP bit configuration.r֎r׎}r؎(jjӎjjюubaubaubj{)rَ}rڎ(jXNAfter flashing successfully remove SD card and reboot to see following logs jjɎjj\jjj}rێ(j]j]j]j]j]ujNjhj]r܎j)rݎ}rގ(jXMAfter flashing successfully remove SD card and reboot to see following logsrߎjjَjj\jjj}r(j]j]j]j]j]ujMj]rjXMAfter flashing successfully remove SD card and reboot to see following logsrr}r(jjߎjjݎubaubaubeubj)r}r(jXCStarterWare Boot Loader BOARDInit status [0x0] SoC  : [AM43XX] Core  : [A9] Board Detected  : [IDKEVM] Base Board Revision  : [UNKNOWN] Daughter Card Revision: [UNKNOWN] Copying Header of the application image Copying image from flash to DDR Jumping to StarterWare Application...jjjj\jjj}r(j@jAj]j]j]j]j]ujMW!jhj]rjXCStarterWare Boot Loader BOARDInit status [0x0] SoC  : [AM43XX] Core  : [A9] Board Detected  : [IDKEVM] Base Board Revision  : [UNKNOWN] Daughter Card Revision: [UNKNOWN] Copying Header of the application image Copying image from flash to DDR Jumping to StarterWare Application...rr}r(jUjjubaubj)r}r(jXDNOTE: Boot logs will appear approximately after 25 seconds on reset.jjjj\jjj}r(j@jAj]j]j]j]j]ujMd!jhj]rjXDNOTE: Boot logs will appear approximately after 25 seconds on reset.rr}r(jUjjubaubj)r}r(jX NOTE:If there is no boot mode selection present on board, boot image will be loaded depending on ROM boot sequence Example: If QSPI flash and MMCSD has valid bootloaders, on reset MMCSD boot image will be loaded following ROM Boot sequence.jjjj\jjj}r(j@jAj]j]j]j]j]ujMh!jhj]rjX NOTE:If there is no boot mode selection present on board, boot image will be loaded depending on ROM boot sequence Example: If QSPI flash and MMCSD has valid bootloaders, on reset MMCSD boot image will be loaded following ROM Boot sequence.rr}r(jUjjubaubeubeubj)r}r(jUjj4jj\jjj}r(j]j]j]j]rUbooting-via-uartraj]rjYaujMjhj]r(j)r}r(jXBooting Via UARTrjjjj\jjj}r(j]j]j]j]j]ujMjhj]rjXBooting Via UARTrr}r(jjjjubaubj)r }r (jXROM and Bootloader supports XMODEM protocol with images being binary not requiring any additional headers. Following are steps for boot:r jjjj\jjj}r (j]j]j]j]j]ujMjhj]r jXROM and Bootloader supports XMODEM protocol with images being binary not requiring any additional headers. Following are steps for boot:rr}r(jj jj ubaubj )r}r(jUjjjj\jj j}r(jU.j]j]j]jUj]j]jjujMjhj]r(j{)r}r(jXConfigure board for UART boot mode : UART boot need to be first in the boot device list. Note: In case if any other boot mode is selected, the first available boot image (eg:NAND or MMCSD etc) will override. In case of no valid images, UART boot will be selected. - Select View->Memory Browser through CCS. - Select address 0x44e10040. - Write 0x19 to last 2 bytes of this memory address.(UART boot) - Soft reset the board. This is a volatile bit which gets reset after power on. jjjNjjj}r(j]j]j]j]j]ujNjhj]r(j)r}r(jXConfigure board for UART boot mode : UART boot need to be first in the boot device list. Note: In case if any other boot mode is selected, the first available boot image (eg:NAND or MMCSD etc) will override. In case of no valid images, UART boot will be selected.rjjjj\jjj}r(j]j]j]j]j]ujMj]rjXConfigure board for UART boot mode : UART boot need to be first in the boot device list. Note: In case if any other boot mode is selected, the first available boot image (eg:NAND or MMCSD etc) will override. In case of no valid images, UART boot will be selected.rr}r (jjjjubaubjt)r!}r"(jUj}r#(jyX-j]j]j]j]j]ujjj]r$(j{)r%}r&(jX(Select View->Memory Browser through CCS.r'j}r((j]j]j]j]j]ujj!j]r)j)r*}r+(jj'jj%jj\jjj}r,(j]j]j]j]j]ujMj]r-jX(Select View->Memory Browser through CCS.r.r/}r0(jj'jj*ubaubajjubj{)r1}r2(jXSelect address 0x44e10040.r3j}r4(j]j]j]j]j]ujj!j]r5j)r6}r7(jj3jj1jj\jjj}r8(j]j]j]j]j]ujMj]r9jXSelect address 0x44e10040.r:r;}r<(jj3jj6ubaubajjubj{)r=}r>(jX=Write 0x19 to last 2 bytes of this memory address.(UART boot)r?j}r@(j]j]j]j]j]ujj!j]rAj)rB}rC(jj?jj=jj\jjj}rD(j]j]j]j]j]ujMj]rEjX=Write 0x19 to last 2 bytes of this memory address.(UART boot)rFrG}rH(jj?jjBubaubajjubj{)rI}rJ(jXNSoft reset the board. This is a volatile bit which gets reset after power on. j}rK(j]j]j]j]j]ujj!j]rLj)rM}rN(jXMSoft reset the board. This is a volatile bit which gets reset after power on.rOjjIjj\jjj}rP(j]j]j]j]j]ujMj]rQjXMSoft reset the board. This is a volatile bit which gets reset after power on.rRrS}rT(jjOjjMubaubajjubejjwubeubj{)rU}rV(jXROM code will print "CC.." on UART console expecting Bootloader via XMODEM. File can be sent via xmodem through tera-term File-> Transfer -> XMODEM -> Send.jjjj\jjj}rW(j]j]j]j]j]ujNjhj]rXj)rY}rZ(jXROM code will print "CC.." on UART console expecting Bootloader via XMODEM. File can be sent via xmodem through tera-term File-> Transfer -> XMODEM -> Send.r[jjUjj\jjj}r\(j]j]j]j]j]ujMj]r]jXROM code will print "CC.." on UART console expecting Bootloader via XMODEM. File can be sent via xmodem through tera-term File-> Transfer -> XMODEM -> Send.r^r_}r`(jj[jjYubaubaubj{)ra}rb(jXOn transmitting bootloader image, bootloader_boot_uart_a9host_debug.bin via XMODEM, following message will be expected on serial console. jjjj\jjj}rc(j]j]j]j]j]ujNjhj]rdj)re}rf(jXOn transmitting bootloader image, bootloader_boot_uart_a9host_debug.bin via XMODEM, following message will be expected on serial console.rgjjajj\jjj}rh(j]j]j]j]j]ujMj]rijXOn transmitting bootloader image, bootloader_boot_uart_a9host_debug.bin via XMODEM, following message will be expected on serial console.rjrk}rl(jjgjjeubaubaubeubj)rm}rn(jXWCCCCCCCCCCCCCCCCCCCCCCCCCCCC StarterWare Boot Loader BOARDInit status [0x0] SoC  : [AM43XX] Core  : [A9] Board Detected  : [IDKEVM] Base Board Revision  : [UNKNOWN] Daughter Card Revision: [UNKNOWN] GPIO Instance number: 0 Pin number: 22 Please transfer file: CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCjjjj\jjj}ro(j@jAj]j]j]j]j]ujM!jhj]rpjXWCCCCCCCCCCCCCCCCCCCCCCCCCCCC StarterWare Boot Loader BOARDInit status [0x0] SoC  : [AM43XX] Core  : [A9] Board Detected  : [IDKEVM] Base Board Revision  : [UNKNOWN] Daughter Card Revision: [UNKNOWN] GPIO Instance number: 0 Pin number: 22 Please transfer file: CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCrqrr}rs(jUjjmubaubj)rt}ru(jX  4.  As  a next step application binary (without header) can be sent via XMODEM which will lead to application start executing.rvjjjj\jjj}rw(j]j]j]j]j]ujMjhj]rxjX  4.  As  a next step application binary (without header) can be sent via XMODEM which will lead to application start executing.ryrz}r{(jjvjjtubaubeubj)r|}r}(jUjj4jj\jjj}r~(j]j]j]j]rUbooting-via-mcspiraj]rh6aujM jhj]r(j)r}r(jXBooting Via McSPIrjj|jj\jjj}r(j]j]j]j]j]ujM jhj]rjXBooting Via McSPIrr}r(jjjjubaubj)r}r(jX&Booting from McSPI involves two steps.rjj|jj\jjj}r(j]j]j]j]j]ujM jhj]rjX&Booting from McSPI involves two steps.rr}r(jjjjubaubj )r}r(jUjj|jj\jj j}r(jU.j]j]j]jUj]j]jjujMjhj]r(j{)r}r(jXPreparing Flash Devicerjjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj\jjj}r(j]j]j]j]j]ujMj]rjXPreparing Flash Devicerr}r(jjjjubaubaubj{)r}r(jXBooting the target. jjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXBooting the target.rjjjj\jjj}r(j]j]j]j]j]ujMj]rjXBooting the target.rr}r(jjjjubaubaubeubjhK)r}r(jXPreparing Flash Devicerjj|jj\jjlKj}r(j]rUpreparing-flash-device-1raj]j]j]j]rhaujNjhj]rjXPreparing Flash Devicerr}r(jjjjubaubjt)r}r(jUjj|jj\jjwj}r(jyX-j]j]j]j]j]ujMjhj]r(j{)r}r(jXSet the appropriate bootmode if applicable for EVM. Refer to corresponding hardware user's guide for bootmode settings. **Note**: Most of the boards may not have switch settings.jjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}rÏ(jXSet the appropriate bootmode if applicable for EVM. Refer to corresponding hardware user's guide for bootmode settings. **Note**: Most of the boards may not have switch settings.jjjj\jjj}rď(j]j]j]j]j]ujMj]rŏ(jXxSet the appropriate bootmode if applicable for EVM. Refer to corresponding hardware user's guide for bootmode settings. rƏrǏ}rȏ(jXxSet the appropriate bootmode if applicable for EVM. Refer to corresponding hardware user's guide for bootmode settings. jjubj)rɏ}rʏ(jX**Note**j}rˏ(j]j]j]j]j]ujjj]ȑjXNoter͏rΏ}rϏ(jUjjɏubajjubjX2: Most of the boards may not have switch settings.rЏrя}rҏ(jX2: Most of the boards may not have switch settings.jjubeubaubj{)rӏ}rԏ(jXUAdd a required target configuration in CCS depending on emulator and board connected.jjjj\jjj}rՏ(j]j]j]j]j]ujNjhj]r֏j)r׏}r؏(jXUAdd a required target configuration in CCS depending on emulator and board connected.rُjjӏjj\jjj}rڏ(j]j]j]j]j]ujMj]rۏjXUAdd a required target configuration in CCS depending on emulator and board connected.r܏rݏ}rޏ(jjُjj׏ubaubaubj{)rߏ}r(jX(Connect target to required core. Ex: A8.rjjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjߏjj\jjj}r(j]j]j]j]j]ujMj]rjX(Connect target to required core. Ex: A8.rr}r(jjjjubaubaubj{)r}r(jXLoad the flash writer from * To FLASH an Image Enter 2 ----> To ERASE Flash Enter 3 ----> To EXITjj|jj\jjj}r(j@jAj]j]j]j]j]ujM!jhj]rjXxStarting SPIWriter. Choose Operation: Enter 1 ----> To FLASH an Image Enter 2 ----> To ERASE Flash Enter 3 ----> To EXITrr}r(jUjj ubaubjt)r}r(jUjj|jj\jjwj}r(jyX-j]j]j]j]j]ujM(jhj]rj{)r}r(jX@When Flash option is chosen program prompts to enter file name. jjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX?When Flash option is chosen program prompts to enter file name.rjjjj\jjj}r(j]j]j]j]j]ujM(j]rjX?When Flash option is chosen program prompts to enter file name.r r!}r"(jjjjubaubaubaubj)r#}r$(jXEnter the File Namejj|jj\jjj}r%(j@jAj]j]j]j]j]ujM!jhj]r&jXEnter the File Namer'r(}r)(jUjj#ubaubjt)r*}r+(jUjj|jj\jjwj}r,(jyX-j]j]j]j]j]ujM.jhj]r-j{)r.}r/(jXProvide the complete path of file *bootloader_boot_mcspi_a8host_release_ti.bin* at directory "binary/bootloader/bin///" and hit Enter. jj*jj\jjj}r0(j]j]j]j]j]ujNjhj]r1j)r2}r3(jXProvide the complete path of file *bootloader_boot_mcspi_a8host_release_ti.bin* at directory "binary/bootloader/bin///" and hit Enter.jj.jj\jjj}r4(j]j]j]j]j]ujM.j]r5(jX"Provide the complete path of file r6r7}r8(jX"Provide the complete path of file jj2ubjM)r9}r:(jX-*bootloader_boot_mcspi_a8host_release_ti.bin*j}r;(j]j]j]j]j]ujj2j]r<jX+bootloader_boot_mcspi_a8host_release_ti.binr=r>}r?(jUjj9ubajjUubjXJ at directory "binary/bootloader/bin///" and hit Enter.r@rA}rB(jXJ at directory "binary/bootloader/bin///" and hit Enter.jj2ubeubaubaubj)rC}rD(jX"Enter the Offset in bytes (in HEX)jj|jj\jjj}rE(j@jAj]j]j]j]j]ujM!jhj]rFjX"Enter the Offset in bytes (in HEX)rGrH}rI(jUjjCubaubjt)rJ}rK(jUjj|jj\jjwj}rL(jyX-j]j]j]j]j]ujM6jhj]rM(j{)rN}rO(jX)Provide **0x00000** to flash bootloader. jjJjj\jjj}rP(j]j]j]j]j]ujNjhj]rQj)rR}rS(jX(Provide **0x00000** to flash bootloader.jjNjj\jjj}rT(j]j]j]j]j]ujM6j]rU(jXProvide rVrW}rX(jXProvide jjRubj)rY}rZ(jX **0x00000**j}r[(j]j]j]j]j]ujjRj]r\jX0x00000r]r^}r_(jUjjYubajjubjX to flash bootloader.r`ra}rb(jX to flash bootloader.jjRubeubaubj{)rc}rd(jX6Wait for few minutes as flashing is a slower process. jjJjj\jjj}re(j]j]j]j]j]ujNjhj]rfj)rg}rh(jX5Wait for few minutes as flashing is a slower process.rijjcjj\jjj}rj(j]j]j]j]j]ujM8j]rkjX5Wait for few minutes as flashing is a slower process.rlrm}rn(jjijjgubaubaubeubj)ro}rp(jXErasing flash at byte offset: xx, byte length: xxxx SF: Successfully erased xxxx bytes @ xxxx Writing flash at page offset: x, number of pages: xxxx Flashing is in progress... Verifying... Success.jj|jj\jjj}rq(j@jAj]j]j]j]j]ujM!jhj]rrjXErasing flash at byte offset: xx, byte length: xxxx SF: Successfully erased xxxx bytes @ xxxx Writing flash at page offset: x, number of pages: xxxx Flashing is in progress... Verifying... Success.rsrt}ru(jUjjoubaubjt)rv}rw(jUjj|jj\jjwj}rx(jyX-j]j]j]j]j]ujMBjhj]ry(j{)rz}r{(jXRepeat the steps to load and run the flash writer, then choose the application binary image _a8host_ti.bin and enter **0x20000** as the offset. Wait until the flashing completes. jjvjj\jjj}r|(j]j]j]j]j]ujNjhj]r}j)r~}r(jXRepeat the steps to load and run the flash writer, then choose the application binary image _a8host_ti.bin and enter **0x20000** as the offset. Wait until the flashing completes.jjzjj\jjj}r(j]j]j]j]j]ujMBj]r(jXRepeat the steps to load and run the flash writer, then choose the application binary image _a8host_ti.bin and enter rr}r(jXRepeat the steps to load and run the flash writer, then choose the application binary image _a8host_ti.bin and enter jj~ubj)r}r(jX **0x20000**j}r(j]j]j]j]j]ujj~j]rjX0x20000rr}r(jUjjubajjubjX2 as the offset. Wait until the flashing completes.rr}r(jX2 as the offset. Wait until the flashing completes.jj~ubeubaubj{)r}r(jX4Once SPI flash writing completes disconnect target. jjvjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX3Once SPI flash writing completes disconnect target.rjjjj\jjj}r(j]j]j]j]j]ujMFj]rjX3Once SPI flash writing completes disconnect target.rr}r(jjjjubaubaubeubjhK)r}r(jXBooting the targetrjj|jj\jjlKj}r(j]rUid69raj]j]j]j]rhnaujNjhj]rjXBooting the targetrr}r(jjjjubaubj )r}r(jUjj|jj\jj j}r(jU.j]j]j]jUj]j]jjujMKjhj]r(j{)r}r(jXConnect a serial cable to a host running a serial terminal application (teraterm/hyperterminal) with 115200 baud, 8bit, No parity and 1 STOP bit configuration.jjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXConnect a serial cable to a host running a serial terminal application (teraterm/hyperterminal) with 115200 baud, 8bit, No parity and 1 STOP bit configuration.rjjjj\jjj}r(j]j]j]j]j]ujMKj]rjXConnect a serial cable to a host running a serial terminal application (teraterm/hyperterminal) with 115200 baud, 8bit, No parity and 1 STOP bit configuration.rr}r(jjjjubaubaubj{)r}r(jX&Configure the board for SPI boot mode.rjjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj\jjj}r(j]j]j]j]j]ujMNj]rjX&Configure the board for SPI boot mode.rr}r(jjjjubaubaubj{)r}rÐ(jXOn reset, ROM bootloader copies the bootloader from flash to internal memory. The bootloader then copies the application image from flash to DDR and passes the control to the application. jjjj\jjj}rĐ(j]j]j]j]j]ujNjhj]rŐj)rƐ}rǐ(jXOn reset, ROM bootloader copies the bootloader from flash to internal memory. The bootloader then copies the application image from flash to DDR and passes the control to the application.rȐjjjj\jjj}rɐ(j]j]j]j]j]ujMOj]rʐjXOn reset, ROM bootloader copies the bootloader from flash to internal memory. The bootloader then copies the application image from flash to DDR and passes the control to the application.rːr̐}r͐(jjȐjjƐubaubaubeubjc)rΐ}rϐ(jUjj|jj\jjfj}rА(j]j]j]j]j]ujMSjhj]rѐji)rҐ}rӐ(jUjlKjjΐjj\jjj}rԐ(j]j]j]j]j]ujKjhj]ubaubeubj)rՐ}r֐(jUjj4jj\jjj}rא(j]j]j]j]rؐUbooting-via-nandrِaj]rڐhaujMVjhj]rې(j)rܐ}rݐ(jXBooting Via NANDrސjjՐjj\jjj}rߐ(j]j]j]j]j]ujMVjhj]rjXBooting Via NANDrr}r(jjސjjܐubaubj)r}r(jX%Booting from NAND involves two steps.rjjՐjj\jjj}r(j]j]j]j]j]ujMXjhj]rjX%Booting from NAND involves two steps.rr}r(jjjjubaubj )r}r(jUjjՐjj\jj j}r(jU.j]j]j]jUj]j]jjujMZjhj]r(j{)r}r(jXPreparing Flash Devicerjjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj\jjj}r(j]j]j]j]j]ujMZj]rjXPreparing Flash Devicerr}r(jjjjubaubaubj{)r}r(jXBooting the target. jjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXBooting the target.rjjjj\jjj}r(j]j]j]j]j]ujM[j]rjXBooting the target.rr}r(jjjjubaubaubeubjhK)r}r (jXPreparing Flash Devicer jjՐjj\jjlKj}r (j]r Upreparing-flash-device-2r aj]j]j]j]rhaujNjhj]rjXPreparing Flash Devicerr}r(jj jjubaubjt)r}r(jUjjՐjj\jjwj}r(jyX-j]j]j]j]j]ujM`jhj]r(j{)r}r(jXDConfigure BOOT pins for NAND according to the hardware user's guide.rjjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj\jjj}r(j]j]j]j]j]ujM`j]rjXDConfigure BOOT pins for NAND according to the hardware user's guide.r r!}r"(jjjjubaubaubj{)r#}r$(jXConnect target with CCS.r%jjjj\jjj}r&(j]j]j]j]j]ujNjhj]r'j)r(}r)(jj%jj#jj\jjj}r*(j]j]j]j]j]ujMaj]r+jXConnect target with CCS.r,r-}r.(jj%jj(ubaubaubj{)r/}r0(jXLoad the ** to target and Run. Flash writer will output messages to CCS console. When it prompts for inputs, proper inputs shall be given via CCS console.jjjj\jjj}r1(j]j]j]j]j]ujNjhj]r2j)r3}r4(jXLoad the ** to target and Run. Flash writer will output messages to CCS console. When it prompts for inputs, proper inputs shall be given via CCS console.jj/jj\jjj}r5(j]j]j]j]j]ujMbj]r6(jX Load the r7r8}r9(jX Load the jj3ubjM)r:}r;(jX[**j}r<(j]j]j]j]j]ujj3j]r=jXYr>r?}r@(jUjj:ubajjUubjX to target and Run. Flash writer will output messages to CCS console. When it prompts for inputs, proper inputs shall be given via CCS console.rArB}rC(jX to target and Run. Flash writer will output messages to CCS console. When it prompts for inputs, proper inputs shall be given via CCS console.jj3ubeubaubj{)rD}rE(jXAWhen prompted for binary file name, update file with proper path.rFjjjj\jjj}rG(j]j]j]j]j]ujNjhj]rHj)rI}rJ(jjFjjDjj\jjj}rK(j]j]j]j]j]ujMgj]rLjXAWhen prompted for binary file name, update file with proper path.rMrN}rO(jjFjjIubaubaubj{)rP}rQ(jXSelect option for flashing. jjjj\jjj}rR(j]j]j]j]j]ujNjhj]rSj)rT}rU(jXSelect option for flashing.rVjjPjj\jjj}rW(j]j]j]j]j]ujMhj]rXjXSelect option for flashing.rYrZ}r[(jjVjjTubaubaubeubj)r\}r](jXnChoose your operation Enter 1 ---> To Flash an Image Enter 2 ---> To ERASE the whole NAND Enter 3 ---> To EXITjjՐjj\jjj}r^(j@jAj]j]j]j]j]ujM!jhj]r_jXnChoose your operation Enter 1 ---> To Flash an Image Enter 2 ---> To ERASE the whole NAND Enter 3 ---> To EXITr`ra}rb(jUjj\ubaubjt)rc}rd(jUjjՐjj\jjwj}re(jyX-j]j]j]j]j]ujMqjhj]rfj{)rg}rh(jXQIf Option 1 is selected, enter image path to flash when prompted as shown below. jjcjj\jjj}ri(j]j]j]j]j]ujNjhj]rjj)rk}rl(jXPIf Option 1 is selected, enter image path to flash when prompted as shown below.rmjjgjj\jjj}rn(j]j]j]j]j]ujMqj]rojXPIf Option 1 is selected, enter image path to flash when prompted as shown below.rprq}rr(jjmjjkubaubaubaubj)rs}rt(jXEnter image file pathjjՐjj\jjj}ru(j@jAj]j]j]j]j]ujM"jhj]rvjXEnter image file pathrwrx}ry(jUjjsubaubj)rz}r{(jX    Provide the complete path (e.g. //bootloader_boot_nand_a8host__ti.bin)r|jjՐjj\jjj}r}(j]j]j]j]j]ujMxjhj]r~jX    Provide the complete path (e.g. //bootloader_boot_nand_a8host__ti.bin)rr}r(jj|jjzubaubjt)r}r(jUjjՐjj\jjwj}r(jyX-j]j]j]j]j]ujM{jhj]rj{)r}r(jX+Enter offset when prompted as shown below. jjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX*Enter offset when prompted as shown below.rjjjj\jjj}r(j]j]j]j]j]ujM{j]rjX*Enter offset when prompted as shown below.rr}r(jjjjubaubaubaubj)r}r(jXEnter offset (in hex):jjՐjj\jjj}r(j@jAj]j]j]j]j]ujM "jhj]rjXEnter offset (in hex):rr}r(jUjjubaubjc)r}r(jUjjՐjj\jjfj}r(j]j]j]j]j]ujMjhj]r(ji)r}r(jXL    This offset is start location from where the image should be flashed.rjlKjjjj\jjj}r(j]j]j]j]j]ujMjhj]rjXL    This offset is start location from where the image should be flashed.rr}r(jjjjubaubji)r}r(jXNOTE:rjlKjjjj\jjj}r(j]j]j]j]j]ujMjhj]rjXNOTE:rr}r(jjjjubaubeubj )r}r(jUjjՐjj\jj j}r(jU.j]j]j]jUj]j]jjujMjhj]r(j{)r}r(jXUse hex formatrjjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj\jjj}r(j]j]j]j]j]ujMj]rjXUse hex formatrr}r(jjjjubaubaubj{)r}r(jXbIf bootloader is to be flashed, provide **0x00000**. For application binary, provide **0x80000**. jjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r‘(jXaIf bootloader is to be flashed, provide **0x00000**. For application binary, provide **0x80000**.jjjj\jjj}rÑ(j]j]j]j]j]ujMj]rđ(jX(If bootloader is to be flashed, provide rőrƑ}rǑ(jX(If bootloader is to be flashed, provide jjubj)rȑ}rɑ(jX **0x00000**j}rʑ(j]j]j]j]j]ujjj]rˑjX0x00000ȓr͑}rΑ(jUjjȑubajjubjX". For application binary, provide rϑrБ}rё(jX". For application binary, provide jjubj)rґ}rӑ(jX **0x80000**j}rԑ(j]j]j]j]j]ujjj]rՑjX0x80000r֑rב}rؑ(jUjjґubajjubjX.rّ}rڑ(jX.jjubeubaubeubjt)rۑ}rܑ(jUjjՐjj\jjwj}rݑ(jyX-j]j]j]j]j]ujMjhj]rޑj{)rߑ}r(jXSelect ECC for flashing. jjۑjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXSelect ECC for flashing.rjjߑjj\jjj}r(j]j]j]j]j]ujMj]rjXSelect ECC for flashing.rr}r(jjjjubaubaubaubj)r}r(jXChoose the ECC scheme from given options Enter 1 ---> BCH 8 bit Enter 2 ---> HAM Enter 3 ---> T0 EXIT Please enter ECC scheme type:jjՐjj\jjj}r(j@jAj]j]j]j]j]ujM"jhj]rjXChoose the ECC scheme from given options Enter 1 ---> BCH 8 bit Enter 2 ---> HAM Enter 3 ---> T0 EXIT Please enter ECC scheme type:rr}r(jUjjubaubj)r}r(jXm    Always select BCH8 for bootloader and application as ROM code and bootloader uses the BCH8 ECC scheme.rjjՐjj\jjj}r(j]j]j]j]j]ujMjhj]rjXm    Always select BCH8 for bootloader and application as ROM code and bootloader uses the BCH8 ECC scheme.rr}r(jjjjubaubjt)r}r(jUjjՐjj\jjwj}r(jyX-j]j]j]j]j]ujMjhj]r(j{)r}r(jXCEnsure that flash info displayed by tool matches NAND flash in EVM.rjjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj\jjj}r(j]j]j]j]j]ujMj]rjXCEnsure that flash info displayed by tool matches NAND flash in EVM.rr}r (jjjjubaubaubj{)r }r (jXbAfter this tool should first erase the required region in flash and then start flashing new image.jjjj\jjj}r (j]j]j]j]j]ujNjhj]r j)r}r(jXbAfter this tool should first erase the required region in flash and then start flashing new image.rjj jj\jjj}r(j]j]j]j]j]ujMj]rjXbAfter this tool should first erase the required region in flash and then start flashing new image.rr}r(jjjjubaubaubj{)r}r(jXIIf flashing procedure is complete following message should be displayed. jjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXHIf flashing procedure is complete following message should be displayed.rjjjj\jjj}r(j]j]j]j]j]ujMj]rjXHIf flashing procedure is complete following message should be displayed.rr }r!(jjjjubaubaubeubj)r"}r#(jX=Application is successfully flashed NAND flashing successful!jjՐjj\jjj}r$(j@jAj]j]j]j]j]ujM*"jhj]r%jX=Application is successfully flashed NAND flashing successful!r&r'}r((jUjj"ubaubjt)r)}r*(jUjjՐjj\jjwj}r+(jyX-j]j]j]j]j]ujMjhj]r,j{)r-}r.(jX8Once NAND flash writing completes, disconnect from CCS. jj)jj\jjj}r/(j]j]j]j]j]ujNjhj]r0j)r1}r2(jX7Once NAND flash writing completes, disconnect from CCS.r3jj-jj\jjj}r4(j]j]j]j]j]ujMj]r5jX7Once NAND flash writing completes, disconnect from CCS.r6r7}r8(jj3jj1ubaubaubaubjhK)r9}r:(jXBooting the targetr;jjՐjj\jjlKj}r<(j]r=Ubooting-the-target-1r>aj]j]j]j]r?haujNjhj]r@jXBooting the targetrArB}rC(jj;jj9ubaubjt)rD}rE(jUjjՐjj\jjwj}rF(jyX-j]j]j]j]j]ujMjhj]rG(j{)rH}rI(jXConnect a UART cable to a host running a serial terminal application (teraterm/hyperterminal) with 115200 baud, 8bit, No parity and 1 STOP bit configuration.jjDjj\jjj}rJ(j]j]j]j]j]ujNjhj]rKj)rL}rM(jXConnect a UART cable to a host running a serial terminal application (teraterm/hyperterminal) with 115200 baud, 8bit, No parity and 1 STOP bit configuration.rNjjHjj\jjj}rO(j]j]j]j]j]ujMj]rPjXConnect a UART cable to a host running a serial terminal application (teraterm/hyperterminal) with 115200 baud, 8bit, No parity and 1 STOP bit configuration.rQrR}rS(jjNjjLubaubaubj{)rT}rU(jXlConfigure the board for NAND boot mode. Refer to corresponding hardware user's guide for bootmode settings.jjDjj\jjj}rV(j]j]j]j]j]ujNjhj]rWj)rX}rY(jXlConfigure the board for NAND boot mode. Refer to corresponding hardware user's guide for bootmode settings.rZjjTjj\jjj}r[(j]j]j]j]j]ujMj]r\jXlConfigure the board for NAND boot mode. Refer to corresponding hardware user's guide for bootmode settings.r]r^}r_(jjZjjXubaubaubj{)r`}ra(jXOn reset, ROM detects bootloader from NAND and copies it to internal memory. Bootloader then copies application image from the NAND to DDR and passes control to application. If the process is successful, following messages appear in serial console. jjDjj\jjj}rb(j]j]j]j]j]ujNjhj]rcj)rd}re(jXOn reset, ROM detects bootloader from NAND and copies it to internal memory. Bootloader then copies application image from the NAND to DDR and passes control to application. If the process is successful, following messages appear in serial console.rfjj`jj\jjj}rg(j]j]j]j]j]ujMj]rhjXOn reset, ROM detects bootloader from NAND and copies it to internal memory. Bootloader then copies application image from the NAND to DDR and passes control to application. If the process is successful, following messages appear in serial console.rirj}rk(jjfjjdubaubaubeubj)rl}rm(jX' StarterWare Boot Loader BOARDInit status [0x0] SoC  : [AM335X] Core  : [A8] Board Detected  : [GPEVM] Base Board Revision  : [1.5] Daughter Card Revision: [UNKNOWN] NAND flash is connected to GPMC on this board Jumping to StarterWare Application...jjՐjj\jjj}rn(j@jAj]j]j]j]j]ujM>"jhj]rojX' StarterWare Boot Loader BOARDInit status [0x0] SoC  : [AM335X] Core  : [A8] Board Detected  : [GPEVM] Base Board Revision  : [1.5] Daughter Card Revision: [UNKNOWN] NAND flash is connected to GPMC on this board Jumping to StarterWare Application...rprq}rr(jUjjlubaubj)rs}rt(jX7After this application should take control and execute.rujjՐjj\jjj}rv(j]j]j]j]j]ujMjhj]rwjX7After this application should take control and execute.rxry}rz(jjujjsubaubeubeubj)r{}r|(jUjKjjJjj\jjj}r}(j]r~Xtest applicationraj]j]j]rUtest-applicationraj]ujMjhj]r(j)r}r(jXTest Applicationrjj{jj\jjj}r(j]j]j]j]j]ujMjhj]rjXTest Applicationrr}r(jjjjubaubj)r}r(jXyThe section explains steps for building and booting a sample pdk application for am335x or am437x using MMCSD bootloader.rjj{jj\jjj}r(j]j]j]j]j]ujMjhj]rjXyThe section explains steps for building and booting a sample pdk application for am335x or am437x using MMCSD bootloader.rr}r(jjjjubaubj)r}r(jUjj{jj\jjj}r(j]j]j]j]rUtest-application-image-creationraj]rhaujMjhj]r(j)r}r(jXTest Application Image Creationrjjjj\jjj}r(j]j]j]j]j]ujMjhj]rjXTest Application Image Creationrr}r(jjjjubaubj)r}r(jX>Follow below steps to generate the bootable application image.rjjjj\jjj}r(j]j]j]j]j]ujMjhj]rjX>Follow below steps to generate the bootable application image.rr}r(jjjjubaubj )r}r(jUjjjj\jj j}r(jU.j]j]j]jUj]j]jjujMjhj]r(j{)r}r(jXGenerate .out files using steps for `Rebuilding PDK `__. Locate .out file in directory */Debug>*jjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXGenerate .out files using steps for `Rebuilding PDK `__. Locate .out file in directory */Debug>*jjjj\jjj}r(j]j]j]j]j]ujMj]r(jX$Generate .out files using steps for rr}r(jX$Generate .out files using steps for jjubj)r}r(jXP`Rebuilding PDK `__j}r(UnameXRebuilding PDKjX;index_how_to_guides.html#rebuild-drivers-from-pdk-directoryj]j]j]j]j]ujjj]rjXRebuilding PDKrr}r(jUjjubajjubjX . Locate .out file in directory rr}r’(jX . Locate .out file in directory jjubjM)rÒ}rĒ(jXF*/Debug>*j}rŒ(j]j]j]j]j]ujjj]rƒjXD/Debug>rǒrȒ}rɒ(jUjjÒubajjUubeubaubj{)rʒ}r˒(jXConvert files to support MMCSD boot using steps as per `Binary format conversion procedure `__.jjjj\jjj}r̒(j]j]j]j]j]ujNjhj]r͒j)rΒ}rϒ(jXConvert files to support MMCSD boot using steps as per `Binary format conversion procedure `__.jjʒjj\jjj}rВ(j]j]j]j]j]ujMj]rђ(jX7Convert files to support MMCSD boot using steps as per rҒrӒ}rԒ(jX7Convert files to support MMCSD boot using steps as per jjΒubj)rՒ}r֒(jXn`Binary format conversion procedure `__j}rג(UnameX"Binary format conversion procedurejXEindex_Foundational_Components.html#binary-format-conversion-procedurej]j]j]j]j]ujjΒj]rؒjX"Binary format conversion procedurerْrڒ}rے(jUjjՒubajjubjX.rܒ}rݒ(jX.jjΒubeubaubj{)rޒ}rߒ(jX0Rename generated _ti.bin to "app". jjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX/Rename generated _ti.bin to "app".rjjޒjj\jjj}r(j]j]j]j]j]ujMj]rjX/Rename generated _ti.bin to "app".rr}r(jjjjubaubaubeubeubj)r}r(jUjj{jj\jjj}r(j]j]j]j]rUloading-test-applicationraj]rjaujMjhj]r(j)r}r(jXLoading Test applicationrjjjj\jjj}r(j]j]j]j]j]ujMjhj]rjXLoading Test applicationrr}r(jjjjubaubj)r}r(jXFollow procedure to use "app" file as per section `Booting Via SD Card `__.jjjj\jjj}r(j]j]j]j]j]ujMjhj]r(jX2Follow procedure to use "app" file as per section rr}r(jX2Follow procedure to use "app" file as per section jjubj)r}r(jXP`Booting Via SD Card `__j}r(UnameXBooting Via SD CardjX6index_Foundational_Components.html#booting-via-sd-cardj]j]j]j]j]ujjj]rjXBooting Via SD Cardrr}r(jUjjubajjubjX.r}r(jX.jjubeubeubeubj)r }r (jUjKjjJjj\jjj}r (j]r X usage notesr aj]j]j]rU usage-notesraj]ujMjhj]r(j)r}r(jX Usage Notesrjj jj\jjj}r(j]j]j]j]j]ujMjhj]rjX Usage Notesrr}r(jjjjubaubjt)r}r(jUjj jj\jjwj}r(jyX-j]j]j]j]j]ujMjhj]rj{)r}r(jX**Bootloader Memory map** jjjj\jjj}r(j]j]j]j]j]ujNjhj]r j)r!}r"(jX**Bootloader Memory map**r#jjjj\jjj}r$(j]j]j]j]j]ujMj]r%j)r&}r'(jj#j}r((j]j]j]j]j]ujj!j]r)jXBootloader Memory mapr*r+}r,(jUjj&ubajjubaubaubaubj)r-}r.(jXThe bootloader code runs from internal OCMC memory and occupies certain amount of OCMC memory that is not available for application to use during booting.r/jj jj\jjj}r0(j]j]j]j]j]ujMjhj]r1jXThe bootloader code runs from internal OCMC memory and occupies certain amount of OCMC memory that is not available for application to use during booting.r2r3}r4(jj/jj-ubaubj)r5}r6(jXwRefer to the map file for the boot loader to check for latest information on the memory utilization in the boot loader.r7jj jj\jjj}r8(j]j]j]j]j]ujMjhj]r9jXwRefer to the map file for the boot loader to check for latest information on the memory utilization in the boot loader.r:r;}r<(jj7jj5ubaubj)r=}r>(jX Location of linker command file:r?jj jj\jjj}r@(j]j]j]j]j]ujMjhj]rAjX Location of linker command file:rBrC}rD(jj?jj=ubaubj)rE}rF(jX-BASE_DIR\binary\bootloader\bin\\gccjj jj\jjj}rG(j@jAj]j]j]j]j]ujMr"jhj]rHjX-BASE_DIR\binary\bootloader\bin\\gccrIrJ}rK(jUjjEubaubj)rL}rM(jXXAfter SBL execution is complete, this region can be used as per application requirement.rNjj jj\jjj}rO(j]j]j]j]j]ujMjhj]rPjXXAfter SBL execution is complete, this region can be used as per application requirement.rQrR}rS(jjNjjLubaubjt)rT}rU(jUjj jj\jjwj}rV(jyX-j]j]j]j]j]ujMjhj]rWj{)rX}rY(jX$**Configuring entry point for SBL** jjTjj\jjj}rZ(j]j]j]j]j]ujNjhj]r[j)r\}r](jX#**Configuring entry point for SBL**r^jjXjj\jjj}r_(j]j]j]j]j]ujMj]r`j)ra}rb(jj^j}rc(j]j]j]j]j]ujj\j]rdjXConfiguring entry point for SBLrerf}rg(jUjjaubajjubaubaubaubj)rh}ri(jXThe three files that help setup the entry point in the bootloader build are "PDK_INSTALL_PATH/packages/ti/starterware/soc/armv7a/gcc/sbl_init.S" and the linker command file "PDK_INSTALL_PATH/packages/ti/starterware/examples/gcc/_boot.lds". The global symbol Entry is used to provide the entry point to the bootloader. The Base address of the memory section OCMCRAM (starts at 1K offset in OCMC RAM as defined in TRM) is then used by the tiimage or GPHEader tool to provide RBL the guidance to find the entry point to pass control. After MLO is created check the TI image format file( \_ti.bin) to confirm that the entry point matches the location of Entry symbol in the .map file.jj jj\jjj}rj(j]j]j]j]j]ujMjhj]rkjXThe three files that help setup the entry point in the bootloader build are "PDK_INSTALL_PATH/packages/ti/starterware/soc/armv7a/gcc/sbl_init.S" and the linker command file "PDK_INSTALL_PATH/packages/ti/starterware/examples/gcc/_boot.lds". The global symbol Entry is used to provide the entry point to the bootloader. The Base address of the memory section OCMCRAM (starts at 1K offset in OCMC RAM as defined in TRM) is then used by the tiimage or GPHEader tool to provide RBL the guidance to find the entry point to pass control. After MLO is created check the TI image format file( _ti.bin) to confirm that the entry point matches the location of Entry symbol in the .map file.rlrm}rn(jXThe three files that help setup the entry point in the bootloader build are "PDK_INSTALL_PATH/packages/ti/starterware/soc/armv7a/gcc/sbl_init.S" and the linker command file "PDK_INSTALL_PATH/packages/ti/starterware/examples/gcc/_boot.lds". The global symbol Entry is used to provide the entry point to the bootloader. The Base address of the memory section OCMCRAM (starts at 1K offset in OCMC RAM as defined in TRM) is then used by the tiimage or GPHEader tool to provide RBL the guidance to find the entry point to pass control. After MLO is created check the TI image format file( \_ti.bin) to confirm that the entry point matches the location of Entry symbol in the .map file.jjhubaubj)ro}rp(jXThe object file created by sbl_init.S should always be the first object file in the link order for the symbol Entry to be placed at the BASE address of the memory section SBL_MEMjj jj\jjj}rq(j]j]j]j]j]ujNjhj]rrj)rs}rt(jXThe object file created by sbl_init.S should always be the first object file in the link order for the symbol Entry to be placed at the BASE address of the memory section SBL_MEMrujjojj\jjj}rv(j]j]j]j]j]ujMj]rwjXThe object file created by sbl_init.S should always be the first object file in the link order for the symbol Entry to be placed at the BASE address of the memory section SBL_MEMrxry}rz(jjujjsubaubaubjt)r{}r|(jUjj jj\jjwj}r}(jyX-j]j]j]j]j]ujMjhj]r~j{)r}r(jX[**Boot image creation tools generates a large boot image if load sections are fragmented** jj{jj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXZ**Boot image creation tools generates a large boot image if load sections are fragmented**rjjjj\jjj}r(j]j]j]j]j]ujMj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXVBoot image creation tools generates a large boot image if load sections are fragmentedrr}r(jUjjubajjubaubaubaubj)r}r(jXPlease note that when using objcopy the compiler generates a contiguous binary that gets loaded by the bootloader at the location specified in the header appended by TIIMAGE boot utility. IF you have some code sections in OCMC or SRAM and some section in DDR the compiler will generates a binary that spans across full memory range which would be in order of MB or even GB size so it is recommended that you create compact binaries that can be loaded into memory or implement a ELF parser to bootloader memory sections that may be fragmented in the address space. you can also load separate binaries for OCMC sections and DDR memory and load the sections separatelyrjj jj\jjj}r(j]j]j]j]j]ujMjhj]rjXPlease note that when using objcopy the compiler generates a contiguous binary that gets loaded by the bootloader at the location specified in the header appended by TIIMAGE boot utility. IF you have some code sections in OCMC or SRAM and some section in DDR the compiler will generates a binary that spans across full memory range which would be in order of MB or even GB size so it is recommended that you create compact binaries that can be loaded into memory or implement a ELF parser to bootloader memory sections that may be fragmented in the address space. you can also load separate binaries for OCMC sections and DDR memory and load the sections separatelyrr}r(jjjjubaubjt)r}r(jUjj jj\jjwj}r(jyX-j]j]j]j]j]ujM jhj]rj{)r}r(jXI**Removing Heap section from application binary to speed up boot times** jjjj\jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXH**Removing Heap section from application binary to speed up boot times**rjjjj\jjj}r(j]j]j]j]j]ujM j]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXDRemoving Heap section from application binary to speed up boot timesrr}r(jUjjubajjubaubaubaubj)r}r(jXA common issue reported with the ARM GCC compiler is that it appends Heap section associated with the binary to the binary image used to boot. The Heap section is usually filled with zeros so can cause significant delay in boot times. Essentially the bootloader will be writing a bunch of zeros in memory so is inefficient. Following work around has been used to circumvent the issuerjj jj\jjj}r(j]j]j]j]j]ujMjhj]rjXA common issue reported with the ARM GCC compiler is that it appends Heap section associated with the binary to the binary image used to boot. The Heap section is usually filled with zeros so can cause significant delay in boot times. Essentially the bootloader will be writing a bunch of zeros in memory so is inefficient. Following work around has been used to circumvent the issuerr}r(jjjjubaubj)r}r(jXt**Option 1:** Eliminate the heap by using the compiler option "--remove-section" as described in the E2E post below:jj jj\jjj}r(j]j]j]j]j]ujMjhj]r(j)r}r(jX **Option 1:**j}r(j]j]j]j]j]ujjj]rjX Option 1:rr}r(jUjjubajjubjXg Eliminate the heap by using the compiler option "--remove-section" as described in the E2E post below:rr}r(jXg Eliminate the heap by using the compiler option "--remove-section" as described in the E2E post below:jjubeubj)r}r“(jX**Refer:** `E2E post to configure Heap in ARM application binary by adding "--remove-section" `__jj jj\jjj}rÓ(j]j]j]j]j]ujMjhj]rē(j)rœ}rƓ(jX **Refer:**j}rǓ(j]j]j]j]j]ujjj]rȓjXRefer:rɓrʓ}r˓(jUjjœubajjubjX r̓}r͓(jX jjubj)rΓ}rϓ(jX`E2E post to configure Heap in ARM application binary by adding "--remove-section" `__j}rГ(UnameXQE2E post to configure Heap in ARM application binary by adding "--remove-section"jX@https://e2e.ti.com/support/arm/sitara_arm/f/791/p/604616/2225826j]j]j]j]j]ujjj]rѓjXQE2E post to configure Heap in ARM application binary by adding "--remove-section"rғrӓ}rԓ(jUjjΓubajjubeubj)rՓ}r֓(jX**Example BIOS configuration:**rדjj jj\jjj}rؓ(j]j]j]j]j]ujMjhj]rٓj)rړ}rۓ(jjדj}rܓ(j]j]j]j]j]ujjՓj]rݓjXExample BIOS configuration:rޓrߓ}r(jUjjړubajjubaubj)r}r(jXvar heap1 = HeapMem.create(); heap1.size = 256 * 1024 * 1024; heap1.sectionName = ".stack"; Memory.defaultHeapInstance = heap1;jj jj\jjj}r(j@jAj]j]j]j]j]ujM"jhj]rjXvar heap1 = HeapMem.create(); heap1.size = 256 * 1024 * 1024; heap1.sectionName = ".stack"; Memory.defaultHeapInstance = heap1;rr}r(jUjjubaubj)r}r(jX/**Compiler Setting :** --remove-section=.stackrjj jj\jjj}r(j]j]j]j]j]ujM&jhj]r(j)r}r(jX**Compiler Setting :**j}r(j]j]j]j]j]ujjj]rjXCompiler Setting :rr}r(jUjjubajjubjX --remove-section=.stackrr}r(jX --remove-section=.stackjjubeubj)r}r(jXS**Option 2** Configure Segment type to be "NO LOAD" in .cfg and use excludeSectionsjj jj\jjj}r(j]j]j]j]j]ujM(jhj]r(j)r}r(jX **Option 2**j}r(j]j]j]j]j]ujjj]rjXOption 2rr}r(jUjjubajjubjXG Configure Segment type to be "NO LOAD" in .cfg and use excludeSectionsrr}r(jXG Configure Segment type to be "NO LOAD" in .cfg and use excludeSectionsjjubeubj)r}r(jXSYSBIOS Memory map configurations allows user to specify the section name, length and type. by configuring the section type to "NOLOAD" and using excludeSection option the heap memory can be eliminated from the final binary.rjj jj\jjj}r(j]j]j]j]j]ujM+jhj]r jXSYSBIOS Memory map configurations allows user to specify the section name, length and type. by configuring the section type to "NOLOAD" and using excludeSection option the heap memory can be eliminated from the final binary.r r }r (jjjjubaubj)r }r(jX**Example BIOS configuration:**rjj jj\jjj}r(j]j]j]j]j]ujM0jhj]rj)r}r(jjj}r(j]j]j]j]j]ujj j]rjXExample BIOS configuration:rr}r(jUjjubajjubaubj)r}r(jXProgram.sectMap[".biosheap"] = new Program.SectionSpec(); Program.sectMap[".biosheap"].runSegment = "DDR2" Program.sectMap[".biosheap"].type = "NOLOAD";jj jj\jjj}r(j@jAj]j]j]j]j]ujM"jhj]rjXProgram.sectMap[".biosheap"] = new Program.SectionSpec(); Program.sectMap[".biosheap"].runSegment = "DDR2" Program.sectMap[".biosheap"].type = "NOLOAD";rr}r(jUjjubaubj)r }r!(jX%Program.sectionsExclude = ".biosheap"jj jj\jjj}r"(j@jAj]j]j]j]j]ujM"jhj]r#jX%Program.sectionsExclude = ".biosheap"r$r%}r&(jUjj ubaubj)r'}r((jX-Alternate approach using linker command file:r)jj jj\jjj}r*(j]j]j]j]j]ujM<jhj]r+jX-Alternate approach using linker command file:r,r-}r.(jj)jj'ubaubj)r/}r0(jX:.ddr3Heap (NOLOAD): { *(.ddr3Heap) } > HOST_DDR3jj jj\jjj}r1(j@jAj]j]j]j]j]ujM"jhj]r2jX:.ddr3Heap (NOLOAD): { *(.ddr3Heap) } > HOST_DDR3r3r4}r5(jUjj/ubaubj)r6}r7(jXThe approach described above helps improve boot times but Users are recommended to initialize the HEAP sections to zeros post boot during initialization to avoid any undesired behavior during normal operation of the appjj jj\jjj}r8(j]j]j]j]j]ujNjhj]r9j)r:}r;(jXThe approach described above helps improve boot times but Users are recommended to initialize the HEAP sections to zeros post boot during initialization to avoid any undesired behavior during normal operation of the appr<jj6jj\jjj}r=(j]j]j]j]j]ujMFj]r>jXThe approach described above helps improve boot times but Users are recommended to initialize the HEAP sections to zeros post boot during initialization to avoid any undesired behavior during normal operation of the appr?r@}rA(jj<jj:ubaubaubeubj)rB}rC(jUjKjjJjj\jjj}rD(j]rEXdebugging application bootrFaj]j]j]rGUdebugging-application-bootrHaj]ujMLjhj]rI(j)rJ}rK(jXDebugging application bootrLjjBjj\jjj}rM(j]j]j]j]j]ujMLjhj]rNjXDebugging application bootrOrP}rQ(jjLjjJubaubj)rR}rS(jXSteps to debug application boot using Processor SDK RTOS bootloader are discussed in the article **`Common steps to debug application boot `__**jjBjj\jjj}rT(j]j]j]j]j]ujMNjhj]rU(jXaSteps to debug application boot using Processor SDK RTOS bootloader are discussed in the article rVrW}rX(jXaSteps to debug application boot using Processor SDK RTOS bootloader are discussed in the article jjRubj)rY}rZ(jXz**`Common steps to debug application boot `__**j}r[(j]j]j]j]j]ujjRj]r\jXv`Common steps to debug application boot `__r]r^}r_(jUjjYubajjubeubeubeubj)r`}ra(jUjj;jjjjj}rb(j]j]j]j]rcUam57xrdaj]rejnaujKOjhj]rf(j)rg}rh(jXAM57xrijj`jjjjj}rj(j]j]j]j]j]ujKOjhj]rkjXAM57xrlrm}rn(jjijjgubaubj7)ro}rp(jXEhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_BOOT_AM57xjj`jj:XTsource/rtos/PDK_Platform_Software/Boot_Board_and_EVM_Abstractions/BOOT_AM57x.rst.incrqrr}rsbjj>j}rt(j@jAj]j]j]j]j]ujKjhj]rujXEhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_BOOT_AM57xrvrw}rx(jUjjoubaubj)ry}rz(jUjKjj`jjrjjj}r{(j]r|Xoverviewr}aj]j]j]r~Uid70raj]ujKjhj]r(j)r}r(jXOverviewrjjyjjrjjj}r(j]j]j]j]j]ujKjhj]rjXOverviewrr}r(jjjjubaubj)r}r(jXThe Secondary Bootloader (SBL) for AM57xx device initializes the execution environment for multi-core application and this can be used to demonstrate an out-of-box experience.The section covers additional details including execution sequence, tools and additional flashing instructions.rjjyjjrjjj}r(j]j]j]j]j]ujKjhj]rjXThe Secondary Bootloader (SBL) for AM57xx device initializes the execution environment for multi-core application and this can be used to demonstrate an out-of-box experience.The section covers additional details including execution sequence, tools and additional flashing instructions.rr}r(jjjjubaubeubj)r}r(jUjKjj`jjrjjj}r(j]rj{aj]j]j]rUid71raj]ujK jhj]r(j)r}r(jXBootloader Execution Sequencerjjjjrjjj}r(j]j]j]j]j]ujK jhj]rjXBootloader Execution Sequencerr}r(jjjjubaubjt)r}r(jUjjjjrjjwj}r(jyX-j]j]j]j]j]ujKjhj]r(j{)r}r(jX**Power On Reset**rjjjjrjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjrjjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXPower On Resetrr}r(jUjjubajjubaubaubj{)r}r(jX**ROM Bootloader (RBL)** - Software pre-programmed in ROM memory starts executing - Checks Sysboot pins and choose booting device - If no valid bootloader found on booting device, RBL checks for next booting device. - Platform configuration and initialization. - Configures DPLL and clock settings for MPU, and boot media like I2C, MMCSD, SD/MMC, SPI, QSPI, Ethernet etc for reliable boot. - The sequence depends on RBL execution flow and Sysboot pins. - RBL gets image size and load address by checking TI Image Header appended on bootloader binary(.bin). Check binary formats. - Loads the binary to internal memory at the Load address fetched from TI Image Header - Passes control to Secondary Bootloader(SBL) jjjNjjj}r(j]j]j]j]j]ujNjhj]r(j)r}r(jX**ROM Bootloader (RBL)**rjjjjrjjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXROM Bootloader (RBL)rr”}rÔ(jUjjubajjubaubjt)rĔ}rŔ(jUj}rƔ(jyX-j]j]j]j]j]ujjj]rǔ(j{)rȔ}rɔ(jX6Software pre-programmed in ROM memory starts executingrʔj}r˔(j]j]j]j]j]ujjĔj]r̔j)r͔}rΔ(jjʔjjȔjjrjjj}rϔ(j]j]j]j]j]ujKj]rДjX6Software pre-programmed in ROM memory starts executingrєrҔ}rӔ(jjʔjj͔ubaubajjubj{)rԔ}rՔ(jX-Checks Sysboot pins and choose booting devicer֔j}rה(j]j]j]j]j]ujjĔj]rؔj)rٔ}rڔ(jj֔jjԔjjrjjj}r۔(j]j]j]j]j]ujKj]rܔjX-Checks Sysboot pins and choose booting devicerݔrޔ}rߔ(jj֔jjٔubaubajjubj{)r}r(jXSIf no valid bootloader found on booting device, RBL checks for next booting device.j}r(j]j]j]j]j]ujjĔj]rj)r}r(jXSIf no valid bootloader found on booting device, RBL checks for next booting device.rjjjjrjjj}r(j]j]j]j]j]ujKj]rjXSIf no valid bootloader found on booting device, RBL checks for next booting device.rr}r(jjjjubaubajjubj{)r}r(jX*Platform configuration and initialization.rj}r(j]j]j]j]j]ujjĔj]rj)r}r(jjjjjjrjjj}r(j]j]j]j]j]ujKj]rjX*Platform configuration and initialization.rr}r(jjjjubaubajjubj{)r}r(jX~Configures DPLL and clock settings for MPU, and boot media like I2C, MMCSD, SD/MMC, SPI, QSPI, Ethernet etc for reliable boot.j}r(j]j]j]j]j]ujjĔj]rj)r}r(jX~Configures DPLL and clock settings for MPU, and boot media like I2C, MMCSD, SD/MMC, SPI, QSPI, Ethernet etc for reliable boot.rjjjjrjjj}r(j]j]j]j]j]ujKj]rjX~Configures DPLL and clock settings for MPU, and boot media like I2C, MMCSD, SD/MMC, SPI, QSPI, Ethernet etc for reliable boot.rr}r(jjjjubaubajjubj{)r}r(jX<The sequence depends on RBL execution flow and Sysboot pins.rj}r(j]j]j]j]j]ujjĔj]rj)r }r (jjjjjjrjjj}r (j]j]j]j]j]ujKj]r jX<The sequence depends on RBL execution flow and Sysboot pins.r r}r(jjjj ubaubajjubj{)r}r(jX|RBL gets image size and load address by checking TI Image Header appended on bootloader binary(.bin). Check binary formats.j}r(j]j]j]j]j]ujjĔj]rj)r}r(jX|RBL gets image size and load address by checking TI Image Header appended on bootloader binary(.bin). Check binary formats.rjjjjrjjj}r(j]j]j]j]j]ujKj]rjX|RBL gets image size and load address by checking TI Image Header appended on bootloader binary(.bin). Check binary formats.rr}r(jjjjubaubajjubj{)r}r(jXTLoads the binary to internal memory at the Load address fetched from TI Image Headerj}r(j]j]j]j]j]ujjĔj]rj)r }r!(jXTLoads the binary to internal memory at the Load address fetched from TI Image Headerr"jjjjrjjj}r#(j]j]j]j]j]ujKj]r$jXTLoads the binary to internal memory at the Load address fetched from TI Image Headerr%r&}r'(jj"jj ubaubajjubj{)r(}r)(jX,Passes control to Secondary Bootloader(SBL) j}r*(j]j]j]j]j]ujjĔj]r+j)r,}r-(jX+Passes control to Secondary Bootloader(SBL)r.jj(jjrjjj}r/(j]j]j]j]j]ujKj]r0jX+Passes control to Secondary Bootloader(SBL)r1r2}r3(jj.jj,ubaubajjubejjwubeubeubj)r4}r5(jXDetailed description of ROM bootloader is provided in Initialization Chapter in `AM57xx Technical Reference manual `__jjjjrjjj}r6(j]j]j]j]j]ujNjhj]r7j)r8}r9(jXDetailed description of ROM bootloader is provided in Initialization Chapter in `AM57xx Technical Reference manual `__jj4jjrjjj}r:(j]j]j]j]j]ujK!j]r;(jXPDetailed description of ROM bootloader is provided in Initialization Chapter in r<r=}r>(jXPDetailed description of ROM bootloader is provided in Initialization Chapter in jj8ubj)r?}r@(jXI`AM57xx Technical Reference manual `__j}rA(UnameX!AM57xx Technical Reference manualjX!http://www.ti.com/lit/pdf/spruhz6j]j]j]j]j]ujj8j]rBjX!AM57xx Technical Reference manualrCrD}rE(jUjj?ubajjubeubaubjt)rF}rG(jUjjjjrjjwj}rH(jyX-j]j]j]j]j]ujK%jhj]rI(j{)rJ}rK(jXt**Secondary bootloader(SBL)** - User level secondary bootloader(SBL) begins execution from internal memory by running basic initialization routines like setting up Stack, BSS and then jumps to main() to begin Board Initialization. - Board Initialization is done by a call to **Board_init()** API.For additional details refer `Processor SDK Board Support `__. - It includes setting up PLLs, enabling clocks to all interfaces and modules, performing pinmux and setting up UART console. - Once Board Initialization is complete, it enables clocks to the slave cores like C66x/DSP, IPU, etc and brings them out of reset. - Parses Multicore Application image located in memory device and copies it to DDR memory based on load address for different sections. - Once copy is successful it transfers control to application. jjFjNjjj}rL(j]j]j]j]j]ujNjhj]rM(j)rN}rO(jX**Secondary bootloader(SBL)**rPjjJjjrjjj}rQ(j]j]j]j]j]ujK%j]rRj)rS}rT(jjPj}rU(j]j]j]j]j]ujjNj]rVjXSecondary bootloader(SBL)rWrX}rY(jUjjSubajjubaubjt)rZ}r[(jUj}r\(jyX-j]j]j]j]j]ujjJj]r](j{)r^}r_(jXUser level secondary bootloader(SBL) begins execution from internal memory by running basic initialization routines like setting up Stack, BSS and then jumps to main() to begin Board Initialization.j}r`(j]j]j]j]j]ujjZj]raj)rb}rc(jXUser level secondary bootloader(SBL) begins execution from internal memory by running basic initialization routines like setting up Stack, BSS and then jumps to main() to begin Board Initialization.rdjj^jjrjjj}re(j]j]j]j]j]ujK'j]rfjXUser level secondary bootloader(SBL) begins execution from internal memory by running basic initialization routines like setting up Stack, BSS and then jumps to main() to begin Board Initialization.rgrh}ri(jjdjjbubaubajjubj{)rj}rk(jXBoard Initialization is done by a call to **Board_init()** API.For additional details refer `Processor SDK Board Support `__.j}rl(j]j]j]j]j]ujjZj]rmj)rn}ro(jXBoard Initialization is done by a call to **Board_init()** API.For additional details refer `Processor SDK Board Support `__.jjjjjrjjj}rp(j]j]j]j]j]ujK+j]rq(jX*Board Initialization is done by a call to rrrs}rt(jX*Board Initialization is done by a call to jjnubj)ru}rv(jX**Board_init()**j}rw(j]j]j]j]j]ujjnj]rxjX Board_init()ryrz}r{(jUjjuubajjubjX" API.For additional details refer r|r}}r~(jX" API.For additional details refer jjnubj)r}r(jX@`Processor SDK Board Support `__j}r(UnameXProcessor SDK Board SupportjXindex_board.html#board-supportj]j]j]j]j]ujjnj]rjXProcessor SDK Board Supportrr}r(jUjjubajjubjX.r}r(jX.jjnubeubajjubj{)r}r(jXzIt includes setting up PLLs, enabling clocks to all interfaces and modules, performing pinmux and setting up UART console.j}r(j]j]j]j]j]ujjZj]rj)r}r(jXzIt includes setting up PLLs, enabling clocks to all interfaces and modules, performing pinmux and setting up UART console.rjjjjrjjj}r(j]j]j]j]j]ujK.j]rjXzIt includes setting up PLLs, enabling clocks to all interfaces and modules, performing pinmux and setting up UART console.rr}r(jjjjubaubajjubj{)r}r(jXOnce Board Initialization is complete, it enables clocks to the slave cores like C66x/DSP, IPU, etc and brings them out of reset.j}r(j]j]j]j]j]ujjZj]rj)r}r(jXOnce Board Initialization is complete, it enables clocks to the slave cores like C66x/DSP, IPU, etc and brings them out of reset.rjjjjrjjj}r(j]j]j]j]j]ujK0j]rjXOnce Board Initialization is complete, it enables clocks to the slave cores like C66x/DSP, IPU, etc and brings them out of reset.rr}r(jjjjubaubajjubj{)r}r(jXParses Multicore Application image located in memory device and copies it to DDR memory based on load address for different sections.j}r(j]j]j]j]j]ujjZj]rj)r}r(jXParses Multicore Application image located in memory device and copies it to DDR memory based on load address for different sections.rjjjjrjjj}r(j]j]j]j]j]ujK2j]rjXParses Multicore Application image located in memory device and copies it to DDR memory based on load address for different sections.rr}r(jjjjubaubajjubj{)r}r(jX>Once copy is successful it transfers control to application. j}r(j]j]j]j]j]ujjZj]rj)r}r(jX=Once copy is successful it transfers control to application.rjjjjrjjj}r(j]j]j]j]j]ujK5j]rjX=Once copy is successful it transfers control to application.rr}r(jjjjubaubajjubejjwubeubj{)r}r(jX0**Application then starts executing from DDR**. jjFjjrjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX/**Application then starts executing from DDR**.jjjjrjjj}r(j]j]j]j]j]ujK7j]r(j)r}r(jX.**Application then starts executing from DDR**j}r•(j]j]j]j]j]ujjj]rÕjX*Application then starts executing from DDRrĕrŕ}rƕ(jUjjubajjubjX.rǕ}rȕ(jX.jjubeubaubeubj)rɕ}rʕ(jX- RBL requires boot loader to be in a special format with a header appended to the binary image. The header shall contain the load address of the bootloader and size of the bootloader image. - For more information on the TI header refer TRM documentjjjNjjj}r˕(j]j]j]j]j]ujNjhj]r̕jt)r͕}rΕ(jUj}rϕ(jyX-j]j]j]j]j]ujjɕj]rЕ(j{)rѕ}rҕ(jXRBL requires boot loader to be in a special format with a header appended to the binary image. The header shall contain the load address of the bootloader and size of the bootloader image.j}rӕ(j]j]j]j]j]ujj͕j]rԕj)rՕ}r֕(jXRBL requires boot loader to be in a special format with a header appended to the binary image. The header shall contain the load address of the bootloader and size of the bootloader image.rוjjѕjjrjjj}rؕ(j]j]j]j]j]ujK;j]rٕjXRBL requires boot loader to be in a special format with a header appended to the binary image. The header shall contain the load address of the bootloader and size of the bootloader image.rڕrە}rܕ(jjוjjՕubaubajjubj{)rݕ}rޕ(jX8For more information on the TI header refer TRM documentrߕj}r(j]j]j]j]j]ujj͕j]rj)r}r(jjߕjjݕjjrjjj}r(j]j]j]j]j]ujK>j]rjX8For more information on the TI header refer TRM documentrr}r(jjߕjjubaubajjubejjwubaubeubj)r}r(jUjKjj`jjrjjj}r(j]rXdirectory structureraj]j]j]rUdirectory-structureraj]ujKAjhj]r(j)r}r(jXDirectory structurerjjjjrjjj}r(j]j]j]j]j]ujKAjhj]rjXDirectory structurerr}r(jjjjubaubj)r}r(jX**Makefiles:**rjjjjrjjj}r(j]j]j]j]j]ujKCjhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX Makefiles:rr}r(jUjjubajjubaubjt)r}r(jUjjjjrjjwj}r(jyX-j]j]j]j]j]ujKEjhj]rj{)r }r (jX**PDK_INSTALL_PATH/ti/boot/sbl/board//build**: Makefile for bootloader that provides list of source files and library and compiler options to create bootloader binary. jjjjrjjj}r (j]j]j]j]j]ujNjhj]r j)r }r(jX**PDK_INSTALL_PATH/ti/boot/sbl/board//build**: Makefile for bootloader that provides list of source files and library and compiler options to create bootloader binary.jj jjrjjj}r(j]j]j]j]j]ujKEj]r(j)r}r(jX9**PDK_INSTALL_PATH/ti/boot/sbl/board//build**j}r(j]j]j]j]j]ujj j]rjX5PDK_INSTALL_PATH/ti/boot/sbl/board//buildrr}r(jUjjubajjubjXz: Makefile for bootloader that provides list of source files and library and compiler options to create bootloader binary.rr}r(jXz: Makefile for bootloader that provides list of source files and library and compiler options to create bootloader binary.jj ubeubaubaubj)r}r(jX**Source Files:**rjjjjrjjj}r(j]j]j]j]j]ujKIjhj]rj)r }r!(jjj}r"(j]j]j]j]j]ujjj]r#jX Source Files:r$r%}r&(jUjj ubajjubaubjt)r'}r((jUjjjjrjjwj}r)(jyX-j]j]j]j]j]ujKKjhj]r*(j{)r+}r,(jXo**PDK_INSTALL_PATH/ti/boot/sbl/board/**: Source to SBL main function that consolidates all featuresjj'jjrjjj}r-(j]j]j]j]j]ujNjhj]r.j)r/}r0(jXo**PDK_INSTALL_PATH/ti/boot/sbl/board/**: Source to SBL main function that consolidates all featuresjj+jjrjjj}r1(j]j]j]j]j]ujKKj]r2(j)r3}r4(jX3**PDK_INSTALL_PATH/ti/boot/sbl/board/**j}r5(j]j]j]j]j]ujj/j]r6jX/PDK_INSTALL_PATH/ti/boot/sbl/board/r7r8}r9(jUjj3ubajjubjX<: Source to SBL main function that consolidates all featuresr:r;}r<(jX<: Source to SBL main function that consolidates all featuresjj/ubeubaubj{)r=}r>(jX\**PDK_INSTALL_PATH/ti/boot/sbl/soc**: Source to SOC specific initialization used in the SBL.jj'jjrjjj}r?(j]j]j]j]j]ujNjhj]r@j)rA}rB(jX\**PDK_INSTALL_PATH/ti/boot/sbl/soc**: Source to SOC specific initialization used in the SBL.jj=jjrjjj}rC(j]j]j]j]j]ujKMj]rD(j)rE}rF(jX$**PDK_INSTALL_PATH/ti/boot/sbl/soc**j}rG(j]j]j]j]j]ujjAj]rHjX PDK_INSTALL_PATH/ti/boot/sbl/socrIrJ}rK(jUjjEubajjubjX8: Source to SOC specific initialization used in the SBL.rLrM}rN(jX8: Source to SOC specific initialization used in the SBL.jjAubeubaubj{)rO}rP(jXd**PDK_INSTALL_PATH/ti/boot/sbl/src**: Source to boot media specific initialization used in the SBL. jj'jjrjjj}rQ(j]j]j]j]j]ujNjhj]rRj)rS}rT(jXc**PDK_INSTALL_PATH/ti/boot/sbl/src**: Source to boot media specific initialization used in the SBL.jjOjjrjjj}rU(j]j]j]j]j]ujKOj]rV(j)rW}rX(jX$**PDK_INSTALL_PATH/ti/boot/sbl/src**j}rY(j]j]j]j]j]ujjSj]rZjX PDK_INSTALL_PATH/ti/boot/sbl/srcr[r\}r](jUjjWubajjubjX?: Source to boot media specific initialization used in the SBL.r^r_}r`(jX?: Source to boot media specific initialization used in the SBL.jjSubeubaubeubjc)ra}rb(jUjjjjrjjfj}rc(j]j]j]j]j]ujKRjhj]rdji)re}rf(jUjlKjjajjrjjj}rg(j]j]j]j]j]ujKjhj]ubaubeubj)rh}ri(jUjKjj`jjrjjj}rj(j]rkjraj]j]j]rlUid72rmaj]ujKUjhj]rn(j)ro}rp(jXTools and Binary Formatsrqjjhjjrjjj}rr(j]j]j]j]j]ujKUjhj]rsjXTools and Binary Formatsrtru}rv(jjqjjoubaubj)rw}rx(jXThis section lists out the various tools and scripts used by SBL for different boot modes and those required to create a bootable application image.ryjjhjjrjjj}rz(j]j]j]j]j]ujKWjhj]r{jXThis section lists out the various tools and scripts used by SBL for different boot modes and those required to create a bootable application image.r|r}}r~(jjyjjwubaubj)r}r(jX"**SBL/MLO image format:** To generate the *MLO*, SBL uses tiImageGen tool to prepend the sbl.bin image with the TI header information. The image format has been described in detail in the Image Format Section of the\ `AM57xx Technical Reference manual `__jjhjjrjjj}r(j]j]j]j]j]ujK[jhj]r(j)r}r(jX**SBL/MLO image format:**j}r(j]j]j]j]j]ujjj]rjXSBL/MLO image format:rr}r(jUjjubajjubjX To generate the rr}r(jX To generate the jjubjM)r}r(jX*MLO*j}r(j]j]j]j]j]ujjj]rjXMLOrr}r(jUjjubajjUubjX, SBL uses tiImageGen tool to prepend the sbl.bin image with the TI header information. The image format has been described in detail in the Image Format Section of therr}r(jX, SBL uses tiImageGen tool to prepend the sbl.bin image with the TI header information. The image format has been described in detail in the Image Format Section of the\ jjubj)r}r(jXI`AM57xx Technical Reference manual `__j}r(UnameX!AM57xx Technical Reference manualjX!http://www.ti.com/lit/pdf/spruhz6j]j]j]j]j]ujjj]rjX!AM57xx Technical Reference manualrr}r(jUjjubajjubeubjc)r}r(jUjjhjjrjjfj}r(j]j]j]j]j]ujKajhj]rji)r}r(jUjlKjjjjrjjj}r(j]j]j]j]j]ujKjhj]ubaubj)r}r(jX**Application image format:** A bootable application image can be created by using the Am57xImageGen script provided under tools folder as part of sbl. It can be located at */packages/ti/boot/sbl/tools/scripts* folder.jjhjjrjjj}r(j]j]j]j]j]ujKbjhj]r(j)r}r(jX**Application image format:**j}r(j]j]j]j]j]ujjj]rjXApplication image format:rr}r(jUjjubajjubjX A bootable application image can be created by using the Am57xImageGen script provided under tools folder as part of sbl. It can be located at rr}r(jX A bootable application image can be created by using the Am57xImageGen script provided under tools folder as part of sbl. It can be located at jjubjM)r}r(jX6*/packages/ti/boot/sbl/tools/scripts*j}r(j]j]j]j]j]ujjj]rjX4/packages/ti/boot/sbl/tools/scriptsrr}r(jUjjubajjUubjX folder.rr}r(jX folder.jjubeubj)r}r(jXThe Am57xImageGen script uses out2rprc and multicoreImageGen format conversion tools to create the final application image. Graphical view of the multicore application image is provided below:rjjhjjrjjj}r(j]j]j]j]j]ujKgjhj]rjXThe Am57xImageGen script uses out2rprc and multicoreImageGen format conversion tools to create the final application image. Graphical view of the multicore application image is provided below:r–rÖ}rĖ(jjjjubaubjR)rŖ}rƖ(jX-.. Image:: ../images/Multicore_app_image.png jjhjjrjjZj}rǖ(UuriX&rtos/../images/Multicore_app_image.pngrȖj]j]j]j]jX}rɖU*jȖsj]ujKljhj]ubj)rʖ}r˖(jX0The script creates the bootable image in 2 stepsr̖jjhjjrjjj}r͖(j]j]j]j]j]ujKmjhj]rΖjX0The script creates the bootable image in 2 stepsrϖrЖ}rі(jj̖jjʖubaubj)rҖ}rӖ(jX0**Step 1: Conversion to RPRC format conversion**rԖjjhjjrjjj}rՖ(j]j]j]j]j]ujKojhj]r֖j)rז}rؖ(jjԖj}rٖ(j]j]j]j]j]ujjҖj]rږjX,Step 1: Conversion to RPRC format conversionrۖrܖ}rݖ(jUjjזubajjubaubjt)rޖ}rߖ(jUjjhjjrjjwj}r(jyX-j]j]j]j]j]ujKqjhj]r(j{)r}r(jXkFirstly, application executable is converted from ELF/COFF format (.out) to custom TI Rprc binary image using out2rprc tool. This tool strips out the initialized sections from the executable file (i.e. \*.out) and places them in a compact format that the SBL can understand. The output (bin) file is typically much smaller than the original executable (out) file.jjޖjjrjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXkFirstly, application executable is converted from ELF/COFF format (.out) to custom TI Rprc binary image using out2rprc tool. This tool strips out the initialized sections from the executable file (i.e. \*.out) and places them in a compact format that the SBL can understand. The output (bin) file is typically much smaller than the original executable (out) file.jjjjrjjj}r(j]j]j]j]j]ujKqj]rjXjFirstly, application executable is converted from ELF/COFF format (.out) to custom TI Rprc binary image using out2rprc tool. This tool strips out the initialized sections from the executable file (i.e. *.out) and places them in a compact format that the SBL can understand. The output (bin) file is typically much smaller than the original executable (out) file.rr}r(jXkFirstly, application executable is converted from ELF/COFF format (.out) to custom TI Rprc binary image using out2rprc tool. This tool strips out the initialized sections from the executable file (i.e. \*.out) and places them in a compact format that the SBL can understand. The output (bin) file is typically much smaller than the original executable (out) file.jjubaubaubj{)r}r(jX~The rprc files are intermediate files in a format that is consumed by MulticoreImageGen tool that generates the final binary. jjޖjjrjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX}The rprc files are intermediate files in a format that is consumed by MulticoreImageGen tool that generates the final binary.rjjjjrjjj}r(j]j]j]j]j]ujKwj]rjX}The rprc files are intermediate files in a format that is consumed by MulticoreImageGen tool that generates the final binary.rr}r(jjjjubaubaubeubj)r}r(jX**RPRC File Header Format**rjjhjjrjjj}r(j]j]j]j]j]ujKzjhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXRPRC File Header Formatrr}r(jUjjubajjubaubjy )r}r(jUjjhjjrjj j}r(j]j]j]j]j]ujNjhj]rj~ )r }r (jUj}r (j]j]j]j]j]UcolsKujjj]r (j )r }r(jUj}r(j]j]j]j]j]UcolwidthK ujj j]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujj j]jj ubj )r}r(jUj}r(j]j]j]j]j]ujj j]rj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r (jXOffsetr!jjjjrjjj}r"(j]j]j]j]j]ujK}j]r#jXOffsetr$r%}r&(jj!jjubaubajj ubj )r'}r((jUj}r)(j]j]j]j]j]ujjj]r*j)r+}r,(jX Binary valuer-jj'jjrjjj}r.(j]j]j]j]j]ujK}j]r/jX Binary valuer0r1}r2(jj-jj+ubaubajj ubejj ubajj ubj )r3}r4(jUj}r5(j]j]j]j]j]ujj j]r6(j )r7}r8(jUj}r9(j]j]j]j]j]ujj3j]r:(j )r;}r<(jUj}r=(j]j]j]j]j]ujj7j]r>j)r?}r@(jX 0x00000000rAjj;jjrjjj}rB(j]j]j]j]j]ujKj]rCjX 0x00000000rDrE}rF(jjAjj?ubaubajj ubj )rG}rH(jUj}rI(j]j]j]j]j]ujj7j]rJj)rK}rL(jX**Magic Word(43525052)**rMjjGjjrjjj}rN(j]j]j]j]j]ujKj]rOj)rP}rQ(jjMj}rR(j]j]j]j]j]ujjKj]rSjXMagic Word(43525052)rTrU}rV(jUjjPubajjubaubajj ubejj ubj )rW}rX(jUj}rY(j]j]j]j]j]ujj3j]rZ(j )r[}r\(jUj}r](j]j]j]j]j]ujjWj]r^j)r_}r`(jX 0x00000004rajj[jjrjjj}rb(j]j]j]j]j]ujKj]rcjX 0x00000004rdre}rf(jjajj_ubaubajj ubj )rg}rh(jUj}ri(j]j]j]j]j]ujjWj]rjj)rk}rl(jX**Entry Point (Location)**rmjjgjjrjjj}rn(j]j]j]j]j]ujKj]roj)rp}rq(jjmj}rr(j]j]j]j]j]ujjkj]rsjXEntry Point (Location)rtru}rv(jUjjpubajjubaubajj ubejj ubj )rw}rx(jUj}ry(j]j]j]j]j]ujj3j]rz(j )r{}r|(jUj}r}(j]j]j]j]j]ujjwj]r~j)r}r(jX 0x00000008rjj{jjrjjj}r(j]j]j]j]j]ujKj]rjX 0x00000008rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjwj]rj)r}r(jX**Reserved Addr**rjjjjrjjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX Reserved Addrrr}r(jUjjubajjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujj3j]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX 0x0000000Crjjjjrjjj}r(j]j]j]j]j]ujKj]rjX 0x0000000Crr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX**Section Count**rjjjjrjjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX Section Countrr}r(jUjjubajjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujj3j]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX 0x00000010rjjjjrjjj}r—(j]j]j]j]j]ujKj]r×jX 0x00000010rėrŗ}rƗ(jjjjubaubajj ubj )rǗ}rȗ(jUj}rɗ(j]j]j]j]j]ujjj]rʗj)r˗}r̗(jX **Version**r͗jjǗjjrjjj}rΗ(j]j]j]j]j]ujKj]rϗj)rЗ}rї(jj͗j}rҗ(j]j]j]j]j]ujj˗j]rӗjXVersionrԗr՗}r֗(jUjjЗubajjubaubajj ubejj ubejj ubejj ubaubj)rח}rؗ(jX**RPRC Section Header Format**rٗjjhjjrjjj}rڗ(j]j]j]j]j]ujKjhj]rۗj)rܗ}rݗ(jjٗj}rޗ(j]j]j]j]j]ujjחj]rߗjXRPRC Section Header Formatrr}r(jUjjܗubajjubaubjy )r}r(jUjjhjjrjj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujjj]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthK ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXOffsetrjjjjrjjj}r(j]j]j]j]j]ujKj]rjXOffsetrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r }r (jX Binary valuer jjjjrjjj}r (j]j]j]j]j]ujKj]r jX Binary valuerr}r(jj jj ubaubajj ubejj ubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX 0x00000000rjjjjrjjj}r (j]j]j]j]j]ujKj]r!jX 0x00000000r"r#}r$(jjjjubaubajj ubj )r%}r&(jUj}r'(j]j]j]j]j]ujjj]r(j)r)}r*(jX**Section start Address**r+jj%jjrjjj}r,(j]j]j]j]j]ujKj]r-j)r.}r/(jj+j}r0(j]j]j]j]j]ujj)j]r1jXSection start Addressr2r3}r4(jUjj.ubajjubaubajj ubejj ubj )r5}r6(jUj}r7(j]j]j]j]j]ujjj]r8(j )r9}r:(jUj}r;(j]j]j]j]j]ujj5j]r<j)r=}r>(jX 0x00000004r?jj9jjrjjj}r@(j]j]j]j]j]ujKj]rAjX 0x00000004rBrC}rD(jj?jj=ubaubajj ubj )rE}rF(jUj}rG(j]j]j]j]j]ujj5j]rHj)rI}rJ(jX**Reserved Addr**rKjjEjjrjjj}rL(j]j]j]j]j]ujKj]rMj)rN}rO(jjKj}rP(j]j]j]j]j]ujjIj]rQjX Reserved AddrrRrS}rT(jUjjNubajjubaubajj ubejj ubj )rU}rV(jUj}rW(j]j]j]j]j]ujjj]rX(j )rY}rZ(jUj}r[(j]j]j]j]j]ujjUj]r\j)r]}r^(jX 0x00000008r_jjYjjrjjj}r`(j]j]j]j]j]ujKj]rajX 0x00000008rbrc}rd(jj_jj]ubaubajj ubj )re}rf(jUj}rg(j]j]j]j]j]ujjUj]rhj)ri}rj(jX**Size**rkjjejjrjjj}rl(j]j]j]j]j]ujKj]rmj)rn}ro(jjkj}rp(j]j]j]j]j]ujjij]rqjXSizerrrs}rt(jUjjnubajjubaubajj ubejj ubj )ru}rv(jUj}rw(j]j]j]j]j]ujjj]rx(j )ry}rz(jUj}r{(j]j]j]j]j]ujjuj]r|j)r}}r~(jX 0x0000000Crjjyjjrjjj}r(j]j]j]j]j]ujKj]rjX 0x0000000Crr}r(jjjj}ubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjuj]rj)r}r(jX**Reserved CRC**rjjjjrjjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX Reserved CRCrr}r(jUjjubajjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX 0x00000010rjjjjrjjj}r(j]j]j]j]j]ujKj]rjX 0x00000010rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX **Reserved**rjjjjrjjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXReservedrr}r(jUjjubajjubaubajj ubejj ubejj ubejj ubaubjc)r}r(jUjjhjjrjjfj}r(j]j]j]j]j]ujKjhj]rji)r}r(jUjlKjjjjrjjj}r(j]j]j]j]j]ujKjhj]ubaubj)r}r(jX+**Step 2: Multicore Image file generation**rjjhjjrjjj}r(j]j]j]j]j]ujKjhj]rj)r}r˜(jjj}rØ(j]j]j]j]j]ujjj]rĘjX'Step 2: Multicore Image file generationrŘrƘ}rǘ(jUjjubajjubaubjt)rȘ}rɘ(jUjjhjjrjjwj}rʘ(jyX-j]j]j]j]j]ujKjhj]r˘j{)r̘}r͘(jXZRPRC files for each cores is combined into a single multicore bootable application image. jjȘjjrjjj}rΘ(j]j]j]j]j]ujNjhj]rϘj)rИ}rј(jXYRPRC files for each cores is combined into a single multicore bootable application image.rҘjj̘jjrjjj}rӘ(j]j]j]j]j]ujKj]rԘjXYRPRC files for each cores is combined into a single multicore bootable application image.r՘r֘}rט(jjҘjjИubaubaubaubj)rؘ}r٘(jX**Multicore boot image format**rژjjhjjrjjj}rۘ(j]j]j]j]j]ujKjhj]rܘj)rݘ}rޘ(jjژj}rߘ(j]j]j]j]j]ujjؘj]rjXMulticore boot image formatrr}r(jUjjݘubajjubaubj)r}r(jX**Meta Header Start**rjjhjjrjjj}r(j]j]j]j]j]ujKjhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXMeta Header Startrr}r(jUjjubajjubaubjy )r}r(jUjjhjjrjj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujjj]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthK ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]r j)r }r (jXOffsetr jjjjrjjj}r (j]j]j]j]j]ujKj]rjXOffsetrr}r(jj jj ubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX Binary valuerjjjjrjjj}r(j]j]j]j]j]ujKj]rjX Binary valuerr}r(jjjjubaubajj ubejj ubajj ubj )r}r(jUj}r (j]j]j]j]j]ujjj]r!(j )r"}r#(jUj}r$(j]j]j]j]j]ujjj]r%(j )r&}r'(jUj}r((j]j]j]j]j]ujj"j]r)j)r*}r+(jX 0x00000000r,jj&jjrjjj}r-(j]j]j]j]j]ujKj]r.jX 0x00000000r/r0}r1(jj,jj*ubaubajj ubj )r2}r3(jUj}r4(j]j]j]j]j]ujj"j]r5j)r6}r7(jX**Magic String (0x5254534D)**r8jj2jjrjjj}r9(j]j]j]j]j]ujKj]r:j)r;}r<(jj8j}r=(j]j]j]j]j]ujj6j]r>jXMagic String (0x5254534D)r?r@}rA(jUjj;ubajjubaubajj ubejj ubj )rB}rC(jUj}rD(j]j]j]j]j]ujjj]rE(j )rF}rG(jUj}rH(j]j]j]j]j]ujjBj]rIj)rJ}rK(jX 0x00000004rLjjFjjrjjj}rM(j]j]j]j]j]ujKj]rNjX 0x00000004rOrP}rQ(jjLjjJubaubajj ubj )rR}rS(jUj}rT(j]j]j]j]j]ujjBj]rUj)rV}rW(jX**Number of Files**rXjjRjjrjjj}rY(j]j]j]j]j]ujKj]rZj)r[}r\(jjXj}r](j]j]j]j]j]ujjVj]r^jXNumber of Filesr_r`}ra(jUjj[ubajjubaubajj ubejj ubj )rb}rc(jUj}rd(j]j]j]j]j]ujjj]re(j )rf}rg(jUj}rh(j]j]j]j]j]ujjbj]rij)rj}rk(jX 0x00000008rljjfjjrjjj}rm(j]j]j]j]j]ujKj]rnjX 0x00000008rorp}rq(jjljjjubaubajj ubj )rr}rs(jUj}rt(j]j]j]j]j]ujjbj]ruj)rv}rw(jX **Device ID**rxjjrjjrjjj}ry(j]j]j]j]j]ujKj]rzj)r{}r|(jjxj}r}(j]j]j]j]j]ujjvj]r~jX Device IDrr}r(jUjj{ubajjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX 0x0000000Crjjjjrjjj}r(j]j]j]j]j]ujKj]rjX 0x0000000Crr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX **Reserved**rjjjjrjjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXReservedrr}r(jUjjubajjubaubajj ubejj ubejj ubejj ubaubj)r}r(jX**Meta Header per Core**rjjhjjrjjj}r(j]j]j]j]j]ujKjhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXMeta Header per Corerr}r(jUjjubajjubaubjy )r}r(jUjjhjjrjj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujjj]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthK ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj )r}r(jUj}r™(j]j]j]j]j]ujjj]rÙ(j )rę}rř(jUj}rƙ(j]j]j]j]j]ujjj]rǙj)rș}rə(jXOffsetrʙjjęjjrjjj}r˙(j]j]j]j]j]ujKj]r̙jXOffsetr͙rΙ}rϙ(jjʙjjșubaubajj ubj )rЙ}rљ(jUj}rҙ(j]j]j]j]j]ujjj]rәj)rԙ}rՙ(jX Binary valuer֙jjЙjjrjjj}rי(j]j]j]j]j]ujKj]rؙjX Binary valuerٙrڙ}rۙ(jj֙jjԙubaubajj ubejj ubajj ubj )rܙ}rݙ(jUj}rޙ(j]j]j]j]j]ujjj]rߙ(j )r}r(jUj}r(j]j]j]j]j]ujjܙj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX 0x00000000rjjjjrjjj}r(j]j]j]j]j]ujKj]rjX 0x00000000rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX **Core ID**rjjjjrjjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXCore IDrr}r(jUjjubajjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjܙj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r (jX 0x00000004r jjjjrjjj}r (j]j]j]j]j]ujKj]r jX 0x00000004r r}r(jj jjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX**Image Offset**rjjjjrjjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX Image Offsetrr}r(jUjjubajjubaubajj ubejj ubejj ubejj ubaubj)r }r!(jXCore ID and Device ID for specific devices can be located in the file sbl_slave_core_boot.h in the boot/sbl/soc/ folderr"jjhjjrjjj}r#(j]j]j]j]j]ujKjhj]r$jXCore ID and Device ID for specific devices can be located in the file sbl_slave_core_boot.h in the boot/sbl/soc/ folderr%r&}r'(jj"jj ubaubj)r(}r)(jXRefer section `App Image Creation `__ for more details on usage of this script and application image creation.jjhjjrjjj}r*(j]j]j]j]j]ujKjhj]r+(jXRefer section r,r-}r.(jXRefer section jj(ubj)r/}r0(jXV`App Image Creation `__j}r1(UnameXApp Image CreationjX=index_Foundational_Components.html#application-image-creationj]j]j]j]j]ujj(j]r2jXApp Image Creationr3r4}r5(jUjj/ubajjubjXI for more details on usage of this script and application image creation.r6r7}r8(jXI for more details on usage of this script and application image creation.jj(ubeubj)r9}r:(jX**Flashing Tools**r;jjhjjrjjj}r<(j]j]j]j]j]ujKjhj]r=j)r>}r?(jj;j}r@(j]j]j]j]j]ujj9j]rAjXFlashing ToolsrBrC}rD(jUjj>ubajjubaubj)rE}rF(jXSBL provides a CCS based qspi flash writer utility to flash image and multicore AppImage from a SD card to onboard QSPI device. It is located at */packages/ti/boot/sbl/tools/flashWriter/qspi*jjhjjrjjj}rG(j]j]j]j]j]ujKjhj]rH(jXSBL provides a CCS based qspi flash writer utility to flash image and multicore AppImage from a SD card to onboard QSPI device. It is located at rIrJ}rK(jXSBL provides a CCS based qspi flash writer utility to flash image and multicore AppImage from a SD card to onboard QSPI device. It is located at jjEubjM)rL}rM(jX?*/packages/ti/boot/sbl/tools/flashWriter/qspi*j}rN(j]j]j]j]j]ujjEj]rOjX=/packages/ti/boot/sbl/tools/flashWriter/qspirPrQ}rR(jUjjLubajjUubeubeubj)rS}rT(jUjj`jjrjjj}rU(j]j]j]j]rVUbuilding-the-sblrWaj]rXjaujKjhj]rY(j)rZ}r[(jXBuilding the SBLr\jjSjjrjjj}r](j]j]j]j]j]ujKjhj]r^jXBuilding the SBLr_r`}ra(jj\jjZubaubj)rb}rc(jX**Pre-requisites to Building**rdjjSjjrjjj}re(j]j]j]j]j]ujKjhj]rfj)rg}rh(jjdj}ri(j]j]j]j]j]ujjbj]rjjXPre-requisites to Buildingrkrl}rm(jUjjgubajjubaubjt)rn}ro(jUjjSjjrjjwj}rp(jyX-j]j]j]j]j]ujKjhj]rq(j{)rr}rs(jXSet your environment using pdksetupenv.bat or pdksetupenv.sh. Refer to the Processor SDK RTOS Building page for information on setting up your build environmentjjnjjrjjj}rt(j]j]j]j]j]ujNjhj]ruj)rv}rw(jXSet your environment using pdksetupenv.bat or pdksetupenv.sh. Refer to the Processor SDK RTOS Building page for information on setting up your build environmentrxjjrjjrjjj}ry(j]j]j]j]j]ujKj]rzjXSet your environment using pdksetupenv.bat or pdksetupenv.sh. Refer to the Processor SDK RTOS Building page for information on setting up your build environmentr{r|}r}(jjxjjvubaubaubj{)r~}r(jXThe SBL has following dependencies and will need the following libraries built - Board - UART - I2C - SPI - CSL - OSAL - MMCSD - PM jjnjNjjj}r(j]j]j]j]j]ujNjhj]r(j)r}r(jXNThe SBL has following dependencies and will need the following libraries builtrjj~jjrjjj}r(j]j]j]j]j]ujKj]rjXNThe SBL has following dependencies and will need the following libraries builtrr}r(jjjjubaubjt)r}r(jUj}r(jyX-j]j]j]j]j]ujj~j]r(j{)r}r(jXBoardrj}r(j]j]j]j]j]ujjj]rj)r}r(jjjjjjrjjj}r(j]j]j]j]j]ujKj]rjXBoardrr}r(jjjjubaubajjubj{)r}r(jXUARTrj}r(j]j]j]j]j]ujjj]rj)r}r(jjjjjjrjjj}r(j]j]j]j]j]ujKj]rjXUARTrr}r(jjjjubaubajjubj{)r}r(jXI2Crj}r(j]j]j]j]j]ujjj]rj)r}r(jjjjjjrjjj}r(j]j]j]j]j]ujKj]rjXI2Crr}r(jjjjubaubajjubj{)r}r(jXSPIrj}r(j]j]j]j]j]ujjj]rj)r}r(jjjjjjrjjj}r(j]j]j]j]j]ujKj]rjXSPIrr}r(jjjjubaubajjubj{)r}r(jXCSLrj}r(j]j]j]j]j]ujjj]ršj)rÚ}rĚ(jjjjjjrjjj}rŚ(j]j]j]j]j]ujKj]rƚjXCSLrǚrȚ}rɚ(jjjjÚubaubajjubj{)rʚ}r˚(jXOSALr̚j}r͚(j]j]j]j]j]ujjj]rΚj)rϚ}rК(jj̚jjʚjjrjjj}rњ(j]j]j]j]j]ujKj]rҚjXOSALrӚrԚ}r՚(jj̚jjϚubaubajjubj{)r֚}rך(jXMMCSDrؚj}rٚ(j]j]j]j]j]ujjj]rښj)rۚ}rܚ(jjؚjj֚jjrjjj}rݚ(j]j]j]j]j]ujKj]rޚjXMMCSDrߚr}r(jjؚjjۚubaubajjubj{)r}r(jXPM j}r(j]j]j]j]j]ujjj]rj)r}r(jXPMrjjjjrjjj}r(j]j]j]j]j]ujKj]rjXPMrr}r(jjjjubaubajjubejjwubeubeubj)r}r(jXRefer to the makefile for the board you are using for the latest driver dependency. These libraries should come pre-built with any fresh installation of the Processor SDK RTOS but may be removed if a gmake clean is invokedjjSjjrjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXRefer to the makefile for the board you are using for the latest driver dependency. These libraries should come pre-built with any fresh installation of the Processor SDK RTOS but may be removed if a gmake clean is invokedrjjjjrjjj}r(j]j]j]j]j]ujKj]rjXRefer to the makefile for the board you are using for the latest driver dependency. These libraries should come pre-built with any fresh installation of the Processor SDK RTOS but may be removed if a gmake clean is invokedrr}r(jjjjubaubaubj)r}r(jX **Compiling the SBL Components**rjjSjjrjjj}r(j]j]j]j]j]ujKjhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXCompiling the SBL Componentsrr}r(jUjjubajjubaubj)r}r(jXTo build the SBL components:rjjSjjrjjj}r (j]j]j]j]j]ujKjhj]r jXTo build the SBL components:r r }r (jjjjubaubj )r}r(jUjjSjjrjj j}r(jU.j]j]j]jUj]j]jjujKjhj]r(j{)r}r(jX#**cd /packages/ti/board/diag**rjjjjrjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjrjjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXcd /packages/ti/board/diagrr }r!(jUjjubajjubaubaubj{)r"}r#(jXD**make all BOARD= SOC= BOOTMODE=** jjjjrjjj}r$(j]j]j]j]j]ujNjhj]r%j)r&}r'(jXC**make all BOARD= SOC= BOOTMODE=**r(jj"jjrjjj}r)(j]j]j]j]j]ujKj]r*j)r+}r,(jj(j}r-(j]j]j]j]j]ujj&j]r.jX?make all BOARD= SOC= BOOTMODE=r/r0}r1(jUjj+ubajjubaubaubeubjt)r2}r3(jUjjSjjrjjwj}r4(jyX-j]j]j]j]j]ujKjhj]r5(j{)r6}r7(jX8BOARD_NAME : idkAM572x, idkAM571x, evmAM572x, idkAM574xr8jj2jjrjjj}r9(j]j]j]j]j]ujNjhj]r:j)r;}r<(jj8jj6jjrjjj}r=(j]j]j]j]j]ujKj]r>jX8BOARD_NAME : idkAM572x, idkAM571x, evmAM572x, idkAM574xr?r@}rA(jj8jj;ubaubaubj{)rB}rC(jX#SOC_NAME : AM572x, AM571x, AM574x jj2jjrjjj}rD(j]j]j]j]j]ujNjhj]rEj)rF}rG(jX"SOC_NAME : AM572x, AM571x, AM574xrHjjBjjrjjj}rI(j]j]j]j]j]ujKj]rJjX"SOC_NAME : AM572x, AM571x, AM574xrKrL}rM(jjHjjFubaubaubeubj)rN}rO(jXThis will make the SBL for a specific $BOARD and $BOOT_MEDIA. Output files will be located in: **/packages/ti/boot/sbl/binary/**jjSjjrjjj}rP(j]j]j]j]j]ujKjhj]rQ(jX_This will make the SBL for a specific $BOARD and $BOOT_MEDIA. Output files will be located in: rRrS}rT(jX_This will make the SBL for a specific $BOARD and $BOOT_MEDIA. Output files will be located in: jjNubj)rU}rV(jX-**/packages/ti/boot/sbl/binary/**j}rW(j]j]j]j]j]ujjNj]rXjX)/packages/ti/boot/sbl/binary/rYrZ}r[(jUjjUubajjubeubj)r\}r](jXKRefer **/packages/ti/boot/sbl/sbl_.sh** for more build optionsjjSjjrjjj}r^(j]j]j]j]j]ujNjhj]r_j)r`}ra(jXKRefer **/packages/ti/boot/sbl/sbl_.sh** for more build optionsjj\jjrjjj}rb(j]j]j]j]j]ujKj]rc(jXRefer rdre}rf(jXRefer jj`ubj)rg}rh(jX.**/packages/ti/boot/sbl/sbl_.sh**j}ri(j]j]j]j]j]ujj`j]rjjX*/packages/ti/boot/sbl/sbl_.shrkrl}rm(jUjjgubajjubjX for more build optionsrnro}rp(jX for more build optionsjj`ubeubaubjhK)rq}rr(jX Boot ModesrsjjSjjrjjlKj}rt(j]ruUid73rvaj]j]j]j]rwj"aujNjhj]rxjX Boot Modesryrz}r{(jjsjjqubaubj)r|}r}(jXThis Release of SBL supports MMCSD and QSPI Boot modes. The different boot modes supported for all the boards is tabulated in the table below.r~jjSjjrjjj}r(j]j]j]j]j]ujKjhj]rjXThis Release of SBL supports MMCSD and QSPI Boot modes. The different boot modes supported for all the boards is tabulated in the table below.rr}r(jj~jj|ubaubjy )r}r(jUjjSjjrjj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujjj]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXMMCSDrjjjjrjjj}r(j]j]j]j]j]ujKj]rjXMMCSDrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXQSPIrjjjjrjjj}r(j]j]j]j]j]ujKj]rjXQSPIrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXeMMCrjjjjrjjj}r›(j]j]j]j]j]ujKj]rÛjXeMMCrěrś}rƛ(jjjjubaubajj ubejj ubj )rǛ}rț(jUj}rɛ(j]j]j]j]j]ujjj]rʛ(j )r˛}r̛(jUj}r͛(j]j]j]j]j]ujjǛj]rΛj)rϛ}rЛ(jX AM572x GPEVMrћjj˛jjrjjj}rқ(j]j]j]j]j]ujKj]rӛjX AM572x GPEVMrԛr՛}r֛(jjћjjϛubaubajj ubj )rכ}r؛(jUj}rٛ(j]j]j]j]j]ujjǛj]rڛj)rۛ}rܛ(jXYESrݛjjכjjrjjj}rޛ(j]j]j]j]j]ujKj]rߛjXYESrr}r(jjݛjjۛubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjǛj]rj)r}r(jXNOrjjjjrjjj}r(j]j]j]j]j]ujKj]rjXNOrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjǛj]rj)r}r(jXYESrjjjjrjjj}r(j]j]j]j]j]ujKj]rjXYESrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX AM572x IDKEVMrjjjjrjjj}r(j]j]j]j]j]ujMj]rjX AM572x IDKEVMrr }r (jjjjubaubajj ubj )r }r (jUj}r (j]j]j]j]j]ujjj]rj)r}r(jXYESrjj jjrjjj}r(j]j]j]j]j]ujMj]rjXYESrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXYESrjjjjrjjj}r(j]j]j]j]j]ujMj]rjXYESr r!}r"(jjjjubaubajj ubj )r#}r$(jUj}r%(j]j]j]j]j]ujjj]r&j)r'}r((jXNOr)jj#jjrjjj}r*(j]j]j]j]j]ujMj]r+jXNOr,r-}r.(jj)jj'ubaubajj ubejj ubj )r/}r0(jUj}r1(j]j]j]j]j]ujjj]r2(j )r3}r4(jUj}r5(j]j]j]j]j]ujj/j]r6j)r7}r8(jX AM571x IDKEVMr9jj3jjrjjj}r:(j]j]j]j]j]ujMj]r;jX AM571x IDKEVMr<r=}r>(jj9jj7ubaubajj ubj )r?}r@(jUj}rA(j]j]j]j]j]ujj/j]rBj)rC}rD(jXYESrEjj?jjrjjj}rF(j]j]j]j]j]ujMj]rGjXYESrHrI}rJ(jjEjjCubaubajj ubj )rK}rL(jUj}rM(j]j]j]j]j]ujj/j]rNj)rO}rP(jXYESrQjjKjjrjjj}rR(j]j]j]j]j]ujMj]rSjXYESrTrU}rV(jjQjjOubaubajj ubj )rW}rX(jUj}rY(j]j]j]j]j]ujj/j]rZj)r[}r\(jXNOr]jjWjjrjjj}r^(j]j]j]j]j]ujMj]r_jXNOr`ra}rb(jj]jj[ubaubajj ubejj ubj )rc}rd(jUj}re(j]j]j]j]j]ujjj]rf(j )rg}rh(jUj}ri(j]j]j]j]j]ujjcj]rjj)rk}rl(jX AM574x IDKEVMrmjjgjjrjjj}rn(j]j]j]j]j]ujMj]rojX AM574x IDKEVMrprq}rr(jjmjjkubaubajj ubj )rs}rt(jUj}ru(j]j]j]j]j]ujjcj]rvj)rw}rx(jXYESryjjsjjrjjj}rz(j]j]j]j]j]ujMj]r{jXYESr|r}}r~(jjyjjwubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjcj]rj)r}r(jXYESrjjjjrjjj}r(j]j]j]j]j]ujMj]rjXYESrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjcj]rj)r}r(jXNOrjjjjrjjj}r(j]j]j]j]j]ujMj]rjXNOrr}r(jjjjubaubajj ubejj ubejj ubejj ubaubjc)r}r(jUjjSjjrjjfj}r(j]j]j]j]j]ujMjhj]rji)r}r(jUjlKjjjjrjjj}r(j]j]j]j]j]ujKjhj]ubaubj)r}r(jUjKjjSjjrjjj}r(j]rjGaj]j]j]rUid74raj]ujM jhj]r(j)r}r(jXBooting Via SD Cardrjjjjrjjj}r(j]j]j]j]j]ujM jhj]rjXBooting Via SD Cardrr}r(jjjjubaubj )r}r(jUjjjjrjj j}r(jU.j]j]j]jUj]j]jjujM jhj]r(j{)r}r(jXPreparing the SD card.rjjjjrjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjrjjj}r(j]j]j]j]j]ujM j]rjXPreparing the SD card.rr}r(jjjjubaubaubj{)r}r(jXBooting the target. jjjjrjjj}r(j]j]j]j]j]ujNjhj]rj)r}rœ(jXBooting the target.rÜjjjjrjjj}rĜ(j]j]j]j]j]ujM j]rŜjXBooting the target.rƜrǜ}rȜ(jjÜjjubaubaubeubj)rɜ}rʜ(jUjKjjjjrjjj}r˜(j]r̜Xpreparing the sd cardr͜aj]j]j]rΜUpreparing-the-sd-cardrϜaj]ujMjhj]rМ(j)rќ}rҜ(jXPreparing the SD cardrӜjjɜjjrjjj}rԜ(j]j]j]j]j]ujMjhj]r՜jXPreparing the SD cardr֜rל}r؜(jjӜjjќubaubj )rٜ}rڜ(jUjjɜjjrjj j}rۜ(jU.j]j]j]jUj]j]jjujMjhj]rܜ(j{)rݜ}rޜ(jXTo boot the target the SD card should be bootable. Follow the steps at `Creating bootable SD card in windows `__ or `Creating bootable SD card in Linux `__.jjٜjjrjjj}rߜ(j]j]j]j]j]ujNjhj]rj)r}r(jXTo boot the target the SD card should be bootable. Follow the steps at `Creating bootable SD card in windows `__ or `Creating bootable SD card in Linux `__.jjݜjjrjjj}r(j]j]j]j]j]ujMj]r(jXGTo boot the target the SD card should be bootable. Follow the steps at rr}r(jXGTo boot the target the SD card should be bootable. Follow the steps at jjubj)r}r(jX]`Creating bootable SD card in windows `__j}r(UnameX$Creating bootable SD card in windowsjX2index_overview.html#windows-sd-card-creation-guidej]j]j]j]j]ujjj]rjX$Creating bootable SD card in windowsrr}r(jUjjubajjubjX or rr}r(jX or jjubj)r}r(jXY`Creating bootable SD card in Linux `__j}r(UnameX"Creating bootable SD card in LinuxjX0index_overview.html#linux-sd-card-creation-guidej]j]j]j]j]ujjj]rjX"Creating bootable SD card in Linuxrr}r(jUjjubajjubjX.r}r(jX.jjubeubaubj{)r}r(jXnDelete the "MLO" and "app" in the bootable SD card which are created in the process of making the SD bootable.jjٜjjrjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXnDelete the "MLO" and "app" in the bootable SD card which are created in the process of making the SD bootable.rjjjjrjjj}r(j]j]j]j]j]ujMj]rjXnDelete the "MLO" and "app" in the bootable SD card which are created in the process of making the SD bootable.rr}r(jjjjubaubaubj{)r}r(jX(Copy the sbl binary(MLO) to the SD card.r jjٜjjrjjj}r (j]j]j]j]j]ujNjhj]r j)r }r (jj jjjjrjjj}r(j]j]j]j]j]ujMj]rjX(Copy the sbl binary(MLO) to the SD card.rr}r(jj jj ubaubaubj{)r}r(jXCopy the Application image(app) generated using the `Script `__ to the SD card. jjٜjjrjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXCopy the Application image(app) generated using the `Script `__ to the SD card.jjjjrjjj}r(j]j]j]j]j]ujMj]r(jX4Copy the Application image(app) generated using the rr}r(jX4Copy the Application image(app) generated using the jjubj)r}r(jXJ`Script `__j}r (UnameXScriptjX=index_Foundational_Components.html#application-image-creationj]j]j]j]j]ujjj]r!jXScriptr"r#}r$(jUjjubajjubjX to the SD card.r%r&}r'(jX to the SD card.jjubeubaubeubeubj)r(}r)(jUjKjjjjrjjj}r*(j]r+Xbooting the targetr,aj]j]j]r-Uid75r.aj]ujMjhj]r/(j)r0}r1(jXBooting the targetr2jj(jjrjjj}r3(j]j]j]j]j]ujMjhj]r4jXBooting the targetr5r6}r7(jj2jj0ubaubj )r8}r9(jUjj(jjrjj j}r:(jU.j]j]j]jUj]j]jjujMjhj]r;(j{)r<}r=(jX8Insert micro SD card into the SD card slot of the board.r>jj8jjrjjj}r?(j]j]j]j]j]ujNjhj]r@j)rA}rB(jj>jj<jjrjjj}rC(j]j]j]j]j]ujMj]rDjX8Insert micro SD card into the SD card slot of the board.rErF}rG(jj>jjAubaubaubj{)rH}rI(jXkOpen a serial communication terminal like TeraTerm, MiniCom on host PC and connect to the UART console portjj8jjrjjj}rJ(j]j]j]j]j]ujNjhj]rKj)rL}rM(jXkOpen a serial communication terminal like TeraTerm, MiniCom on host PC and connect to the UART console portrNjjHjjrjjj}rO(j]j]j]j]j]ujM j]rPjXkOpen a serial communication terminal like TeraTerm, MiniCom on host PC and connect to the UART console portrQrR}rS(jjNjjLubaubaubj{)rT}rU(jXGDo a power reset of the board to boot the appliation from the SD card. jj8jjrjjj}rV(j]j]j]j]j]ujNjhj]rWj)rX}rY(jXFDo a power reset of the board to boot the appliation from the SD card.rZjjTjjrjjj}r[(j]j]j]j]j]ujM"j]r\jXFDo a power reset of the board to boot the appliation from the SD card.r]r^}r_(jjZjjXubaubaubeubeubeubj)r`}ra(jUjjSjjrjjj}rb(j]j]j]j]rcUbooting-via-emmcrdaj]rej#aujM&jhj]rf(j)rg}rh(jXBooting Via eMMCrijj`jjrjjj}rj(j]j]j]j]j]ujM&jhj]rkjXBooting Via eMMCrlrm}rn(jjijjgubaubj )ro}rp(jUjj`jjrjj j}rq(jU.j]j]j]jUj]j]jjujM(jhj]rr(j{)rs}rt(jXPreparing the eMMC.rujjojjrjjj}rv(j]j]j]j]j]ujNjhj]rwj)rx}ry(jjujjsjjrjjj}rz(j]j]j]j]j]ujM(j]r{jXPreparing the eMMC.r|r}}r~(jjujjxubaubaubj{)r}r(jXBooting the target. jjojjrjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXBooting the target.rjjjjrjjj}r(j]j]j]j]j]ujM)j]rjXBooting the target.rr}r(jjjjubaubaubeubj)r}r(jUjj`jjrjjj}r(j]j]j]j]rUpreparing-the-emmcraj]rhaujM,jhj]r(j)r}r(jXPreparing the eMMCrjjjjrjjj}r(j]j]j]j]j]ujM,jhj]rjXPreparing the eMMCrr}r(jjjjubaubj )r}r(jUjjjjrjj j}r(jU.j]j]j]jUj]j]jjujM.jhj]r(j{)r}r(jXTo format the eMMC of the target board, Run the following application on the target board `USB_DevMsc_mmcsd `__ .jjjjrjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXTo format the eMMC of the target board, Run the following application on the target board `USB_DevMsc_mmcsd `__ .jjjjrjjj}r(j]j]j]j]j]ujM.j]r(jXZTo format the eMMC of the target board, Run the following application on the target board rr}r(jXZTo format the eMMC of the target board, Run the following application on the target board jjubj)r}r(jX.`USB_DevMsc_mmcsd `__j}r(UnameXUSB_DevMsc_mmcsdjXDevice_Drivers.html#id6j]j]j]j]j]ujjj]rjXUSB_DevMsc_mmcsdrr}r(jUjjubajjubjX .rr}r(jX .jjubeubaubj{)r}r(jX_To boot the target the eMMC should be bootable. Follow the steps same as SD card formatting as given at `Creating bootable SD card in windows `__ or `Creating bootable SD card in Linux `__ except instead of SD card, connect the target board eMMC to the host PC.jjjjrjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX_To boot the target the eMMC should be bootable. Follow the steps same as SD card formatting as given at `Creating bootable SD card in windows `__ or `Creating bootable SD card in Linux `__ except instead of SD card, connect the target board eMMC to the host PC.jjjjrjjj}r(j]j]j]j]j]ujM0j]r(jXhTo boot the target the eMMC should be bootable. Follow the steps same as SD card formatting as given at rr}r(jXhTo boot the target the eMMC should be bootable. Follow the steps same as SD card formatting as given at jjubj)r}r(jXW`Creating bootable SD card in windows `__j}r(UnameX$Creating bootable SD card in windowsjX,Overview.html#windows-sd-card-creation-guidej]j]j]j]j]ujjj]rjX$Creating bootable SD card in windowsrrÝ}rĝ(jUjjubajjubjX or rŝrƝ}rǝ(jX or jjubj)rȝ}rɝ(jXS`Creating bootable SD card in Linux `__j}rʝ(UnameX"Creating bootable SD card in LinuxjX*Overview.html#linux-sd-card-creation-guidej]j]j]j]j]ujjj]r˝jX"Creating bootable SD card in Linuxr̝r͝}rΝ(jUjjȝubajjubjXI except instead of SD card, connect the target board eMMC to the host PC.rϝrН}rѝ(jXI except instead of SD card, connect the target board eMMC to the host PC.jjubeubaubj{)rҝ}rӝ(jXmDelete the "MLO" and "app" in the bootable eMMC which are created in the process of making the eMMC bootable.jjjjrjjj}rԝ(j]j]j]j]j]ujNjhj]r՝j)r֝}rם(jXmDelete the "MLO" and "app" in the bootable eMMC which are created in the process of making the eMMC bootable.r؝jjҝjjrjjj}rٝ(j]j]j]j]j]ujM5j]rڝjXmDelete the "MLO" and "app" in the bootable eMMC which are created in the process of making the eMMC bootable.r۝rܝ}rݝ(jj؝jj֝ubaubaubj{)rޝ}rߝ(jX%Copy the sbl binary(MLO) to the eMMC.rjjjjrjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjޝjjrjjj}r(j]j]j]j]j]ujM7j]rjX%Copy the sbl binary(MLO) to the eMMC.rr}r(jjjjubaubaubj{)r}r(jXCopy the Application image(app) generated using the `Script `__ to the eMMC. jjjjrjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXCopy the Application image(app) generated using the `Script `__ to the eMMC.jjjjrjjj}r(j]j]j]j]j]ujM8j]r(jX4Copy the Application image(app) generated using the rr}r(jX4Copy the Application image(app) generated using the jjubj)r}r(jXD`Script `__j}r(UnameXScriptjX7Foundational_Components.html#application-image-creationj]j]j]j]j]ujjj]rjXScriptrr}r(jUjjubajjubjX to the eMMC.rr}r(jX to the eMMC.jjubeubaubeubeubj)r}r(jUjKjj`jjrjjj}r(j]rj,aj]j]j]rUid76raj]ujM=jhj]r(j)r}r(jXBooting the targetrjjjjrjjj}r (j]j]j]j]j]ujM=jhj]r jXBooting the targetr r }r (jjjjubaubj )r}r(jUjjjjrjj j}r(jU.j]j]j]jUj]j]jjujM?jhj]r(j{)r}r(jX`Set boot settings to eMMC by selecting J3, J4 and J6 jumpers on Pin 2 and 3 of AM572x EVM Board.jjjjrjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX`Set boot settings to eMMC by selecting J3, J4 and J6 jumpers on Pin 2 and 3 of AM572x EVM Board.rjjjjrjjj}r(j]j]j]j]j]ujM?j]rjX`Set boot settings to eMMC by selecting J3, J4 and J6 jumpers on Pin 2 and 3 of AM572x EVM Board.rr}r(jjjjubaubaubj{)r}r(jX8Ensure there is no SD card inserted in the SD card slot.r jjjjrjjj}r!(j]j]j]j]j]ujNjhj]r"j)r#}r$(jj jjjjrjjj}r%(j]j]j]j]j]ujMAj]r&jX8Ensure there is no SD card inserted in the SD card slot.r'r(}r)(jj jj#ubaubaubj{)r*}r+(jXkOpen a serial communication terminal like TeraTerm, MiniCom on host PC and connect to the UART console portjjjjrjjj}r,(j]j]j]j]j]ujNjhj]r-j)r.}r/(jXkOpen a serial communication terminal like TeraTerm, MiniCom on host PC and connect to the UART console portr0jj*jjrjjj}r1(j]j]j]j]j]ujMBj]r2jXkOpen a serial communication terminal like TeraTerm, MiniCom on host PC and connect to the UART console portr3r4}r5(jj0jj.ubaubaubj{)r6}r7(jXDDo a power reset of the board to boot the appliation from the eMMC. jjjjrjjj}r8(j]j]j]j]j]ujNjhj]r9j)r:}r;(jXCDo a power reset of the board to boot the appliation from the eMMC.r<jj6jjrjjj}r=(j]j]j]j]j]ujMDj]r>jXCDo a power reset of the board to boot the appliation from the eMMC.r?r@}rA(jj<jj:ubaubaubeubeubeubj)rB}rC(jUjKjjSjjrjjj}rD(j]rEj͍aj]j]j]rFUid77rGaj]ujMGjhj]rH(j)rI}rJ(jXBooting Via QSPIrKjjBjjrjjj}rL(j]j]j]j]j]ujMGjhj]rMjXBooting Via QSPIrNrO}rP(jjKjjIubaubj)rQ}rR(jX+Booting from QSPI flash involves two steps-rSjjBjjrjjj}rT(j]j]j]j]j]ujMHjhj]rUjX+Booting from QSPI flash involves two steps-rVrW}rX(jjSjjQubaubj )rY}rZ(jUjjBjjrjj j}r[(jU.j]j]j]jUj]j]jjujMJjhj]r\(j{)r]}r^(jX1Flashing bootloader and app image to QSPI flash.r_jjYjjrjjj}r`(j]j]j]j]j]ujNjhj]raj)rb}rc(jj_jj]jjrjjj}rd(j]j]j]j]j]ujMJj]rejX1Flashing bootloader and app image to QSPI flash.rfrg}rh(jj_jjbubaubaubj{)ri}rj(jXBooting the target. jjYjjrjjj}rk(j]j]j]j]j]ujNjhj]rlj)rm}rn(jXBooting the target.rojjijjrjjj}rp(j]j]j]j]j]ujMKj]rqjXBooting the target.rrrs}rt(jjojjmubaubaubeubj)ru}rv(jUjKjjBjjrjjj}rw(j]rxjaj]j]j]ryUid78rzaj]ujMNjhj]r{(j)r|}r}(jXPreparing Flash Devicer~jjujjrjjj}r(j]j]j]j]j]ujMNjhj]rjXPreparing Flash Devicerr}r(jj~jj|ubaubj)r}r(jXUse the CCS based qspi_flash_writer.out utility provided in <*TI_PDK_INSTALL_DIR>/packages/ti/boot/sbl/tools/flashwriter/qspi/'* to flash the SBL image at offset 0 and application image at offset 0x80000 to the QSPI device.jjujjrjjj}r(j]j]j]j]j]ujMPjhj]r(jX=Use the CCS based qspi_flash_writer.out utility provided in /packages/ti/boot/sbl/tools/flashwriter/qspi/'*j}r(j]j]j]j]j]ujjj]rjXHTI_PDK_INSTALL_DIR>/packages/ti/boot/sbl/tools/flashwriter/qspi/'rr}r(jUjjubajjUubjX` to flash the SBL image at offset 0 and application image at offset 0x80000 to the QSPI device.rr}r(jX` to flash the SBL image at offset 0 and application image at offset 0x80000 to the QSPI device.jjubeubj)r}r(jXQSPI device Memory Map:rjjujjrjjj}r(j]j]j]j]j]ujMUjhj]rjXQSPI device Memory Map:rr}r(jjjjubaubjy )r}r(jUjjujjrjj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujjj]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX Offset 0x00rjjjjrjjj}r(j]j]j]j]j]ujMXj]rjX Offset 0x00rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]ržj)rÞ}rĞ(jXSBLrŞjjjjrjjj}rƞ(j]j]j]j]j]ujMXj]rǞjXSBLrȞrɞ}rʞ(jjŞjjÞubaubajj ubejj ubj )r˞}r̞(jUj}r͞(j]j]j]j]j]ujjj]rΞ(j )rϞ}rО(jUj}rў(j]j]j]j]j]ujj˞j]rҞj)rӞ}rԞ(jXOffset 0x80000r՞jjϞjjrjjj}r֞(j]j]j]j]j]ujMZj]rמjXOffset 0x80000r؞rٞ}rڞ(jj՞jjӞubaubajj ubj )r۞}rܞ(jUj}rݞ(j]j]j]j]j]ujj˞j]rޞj)rߞ}r(jXApplication Multicore Imagerjj۞jjrjjj}r(j]j]j]j]j]ujMZj]rjXApplication Multicore Imagerr}r(jjjjߞubaubajj ubejj ubejj ubejj ubaubj)r}r(jXIThe images can be flashed into QSPI flash by following steps given below.rjjujjrjjj}r(j]j]j]j]j]ujM]jhj]rjXIThe images can be flashed into QSPI flash by following steps given below.rr}r(jjjjubaubj )r}r(jUjjujjrjj j}r(jU.j]j]j]jUj]j]jjujM`jhj]r(j{)r}r(jXCopy QSPI mode SBL image */packages/ti/boot/sbl/binary//qspi/bin/MLO* and application image(app) generated using the Script into the SD card. Rename the bootloader file to 'boot' and application image to 'app' with no extensions.jjjjrjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXCopy QSPI mode SBL image */packages/ti/boot/sbl/binary//qspi/bin/MLO* and application image(app) generated using the Script into the SD card. Rename the bootloader file to 'boot' and application image to 'app' with no extensions.jjjjrjjj}r(j]j]j]j]j]ujM`j]r(jXCopy QSPI mode SBL image rr}r(jXCopy QSPI mode SBL image jjubjM)r}r(jXK*/packages/ti/boot/sbl/binary//qspi/bin/MLO*j}r(j]j]j]j]j]ujjj]rjXI/packages/ti/boot/sbl/binary//qspi/bin/MLOrr}r(jUjjubajjUubjX and application image(app) generated using the Script into the SD card. Rename the bootloader file to 'boot' and application image to 'app' with no extensions.rr}r(jX and application image(app) generated using the Script into the SD card. Rename the bootloader file to 'boot' and application image to 'app' with no extensions.jjubeubaubj{)r}r (jXCopy 'config' file into the SD card, the config file should contain names of the image to be flashed and the offset. A sample config file can be found at */packages/ti/boot/sbl/tools/flashWriter/qspi/config*. Do not change the name of the config file. **NOTE:** "config" file can be used without any modifications if bootloader and application images are renamed to "boot" and "app". **NOTE:** Do not rename the bootloader to be copied to SD card as "MLO", as MMCSD bootloader expects "MLO" and "app" to boot.jjjjrjjj}r (j]j]j]j]j]ujNjhj]r j)r }r (jXCopy 'config' file into the SD card, the config file should contain names of the image to be flashed and the offset. A sample config file can be found at */packages/ti/boot/sbl/tools/flashWriter/qspi/config*. Do not change the name of the config file. **NOTE:** "config" file can be used without any modifications if bootloader and application images are renamed to "boot" and "app". **NOTE:** Do not rename the bootloader to be copied to SD card as "MLO", as MMCSD bootloader expects "MLO" and "app" to boot.jjjjrjjj}r(j]j]j]j]j]ujMfj]r(jXCopy 'config' file into the SD card, the config file should contain names of the image to be flashed and the offset. A sample config file can be found at rr}r(jXCopy 'config' file into the SD card, the config file should contain names of the image to be flashed and the offset. A sample config file can be found at jj ubjM)r}r(jXI*/packages/ti/boot/sbl/tools/flashWriter/qspi/config*j}r(j]j]j]j]j]ujj j]rjXG/packages/ti/boot/sbl/tools/flashWriter/qspi/configrr}r(jUjjubajjUubjX-. Do not change the name of the config file. rr}r(jX-. Do not change the name of the config file. jj ubj)r}r(jX **NOTE:**j}r(j]j]j]j]j]ujj j]r jXNOTE:r!r"}r#(jUjjubajjubjX{ "config" file can be used without any modifications if bootloader and application images are renamed to "boot" and "app". r$r%}r&(jX{ "config" file can be used without any modifications if bootloader and application images are renamed to "boot" and "app". jj ubj)r'}r((jX **NOTE:**j}r)(j]j]j]j]j]ujj j]r*jXNOTE:r+r,}r-(jUjj'ubajjubjXt Do not rename the bootloader to be copied to SD card as "MLO", as MMCSD bootloader expects "MLO" and "app" to boot.r.r/}r0(jXt Do not rename the bootloader to be copied to SD card as "MLO", as MMCSD bootloader expects "MLO" and "app" to boot.jj ubeubaubj{)r1}r2(jXNow SD card contains 3 files 1)boot 2)app 3)config files. config file contains the address of boot image as 0x0 and app image as 0x80000. Insert it into the SD card slot.jjjjrjjj}r3(j]j]j]j]j]ujNjhj]r4j)r5}r6(jXNow SD card contains 3 files 1)boot 2)app 3)config files. config file contains the address of boot image as 0x0 and app image as 0x80000. Insert it into the SD card slot.r7jj1jjrjjj}r8(j]j]j]j]j]ujMoj]r9jXNow SD card contains 3 files 1)boot 2)app 3)config files. config file contains the address of boot image as 0x0 and app image as 0x80000. Insert it into the SD card slot.r:r;}r<(jj7jj5ubaubaubj{)r=}r>(jXConnect the board with CCS and and load the prebuilt qspi flash writer application from /packages/ti/boot/sbl/tools/flashWriter/qspi/bin/jjjjrjjj}r?(j]j]j]j]j]ujNjhj]r@j)rA}rB(jXConnect the board with CCS and and load the prebuilt qspi flash writer application from /packages/ti/boot/sbl/tools/flashWriter/qspi/bin/rCjj=jjrjjj}rD(j]j]j]j]j]ujMsj]rEjXConnect the board with CCS and and load the prebuilt qspi flash writer application from /packages/ti/boot/sbl/tools/flashWriter/qspi/bin/rFrG}rH(jjCjjAubaubaubj{)rI}rJ(jXaRun the QSPI flash writer application. You will see the following logs on the EVM's UART console.jjjjrjjj}rK(j]j]j]j]j]ujNjhj]rLj)rM}rN(jXaRun the QSPI flash writer application. You will see the following logs on the EVM's UART console.rOjjIjjrjjj}rP(j]j]j]j]j]ujMvj]rQjXaRun the QSPI flash writer application. You will see the following logs on the EVM's UART console.rRrS}rT(jjOjjMubaubaubj{)rU}rV(jX}After the images have been flashed to the QSPI device disconnect from CCS and do a power reset to boot from the QSPI memory. jjjjrjjj}rW(j]j]j]j]j]ujNjhj]rXj)rY}rZ(jX|After the images have been flashed to the QSPI device disconnect from CCS and do a power reset to boot from the QSPI memory.r[jjUjjrjjj}r\(j]j]j]j]j]ujMxj]r]jX|After the images have been flashed to the QSPI device disconnect from CCS and do a power reset to boot from the QSPI memory.r^r_}r`(jj[jjYubaubaubeubj)ra}rb(jXPDK QSPI Flash Writer!! Copying boot to QSPI Flash Copying app to QSPI Flash Changing read to quad mode Read mode has been changed to Quad mode SUCCESS!!! Flashing completedjjujjrjjj}rc(j@jAj]j]j]j]j]ujMb$jhj]rdjXPDK QSPI Flash Writer!! Copying boot to QSPI Flash Copying app to QSPI Flash Changing read to quad mode Read mode has been changed to Quad mode SUCCESS!!! Flashing completedrerf}rg(jUjjaubaubj)rh}ri(jXq- The file names have to be renamed in such a way that the length of name is less than 9 characters. Any file name less than 9 characters can be used. - This application will flash the image at required offset without taking into consideration any overwriting to previously flashed image. - It is the responsibility of the user to provide proper offsets.jjujNjjj}rj(j]j]j]j]j]ujNjhj]rkjt)rl}rm(jUj}rn(jyX-j]j]j]j]j]ujjhj]ro(j{)rp}rq(jXThe file names have to be renamed in such a way that the length of name is less than 9 characters. Any file name less than 9 characters can be used.j}rr(j]j]j]j]j]ujjlj]rsj)rt}ru(jXThe file names have to be renamed in such a way that the length of name is less than 9 characters. Any file name less than 9 characters can be used.rvjjpjjrjjj}rw(j]j]j]j]j]ujMj]rxjXThe file names have to be renamed in such a way that the length of name is less than 9 characters. Any file name less than 9 characters can be used.ryrz}r{(jjvjjtubaubajjubj{)r|}r}(jXThis application will flash the image at required offset without taking into consideration any overwriting to previously flashed image.j}r~(j]j]j]j]j]ujjlj]rj)r}r(jXThis application will flash the image at required offset without taking into consideration any overwriting to previously flashed image.rjj|jjrjjj}r(j]j]j]j]j]ujMj]rjXThis application will flash the image at required offset without taking into consideration any overwriting to previously flashed image.rr}r(jjjjubaubajjubj{)r}r(jX?It is the responsibility of the user to provide proper offsets.rj}r(j]j]j]j]j]ujjlj]rj)r}r(jjjjjjrjjj}r(j]j]j]j]j]ujMj]rjX?It is the responsibility of the user to provide proper offsets.rr}r(jjjjubaubajjubejjwubaubeubeubeubj)r}r(jUjKjj`jjrjjj}r(j]rjaj]j]j]rUid79raj]ujMjhj]r(j)r}r(jXTest Applicationrjjjjrjjj}r(j]j]j]j]j]ujMjhj]rjXTest Applicationrr}r(jjjjubaubj)r}r(jXSBL provides a test application to demonstrate booting of multicore application image on A15 and DSP cores.The multicore sample application uses mailbox for inter-processor communication. It is used to validate the multi-core boot-up use case.rjjjjrjjj}r(j]j]j]j]j]ujMjhj]rjXSBL provides a test application to demonstrate booting of multicore application image on A15 and DSP cores.The multicore sample application uses mailbox for inter-processor communication. It is used to validate the multi-core boot-up use case.rr}r(jjjjubaubj)r}r(jXMaster application sends wake-up message to the DSP slave cores & waits for acknowledgement message from the slave cores in an infinite loop.Each slave DSP core waits for wake-up message from the master core responds back with an acknowledgement message.rjjjjrjjj}r(j]j]j]j]j]ujMjhj]rjXMaster application sends wake-up message to the DSP slave cores & waits for acknowledgement message from the slave cores in an infinite loop.Each slave DSP core waits for wake-up message from the master core responds back with an acknowledgement message.rr}r(jjjjubaubj)r}r(jUjjjjrjjj}r(j]j]j]j]rUapplication-image-creationraj]rhaujMjhj]r(j)r}r(jXApplication Image Creationrjjjjrjjj}r(j]j]j]j]j]ujMjhj]rjXApplication Image Creationrr}r(jjjjubaubj)rŸ}rß(jX.Application Image creation involves two steps.rğjjjjrjjj}rş(j]j]j]j]j]ujMjhj]rƟjX.Application Image creation involves two steps.rǟrȟ}rɟ(jjğjjŸubaubj )rʟ}r˟(jUjjjjrjj j}r̟(jU.j]j]j]jUj]j]jjujMjhj]r͟(j{)rΟ}rϟ(jX9Generating the .outs of applications for individual coresrПjjʟjjrjjj}rџ(j]j]j]j]j]ujNjhj]rҟj)rӟ}rԟ(jjПjjΟjjrjjj}r՟(j]j]j]j]j]ujMj]r֟jX9Generating the .outs of applications for individual coresrןr؟}rٟ(jjПjjӟubaubaubj{)rڟ}r۟(jXMCombining the .outs of individual cores to create a bootable multicore image jjʟjjrjjj}rܟ(j]j]j]j]j]ujNjhj]rݟj)rޟ}rߟ(jXLCombining the .outs of individual cores to create a bootable multicore imagerjjڟjjrjjj}r(j]j]j]j]j]ujMj]rjXLCombining the .outs of individual cores to create a bootable multicore imagerr}r(jjjjޟubaubaubeubj)r}r(jXYThe steps to create the bootable image in Linux and Windows environment are listed below.rjjjjrjjj}r(j]j]j]j]j]ujMjhj]rjXYThe steps to create the bootable image in Linux and Windows environment are listed below.rr}r(jjjjubaubj)r}r(jXa- Valid SOC settings are AM571x/AM572x - Valid BOARD settings are evmAM572x/idkAM571x/idkAM572xjjjNjjj}r(j]j]j]j]j]ujNjhj]rjt)r}r(jUj}r(jyX-j]j]j]j]j]ujjj]r(j{)r}r(jX$Valid SOC settings are AM571x/AM572xrj}r(j]j]j]j]j]ujjj]rj)r}r(jjjjjjrjjj}r(j]j]j]j]j]ujMj]rjX$Valid SOC settings are AM571x/AM572xrr}r(jjjjubaubajjubj{)r}r(jX6Valid BOARD settings are evmAM572x/idkAM571x/idkAM572xrj}r(j]j]j]j]j]ujjj]rj)r}r(jjjjjjrjjj}r (j]j]j]j]j]ujMj]r jX6Valid BOARD settings are evmAM572x/idkAM571x/idkAM572xr r }r (jjjjubaubajjubejjwubaubeubj)r}r(jUjjjjrjjj}r(j]j]j]j]rUlinux-environmentraj]rhaujMjhj]r(j)r}r(jXLinux Environmentrjjjjrjjj}r(j]j]j]j]j]ujMjhj]rjXLinux Environmentrr}r(jjjjubaubj)r}r(jX&Command to build the test application.rjjjjrjjj}r (j]j]j]j]j]ujMjhj]r!jX&Command to build the test application.r"r#}r$(jjjjubaubj)r%}r&(jXGo to cd (TI_PDK_INSTALL_DIR)\packages\ti\boot\sbl make example BOARD= SOC= to build the application make example_clean BOARD=jjjjrjjj}r'(j@jAj]j]j]j]j]ujM$jhj]r(jXGo to cd (TI_PDK_INSTALL_DIR)\packages\ti\boot\sbl make example BOARD= SOC= to build the application make example_clean BOARD=r)r*}r+(jUjj%ubaubj)r,}r-(jXExample:r.jjjjrjjj}r/(j]j]j]j]j]ujMjhj]r0jXExample:r1r2}r3(jj.jj,ubaubj)r4}r5(jX'make example BOARD=idkAM572x SOC=AM572xjjjjrjjj}r6(j@jAj]j]j]j]j]ujM$jhj]r7jX'make example BOARD=idkAM572x SOC=AM572xr8r9}r:(jUjj4ubaubj)r;}r<(jXbTo create the final bootable application image use the AM57xImageGen script and follow these stepsr=jjjjrjjj}r>(j]j]j]j]j]ujMjhj]r?jXbTo create the final bootable application image use the AM57xImageGen script and follow these stepsr@rA}rB(jj=jj;ubaubj)rC}rD(jX1. Set the following environment variable in the shell.  BIN_PATH: Pointing to the path where the AppImage needs to be generatedrEjjjjrjjj}rF(j]j]j]j]j]ujMjhj]rGjX1. Set the following environment variable in the shell.  BIN_PATH: Pointing to the path where the AppImage needs to be generatedrHrI}rJ(jjEjjCubaubj)rK}rL(jXEEx: export BIN_PATH=$(TI_PDK_INSTALL_DIR)/packages/ti/boot/sbl/binaryjjjjrjjj}rM(j@jAj]j]j]j]j]ujM$jhj]rNjXEEx: export BIN_PATH=$(TI_PDK_INSTALL_DIR)/packages/ti/boot/sbl/binaryrOrP}rQ(jUjjKubaubj)rR}rS(jXi2. Edit the script file to point to the application elf files by setting the input application variables.rTjjjjrjjj}rU(j]j]j]j]j]ujMjhj]rVjXi2. Edit the script file to point to the application elf files by setting the input application variables.rWrX}rY(jjTjjRubaubj)rZ}r[(jXApp_MPU_CPU0: Point to the path where the application .out for A15 MPU is located App_DSP1: Point to the path where the dsp core 1 application is located App_DSP2: Point to the path where the dsp core 2 application is locatedr\jjjjrjjj}r](j]j]j]j]j]ujMjhj]r^jXApp_MPU_CPU0: Point to the path where the application .out for A15 MPU is located App_DSP1: Point to the path where the dsp core 1 application is located App_DSP2: Point to the path where the dsp core 2 application is locatedr_r`}ra(jj\jjZubaubj)rb}rc(jX2export APP_MPU_CPU0=$(TI_PDK_INSTALL_DIR)/packages/ti/boot/sbl/binary/idkAM572x/example/armv7/bin/sbl_app.out export APP_DSP1=$(TI_PDK_INSTALL_DIR)/packages/ti/boot/sbl/binary/idkAM572x/example/c66/dsp1/bin/sbl_app.xe66 export APP_DSP2=$(TI_PDK_INSTALL_DIR)/packages/ti/boot/sbl/binary/idkAM572x/example/c66/dsp2/bin/sbl_app.xe663 export APP_IPU1_CPU0=$(TI_PDK_INSTALL_DIR)/packages/ti/boot/sbl/binary/idkAM572x/example/m4/ipu1/bin/sbl_app.xem4 export APP_IPU1_CPU0=$(TI_PDK_INSTALL_DIR)/packages/ti/boot/sbl/binary/idkAM572x/example/m4/ipu2/bin/sbl_app.xem4jjjjrjjj}rd(j@jAj]j]j]j]j]ujM$jhj]rejX2export APP_MPU_CPU0=$(TI_PDK_INSTALL_DIR)/packages/ti/boot/sbl/binary/idkAM572x/example/armv7/bin/sbl_app.out export APP_DSP1=$(TI_PDK_INSTALL_DIR)/packages/ti/boot/sbl/binary/idkAM572x/example/c66/dsp1/bin/sbl_app.xe66 export APP_DSP2=$(TI_PDK_INSTALL_DIR)/packages/ti/boot/sbl/binary/idkAM572x/example/c66/dsp2/bin/sbl_app.xe663 export APP_IPU1_CPU0=$(TI_PDK_INSTALL_DIR)/packages/ti/boot/sbl/binary/idkAM572x/example/m4/ipu1/bin/sbl_app.xem4 export APP_IPU1_CPU0=$(TI_PDK_INSTALL_DIR)/packages/ti/boot/sbl/binary/idkAM572x/example/m4/ipu2/bin/sbl_app.xem4rfrg}rh(jUjjbubaubj)ri}rj(jXZ3. If it is not required to load an application on specific core leave the variable blank.rkjjjjrjjj}rl(j]j]j]j]j]ujMjhj]rmjXZ3. If it is not required to load an application on specific core leave the variable blank.rnro}rp(jjkjjiubaubj )rq}rr(jUjjjjrjj j}rs(jU.jO3Kj]j]j]jUj]j]jjujMjhj]rtj{)ru}rv(jXpRun the script file AM57xImageGen found under the path $(TI_PDK_INSTALL_DIR)/packages/ti/boot/sbl/tools/scripts jjqjjrjjj}rw(j]j]j]j]j]ujNjhj]rxj)ry}rz(jXoRun the script file AM57xImageGen found under the path $(TI_PDK_INSTALL_DIR)/packages/ti/boot/sbl/tools/scriptsr{jjujjrjjj}r|(j]j]j]j]j]ujMj]r}jXoRun the script file AM57xImageGen found under the path $(TI_PDK_INSTALL_DIR)/packages/ti/boot/sbl/tools/scriptsr~r}r(jj{jjyubaubaubaubj)r}r(jXW5. An application image by name app is created in the path pointed by BIN_PATH variablerjjjjrjjj}r(j]j]j]j]j]ujMjhj]rjXW5. An application image by name app is created in the path pointed by BIN_PATH variablerr}r(jjjjubaubj)r}r(jXd6. Copy the Bootlaoder image(MLO) and application(app) in the SD card to boot using MMCSD boot mode.rjjjjrjjj}r(j]j]j]j]j]ujMjhj]rjXd6. Copy the Bootlaoder image(MLO) and application(app) in the SD card to boot using MMCSD boot mode.rr}r(jjjjubaubj)r}r(jX- The AM57xImageGen.sh script depends on tools like mono to execute the out2rprc.exe. - The linux host environment needs to have this tool installed to execute this script. - Refer this link to download the `mono `__ tooljjjNjjj}r(j]j]j]j]j]ujNjhj]rjt)r}r(jUj}r(jyX-j]j]j]j]j]ujjj]r(j{)r}r(jXSThe AM57xImageGen.sh script depends on tools like mono to execute the out2rprc.exe.j}r(j]j]j]j]j]ujjj]rj)r}r(jXSThe AM57xImageGen.sh script depends on tools like mono to execute the out2rprc.exe.rjjjjrjjj}r(j]j]j]j]j]ujMj]rjXSThe AM57xImageGen.sh script depends on tools like mono to execute the out2rprc.exe.rr}r(jjjjubaubajjubj{)r}r(jXTThe linux host environment needs to have this tool installed to execute this script.j}r(j]j]j]j]j]ujjj]rj)r}r(jXTThe linux host environment needs to have this tool installed to execute this script.rjjjjrjjj}r(j]j]j]j]j]ujMj]rjXTThe linux host environment needs to have this tool installed to execute this script.rr}r(jjjjubaubajjubj{)r}r(jXKRefer this link to download the `mono `__ toolj}r(j]j]j]j]j]ujjj]rj)r}r(jXKRefer this link to download the `mono `__ tooljjjjrjjj}r(j]j]j]j]j]ujMj]r(jX Refer this link to download the rr}r(jX Refer this link to download the jjubj)r}r(jX&`mono `__j}r(UnameXmonojXhttp://www.mono-project.comj]j]j]j]j]ujjj]rjXmonorr}r (jUjjubajjubjX toolràrĠ}rŠ(jX tooljjubeubajjubejjwubaubeubj)rƠ}rǠ(jUjjjjrjjj}rȠ(j]j]j]j]rɠUwindows-environmentrʠaj]rˠhaaujMjhj]r̠(j)r͠}rΠ(jXWindows environmentrϠjjƠjjrjjj}rР(j]j]j]j]j]ujMjhj]rѠjXWindows environmentrҠrӠ}rԠ(jjϠjj͠ubaubj)rՠ}r֠(jX&Command to build the test application.rנjjƠjjrjjj}rؠ(j]j]j]j]j]ujMjhj]r٠jX&Command to build the test application.rڠr۠}rܠ(jjנjjՠubaubj)rݠ}rޠ(jXGo to cd (TI_PDK_INSTALL_DIR)\packages\ti\boot\sbl gmake example BOARD= SOC= to build the application gmake example_clean BOARD=jjƠjjrjjj}rߠ(j@jAj]j]j]j]j]ujM$jhj]rjXGo to cd (TI_PDK_INSTALL_DIR)\packages\ti\boot\sbl gmake example BOARD= SOC= to build the application gmake example_clean BOARD=rr}r(jUjjݠubaubj)r}r(jXExample:rjjƠjjrjjj}r(j]j]j]j]j]ujMjhj]rjXExample:rr}r(jjjjubaubj)r}r(jX(gmake example BOARD=idkAM572x SOC=AM572xjjƠjjrjjj}r(j@jAj]j]j]j]j]ujM$jhj]rjX(gmake example BOARD=idkAM572x SOC=AM572xrr}r(jUjjubaubj)r}r(jXbTo create the final bootable application image use the AM57xImageGen script and follow these stepsrjjƠjjrjjj}r(j]j]j]j]j]ujMjhj]rjXbTo create the final bootable application image use the AM57xImageGen script and follow these stepsrr}r(jjjjubaubj )r}r(jUjjƠjjrjj j}r(jU.j]j]j]jUj]j]jjujMjhj]rj{)r}r(jXASet the following environment variable in windows command prompt jjjjrjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX@Set the following environment variable in windows command promptrjjjjrjjj}r(j]j]j]j]j]ujMj]rjX@Set the following environment variable in windows command promptrr }r (jjjjubaubaubaubj)r }r (jXGBIN_PATH: Pointing to the path where the AppImage needs to be generatedr jjƠjjrjjj}r(j]j]j]j]j]ujMjhj]rjXGBIN_PATH: Pointing to the path where the AppImage needs to be generatedrr}r(jj jj ubaubj)r}r(jXBEx: set BIN_PATH=%TI_PDK_INSTALL_DIR%\packages\ti\boot\sbl\binaryjjƠjjrjjj}r(j@jAj]j]j]j]j]ujM$jhj]rjXBEx: set BIN_PATH=%TI_PDK_INSTALL_DIR%\packages\ti\boot\sbl\binaryrr}r(jUjjubaubj)r}r(jXh2. Edit the batch file to point to the application elf files by setting the input application variables.rjjƠjjrjjj}r(j]j]j]j]j]ujM jhj]rjXh2. Edit the batch file to point to the application elf files by setting the input application variables.rr }r!(jjjjubaubj)r"}r#(jXApp_MPU_CPU0: Point to the path where the application .out for A15 MPU is located App_DSP1: Point to the path where the dsp core 1 application is located App_DSP2: Point to the path where the dsp core 2 application is locatedr$jjƠjjrjjj}r%(j]j]j]j]j]ujMjhj]r&jXApp_MPU_CPU0: Point to the path where the application .out for A15 MPU is located App_DSP1: Point to the path where the dsp core 1 application is located App_DSP2: Point to the path where the dsp core 2 application is locatedr'r(}r)(jj$jj"ubaubj)r*}r+(jXset App_MPU_CPU0=%TI_PDK_INSTALL_DIR%\packages\ti\boot\sbl\binary\idkAM572x\example\armv7\bin\sbl_app.out set App_DSP1=%TI_PDK_INSTALL_DIR%\packages\ti\boot\sbl\binary\idkAM572x\example\c66\dsp1\bin\sbl_app.xe66 set App_DSP2=%TI_PDK_INSTALL_DIR%\packages\ti\boot\sbl\binary\idkAM572x\example\c66\dsp2\bin\sbl_app.xe66 set App_IPU1_CPU0=%TI_PDK_INSTALL_DIR%\packages\ti\boot\sbl\binary\idkAM572x\example\m4\ipu1\bin\sbl_app.xem4 set App_IPU2_CPU0=%TI_PDK_INSTALL_DIR%\packages\ti\boot\sbl\binary\idkAM572x\example\m4\ipu2\bin\sbl_app.xem4jjƠjjrjjj}r,(j@jAj]j]j]j]j]ujM$jhj]r-jXset App_MPU_CPU0=%TI_PDK_INSTALL_DIR%\packages\ti\boot\sbl\binary\idkAM572x\example\armv7\bin\sbl_app.out set App_DSP1=%TI_PDK_INSTALL_DIR%\packages\ti\boot\sbl\binary\idkAM572x\example\c66\dsp1\bin\sbl_app.xe66 set App_DSP2=%TI_PDK_INSTALL_DIR%\packages\ti\boot\sbl\binary\idkAM572x\example\c66\dsp2\bin\sbl_app.xe66 set App_IPU1_CPU0=%TI_PDK_INSTALL_DIR%\packages\ti\boot\sbl\binary\idkAM572x\example\m4\ipu1\bin\sbl_app.xem4 set App_IPU2_CPU0=%TI_PDK_INSTALL_DIR%\packages\ti\boot\sbl\binary\idkAM572x\example\m4\ipu2\bin\sbl_app.xem4r.r/}r0(jUjj*ubaubj)r1}r2(jXZ3. If it is not required to load an application on specific core leave the variable blank.r3jjƠjjrjjj}r4(j]j]j]j]j]ujMjhj]r5jXZ3. If it is not required to load an application on specific core leave the variable blank.r6r7}r8(jj3jj1ubaubj )r9}r:(jUjjƠjjrjj j}r;(jU.jO3Kj]j]j]jUj]j]jjujM!jhj]r<j{)r=}r>(jXoRun the batch file AM57xImageGen found under the path $(TI_PDK_INSTALL_DIR)/packages/ti/boot/sbl/tools/scripts jj9jjrjjj}r?(j]j]j]j]j]ujNjhj]r@j)rA}rB(jXnRun the batch file AM57xImageGen found under the path $(TI_PDK_INSTALL_DIR)/packages/ti/boot/sbl/tools/scriptsrCjj=jjrjjj}rD(j]j]j]j]j]ujM!j]rEjXnRun the batch file AM57xImageGen found under the path $(TI_PDK_INSTALL_DIR)/packages/ti/boot/sbl/tools/scriptsrFrG}rH(jjCjjAubaubaubaubj)rI}rJ(jX5. Follow the steps 4 to 6 listed above for Linux environment. | Setup Requirements """""""""""""""""""" For information on board specific requirements like power supply, UART console port connections refer the Hardware User guide of the respective boards.rKjjƠjjrjjj}rL(j]j]j]j]j]ujM#jhj]rMjX5. Follow the steps 4 to 6 listed above for Linux environment. | Setup Requirements """""""""""""""""""" For information on board specific requirements like power supply, UART console port connections refer the Hardware User guide of the respective boards.rNrO}rP(jjKjjIubaubj)rQ}rR(jXThe configurations needed to setup UART console through a serial terminal application on host PC are listed in the next section.rSjjƠjjrjjj}rT(j]j]j]j]j]ujM+jhj]rUjXThe configurations needed to setup UART console through a serial terminal application on host PC are listed in the next section.rVrW}rX(jjSjjQubaubj)rY}rZ(jUjjƠjjrjjj}r[(j]j]j]j]r\Uuart-console-setupr]aj]r^jaujM/jhj]r_(j)r`}ra(jXUART Console SetuprbjjYjjrjjj}rc(j]j]j]j]j]ujM/jhj]rdjXUART Console Setuprerf}rg(jjbjj`ubaubj)rh}ri(jXPDK SBL prints messages on the UART Serial Console running on the host. Hence, a serial terminal application (like Tera Term/HyperTerminal/minicom) should be running on the host.rjjjYjjrjjj}rk(j]j]j]j]j]ujM0jhj]rljXPDK SBL prints messages on the UART Serial Console running on the host. Hence, a serial terminal application (like Tera Term/HyperTerminal/minicom) should be running on the host.rmrn}ro(jjjjjhubaubj)rp}rq(jXThe host serial port must be configured at 115200 baud, no parity, 1 stop bit and no flow control. Please ensure that the local echo setting for the terminal is turned off.rrjjYjjrjjj}rs(j]j]j]j]j]ujM4jhj]rtjXThe host serial port must be configured at 115200 baud, no parity, 1 stop bit and no flow control. Please ensure that the local echo setting for the terminal is turned off.rurv}rw(jjrjjpubaubeubj)rx}ry(jUjjƠjjrjjj}rz(j]j]j]j]r{Uloading-the-test-applicationr|aj]r}haujM9jhj]r~(j)r}r(jXLoading the test applicationrjjxjjrjjj}r(j]j]j]j]j]ujM9jhj]rjXLoading the test applicationrr}r(jjjjubaubj)r}r(jXMFollow these steps to load the test application using a SD card on the targetrjjxjjrjjj}r(j]j]j]j]j]ujM:jhj]rjXMFollow these steps to load the test application using a SD card on the targetrr}r(jjjjubaubj)r}r(jXjcopy the MLO to your SD card (located at $(TI_PDK_INSTALL_DIR)/packages/ti/boot/sbl/binary/[BOARD]/mmcsd)rjjxjjrjjj}r(j]j]j]j]j]ujM=jhj]rjXjcopy the MLO to your SD card (located at $(TI_PDK_INSTALL_DIR)/packages/ti/boot/sbl/binary/[BOARD]/mmcsd)rr}r(jjjjubaubj )r}r(jUjjxjjrjj j}r(jU.j]j]j]jUj]j]jjujM@jhj]r(j{)r}r(jXKcopy the example app located at path pointed to by BIN_PATH to your SD cardjjjjrjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXKcopy the example app located at path pointed to by BIN_PATH to your SD cardrjjjjrjjj}r(j]j]j]j]j]ujM@j]rjXKcopy the example app located at path pointed to by BIN_PATH to your SD cardrr}r(jjjjubaubaubj{)r}r(jX;insert your SD card into your board and power on your boardrjjjjrjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjrjjj}r(j]j]j]j]j]ujMBj]rjX;insert your SD card into your board and power on your boardrr}r(jjjjubaubaubj{)r}r(jX4open teraterm to connect to the board's UART consolerjjjjrjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjrjjj}r(j]j]j]j]j]ujMCj]rjX4open teraterm to connect to the board's UART consolerr}r(jjjjubaubaubj{)r}r(jX,press the "Hard Reset" button on your board jjjjrjjj}r(j]j]j]j]j]ujNjhj]r¡j)rá}rġ(jX+press the "Hard Reset" button on your boardršjjjjrjjj}rơ(j]j]j]j]j]ujMDj]rǡjX+press the "Hard Reset" button on your boardrȡrɡ}rʡ(jjšjjáubaubaubeubj)rˡ}r̡(jXdOn Successful bootup you should see the following logs on the UART console for a AM572x based board.r͡jjxjjrjjj}rΡ(j]j]j]j]j]ujMFjhj]rϡjXdOn Successful bootup you should see the following logs on the UART console for a AM572x based board.rСrѡ}rҡ(jj͡jjˡubaubjR)rӡ}rԡ(jX%.. Image:: ../images/Sbl_example.jpg jjxjjrjjZj}rա(UuriXrtos/../images/Sbl_example.jpgr֡j]j]j]j]jX}rסU*j֡sj]ujMJjhj]ubj)rء}r١(jX MPU Core 0 example does a sequential check of mailbox messages sent from the other cores. On rare occasions, the check happens before the message is sent - the " boot-up Successful" message might not be displayed even though the core(s) were booted successfully.jjxjjrjjj}rڡ(j]j]j]j]j]ujNjhj]rۡj)rܡ}rݡ(jX MPU Core 0 example does a sequential check of mailbox messages sent from the other cores. On rare occasions, the check happens before the message is sent - the " boot-up Successful" message might not be displayed even though the core(s) were booted successfully.rޡjjءjjrjjj}rߡ(j]j]j]j]j]ujMLj]rjX MPU Core 0 example does a sequential check of mailbox messages sent from the other cores. On rare occasions, the check happens before the message is sent - the " boot-up Successful" message might not be displayed even though the core(s) were booted successfully.rr}r(jjޡjjܡubaubaubeubeubeubj)r}r(jUjj`jjrjjj}r(j]j]j]j]rUapplication-integrationraj]rhaujMRjhj]r(j)r}r(jXApplication Integrationrjjjjrjjj}r(j]j]j]j]j]ujMRjhj]rjXApplication Integrationrr}r(jjjjubaubj)r}r(jUjKjjjjrjjj}r(j]rX memory mapraj]j]j]rU memory-mapraj]ujMUjhj]r(j)r}r(jX Memory Maprjjjjrjjj}r(j]j]j]j]j]ujMUjhj]rjX Memory Maprr}r(jjjjubaubj)r}r(jXTable indicated below provides memory map details for SBL image in OCMC_RAM1.  For more details on pinmux and IO delay requirements refer this link `Processor SDK Board Support `__jjjjrjjj}r(j]j]j]j]j]ujMWjhj]r(jXTable indicated below provides memory map details for SBL image in OCMC_RAM1.  For more details on pinmux and IO delay requirements refer this link rr}r (jXTable indicated below provides memory map details for SBL image in OCMC_RAM1.  For more details on pinmux and IO delay requirements refer this link jjubj)r }r (jX@`Processor SDK Board Support `__j}r (UnameXProcessor SDK Board SupportjXindex_board.html#board-supportj]j]j]j]j]ujjj]r jXProcessor SDK Board Supportrr}r(jUjj ubajjubeubj)r}r(jXWe recommend that users should refer to the linker command file and the map file for the boot loader to check for latest information on the memory utilization in the boot loader.rjjjjrjjj}r(j]j]j]j]j]ujM\jhj]rjXWe recommend that users should refer to the linker command file and the map file for the boot loader to check for latest information on the memory utilization in the boot loader.rr}r(jjjjubaubj)r}r(jX`**Location of linker command file**: /packages/ti/boot/sbl/board//buildjjjjrjjj}r(j]j]j]j]j]ujM`jhj]r(j)r}r(jX#**Location of linker command file**j}r(j]j]j]j]j]ujjj]r jXLocation of linker command filer!r"}r#(jUjjubajjubjX=: /packages/ti/boot/sbl/board//buildr$r%}r&(jX=: /packages/ti/boot/sbl/board//buildjjubeubj)r'}r((jX!The SBL memory map is shown belowr)jjjjrjjj}r*(j]j]j]j]j]ujMcjhj]r+jX!The SBL memory map is shown belowr,r-}r.(jj)jj'ubaubjR)r/}r0(jX(.. Image:: ../images/SBL_memory_map.png jjjjrjjZj}r1(UuriX!rtos/../images/SBL_memory_map.pngr2j]j]j]j]jX}r3U*j2sj]ujMfjhj]ubj)r4}r5(jX - After the application boots and is running on the SOC, it is free to use the SBL_MEM region. - The pinmux data from the board library and MMU Table are part of the SBL_MEM region indicated in the figure above. If pinmux data needs to be placed at a specific location then users can update the SBL linker command file to add the BOARD_IO_DELAY_CODE and BOARD_IO_DELAY_DATA as described in `Application Integration of board library for AM5x `__jjjNjjj}r6(j]j]j]j]j]ujNjhj]r7jt)r8}r9(jUj}r:(jyX-j]j]j]j]j]ujj4j]r;(j{)r<}r=(jX\After the application boots and is running on the SOC, it is free to use the SBL_MEM region.j}r>(j]j]j]j]j]ujj8j]r?j)r@}rA(jX\After the application boots and is running on the SOC, it is free to use the SBL_MEM region.rBjj<jjrjjj}rC(j]j]j]j]j]ujMhj]rDjX\After the application boots and is running on the SOC, it is free to use the SBL_MEM region.rErF}rG(jjBjj@ubaubajjubj{)rH}rI(jXThe pinmux data from the board library and MMU Table are part of the SBL_MEM region indicated in the figure above. If pinmux data needs to be placed at a specific location then users can update the SBL linker command file to add the BOARD_IO_DELAY_CODE and BOARD_IO_DELAY_DATA as described in `Application Integration of board library for AM5x `__j}rJ(j]j]j]j]j]ujj8j]rKj)rL}rM(jXThe pinmux data from the board library and MMU Table are part of the SBL_MEM region indicated in the figure above. If pinmux data needs to be placed at a specific location then users can update the SBL linker command file to add the BOARD_IO_DELAY_CODE and BOARD_IO_DELAY_DATA as described in `Application Integration of board library for AM5x `__jjHjjrjjj}rN(j]j]j]j]j]ujMjj]rO(jX%The pinmux data from the board library and MMU Table are part of the SBL_MEM region indicated in the figure above. If pinmux data needs to be placed at a specific location then users can update the SBL linker command file to add the BOARD_IO_DELAY_CODE and BOARD_IO_DELAY_DATA as described in rPrQ}rR(jX%The pinmux data from the board library and MMU Table are part of the SBL_MEM region indicated in the figure above. If pinmux data needs to be placed at a specific location then users can update the SBL linker command file to add the BOARD_IO_DELAY_CODE and BOARD_IO_DELAY_DATA as described in jjLubj)rS}rT(jXp`Application Integration of board library for AM5x `__j}rU(UnameX1Application Integration of board library for AM5xjX8index_board.html#application-integration-for-am5x-dra7xxj]j]j]j]j]ujjLj]rVjX1Application Integration of board library for AM5xrWrX}rY(jUjjSubajjubeubajjubejjwubaubeubeubj)rZ}r[(jUjj`jjrjjj}r\(j]j]j]j]r]Usbl-customizationr^aj]r_haujMsjhj]r`(j)ra}rb(jXSBL CustomizationrcjjZjjrjjj}rd(j]j]j]j]j]ujMsjhj]rejXSBL Customizationrfrg}rh(jjcjjaubaubj)ri}rj(jUjjZjjrjjj}rk(j]j]j]j]rlUchanging-boot-media-offsetsrmaj]rnjjaujMvjhj]ro(j)rp}rq(jXChanging boot media offsetsrrjjijjrjjj}rs(j]j]j]j]j]ujMvjhj]rtjXChanging boot media offsetsrurv}rw(jjrjjpubaubj)rx}ry(jXThe location at which SBL resides on the flash is predefined by the ROM bootloader spec and so these defaults can`t be changed. However the SBL is a user defined bootloader so many of the defaults can easily be modified to meet application requirements. For example the flash offset location from which the bootloader reads the application is configured in the source files located under /packages/ti/boot/sbl/src/rzjjijjrjjj}r{(j]j]j]j]j]ujMwjhj]r|jXThe location at which SBL resides on the flash is predefined by the ROM bootloader spec and so these defaults can`t be changed. However the SBL is a user defined bootloader so many of the defaults can easily be modified to meet application requirements. For example the flash offset location from which the bootloader reads the application is configured in the source files located under /packages/ti/boot/sbl/src/r}r~}r(jjzjjxubaubj)r}r(jXtExamples of customization that can be changed: - QSPI/SPI flash offsets: These offsets are configured in sbl_qspi.crjjijjrjjj}r(j]j]j]j]j]ujMjhj]rjXtExamples of customization that can be changed: - QSPI/SPI flash offsets: These offsets are configured in sbl_qspi.crr}r(jjjjubaubj3)r}r(jUjjijjrjj6j}r(j]j]j]j]j]ujNjhj]rj)r}r(jX and sbl_spi.crjjjjrjjj}r(j]j]j]j]j]ujMj]rjX and sbl_spi.crr}r(jjjjubaubaubjt)r}r(jUjjijjrjjwj}r(jyX-j]j]j]j]j]ujMjhj]rj{)r}r(jXhMMCSD: The name of the application is hard coded as app in function SBL_MMCBootImage in the sbl_mmcsd.c jjjjrjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXgMMCSD: The name of the application is hard coded as app in function SBL_MMCBootImage in the sbl_mmcsd.crjjjjrjjj}r(j]j]j]j]j]ujMj]rjXgMMCSD: The name of the application is hard coded as app in function SBL_MMCBootImage in the sbl_mmcsd.crr}r(jjjjubaubaubaubeubj)r}r(jUjjZjjrjjj}r(j]j]j]j]rU:speeding-up-boot-by-increasing-speed-of-the-boot-interfaceraj]rh*aujMjhj]r(j)r}r(jX:Speeding up boot by increasing speed of the boot interfacerjjjjrjjj}r(j]j]j]j]j]ujMjhj]rjX:Speeding up boot by increasing speed of the boot interfacerr}r(jjjjubaubj)r}r(jXzThe SBL for AM57xx devices uses LLD drivers to read and write from boot media supported. The SBL uses the default SOC configuration of the drivers and the speeds setup. For example, the SPI driver default SPI bitrate is 1 MHz (Refer /packages/ti/drv/spi/src/SPI_drv.c) so if you wish to speed up boot you can update the SPI parameter in the SBL as shown below:rjjjjrjjj}r(j]j]j]j]j]ujMjhj]rjXzThe SBL for AM57xx devices uses LLD drivers to read and write from boot media supported. The SBL uses the default SOC configuration of the drivers and the speeds setup. For example, the SPI driver default SPI bitrate is 1 MHz (Refer /packages/ti/drv/spi/src/SPI_drv.c) so if you wish to speed up boot you can update the SPI parameter in the SBL as shown below:rr}r(jjjjubaubj)r}r(jX;SPI_Params_init(&spiParams); spiParams.bitRate = 24000000U;jjjjrjjj}r(j@jAj]j]j]j]j]ujMv%jhj]rjX;SPI_Params_init(&spiParams); spiParams.bitRate = 24000000U;rr}r(jUjjubaubj)r¢}râ(jX\The configuration of the driver is usually done in the boot/sbl/soc//sbl_soc.c file.rĢjjjjrjjj}rŢ(j]j]j]j]j]ujMjhj]rƢjX\The configuration of the driver is usually done in the boot/sbl/soc//sbl_soc.c file.rǢrȢ}rɢ(jjĢjj¢ubaubjt)rʢ}rˢ(jUjjjjrjjwj}r̢(jyX-j]j]j]j]j]ujMjhj]r͢(j{)r΢}rϢ(jXr**For SD/MMC**: You can configure higher speed and change bus width using MMCSD_v1_HwAttrs_s or MMCSD_v0_HwAttrs_sjjʢjjrjjj}rТ(j]j]j]j]j]ujNjhj]rѢj)rҢ}rӢ(jXr**For SD/MMC**: You can configure higher speed and change bus width using MMCSD_v1_HwAttrs_s or MMCSD_v0_HwAttrs_sjj΢jjrjjj}rԢ(j]j]j]j]j]ujMj]rբ(j)r֢}rע(jX**For SD/MMC**j}rآ(j]j]j]j]j]ujjҢj]r٢jX For SD/MMCrڢrۢ}rܢ(jUjj֢ubajjubjXd: You can configure higher speed and change bus width using MMCSD_v1_HwAttrs_s or MMCSD_v0_HwAttrs_srݢrޢ}rߢ(jXd: You can configure higher speed and change bus width using MMCSD_v1_HwAttrs_s or MMCSD_v0_HwAttrs_sjjҢubeubaubj{)r}r(jX**For QSPI**: 2 pin and 4 pin mode, and input frequency is configured using QSPI_HwAttrs in the QSPI driver. Check driver for defaults. jjʢjjrjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX**For QSPI**: 2 pin and 4 pin mode, and input frequency is configured using QSPI_HwAttrs in the QSPI driver. Check driver for defaults.jjjjrjjj}r(j]j]j]j]j]ujMj]r(j)r}r(jX **For QSPI**j}r(j]j]j]j]j]ujjj]rjXFor QSPIrr}r(jUjjubajjubjX{: 2 pin and 4 pin mode, and input frequency is configured using QSPI_HwAttrs in the QSPI driver. Check driver for defaults.rr}r(jX{: 2 pin and 4 pin mode, and input frequency is configured using QSPI_HwAttrs in the QSPI driver. Check driver for defaults.jjubeubaubeubj)r}r(jX`Also, check to see if the CACHE and MMU settings for the ARM core are setup to enable fast boot.rjjjjrjjj}r(j]j]j]j]j]ujMjhj]rjX`Also, check to see if the CACHE and MMU settings for the ARM core are setup to enable fast boot.rr}r(jjjjubaubj)r}r(jX**SYSBOOT settings for AM57xx** The SYSBOOT configuration in your hardware using Sitara devices (AM3/AM4/AM5) can play a big role in the time required to boot successfully. On these devices the boot pins configure a boot sequence for the ROM bootloader to check for valid boot image so if you have a preferred boot mode designers are required to use SYSBOOT setup such that the preferred boot media is first in the boot sequence. If the preferred boot media occurs later boot sequence, the boot is likely to add the time required by RBL to check other boot media for an valid image. For example if QSPI is the preferred boot media on your AM57xx hardware then you should have system configure SYSBOOT to boot of QSPI first using SYSBOOT setting for QSPI_1 or QSPI4 for Memory preferred booting or Production booting (Refer: Initialization chapter in TRM).Incorrect SYSBOOT configuration can causes long delays especially if peripheral boot is configured to be one of the preferred boot modes in the boot orderjjjjrjjj}r(j]j]j]j]j]ujNjhj]r(j)r}r(jX**SYSBOOT settings for AM57xx**rjjjjrjjj}r(j]j]j]j]j]ujMj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXSYSBOOT settings for AM57xxrr}r (jUjjubajjubaubj)r }r (jXThe SYSBOOT configuration in your hardware using Sitara devices (AM3/AM4/AM5) can play a big role in the time required to boot successfully. On these devices the boot pins configure a boot sequence for the ROM bootloader to check for valid boot image so if you have a preferred boot mode designers are required to use SYSBOOT setup such that the preferred boot media is first in the boot sequence. If the preferred boot media occurs later boot sequence, the boot is likely to add the time required by RBL to check other boot media for an valid image. For example if QSPI is the preferred boot media on your AM57xx hardware then you should have system configure SYSBOOT to boot of QSPI first using SYSBOOT setting for QSPI_1 or QSPI4 for Memory preferred booting or Production booting (Refer: Initialization chapter in TRM).Incorrect SYSBOOT configuration can causes long delays especially if peripheral boot is configured to be one of the preferred boot modes in the boot orderr jjjjrjjj}r (j]j]j]j]j]ujMj]rjXThe SYSBOOT configuration in your hardware using Sitara devices (AM3/AM4/AM5) can play a big role in the time required to boot successfully. On these devices the boot pins configure a boot sequence for the ROM bootloader to check for valid boot image so if you have a preferred boot mode designers are required to use SYSBOOT setup such that the preferred boot media is first in the boot sequence. If the preferred boot media occurs later boot sequence, the boot is likely to add the time required by RBL to check other boot media for an valid image. For example if QSPI is the preferred boot media on your AM57xx hardware then you should have system configure SYSBOOT to boot of QSPI first using SYSBOOT setting for QSPI_1 or QSPI4 for Memory preferred booting or Production booting (Refer: Initialization chapter in TRM).Incorrect SYSBOOT configuration can causes long delays especially if peripheral boot is configured to be one of the preferred boot modes in the boot orderrr}r(jj jj ubaubeubjc)r}r(jUjjjjrjjfj}r(j]j]j]j]j]ujMjhj]rji)r}r(jUjlKjjjjrjjj}r(j]j]j]j]j]ujKjhj]ubaubeubj)r}r(jUjjZjjrjjj}r(j]j]j]j]rU$reducing-size-of-sbl-and-applicationraj]rjfaujMjhj]r(j)r }r!(jX$Reducing size of SBL and applicationr"jjjjrjjj}r#(j]j]j]j]j]ujMjhj]r$jX$Reducing size of SBL and applicationr%r&}r'(jj"jj ubaubj)r(}r)(jXAnother way to optimize boot times is to reduce the size of the binary that needs to be loaded by the bootloader by building the app with optimization for code size using -Os (GNU GCC) and for -O when using TI compilers.r*jjjjrjjj}r+(j]j]j]j]j]ujMjhj]r,jXAnother way to optimize boot times is to reduce the size of the binary that needs to be loaded by the bootloader by building the app with optimization for code size using -Os (GNU GCC) and for -O when using TI compilers.r-r.}r/(jj*jj(ubaubj)r0}r1(jXOther than compiler based optimizations developers can actively shutdown non-essential modules and features to reduce code size. For example if UART logging is not required or DDR memory is not connected in the system, the initialization functions can be removed to reduce code size.r2jjjjrjjj}r3(j]j]j]j]j]ujMjhj]r4jXOther than compiler based optimizations developers can actively shutdown non-essential modules and features to reduce code size. For example if UART logging is not required or DDR memory is not connected in the system, the initialization functions can be removed to reduce code size.r5r6}r7(jj2jj0ubaubeubeubj)r8}r9(jUjKjj`jjrjjj}r:(j]r;j aj]j]j]r<Uid80r=aj]ujMjhj]r>(j)r?}r@(jX Usage NotesrAjj8jjrjjj}rB(j]j]j]j]j]ujMjhj]rCjX Usage NotesrDrE}rF(jjAjj?ubaubj)rG}rH(jUjj8jjrjjj}rI(j]j]j]j]rJUsbl-avs-and-abb-setuprKaj]rLh`aujMjhj]rM(j)rN}rO(jXSBL AVS and ABB setuprPjjGjjrjjj}rQ(j]j]j]j]j]ujMjhj]rRjXSBL AVS and ABB setuprSrT}rU(jjPjjNubaubj)rV}rW(jX\AVS and ABB configuration is mandated for normal operation of AM57xx devices. All Processor SDK RTOS releases v3.3 and later contain SBL that sets up AVS and ABB configuration features using PM LLD APIs The complete details of PMIC configuration and AVS and ABB configuration required by the chip for different OPP has been implemented in the file:rXjjGjjrjjj}rY(j]j]j]j]j]ujMjhj]rZjX\AVS and ABB configuration is mandated for normal operation of AM57xx devices. All Processor SDK RTOS releases v3.3 and later contain SBL that sets up AVS and ABB configuration features using PM LLD APIs The complete details of PMIC configuration and AVS and ABB configuration required by the chip for different OPP has been implemented in the file:r[r\}r](jjXjjVubaubj)r^}r_(jX/packages/ti/boot/sbl/board/src/sbl_avs_config.c If you are using the same PMIC as GP EVM or IDK platform then you can reuse the settings as is in SBL for your custom platformr`jjGjjrjjj}ra(j]j]j]j]j]ujMjhj]rbjX/packages/ti/boot/sbl/board/src/sbl_avs_config.c If you are using the same PMIC as GP EVM or IDK platform then you can reuse the settings as is in SBL for your custom platformrcrd}re(jj`jj^ubaubeubj)rf}rg(jUjj8jjrjjj}rh(j]j]j]j]riUconfiguring-entry-point-for-sblrjaj]rkhaujMjhj]rl(j)rm}rn(jXConfiguring entry point for SBLrojjfjjrjjj}rp(j]j]j]j]j]ujMjhj]rqjXConfiguring entry point for SBLrrrs}rt(jjojjmubaubj)ru}rv(jX<The two key files that help setup the entry point in the SBL build are "sbl/soc//sbl_init.S" and the linker command file "sbl/soc//linker.cmd". The global symbol Entry is used to provide the entry point to the SBL. The Base address of the memory section SBL_MEM is then used by the tiimage and GP Header tool to provide RBL the guidance to find the entry point to pass control. After MLO is created check the TI image format file(MLO or \_ti.bin) or the GP Header file to confirm that the entry point matches the location of Entry symbol in the sbl.mapjjfjjrjjj}rw(j]j]j]j]j]ujMjhj]rxjX;The two key files that help setup the entry point in the SBL build are "sbl/soc//sbl_init.S" and the linker command file "sbl/soc//linker.cmd". The global symbol Entry is used to provide the entry point to the SBL. The Base address of the memory section SBL_MEM is then used by the tiimage and GP Header tool to provide RBL the guidance to find the entry point to pass control. After MLO is created check the TI image format file(MLO or _ti.bin) or the GP Header file to confirm that the entry point matches the location of Entry symbol in the sbl.mapryrz}r{(jX<The two key files that help setup the entry point in the SBL build are "sbl/soc//sbl_init.S" and the linker command file "sbl/soc//linker.cmd". The global symbol Entry is used to provide the entry point to the SBL. The Base address of the memory section SBL_MEM is then used by the tiimage and GP Header tool to provide RBL the guidance to find the entry point to pass control. After MLO is created check the TI image format file(MLO or \_ti.bin) or the GP Header file to confirm that the entry point matches the location of Entry symbol in the sbl.mapjjuubaubj)r|}r}(jXThe object file created by sbl_init.S should always be the first object file in the link order for the symbol Entry to be placed at the BASE address of the memory section SBL_MEMjjfjjrjjj}r~(j]j]j]j]j]ujNjhj]rj)r}r(jXThe object file created by sbl_init.S should always be the first object file in the link order for the symbol Entry to be placed at the BASE address of the memory section SBL_MEMrjj|jjrjjj}r(j]j]j]j]j]ujMj]rjXThe object file created by sbl_init.S should always be the first object file in the link order for the symbol Entry to be placed at the BASE address of the memory section SBL_MEMrr}r(jjjjubaubaubeubj)r}r(jUjKjj8jjrjjj}r(j]rjFaj]j]j]rUid81raj]ujMjhj]r(j)r}r(jXDebugging application bootrjjjjrjjj}r(j]j]j]j]j]ujMjhj]rjXDebugging application bootrr}r(jjjjubaubj)r}r(jXSteps to debug application boot using Processor SDK RTOS bootloader are discussed in the article `Common steps to debug application boot `__jjjjrjjj}r(j]j]j]j]j]ujMjhj]r(jXaSteps to debug application boot using Processor SDK RTOS bootloader are discussed in the article rr}r(jXaSteps to debug application boot using Processor SDK RTOS bootloader are discussed in the article jjubj)r}r(jXv`Common steps to debug application boot `__j}r(UnameX&Common steps to debug application bootjXIindex_Foundational_Components.html#common-steps-to-debug-application-bootj]j]j]j]j]ujjj]rjX&Common steps to debug application bootrr}r(jUjjubajjubeubeubeubeubj)r}r(jUjj;jjjjj}r(j]j]j]j]rU am65x-j721eraj]rhaujKSjhj]r(j)r}r(jX AM65x/J721Erjjjjjjj}r(j]j]j]j]j]ujKSjhj]rjX AM65x/J721Err}r(jjjjubaubj7)r}r(jXKhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_BOOT_AM65x_J721Ejjjj:XZsource/rtos/PDK_Platform_Software/Boot_Board_and_EVM_Abstractions/BOOT_AM65x_J721E.rst.incrr}rbjj>j}r(j@jAj]j]j]j]j]ujKjhj]rjXKhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_BOOT_AM65x_J721Err}r(jUjjubaubj)r}r(jUjKjjjjjjj}r(j]rXoverviewr£aj]j]j]rãUid82rģaj]ujKjhj]rţ(j)rƣ}rǣ(jXOverviewrȣjjjjjjj}rɣ(j]j]j]j]j]ujKjhj]rʣjXOverviewrˣṛ}rͣ(jjȣjjƣubaubj)rΣ}rϣ(jX.The Secondary Bootloader (SBL) for AM65xx/J721E device initializes the execution environment for multi-core applications and this can be used to demonstrate a real world product experience. This section covers additional details including execution sequence, tools and additional flashing instructions.rУjjjjjjj}rѣ(j]j]j]j]j]ujKjhj]rңjX.The Secondary Bootloader (SBL) for AM65xx/J721E device initializes the execution environment for multi-core applications and this can be used to demonstrate a real world product experience. This section covers additional details including execution sequence, tools and additional flashing instructions.rӣrԣ}rգ(jjУjjΣubaubj)r֣}rף(jXbThe SBL is essentially a baremetal application, and it uses many components from the Processor SDKrأjjjjjjj}r٣(j]j]j]j]j]ujK jhj]rڣjXbThe SBL is essentially a baremetal application, and it uses many components from the Processor SDKrۣrܣ}rݣ(jjأjj֣ubaubjt)rޣ}rߣ(jUjjjjjjwj}r(jyX-j]j]j]j]j]ujKjhj]r(j{)r}r(jX3/packages/ti/build : For build infrastructurerjjޣjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujKj]rjX3/packages/ti/build : For build infrastructurerr}r(jjjjubaubaubj{)r}r(jX</packages/ti/csl : For initialization and SoC addressesrjjޣjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujKj]rjX</packages/ti/csl : For initialization and SoC addressesrr}r(jjjjubaubaubj{)r}r(jXG/packages/ti/board : For board and usecase specific initializationrjjޣjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujKj]rjXG/packages/ti/board : For board and usecase specific initializationrr}r(jjjjubaubaubj{)r}r(jXG/packages/ti/drv/spi : For reading applications from OSPI flashesrjjޣjjjjj}r (j]j]j]j]j]ujNjhj]r j)r }r (jjjjjjjjj}r (j]j]j]j]j]ujKj]rjXG/packages/ti/drv/spi : For reading applications from OSPI flashesrr}r(jjjj ubaubaubj{)r}r(jXH/packages/ti/drv/udma : For reading data from boot media using DMArjjޣjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujKj]rjXH/packages/ti/drv/udma : For reading data from boot media using DMArr}r(jjjjubaubaubj{)r}r(jXG/packages/ti/drv/mmcsd : For reading applications from MMC/SD/eMMCr jjޣjjjjj}r!(j]j]j]j]j]ujNjhj]r"j)r#}r$(jj jjjjjjj}r%(j]j]j]j]j]ujKj]r&jXG/packages/ti/drv/mmcsd : For reading applications from MMC/SD/eMMCr'r(}r)(jj jj#ubaubaubj{)r*}r+(jX?/packages/ti/fs/fatfs : For reading files from MMC/SD/eMMCr,jjޣjjjjj}r-(j]j]j]j]j]ujNjhj]r.j)r/}r0(jj,jj*jjjjj}r1(j]j]j]j]j]ujKj]r2jX?/packages/ti/fs/fatfs : For reading files from MMC/SD/eMMCr3r4}r5(jj,jj/ubaubaubj{)r6}r7(jXH/packages/ti/drv/sciclient : For communicating with DMSC sub-systemr8jjޣjjjjj}r9(j]j]j]j]j]ujNjhj]r:j)r;}r<(jj8jj6jjjjj}r=(j]j]j]j]j]ujKj]r>jXH/packages/ti/drv/sciclient : For communicating with DMSC sub-systemr?r@}rA(jj8jj;ubaubaubj{)rB}rC(jX-/packages/ti/drv/uart : For log messagesrDjjޣjjjjj}rE(j]j]j]j]j]ujNjhj]rFj)rG}rH(jjDjjBjjjjj}rI(j]j]j]j]j]ujKj]rJjX-/packages/ti/drv/uart : For log messagesrKrL}rM(jjDjjGubaubaubj{)rN}rO(jXB/packages/ti/osal : Primitives required by ti/drv components jjޣjjjjj}rP(j]j]j]j]j]ujNjhj]rQj)rR}rS(jXA/packages/ti/osal : Primitives required by ti/drv componentsrTjjNjjjjj}rU(j]j]j]j]j]ujKj]rVjXA/packages/ti/osal : Primitives required by ti/drv componentsrWrX}rY(jjTjjRubaubaubeubj)rZ}r[(jXLThe SBL is in turn used by the board framework to load and start diagnosticsr\jjjjjjj}r](j]j]j]j]j]ujKjhj]r^jXLThe SBL is in turn used by the board framework to load and start diagnosticsr_r`}ra(jj\jjZubaubjhK)rb}rc(jXBootloader Execution SequencerdjjjjjjlKj}re(j]rfUid83rgaj]j]j]j]rhhJaujNjhj]rijXBootloader Execution Sequencerjrk}rl(jjdjjbubaubjt)rm}rn(jUjjjjjjwj}ro(jyX-j]j]j]j]j]ujKjhj]rp(j{)rq}rr(jX**Power On Reset**rsjjmjjjjj}rt(j]j]j]j]j]ujNjhj]ruj)rv}rw(jjsjjqjjjjj}rx(j]j]j]j]j]ujKj]ryj)rz}r{(jjsj}r|(j]j]j]j]j]ujjvj]r}jXPower On Resetr~r}r(jUjjzubajjubaubaubj{)r}r(jXI**ROM Bootloader (RBL)** - Software pre-programmed in AM65xx/J721E ROM memory starts executing - The RBL performs platform configuration and initialization. - It then checks sysboot pins and chooses booting device - The RBL then configures PLL and clock settings for R5, and boot media like eMMC, SD/MMC, OSPI, UART, PCIe, Ethernet etc for reliable boot. - If no valid bootloader found on booting device, the RBL checks for next booting device, based on sysboot pins - It then gets image size and load address by checking the X.509 certificate that is part of the bootloader image. - The RBL then verifies, optionally decrypts and loads the binary to internal memory at the load address specified in the X.509 certificate. - Finally it resets the R5 and passes control to Secondary Bootloader(SBL) running on the R5. jjmjNjjj}r(j]j]j]j]j]ujNjhj]r(j)r}r(jX**ROM Bootloader (RBL)**rjjjjjjj}r(j]j]j]j]j]ujK j]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXROM Bootloader (RBL)rr}r(jUjjubajjubaubjt)r}r(jUj}r(jyX-j]j]j]j]j]ujjj]r(j{)r}r(jXCSoftware pre-programmed in AM65xx/J721E ROM memory starts executingrj}r(j]j]j]j]j]ujjj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujK"j]rjXCSoftware pre-programmed in AM65xx/J721E ROM memory starts executingrr}r(jjjjubaubajjubj{)r}r(jX;The RBL performs platform configuration and initialization.rj}r(j]j]j]j]j]ujjj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujK#j]rjX;The RBL performs platform configuration and initialization.rr}r(jjjjubaubajjubj{)r}r(jX6It then checks sysboot pins and chooses booting devicerj}r(j]j]j]j]j]ujjj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujK$j]rjX6It then checks sysboot pins and chooses booting devicerr}r(jjjjubaubajjubj{)r}r(jXThe RBL then configures PLL and clock settings for R5, and boot media like eMMC, SD/MMC, OSPI, UART, PCIe, Ethernet etc for reliable boot.j}r(j]j]j]j]j]ujjj]rj)r}r(jXThe RBL then configures PLL and clock settings for R5, and boot media like eMMC, SD/MMC, OSPI, UART, PCIe, Ethernet etc for reliable boot.rjjjjjjj}r(j]j]j]j]j]ujK%j]rjXThe RBL then configures PLL and clock settings for R5, and boot media like eMMC, SD/MMC, OSPI, UART, PCIe, Ethernet etc for reliable boot.r¤rä}rĤ(jjjjubaubajjubj{)rŤ}rƤ(jXmIf no valid bootloader found on booting device, the RBL checks for next booting device, based on sysboot pinsj}rǤ(j]j]j]j]j]ujjj]rȤj)rɤ}rʤ(jXmIf no valid bootloader found on booting device, the RBL checks for next booting device, based on sysboot pinsrˤjjŤjjjjj}r̤(j]j]j]j]j]ujK(j]rͤjXmIf no valid bootloader found on booting device, the RBL checks for next booting device, based on sysboot pinsrΤrϤ}rФ(jjˤjjɤubaubajjubj{)rѤ}rҤ(jXpIt then gets image size and load address by checking the X.509 certificate that is part of the bootloader image.j}rӤ(j]j]j]j]j]ujjj]rԤj)rդ}r֤(jXpIt then gets image size and load address by checking the X.509 certificate that is part of the bootloader image.rפjjѤjjjjj}rؤ(j]j]j]j]j]ujK*j]r٤jXpIt then gets image size and load address by checking the X.509 certificate that is part of the bootloader image.rڤrۤ}rܤ(jjפjjդubaubajjubj{)rݤ}rޤ(jXThe RBL then verifies, optionally decrypts and loads the binary to internal memory at the load address specified in the X.509 certificate.j}rߤ(j]j]j]j]j]ujjj]rj)r}r(jXThe RBL then verifies, optionally decrypts and loads the binary to internal memory at the load address specified in the X.509 certificate.rjjݤjjjjj}r(j]j]j]j]j]ujK,j]rjXThe RBL then verifies, optionally decrypts and loads the binary to internal memory at the load address specified in the X.509 certificate.rr}r(jjjjubaubajjubj{)r}r(jX\Finally it resets the R5 and passes control to Secondary Bootloader(SBL) running on the R5. j}r(j]j]j]j]j]ujjj]rj)r}r(jX[Finally it resets the R5 and passes control to Secondary Bootloader(SBL) running on the R5.rjjjjjjj}r(j]j]j]j]j]ujK.j]rjX[Finally it resets the R5 and passes control to Secondary Bootloader(SBL) running on the R5.rr}r(jjjjubaubajjubejjwubeubj{)r}r(jX**Secondary bootloader(SBL)** - User level secondary bootloader(SBL) begins execution from internal memory. It enables ATCM, starts PMU timers for profiling, initializes the MCU, and sets up the stack, heap and globals. It then jumps to main(). - Board Initialization is done by calls to **Board_init()** API.For additional details refer `Processor SDK Board Support `__. - The RAT is setup. Pin MUX and UART console are setup by calling **Board_init()** API. The system firmware (SYSFW) is then loaded from the boot media into the DMSC subsystem. - Once the SYSFW is up and running, the rest of the initialization can be done. - This includes optionally using **Board_init()** to configure PLLs, LPSCs and DDR. - The SBL then loads the application from the boot media. If the image is signed, the application will be copied into a user specified reserved memory, and the SBL will attempt to verify the image by calling system firmware APIs. On HS devices, the boot proceeds only if image verification passes. - The SBL parses application image(s) for each of the core(s) from boot media and scatter loads it to memory. - Once the application is loaded, the SBL communicates with the system firmware to setup the clocks for the core(s) and release it from reset. - The core then starts executing from application entry point. jjmjNjjj}r(j]j]j]j]j]ujNjhj]r(j)r}r(jX**Secondary bootloader(SBL)**rjjjjjjj}r(j]j]j]j]j]ujK0j]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXSecondary bootloader(SBL)rr}r(jUjjubajjubaubjt)r}r(jUj}r(jyX-j]j]j]j]j]ujjj]r(j{)r }r (jXUser level secondary bootloader(SBL) begins execution from internal memory. It enables ATCM, starts PMU timers for profiling, initializes the MCU, and sets up the stack, heap and globals. It then jumps to main().j}r (j]j]j]j]j]ujjj]r j)r }r(jXUser level secondary bootloader(SBL) begins execution from internal memory. It enables ATCM, starts PMU timers for profiling, initializes the MCU, and sets up the stack, heap and globals. It then jumps to main().rjj jjjjj}r(j]j]j]j]j]ujK2j]rjXUser level secondary bootloader(SBL) begins execution from internal memory. It enables ATCM, starts PMU timers for profiling, initializes the MCU, and sets up the stack, heap and globals. It then jumps to main().rr}r(jjjj ubaubajjubj{)r}r(jXBoard Initialization is done by calls to **Board_init()** API.For additional details refer `Processor SDK Board Support `__.j}r(j]j]j]j]j]ujjj]rj)r}r(jXBoard Initialization is done by calls to **Board_init()** API.For additional details refer `Processor SDK Board Support `__.jjjjjjj}r(j]j]j]j]j]ujK5j]r(jX)Board Initialization is done by calls to rr}r(jX)Board Initialization is done by calls to jjubj)r }r!(jX**Board_init()**j}r"(j]j]j]j]j]ujjj]r#jX Board_init()r$r%}r&(jUjj ubajjubjX" API.For additional details refer r'r(}r)(jX" API.For additional details refer jjubj)r*}r+(jX}`Processor SDK Board Support `__j}r,(UnameXProcessor SDK Board SupportjX[http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/Board_EVM_Abstration.htmlj]j]j]j]j]ujjj]r-jXProcessor SDK Board Supportr.r/}r0(jUjj*ubajjubjX.r1}r2(jX.jjubeubajjubj{)r3}r4(jXThe RAT is setup. Pin MUX and UART console are setup by calling **Board_init()** API. The system firmware (SYSFW) is then loaded from the boot media into the DMSC subsystem.j}r5(j]j]j]j]j]ujjj]r6j)r7}r8(jXThe RAT is setup. Pin MUX and UART console are setup by calling **Board_init()** API. The system firmware (SYSFW) is then loaded from the boot media into the DMSC subsystem.jj3jjjjj}r9(j]j]j]j]j]ujK8j]r:(jX@The RAT is setup. Pin MUX and UART console are setup by calling r;r<}r=(jX@The RAT is setup. Pin MUX and UART console are setup by calling jj7ubj)r>}r?(jX**Board_init()**j}r@(j]j]j]j]j]ujj7j]rAjX Board_init()rBrC}rD(jUjj>ubajjubjX] API. The system firmware (SYSFW) is then loaded from the boot media into the DMSC subsystem.rErF}rG(jX] API. The system firmware (SYSFW) is then loaded from the boot media into the DMSC subsystem.jj7ubeubajjubj{)rH}rI(jXMOnce the SYSFW is up and running, the rest of the initialization can be done.rJj}rK(j]j]j]j]j]ujjj]rLj)rM}rN(jjJjjHjjjjj}rO(j]j]j]j]j]ujK:j]rPjXMOnce the SYSFW is up and running, the rest of the initialization can be done.rQrR}rS(jjJjjMubaubajjubj{)rT}rU(jXQThis includes optionally using **Board_init()** to configure PLLs, LPSCs and DDR.rVj}rW(j]j]j]j]j]ujjj]rXj)rY}rZ(jjVjjTjjjjj}r[(j]j]j]j]j]ujK;j]r\(jXThis includes optionally using r]r^}r_(jXThis includes optionally using jjYubj)r`}ra(jX**Board_init()**j}rb(j]j]j]j]j]ujjYj]rcjX Board_init()rdre}rf(jUjj`ubajjubjX" to configure PLLs, LPSCs and DDR.rgrh}ri(jX" to configure PLLs, LPSCs and DDR.jjYubeubajjubj{)rj}rk(jX'The SBL then loads the application from the boot media. If the image is signed, the application will be copied into a user specified reserved memory, and the SBL will attempt to verify the image by calling system firmware APIs. On HS devices, the boot proceeds only if image verification passes.j}rl(j]j]j]j]j]ujjj]rmj)rn}ro(jX'The SBL then loads the application from the boot media. If the image is signed, the application will be copied into a user specified reserved memory, and the SBL will attempt to verify the image by calling system firmware APIs. On HS devices, the boot proceeds only if image verification passes.rpjjjjjjjj}rq(j]j]j]j]j]ujKjjjjjjj}r(UformatXhtmlj@jAj]j]j]j]j]ujKFjhj]rjXh
rr}r(jUjjubaubj)r}r(jX**NOTE**rjjjjjjj}r(j]j]j]j]j]ujKKjhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXNOTErr}r(jUjjubajjubaubjt)r}r(jUjjjjjjwj}r(jyX-j]j]j]j]j]ujKMjhj]r(j{)r}r(jXRBL requires boot loader (SBL) to be in a special format with the binary image appended to a X.509 certificate. The certificate contains the load address, size and SHA of the bootloader image.jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXRBL requires boot loader (SBL) to be in a special format with the binary image appended to a X.509 certificate. The certificate contains the load address, size and SHA of the bootloader image.rjjjjjjj}r(j]j]j]j]j]ujKMj]rjXRBL requires boot loader (SBL) to be in a special format with the binary image appended to a X.509 certificate. The certificate contains the load address, size and SHA of the bootloader image.rr}r(jjjjubaubaubj{)r}r(jX,For a detailed description of ROM bootloader and more information on the image format expected by the RBL refer the initialization chapter in the `AM65xx Technical Reference Manual `__ and the `J721E Technical Reference Manual `__jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r¥(jX,For a detailed description of ROM bootloader and more information on the image format expected by the RBL refer the initialization chapter in the `AM65xx Technical Reference Manual `__ and the `J721E Technical Reference Manual `__jjjjjjj}rå(j]j]j]j]j]ujKPj]rĥ(jXFor a detailed description of ROM bootloader and more information on the image format expected by the RBL refer the initialization chapter in the rťrƥ}rǥ(jXFor a detailed description of ROM bootloader and more information on the image format expected by the RBL refer the initialization chapter in the jjubj)rȥ}rɥ(jXI`AM65xx Technical Reference Manual `__j}rʥ(UnameX!AM65xx Technical Reference ManualjX!http://www.ti.com/lit/pdf/spruid7j]j]j]j]j]ujjj]r˥jX!AM65xx Technical Reference Manualr̥rͥ}rΥ(jUjjȥubajjubjX and the rϥrХ}rѥ(jX and the jjubj)rҥ}rӥ(jXH`J721E Technical Reference Manual `__j}rԥ(UnameX J721E Technical Reference ManualjX!http://www.ti.com/lit/pdf/spruil1j]j]j]j]j]ujjj]rեjX J721E Technical Reference Manualr֥rץ}rإ(jUjjҥubajjubeubaubj{)r٥}rڥ(jXIn addition to the bootloader and application, the DMSC firmware binary is also needed for the SoC to complete the system boot flow.jjjjjjj}rۥ(j]j]j]j]j]ujNjhj]rܥj)rݥ}rޥ(jXIn addition to the bootloader and application, the DMSC firmware binary is also needed for the SoC to complete the system boot flow.rߥjj٥jjjjj}r(j]j]j]j]j]ujKTj]rjXIn addition to the bootloader and application, the DMSC firmware binary is also needed for the SoC to complete the system boot flow.rr}r(jjߥjjݥubaubaubj{)r}r(jXzThe first 256 bytes of the ATCM are reserved by SBL for its use. The SBL initializes the ATCM with 0xFF before it uses it.jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXzThe first 256 bytes of the ATCM are reserved by SBL for its use. The SBL initializes the ATCM with 0xFF before it uses it.rjjjjjjj}r(j]j]j]j]j]ujKVj]rjXzThe first 256 bytes of the ATCM are reserved by SBL for its use. The SBL initializes the ATCM with 0xFF before it uses it.rr}r(jjjjubaubaubj{)r}r(jXIf the multicore application image is signed using the TI Dummy Key, instead of a degenerate key (default setting) the same binary can be used on GP and HS devices. For information on the application's X.509 certificate format, please refer `Security X509 Certificate Documentation `__jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXIf the multicore application image is signed using the TI Dummy Key, instead of a degenerate key (default setting) the same binary can be used on GP and HS devices. For information on the application's X.509 certificate format, please refer `Security X509 Certificate Documentation `__jjjjjjj}r(j]j]j]j]j]ujKXj]r(jXIf the multicore application image is signed using the TI Dummy Key, instead of a degenerate key (default setting) the same binary can be used on GP and HS devices. For information on the application's X.509 certificate format, please refer rr}r(jXIf the multicore application image is signed using the TI Dummy Key, instead of a degenerate key (default setting) the same binary can be used on GP and HS devices. For information on the application's X.509 certificate format, please refer jjubj)r}r(jX`Security X509 Certificate Documentation `__j}r(UnameX'Security X509 Certificate DocumentationjX{http://downloads.ti.com/tisci/esd/latest/2_tisci_msgs/security/sec_cert_format.html#security-x509-certificate-documentationj]j]j]j]j]ujjj]rjX'Security X509 Certificate Documentationrr}r(jUjjubajjubeubaubj{)r}r(jXlWhen the R5 is released from reset, it will always fetch and execute the first intruction from address 0x0. jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXkWhen the R5 is released from reset, it will always fetch and execute the first intruction from address 0x0.r jjjjjjj}r (j]j]j]j]j]ujK]j]r jXkWhen the R5 is released from reset, it will always fetch and execute the first intruction from address 0x0.r r }r(jj jjubaubaubeubj)r}r(jX
jjjjjjj}r(UformatXhtmlj@jAj]j]j]j]j]ujK`jhj]rjXrr}r(jUjjubaubj)r}r(jX.. _am655x-sbl-high-level-arch:jjjjjj j}r(j]j]j]j]j]jUam655x-sbl-high-level-archrujM6&jhj]ubeubj)r}r(jUjjjjUexpect_referenced_by_namer}rj5jsjjj}r(j]j]j]j]r(U block-diagramr jej]r!(j.j5eujKgjhUexpect_referenced_by_idr"}r#jjsj]r$(j)r%}r&(jX Block Diagramr'jjjjjjj}r((j]j]j]j]j]ujKgjhj]r)jX Block Diagramr*r+}r,(jj'jj%ubaubjR)r-}r.(jX0.. Image:: ../images/k3_sbl_arch_block_diag.png jjjjjjZj}r/(UuriX)rtos/../images/k3_sbl_arch_block_diag.pngr0j]j]j]j]jX}r1U*j0sj]ujKjjhj]ubj)r2}r3(jX.. _am655x-sbl-memory-usage:jKjjjjjj j}r4(j]j]j]j]j]jUam655x-sbl-memory-usager5ujM=&jhj]ubeubj)r6}r7(jUjKjjjjj}r8j;j2sjjj}r9(j]r:jaj]j]j]r;(j5Uid84r<ej]r=j;aujKnjhj"}r>j5j2sj]r?(j)r@}rA(jX Memory MaprBjj6jjjjj}rC(j]j]j]j]j]ujKnjhj]rDjX Memory MaprErF}rG(jjBjj@ubaubjR)rH}rI(jX+.. Image:: ../images/k3_sbl_mem_usage.png jj6jjjjZj}rJ(UuriX#rtos/../images/k3_sbl_mem_usage.pngrKj]j]j]j]jX}rLU*jKsj]ujKrjhj]ubj)rM}rN(jX#.. _am655x-sbl-directory-structure:jj6jjjj j}rO(j]j]j]j]j]jUam655x-sbl-directory-structurerPujME&jhj]ubeubj)rQ}rR(jUjKjjjjj}rShjMsjjj}rT(j]rUjaj]j]j]rV(jPUid85rWej]rXhaujKvjhj"}rYjPjMsj]rZ(j)r[}r\(jXDirectory structurer]jjQjjjjj}r^(j]j]j]j]j]ujKvjhj]r_jXDirectory structurer`ra}rb(jj]jj[ubaubj)rc}rd(jXsbl │ ├── board │ └── k3 │ └── sbl_main.c <= define main() for SBL, board specific init │ ├── build │ ├── makefile <= makefile for the SBL component │ ├── sbl_am65xx.sh <= For legacy, called by Yocto build │ ├── sbl_boot_test.mk <= Builds SBL single core tests │ ├── sbl_smp_test.mk <= Builds example app for using SBL lib │ ├── sbl_mcu0_boot_perf_test.mk <= Builds example app for SBL performance tuning │ ├── sbl_mcu0_boot_xip_entry.mk <= Builds example trampoline app to demonstrate transitioning to a XIP app from SBL │ ├── sbl_mcu0_boot_xip_test.mk <= Builds example app to demonstrate XIP execution from XIP capable boot media │ ├── sbl_img.mk <= builds SBL image that is loaded and executed by ROM code │ ├── sbl_lib.mk <= Builds sbl library that other apps can link into │ ├── sbl_multicore_smp.mk <= Builds multi-core image from SBL lib eg. test to demonstrate symmetric multiprocessor boot (SMP) │ └── sbl_multicore_amp.mk <= Builds multi-core image from single core tests to demonstrate asymmetric multiprocessor boot (AMP) │ ├── example │ └── k3MulticoreApp │ ├── binary │ │ └── [soc] │ │ ├── sbl_baremetal_*.appimage <= SBL loadable board specific sample apps for testing SBL boot flow on GP devices │ │ ├── sbl_baremetal_*.appimage.signed <= SBL loadable board specific signed sample apps for testing SBL boot flow on HS devices │ │ └── sbl_baremetal_*_release.x*.bin <= Binary image that can be eXecuted In Place on XIP capable boot media │ ├── mcuAmplinker.lds <= Linker comamnd file when TI CGT is used for Asym. Multiproc. boot │ ├── mpuAmplinker.lds <= GCC linker command file (for Cortex Axx cores) for Asym. Multiproc. boot │ ├── mcuBootPerfLinker.lds <= TI CGT Linker comamnd file for SBL performance tuning example. │ ├── mcuLockStepLinker.lds <= Linker comamnd file when TI CGT is used for R5 lock-step boot │ ├── mpuSmplinker.lds <= GCC linker command file (for Cortex Axx cores) for SMP boot │ ├── mcuXiplinker.lds <= Linker command file for XIP trampoline app │ ├── xip_entry.lds <= Linker comamnd file for XIP test case │ ├── xip_entry.asm <= Entry point of XIP trampoline app │ ├── xip_stub.c <= Simple SBL test app that demonstrates transitioning to a XIP app │ ├── sbl_amp_multicore.c <= Simple SBL test that displays UART message │ ├── sbl_amp_multicore_sections.h <= Allows same source to be loaded to different sections for different cores. │ ├── sbl_mcu_0_boot_perf_benchmark.c <= SBL Test to tune boot performance. │ ├── sbl_multicore_a53.asm <= Test case entry point for Cortex-Axx cores │ ├── sbl_multicore_r5.asm <= Test case entry point for Cortex-R5 cores │ ├── sbl_multicore_r5_sections.inc <= Allows same source to be loaded to different sections for different MCUs. │ ├── sbl_printf.c <= Lightweight UART printf function for SBL testing │ ├── sbl_smp_multicore.c <= Simple SBL SMP test that uses SBL lib to reset MPUs │ └── sbl_smp_r5.asm <= Provides dummy override function for __mpu_init for SMP testcase. │ ├── binary <= ROM bootable SBL images for each board/boot media │   ├── [board] │      └── [bootmedia] │        └── bin │         └── sbl_[bootmedia]_img_mcu1_0_release.tiimage │ ├── lib <= SBL lib for each boot media/board supported │   ├── [bootmedia] │   │ └── [board] │   │    └── r5f │   │    └── release │   │    └── sbl_lib_[bootmedia].aer5f │   └── cust │   └── [board] │      └── r5f │      └── release │      └── sbl_lib_cust.aer5f │ ├── soc <= SOC specific SBL code │ └── k3 │ ├── linker.cmd <= Linker file used for generating ROM loadable SBL image. │ ├── sbl_err_trap.h <= Error loops for SBL │ ├── sbl_init.asm <= SBL Entry point │ ├── sbl_misc.asm <= SBL Assembly utility functions │ ├── sbl_log.h <= SBL logging framework │ ├── sbl_sci_client.c <= Calls SYSFW on DMSC │ ├── sbl_sci_client.h │ ├── sbl_slave_core_boot.c <= Code that contains the sequence to release a core from reset │ ├── sbl_slave_core_boot.h │ ├── sbl_soc.c <= Cache Ops, PMU init, image verfication, etc & SoC specific code like RAT Init.. │ ├── sbl_soc_cfg.h <= Abstraction layer for hiding SoC level changes from SBL │ └── sbl_profile.h <= SBL profiling framework │ ├── src <= Common drivers used across SOCs │ ├── mmcsd │ ├── hyperflash │ ├── ospi │ ├── qspi │ ├── uart │ ├── rprc <= RPRC image parser used by SBL │ └── spi │ └── tools ├── btoccs ├── byteswap ├── ccsutil ├── flashWriter <= Unused for AM65xx/J721E. AM65xx/J721E uses Uniflash to program flashes. ├── multicoreImageGen <= Stitches multiple RPRC images for different cores into a single image ├── omapl13x_boot_utils <= Unused for AM65xx/J721E ├── omapl13x_sd_card_format <= Unused for AM65xx/J721E ├── out2rprc <= Converts .out into .rprc files, so that SBL can load non-continuous memory sections ├── scripts <= Scripts used by .out generated by CCS projects into SBL loadable images │ ├── K3ImageGen.bat │ └── K3ImageGen.sh └── tiImageGen <= Unused for AM65xx/J721E. Image generation is handled by PDK build framework (/pdk_*/packages/ti/build/)jjQjjjjj}re(j@jAj]j]j]j]j]ujML&jhj]rfjXsbl │ ├── board │ └── k3 │ └── sbl_main.c <= define main() for SBL, board specific init │ ├── build │ ├── makefile <= makefile for the SBL component │ ├── sbl_am65xx.sh <= For legacy, called by Yocto build │ ├── sbl_boot_test.mk <= Builds SBL single core tests │ ├── sbl_smp_test.mk <= Builds example app for using SBL lib │ ├── sbl_mcu0_boot_perf_test.mk <= Builds example app for SBL performance tuning │ ├── sbl_mcu0_boot_xip_entry.mk <= Builds example trampoline app to demonstrate transitioning to a XIP app from SBL │ ├── sbl_mcu0_boot_xip_test.mk <= Builds example app to demonstrate XIP execution from XIP capable boot media │ ├── sbl_img.mk <= builds SBL image that is loaded and executed by ROM code │ ├── sbl_lib.mk <= Builds sbl library that other apps can link into │ ├── sbl_multicore_smp.mk <= Builds multi-core image from SBL lib eg. test to demonstrate symmetric multiprocessor boot (SMP) │ └── sbl_multicore_amp.mk <= Builds multi-core image from single core tests to demonstrate asymmetric multiprocessor boot (AMP) │ ├── example │ └── k3MulticoreApp │ ├── binary │ │ └── [soc] │ │ ├── sbl_baremetal_*.appimage <= SBL loadable board specific sample apps for testing SBL boot flow on GP devices │ │ ├── sbl_baremetal_*.appimage.signed <= SBL loadable board specific signed sample apps for testing SBL boot flow on HS devices │ │ └── sbl_baremetal_*_release.x*.bin <= Binary image that can be eXecuted In Place on XIP capable boot media │ ├── mcuAmplinker.lds <= Linker comamnd file when TI CGT is used for Asym. Multiproc. boot │ ├── mpuAmplinker.lds <= GCC linker command file (for Cortex Axx cores) for Asym. Multiproc. boot │ ├── mcuBootPerfLinker.lds <= TI CGT Linker comamnd file for SBL performance tuning example. │ ├── mcuLockStepLinker.lds <= Linker comamnd file when TI CGT is used for R5 lock-step boot │ ├── mpuSmplinker.lds <= GCC linker command file (for Cortex Axx cores) for SMP boot │ ├── mcuXiplinker.lds <= Linker command file for XIP trampoline app │ ├── xip_entry.lds <= Linker comamnd file for XIP test case │ ├── xip_entry.asm <= Entry point of XIP trampoline app │ ├── xip_stub.c <= Simple SBL test app that demonstrates transitioning to a XIP app │ ├── sbl_amp_multicore.c <= Simple SBL test that displays UART message │ ├── sbl_amp_multicore_sections.h <= Allows same source to be loaded to different sections for different cores. │ ├── sbl_mcu_0_boot_perf_benchmark.c <= SBL Test to tune boot performance. │ ├── sbl_multicore_a53.asm <= Test case entry point for Cortex-Axx cores │ ├── sbl_multicore_r5.asm <= Test case entry point for Cortex-R5 cores │ ├── sbl_multicore_r5_sections.inc <= Allows same source to be loaded to different sections for different MCUs. │ ├── sbl_printf.c <= Lightweight UART printf function for SBL testing │ ├── sbl_smp_multicore.c <= Simple SBL SMP test that uses SBL lib to reset MPUs │ └── sbl_smp_r5.asm <= Provides dummy override function for __mpu_init for SMP testcase. │ ├── binary <= ROM bootable SBL images for each board/boot media │   ├── [board] │      └── [bootmedia] │        └── bin │         └── sbl_[bootmedia]_img_mcu1_0_release.tiimage │ ├── lib <= SBL lib for each boot media/board supported │   ├── [bootmedia] │   │ └── [board] │   │    └── r5f │   │    └── release │   │    └── sbl_lib_[bootmedia].aer5f │   └── cust │   └── [board] │      └── r5f │      └── release │      └── sbl_lib_cust.aer5f │ ├── soc <= SOC specific SBL code │ └── k3 │ ├── linker.cmd <= Linker file used for generating ROM loadable SBL image. │ ├── sbl_err_trap.h <= Error loops for SBL │ ├── sbl_init.asm <= SBL Entry point │ ├── sbl_misc.asm <= SBL Assembly utility functions │ ├── sbl_log.h <= SBL logging framework │ ├── sbl_sci_client.c <= Calls SYSFW on DMSC │ ├── sbl_sci_client.h │ ├── sbl_slave_core_boot.c <= Code that contains the sequence to release a core from reset │ ├── sbl_slave_core_boot.h │ ├── sbl_soc.c <= Cache Ops, PMU init, image verfication, etc & SoC specific code like RAT Init.. │ ├── sbl_soc_cfg.h <= Abstraction layer for hiding SoC level changes from SBL │ └── sbl_profile.h <= SBL profiling framework │ ├── src <= Common drivers used across SOCs │ ├── mmcsd │ ├── hyperflash │ ├── ospi │ ├── qspi │ ├── uart │ ├── rprc <= RPRC image parser used by SBL │ └── spi │ └── tools ├── btoccs ├── byteswap ├── ccsutil ├── flashWriter <= Unused for AM65xx/J721E. AM65xx/J721E uses Uniflash to program flashes. ├── multicoreImageGen <= Stitches multiple RPRC images for different cores into a single image ├── omapl13x_boot_utils <= Unused for AM65xx/J721E ├── omapl13x_sd_card_format <= Unused for AM65xx/J721E ├── out2rprc <= Converts .out into .rprc files, so that SBL can load non-continuous memory sections ├── scripts <= Scripts used by .out generated by CCS projects into SBL loadable images │ ├── K3ImageGen.bat │ └── K3ImageGen.sh └── tiImageGen <= Unused for AM65xx/J721E. Image generation is handled by PDK build framework (/pdk_*/packages/ti/build/)rgrh}ri(jUjjcubaubj)rj}rk(jX.. _am655x-image-formats:jjQjjjj j}rl(j]j]j]j]j]jUam655x-image-formatsrmujM&jhj]ubeubj)rn}ro(jUjjjjj}rphDjjsjjj}rq(j]j]j]j]rr(U image-formatsrsjmej]rt(jAhDeujKjhj"}rujmjjsj]rv(j)rw}rx(jX Image Formatsryjjnjjjjj}rz(j]j]j]j]j]ujKjhj]r{jX Image Formatsr|r}}r~(jjyjjwubaubj)r}r(jX**SBL format:**rjjnjjjjj}r(j]j]j]j]j]ujKjhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX SBL format:rr}r(jUjjubajjubaubj)r}r(jXTo generate the a bootable image, the SBL build uses the x509CertificateGen script to sign the sbl binary with so that the ROM Boot Loader (RBL) can parse it. The image format expected by the RBL has been described in detail in the Image Format Section of the `AM65xx Technical Reference Manual `__ and the `J721E Technical Reference Manual `__jjnjjjjj}r(j]j]j]j]j]ujKjhj]r(jXTo generate the a bootable image, the SBL build uses the x509CertificateGen script to sign the sbl binary with so that the ROM Boot Loader (RBL) can parse it. The image format expected by the RBL has been described in detail in the Image Format Section of the rr}r(jXTo generate the a bootable image, the SBL build uses the x509CertificateGen script to sign the sbl binary with so that the ROM Boot Loader (RBL) can parse it. The image format expected by the RBL has been described in detail in the Image Format Section of the jjubj)r}r(jXI`AM65xx Technical Reference Manual `__j}r(UnameX!AM65xx Technical Reference ManualjX!http://www.ti.com/lit/pdf/spruid7j]j]j]j]j]ujjj]rjX!AM65xx Technical Reference Manualrr}r(jUjjubajjubjX and the rr}r(jX and the jjubj)r}r(jXH`J721E Technical Reference Manual `__j}r(UnameX J721E Technical Reference ManualjX!http://www.ti.com/lit/pdf/spruil1j]j]j]j]j]ujjj]rjX J721E Technical Reference Manualrr}r(jUjjubajjubeubj)r}r(jXFor HS devices, the SBL and system firmware have to be signed with the MPK. For an easy out-of-box experience, the Processor SDK for HS devices signs the SBL and system firmware with a TI Dummy Key. Images signed with a TI dummy key will boot on both GP and HS boards from TI. The build system invokes the script /packages/ti/build/makerules/x509CertificateGen* which inturn calls OpenSSL to create the X509 certificate.jjnjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXFor HS devices, the SBL and system firmware have to be signed with the MPK. For an easy out-of-box experience, the Processor SDK for HS devices signs the SBL and system firmware with a TI Dummy Key. Images signed with a TI dummy key will boot on both GP and HS boards from TI. The build system invokes the script /packages/ti/build/makerules/x509CertificateGen* which inturn calls OpenSSL to create the X509 certificate.rjjjjjjj}r(j]j]j]j]j]ujKj]rjXFor HS devices, the SBL and system firmware have to be signed with the MPK. For an easy out-of-box experience, the Processor SDK for HS devices signs the SBL and system firmware with a TI Dummy Key. Images signed with a TI dummy key will boot on both GP and HS boards from TI. The build system invokes the script /packages/ti/build/makerules/x509CertificateGen* which inturn calls OpenSSL to create the X509 certificate.rr}r(jjjjubaubaubcdocutils.nodes warning r)r}r(jXGThe TI Dummy Key(s) *MUST* be replaced by customers during production with their own Private Keys. If the TI Dummy Keys are used in a production system, the system will be open to security attacks. The path of the default (dummy) key used by the signing script for HS devices is /packages/ti/build/makerules/k3_dev_mpk.pemjjnjjjUwarningrj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXGThe TI Dummy Key(s) *MUST* be replaced by customers during production with their own Private Keys. If the TI Dummy Keys are used in a production system, the system will be open to security attacks. The path of the default (dummy) key used by the signing script for HS devices is /packages/ti/build/makerules/k3_dev_mpk.pemjjjjjjj}r(j]j]j]j]j]ujKj]r(jXThe TI Dummy Key(s) rr}r(jXThe TI Dummy Key(s) jjubjM)r}r(jX*MUST*j}r(j]j]j]j]j]ujjj]rjXMUSTrr}r¦(jUjjubajjUubjX- be replaced by customers during production with their own Private Keys. If the TI Dummy Keys are used in a production system, the system will be open to security attacks. The path of the default (dummy) key used by the signing script for HS devices is /packages/ti/build/makerules/k3_dev_mpk.pemrærĦ}rŦ(jX- be replaced by customers during production with their own Private Keys. If the TI Dummy Keys are used in a production system, the system will be open to security attacks. The path of the default (dummy) key used by the signing script for HS devices is /packages/ti/build/makerules/k3_dev_mpk.pemjjubeubaubj)rƦ}rǦ(jX7While SBL and system firmware images signed with the TI Dummy Keys will work on both GP and HS devices, the boot time will be significantly impacted on GP devices. Using SBL signed by TI Dummy Keys on GP devices is only recommended during the prototyping phase - when porting code developed on GP to HS devices.jjnjjjjj}rȦ(j]j]j]j]j]ujNjhj]rɦj)rʦ}r˦(jX7While SBL and system firmware images signed with the TI Dummy Keys will work on both GP and HS devices, the boot time will be significantly impacted on GP devices. Using SBL signed by TI Dummy Keys on GP devices is only recommended during the prototyping phase - when porting code developed on GP to HS devices.r̦jjƦjjjjj}rͦ(j]j]j]j]j]ujKj]rΦjX7While SBL and system firmware images signed with the TI Dummy Keys will work on both GP and HS devices, the boot time will be significantly impacted on GP devices. Using SBL signed by TI Dummy Keys on GP devices is only recommended during the prototyping phase - when porting code developed on GP to HS devices.rϦrЦ}rѦ(jj̦jjʦubaubaubj)rҦ}rӦ(jX**Application image format:**rԦjjnjjjjj}rզ(j]j]j]j]j]ujKjhj]r֦j)rצ}rئ(jjԦj}r٦(j]j]j]j]j]ujjҦj]rڦjXApplication image format:rۦrܦ}rݦ(jUjjצubajjubaubj)rަ}rߦ(jXTwo utilities - out2rprc and multicoreImageGen are used to convert an application elf image(s) into an image loadable by the SBL. The structure of a multicore application image is provided below:rjjnjjjjj}r(j]j]j]j]j]ujMjhj]rjXTwo utilities - out2rprc and multicoreImageGen are used to convert an application elf image(s) into an image loadable by the SBL. The structure of a multicore application image is provided below:rr}r(jjjjަubaubjR)r}r(jX-.. Image:: ../images/Multicore_app_image.png jjnjjjjZj}r(UuriX&rtos/../images/Multicore_app_image.pngrj]j]j]j]jX}rU*jsj]ujMjhj]ubj)r}r(jX**RPRC File Header Format**rjjnjjjjj}r(j]j]j]j]j]ujMjhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXRPRC File Header Formatrr}r(jUjjubajjubaubjy )r}r(jUjjnjjjj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujjj]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthK ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj )r }r (jUj}r (j]j]j]j]j]ujjj]r (j )r }r(jUj}r(j]j]j]j]j]ujj j]rj)r}r(jXOffsetrjj jjjjj}r(j]j]j]j]j]ujM j]rjXOffsetrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj j]rj)r}r(jX Binary valuerjjjjjjj}r (j]j]j]j]j]ujM j]r!jX Binary valuer"r#}r$(jjjjubaubajj ubejj ubajj ubj )r%}r&(jUj}r'(j]j]j]j]j]ujjj]r((j )r)}r*(jUj}r+(j]j]j]j]j]ujj%j]r,(j )r-}r.(jUj}r/(j]j]j]j]j]ujj)j]r0j)r1}r2(jX 0x00000000r3jj-jjjjj}r4(j]j]j]j]j]ujM j]r5jX 0x00000000r6r7}r8(jj3jj1ubaubajj ubj )r9}r:(jUj}r;(j]j]j]j]j]ujj)j]r<j)r=}r>(jX**Magic Word(43525052)**r?jj9jjjjj}r@(j]j]j]j]j]ujM j]rAj)rB}rC(jj?j}rD(j]j]j]j]j]ujj=j]rEjXMagic Word(43525052)rFrG}rH(jUjjBubajjubaubajj ubejj ubj )rI}rJ(jUj}rK(j]j]j]j]j]ujj%j]rL(j )rM}rN(jUj}rO(j]j]j]j]j]ujjIj]rPj)rQ}rR(jX 0x00000004rSjjMjjjjj}rT(j]j]j]j]j]ujMj]rUjX 0x00000004rVrW}rX(jjSjjQubaubajj ubj )rY}rZ(jUj}r[(j]j]j]j]j]ujjIj]r\j)r]}r^(jX**Entry Point (Location)**r_jjYjjjjj}r`(j]j]j]j]j]ujMj]raj)rb}rc(jj_j}rd(j]j]j]j]j]ujj]j]rejXEntry Point (Location)rfrg}rh(jUjjbubajjubaubajj ubejj ubj )ri}rj(jUj}rk(j]j]j]j]j]ujj%j]rl(j )rm}rn(jUj}ro(j]j]j]j]j]ujjij]rpj)rq}rr(jX 0x00000008rsjjmjjjjj}rt(j]j]j]j]j]ujMj]rujX 0x00000008rvrw}rx(jjsjjqubaubajj ubj )ry}rz(jUj}r{(j]j]j]j]j]ujjij]r|j)r}}r~(jX**Reserved Addr**rjjyjjjjj}r(j]j]j]j]j]ujMj]rj)r}r(jjj}r(j]j]j]j]j]ujj}j]rjX Reserved Addrrr}r(jUjjubajjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujj%j]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX 0x0000000Crjjjjjjj}r(j]j]j]j]j]ujMj]rjX 0x0000000Crr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX**Section Count**rjjjjjjj}r(j]j]j]j]j]ujMj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX Section Countrr}r(jUjjubajjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujj%j]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX 0x00000010rjjjjjjj}r(j]j]j]j]j]ujMj]rjX 0x00000010rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX **Version**rjjjjjjj}r(j]j]j]j]j]ujMj]rj)r§}rç(jjj}rħ(j]j]j]j]j]ujjj]rŧjXVersionrƧrǧ}rȧ(jUjj§ubajjubaubajj ubejj ubejj ubejj ubaubj)rɧ}rʧ(jX**RPRC Section Header Format**r˧jjnjjjjj}ŗ(j]j]j]j]j]ujMjhj]rͧj)rΧ}rϧ(jj˧j}rЧ(j]j]j]j]j]ujjɧj]rѧjXRPRC Section Header Formatrҧrӧ}rԧ(jUjjΧubajjubaubjy )rէ}r֧(jUjjnjjjj j}rק(j]j]j]j]j]ujNjhj]rاj~ )r٧}rڧ(jUj}rۧ(j]j]j]j]j]UcolsKujjէj]rܧ(j )rݧ}rާ(jUj}rߧ(j]j]j]j]j]UcolwidthK ujj٧j]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujj٧j]jj ubj )r}r(jUj}r(j]j]j]j]j]ujj٧j]rj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXOffsetrjjjjjjj}r(j]j]j]j]j]ujMj]rjXOffsetrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX Binary valuerjjjjjjj}r(j]j]j]j]j]ujMj]rjX Binary valuerr}r(jjjjubaubajj ubejj ubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj٧j]r(j )r}r(jUj}r (j]j]j]j]j]ujjj]r (j )r }r (jUj}r (j]j]j]j]j]ujjj]rj)r}r(jX 0x00000000rjj jjjjj}r(j]j]j]j]j]ujMj]rjX 0x00000000rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX**Section start Address**rjjjjjjj}r(j]j]j]j]j]ujMj]rj)r }r!(jjj}r"(j]j]j]j]j]ujjj]r#jXSection start Addressr$r%}r&(jUjj ubajjubaubajj ubejj ubj )r'}r((jUj}r)(j]j]j]j]j]ujjj]r*(j )r+}r,(jUj}r-(j]j]j]j]j]ujj'j]r.j)r/}r0(jX 0x00000004r1jj+jjjjj}r2(j]j]j]j]j]ujMj]r3jX 0x00000004r4r5}r6(jj1jj/ubaubajj ubj )r7}r8(jUj}r9(j]j]j]j]j]ujj'j]r:j)r;}r<(jX**Reserved Addr**r=jj7jjjjj}r>(j]j]j]j]j]ujMj]r?j)r@}rA(jj=j}rB(j]j]j]j]j]ujj;j]rCjX Reserved AddrrDrE}rF(jUjj@ubajjubaubajj ubejj ubj )rG}rH(jUj}rI(j]j]j]j]j]ujjj]rJ(j )rK}rL(jUj}rM(j]j]j]j]j]ujjGj]rNj)rO}rP(jX 0x00000008rQjjKjjjjj}rR(j]j]j]j]j]ujM j]rSjX 0x00000008rTrU}rV(jjQjjOubaubajj ubj )rW}rX(jUj}rY(j]j]j]j]j]ujjGj]rZj)r[}r\(jX**Size**r]jjWjjjjj}r^(j]j]j]j]j]ujM j]r_j)r`}ra(jj]j}rb(j]j]j]j]j]ujj[j]rcjXSizerdre}rf(jUjj`ubajjubaubajj ubejj ubj )rg}rh(jUj}ri(j]j]j]j]j]ujjj]rj(j )rk}rl(jUj}rm(j]j]j]j]j]ujjgj]rnj)ro}rp(jX 0x0000000Crqjjkjjjjj}rr(j]j]j]j]j]ujM"j]rsjX 0x0000000Crtru}rv(jjqjjoubaubajj ubj )rw}rx(jUj}ry(j]j]j]j]j]ujjgj]rzj)r{}r|(jX**Reserved CRC**r}jjwjjjjj}r~(j]j]j]j]j]ujM"j]rj)r}r(jj}j}r(j]j]j]j]j]ujj{j]rjX Reserved CRCrr}r(jUjjubajjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX 0x00000010rjjjjjjj}r(j]j]j]j]j]ujM$j]rjX 0x00000010rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX **Reserved**rjjjjjjj}r(j]j]j]j]j]ujM$j]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXReservedrr}r(jUjjubajjubaubajj ubejj ubejj ubejj ubaubj)r}r(jX**Multicore boot image format**rjjnjjjjj}r(j]j]j]j]j]ujM'jhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXMulticore boot image formatrr}r(jUjjubajjubaubj)r}r(jX**Meta Header Start**rjjnjjjjj}r(j]j]j]j]j]ujM)jhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXMeta Header Startrr}r(jUjjubajjubaubjy )r}r(jUjjnjjjj j}r(j]j]j]j]j]ujNjhj]r¨j~ )rè}rĨ(jUj}rŨ(j]j]j]j]j]UcolsKujjj]rƨ(j )rǨ}rȨ(jUj}rɨ(j]j]j]j]j]UcolwidthK ujjèj]jj ubj )rʨ}r˨(jUj}r̨(j]j]j]j]j]UcolwidthKujjèj]jj ubj )rͨ}rΨ(jUj}rϨ(j]j]j]j]j]ujjèj]rШj )rѨ}rҨ(jUj}rӨ(j]j]j]j]j]ujjͨj]rԨ(j )rը}r֨(jUj}rר(j]j]j]j]j]ujjѨj]rبj)r٨}rڨ(jXOffsetrۨjjըjjjjj}rܨ(j]j]j]j]j]ujM,j]rݨjXOffsetrިrߨ}r(jjۨjj٨ubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjѨj]rj)r}r(jX Binary valuerjjjjjjj}r(j]j]j]j]j]ujM,j]rjX Binary valuerr}r(jjjjubaubajj ubejj ubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjèj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX 0x00000000rjjjjjjj}r(j]j]j]j]j]ujM.j]rjX 0x00000000rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX**Magic String (0x5254534D)**rjjjjjjj}r(j]j]j]j]j]ujM.j]r j)r }r (jjj}r (j]j]j]j]j]ujjj]r jXMagic String (0x5254534D)rr}r(jUjj ubajjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX 0x00000004rjjjjjjj}r(j]j]j]j]j]ujM0j]rjX 0x00000004rr}r (jjjjubaubajj ubj )r!}r"(jUj}r#(j]j]j]j]j]ujjj]r$j)r%}r&(jX**Number of Files**r'jj!jjjjj}r((j]j]j]j]j]ujM0j]r)j)r*}r+(jj'j}r,(j]j]j]j]j]ujj%j]r-jXNumber of Filesr.r/}r0(jUjj*ubajjubaubajj ubejj ubj )r1}r2(jUj}r3(j]j]j]j]j]ujjj]r4(j )r5}r6(jUj}r7(j]j]j]j]j]ujj1j]r8j)r9}r:(jX 0x00000008r;jj5jjjjj}r<(j]j]j]j]j]ujM2j]r=jX 0x00000008r>r?}r@(jj;jj9ubaubajj ubj )rA}rB(jUj}rC(j]j]j]j]j]ujj1j]rDj)rE}rF(jX **Device ID**rGjjAjjjjj}rH(j]j]j]j]j]ujM2j]rIj)rJ}rK(jjGj}rL(j]j]j]j]j]ujjEj]rMjX Device IDrNrO}rP(jUjjJubajjubaubajj ubejj ubj )rQ}rR(jUj}rS(j]j]j]j]j]ujjj]rT(j )rU}rV(jUj}rW(j]j]j]j]j]ujjQj]rXj)rY}rZ(jX 0x0000000Cr[jjUjjjjj}r\(j]j]j]j]j]ujM4j]r]jX 0x0000000Cr^r_}r`(jj[jjYubaubajj ubj )ra}rb(jUj}rc(j]j]j]j]j]ujjQj]rdj)re}rf(jX **Reserved**rgjjajjjjj}rh(j]j]j]j]j]ujM4j]rij)rj}rk(jjgj}rl(j]j]j]j]j]ujjej]rmjXReservedrnro}rp(jUjjjubajjubaubajj ubejj ubejj ubejj ubaubj)rq}rr(jX**Meta Header per Core**rsjjnjjjjj}rt(j]j]j]j]j]ujM7jhj]ruj)rv}rw(jjsj}rx(j]j]j]j]j]ujjqj]ryjXMeta Header per Corerzr{}r|(jUjjvubajjubaubjy )r}}r~(jUjjnjjjj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujj}j]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthK ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXOffsetrjjjjjjj}r(j]j]j]j]j]ujM:j]rjXOffsetrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX Binary valuerjjjjjjj}r(j]j]j]j]j]ujM:j]rjX Binary valuerr}r(jjjjubaubajj ubejj ubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX 0x00000000rjjjjjjj}r(j]j]j]j]j]ujM<j]rjX 0x00000000rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r©j)ré}rĩ(jX **Core ID**rũjjjjjjj}rƩ(j]j]j]j]j]ujM<j]rǩj)rȩ}rɩ(jjũj}rʩ(j]j]j]j]j]ujjéj]r˩jXCore IDr̩rͩ}rΩ(jUjjȩubajjubaubajj ubejj ubj )rϩ}rЩ(jUj}rѩ(j]j]j]j]j]ujjj]rҩ(j )rө}rԩ(jUj}rթ(j]j]j]j]j]ujjϩj]r֩j)rש}rة(jX 0x00000004r٩jjөjjjjj}rک(j]j]j]j]j]ujM>j]r۩jX 0x00000004rܩrݩ}rީ(jj٩jjשubaubajj ubj )rߩ}r(jUj}r(j]j]j]j]j]ujjϩj]rj)r}r(jX**Image Offset**rjjߩjjjjj}r(j]j]j]j]j]ujM>j]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX Image Offsetrr}r(jUjjubajjubaubajj ubejj ubejj ubejj ubaubj)r}r(jX$**Signed application image format:**rjjnjjjjj}r(j]j]j]j]j]ujMBjhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX Signed application image format:rr}r(jUjjubajjubaubj)r}r(jXOTo convert the multicore application image into a format that can be verified, the build flow uses the x509CertificateGen script to create a x509 certificate for the app image. Images that have a x509 certificate are called signed images. Signed applications images are mandatory for HS devices, but will work also work on GP devices.rjjnjjjjj}r(j]j]j]j]j]ujMDjhj]rjXOTo convert the multicore application image into a format that can be verified, the build flow uses the x509CertificateGen script to create a x509 certificate for the app image. Images that have a x509 certificate are called signed images. Signed applications images are mandatory for HS devices, but will work also work on GP devices.rr}r(jjjjubaubj)r}r(jXSigned images are automatically detected by the SBL and loaded into a scratch memory area specified during SBL build. The scratch memory area used by default is specified in `sbl_lib.mk `__ via the flags SBL_SCRATCH_MEM_START and SBL_SCRATCH_MEM_SIZE. The SBL_SCRATCH_MEM* options can also be specified for custom builds to override the defaults.jjnjjjjj}r(j]j]j]j]j]ujMIjhj]r(jXSigned images are automatically detected by the SBL and loaded into a scratch memory area specified during SBL build. The scratch memory area used by default is specified in rr}r (jXSigned images are automatically detected by the SBL and loaded into a scratch memory area specified during SBL build. The scratch memory area used by default is specified in jjubj)r }r (jXT`sbl_lib.mk `__j}r (UnameX sbl_lib.mkjXBhttps://git.ti.com/keystone-rtos/sbl/blobs/master/build/sbl_lib.mkj]j]j]j]j]ujjj]r jX sbl_lib.mkrr}r(jUjj ubajjubjX via the flags SBL_SCRATCH_MEM_START and SBL_SCRATCH_MEM_SIZE. The SBL_SCRATCH_MEM* options can also be specified for custom builds to override the defaults.rr}r(jX via the flags SBL_SCRATCH_MEM_START and SBL_SCRATCH_MEM_SIZE. The SBL_SCRATCH_MEM* options can also be specified for custom builds to override the defaults.jjubeubj)r}r(jXThe SBL scratch memory is unavailable to applications during app load time, as the SBL is still active. Once the SBL transfers control to the application, this memory is available for app use - in other words SBL_SCRATCH_MEM* is available during app runtime.rjjnjjjjj}r(j]j]j]j]j]ujMOjhj]rjXThe SBL scratch memory is unavailable to applications during app load time, as the SBL is still active. Once the SBL transfers control to the application, this memory is available for app use - in other words SBL_SCRATCH_MEM* is available during app runtime.rr}r(jjjjubaubj)r}r(jXFor information on the application's X.509 certificate format, please refer `Security X509 Certificate Documentation `__jjnjjjjj}r(j]j]j]j]j]ujMSjhj]r(jXLFor information on the application's X.509 certificate format, please refer r r!}r"(jXLFor information on the application's X.509 certificate format, please refer jjubj)r#}r$(jX`Security X509 Certificate Documentation `__j}r%(UnameX'Security X509 Certificate DocumentationjX{http://downloads.ti.com/tisci/esd/latest/2_tisci_msgs/security/sec_cert_format.html#security-x509-certificate-documentationj]j]j]j]j]ujjj]r&jX'Security X509 Certificate Documentationr'r(}r)(jUjj#ubajjubeubeubj)r*}r+(jUjjjjjjj}r,(j]j]j]j]r-U#building-the-sbl-and-its-componentsr.aj]r/h0aujMXjhj]r0(j)r1}r2(jX#Building the SBL and its componentsr3jj*jjjjj}r4(j]j]j]j]j]ujMXjhj]r5jX#Building the SBL and its componentsr6r7}r8(jj3jj1ubaubj)r9}r:(jX**Pre-requisites to Building**r;jj*jjjjj}r<(j]j]j]j]j]ujMZjhj]r=j)r>}r?(jj;j}r@(j]j]j]j]j]ujj9j]rAjXPre-requisites to BuildingrBrC}rD(jUjj>ubajjubaubjt)rE}rF(jUjj*jjjjwj}rG(jyX-j]j]j]j]j]ujM\jhj]rHj{)rI}rJ(jXSet your environment using pdksetupenv.bat or pdksetupenv.sh. Refer to `Processor SDK RTOS Building `__ for information on setting up your build environment jjEjjjjj}rK(j]j]j]j]j]ujNjhj]rLj)rM}rN(jXSet your environment using pdksetupenv.bat or pdksetupenv.sh. Refer to `Processor SDK RTOS Building `__ for information on setting up your build environmentjjIjjjjj}rO(j]j]j]j]j]ujM\j]rP(jXGSet your environment using pdksetupenv.bat or pdksetupenv.sh. Refer to rQrR}rS(jXGSet your environment using pdksetupenv.bat or pdksetupenv.sh. Refer to jjMubj)rT}rU(jX`Processor SDK RTOS Building `__j}rV(UnameXProcessor SDK RTOS BuildingjXghttp://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_overview.html#setup-environmentj]j]j]j]j]ujjMj]rWjXProcessor SDK RTOS BuildingrXrY}rZ(jUjjTubajjubjX5 for information on setting up your build environmentr[r\}r](jX5 for information on setting up your build environmentjjMubeubaubaubj)r^}r_(jXh
jj*jjjjj}r`(UformatXhtmlj@jAj]j]j]j]j]ujM_jhj]rajXh
rbrc}rd(jUjj^ubaubj)re}rf(jX**NOTE**rgjj*jjjjj}rh(j]j]j]j]j]ujMdjhj]rij)rj}rk(jjgj}rl(j]j]j]j]j]ujjej]rmjXNOTErnro}rp(jUjjjubajjubaubjt)rq}rr(jUjj*jjjjwj}rs(jyX-j]j]j]j]j]ujMfjhj]rtj{)ru}rv(jXnSBL needs openssl to build. To check if openssl is present, type the following at the linux or windows prompt.jjqjjjjj}rw(j]j]j]j]j]ujNjhj]rxj)ry}rz(jXnSBL needs openssl to build. To check if openssl is present, type the following at the linux or windows prompt.r{jjujjjjj}r|(j]j]j]j]j]ujMfj]r}jXnSBL needs openssl to build. To check if openssl is present, type the following at the linux or windows prompt.r~r}r(jj{jjyubaubaubaubj)r}r(jXopenssl versionjj*jjjjj}r(j@jAj]j]j]j]j]ujM<'jhj]rjXopenssl versionrr}r(jUjjubaubjt)r}r(jUjj*jjjjwj}r(jyX-j]j]j]j]j]ujMmjhj]r(j{)r}r(jXVTo build on Linux, you need to have `mono `__ installed. jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXUTo build on Linux, you need to have `mono `__ installed.jjjjjjj}r(j]j]j]j]j]ujMmj]r(jX$To build on Linux, you need to have rr}r(jX$To build on Linux, you need to have jjubj)r}r(jX&`mono `__j}r(UnameXmonojXhttp://www.mono-project.comj]j]j]j]j]ujjj]rjXmonorr}r(jUjjubajjubjX installed.rr}r(jX installed.jjubeubaubj{)r}r(jXRefer `Build Dependencies `__ for instructions on how to install these tools, if they are not already present on your system. jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXRefer `Build Dependencies `__ for instructions on how to install these tools, if they are not already present on your system.jjjjjjj}r(j]j]j]j]j]ujMoj]r(jXRefer rr}r(jXRefer jjubj)r}r(jXp`Build Dependencies `__j}r(UnameXBuild DependenciesjXWhttp://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/Overview.html#commandj]j]j]j]j]ujjj]rjXBuild Dependenciesrr}r(jUjjubajjubjX` for instructions on how to install these tools, if they are not already present on your system.rr}r(jX` for instructions on how to install these tools, if they are not already present on your system.jjubeubaubeubj)r}r(jX
jj*jjjjj}r(UformatXhtmlj@jAj]j]j]j]j]ujMsjhj]rjX
rr}r(jUjjubaubj)r}r(jX**Compiling the SBL**rjj*jjjjj}r(j]j]j]j]j]ujMwjhj]rj)rª}rê(jjj}rĪ(j]j]j]j]j]ujjj]rŪjXCompiling the SBLrƪrǪ}rȪ(jUjjªubajjubaubj)rɪ}rʪ(jX#To build all the SBL components: ::jj*jjjjj}r˪(j]j]j]j]j]ujMyjhj]r̪jX To build all the SBL components:rͪrΪ}rϪ(jX To build all the SBL components:jjɪubaubj)rЪ}rѪ(jX]cd /packages/ti/boot/sbl/build gmake clean all (for windows) make clean all (for Linux)jj*jjjjj}rҪ(j@jAj]j]j]j]j]ujMN'jhj]rӪjX]cd /packages/ti/boot/sbl/build gmake clean all (for windows) make clean all (for Linux)rԪrժ}r֪(jUjjЪubaubjt)rת}rت(jUjj*jjjjwj}r٪(jyX-j]j]j]j]j]ujMjhj]rڪ(j{)r۪}rܪ(jXISBL image files are be located at: **/packages/ti/boot/sbl/binary/**rݪjjתjjjjj}rު(j]j]j]j]j]ujNjhj]rߪj)r}r(jjݪjj۪jjjjj}r(j]j]j]j]j]ujMj]r(jX#SBL image files are be located at: rr}r(jX#SBL image files are be located at: jjubj)r}r(jX&**/packages/ti/boot/sbl/binary/**j}r(j]j]j]j]j]ujjj]rjX"/packages/ti/boot/sbl/binary/rr}r(jUjjubajjubeubaubj{)r}r(jXYSBL examples are located at **/packages/ti/boot/sbl/examples/k3MulticoreApp/binary**rjjתjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujMj]r(jXSBL examples are located at rr}r(jXSBL examples are located at jjubj)r}r(jX=**/packages/ti/boot/sbl/examples/k3MulticoreApp/binary**j}r(j]j]j]j]j]ujjj]rjX9/packages/ti/boot/sbl/examples/k3MulticoreApp/binaryrr}r(jUjjubajjubeubaubj{)r}r(jX;SBL lib are located at **/packages/ti/boot/sbl/lib/** jjתjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX:SBL lib are located at **/packages/ti/boot/sbl/lib/**jjjjjjj}r(j]j]j]j]j]ujMj]r(jXSBL lib are located at r r }r (jXSBL lib are located at jjubj)r }r (jX#**/packages/ti/boot/sbl/lib/**j}r(j]j]j]j]j]ujjj]rjX/packages/ti/boot/sbl/lib/rr}r(jUjj ubajjubeubaubeubj)r}r(jX$**Compile time options for the SBL**rjj*jjjjj}r(j]j]j]j]j]ujMjhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX Compile time options for the SBLrr}r(jUjjubajjubaubj)r}r (jXThe SBL supports several compile time options to tweak the SBL to satisfy requirements of ease of use, boot time and size. These can be enabled or disabled by editing `sbl/sbl_component.mk `__jj*jjjjj}r!(j]j]j]j]j]ujMjhj]r"(jXThe SBL supports several compile time options to tweak the SBL to satisfy requirements of ease of use, boot time and size. These can be enabled or disabled by editing r#r$}r%(jXThe SBL supports several compile time options to tweak the SBL to satisfy requirements of ease of use, boot time and size. These can be enabled or disabled by editing jjubj)r&}r'(jXn`sbl/sbl_component.mk `__j}r((UnameXsbl/sbl_component.mkjXShttp://git.ti.com/cgit/processor-sdk/pdk/tree/packages/ti/boot/sbl/sbl_component.mkj]j]j]j]j]ujjj]r)jXsbl/sbl_component.mkr*r+}r,(jUjj&ubajjubeubjt)r-}r.(jUjj*jjjjwj}r/(jyX-j]j]j]j]j]ujMjhj]r0(j{)r1}r2(jXSBL_LOG_LEVEL : Controls amount of SBL logs (on the MCU UART) and system firmware logs(on WAKEUP UART). Varies from 0(no logs) to 3 (all logs)jj-jjjjj}r3(j]j]j]j]j]ujNjhj]r4j)r5}r6(jXSBL_LOG_LEVEL : Controls amount of SBL logs (on the MCU UART) and system firmware logs(on WAKEUP UART). Varies from 0(no logs) to 3 (all logs)r7jj1jjjjj}r8(j]j]j]j]j]ujMj]r9jXSBL_LOG_LEVEL : Controls amount of SBL logs (on the MCU UART) and system firmware logs(on WAKEUP UART). Varies from 0(no logs) to 3 (all logs)r:r;}r<(jj7jj5ubaubaubj{)r=}r>(jXdSBL_USE_DMA : Valid values are 0 (use CPU to access boot media) or 1 (use DMA to access boot media).jj-jjjjj}r?(j]j]j]j]j]ujNjhj]r@j)rA}rB(jXdSBL_USE_DMA : Valid values are 0 (use CPU to access boot media) or 1 (use DMA to access boot media).rCjj=jjjjj}rD(j]j]j]j]j]ujMj]rEjXdSBL_USE_DMA : Valid values are 0 (use CPU to access boot media) or 1 (use DMA to access boot media).rFrG}rH(jjCjjAubaubaubj{)rI}rJ(jX SBL_DISPLAY_PROFILE_INFO : At the end of the boot process, displays a log of timestamps at which different SBL profile points are hit. This is useful to see how much time the SBL spends in different functions. SBL_LOG_LEVEL can significantly affect performance numbers.jj-jjjjj}rK(j]j]j]j]j]ujNjhj]rLj)rM}rN(jX SBL_DISPLAY_PROFILE_INFO : At the end of the boot process, displays a log of timestamps at which different SBL profile points are hit. This is useful to see how much time the SBL spends in different functions. SBL_LOG_LEVEL can significantly affect performance numbers.rOjjIjjjjj}rP(j]j]j]j]j]ujMj]rQjX SBL_DISPLAY_PROFILE_INFO : At the end of the boot process, displays a log of timestamps at which different SBL profile points are hit. This is useful to see how much time the SBL spends in different functions. SBL_LOG_LEVEL can significantly affect performance numbers.rRrS}rT(jjOjjMubaubaubj{)rU}rV(jXSBL_ENABLE_PLL : Dials up all the PLLs calling Board_init(). Makes it easier for applications as they no longer have to initialize the PLLs. However, enabling this significantly increases boot time and power consumption. Requires system firmware to be loaded.jj-jjjjj}rW(j]j]j]j]j]ujNjhj]rXj)rY}rZ(jXSBL_ENABLE_PLL : Dials up all the PLLs calling Board_init(). Makes it easier for applications as they no longer have to initialize the PLLs. However, enabling this significantly increases boot time and power consumption. Requires system firmware to be loaded.r[jjUjjjjj}r\(j]j]j]j]j]ujMj]r]jXSBL_ENABLE_PLL : Dials up all the PLLs calling Board_init(). Makes it easier for applications as they no longer have to initialize the PLLs. However, enabling this significantly increases boot time and power consumption. Requires system firmware to be loaded.r^r_}r`(jj[jjYubaubaubj{)ra}rb(jXSBL_ENABLE_CLOCKS : Enables all the module clocks by calling Board_init(). Makes it easier for applications as they no longer have to enable clocks.jj-jjjjj}rc(j]j]j]j]j]ujNjhj]rdj)re}rf(jXSBL_ENABLE_CLOCKS : Enables all the module clocks by calling Board_init(). Makes it easier for applications as they no longer have to enable clocks.rgjjajjjjj}rh(j]j]j]j]j]ujMj]rijXSBL_ENABLE_CLOCKS : Enables all the module clocks by calling Board_init(). Makes it easier for applications as they no longer have to enable clocks.rjrk}rl(jjgjjeubaubaubj{)rm}rn(jXSBL_ENABLE_DDR : Initializes the DDR. At the cost of boot time, this enables applications to run from and use DDR. SBL_ENABLE_CLOCKS and SBL_ENABLE_PLL must also be enabed for this to work. Enabling this option increases the boot time.jj-jjjjj}ro(j]j]j]j]j]ujNjhj]rpj)rq}rr(jXSBL_ENABLE_DDR : Initializes the DDR. At the cost of boot time, this enables applications to run from and use DDR. SBL_ENABLE_CLOCKS and SBL_ENABLE_PLL must also be enabed for this to work. Enabling this option increases the boot time.rsjjmjjjjj}rt(j]j]j]j]j]ujMj]rujXSBL_ENABLE_DDR : Initializes the DDR. At the cost of boot time, this enables applications to run from and use DDR. SBL_ENABLE_CLOCKS and SBL_ENABLE_PLL must also be enabed for this to work. Enabling this option increases the boot time.rvrw}rx(jjsjjqubaubaubj{)ry}rz(jXSBL_SKIP_MCU_RESET : Jumps to the MCU0 application entry point without resetting the core. Enables faster boot time. Will not change the MCU's mode (lock-step/split). Application also inherits the MCU state as the SBL left it in.jj-jjjjj}r{(j]j]j]j]j]ujNjhj]r|j)r}}r~(jXSBL_SKIP_MCU_RESET : Jumps to the MCU0 application entry point without resetting the core. Enables faster boot time. Will not change the MCU's mode (lock-step/split). Application also inherits the MCU state as the SBL left it in.rjjyjjjjj}r(j]j]j]j]j]ujMj]rjXSBL_SKIP_MCU_RESET : Jumps to the MCU0 application entry point without resetting the core. Enables faster boot time. Will not change the MCU's mode (lock-step/split). Application also inherits the MCU state as the SBL left it in.rr}r(jjjj}ubaubaubj{)r}r(jXSBL_ENABLE_DEV_GRP_MCU : Will cause the system firmware to only use MCU domain resources during system firmware initialization. This can be dont either to support boot when the main power domain is off, or to save boot time. jj-jjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXSBL_ENABLE_DEV_GRP_MCU : Will cause the system firmware to only use MCU domain resources during system firmware initialization. This can be dont either to support boot when the main power domain is off, or to save boot time.rjjjjjjj}r(j]j]j]j]j]ujMj]rjXSBL_ENABLE_DEV_GRP_MCU : Will cause the system firmware to only use MCU domain resources during system firmware initialization. This can be dont either to support boot when the main power domain is off, or to save boot time.rr}r(jjjjubaubaubeubj)r}r(jXThe SBL also supports a "custom" build, in addition to standard out-of-box builds. A custom build is a useful way of testing out the effect of different build options - like when optimizing for boot time, or enabling custom usecases like eXecute In Place (XIP) to reduce memory usage.rjj*jjjjj}r(j]j]j]j]j]ujMjhj]rjXThe SBL also supports a "custom" build, in addition to standard out-of-box builds. A custom build is a useful way of testing out the effect of different build options - like when optimizing for boot time, or enabling custom usecases like eXecute In Place (XIP) to reduce memory usage.rr}r(jjjjubaubj)r}r(jXFor an example of how to use such custom builds, please refer to `sbl/sbl_component.mk `__. It shows how to specify a select list of build options while building SBL images and libs.jj*jjjjj}r(j]j]j]j]j]ujMjhj]r(jXAFor an example of how to use such custom builds, please refer to rr}r(jXAFor an example of how to use such custom builds, please refer to jjubj)r}r(jXt`sbl/sbl_component.mk `__j}r(UnameXsbl/sbl_component.mkjXYhttps://git.ti.com/cgit/processor-sdk/pdk/tree/packages/ti/boot/sbl/sbl_component.mk#n526j]j]j]j]j]ujjj]rjXsbl/sbl_component.mkrr}r(jUjjubajjubjX\. It shows how to specify a select list of build options while building SBL images and libs.rr}r(jX\. It shows how to specify a select list of build options while building SBL images and libs.jjubeubj)r}r(jX**SBL Startup**rjj*jjjjj}r(j]j]j]j]j]ujMjhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX SBL Startuprr}r(jUjjubajjubaubj)r}r(jXxThe SBL can specify the R5 configuration (lockstep or split) that ROM needs to use when it starts up the SBL. This info is passed to ROM as a field in the X509 certificate. The value in this field can be controlled by editing the build flag R5_STARTUP_MODE in `sbl/build/sbl_img.mk `__jj*jjjjj}r(j]j]j]j]j]ujMjhj]r(jXThe SBL can specify the R5 configuration (lockstep or split) that ROM needs to use when it starts up the SBL. This info is passed to ROM as a field in the X509 certificate. The value in this field can be controlled by editing the build flag R5_STARTUP_MODE in rr}r(jXThe SBL can specify the R5 configuration (lockstep or split) that ROM needs to use when it starts up the SBL. This info is passed to ROM as a field in the X509 certificate. The value in this field can be controlled by editing the build flag R5_STARTUP_MODE in jjubj)r}r(jXs`sbl/build/sbl_img.mk `__j}r(UnameXsbl/build/sbl_img.mkjXXhttps://git.ti.com/cgit/processor-sdk/pdk/tree/packages/ti/boot/sbl/build/sbl_img.mk#n91j]j]j]j]j]ujjj]rjXsbl/build/sbl_img.mkrr«}rë(jUjjubajjubeubjt)rī}rū(jUjj*jjjjwj}rƫ(jyX-j]j]j]j]j]ujMjhj]rǫ(j{)rȫ}rɫ(jXPEFUSE_DEFAULT : SBL will run with the same R5 configuration the boot rom ran in.rʫjjījjjjj}r˫(j]j]j]j]j]ujNjhj]r̫j)rͫ}rΫ(jjʫjjȫjjjjj}rϫ(j]j]j]j]j]ujMj]rЫjXPEFUSE_DEFAULT : SBL will run with the same R5 configuration the boot rom ran in.rѫrҫ}rӫ(jjʫjjͫubaubaubj{)rԫ}rի(jXWSPLIT_MODE : ROM will switch the R5 to split mode before starting the SBL (default). jjījjjjj}r֫(j]j]j]j]j]ujNjhj]r׫j)rث}r٫(jXUSPLIT_MODE : ROM will switch the R5 to split mode before starting the SBL (default).rګjjԫjjjjj}r۫(j]j]j]j]j]ujMj]rܫjXUSPLIT_MODE : ROM will switch the R5 to split mode before starting the SBL (default).rݫrޫ}r߫(jjګjjثubaubaubeubj)r}r(jX-**Enabling/Disabling JTAG on secure devices**rjj*jjjjj}r(j]j]j]j]j]ujMjhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX)Enabling/Disabling JTAG on secure devicesrr}r(jUjjubajjubaubj)r}r(jX@JTAG access is controlled using a field in the X509 certificate.rjj*jjjjj}r(j]j]j]j]j]ujMjhj]rjX@JTAG access is controlled using a field in the X509 certificate.rr}r(jjjjubaubj)r}r(jXBy default, for an easy out of box experience, the Processor SDK enables debug via JTAG on High Secure devices. Leaving JTAG enabled, while making it easy for software development, creates a major security hole in production devices.rjj*jjjjj}r(j]j]j]j]j]ujMjhj]rjXBy default, for an easy out of box experience, the Processor SDK enables debug via JTAG on High Secure devices. Leaving JTAG enabled, while making it easy for software development, creates a major security hole in production devices.rr}r(jjjjubaubj)r}r(jXTo disable/change the level of JTAG access on HS devices, update the value of the debugType field in the signing scripts `build/makerules/x509template.txt `__ (when building from windows) and `build/makerules/x509CertificateGen.sh `__ (when building from linux).jj*jjjjj}r(j]j]j]j]j]ujMjhj]r(jXyTo disable/change the level of JTAG access on HS devices, update the value of the debugType field in the signing scripts rr}r(jXyTo disable/change the level of JTAG access on HS devices, update the value of the debugType field in the signing scripts jjubj)r}r(jX`build/makerules/x509template.txt `__j}r(UnameX build/makerules/x509template.txtjX^http://git.ti.com/cgit/processor-sdk/pdk/tree/packages/ti/build/makerules/x509template.txt#n74j]j]j]j]j]ujjj]rjX build/makerules/x509template.txtrr}r (jUjjubajjubjX" (when building from windows) and r r }r (jX" (when building from windows) and jjubj)r }r(jX`build/makerules/x509CertificateGen.sh `__j}r(UnameX%build/makerules/x509CertificateGen.shjXdhttp://git.ti.com/cgit/processor-sdk/pdk/tree/packages/ti/build/makerules/x509CertificateGen.sh#n513j]j]j]j]j]ujjj]rjX%build/makerules/x509CertificateGen.shrr}r(jUjj ubajjubjX (when building from linux).rr}r(jX (when building from linux).jjubeubj)r}r(jXValid values arerjj*jjjjj}r(j]j]j]j]j]ujMjhj]rjXValid values arerr}r(jjjjubaubjt)r}r (jUjj*jjjjwj}r!(jyX-j]j]j]j]j]ujMjhj]r"(j{)r#}r$(jX>0 : Disable all JTAG access (most secure and most restrictive)r%jjjjjjj}r&(j]j]j]j]j]ujNjhj]r'j)r(}r)(jj%jj#jjjjj}r*(j]j]j]j]j]ujMj]r+jX>0 : Disable all JTAG access (most secure and most restrictive)r,r-}r.(jj%jj(ubaubaubj{)r/}r0(jX:1 : Use device defaults (most secure and most restrictive)r1jjjjjjj}r2(j]j]j]j]j]ujNjhj]r3j)r4}r5(jj1jj/jjjjj}r6(j]j]j]j]j]ujMj]r7jX:1 : Use device defaults (most secure and most restrictive)r8r9}r:(jj1jj4ubaubaubj{)r;}r<(jXj2 : Allow debug of non-secure code, when the CPU is running in secure mode, JTAG connectivity will be lostr=jjjjjjj}r>(j]j]j]j]j]ujNjhj]r?j)r@}rA(jj=jj;jjjjj}rB(j]j]j]j]j]ujMj]rCjXj2 : Allow debug of non-secure code, when the CPU is running in secure mode, JTAG connectivity will be lostrDrE}rF(jj=jj@ubaubaubj{)rG}rH(jXo4 : Allow debug of both secure and non-secure code (least secure and least restrictive). This is the default. jjjjjjj}rI(j]j]j]j]j]ujNjhj]rJj)rK}rL(jXm4 : Allow debug of both secure and non-secure code (least secure and least restrictive). This is the default.rMjjGjjjjj}rN(j]j]j]j]j]ujMj]rOjXm4 : Allow debug of both secure and non-secure code (least secure and least restrictive). This is the default.rPrQ}rR(jjMjjKubaubaubeubj)rS}rT(jXjj*jjjjj}rU(UformatXhtmlj@jAj]j]j]j]j]ujMjhj]rVjXrWrX}rY(jUjjSubaubj)rZ}r[(jX".. _am655x-compiling-apps-for-sbl:jj*jjjj j}r\(j]j]j]j]j]jUam655x-compiling-apps-for-sblr]ujM'jhj]ubj)r^}r_(jX-**Compiling apps that can be loaded by SBL:**r`jj*jjj}rahvjZsjjj}rb(j]j]j]j]rcj]aj]rdhvaujMjhj"}rej]jZsj]rfj)rg}rh(jj`j}ri(j]j]j]j]j]ujj^j]rjjX)Compiling apps that can be loaded by SBL:rkrl}rm(jUjjgubajjubaubj)rn}ro(jX**Memory Map Considerations**rpjj*jjjjj}rq(j]j]j]j]j]ujMjhj]rrj)rs}rt(jjpj}ru(j]j]j]j]j]ujjnj]rvjXMemory Map Considerationsrwrx}ry(jUjjsubajjubaubj)rz}r{(jXApplications that the SBL loads must comply with the am655x-sbl-memory-usage_. In the application's linker command file, care must be taken to not use the first 0x100 bytes of any R5 MCU's ATCM memory and SBL reserved memory from 0x41C00100 to 0x41C3E000. If the applications are signed, no loadable sections must be placed in the SBL scratch memory area. The scratch memory can be used at application runtime for stacks, heaps, etc.jj*jjjjj}r|(j]j]j]j]j]ujMjhj]r}(jX5Applications that the SBL loads must comply with the r~r}r(jX5Applications that the SBL loads must comply with the jjzubj)r}r(jXam655x-sbl-memory-usage_jKjjzjjj}r(UnameXam655x-sbl-memory-usagerj]j]j]j]j]jj5uj]rjXam655x-sbl-memory-usagerr}r(jUjjubaubjXd. In the application's linker command file, care must be taken to not use the first 0x100 bytes of any R5 MCU's ATCM memory and SBL reserved memory from 0x41C00100 to 0x41C3E000. If the applications are signed, no loadable sections must be placed in the SBL scratch memory area. The scratch memory can be used at application runtime for stacks, heaps, etc.rr}r(jXd. In the application's linker command file, care must be taken to not use the first 0x100 bytes of any R5 MCU's ATCM memory and SBL reserved memory from 0x41C00100 to 0x41C3E000. If the applications are signed, no loadable sections must be placed in the SBL scratch memory area. The scratch memory can be used at application runtime for stacks, heaps, etc.jjzubeubj)r}r(jXh
jj*jjjjj}r(UformatXhtmlj@jAj]j]j]j]j]ujMjhj]rjXh
rr}r(jUjjubaubj)r}r(jX**NOTE**rjj*jjjjj}r(j]j]j]j]j]ujMjhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXNOTErr}r(jUjjubajjubaubjt)r}r(jUjj*jjjjwj}r(jyX-j]j]j]j]j]ujMjhj]rj{)r}r(jXThe local address 0x0 of the MPU is not accessible from the MCU, so any MPU linker command file must not specify any loadable sections in that memory region. The SBL will not be able to access that memory to load code or data. jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXThe local address 0x0 of the MPU is not accessible from the MCU, so any MPU linker command file must not specify any loadable sections in that memory region. The SBL will not be able to access that memory to load code or data.rjjjjjjj}r(j]j]j]j]j]ujMj]rjXThe local address 0x0 of the MPU is not accessible from the MCU, so any MPU linker command file must not specify any loadable sections in that memory region. The SBL will not be able to access that memory to load code or data.rr}r(jjjjubaubaubaubj)r}r(jX
jj*jjjjj}r(UformatXhtmlj@jAj]j]j]j]j]ujMjhj]rjX
rr}r(jUjjubaubj)r}r(jX4**Converting ELF executables to SBL loadable image**rjj*jjjjj}r(j]j]j]j]j]ujMjhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX0Converting ELF executables to SBL loadable imagerr}r(jUjjubajjubaubj)r¬}rì(jX~Depending on the usecase, an ELF application executable can be converted into an image that can be loaded by SBL in many ways.rĬjj*jjjjj}rŬ(j]j]j]j]j]ujMjhj]rƬjX~Depending on the usecase, an ELF application executable can be converted into an image that can be loaded by SBL in many ways.rǬrȬ}rɬ(jjĬjj¬ubaubjt)rʬ}rˬ(jUjj*jjjjwj}r̬(jyX-j]j]j]j]j]ujMjhj]rͬ(j{)rά}rϬ(jX**Using CCS**: Any project created using the pdkProjectCreate scripts will automatically generate a SBL loadable app, as part of a post-build step. jjʬjjjjj}rЬ(j]j]j]j]j]ujNjhj]rѬj)rҬ}rӬ(jX**Using CCS**: Any project created using the pdkProjectCreate scripts will automatically generate a SBL loadable app, as part of a post-build step.jjάjjjjj}rԬ(j]j]j]j]j]ujMj]rլ(j)r֬}r׬(jX **Using CCS**j}rج(j]j]j]j]j]ujjҬj]r٬jX Using CCSrڬr۬}rܬ(jUjj֬ubajjubjX: Any project created using the pdkProjectCreate scripts will automatically generate a SBL loadable app, as part of a post-build step.rݬrެ}r߬(jX: Any project created using the pdkProjectCreate scripts will automatically generate a SBL loadable app, as part of a post-build step.jjҬubeubaubj{)r}r(jXH**Using makefiles**: Add the following lines to the component's .mk filerjjʬjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujMj]r(j)r}r(jX**Using makefiles**j}r(j]j]j]j]j]ujjj]rjXUsing makefilesrr}r(jUjjubajjubjX5: Add the following lines to the component's .mk filerr}r(jX5: Add the following lines to the component's .mk filejjubeubaubeubj)r}r(jX>app_name_SBL_APPIMAGEGEN = yes export app_name_SBL_APPIMAGEGENjj*jjjjj}r(j@jAj]j]j]j]j]ujM'jhj]rjX>app_name_SBL_APPIMAGEGEN = yes export app_name_SBL_APPIMAGEGENrr}r(jUjjubaubjt)r}r(jUjj*jjjjwj}r(jyX-j]j]j]j]j]ujMjhj]rj{)r}r(jX>**Existing ELF executable**: By calling the K3ImageGen script.rjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujMj]r(j)r}r(jX**Existing ELF executable**j}r (j]j]j]j]j]ujjj]r jXExisting ELF executabler r }r (jUjjubajjubjX#: By calling the K3ImageGen script.rr}r(jX#: By calling the K3ImageGen script.jjubeubaubaubj)r}r(jXLinux Syntax: K3ImageGen.sh <.out> Example: cd /pdk_*/packages/ti/boot/sbl/example/ampMulticoreApp/binary/am65xx_evm/ K3ImageGen.sh 4 sbl_baremetal_boot_test_am65xx_evm_mcu1_0TestApp_release.xer5fjj*jjjjj}r(j@jAj]j]j]j]j]ujM'jhj]rjXLinux Syntax: K3ImageGen.sh <.out> Example: cd /pdk_*/packages/ti/boot/sbl/example/ampMulticoreApp/binary/am65xx_evm/ K3ImageGen.sh 4 sbl_baremetal_boot_test_am65xx_evm_mcu1_0TestApp_release.xer5frr}r(jUjjubaubj)r}r(jXWindows Syntax: K3ImageGen.bat " <.out>" Example: cd \pdk_*\packages\ti\boot\sbl\example\ampMulticoreApp\binary\am65xx_evm\ K3ImageGen.bat "4 sbl_baremetal_boot_test_am65xx_evm_mcu1_0TestApp_release.xer5f"jj*jjjjj}r(j@jAj]j]j]j]j]ujM'jhj]rjXWindows Syntax: K3ImageGen.bat " <.out>" Example: cd \pdk_*\packages\ti\boot\sbl\example\ampMulticoreApp\binary\am65xx_evm\ K3ImageGen.bat "4 sbl_baremetal_boot_test_am65xx_evm_mcu1_0TestApp_release.xer5f"rr}r(jUjjubaubjt)r}r (jUjj*jjjjwj}r!(jyX-j]j]j]j]j]ujM jhj]r"j{)r#}r$(jX**Multicore Images**: Multicore images, as the name suggests, allows the SBL to load applications for multiple cores from a single image. Creating such images invloves three steps.jjjjjjj}r%(j]j]j]j]j]ujNjhj]r&j)r'}r((jX**Multicore Images**: Multicore images, as the name suggests, allows the SBL to load applications for multiple cores from a single image. Creating such images invloves three steps.jj#jjjjj}r)(j]j]j]j]j]ujM j]r*(j)r+}r,(jX**Multicore Images**j}r-(j]j]j]j]j]ujj'j]r.jXMulticore Imagesr/r0}r1(jUjj+ubajjubjX: Multicore images, as the name suggests, allows the SBL to load applications for multiple cores from a single image. Creating such images invloves three steps.r2r3}r4(jX: Multicore images, as the name suggests, allows the SBL to load applications for multiple cores from a single image. Creating such images invloves three steps.jj'ubeubaubaubj )r5}r6(jUjj*jjjj j}r7(jU.j]j]j]jUj]j]jjujMjhj]r8(j{)r9}r:(jX=Generate the ELF application executables for individual coresr;jj5jjjjj}r<(j]j]j]j]j]ujNjhj]r=j)r>}r?(jj;jj9jjjjj}r@(j]j]j]j]j]ujMj]rAjX=Generate the ELF application executables for individual coresrBrC}rD(jj;jj>ubaubaubj{)rE}rF(jX:Convert the ELF executables into intermediate .rprc imagesrGjj5jjjjj}rH(j]j]j]j]j]ujNjhj]rIj)rJ}rK(jjGjjEjjjjj}rL(j]j]j]j]j]ujMj]rMjX:Convert the ELF executables into intermediate .rprc imagesrNrO}rP(jjGjjJubaubaubj{)rQ}rR(jXPCombine the .rprc images of individual cores to create a single multicore image jj5jjjjj}rS(j]j]j]j]j]ujNjhj]rTj)rU}rV(jXOCombine the .rprc images of individual cores to create a single multicore imagerWjjQjjjjj}rX(j]j]j]j]j]ujMj]rYjXOCombine the .rprc images of individual cores to create a single multicore imagerZr[}r\(jjWjjUubaubaubeubj)r]}r^(jXXTo covert any .out into the intermediate .rprc format, execute the following commands ::jj*jjjjj}r_(j]j]j]j]j]ujMjhj]r`jXUTo covert any .out into the intermediate .rprc format, execute the following commandsrarb}rc(jXUTo covert any .out into the intermediate .rprc format, execute the following commandsjj]ubaubj)rd}re(jX`For Linux: mono /packages/ti/boot/sbl/tools/out2rprc/bin/out2rprc.exe input.out output.rprcjj*jjjjj}rf(j@jAj]j]j]j]j]ujM'jhj]rgjX`For Linux: mono /packages/ti/boot/sbl/tools/out2rprc/bin/out2rprc.exe input.out output.rprcrhri}rj(jUjjdubaubj)rk}rl(jX]For Windows: \packages\ti\boot\sbl\tools\out2rprc\bin\out2rprc.exe input.out output.rprcjj*jjjjj}rm(j@jAj]j]j]j]j]ujM'jhj]rnjX]For Windows: \packages\ti\boot\sbl\tools\out2rprc\bin\out2rprc.exe input.out output.rprcrorp}rq(jUjjkubaubj)rr}rs(jXXTo stitch multiple .rprc images into a multicore image, execute the following command ::jj*jjjjj}rt(j]j]j]j]j]ujMjhj]rujXUTo stitch multiple .rprc images into a multicore image, execute the following commandrvrw}rx(jXUTo stitch multiple .rprc images into a multicore image, execute the following commandjjrubaubj)ry}rz(jXFor Linux: /packages/ti/boot/sbl/tools/multicoreImageGen/bin/MulticoreImageGen LE 55 output.appimage core_1.rprc core_2.rprcjj*jjjjj}r{(j@jAj]j]j]j]j]ujM'jhj]r|jXFor Linux: /packages/ti/boot/sbl/tools/multicoreImageGen/bin/MulticoreImageGen LE 55 output.appimage core_1.rprc core_2.rprcr}r~}r(jUjjyubaubj)r}r(jXFor Windows: /packages/ti/boot/sbl/tools/multicoreImageGen/bin/MulticoreImageGen.exe LE 55 output.appimage core_1.rprc core_2.rprcjj*jjjjj}r(j@jAj]j]j]j]j]ujM'jhj]rjXFor Windows: /packages/ti/boot/sbl/tools/multicoreImageGen/bin/MulticoreImageGen.exe LE 55 output.appimage core_1.rprc core_2.rprcrr}r(jUjjubaubj)r}r(jXh
jj*jjjjj}r(UformatXhtmlj@jAj]j]j]j]j]ujM)jhj]rjXh
rr}r(jUjjubaubj)r}r(jX**NOTE**rjj*jjjjj}r(j]j]j]j]j]ujM.jhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXNOTErr}r(jUjjubajjubaubjt)r}r(jUjj*jjjjwj}r(jyX-j]j]j]j]j]ujM0jhj]r(j{)r}r(jXZThe linux host environment needs to have `mono `__ installed.rjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujM0j]r(jX)The linux host environment needs to have rr}r(jX)The linux host environment needs to have jjubj)r}r(jX&`mono `__j}r(UnameXmonojXhttp://www.mono-project.comj]j]j]j]j]ujjj]rjXmonorr}r(jUjjubajjubjX installed.rr}r(jX installed.jjubeubaubj{)r}r(jXThe values used for the Core ID and Device ID can be found in `sbl/soc/k3/ sbl_slave_core_boot.h `__jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXThe values used for the Core ID and Device ID can be found in `sbl/soc/k3/ sbl_slave_core_boot.h `__jjjjjjj}r(j]j]j]j]j]ujM1j]r(jX>The values used for the Core ID and Device ID can be found in rr}r(jX>The values used for the Core ID and Device ID can be found in jjubj)r}r(jX`sbl/soc/k3/ sbl_slave_core_boot.h `__j}r(UnameX!sbl/soc/k3/ sbl_slave_core_boot.hjXdhttps://git.ti.com/cgit/processor-sdk/pdk/tree/packages/ti/boot/sbl/soc/k3/sbl_slave_core_boot.h#n51j]j]j]j]j]ujjj]r­jX!sbl/soc/k3/ sbl_slave_core_boot.hrírĭ}rŭ(jUjjubajjubeubaubj{)rƭ}rǭ(jXITo simply load an ELF without executing it, use CoreID value ONLY_LOAD_IDrȭjjjjjjj}rɭ(j]j]j]j]j]ujNjhj]rʭj)r˭}r̭(jjȭjjƭjjjjj}rͭ(j]j]j]j]j]ujM3j]rέjXITo simply load an ELF without executing it, use CoreID value ONLY_LOAD_IDrϭrЭ}rѭ(jjȭjj˭ubaubaubj{)rҭ}rӭ(jXUIf an image for MCU_1 core is provided, the SBL will attempt to switch to split mode.jjjjjjj}rԭ(j]j]j]j]j]ujNjhj]rխj)r֭}r׭(jXUIf an image for MCU_1 core is provided, the SBL will attempt to switch to split mode.rحjjҭjjjjj}r٭(j]j]j]j]j]ujM4j]rڭjXUIf an image for MCU_1 core is provided, the SBL will attempt to switch to split mode.rۭrܭ}rݭ(jjحjj֭ubaubaubj{)rޭ}r߭(jX^If only an image for MCU_0 is provided, the SBL will not change the mode of the MCU subsystem.jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX^If only an image for MCU_0 is provided, the SBL will not change the mode of the MCU subsystem.rjjޭjjjjj}r(j]j]j]j]j]ujM6j]rjX^If only an image for MCU_0 is provided, the SBL will not change the mode of the MCU subsystem.rr}r(jjjjubaubaubj{)r}r(jXPTo enable SMP on the MPU, ie, to get multiple MPUs execute from a single binary from the same address, use one of the following core_ids - MPU1_SMP_ID: The same app binary runs on both cores in MPU cluster 1 - MPU2_SMP_ID: The same app binary runs on both cores in MPU cluster 2 - MPU_SMP_ID: The same app binary runs all the MPUs jjjNjjj}r(j]j]j]j]j]ujNjhj]r(j)r}r(jXTo enable SMP on the MPU, ie, to get multiple MPUs execute from a single binary from the same address, use one of the following core_idsrjjjjjjj}r(j]j]j]j]j]ujM8j]rjXTo enable SMP on the MPU, ie, to get multiple MPUs execute from a single binary from the same address, use one of the following core_idsrr}r(jjjjubaubjt)r}r(jUj}r(jyX-j]j]j]j]j]ujjj]r(j{)r}r(jXDMPU1_SMP_ID: The same app binary runs on both cores in MPU cluster 1rj}r(j]j]j]j]j]ujjj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujM;j]rjXDMPU1_SMP_ID: The same app binary runs on both cores in MPU cluster 1rr}r(jjjjubaubajjubj{)r}r(jXDMPU2_SMP_ID: The same app binary runs on both cores in MPU cluster 2rj}r (j]j]j]j]j]ujjj]r j)r }r (jjjjjjjjj}r (j]j]j]j]j]ujM<j]rjXDMPU2_SMP_ID: The same app binary runs on both cores in MPU cluster 2rr}r(jjjj ubaubajjubj{)r}r(jX3MPU_SMP_ID: The same app binary runs all the MPUs j}r(j]j]j]j]j]ujjj]rj)r}r(jX2MPU_SMP_ID: The same app binary runs all the MPUsrjjjjjjj}r(j]j]j]j]j]ujM=j]rjX2MPU_SMP_ID: The same app binary runs all the MPUsrr}r(jjjjubaubajjubejjwubeubeubj)r}r(jX
jj*jjjjj}r (UformatXhtmlj@jAj]j]j]j]j]ujM?jhj]r!jX
r"r#}r$(jUjjubaubj)r%}r&(jX:**Converting ELF executables to executable binary images**r'jj*jjjjj}r((j]j]j]j]j]ujMDjhj]r)j)r*}r+(jj'j}r,(j]j]j]j]j]ujj%j]r-jX6Converting ELF executables to executable binary imagesr.r/}r0(jUjj*ubajjubaubj)r1}r2(jXSometimes, for exteremely constrained and specialized usecases like ultra-low-latency boot or DDR-less systems, an ELF application executable can be converted into a binary image that can executed directly from the boot media, without loading into internal memory.r3jj*jjjjj}r4(j]j]j]j]j]ujMFjhj]r5jXSometimes, for exteremely constrained and specialized usecases like ultra-low-latency boot or DDR-less systems, an ELF application executable can be converted into a binary image that can executed directly from the boot media, without loading into internal memory.r6r7}r8(jj3jj1ubaubj)r9}r:(jXAs internal memory is always accessible, this mode of execution allows some otherwise mandatory steps steps like DDR initlization or clock initialization to be done later or skipped altogether.r;jj*jjjjj}r<(j]j]j]j]j]ujMKjhj]r=jXAs internal memory is always accessible, this mode of execution allows some otherwise mandatory steps steps like DDR initlization or clock initialization to be done later or skipped altogether.r>r?}r@(jj;jj9ubaubj)rA}rB(jXHWorking with such highly contrained systems require some special steps..rCjj*jjjjj}rD(j]j]j]j]j]ujMOjhj]rEjXHWorking with such highly contrained systems require some special steps..rFrG}rH(jjCjjAubaubjt)rI}rJ(jUjj*jjjjwj}rK(jyX-j]j]j]j]j]ujMQjhj]rL(j{)rM}rN(jXAMake sure that the boot media supports eXecuting In Place (XIP). jjIjjjjj}rO(j]j]j]j]j]ujNjhj]rPj)rQ}rR(jX@Make sure that the boot media supports eXecuting In Place (XIP).rSjjMjjjjj}rT(j]j]j]j]j]ujMQj]rUjX@Make sure that the boot media supports eXecuting In Place (XIP).rVrW}rX(jjSjjQubaubaubj{)rY}rZ(jXiUse the custom SBL build to select the build options to build a SBL that meets the usecase requirements. jjIjjjjj}r[(j]j]j]j]j]ujNjhj]r\j)r]}r^(jXhUse the custom SBL build to select the build options to build a SBL that meets the usecase requirements.r_jjYjjjjj}r`(j]j]j]j]j]ujMSj]rajXhUse the custom SBL build to select the build options to build a SBL that meets the usecase requirements.rbrc}rd(jj_jj]ubaubaubj{)re}rf(jXIn the linker command file for the application, make sure that all the data sections, stacks, heaps and globals are in internal read/write memory jjIjjjjj}rg(j]j]j]j]j]ujNjhj]rhj)ri}rj(jXIn the linker command file for the application, make sure that all the data sections, stacks, heaps and globals are in internal read/write memoryrkjjejjjjj}rl(j]j]j]j]j]ujMVj]rmjXIn the linker command file for the application, make sure that all the data sections, stacks, heaps and globals are in internal read/write memoryrnro}rp(jjkjjiubaubaubj{)rq}rr(jXIn the linker command file for the application, make sure that there are no holes in the loadable sections. Such non-contiguous sections can drastically blow up the binary image size, when comapred to the ELF executable size. jjIjjjjj}rs(j]j]j]j]j]ujNjhj]rtj)ru}rv(jXIn the linker command file for the application, make sure that there are no holes in the loadable sections. Such non-contiguous sections can drastically blow up the binary image size, when comapred to the ELF executable size.rwjjqjjjjj}rx(j]j]j]j]j]ujMYj]ryjXIn the linker command file for the application, make sure that there are no holes in the loadable sections. Such non-contiguous sections can drastically blow up the binary image size, when comapred to the ELF executable size.rzr{}r|(jjwjjuubaubaubj{)r}}r~(jXzTo generate an executable binary image from the applications ELF file, add the following lines to the component's .mk filejjIjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXzTo generate an executable binary image from the applications ELF file, add the following lines to the component's .mk filerjj}jjjjj}r(j]j]j]j]j]ujM]j]rjXzTo generate an executable binary image from the applications ELF file, add the following lines to the component's .mk filerr}r(jjjjubaubaubeubj)r}r(jXFapp_name_SBL_APP_BINIMAGEGEN = yes export app_name_SBL_APP_BINIMAGEGENjj*jjjjj}r(j@jAj]j]j]j]j]ujM3(jhj]rjXFapp_name_SBL_APP_BINIMAGEGEN = yes export app_name_SBL_APP_BINIMAGEGENrr}r(jUjjubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rUtesting-the-sblraj]rhaujMfjhj]r(j)r}r(jXTesting the SBLrjjjjjjj}r(j]j]j]j]j]ujMfjhj]rjXTesting the SBLrr}r(jjjjubaubj)r}r(jX!SBL provides test applications to demonstrate booting the A53 and R5 cores in both symmetric/lock step & asymmetric/split-mode and other features. The multicore sample application prints a message on the UART for each core. The functionality the different tests exercises are listed below.rjjjjjjj}r(j]j]j]j]j]ujMhjhj]rjX!SBL provides test applications to demonstrate booting the A53 and R5 cores in both symmetric/lock step & asymmetric/split-mode and other features. The multicore sample application prints a message on the UART for each core. The functionality the different tests exercises are listed below.rr}r(jjjjubaubjt)r}r(jUjjjjjjwj}r(jyX-j]j]j]j]j]ujMmjhj]r(j{)r}r(jXsbl_*_boot_test_*_all_coresTestApp_release: A single multicore boot test case that boots each core in the SoC with a separate app. Also tests DDR loadingjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXsbl_*_boot_test_*_all_coresTestApp_release: A single multicore boot test case that boots each core in the SoC with a separate app. Also tests DDR loadingrjjjjjjj}r(j]j]j]j]j]ujMmj]rjXsbl_*_boot_test_*_all_coresTestApp_release: A single multicore boot test case that boots each core in the SoC with a separate app. Also tests DDR loadingrr}r(jjjjubaubaubj{)r}r(jXusbl_*_boot_test_*_xxxx_xTestApp_release.appimage: A simple testcase for booting core xxxx_x (eg. MCU1_0, MPU2_0 etc.)jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXusbl_*_boot_test_*_xxxx_xTestApp_release.appimage: A simple testcase for booting core xxxx_x (eg. MCU1_0, MPU2_0 etc.)rjjjjjjj}r(j]j]j]j]j]ujMoj]rjXusbl_*_boot_test_*_xxxx_xTestApp_release.appimage: A simple testcase for booting core xxxx_x (eg. MCU1_0, MPU2_0 etc.)rr}r®(jjjjubaubaubj{)rî}rĮ(jXsbl_*_smp_test_*_all_coresTestApp_release.appimage: A single SMP boot test case that boots MCUs in lock step. The MCU app then uses the SBL lib to boot all the MPUs in SMP mode, ie, all the MPUs execute a single binary from the same address.jjjjjjj}rŮ(j]j]j]j]j]ujNjhj]rƮj)rǮ}rȮ(jXsbl_*_smp_test_*_all_coresTestApp_release.appimage: A single SMP boot test case that boots MCUs in lock step. The MCU app then uses the SBL lib to boot all the MPUs in SMP mode, ie, all the MPUs execute a single binary from the same address.rɮjjîjjjjj}rʮ(j]j]j]j]j]ujMqj]rˮjXsbl_*_smp_test_*_all_coresTestApp_release.appimage: A single SMP boot test case that boots MCUs in lock step. The MCU app then uses the SBL lib to boot all the MPUs in SMP mode, ie, all the MPUs execute a single binary from the same address.r̮rͮ}rή(jjɮjjǮubaubaubj{)rϮ}rЮ(jXsbl_baremetal_boot_perf_*_mcu1_0TestApp_release.appimage: A single MCU1_0 test case that can be used to measure the effect of enabling/disabling the perf. tuning knobs in the SBL for OSPI boot. The size of the test case can be easily modified by changing the values of .space directives in `sbl/example/k3MulticoreApp/ sbl_boot_perf_r5.asm `__ to profile for different app image sizes.jjjjjjj}rѮ(j]j]j]j]j]ujNjhj]rҮj)rӮ}rԮ(jXsbl_baremetal_boot_perf_*_mcu1_0TestApp_release.appimage: A single MCU1_0 test case that can be used to measure the effect of enabling/disabling the perf. tuning knobs in the SBL for OSPI boot. The size of the test case can be easily modified by changing the values of .space directives in `sbl/example/k3MulticoreApp/ sbl_boot_perf_r5.asm `__ to profile for different app image sizes.jjϮjjjjj}rծ(j]j]j]j]j]ujMtj]r֮(jX"sbl_baremetal_boot_perf_*_mcu1_0TestApp_release.appimage: A single MCU1_0 test case that can be used to measure the effect of enabling/disabling the perf. tuning knobs in the SBL for OSPI boot. The size of the test case can be easily modified by changing the values of .space directives in r׮rخ}rٮ(jX"sbl_baremetal_boot_perf_*_mcu1_0TestApp_release.appimage: A single MCU1_0 test case that can be used to measure the effect of enabling/disabling the perf. tuning knobs in the SBL for OSPI boot. The size of the test case can be easily modified by changing the values of .space directives in jjӮubj)rڮ}rۮ(jX`sbl/example/k3MulticoreApp/ sbl_boot_perf_r5.asm `__j}rܮ(UnameX0sbl/example/k3MulticoreApp/ sbl_boot_perf_r5.asmjXrhttp://git.ti.com/cgit/processor-sdk/pdk/tree/packages/ti/boot/sbl/example/k3MulticoreApp/sbl_boot_perf_r5.asm#n42j]j]j]j]j]ujjӮj]rݮjX0sbl/example/k3MulticoreApp/ sbl_boot_perf_r5.asmrޮr߮}r(jUjjڮubajjubjX* to profile for different app image sizes.rr}r(jX* to profile for different app image sizes.jjӮubeubaubj{)r}r(jXmsbl_baremetal_boot_xip_test_*_mcu1_0TestApp_release.xer5f.bin: A testcase demonstrating booting an XIP application from OSPI flash. Please refer `sbl/build/ sbl_mcu0_boot_xip_test.mk `__ and `sbl/example/k3MulticoreApp/mcuXiplinker.lds `__ to see how to convert an existing application into an XIP application. The sbl_*_xip_entry_*.appimage works in tandem with sbl_*xip_test_*.xer5f.bin to transition the system from non-xip to xip boot, as the ROM, by default, does not support XIP from boot media. After programming the sbl and syfw, to program both sbl_*_xip_entry_*.appimage and sbl_*xip_test_*.xer5f.bin into OSPI flash, use the following uniflash commands jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXlsbl_baremetal_boot_xip_test_*_mcu1_0TestApp_release.xer5f.bin: A testcase demonstrating booting an XIP application from OSPI flash. Please refer `sbl/build/ sbl_mcu0_boot_xip_test.mk `__ and `sbl/example/k3MulticoreApp/mcuXiplinker.lds `__ to see how to convert an existing application into an XIP application. The sbl_*_xip_entry_*.appimage works in tandem with sbl_*xip_test_*.xer5f.bin to transition the system from non-xip to xip boot, as the ROM, by default, does not support XIP from boot media. After programming the sbl and syfw, to program both sbl_*_xip_entry_*.appimage and sbl_*xip_test_*.xer5f.bin into OSPI flash, use the following uniflash commandsjjjjjjj}r(j]j]j]j]j]ujMzj]r(jXsbl_baremetal_boot_xip_test_*_mcu1_0TestApp_release.xer5f.bin: A testcase demonstrating booting an XIP application from OSPI flash. Please refer rr}r(jXsbl_baremetal_boot_xip_test_*_mcu1_0TestApp_release.xer5f.bin: A testcase demonstrating booting an XIP application from OSPI flash. Please refer jjubj)r}r(jX`sbl/build/ sbl_mcu0_boot_xip_test.mk `__j}r(UnameX$sbl/build/ sbl_mcu0_boot_xip_test.mkjXchttps://git.ti.com/cgit/processor-sdk/pdk/tree/packages/ti/boot/sbl/build/sbl_mcu0_boot_xip_test.mkj]j]j]j]j]ujjj]rjX$sbl/build/ sbl_mcu0_boot_xip_test.mkrr}r(jUjjubajjubjX and rr}r(jX and jjubj)r}r(jX`sbl/example/k3MulticoreApp/mcuXiplinker.lds `__j}r(UnameX+sbl/example/k3MulticoreApp/mcuXiplinker.ldsjXkhttps://git.ti.com/cgit/processor-sdk/pdk/tree/packages/ti/boot/sbl/example/k3MulticoreApp/mcuXiplinker.ldsj]j]j]j]j]ujjj]rjX+sbl/example/k3MulticoreApp/mcuXiplinker.ldsrr}r(jUjjubajjubjX to see how to convert an existing application into an XIP application. The sbl_*_xip_entry_*.appimage works in tandem with sbl_*xip_test_*.xer5f.bin to transition the system from non-xip to xip boot, as the ROM, by default, does not support XIP from boot media. After programming the sbl and syfw, to program both sbl_*_xip_entry_*.appimage and sbl_*xip_test_*.xer5f.bin into OSPI flash, use the following uniflash commandsrr}r(jX to see how to convert an existing application into an XIP application. The sbl_*_xip_entry_*.appimage works in tandem with sbl_*xip_test_*.xer5f.bin to transition the system from non-xip to xip boot, as the ROM, by default, does not support XIP from boot media. After programming the sbl and syfw, to program both sbl_*_xip_entry_*.appimage and sbl_*xip_test_*.xer5f.bin into OSPI flash, use the following uniflash commandsjjubeubaubeubj)r}r(jXFor Windows: .\dslite.bat --mode processors -c COM9 -f \packages\ti\boot\sbl\example\k3MulticoreApp\binary\am65xx\sbl_baremetal_boot_xip_entry_am65xx_evm_mcu1_0TestApp_release.appimage -d 3 -o A0000 .\dslite.bat --mode processors -c COM9 -f \packages\ti\boot\sbl\example\k3MulticoreApp\binary\am65xx\sbl_baremetal_boot_xip_test_am65xx_evm_mcu1_0TestApp_release.xer5f.bin -d 3 -o E0000jjjjjjj}r(j@jAj]j]j]j]j]ujMY(jhj]rjXFor Windows: .\dslite.bat --mode processors -c COM9 -f \packages\ti\boot\sbl\example\k3MulticoreApp\binary\am65xx\sbl_baremetal_boot_xip_entry_am65xx_evm_mcu1_0TestApp_release.appimage -d 3 -o A0000 .\dslite.bat --mode processors -c COM9 -f \packages\ti\boot\sbl\example\k3MulticoreApp\binary\am65xx\sbl_baremetal_boot_xip_test_am65xx_evm_mcu1_0TestApp_release.xer5f.bin -d 3 -o E0000rr}r (jUjjubaubj)r }r (jXFor Linux: sudo ./dslite.sh --mode processors -c /dev/ttyUSB1 -f /packages/ti/boot/sbl/example/k3MulticoreApp/binary/am65xx/sbl_baremetal_boot_xip_entry_am65xx_evm_mcu1_0TestApp_release.appimage -d 3 -o A0000 sudo ./dslite.sh --mode processors -c /dev/ttyUSB1 -f /packages/ti/boot/sbl/example/k3MulticoreApp/binary/am65xx/sbl_baremetal_boot_xip_test_am65xx_evm_mcu1_0TestApp_release.xer5f.bin -d 3 -o E0000jjjjjjj}r (j@jAj]j]j]j]j]ujM`(jhj]r jXFor Linux: sudo ./dslite.sh --mode processors -c /dev/ttyUSB1 -f /packages/ti/boot/sbl/example/k3MulticoreApp/binary/am65xx/sbl_baremetal_boot_xip_entry_am65xx_evm_mcu1_0TestApp_release.appimage -d 3 -o A0000 sudo ./dslite.sh --mode processors -c /dev/ttyUSB1 -f /packages/ti/boot/sbl/example/k3MulticoreApp/binary/am65xx/sbl_baremetal_boot_xip_test_am65xx_evm_mcu1_0TestApp_release.xer5f.bin -d 3 -o E0000rr}r(jUjj ubaubj)r}r(jXHAn example test log for sbl_*_boot_test_*_all_coresTestApp_release is ::jjjjjjj}r(j]j]j]j]j]ujMjhj]rjXEAn example test log for sbl_*_boot_test_*_all_coresTestApp_release isrr}r(jXEAn example test log for sbl_*_boot_test_*_all_coresTestApp_release isjjubaubj)r}r(jXSYSFW ver xx.x.x-v20xx.xx (xxx xxx) running SBL Revision: xx.xx.xx.xx (MMM DD YYYY - HH:MM:SS) MPU1_0 running MPU1_1 running MPU2_0 running MPU2_1 running MCU1_1 running MCU1_0 running MCU1_0 reports: All tests have passedjjjjjjj}r(j@jAj]j]j]j]j]ujMi(jhj]rjXSYSFW ver xx.x.x-v20xx.xx (xxx xxx) running SBL Revision: xx.xx.xx.xx (MMM DD YYYY - HH:MM:SS) MPU1_0 running MPU1_1 running MPU2_0 running MPU2_1 running MCU1_1 running MCU1_0 running MCU1_0 reports: All tests have passedrr}r(jUjjubaubj)r}r (jXKAn example log for sbl_*_smp_test_*_all_coresTestApp_release.appimage is ::jjjjjjj}r!(j]j]j]j]j]ujMjhj]r"jXHAn example log for sbl_*_smp_test_*_all_coresTestApp_release.appimage isr#r$}r%(jXHAn example log for sbl_*_smp_test_*_all_coresTestApp_release.appimage isjjubaubj)r&}r'(jX{SYSFW ver xx.x.x-v20xx.xx (xxx xxx) running SBL Revision: xx.xx.xx.xx (MMM DD YYYY - HH:MM:SS) MPU SMP boot test Cores 0 & 1 will boot from 0x801007a0 Cores 2 & 3 will boot from 0x803007a0 Resetting all ARM cores now... No of Cortex-A core(s) running: 1 No of Cortex-A core(s) running: 2 No of Cortex-A core(s) running: 3 No of Cortex-A core(s) running: 4 All tests have passedjjjjjjj}r((j@jAj]j]j]j]j]ujMv(jhj]r)jX{SYSFW ver xx.x.x-v20xx.xx (xxx xxx) running SBL Revision: xx.xx.xx.xx (MMM DD YYYY - HH:MM:SS) MPU SMP boot test Cores 0 & 1 will boot from 0x801007a0 Cores 2 & 3 will boot from 0x803007a0 Resetting all ARM cores now... No of Cortex-A core(s) running: 1 No of Cortex-A core(s) running: 2 No of Cortex-A core(s) running: 3 No of Cortex-A core(s) running: 4 All tests have passedr*r+}r,(jUjj&ubaubj)r-}r.(jXuAn example log for sbl_baremetal_boot_perf_*_mcu1_0TestApp_release.appimage, when the best boot time is reached is ::jjjjjjj}r/(j]j]j]j]j]ujMjhj]r0jXrAn example log for sbl_baremetal_boot_perf_*_mcu1_0TestApp_release.appimage, when the best boot time is reached isr1r2}r3(jXrAn example log for sbl_baremetal_boot_perf_*_mcu1_0TestApp_release.appimage, when the best boot time is reached isjj-ubaubj)r4}r5(jXTime elapsed since start of SBL: 36665us fxn:boot_perf_test_main cycles: 14666041 Attempting board config ...BOARD_INIT_PLL ...passed BOARD_INIT_MODULE_CLOCK...passed BOARD_INIT_DDR...passed Analyzing run results .... Boot time is now optimized.... All tests have passed Profiling info .... MCU @ 400000000Hz. cycles per usec = 400 fxn: main line: 75 cycle: xxx timestamp: 432us . . . fxn: SBL_SlaveCoreBoot line: 231 cycle: xxx timestamp: 36149usjjjjjjj}r6(j@jAj]j]j]j]j]ujM(jhj]r7jXTime elapsed since start of SBL: 36665us fxn:boot_perf_test_main cycles: 14666041 Attempting board config ...BOARD_INIT_PLL ...passed BOARD_INIT_MODULE_CLOCK...passed BOARD_INIT_DDR...passed Analyzing run results .... Boot time is now optimized.... All tests have passed Profiling info .... MCU @ 400000000Hz. cycles per usec = 400 fxn: main line: 75 cycle: xxx timestamp: 432us . . . fxn: SBL_SlaveCoreBoot line: 231 cycle: xxx timestamp: 36149usr8r9}r:(jUjj4ubaubj)r;}r<(jX1The test log for sbl_*_xip_test_*.xer5f.bin is ::jjjjjjj}r=(j]j]j]j]j]ujMjhj]r>jX.The test log for sbl_*_xip_test_*.xer5f.bin isr?r@}rA(jX.The test log for sbl_*_xip_test_*.xer5f.bin isjj;ubaubj)rB}rC(jXMCU1_0 runningjjjjjjj}rD(j@jAj]j]j]j]j]ujM(jhj]rEjXMCU1_0 runningrFrG}rH(jUjjBubaubeubj)rI}rJ(jUjKjjjjjjj}rK(j]rLX boot modesrMaj]j]j]rNUid86rOaj]ujMjhj]rP(j)rQ}rR(jX Boot ModesrSjjIjjjjj}rT(j]j]j]j]j]ujMjhj]rUjX Boot ModesrVrW}rX(jjSjjQubaubj)rY}rZ(jXThe SBL supports MMCSD, OSPI, UART and Hyperflash Boot modes. The different boot modes supported for all the boards is tabulated below.r[jjIjjjjj}r\(j]j]j]j]j]ujMjhj]r]jXThe SBL supports MMCSD, OSPI, UART and Hyperflash Boot modes. The different boot modes supported for all the boards is tabulated below.r^r_}r`(jj[jjYubaubjy )ra}rb(jUjjIjjjj j}rc(j]j]j]j]j]ujNjhj]rdj~ )re}rf(jUj}rg(j]j]j]j]j]UcolsKujjaj]rh(j )ri}rj(jUj}rk(j]j]j]j]j]UcolwidthKujjej]jj ubj )rl}rm(jUj}rn(j]j]j]j]j]UcolwidthKujjej]jj ubj )ro}rp(jUj}rq(j]j]j]j]j]UcolwidthKujjej]jj ubj )rr}rs(jUj}rt(j]j]j]j]j]UcolwidthKujjej]jj ubj )ru}rv(jUj}rw(j]j]j]j]j]UcolwidthKujjej]jj ubj )rx}ry(jUj}rz(j]j]j]j]j]UcolwidthKujjej]jj ubj )r{}r|(jUj}r}(j]j]j]j]j]UcolwidthK ujjej]jj ubj )r~}r(jUj}r(j]j]j]j]j]ujjej]r(j )r}r(jUj}r(j]j]j]j]j]ujj~j]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXMMCSDrjjjjjjj}r(j]j]j]j]j]ujMj]rjXMMCSDrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXOSPIrjjjjjjj}r(j]j]j]j]j]ujMj]rjXOSPIrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXUARTrjjjjjjj}r(j]j]j]j]j]ujMj]rjXUARTrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXPCIerjjjjjjj}r(j]j]j]j]j]ujMj]rjXPCIerr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXETHrjjjjjjj}r(j]j]j]j]j]ujMj]rjXETHr¯rï}rį(jjjjubaubajj ubj )rů}rƯ(jUj}rǯ(j]j]j]j]j]ujjj]rȯj)rɯ}rʯ(jX HYPERFLASHr˯jjůjjjjj}r̯(j]j]j]j]j]ujMj]rͯjX HYPERFLASHrίrϯ}rЯ(jj˯jjɯubaubajj ubejj ubj )rѯ}rү(jUj}rӯ(j]j]j]j]j]ujj~j]rԯ(j )rկ}r֯(jUj}rׯ(j]j]j]j]j]ujjѯj]rدj)rٯ}rگ(jX AM65xx EVMrۯjjկjjjjj}rܯ(j]j]j]j]j]ujMj]rݯjX AM65xx EVMrޯr߯}r(jjۯjjٯubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjѯj]rj)r}r(jXYESrjjjjjjj}r(j]j]j]j]j]ujMj]rjXYESrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjѯj]rj)r}r(jXYESrjjjjjjj}r(j]j]j]j]j]ujMj]rjXYESrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjѯj]rj)r}r(jXYESrjjjjjjj}r(j]j]j]j]j]ujMj]rjXYESrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjѯj]rj)r }r (jXNOr jjjjjjj}r (j]j]j]j]j]ujMj]r jXNOrr}r(jj jj ubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjѯj]rj)r}r(jXNOrjjjjjjj}r(j]j]j]j]j]ujMj]rjXNOrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjѯj]r j)r!}r"(jXNOr#jjjjjjj}r$(j]j]j]j]j]ujMj]r%jXNOr&r'}r((jj#jj!ubaubajj ubejj ubj )r)}r*(jUj}r+(j]j]j]j]j]ujj~j]r,(j )r-}r.(jUj}r/(j]j]j]j]j]ujj)j]r0j)r1}r2(jX AM65xx IDKr3jj-jjjjj}r4(j]j]j]j]j]ujMj]r5jX AM65xx IDKr6r7}r8(jj3jj1ubaubajj ubj )r9}r:(jUj}r;(j]j]j]j]j]ujj)j]r<j)r=}r>(jXYESr?jj9jjjjj}r@(j]j]j]j]j]ujMj]rAjXYESrBrC}rD(jj?jj=ubaubajj ubj )rE}rF(jUj}rG(j]j]j]j]j]ujj)j]rHj)rI}rJ(jXYESrKjjEjjjjj}rL(j]j]j]j]j]ujMj]rMjXYESrNrO}rP(jjKjjIubaubajj ubj )rQ}rR(jUj}rS(j]j]j]j]j]ujj)j]rTj)rU}rV(jXYESrWjjQjjjjj}rX(j]j]j]j]j]ujMj]rYjXYESrZr[}r\(jjWjjUubaubajj ubj )r]}r^(jUj}r_(j]j]j]j]j]ujj)j]r`j)ra}rb(jXNOrcjj]jjjjj}rd(j]j]j]j]j]ujMj]rejXNOrfrg}rh(jjcjjaubaubajj ubj )ri}rj(jUj}rk(j]j]j]j]j]ujj)j]rlj)rm}rn(jXNOrojjijjjjj}rp(j]j]j]j]j]ujMj]rqjXNOrrrs}rt(jjojjmubaubajj ubj )ru}rv(jUj}rw(j]j]j]j]j]ujj)j]rxj)ry}rz(jXNOr{jjujjjjj}r|(j]j]j]j]j]ujMj]r}jXNOr~r}r(jj{jjyubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujj~j]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX J721E EVMrjjjjjjj}r(j]j]j]j]j]ujMj]rjX J721E EVMrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXYESrjjjjjjj}r(j]j]j]j]j]ujMj]rjXYESrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXYESrjjjjjjj}r(j]j]j]j]j]ujMj]rjXYESrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXYESrjjjjjjj}r(j]j]j]j]j]ujMj]rjXYESrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXNOrjjjjjjj}r(j]j]j]j]j]ujMj]rjXNOrr}r(jjjjubaubajj ubj )r}r°(jUj}rð(j]j]j]j]j]ujjj]rİj)rŰ}rư(jXNOrǰjjjjjjj}rȰ(j]j]j]j]j]ujMj]rɰjXNOrʰr˰}r̰(jjǰjjŰubaubajj ubj )rͰ}rΰ(jUj}rϰ(j]j]j]j]j]ujjj]rаj)rѰ}rҰ(jXYESrӰjjͰjjjjj}r԰(j]j]j]j]j]ujMj]rհjXYESrְrװ}rذ(jjӰjjѰubaubajj ubejj ubejj ubejj ubaubj)rٰ}rڰ(jX**Booting Via SD Card**r۰jjIjjjjj}rܰ(j]j]j]j]j]ujMjhj]rݰj)rް}r߰(jj۰j}r(j]j]j]j]j]ujjٰj]rjXBooting Via SD Cardrr}r(jUjjްubajjubaubj )r}r(jUjjIjjjj j}r(jU.j]j]j]jUj]j]jjujMjhj]r(j{)r}r(jXPreparing the SD card.rjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujMj]rjXPreparing the SD card.rr}r(jjjjubaubaubj{)r}r(jX#Booting the testcase from SD card. jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX"Booting the testcase from SD card.rjjjjjjj}r(j]j]j]j]j]ujMj]rjX"Booting the testcase from SD card.rr}r(jjjjubaubaubeubj)r}r(jX**Preparing the SD card**rjjIjjjjj}r(j]j]j]j]j]ujMjhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]r jXPreparing the SD cardr r }r (jUjjubajjubaubj )r }r(jUjjIjjjj j}r(jU.j]j]j]jUj]j]jjujMjhj]r(j{)r}r(jXJTo boot the target the SD card should be bootable. Follow the steps at `Creating bootable SD card in windows `__ or `Creating bootable SD card in Linux `__.jj jjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXJTo boot the target the SD card should be bootable. Follow the steps at `Creating bootable SD card in windows `__ or `Creating bootable SD card in Linux `__.jjjjjjj}r(j]j]j]j]j]ujMj]r(jXGTo boot the target the SD card should be bootable. Follow the steps at rr}r(jXGTo boot the target the SD card should be bootable. Follow the steps at jjubj)r}r(jX`Creating bootable SD card in windows `__j}r(UnameX$Creating bootable SD card in windowsjXZhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_Creating_a_SD_Card_with_Windowsj]j]j]j]j]ujjj]rjX$Creating bootable SD card in windowsr r!}r"(jUjjubajjubjX or r#r$}r%(jX or jjubj)r&}r'(jXy`Creating bootable SD card in Linux `__j}r((UnameX"Creating bootable SD card in LinuxjXPhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_create_SD_card_scriptj]j]j]j]j]ujjj]r)jX"Creating bootable SD card in Linuxr*r+}r,(jUjj&ubajjubjX.r-}r.(jX.jjubeubaubj{)r/}r0(jXTo update the SBL with a newer version, copy the sbl image (sbl_mmcsd_img_mcu1_0_release.tiimage) to the SD card. Rename it to **tiboot3.bin**jj jjjjj}r1(j]j]j]j]j]ujNjhj]r2j)r3}r4(jXTo update the SBL with a newer version, copy the sbl image (sbl_mmcsd_img_mcu1_0_release.tiimage) to the SD card. Rename it to **tiboot3.bin**jj/jjjjj}r5(j]j]j]j]j]ujMj]r6(jXTo update the SBL with a newer version, copy the sbl image (sbl_mmcsd_img_mcu1_0_release.tiimage) to the SD card. Rename it to r7r8}r9(jXTo update the SBL with a newer version, copy the sbl image (sbl_mmcsd_img_mcu1_0_release.tiimage) to the SD card. Rename it to jj3ubj)r:}r;(jX**tiboot3.bin**j}r<(j]j]j]j]j]ujj3j]r=jX tiboot3.binr>r?}r@(jUjj:ubajjubeubaubj{)rA}rB(jXdTo update the SYSFW with a newer version, copy the system firmware image (sysfw.bin) to the SD card.rCjj jjjjj}rD(j]j]j]j]j]ujNjhj]rEj)rF}rG(jjCjjAjjjjj}rH(j]j]j]j]j]ujMj]rIjXdTo update the SYSFW with a newer version, copy the system firmware image (sysfw.bin) to the SD card.rJrK}rL(jjCjjFubaubaubj{)rM}rN(jXWCopy the generated application image(\*.appimage) to the SD card. Rename it to **app** jj jjjjj}rO(j]j]j]j]j]ujNjhj]rPj)rQ}rR(jXVCopy the generated application image(\*.appimage) to the SD card. Rename it to **app**jjMjjjjj}rS(j]j]j]j]j]ujMj]rT(jXNCopy the generated application image(*.appimage) to the SD card. Rename it to rUrV}rW(jXOCopy the generated application image(\*.appimage) to the SD card. Rename it to jjQubj)rX}rY(jX**app**j}rZ(j]j]j]j]j]ujjQj]r[jXappr\r]}r^(jUjjXubajjubeubaubeubj)r_}r`(jX&**Booting the testcase from SD card**rajjIjjjjj}rb(j]j]j]j]j]ujMjhj]rcj)rd}re(jjaj}rf(j]j]j]j]j]ujj_j]rgjX"Booting the testcase from SD cardrhri}rj(jUjjdubajjubaubj )rk}rl(jUjjIjjjj j}rm(jU.j]j]j]jUj]j]jjujMjhj]rn(j{)ro}rp(jX2Insert SD card into the SD card slot of the board.rqjjkjjjjj}rr(j]j]j]j]j]ujNjhj]rsj)rt}ru(jjqjjojjjjj}rv(j]j]j]j]j]ujMj]rwjX2Insert SD card into the SD card slot of the board.rxry}rz(jjqjjtubaubaubj{)r{}r|(jXRefer Boot Modes section in the `AM6x EVM Hardware Users Guide `__ to setup EVM to boot from MMCSD.jjkjjjjj}r}(j]j]j]j]j]ujNjhj]r~j)r}r(jXRefer Boot Modes section in the `AM6x EVM Hardware Users Guide `__ to setup EVM to boot from MMCSD.jj{jjjjj}r(j]j]j]j]j]ujMj]r(jX Refer Boot Modes section in the rr}r(jX Refer Boot Modes section in the jjubj)r}r(jXE`AM6x EVM Hardware Users Guide `__j}r(UnameXAM6x EVM Hardware Users GuidejX!http://www.ti.com/lit/pdf/spruim7j]j]j]j]j]ujjj]rjXAM6x EVM Hardware Users Guiderr}r(jUjjubajjubjX" to setup EVM to boot from MMCSD.rr}r(jX" to setup EVM to boot from MMCSD.jjubeubaubj{)r}r(jXoOpen a serial communication terminal like TeraTerm, MiniCom on host PC and connect to the MCU UART console portjjkjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXoOpen a serial communication terminal like TeraTerm, MiniCom on host PC and connect to the MCU UART console portrjjjjjjj}r(j]j]j]j]j]ujMj]rjXoOpen a serial communication terminal like TeraTerm, MiniCom on host PC and connect to the MCU UART console portrr}r(jjjjubaubaubj{)r}r(jX?Power cycle the board to boot the application from the SD card.rjjkjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujMj]rjX?Power cycle the board to boot the application from the SD card.rr}r(jjjjubaubaubj{)r}r(jX0The test logs will be displayed on the MCU UART jjkjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX/The test logs will be displayed on the MCU UARTrjjjjjjj}r(j]j]j]j]j]ujMj]rjX/The test logs will be displayed on the MCU UARTrr}r(jjjjubaubaubeubj)r}r(jX**Booting Via OSPI flash**rjjIjjjjj}r(j]j]j]j]j]ujMjhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXBooting Via OSPI flashrr}r(jUjjubajjubaubj )r}r(jUjjIjjjj j}r±(jU.j]j]j]jUj]j]jjujMjhj]rñ(j{)rı}rű(jX|`Programming the OSPI flash `__rƱjjjjjjj}rDZ(j]j]j]j]j]ujNjhj]rȱj)rɱ}rʱ(jjƱjjıjjjjj}r˱(j]j]j]j]j]ujMj]ṟj)rͱ}rα(jjƱj}rϱ(UnameXProgramming the OSPI flashjX[http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_board.html#uniflashj]j]j]j]j]ujjɱj]rбjXProgramming the OSPI flashrѱrұ}rӱ(jUjjͱubajjubaubaubj{)rԱ}rձ(jX&Booting the testcase from OSPI flash jjjjjjj}rֱ(j]j]j]j]j]ujNjhj]rױj)rر}rٱ(jX$Booting the testcase from OSPI flashrڱjjԱjjjjj}r۱(j]j]j]j]j]ujMj]rܱjX$Booting the testcase from OSPI flashrݱrޱ}r߱(jjڱjjرubaubaubeubj)r}r(jX(**Booting the testcase from OSPI flash**rjjIjjjjj}r(j]j]j]j]j]ujMjhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX$Booting the testcase from OSPI flashrr}r(jUjjubajjubaubj )r}r(jUjjIjjjj j}r(jU.j]j]j]jUj]j]jjujMjhj]r(j{)r}r(jXRefer Boot Modes section in the `AM6x EVM Hardware Users Guide `__ to setup EVM to boot from OSPI.jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXRefer Boot Modes section in the `AM6x EVM Hardware Users Guide `__ to setup EVM to boot from OSPI.jjjjjjj}r(j]j]j]j]j]ujMj]r(jX Refer Boot Modes section in the rr}r(jX Refer Boot Modes section in the jjubj)r}r(jXE`AM6x EVM Hardware Users Guide `__j}r(UnameXAM6x EVM Hardware Users GuidejX!http://www.ti.com/lit/pdf/spruim7j]j]j]j]j]ujjj]rjXAM6x EVM Hardware Users Guiderr}r(jUjjubajjubjX! to setup EVM to boot from OSPI.rr}r(jX! to setup EVM to boot from OSPI.jjubeubaubj{)r}r(jXoOpen a serial communication terminal like TeraTerm, MiniCom on host PC and connect to the MCU UART console portjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r }r (jXoOpen a serial communication terminal like TeraTerm, MiniCom on host PC and connect to the MCU UART console portr jjjjjjj}r (j]j]j]j]j]ujMj]r jXoOpen a serial communication terminal like TeraTerm, MiniCom on host PC and connect to the MCU UART console portrr}r(jj jj ubaubaubj{)r}r(jXCPower cycle the board to boot the application from the OSPI flash.rjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujMj]rjXCPower cycle the board to boot the application from the OSPI flash.rr}r(jjjjubaubaubj{)r}r(jX1The test logs will be displayed on the MCU UART jjjjjjj}r(j]j]j]j]j]ujNjhj]r j)r!}r"(jX/The test logs will be displayed on the MCU UARTr#jjjjjjj}r$(j]j]j]j]j]ujMj]r%jX/The test logs will be displayed on the MCU UARTr&r'}r((jj#jj!ubaubaubeubj)r)}r*(jX"**Booting the testcase from UART**r+jjIjjjjj}r,(j]j]j]j]j]ujM jhj]r-j)r.}r/(jj+j}r0(j]j]j]j]j]ujj)j]r1jXBooting the testcase from UARTr2r3}r4(jUjj.ubajjubaubj )r5}r6(jUjjIjjjj j}r7(jU.j]j]j]jUj]j]jjujM jhj]r8(j{)r9}r:(jXRefer Boot Modes section in the `AM6x EVM Hardware Users Guide `__ to setup EVM to boot from UART.jj5jjjjj}r;(j]j]j]j]j]ujNjhj]r<j)r=}r>(jXRefer Boot Modes section in the `AM6x EVM Hardware Users Guide `__ to setup EVM to boot from UART.jj9jjjjj}r?(j]j]j]j]j]ujM j]r@(jX Refer Boot Modes section in the rArB}rC(jX Refer Boot Modes section in the jj=ubj)rD}rE(jXE`AM6x EVM Hardware Users Guide `__j}rF(UnameXAM6x EVM Hardware Users GuidejX!http://www.ti.com/lit/pdf/spruim7j]j]j]j]j]ujj=j]rGjXAM6x EVM Hardware Users GuiderHrI}rJ(jUjjDubajjubjX! to setup EVM to boot from UART.rKrL}rM(jX! to setup EVM to boot from UART.jj=ubeubaubj{)rN}rO(jXoOpen a serial communication terminal like TeraTerm, MiniCom on host PC and connect to the MCU UART console portjj5jjjjj}rP(j]j]j]j]j]ujNjhj]rQj)rR}rS(jXoOpen a serial communication terminal like TeraTerm, MiniCom on host PC and connect to the MCU UART console portrTjjNjjjjj}rU(j]j]j]j]j]ujM j]rVjXoOpen a serial communication terminal like TeraTerm, MiniCom on host PC and connect to the MCU UART console portrWrX}rY(jjTjjRubaubaubj{)rZ}r[(jXNPower cycle the board, the console should show a sequence of CCC being printedr\jj5jjjjj}r](j]j]j]j]j]ujNjhj]r^j)r_}r`(jj\jjZjjjjj}ra(j]j]j]j]j]ujMj]rbjXNPower cycle the board, the console should show a sequence of CCC being printedrcrd}re(jj\jj_ubaubaubj{)rf}rg(jXChoose the X-Modem interface and send the SBL that was built for UART. After the transfer is completed, repeat the same step for sysfw.bin and the application. You will see notifications to perform these actions. jj5jjjjj}rh(j]j]j]j]j]ujNjhj]rij)rj}rk(jXChoose the X-Modem interface and send the SBL that was built for UART. After the transfer is completed, repeat the same step for sysfw.bin and the application. You will see notifications to perform these actions.rljjfjjjjj}rm(j]j]j]j]j]ujMj]rnjXChoose the X-Modem interface and send the SBL that was built for UART. After the transfer is completed, repeat the same step for sysfw.bin and the application. You will see notifications to perform these actions.rorp}rq(jjljjjubaubaubeubj)rr}rs(jXIf sysfw.bin is not present in the boot media, the boot will fail without displaying any logs on the MCU UART. SBL enables UART logging only after successfully starting the system firmware image. If the system firmware load fails, the RBL will eventually reset the system.jjIjjjjj}rt(j]j]j]j]j]ujNjhj]ruj)rv}rw(jXIf sysfw.bin is not present in the boot media, the boot will fail without displaying any logs on the MCU UART. SBL enables UART logging only after successfully starting the system firmware image. If the system firmware load fails, the RBL will eventually reset the system.rxjjrjjjjj}ry(j]j]j]j]j]ujMj]rzjXIf sysfw.bin is not present in the boot media, the boot will fail without displaying any logs on the MCU UART. SBL enables UART logging only after successfully starting the system firmware image. If the system firmware load fails, the RBL will eventually reset the system.r{r|}r}(jjxjjvubaubaubj)r~}r(jX**Booting Via Hyperflash**rjjIjjjjj}r(j]j]j]j]j]ujMjhj]rj)r}r(jjj}r(j]j]j]j]j]ujj~j]rjXBooting Via Hyperflashrr}r(jUjjubajjubaubj )r}r(jUjjIjjjj j}r(jU.j]j]j]jUj]j]jjujMjhj]r(j{)r}r(jX|`Programming the Hyperflash `__rjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujMj]rj)r}r(jjj}r(UnameXProgramming the HyperflashjX[http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_board.html#uniflashj]j]j]j]j]ujjj]rjXProgramming the Hyperflashrr}r(jUjjubajjubaubaubj{)r}r(jX+Booting the testcase from Hyperflashflash jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX)Booting the testcase from Hyperflashflashrjjjjjjj}r(j]j]j]j]j]ujMj]rjX)Booting the testcase from Hyperflashflashrr}r(jjjjubaubaubeubj)r}r(jX(**Booting the testcase from Hyperflash**rjjIjjjjj}r(j]j]j]j]j]ujMjhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX$Booting the testcase from Hyperflashrr}r(jUjjubajjubaubj )r}r(jUjjIjjjj j}r(jU.j]j]j]jUj]j]jjujM!jhj]r(j{)r}r(jXRefer Boot Modes section in the `J721E EVM Hardware Users Guide `__ to setup EVM to boot from Hyperflash.jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXRefer Boot Modes section in the `J721E EVM Hardware Users Guide `__ to setup EVM to boot from Hyperflash.jjjjjjj}r(j]j]j]j]j]ujM!j]r(jX Refer Boot Modes section in the r²rò}rIJ(jX Refer Boot Modes section in the jjubj)rŲ}rƲ(jX|`J721E EVM Hardware Users Guide `__j}rDz(UnameXJ721E EVM Hardware Users GuidejXWhttps://cdds.ext.ti.com/ematrix/common/emxNavigator.jsp?objectId=28670.42872.4850.38306j]j]j]j]j]ujjj]rȲjXJ721E EVM Hardware Users Guiderɲrʲ}r˲(jUjjŲubajjubjX& to setup EVM to boot from Hyperflash.r̲rͲ}rβ(jX& to setup EVM to boot from Hyperflash.jjubeubaubj{)rϲ}rв(jXoOpen a serial communication terminal like TeraTerm, MiniCom on host PC and connect to the MCU UART console portjjjjjjj}rѲ(j]j]j]j]j]ujNjhj]rҲj)rӲ}rԲ(jXoOpen a serial communication terminal like TeraTerm, MiniCom on host PC and connect to the MCU UART console portrղjjϲjjjjj}rֲ(j]j]j]j]j]ujM$j]rײjXoOpen a serial communication terminal like TeraTerm, MiniCom on host PC and connect to the MCU UART console portrزrٲ}rڲ(jjղjjӲubaubaubj{)r۲}rܲ(jXCPower cycle the board to boot the application from the Hyperflash.rݲjjjjjjj}r޲(j]j]j]j]j]ujNjhj]r߲j)r}r(jjݲjj۲jjjjj}r(j]j]j]j]j]ujM&j]rjXCPower cycle the board to boot the application from the Hyperflash.rr}r(jjݲjjubaubaubj{)r}r(jX1The test logs will be displayed on the MCU UART jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX/The test logs will be displayed on the MCU UARTrjjjjjjj}r(j]j]j]j]j]ujM'j]rjX/The test logs will be displayed on the MCU UARTrr}r(jjjjubaubaubeubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rUevm-setup-for-testing-sblraj]rh>aujM+jhj]r(j)r}r(jXEVM Setup for testing SBLrjjjjjjj}r(j]j]j]j]j]ujM+jhj]rjXEVM Setup for testing SBLrr}r(jjjjubaubj)r}r(jXFor information on board specific requirements like power supply, UART console port connections refer the Hardware User guide of the respective boards.rjjjjjjj}r(j]j]j]j]j]ujM-jhj]rjXFor information on board specific requirements like power supply, UART console port connections refer the Hardware User guide of the respective boards.rr}r (jjjjubaubj)r }r (jXThe configurations needed to setup UART console through a serial terminal application on host PC are listed in the next section.r jjjjjjj}r (j]j]j]j]j]ujM0jhj]rjXThe configurations needed to setup UART console through a serial terminal application on host PC are listed in the next section.rr}r(jj jj ubaubj)r}r(jX**UART Console Setup**rjjjjjjj}r(j]j]j]j]j]ujM3jhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXUART Console Setuprr}r(jUjjubajjubaubj)r}r(jXPDK SBL prints messages on the UART Serial Console running on the host. Hence, a serial terminal application (like Tera Term/HyperTerminal/minicom) should be running on the host.r jjjjjjj}r!(j]j]j]j]j]ujM5jhj]r"jXPDK SBL prints messages on the UART Serial Console running on the host. Hence, a serial terminal application (like Tera Term/HyperTerminal/minicom) should be running on the host.r#r$}r%(jj jjubaubjt)r&}r'(jUjjjjjjwj}r((jyX-j]j]j]j]j]ujM9jhj]r)(j{)r*}r+(jXeThe host serial port must be configured at 115200 baud, no parity, 1 stop bit and no flow control.jj&jjjjj}r,(j]j]j]j]j]ujNjhj]r-j)r.}r/(jXeThe host serial port must be configured at 115200 baud, no parity, 1 stop bit and no flow control.r0jj*jjjjj}r1(j]j]j]j]j]ujM9j]r2jXeThe host serial port must be configured at 115200 baud, no parity, 1 stop bit and no flow control.r3r4}r5(jj0jj.ubaubaubj{)r6}r7(jXJPlease ensure that the local echo setting for the terminal is turned off.r8jj&jjjjj}r9(j]j]j]j]j]ujNjhj]r:j)r;}r<(jj8jj6jjjjj}r=(j]j]j]j]j]ujM;j]r>jXJPlease ensure that the local echo setting for the terminal is turned off.r?r@}rA(jj8jj;ubaubaubj{)rB}rC(jXAll SBL prints are routed to the `MCU UART `__rDjj&jjjjj}rE(j]j]j]j]j]ujNjhj]rFj)rG}rH(jjDjjBjjjjj}rI(j]j]j]j]j]ujM<j]rJ(jX!All SBL prints are routed to the rKrL}rM(jX!All SBL prints are routed to the jjGubj)rN}rO(jXy`MCU UART `__j}rP(UnameXMCU UARTjXjhttp://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_how_to_guides.html#uart-connectionj]j]j]j]j]ujjGj]rQjXMCU UARTrRrS}rT(jUjjNubajjubeubaubj{)rU}rV(jXTo verify setup is correct, setup the EVM to boot from UART as the Primary Boot Device(refer `AM6x EVM Hardware Users Guide `__. Power cycle the EVM, and look for the string CCCCCCC on the UART. jj&jXqinternal padding after source/rtos/PDK_Platform_Software/Boot_Board_and_EVM_Abstractions/BOOT_AM65x_J721E.rst.incrWjjj}rX(j]j]j]j]j]ujNjhj]rYj)rZ}r[(jXTo verify setup is correct, setup the EVM to boot from UART as the Primary Boot Device(refer `AM6x EVM Hardware Users Guide `__. Power cycle the EVM, and look for the string CCCCCCC on the UART.jjUjjjjj}r\(j]j]j]j]j]ujM=j]r](jX^To verify setup is correct, setup the EVM to boot from UART as the Primary Boot Device(refer r^r_}r`(jX^To verify setup is correct, setup the EVM to boot from UART as the Primary Boot Device(refer jjZubj)ra}rb(jXE`AM6x EVM Hardware Users Guide `__j}rc(UnameXAM6x EVM Hardware Users GuidejX!http://www.ti.com/lit/pdf/spruim7j]j]j]j]j]ujjZj]rdjXAM6x EVM Hardware Users Guidererf}rg(jUjjaubajjubjXC. Power cycle the EVM, and look for the string CCCCCCC on the UART.rhri}rj(jXC. Power cycle the EVM, and look for the string CCCCCCC on the UART.jjZubeubaubeubeubeubj)rk}rl(jUjj;jjjjj}rm(j]j]j]j]rnUc66xroaj]rphaujKWjhj]rq(j)rr}rs(jXC66xrtjjkjjjjj}ru(j]j]j]j]j]ujKWjhj]rvjXC66xrwrx}ry(jjtjjrubaubj7)rz}r{(jXDhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_BOOT_C66xjjkjj:XSsource/rtos/PDK_Platform_Software/Boot_Board_and_EVM_Abstractions/BOOT_C66x.rst.incr|r}}r~bjj>j}r(j@jAj]j]j]j]j]ujKjhj]rjXDhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_BOOT_C66xrr}r(jUjjzubaubj)r}r(jUjKjjkjj}jjj}r(j]rXoverviewraj]j]j]rUid87raj]ujKjhj]r(j)r}r(jXOverviewrjjjj}jjj}r(j]j]j]j]j]ujKjhj]rjXOverviewrr}r(jjjjubaubj)r}r(jXC66x SOCs use the Intermediate Boot-Loader (IBL) to initialize and setup the SOC for specific boot modes. The table below illustrates the supported bootmodes:rjjjj}jjj}r(j]j]j]j]j]ujKjhj]rjXC66x SOCs use the Intermediate Boot-Loader (IBL) to initialize and setup the SOC for specific boot modes. The table below illustrates the supported bootmodes:rr}r(jjjjubaubjy )r}r(jUjjjj}jj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujjj]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthK&ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthK ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthK ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX Boot Moderjjjj}jjj}r(j]j]j]j]j]ujK j]rjX Boot Moderr}r(jjjjubaubajj ubj )r}r³(jUj}ró(j]j]j]j]j]ujjj]rijj)rų}rƳ(jX TMDSEVM6678rdzjjjj}jjj}rȳ(j]j]j]j]j]ujK j]rɳjX TMDSEVM6678rʳr˳}r̳(jjdzjjųubaubajj ubj )rͳ}rγ(jUj}rϳ(j]j]j]j]j]ujjj]rгj)rѳ}rҳ(jX TMDXEVM6657rӳjjͳjj}jjj}rԳ(j]j]j]j]j]ujK j]rճjX TMDXEVM6657rֳr׳}rس(jjӳjjѳubaubajj ubejj ubajj ubj )rٳ}rڳ(jUj}r۳(j]j]j]j]j]ujjj]rܳ(j )rݳ}r޳(jUj}r߳(j]j]j]j]j]ujjٳj]r(j )r}r(jUj}r(j]j]j]j]j]ujjݳj]rj)r}r(jX#NOR boot via IBL over I2C\ :sup:`1`jjjj}jjj}r(j]j]j]j]j]ujK j]r(jXNOR boot via IBL over I2Crr}r(jXNOR boot via IBL over I2C\ jjubcdocutils.nodes superscript r)r}r(jX:sup:`1`j}r(j]j]j]j]j]ujjj]rjX1r}r(jUjjubajU superscriptrubeubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjݳj]rj)r}r(jXYesrjjjj}jjj}r(j]j]j]j]j]ujK j]rjXYesrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjݳj]rj)r}r(jXYesrjjjj}jjj}r(j]j]j]j]j]ujK j]rjXYesr r }r (jjjjubaubajj ubejj ubj )r }r (jUj}r(j]j]j]j]j]ujjٳj]r(j )r}r(jUj}r(j]j]j]j]j]ujj j]rj)r}r(jX$NAND boot via IBL over I2C\ :sup:`1`jjjj}jjj}r(j]j]j]j]j]ujKj]r(jXNAND boot via IBL over I2Crr}r(jXNAND boot via IBL over I2C\ jjubj)r}r(jX:sup:`1`j}r(j]j]j]j]j]ujjj]rjX1r}r (jUjjubajjubeubajj ubj )r!}r"(jUj}r#(j]j]j]j]j]ujj j]r$j)r%}r&(jXYesr'jj!jj}jjj}r((j]j]j]j]j]ujKj]r)jXYesr*r+}r,(jj'jj%ubaubajj ubj )r-}r.(jUj}r/(j]j]j]j]j]ujj j]r0j)r1}r2(jXYesr3jj-jj}jjj}r4(j]j]j]j]j]ujKj]r5jXYesr6r7}r8(jj3jj1ubaubajj ubejj ubj )r9}r:(jUj}r;(j]j]j]j]j]ujjٳj]r<(j )r=}r>(jUj}r?(j]j]j]j]j]ujj9j]r@j)rA}rB(jX$TFTP boot via IBL over I2C\ :sup:`1`jj=jj}jjj}rC(j]j]j]j]j]ujKj]rD(jXTFTP boot via IBL over I2CrErF}rG(jXTFTP boot via IBL over I2C\ jjAubj)rH}rI(jX:sup:`1`j}rJ(j]j]j]j]j]ujjAj]rKjX1rL}rM(jUjjHubajjubeubajj ubj )rN}rO(jUj}rP(j]j]j]j]j]ujj9j]rQj)rR}rS(jXYesrTjjNjj}jjj}rU(j]j]j]j]j]ujKj]rVjXYesrWrX}rY(jjTjjRubaubajj ubj )rZ}r[(jUj}r\(j]j]j]j]j]ujj9j]r]j)r^}r_(jXYesr`jjZjj}jjj}ra(j]j]j]j]j]ujKj]rbjXYesrcrd}re(jj`jj^ubaubajj ubejj ubj )rf}rg(jUj}rh(j]j]j]j]j]ujjٳj]ri(j )rj}rk(jUj}rl(j]j]j]j]j]ujjfj]rmj)rn}ro(jXI2C POST boot\ :sup:`2`jjjjj}jjj}rp(j]j]j]j]j]ujKj]rq(jX I2C POST bootrrrs}rt(jXI2C POST boot\ jjnubj)ru}rv(jX:sup:`2`j}rw(j]j]j]j]j]ujjnj]rxjX2ry}rz(jUjjuubajjubeubajj ubj )r{}r|(jUj}r}(j]j]j]j]j]ujjfj]r~j)r}r(jXYesrjj{jj}jjj}r(j]j]j]j]j]ujKj]rjXYesrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjfj]rj)r}r(jXYesrjjjj}jjj}r(j]j]j]j]j]ujKj]rjXYesrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjٳj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX Ethernet bootrjjjj}jjj}r(j]j]j]j]j]ujKj]rjX Ethernet bootrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXYesrjjjj}jjj}r(j]j]j]j]j]ujKj]rjXYesrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXYesrjjjj}jjj}r(j]j]j]j]j]ujKj]rjXYesrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjٳj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]r´j)rô}rĴ(jX SRIO bootrŴjjjj}jjj}rƴ(j]j]j]j]j]ujKj]rǴjX SRIO bootrȴrɴ}rʴ(jjŴjjôubaubajj ubj )r˴}r̴(jUj}rʹ(j]j]j]j]j]ujjj]rδj)rϴ}rд(jXYesrѴjj˴jj}jjj}rҴ(j]j]j]j]j]ujKj]rӴjXYesrԴrմ}rִ(jjѴjjϴubaubajj ubj )r״}rش(jUj}rٴ(j]j]j]j]j]ujjj]rڴj)r۴}rܴ(jXYesrݴjj״jj}jjj}r޴(j]j]j]j]j]ujKj]rߴjXYesrr}r(jjݴjj۴ubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjٳj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX PCIe bootrjjjj}jjj}r(j]j]j]j]j]ujKj]rjX PCIe bootrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXYesrjjjj}jjj}r(j]j]j]j]j]ujKj]rjXYesrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXYesrjjjj}jjj}r(j]j]j]j]j]ujKj]rjXYesrr }r (jjjjubaubajj ubejj ubejj ubejj ubaubj)r }r (jX_#. Support boot over I2C bus address 0x51 #. Support POST boot over I2C bus address 0x50 #. Only ELF and BBLOB images are supported for booting #. IBL is using the first 128KB L2 local memory, any application booting from IBL should NOT use the first 128KB L2 memory, OR should only use the first 128KB L2 memory for uninitialized data sectionjjjNjjj}r (j]j]j]j]j]ujNjhj]rj )r}r(jUj}r(jU.j]j]j]jUj]j]jjujj j]r(j{)r}r(jX&Support boot over I2C bus address 0x51rj}r(j]j]j]j]j]ujjj]rj)r}r(jjjjjj}jjj}r(j]j]j]j]j]ujKj]rjX&Support boot over I2C bus address 0x51rr}r(jjjjubaubajjubj{)r}r (jX,Support POST boot over I2C bus address 0x50r!j}r"(j]j]j]j]j]ujjj]r#j)r$}r%(jj!jjjj}jjj}r&(j]j]j]j]j]ujKj]r'jX,Support POST boot over I2C bus address 0x50r(r)}r*(jj!jj$ubaubajjubj{)r+}r,(jX4Only ELF and BBLOB images are supported for bootingr-j}r.(j]j]j]j]j]ujjj]r/j)r0}r1(jj-jj+jj}jjj}r2(j]j]j]j]j]ujKj]r3jX4Only ELF and BBLOB images are supported for bootingr4r5}r6(jj-jj0ubaubajjubj{)r7}r8(jXIBL is using the first 128KB L2 local memory, any application booting from IBL should NOT use the first 128KB L2 memory, OR should only use the first 128KB L2 memory for uninitialized data sectionj}r9(j]j]j]j]j]ujjj]r:j)r;}r<(jXIBL is using the first 128KB L2 local memory, any application booting from IBL should NOT use the first 128KB L2 memory, OR should only use the first 128KB L2 memory for uninitialized data sectionr=jj7jj}jjj}r>(j]j]j]j]j]ujK j]r?jXIBL is using the first 128KB L2 local memory, any application booting from IBL should NOT use the first 128KB L2 memory, OR should only use the first 128KB L2 memory for uninitialized data sectionr@rA}rB(jj=jj;ubaubajjubejj ubaubj)rC}rD(jX_Please refer to the boot mode dip switch settings for different boot modes on `TMDSEVM6678L_EVM `__, and `TMDSEVM6657L_EVM `__ that IBL supports.jjjj}jjj}rE(j]j]j]j]j]ujK$jhj]rF(jXNPlease refer to the boot mode dip switch settings for different boot modes on rGrH}rI(jXNPlease refer to the boot mode dip switch settings for different boot modes on jjCubj)rJ}rK(jX|`TMDSEVM6678L_EVM `__j}rL(UnameXTMDSEVM6678L_EVMjXehttp://processors.wiki.ti.com/index.php/TMDXEVM6678L_EVM_Hardware_Setup#Boot_Mode_Dip_Switch_Settingsj]j]j]j]j]ujjCj]rMjXTMDSEVM6678L_EVMrNrO}rP(jUjjJubajjubjX, and rQrR}rS(jX, and jjCubj)rT}rU(jX|`TMDSEVM6657L_EVM `__j}rV(UnameXTMDSEVM6657L_EVMjXehttp://processors.wiki.ti.com/index.php/TMDSEVM6657L_EVM_Hardware_Setup#Boot_Mode_Dip_Switch_Settingsj]j]j]j]j]ujjCj]rWjXTMDSEVM6657L_EVMrXrY}rZ(jUjjTubajjubjX that IBL supports.r[r\}r](jX that IBL supports.jjCubeubeubj)r^}r_(jUjKjjkjj}jjj}r`(j]raXflashing the bootloaderrbaj]j]j]rcUflashing-the-bootloaderrdaj]ujK,jhj]re(j)rf}rg(jXFlashing the Bootloaderrhjj^jj}jjj}ri(j]j]j]j]j]ujK,jhj]rjjXFlashing the Bootloaderrkrl}rm(jjhjjfubaubj)rn}ro(jX1IBL needs to be flashed into EEPROM address 0x51.rpjj^jj}jjj}rq(j]j]j]j]j]ujK.jhj]rrjX1IBL needs to be flashed into EEPROM address 0x51.rsrt}ru(jjpjjnubaubj)rv}rw(jXRefer to `Processor SDK RTOS Flashing Bootable Images `__] for instructions on using the script, program_evm.js, to automatically flash your device.jj^jj}jjj}rx(j]j]j]j]j]ujK0jhj]ry(jX Refer to rzr{}r|(jX Refer to jjvubj)r}}r~(jXh`Processor SDK RTOS Flashing Bootable Images `__j}r(UnameX+Processor SDK RTOS Flashing Bootable ImagesjX6http://processors.wiki.ti.com/index.php/Program_EVM_UGj]j]j]j]j]ujjvj]rjX+Processor SDK RTOS Flashing Bootable Imagesrr}r(jUjj}ubajjubjX[] for instructions on using the script, program_evm.js, to automatically flash your device.rr}r(jX[] for instructions on using the script, program_evm.js, to automatically flash your device.jjvubeubeubj)r}r(jUjKjjkjj}jjj}r(j]rXbootloader execution sequenceraj]j]j]rUid88raj]ujK6jhj]r(j)r}r(jXBootloader Execution Sequencerjjjj}jjj}r(j]j]j]j]j]ujK6jhj]rjXBootloader Execution Sequencerr}r(jjjjubaubj)r}r(jXIBL is flashed into I2C EEPROM bus address 0x51. IBL provides a workaround for the PLL lockup issue (please refer to C6678 errata document, February 2011, advisory 8 for details on the PLL lockup issue). For ROM boot modes (EMAC,SRIO,PCIe,Hyperlink etc) and I2C boot mode with bus address 0x50, DSP will initially boot from I2C EEPROM bus address 0x51 which does the PLL reset workaround, updates the DEVSTAT for appropriate values based on the DIP switch settings (SW3 through SW6 settings) and then re enters the ROM to accomplish the desired boot mode. Please note that the re entry is done for all boot modes except for PCIe boot mode and I2C boot mode with bus address 0x51.rjjjj}jjj}r(j]j]j]j]j]ujK8jhj]rjXIBL is flashed into I2C EEPROM bus address 0x51. IBL provides a workaround for the PLL lockup issue (please refer to C6678 errata document, February 2011, advisory 8 for details on the PLL lockup issue). For ROM boot modes (EMAC,SRIO,PCIe,Hyperlink etc) and I2C boot mode with bus address 0x50, DSP will initially boot from I2C EEPROM bus address 0x51 which does the PLL reset workaround, updates the DEVSTAT for appropriate values based on the DIP switch settings (SW3 through SW6 settings) and then re enters the ROM to accomplish the desired boot mode. Please note that the re entry is done for all boot modes except for PCIe boot mode and I2C boot mode with bus address 0x51.rr}r(jjjjubaubj)r}r(jX$Below are the steps done in the IBL:rjjjj}jjj}r(j]j]j]j]j]ujKCjhj]rjX$Below are the steps done in the IBL:rr}r(jjjjubaubj )r}r(jUjjjj}jj j}r(jU.j]j]j]jUj]j]jjujKEjhj]r(j{)r}r(jXFPGA samples the bootmode pinsrjjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj}jjj}r(j]j]j]j]j]ujKEj]rjXFPGA samples the bootmode pinsrr}r(jjjjubaubaubj{)r}r(jX4FPGA forces the DSP to boot via I2C bus address 0x51rjjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj}jjj}r(j]j]j]j]j]ujKFj]rjX4FPGA forces the DSP to boot via I2C bus address 0x51rr}rµ(jjjjubaubaubj{)rõ}rĵ(jX3PLL is initialized correctly by the IBL on the I2C.rŵjjjj}jjj}rƵ(j]j]j]j]j]ujNjhj]rǵj)rȵ}rɵ(jjŵjjõjj}jjj}rʵ(j]j]j]j]j]ujKGj]r˵jX3PLL is initialized correctly by the IBL on the I2C.r̵r͵}rε(jjŵjjȵubaubaubj{)rϵ}rе(jX5IBL reads the sampled bootmode from an FPGA register.rѵjjjj}jjj}rҵ(j]j]j]j]j]ujNjhj]rӵj)rԵ}rյ(jjѵjjϵjj}jjj}rֵ(j]j]j]j]j]ujKHj]r׵jX5IBL reads the sampled bootmode from an FPGA register.rصrٵ}rڵ(jjѵjjԵubaubaubj{)r۵}rܵ(jXIBL checks the bootmode, if it is not I2C boot or it is I2C boot but with bus address 0x50, IBL writes bootmode into the DEVSTAT registerjjjj}jjj}rݵ(j]j]j]j]j]ujNjhj]r޵j)rߵ}r(jXIBL checks the bootmode, if it is not I2C boot or it is I2C boot but with bus address 0x50, IBL writes bootmode into the DEVSTAT registerrjj۵jj}jjj}r(j]j]j]j]j]ujKIj]rjXIBL checks the bootmode, if it is not I2C boot or it is I2C boot but with bus address 0x50, IBL writes bootmode into the DEVSTAT registerrr}r(jjjjߵubaubaubj{)r}r(jXIBL then checks if the bootmode is PCIE boot or not. If it is, it executes some PCIE workaround to configure the PCIE registers (mainly to accept spread spectrum clock) and stays inside IBL waiting for PCIe boot.jjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXIBL then checks if the bootmode is PCIE boot or not. If it is, it executes some PCIE workaround to configure the PCIE registers (mainly to accept spread spectrum clock) and stays inside IBL waiting for PCIe boot.rjjjj}jjj}r(j]j]j]j]j]ujKKj]rjXIBL then checks if the bootmode is PCIE boot or not. If it is, it executes some PCIE workaround to configure the PCIE registers (mainly to accept spread spectrum clock) and stays inside IBL waiting for PCIe boot.rr}r(jjjjubaubaubj{)r}r(jXIf it is not PCIE boot mode, IBL writes the Boot ROM entry address into the DSP Program Counter, DSP executes the desired internal ROM boot mode or boot from I2C bus address 0x50 as normal. jjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXIf it is not PCIE boot mode, IBL writes the Boot ROM entry address into the DSP Program Counter, DSP executes the desired internal ROM boot mode or boot from I2C bus address 0x50 as normal.rjjjj}jjj}r(j]j]j]j]j]ujKOj]rjXIf it is not PCIE boot mode, IBL writes the Boot ROM entry address into the DSP Program Counter, DSP executes the desired internal ROM boot mode or boot from I2C bus address 0x50 as normal.rr}r(jjjjubaubaubeubeubj)r}r(jUjKjjkjj}jjj}r(j]rX compilationraj]j]j]rU compilationraj]ujKTjhj]r(j)r}r(jX Compilationr jjjj}jjj}r (j]j]j]j]j]ujKTjhj]r jX Compilationr r }r(jj jjubaubj)r}r(jXThe recommended rule-of-thumb to compiling projects in the Processor SDK RTOS package is to use the makefiles provided. The makefiles are usable after setting up your shell/terminal/command prompt environment with the setupenv.bat or setupenv.sh script located inrjjjj}jjj}r(j]j]j]j]j]ujKVjhj]rjXThe recommended rule-of-thumb to compiling projects in the Processor SDK RTOS package is to use the makefiles provided. The makefiles are usable after setting up your shell/terminal/command prompt environment with the setupenv.bat or setupenv.sh script located inrr}r(jjjjubaubj)r}r(jX:[SDK Install Path]/processor_sdk_rtos__jjjj}jjj}r(j@jAj]j]j]j]j]ujMv)jhj]rjX:[SDK Install Path]/processor_sdk_rtos__rr}r(jUjjubaubj)r}r(jXRefer to `Processor SDK RTOS Building the SDK `__ guide on how to setup your environment for building within any of the Processor SDK RTOS packages.jjjj}jjj}r (j]j]j]j]j]ujK_jhj]r!(jX Refer to r"r#}r$(jX Refer to jjubj)r%}r&(jXN`Processor SDK RTOS Building the SDK `__j}r'(UnameX#Processor SDK RTOS Building the SDKjX$index_overview.html#building-the-sdkj]j]j]j]j]ujjj]r(jX#Processor SDK RTOS Building the SDKr)r*}r+(jUjj%ubajjubjXc guide on how to setup your environment for building within any of the Processor SDK RTOS packages.r,r-}r.(jXc guide on how to setup your environment for building within any of the Processor SDK RTOS packages.jjubeubj)r/}r0(jXC66x projects are supported by C6000 Code Generation Tools 7.4.x. Make sure your environment variable, C6X_GEN_INSTALL_PATH, is pointing to a valid C6000 compiler. Compiling IBL invokes the C6000 compiler, cl6x, directly. Your PATH variable will need to have $C6X_GEN_INSTALL_PATH/bin.jjjj}jjj}r1(j]j]j]j]j]ujNjhj]r2j)r3}r4(jXC66x projects are supported by C6000 Code Generation Tools 7.4.x. Make sure your environment variable, C6X_GEN_INSTALL_PATH, is pointing to a valid C6000 compiler. Compiling IBL invokes the C6000 compiler, cl6x, directly. Your PATH variable will need to have $C6X_GEN_INSTALL_PATH/bin.r5jj/jj}jjj}r6(j]j]j]j]j]ujKdj]r7jXC66x projects are supported by C6000 Code Generation Tools 7.4.x. Make sure your environment variable, C6X_GEN_INSTALL_PATH, is pointing to a valid C6000 compiler. Compiling IBL invokes the C6000 compiler, cl6x, directly. Your PATH variable will need to have $C6X_GEN_INSTALL_PATH/bin.r8r9}r:(jj5jj3ubaubaubj)r;}r<(jX The IBL package can be found in:r=jjjj}jjj}r>(j]j]j]j]j]ujKjjhj]r?jX The IBL package can be found in:r@rA}rB(jj=jj;ubaubj)rC}rD(jX@[SDK Install Path]/pdk__/packages/ti/boot/ibljjjj}jjj}rE(j@jAj]j]j]j]j]ujM)jhj]rFjX@[SDK Install Path]/pdk__/packages/ti/boot/iblrGrH}rI(jUjjCubaubj)rJ}rK(jX To build:rLjjjj}jjj}rM(j]j]j]j]j]ujKpjhj]rNjX To build:rOrP}rQ(jjLjjJubaubj)rR}rS(jXcd [SDK Install Path]/pdk__/packages/ti/boot/ibl/src/make make ENDIAN= I2C_BUS_ADDR=0x51jjjj}jjj}rT(j@jAj]j]j]j]j]ujM)jhj]rUjXcd [SDK Install Path]/pdk__/packages/ti/boot/ibl/src/make make ENDIAN= I2C_BUS_ADDR=0x51rVrW}rX(jUjjRubaubj)rY}rZ(jXz** can be of values: **evm_c6657_i2c** or **evm_c6678_i2c**. (For C6657 or C6678 platforms, respectively)jjjj}jjj}r[(j]j]j]j]j]ujKwjhj]r\(jM)r]}r^(jX**j}r_(j]j]j]j]j]ujjYj]r`jXrarb}rc(jUjj]ubajjUubjX can be of values: rdre}rf(jX can be of values: jjYubj)rg}rh(jX**evm_c6657_i2c**j}ri(j]j]j]j]j]ujjYj]rjjX evm_c6657_i2crkrl}rm(jUjjgubajjubjX or rnro}rp(jX or jjYubj)rq}rr(jX**evm_c6678_i2c**j}rs(j]j]j]j]j]ujjYj]rtjX evm_c6678_i2crurv}rw(jUjjqubajjubjX.. (For C6657 or C6678 platforms, respectively)rxry}rz(jX.. (For C6657 or C6678 platforms, respectively)jjYubeubj)r{}r|(jX=** can be of values: **little** or **big**r}jjjj}jjj}r~(j]j]j]j]j]ujKzjhj]r(jM)r}r(jX**j}r(j]j]j]j]j]ujj{j]rjXrr}r(jUjjubajjUubjX can be of values: rr}r(jX can be of values: jj{ubj)r}r(jX **little**j}r(j]j]j]j]j]ujj{j]rjXlittlerr}r(jUjjubajjubjX or rr}r(jX or jj{ubj)r}r(jX**big**j}r(j]j]j]j]j]ujj{j]rjXbigrr}r(jUjjubajjubeubj)r}r(jXk*I2C_BUS_ADDR* specifies the I2C bus address to use, and has to be 0x51 for C66x SOCs to access the EEPROM.jjjj}jjj}r(j]j]j]j]j]ujK|jhj]r(jM)r}r(jX*I2C_BUS_ADDR*j}r(j]j]j]j]j]ujjj]rjX I2C_BUS_ADDRrr}r(jUjjubajjUubjX] specifies the I2C bus address to use, and has to be 0x51 for C66x SOCs to access the EEPROM.rr}r(jX] specifies the I2C bus address to use, and has to be 0x51 for C66x SOCs to access the EEPROM.jjubeubj)r}r(jXxThe resulting output will be in [SDK Install Path]/pdk__/packages/ti/boot/ibl/src/make/bin directory.rjjjj}jjj}r(j]j]j]j]j]ujKjhj]rjXxThe resulting output will be in [SDK Install Path]/pdk__/packages/ti/boot/ibl/src/make/bin directory.rr}r(jjjjubaubj)r}r(jXFor developers, who want to build IBL in Windows environment. Please build this using MinGW environment using the instructions provided in the build_instructions.txt that can be found under pdk_c66xx_xx_xx\packages\ti\boot\ibl\doc\ibl\docjjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXFor developers, who want to build IBL in Windows environment. Please build this using MinGW environment using the instructions provided in the build_instructions.txt that can be found under pdk_c66xx_xx_xx\packages\ti\boot\ibl\doc\ibl\docjjjj}jjj}r(j]j]j]j]j]ujKj]rjXFor developers, who want to build IBL in Windows environment. Please build this using MinGW environment using the instructions provided in the build_instructions.txt that can be found under pdk_c66xx_xx_xxpackagestibootibldocibldocrr}r(jXFor developers, who want to build IBL in Windows environment. Please build this using MinGW environment using the instructions provided in the build_instructions.txt that can be found under pdk_c66xx_xx_xx\packages\ti\boot\ibl\doc\ibl\docjjubaubaubjc)r}r(jUjjjj}jjfj}r(j]j]j]j]j]ujKjhj]rji)r}r(jUjlKjjjj}jjj}r¶(j]j]j]j]j]ujKjhj]ubaubeubj)rö}rĶ(jUjKjjkjj}jjj}rŶ(j]rƶX flash writersrǶaj]j]j]rȶU flash-writersrɶaj]ujKjhj]rʶ(j)r˶}r̶(jX Flash WritersrͶjjöjj}jjj}rζ(j]j]j]j]j]ujKjhj]r϶jX Flash WritersrжrѶ}rҶ(jjͶjj˶ubaubj)rӶ}rԶ(jXThere are three types of flash memory provided with the C66x SOCs: EEPROM, NOR, and NAND. Each of these flash memory can hold bootable application binaries. As such, respective flash writers are provided in:rնjjöjj}jjj}rֶ(j]j]j]j]j]ujKjhj]r׶jXThere are three types of flash memory provided with the C66x SOCs: EEPROM, NOR, and NAND. Each of these flash memory can hold bootable application binaries. As such, respective flash writers are provided in:rضrٶ}rڶ(jjնjjӶubaubj)r۶}rܶ(jXC[SDK Install Path]/pdk__/packages/ti/boot/writerjjöjj}jjj}rݶ(j@jAj]j]j]j]j]ujM)jhj]r޶jXC[SDK Install Path]/pdk__/packages/ti/boot/writerr߶r}r(jUjj۶ubaubj)r}r(jXPlease set your EVM to **NO BOOT** mode before loading and running any of the flash writers. Flashing in NO BOOT mode is the safest way since it eliminates any unwarranted interactions with booted applications.jjöjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXPlease set your EVM to **NO BOOT** mode before loading and running any of the flash writers. Flashing in NO BOOT mode is the safest way since it eliminates any unwarranted interactions with booted applications.jjjj}jjj}r(j]j]j]j]j]ujKj]r(jXPlease set your EVM to rr}r(jXPlease set your EVM to jjubj)r}r(jX **NO BOOT**j}r(j]j]j]j]j]ujjj]rjXNO BOOTrr}r(jUjjubajjubjX mode before loading and running any of the flash writers. Flashing in NO BOOT mode is the safest way since it eliminates any unwarranted interactions with booted applications.rr}r(jX mode before loading and running any of the flash writers. Flashing in NO BOOT mode is the safest way since it eliminates any unwarranted interactions with booted applications.jjubeubaubj)r}r(jUjjöjj}jjj}r(j]j]j]j]rU eeprom-writerraj]rhaujKjhj]r(j)r}r(jX EEPROM Writerrjjjj}jjj}r(j]j]j]j]j]ujKjhj]rjX EEPROM Writerrr}r(jjjjubaubj)r}r(jXCThe EEPROM Writer is used to write a binary into the EEPROM memory.rjjjj}jjj}r (j]j]j]j]j]ujKjhj]r jXCThe EEPROM Writer is used to write a binary into the EEPROM memory.r r }r (jjjjubaubj)r}r(jUjKjjjj}jjj}r(j]rjaj]j]j]rUid89raj]ujKjhj]r(j)r}r(jX Compilationrjjjj}jjj}r(j]j]j]j]j]ujKjhj]rjX Compilationrr}r(jjjjubaubj)r}r(jXgcd [SDK Install Path]/pdk__/packages/ti/boot/writer/eeprom//build make alljjjj}jjj}r(j@jAj]j]j]j]j]ujM)jhj]r jXgcd [SDK Install Path]/pdk__/packages/ti/boot/writer/eeprom//build make allr!r"}r#(jUjjubaubeubj)r$}r%(jUjKjjjj}jjj}r&(j]r'Xusager(aj]j]j]r)Uusager*aj]ujKjhj]r+(j)r,}r-(jXUsager.jj$jj}jjj}r/(j]j]j]j]j]ujKjhj]r0jXUsager1r2}r3(jj.jj,ubaubj )r4}r5(jUjj$jj}jj j}r6(jU.j]j]j]jUj]j]jjujKjhj]r7(j{)r8}r9(jXSet your EVM to **NO BOOT**. Power on, launch target configuration in CCS, and connect to Core 0. Be sure the GEL file is used and DDR is initialized.jj4jj}jjj}r:(j]j]j]j]j]ujNjhj]r;j)r<}r=(jXSet your EVM to **NO BOOT**. Power on, launch target configuration in CCS, and connect to Core 0. Be sure the GEL file is used and DDR is initialized.jj8jj}jjj}r>(j]j]j]j]j]ujKj]r?(jXSet your EVM to r@rA}rB(jXSet your EVM to jj<ubj)rC}rD(jX **NO BOOT**j}rE(j]j]j]j]j]ujj<j]rFjXNO BOOTrGrH}rI(jUjjCubajjubjX{. Power on, launch target configuration in CCS, and connect to Core 0. Be sure the GEL file is used and DDR is initialized.rJrK}rL(jX{. Power on, launch target configuration in CCS, and connect to Core 0. Be sure the GEL file is used and DDR is initialized.jj<ubeubaubj{)rM}rN(jXCopy the desired binary you want to flash to [SDK Install Path]/pdk__/packages/ti/boot/writer/eeprom//bin directory.jj4jj}jjj}rO(j]j]j]j]j]ujNjhj]rPj)rQ}rR(jXCopy the desired binary you want to flash to [SDK Install Path]/pdk__/packages/ti/boot/writer/eeprom//bin directory.rSjjMjj}jjj}rT(j]j]j]j]j]ujKj]rUjXCopy the desired binary you want to flash to [SDK Install Path]/pdk__/packages/ti/boot/writer/eeprom//bin directory.rVrW}rX(jjSjjQubaubaubj{)rY}rZ(jX?Rename the binary you copied in the previous step to "app.bin".r[jj4jj}jjj}r\(j]j]j]j]j]ujNjhj]r]j)r^}r_(jj[jjYjj}jjj}r`(j]j]j]j]j]ujKj]rajX?Rename the binary you copied in the previous step to "app.bin".rbrc}rd(jj[jj^ubaubaubj{)re}rf(jX1In CCS, select Core 0 and open the Memory Browserrgjj4jj}jjj}rh(j]j]j]j]j]ujNjhj]rij)rj}rk(jjgjjejj}jjj}rl(j]j]j]j]j]ujKj]rmjX1In CCS, select Core 0 and open the Memory Browserrnro}rp(jjgjjjubaubaubj{)rq}rr(jXBIn the Memory Browser window, right click and select "Load Memory"rsjj4jj}jjj}rt(j]j]j]j]j]ujNjhj]ruj)rv}rw(jjsjjqjj}jjj}rx(j]j]j]j]j]ujKj]ryjXBIn the Memory Browser window, right click and select "Load Memory"rzr{}r|(jjsjjvubaubaubj{)r}}r~(jXLoad your app.bin to 0x0C000000. Do so by selecting app.bin for the file, click Next, and input 0x0C000000 for Start Address (Type-size selected should be 32-bit)jj4jj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXLoad your app.bin to 0x0C000000. Do so by selecting app.bin for the file, click Next, and input 0x0C000000 for Start Address (Type-size selected should be 32-bit)rjj}jj}jjj}r(j]j]j]j]j]ujKj]rjXLoad your app.bin to 0x0C000000. Do so by selecting app.bin for the file, click Next, and input 0x0C000000 for Start Address (Type-size selected should be 32-bit)rr}r(jjjjubaubaubj{)r}r(jXuLoad [SDK Install Path]/pdk__/packages/ti/boot/writer/eeprom//bin/eepromwriter_.outjj4jj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXuLoad [SDK Install Path]/pdk__/packages/ti/boot/writer/eeprom//bin/eepromwriter_.outrjjjj}jjj}r(j]j]j]j]j]ujKj]rjXuLoad [SDK Install Path]/pdk__/packages/ti/boot/writer/eeprom//bin/eepromwriter_.outrr}r(jjjjubaubaubj{)r}r(jX0Run Core 0. This will program the flash memory. jj4jj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX/Run Core 0. This will program the flash memory.rjjjj}jjj}r(j]j]j]j]j]ujKj]rjX/Run Core 0. This will program the flash memory.rr}r(jjjjubaubaubeubj)r}r(jXRIf it succeeds, the console will print "EEPROM programming completed successfully"rjj$jj}jjj}r(j]j]j]j]j]ujKjhj]rjXRIf it succeeds, the console will print "EEPROM programming completed successfully"rr}r(jjjjubaubeubeubj)r}r(jUjjöjj}jjj}r(j]j]j]j]rU nor-writerraj]rhaujKjhj]r(j)r}r(jX NOR Writerrjjjj}jjj}r(j]j]j]j]j]ujKjhj]rjX NOR Writerrr}r(jjjjubaubj)r}r(jX=The NOR Writer is used to write a binary into the NOR memory.rjjjj}jjj}r(j]j]j]j]j]ujKjhj]rjX=The NOR Writer is used to write a binary into the NOR memory.rr}r(jjjjubaubj)r}r(jUjKjjjj}jjj}r·(j]r÷X compilationrķaj]j]j]rŷUid90rƷaj]ujKjhj]rǷ(j)rȷ}rɷ(jX Compilationrʷjjjj}jjj}r˷(j]j]j]j]j]ujKjhj]r̷jX Compilationrͷrη}rϷ(jjʷjjȷubaubj)rз}rѷ(jXdcd [SDK Install Path]/pdk__/packages/ti/boot/writer/nor//build make alljjjj}jjj}rҷ(j@jAj]j]j]j]j]ujM)jhj]rӷjXdcd [SDK Install Path]/pdk__/packages/ti/boot/writer/nor//build make allrԷrշ}rַ(jUjjзubaubeubj)r׷}rط(jUjKjjjj}jjj}rٷ(j]rڷj(aj]j]j]r۷Uid91rܷaj]ujKjhj]rݷ(j)r޷}r߷(jXUsagerjj׷jj}jjj}r(j]j]j]j]j]ujKjhj]rjXUsagerr}r(jjjj޷ubaubj )r}r(jUjj׷jj}jj j}r(jU.j]j]j]jUj]j]jjujKjhj]r(j{)r}r(jXSet your EVM to **NO BOOT**. Power on, launch target configuration in CCS, and connect to Core 0. Be sure the GEL file is used and DDR is initialized.jjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXSet your EVM to **NO BOOT**. Power on, launch target configuration in CCS, and connect to Core 0. Be sure the GEL file is used and DDR is initialized.jjjj}jjj}r(j]j]j]j]j]ujKj]r(jXSet your EVM to rr}r(jXSet your EVM to jjubj)r}r(jX **NO BOOT**j}r(j]j]j]j]j]ujjj]rjXNO BOOTrr}r(jUjjubajjubjX{. Power on, launch target configuration in CCS, and connect to Core 0. Be sure the GEL file is used and DDR is initialized.rr}r(jX{. Power on, launch target configuration in CCS, and connect to Core 0. Be sure the GEL file is used and DDR is initialized.jjubeubaubj{)r}r(jXCopy the desired binary you want to flash to [SDK Install Path]/pdk__/packages/ti/boot/writer/nor//bin directory.jjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXCopy the desired binary you want to flash to [SDK Install Path]/pdk__/packages/ti/boot/writer/nor//bin directory.rjjjj}jjj}r(j]j]j]j]j]ujKj]rjXCopy the desired binary you want to flash to [SDK Install Path]/pdk__/packages/ti/boot/writer/nor//bin directory.rr }r (jjjjubaubaubj{)r }r (jX?Rename the binary you copied in the previous step to "app.bin".r jjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jj jj jj}jjj}r(j]j]j]j]j]ujKj]rjX?Rename the binary you copied in the previous step to "app.bin".rr}r(jj jjubaubaubj{)r}r(jX1In CCS, select Core 0 and open the Memory Browserrjjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj}jjj}r(j]j]j]j]j]ujKj]rjX1In CCS, select Core 0 and open the Memory Browserr r!}r"(jjjjubaubaubj{)r#}r$(jXBIn the Memory Browser window, right click and select "Load Memory"r%jjjj}jjj}r&(j]j]j]j]j]ujNjhj]r'j)r(}r)(jj%jj#jj}jjj}r*(j]j]j]j]j]ujKj]r+jXBIn the Memory Browser window, right click and select "Load Memory"r,r-}r.(jj%jj(ubaubaubj{)r/}r0(jXLoad your app.bin to 0x80000000. Do so by selecting app.bin for the file, click Next, and input 0x80000000 for Start Address (Type-size selected should be 32-bit)jjjj}jjj}r1(j]j]j]j]j]ujNjhj]r2j)r3}r4(jXLoad your app.bin to 0x80000000. Do so by selecting app.bin for the file, click Next, and input 0x80000000 for Start Address (Type-size selected should be 32-bit)r5jj/jj}jjj}r6(j]j]j]j]j]ujKj]r7jXLoad your app.bin to 0x80000000. Do so by selecting app.bin for the file, click Next, and input 0x80000000 for Start Address (Type-size selected should be 32-bit)r8r9}r:(jj5jj3ubaubaubj{)r;}r<(jXoLoad [SDK Install Path]/pdk__/packages/ti/boot/writer/nor//bin/norwriter_.outjjjj}jjj}r=(j]j]j]j]j]ujNjhj]r>j)r?}r@(jXoLoad [SDK Install Path]/pdk__/packages/ti/boot/writer/nor//bin/norwriter_.outrAjj;jj}jjj}rB(j]j]j]j]j]ujKj]rCjXoLoad [SDK Install Path]/pdk__/packages/ti/boot/writer/nor//bin/norwriter_.outrDrE}rF(jjAjj?ubaubaubj{)rG}rH(jX0Run Core 0. This will program the flash memory. jjjj}jjj}rI(j]j]j]j]j]ujNjhj]rJj)rK}rL(jX/Run Core 0. This will program the flash memory.rMjjGjj}jjj}rN(j]j]j]j]j]ujKj]rOjX/Run Core 0. This will program the flash memory.rPrQ}rR(jjMjjKubaubaubeubj)rS}rT(jXOIf it succeeds, the console will print "NOR programming completed successfully"rUjj׷jj}jjj}rV(j]j]j]j]j]ujKjhj]rWjXOIf it succeeds, the console will print "NOR programming completed successfully"rXrY}rZ(jjUjjSubaubeubeubj)r[}r\(jUjjöjj}jjj}r](j]j]j]j]r^U nand-writerr_aj]r`haujKjhj]ra(j)rb}rc(jX NAND Writerrdjj[jj}jjj}re(j]j]j]j]j]ujKjhj]rfjX NAND Writerrgrh}ri(jjdjjbubaubj)rj}rk(jX?The NAND Writer is used to write a binary into the NAND memory.rljj[jj}jjj}rm(j]j]j]j]j]ujKjhj]rnjX?The NAND Writer is used to write a binary into the NAND memory.rorp}rq(jjljjjubaubj)rr}rs(jUjKjj[jj}jjj}rt(j]ruX compilationrvaj]j]j]rwUid92rxaj]ujKjhj]ry(j)rz}r{(jX Compilationr|jjrjj}jjj}r}(j]j]j]j]j]ujKjhj]r~jX Compilationrr}r(jj|jjzubaubj)r}r(jXecd [SDK Install Path]/pdk__/packages/ti/boot/writer/nand//build make alljjrjj}jjj}r(j@jAj]j]j]j]j]ujM*jhj]rjXecd [SDK Install Path]/pdk__/packages/ti/boot/writer/nand//build make allrr}r(jUjjubaubeubj)r}r(jUjKjj[jj}jjj}r(j]rXusageraj]j]j]rUid93raj]ujKjhj]r(j)r}r(jXUsagerjjjj}jjj}r(j]j]j]j]j]ujKjhj]rjXUsagerr}r(jjjjubaubj )r}r(jUjjjj}jj j}r(jU.j]j]j]jUj]j]jjujKjhj]r(j{)r}r(jXSet your EVM to **NO BOOT**. Power on, launch target configuration in CCS, and connect to Core 0. Be sure the GEL file is used and DDR is initialized.jjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXSet your EVM to **NO BOOT**. Power on, launch target configuration in CCS, and connect to Core 0. Be sure the GEL file is used and DDR is initialized.jjjj}jjj}r(j]j]j]j]j]ujKj]r(jXSet your EVM to rr}r(jXSet your EVM to jjubj)r}r(jX **NO BOOT**j}r(j]j]j]j]j]ujjj]rjXNO BOOTrr}r(jUjjubajjubjX{. Power on, launch target configuration in CCS, and connect to Core 0. Be sure the GEL file is used and DDR is initialized.rr}r(jX{. Power on, launch target configuration in CCS, and connect to Core 0. Be sure the GEL file is used and DDR is initialized.jjubeubaubj{)r}r(jXCopy the desired binary you want to flash to [SDK Install Path]/pdk__/packages/ti/boot/writer/nand//bin directory.jjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXCopy the desired binary you want to flash to [SDK Install Path]/pdk__/packages/ti/boot/writer/nand//bin directory.rjjjj}jjj}r(j]j]j]j]j]ujKj]rjXCopy the desired binary you want to flash to [SDK Install Path]/pdk__/packages/ti/boot/writer/nand//bin directory.rr}r(jjjjubaubaubj{)r}r(jX?Rename the binary you copied in the previous step to "app.bin".rjjjj}jjj}r(j]j]j]j]j]ujNjhj]r¸j)rø}rĸ(jjjjjj}jjj}rŸ(j]j]j]j]j]ujKj]rƸjX?Rename the binary you copied in the previous step to "app.bin".rǸrȸ}rɸ(jjjjøubaubaubj{)rʸ}r˸(jX1In CCS, select Core 0 and open the Memory Browserr̸jjjj}jjj}r͸(j]j]j]j]j]ujNjhj]rθj)rϸ}rи(jj̸jjʸjj}jjj}rѸ(j]j]j]j]j]ujKj]rҸjX1In CCS, select Core 0 and open the Memory BrowserrӸrԸ}rո(jj̸jjϸubaubaubj{)rָ}r׸(jXBIn the Memory Browser window, right click and select "Load Memory"rظjjjj}jjj}rٸ(j]j]j]j]j]ujNjhj]rڸj)r۸}rܸ(jjظjjָjj}jjj}rݸ(j]j]j]j]j]ujKj]r޸jXBIn the Memory Browser window, right click and select "Load Memory"r߸r}r(jjظjj۸ubaubaubj{)r}r(jXLoad your app.bin to 0x80000000. Do so by selecting app.bin for the file, click Next, and input 0x80000000 for Start Address (Type-size selected should be 32-bit)jjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXLoad your app.bin to 0x80000000. Do so by selecting app.bin for the file, click Next, and input 0x80000000 for Start Address (Type-size selected should be 32-bit)rjjjj}jjj}r(j]j]j]j]j]ujKj]rjXLoad your app.bin to 0x80000000. Do so by selecting app.bin for the file, click Next, and input 0x80000000 for Start Address (Type-size selected should be 32-bit)rr}r(jjjjubaubaubj{)r}r(jXqLoad [SDK Install Path]/pdk__/packages/ti/boot/writer/nand//bin/nandwriter_.outjjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXqLoad [SDK Install Path]/pdk__/packages/ti/boot/writer/nand//bin/nandwriter_.outrjjjj}jjj}r(j]j]j]j]j]ujKj]rjXqLoad [SDK Install Path]/pdk__/packages/ti/boot/writer/nand//bin/nandwriter_.outrr}r(jjjjubaubaubj{)r}r(jX0Run Core 0. This will program the flash memory. jjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX/Run Core 0. This will program the flash memory.rjjjj}jjj}r(j]j]j]j]j]ujMj]rjX/Run Core 0. This will program the flash memory.rr}r(jjjjubaubaubeubj)r}r(jXPIf it succeeds, the console will print "NAND programming completed successfully"rjjjj}jjj}r (j]j]j]j]j]ujMjhj]r jXPIf it succeeds, the console will print "NAND programming completed successfully"r r }r (jjjjubaubeubeubeubj)r}r(jUjKjjkjj}jjj}r(j]rX boot modesraj]j]j]rUid94raj]ujMjhj]r(j)r}r(jX Boot Modesrjjjj}jjj}r(j]j]j]j]j]ujMjhj]rjX Boot Modesrr}r(jjjjubaubj)r}r(jUjjjj}jjj}r (j]j]j]j]r!U nand-bootr"aj]r#j7aujM jhj]r$(j)r%}r&(jX NAND Bootr'jjjj}jjj}r((j]j]j]j]j]ujM jhj]r)jX NAND Bootr*r+}r,(jj'jj%ubaubjR)r-}r.(jX".. Image:: ../images/Nandboot.jpg jjjj}jjZj}r/(UuriXrtos/../images/Nandboot.jpgr0j]j]j]j]jX}r1U*j0sj]ujM jhj]ubj)r2}r3(jXNAND boot is a multi-stage process which is designed to boot an application from NAND flash after reset. Figure below illustrates the elements of the NAND boot process.r4jjjj}jjj}r5(j]j]j]j]j]ujMjhj]r6jXNAND boot is a multi-stage process which is designed to boot an application from NAND flash after reset. Figure below illustrates the elements of the NAND boot process.r7r8}r9(jj4jj2ubaubj)r:}r;(jXOn reset the DSP starts execution with the bootrom which transfers execution to the secondary bootloader from EEPROM using the I2C slave bus address 0x51. The secondary bootloader loads the application program from NAND flash then transfers control to the application. To execute the NAND bootloader you must ensure the DIP switches for your platform are properly configured for I2C Master Boot and address 0x51, AND the boot parameter index dip switch should be set to 2 or 3.r<jjjj}jjj}r=(j]j]j]j]j]ujMjhj]r>jXOn reset the DSP starts execution with the bootrom which transfers execution to the secondary bootloader from EEPROM using the I2C slave bus address 0x51. The secondary bootloader loads the application program from NAND flash then transfers control to the application. To execute the NAND bootloader you must ensure the DIP switches for your platform are properly configured for I2C Master Boot and address 0x51, AND the boot parameter index dip switch should be set to 2 or 3.r?r@}rA(jj<jj:ubaubj)rB}rC(jX;NAND boot supports multiple images booting. Depending on the boot parameter index dip switch, maximum 2 boot images can be supported. By default NAND boot only supports a BBLOB image format, if the customer wants to boot an ELF image,  the IBL configuration table needs to be modified and re-programmed to EEPROM.rDjjjj}jjj}rE(j]j]j]j]j]ujMjhj]rFjX;NAND boot supports multiple images booting. Depending on the boot parameter index dip switch, maximum 2 boot images can be supported. By default NAND boot only supports a BBLOB image format, if the customer wants to boot an ELF image,  the IBL configuration table needs to be modified and re-programmed to EEPROM.rGrH}rI(jjDjjBubaubjc)rJ}rK(jUjjjj}jjfj}rL(j]j]j]j]j]ujM jhj]rMji)rN}rO(jUjlKjjJjj}jjj}rP(j]j]j]j]j]ujKjhj]ubaubeubj)rQ}rR(jUjjjj}jjj}rS(j]j]j]j]rTUnor-bootrUaj]rVhaujM#jhj]rW(j)rX}rY(jXNOR BootrZjjQjj}jjj}r[(j]j]j]j]j]ujM#jhj]r\jXNOR Bootr]r^}r_(jjZjjXubaubjR)r`}ra(jX!.. Image:: ../images/Norboot.jpg jjQjj}jjZj}rb(UuriXrtos/../images/Norboot.jpgrcj]j]j]j]jX}rdU*jcsj]ujM&jhj]ubj)re}rf(jXNOR boot is a multi-stage process which is designed to boot an application from NOR flash after reset. Figure below illustrates the elements of the NOR boot process.rgjjQjj}jjj}rh(j]j]j]j]j]ujM'jhj]rijXNOR boot is a multi-stage process which is designed to boot an application from NOR flash after reset. Figure below illustrates the elements of the NOR boot process.rjrk}rl(jjgjjeubaubj)rm}rn(jXOn reset the DSP starts execution with the bootrom which transfers execution to the secondary bootloader from EEPROM using the I2C slave address 0x51. The secondary bootloader loads the application program from NOR flash then transfers control to the application. To execute the NOR bootloader you must ensure the DIP switches for your platform are properly configured for I2C Master Boot and address 0x51, AND the boot parameter index switch should be set to 0 or 1.rojjQjj}jjj}rp(j]j]j]j]j]ujM+jhj]rqjXOn reset the DSP starts execution with the bootrom which transfers execution to the secondary bootloader from EEPROM using the I2C slave address 0x51. The secondary bootloader loads the application program from NOR flash then transfers control to the application. To execute the NOR bootloader you must ensure the DIP switches for your platform are properly configured for I2C Master Boot and address 0x51, AND the boot parameter index switch should be set to 0 or 1.rrrs}rt(jjojjmubaubj)ru}rv(jXNOR boot supports multiple images booting. Depending on the boot parameter index dip switch, maximum 2 boot images can be supported.rwjjQjj}jjj}rx(j]j]j]j]j]ujM3jhj]ryjXNOR boot supports multiple images booting. Depending on the boot parameter index dip switch, maximum 2 boot images can be supported.rzr{}r|(jjwjjuubaubjc)r}}r~(jUjjQjj}jjfj}r(j]j]j]j]j]ujM6jhj]rji)r}r(jUjlKjj}jj}jjj}r(j]j]j]j]j]ujKjhj]ubaubeubj)r}r(jUjjjj}jjj}r(j]j]j]j]rU tftp-bootraj]rjaujM9jhj]r(j)r}r(jX TFTP Bootrjjjj}jjj}r(j]j]j]j]j]ujM9jhj]rjX TFTP Bootrr}r(jjjjubaubjR)r}r(jX".. Image:: ../images/Emacboot.jpg jjjj}jjZj}r(UuriXrtos/../images/Emacboot.jpgrj]j]j]j]jX}rU*jsj]ujM<jhj]ubj)r}r(jXEMAC boot is a multi-stage process which is designed to boot an application from TFTP server after reset. Figure below illustrates the elements of the EMAC boot process.rjjjj}jjj}r(j]j]j]j]j]ujM=jhj]rjXEMAC boot is a multi-stage process which is designed to boot an application from TFTP server after reset. Figure below illustrates the elements of the EMAC boot process.rr}r(jjjjubaubj)r}r(jXOn reset the DSP starts execution with the bootrom which transfers execution to the secondary bootloader from EEPROM using the I2C slave address 0x51. The secondary bootloader loads the application program from a remote TFTP server then transfers control to the application. To execute the EMAC bootloader you must ensure the DIP switches for your platform are properly configured for I2C Master Boot and address 0x51, AND the boot parameter index switch should be set to 4. By default EMAC boot only supports a BBLOB image format, if the customer wants to boot an ELF image, the IBL configuration table needs to be modified and re-programmed to EEPROM.rjjjj}jjj}r(j]j]j]j]j]ujMAjhj]rjXOn reset the DSP starts execution with the bootrom which transfers execution to the secondary bootloader from EEPROM using the I2C slave address 0x51. The secondary bootloader loads the application program from a remote TFTP server then transfers control to the application. To execute the EMAC bootloader you must ensure the DIP switches for your platform are properly configured for I2C Master Boot and address 0x51, AND the boot parameter index switch should be set to 4. By default EMAC boot only supports a BBLOB image format, if the customer wants to boot an ELF image, the IBL configuration table needs to be modified and re-programmed to EEPROM.rr}r(jjjjubaubjc)r}r(jUjjjj}jjfj}r(j]j]j]j]j]ujMLjhj]rji)r}r(jUjlKjjjj}jjj}r(j]j]j]j]j]ujKjhj]ubaubj)r}r(jUjjjj}jjj}r(j]j]j]j]rU(updating-the-ibl-ethernet-configurationsraj]rjaujMOjhj]r(j)r}r(jX(Updating the IBL Ethernet Configurationsrjjjj}jjj}r(j]j]j]j]j]ujMOjhj]rjX(Updating the IBL Ethernet Configurationsrr}r(jjjjubaubj)r}r(jXOThere are two ways to update the IBL ethernet configurations for ethernet boot.rjjjj}jjj}r(j]j]j]j]j]ujMQjhj]r¹jXOThere are two ways to update the IBL ethernet configurations for ethernet boot.rùrĹ}rŹ(jjjjubaubj)rƹ}rǹ(jX **Using CCS**rȹjjjj}jjj}rɹ(j]j]j]j]j]ujMTjhj]rʹj)r˹}r̹(jjȹj}r͹(j]j]j]j]j]ujjƹj]rιjX Using CCSrϹrй}rѹ(jUjj˹ubajjubaubj )rҹ}rӹ(jUjjjj}jj j}rԹ(jU.j]j]j]jUj]j]jjujMVjhj]rչ(j{)rֹ}r׹(jXOTurn on and connect to your EVM with the appropriate Target Configuration file.jjҹjj}jjj}rع(j]j]j]j]j]ujNjhj]rٹj)rڹ}r۹(jXOTurn on and connect to your EVM with the appropriate Target Configuration file.rܹjjֹjj}jjj}rݹ(j]j]j]j]j]ujMVj]r޹jXOTurn on and connect to your EVM with the appropriate Target Configuration file.r߹r}r(jjܹjjڹubaubaubj{)r}r(jXConnect to Core 0.rjjҹjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj}jjj}r(j]j]j]j]j]ujMXj]rjXConnect to Core 0.rr}r(jjjjubaubaubj{)r}r(jXGo to Run -> Load Program and select i2cparam_0x51_c667#_le_0x500.out located in [SDK Install Path]/pdk__/packages/ti/boot/ibl/src/make/binjjҹjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXGo to Run -> Load Program and select i2cparam_0x51_c667#_le_0x500.out located in [SDK Install Path]/pdk__/packages/ti/boot/ibl/src/make/binrjjjj}jjj}r(j]j]j]j]j]ujMYj]rjXGo to Run -> Load Program and select i2cparam_0x51_c667#_le_0x500.out located in [SDK Install Path]/pdk__/packages/ti/boot/ibl/src/make/binrr}r(jjjjubaubaubj{)r}r(jXGo to Tools -> GEL Files and then right click on GEL Files window and Load the i2cConfig.gel GEL file, located in [SDK Install Path]/pdk__/packages/ti/boot/ibl/src/make/binjjҹjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXGo to Tools -> GEL Files and then right click on GEL Files window and Load the i2cConfig.gel GEL file, located in [SDK Install Path]/pdk__/packages/ti/boot/ibl/src/make/binrjjjj}jjj}r(j]j]j]j]j]ujM\j]rjXGo to Tools -> GEL Files and then right click on GEL Files window and Load the i2cConfig.gel GEL file, located in [SDK Install Path]/pdk__/packages/ti/boot/ibl/src/make/binrr}r(jjjjubaubaubj{)r}r(jXRun the program. The following message will be printed on the CCS console: *Run the GEL for the SOC to be configured, press return to program the I2C.* **DO NOT PRESS ENTER UNTIL STEP 6 IS DONE**jjҹjj}jjj}r(j]j]j]j]j]ujNjhj]r j)r }r (jXRun the program. The following message will be printed on the CCS console: *Run the GEL for the SOC to be configured, press return to program the I2C.* **DO NOT PRESS ENTER UNTIL STEP 6 IS DONE**jjjj}jjj}r (j]j]j]j]j]ujM_j]r (jXKRun the program. The following message will be printed on the CCS console: rr}r(jXKRun the program. The following message will be printed on the CCS console: jj ubjM)r}r(jXL*Run the GEL for the SOC to be configured, press return to program the I2C.*j}r(j]j]j]j]j]ujj j]rjXJRun the GEL for the SOC to be configured, press return to program the I2C.rr}r(jUjjubajjUubjX r}r(jX jj ubj)r}r(jX+**DO NOT PRESS ENTER UNTIL STEP 6 IS DONE**j}r(j]j]j]j]j]ujj j]rjX'DO NOT PRESS ENTER UNTIL STEP 6 IS DONErr}r (jUjjubajjubeubaubj{)r!}r"(jXERun the GEL script"Scripts -> EVM c6678 IBL" -> setConfig_c6678_main.r#jjҹjj}jjj}r$(j]j]j]j]j]ujNjhj]r%j)r&}r'(jj#jj!jj}jjj}r((j]j]j]j]j]ujMbj]r)jXERun the GEL script"Scripts -> EVM c6678 IBL" -> setConfig_c6678_main.r*r+}r,(jj#jj&ubaubaubj{)r-}r.(jXNow press "Enter" in the CCS console window, and the program will write the boot parameter table to the EEPROM. On success the message "I2c table write complete" will be printed on the CCS console. jjҹjj}jjj}r/(j]j]j]j]j]ujNjhj]r0j)r1}r2(jXNow press "Enter" in the CCS console window, and the program will write the boot parameter table to the EEPROM. On success the message "I2c table write complete" will be printed on the CCS console.r3jj-jj}jjj}r4(j]j]j]j]j]ujMcj]r5jXNow press "Enter" in the CCS console window, and the program will write the boot parameter table to the EEPROM. On success the message "I2c table write complete" will be printed on the CCS console.r6r7}r8(jj3jj1ubaubaubeubj)r9}r:(jXPlease note that the i2cConfig.gel file can be modified via a text editor before loading and running the script in CCS. Please note that this gel file contains configuration settings for multiple SOCs and multiple boot modes.r;jjjj}jjj}r<(j]j]j]j]j]ujMgjhj]r=jXPlease note that the i2cConfig.gel file can be modified via a text editor before loading and running the script in CCS. Please note that this gel file contains configuration settings for multiple SOCs and multiple boot modes.r>r?}r@(jj;jj9ubaubj)rA}rB(jX#**Using iblConfig Utility Program**rCjjjj}jjj}rD(j]j]j]j]j]ujMljhj]rEj)rF}rG(jjCj}rH(j]j]j]j]j]ujjAj]rIjXUsing iblConfig Utility ProgramrJrK}rL(jUjjFubajjubaubj)rM}rN(jX|The second way to update the IBL ethernet configurations is to use **iblConfig.out**. This utility program is located under:jjjj}jjj}rO(j]j]j]j]j]ujMnjhj]rP(jXCThe second way to update the IBL ethernet configurations is to use rQrR}rS(jXCThe second way to update the IBL ethernet configurations is to use jjMubj)rT}rU(jX**iblConfig.out**j}rV(j]j]j]j]j]ujjMj]rWjX iblConfig.outrXrY}rZ(jUjjTubajjubjX(. This utility program is located under:r[r\}r](jX(. This utility program is located under:jjMubeubj)r^}r_(jXY[SDK Install Path]/pdk__/packages/ti/boot/ibl/src/util/iblConfig/buildjjjj}jjj}r`(j@jAj]j]j]j]j]ujM*jhj]rajXY[SDK Install Path]/pdk__/packages/ti/boot/ibl/src/util/iblConfig/buildrbrc}rd(jUjj^ubaubj)re}rf(jXIn command line, use "make" with the given Makefile to generate iblConfig.out and input.txt. Please be sure to fill in the parameters for input.txt before running iblConfig.out; below is an example of input.txt:rgjjjj}jjj}rh(j]j]j]j]j]ujMujhj]rijXIn command line, use "make" with the given Makefile to generate iblConfig.out and input.txt. Please be sure to fill in the parameters for input.txt before running iblConfig.out; below is an example of input.txt:rjrk}rl(jjgjjeubaubj)rm}rn(jXfile_name = ibl.bin SOC = 6 offset = 0x500 ethBoot-doBootp = TRUE ethBoot-bootFormat = ibl_BOOT_FORMAT_ELF ethBoot-ipAddr = 192.168.1.3 ethBoot-serverIp = 192.168.1.2 ethBoot-gatewayIp = 192.168.1.1 ethBoot-netmask = 255.255.255.0 ethBoot-fileName =jjjj}jjj}ro(j@jAj]j]j]j]j]ujM*jhj]rpjXfile_name = ibl.bin SOC = 6 offset = 0x500 ethBoot-doBootp = TRUE ethBoot-bootFormat = ibl_BOOT_FORMAT_ELF ethBoot-ipAddr = 192.168.1.3 ethBoot-serverIp = 192.168.1.2 ethBoot-gatewayIp = 192.168.1.1 ethBoot-netmask = 255.255.255.0 ethBoot-fileName =rqrr}rs(jUjjmubaubj)rt}ru(jXCThe first 3 parameters must be filled in for iblConfig.out to work:rvjjjj}jjj}rw(j]j]j]j]j]ujMjhj]rxjXCThe first 3 parameters must be filled in for iblConfig.out to work:ryrz}r{(jjvjjtubaubjt)r|}r}(jUjjjj}jjwj}r~(jyX-j]j]j]j]j]ujMjhj]r(j{)r}r(jXlfile_name refers to the IBL binary file to update. This file must be in the same directory as iblConfig.out.jj|jj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXlfile_name refers to the IBL binary file to update. This file must be in the same directory as iblConfig.out.rjjjj}jjj}r(j]j]j]j]j]ujMj]rjXlfile_name refers to the IBL binary file to update. This file must be in the same directory as iblConfig.out.rr}r(jjjjubaubaubj{)r}r(jXPSOC refers to the SOC being used. Please enter **6 for C6678, and 8 for C6657**.jj|jj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXPSOC refers to the SOC being used. Please enter **6 for C6678, and 8 for C6657**.jjjj}jjj}r(j]j]j]j]j]ujMj]r(jX/SOC refers to the SOC being used. Please enter rr}r(jX/SOC refers to the SOC being used. Please enter jjubj)r}r(jX **6 for C6678, and 8 for C6657**j}r(j]j]j]j]j]ujjj]rjX6 for C6678, and 8 for C6657rr}r(jUjjubajjubjX.r}r(jX.jjubeubaubj{)r}r(jXUoffset refers to an offset space in the IBL. The value is 0x500 for C6678, and C6657 jj|jj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXToffset refers to an offset space in the IBL. The value is 0x500 for C6678, and C6657rjjjj}jjj}r(j]j]j]j]j]ujMj]rjXToffset refers to an offset space in the IBL. The value is 0x500 for C6678, and C6657rr}r(jjjjubaubaubeubj)r}r(jXThe ethernet parameters (the entries beginning with ethBoot) refer to specific ethernet configurations. If they are not specified, they will be defaulted to the values in the [SDK Install Path]/pdk__/packages/ti/boot/ibl/src/util/iblConfig/src/SOC.h file. In the example above, the ethernet boot file name will be defaulted to c6678-le.bin when iblConfig.out is run.rjjjj}jjj}r(j]j]j]j]j]ujMjhj]rjXThe ethernet parameters (the entries beginning with ethBoot) refer to specific ethernet configurations. If they are not specified, they will be defaulted to the values in the [SDK Install Path]/pdk__/packages/ti/boot/ibl/src/util/iblConfig/src/SOC.h file. In the example above, the ethernet boot file name will be defaulted to c6678-le.bin when iblConfig.out is run.rr}r(jjjjubaubj)r}r(jX`After running iblConfig.out and updating the IBL binary, you must flash the modified IBL binary to your EVM. You can do this as part of program_evm (refer to `Processor SDK Flashing Bootable Images `__) or you can flash it individually using eepromwriter (refer to "Flash Writers" section above).jjjj}jjj}r(j]j]j]j]j]ujMjhj]r(jXAfter running iblConfig.out and updating the IBL binary, you must flash the modified IBL binary to your EVM. You can do this as part of program_evm (refer to rr}r(jXAfter running iblConfig.out and updating the IBL binary, you must flash the modified IBL binary to your EVM. You can do this as part of program_evm (refer to jjubj)r}r(jXc`Processor SDK Flashing Bootable Images `__j}r(UnameX&Processor SDK Flashing Bootable ImagesjX6http://processors.wiki.ti.com/index.php/Program_EVM_UGj]j]j]j]j]ujjj]rjX&Processor SDK Flashing Bootable Imagesrr}r(jUjjubajjubjX_) or you can flash it individually using eepromwriter (refer to "Flash Writers" section above).rºrú}rĺ(jX_) or you can flash it individually using eepromwriter (refer to "Flash Writers" section above).jjubeubj)rź}rƺ(jXIf you updated the IBL with iblConfig and flashed it with eepromwriter, you should **NOT** use i2cparam_0x51_c667#_le_0x500.out and iblConfig.gel - this would overwrite the changes you made to the IBL.jjjj}jjj}rǺ(j]j]j]j]j]ujNjhj]rȺj)rɺ}rʺ(jXIf you updated the IBL with iblConfig and flashed it with eepromwriter, you should **NOT** use i2cparam_0x51_c667#_le_0x500.out and iblConfig.gel - this would overwrite the changes you made to the IBL.jjźjj}jjj}r˺(j]j]j]j]j]ujMj]r̺(jXSIf you updated the IBL with iblConfig and flashed it with eepromwriter, you should rͺrκ}rϺ(jXSIf you updated the IBL with iblConfig and flashed it with eepromwriter, you should jjɺubj)rк}rѺ(jX**NOT**j}rҺ(j]j]j]j]j]ujjɺj]rӺjXNOTrԺrպ}rֺ(jUjjкubajjubjXo use i2cparam_0x51_c667#_le_0x500.out and iblConfig.gel - this would overwrite the changes you made to the IBL.r׺rغ}rٺ(jXo use i2cparam_0x51_c667#_le_0x500.out and iblConfig.gel - this would overwrite the changes you made to the IBL.jjɺubeubaubeubj)rں}rۺ(jUjKjjjj}jjj}rܺ(j]rݺX compilationr޺aj]j]j]rߺUid95raj]ujMjhj]r(j)r}r(jX Compilationrjjںjj}jjj}r(j]j]j]j]j]ujMjhj]rjX Compilationrr}r(jjjjubaubj)r}r(jXbcd [SDK Install Path]/pdk__/packages/ti/boot/i2c/tftp//build make alljjںjj}jjj}r(j@jAj]j]j]j]j]ujM*jhj]rjXbcd [SDK Install Path]/pdk__/packages/ti/boot/i2c/tftp//build make allrr}r(jUjjubaubeubj)r}r(jUjKjjjj}jjj}r(j]rXusageraj]j]j]rUid96raj]ujMjhj]r(j)r}r(jXUsagerjjjj}jjj}r(j]j]j]j]j]ujMjhj]rjXUsagerr}r(jjjjubaubj)r}r(jXAfter your IBL ethernet settings are configured correctly and flashed into EEPROM memory, follow these steps to continue the TFTP booting process:rjjjj}jjj}r(j]j]j]j]j]ujMjhj]rjXAfter your IBL ethernet settings are configured correctly and flashed into EEPROM memory, follow these steps to continue the TFTP booting process:rr}r(jjjjubaubj )r }r (jUjjjj}jj j}r (jU.j]j]j]jUj]j]jjujMjhj]r (j{)r }r(jXStart a TFTP server on your local PC. Your local PC will be the one sending the image to be booted, so make sure your PC and EVM are connected to the same subnet via ethernetjj jj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXStart a TFTP server on your local PC. Your local PC will be the one sending the image to be booted, so make sure your PC and EVM are connected to the same subnet via ethernetrjj jj}jjj}r(j]j]j]j]j]ujMj]rjXStart a TFTP server on your local PC. Your local PC will be the one sending the image to be booted, so make sure your PC and EVM are connected to the same subnet via ethernetrr}r(jjjjubaubaubj{)r}r(jX]Copy i2ctftpboot_.out (refer to compilation step above) to your base TFTP directoryjj jj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX]Copy i2ctftpboot_.out (refer to compilation step above) to your base TFTP directoryrjjjj}jjj}r (j]j]j]j]j]ujMj]r!jX]Copy i2ctftpboot_.out (refer to compilation step above) to your base TFTP directoryr"r#}r$(jjjjubaubaubj{)r%}r&(jX,Rename i2ctftpboot_.out to app.outr'jj jj}jjj}r((j]j]j]j]j]ujNjhj]r)j)r*}r+(jj'jj%jj}jjj}r,(j]j]j]j]j]ujMj]r-jX,Rename i2ctftpboot_.out to app.outr.r/}r0(jj'jj*ubaubaubj{)r1}r2(jXSet the IP address of the PC that is running the TFTP server to 192.168.2.101, since by default IBL will set the EVM IP address to 192.168.2.100 and the TFTP server IP address to 192.168.2.101jj jj}jjj}r3(j]j]j]j]j]ujNjhj]r4j)r5}r6(jXSet the IP address of the PC that is running the TFTP server to 192.168.2.101, since by default IBL will set the EVM IP address to 192.168.2.100 and the TFTP server IP address to 192.168.2.101r7jj1jj}jjj}r8(j]j]j]j]j]ujMj]r9jXSet the IP address of the PC that is running the TFTP server to 192.168.2.101, since by default IBL will set the EVM IP address to 192.168.2.100 and the TFTP server IP address to 192.168.2.101r:r;}r<(jj7jj5ubaubaubj{)r=}r>(jX/Set EVM to TFTP boot mode and power on the EVM jj jj}jjj}r?(j]j]j]j]j]ujNjhj]r@j)rA}rB(jX.Set EVM to TFTP boot mode and power on the EVMrCjj=jj}jjj}rD(j]j]j]j]j]ujMj]rEjX.Set EVM to TFTP boot mode and power on the EVMrFrG}rH(jjCjjAubaubaubeubj)rI}rJ(jXeYour PC will send the application image to the EVM to boot. Open an UART terminal to view the output.rKjjjj}jjj}rL(j]j]j]j]j]ujMjhj]rMjXeYour PC will send the application image to the EVM to boot. Open an UART terminal to view the output.rNrO}rP(jjKjjIubaubeubeubj)rQ}rR(jUjjjj}jjj}rS(j]j]j]j]rTU post-bootrUaj]rVhaujMjhj]rW(j)rX}rY(jX POST BootrZjjQjj}jjj}r[(j]j]j]j]j]ujMjhj]r\jX POST Bootr]r^}r_(jjZjjXubaubj)r`}ra(jX}POST (Power On Self Test) Boot is designed to do a quick self-diagnostic upon boot. The POST application itself is located inrbjjQjj}jjj}rc(j]j]j]j]j]ujMjhj]rdjX}POST (Power On Self Test) Boot is designed to do a quick self-diagnostic upon boot. The POST application itself is located inrerf}rg(jjbjj`ubaubj)rh}ri(jXA[SDK Install Path]/pdk__/packages/ti/boot/postjjQjj}jjj}rj(j@jAj]j]j]j]j]ujM*jhj]rkjXA[SDK Install Path]/pdk__/packages/ti/boot/postrlrm}rn(jUjjhubaubj)ro}rp(jXThis application should already be compiled and flashed into EEPROM out-of-box. Below instructions are for re-compilation or re-flashing only.rqjjQjj}jjj}rr(j]j]j]j]j]ujMjhj]rsjXThis application should already be compiled and flashed into EEPROM out-of-box. Below instructions are for re-compilation or re-flashing only.rtru}rv(jjqjjoubaubj)rw}rx(jUjKjjQjj}jjj}ry(j]rzX compilationr{aj]j]j]r|Uid97r}aj]ujMjhj]r~(j)r}r(jX Compilationrjjwjj}jjj}r(j]j]j]j]j]ujMjhj]rjX Compilationrr}r(jjjjubaubj)r}r(jXcd [SDK Install Path]/pdk__/packages/ti/boot/post//build make all cd [SDK Install Path]/pdk__/packages/ti/boot/post//bin ./post_romparse.shjjwjj}jjj}r(j@jAj]j]j]j]j]ujM*jhj]rjXcd [SDK Install Path]/pdk__/packages/ti/boot/post//build make all cd [SDK Install Path]/pdk__/packages/ti/boot/post//bin ./post_romparse.shrr}r(jUjjubaubj)r}r(jXuNote: You would need to use post_romparse.bat instead of the \*.sh version if your host system is running on Windows.jjwjj}jjj}r(j]j]j]j]j]ujMjhj]rjXtNote: You would need to use post_romparse.bat instead of the *.sh version if your host system is running on Windows.rr}r(jXuNote: You would need to use post_romparse.bat instead of the \*.sh version if your host system is running on Windows.jjubaubeubj)r}r(jUjKjjQjj}jjj}r(j]rXusageraj]j]j]rUid98raj]ujMjhj]r(j)r}r(jXUsagerjjjj}jjj}r(j]j]j]j]j]ujMjhj]rjXUsagerr}r(jjjjubaubj)r}r(jX%To flash the POST binary into EEPROM:rjjjj}jjj}r(j]j]j]j]j]ujMjhj]rjX%To flash the POST binary into EEPROM:rr}r(jjjjubaubj )r}r(jUjjjj}jj j}r(jU.j]j]j]jUj]j]jjujMjhj]r(j{)r}r(jXqRefer to above Flash Writers section on flashing EEPROM memory. The binary you are flashing is "post_i2crom.bin".jjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXqRefer to above Flash Writers section on flashing EEPROM memory. The binary you are flashing is "post_i2crom.bin".rjjjj}jjj}r(j]j]j]j]j]ujMj]rjXqRefer to above Flash Writers section on flashing EEPROM memory. The binary you are flashing is "post_i2crom.bin".rr}r(jjjjubaubaubj{)r}r(jXBefore running the last step of the EEPROM flashing instruction to run the DSP core, modify the **eepromwriter_input.txt** to use **0x50** for the bus_addr field. The **eepromwriter_input.txt** file is located in: jjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r»(jXBefore running the last step of the EEPROM flashing instruction to run the DSP core, modify the **eepromwriter_input.txt** to use **0x50** for the bus_addr field. The **eepromwriter_input.txt** file is located in:jjjj}jjj}rû(j]j]j]j]j]ujMj]rĻ(jX`Before running the last step of the EEPROM flashing instruction to run the DSP core, modify the rŻrƻ}rǻ(jX`Before running the last step of the EEPROM flashing instruction to run the DSP core, modify the jjubj)rȻ}rɻ(jX**eepromwriter_input.txt**j}rʻ(j]j]j]j]j]ujjj]r˻jXeepromwriter_input.txtr̻rͻ}rλ(jUjjȻubajjubjX to use rϻrл}rѻ(jX to use jjubj)rһ}rӻ(jX**0x50**j}rԻ(j]j]j]j]j]ujjj]rջjX0x50rֻr׻}rػ(jUjjһubajjubjX for the bus_addr field. The rٻrڻ}rۻ(jX for the bus_addr field. The jjubj)rܻ}rݻ(jX**eepromwriter_input.txt**j}r޻(j]j]j]j]j]ujjj]r߻jXeepromwriter_input.txtrr}r(jUjjܻubajjubjX file is located in:rr}r(jX file is located in:jjubeubaubeubj)r}r(jXU[SDK Install Path]/pdk__/packages/ti/boot/writers/eeprom//binjjjj}jjj}r(j@jAj]j]j]j]j]ujM+jhj]rjXU[SDK Install Path]/pdk__/packages/ti/boot/writers/eeprom//binrr}r(jUjjubaubj)r}r(jXConfigure your EVM's DIP Switches accordingly to I2C POST BOOT mode. The POST application will be loaded from EEPROM 0x50 and output will be available over the UART serial console.rjjjj}jjj}r(j]j]j]j]j]ujMjhj]rjXConfigure your EVM's DIP Switches accordingly to I2C POST BOOT mode. The POST application will be loaded from EEPROM 0x50 and output will be available over the UART serial console.rr}r(jjjjubaubjc)r}r(jUjjjj}jjfj}r(j]j]j]j]j]ujMjhj]rji)r}r(jUjlKjjjj}jjj}r(j]j]j]j]j]ujKjhj]ubaubeubeubj)r}r(jUjjjj}jjj}r(j]j]j]j]rU ethernet-bootraj]rhaujMjhj]r(j)r}r(jX ETHERNET Bootrjjjj}jjj}r(j]j]j]j]j]ujMjhj]rjX ETHERNET Bootrr }r (jjjjubaubj)r }r (jXETHERNET Boot uses Ethernet sockets to transfer a bootable image from a host to the EVM. After powering on in Ethernet boot mode, the EVM will send BOOTP packets at regular interval - this gives visibility of the MAC ID of the EVM to the network.r jjjj}jjj}r(j]j]j]j]j]ujMjhj]rjXETHERNET Boot uses Ethernet sockets to transfer a bootable image from a host to the EVM. After powering on in Ethernet boot mode, the EVM will send BOOTP packets at regular interval - this gives visibility of the MAC ID of the EVM to the network.rr}r(jj jj ubaubj)r}r(jX{Below are instructions on compiling and running an example to send a simple program to the EVM while in Ethernet boot mode.rjjjj}jjj}r(j]j]j]j]j]ujMjhj]rjX{Below are instructions on compiling and running an example to send a simple program to the EVM while in Ethernet boot mode.rr}r(jjjjubaubj)r}r(jUjKjjjj}jjj}r(j]rX compilationraj]j]j]r Uid99r!aj]ujMjhj]r"(j)r#}r$(jX Compilationr%jjjj}jjj}r&(j]j]j]j]j]ujMjhj]r'jX Compilationr(r)}r*(jj%jj#ubaubj)r+}r,(jXcd [SDK Install Path]/pdk__/packages/ti/boot/examples/ethernet/Utilities make all cd [SDK Install Path]/pdk__/packages/ti/boot/examples/ethernet/simple make alljjjj}jjj}r-(j@jAj]j]j]j]j]ujM+jhj]r.jXcd [SDK Install Path]/pdk__/packages/ti/boot/examples/ethernet/Utilities make all cd [SDK Install Path]/pdk__/packages/ti/boot/examples/ethernet/simple make allr/r0}r1(jUjj+ubaubeubj)r2}r3(jUjKjjjj}jjj}r4(j]r5Xusager6aj]j]j]r7Uid100r8aj]ujMjhj]r9(j)r:}r;(jXUsager<jj2jj}jjj}r=(j]j]j]j]j]ujMjhj]r>jXUsager?r@}rA(jj<jj:ubaubj )rB}rC(jUjj2jj}jj j}rD(jU.j]j]j]jUj]j]jjujM jhj]rE(j{)rF}rG(jXSet the EVM's DIP switches to Ethernet boot mode. Connect Ethernet cables such that the EVM and your Host PC are on the same network.jjBjj}jjj}rH(j]j]j]j]j]ujNjhj]rIj)rJ}rK(jXSet the EVM's DIP switches to Ethernet boot mode. Connect Ethernet cables such that the EVM and your Host PC are on the same network.rLjjFjj}jjj}rM(j]j]j]j]j]ujM j]rNjXSet the EVM's DIP switches to Ethernet boot mode. Connect Ethernet cables such that the EVM and your Host PC are on the same network.rOrP}rQ(jjLjjJubaubaubj{)rR}rS(jXPower on the EVM. The EVM will start sending BOOTP packets. Read the packets for the EVM's MAC ID. You can read the packet by using a network tool such as Wireshark.jjBjj}jjj}rT(j]j]j]j]j]ujNjhj]rUj)rV}rW(jXPower on the EVM. The EVM will start sending BOOTP packets. Read the packets for the EVM's MAC ID. You can read the packet by using a network tool such as Wireshark.rXjjRjj}jjj}rY(j]j]j]j]j]ujM j]rZjXPower on the EVM. The EVM will start sending BOOTP packets. Read the packets for the EVM's MAC ID. You can read the packet by using a network tool such as Wireshark.r[r\}r](jjXjjVubaubaubj{)r^}r_(jXcOn your Host PC, add an ARP entry to associate the EVM's MAC ID with an IP address on your network.jjBjj}jjj}r`(j]j]j]j]j]ujNjhj]raj)rb}rc(jXcOn your Host PC, add an ARP entry to associate the EVM's MAC ID with an IP address on your network.rdjj^jj}jjj}re(j]j]j]j]j]ujMj]rfjXcOn your Host PC, add an ARP entry to associate the EVM's MAC ID with an IP address on your network.rgrh}ri(jjdjjbubaubaubj{)rj}rk(jXoUse the pcsendpkt utility provided to send the simple.eth program compiled in the compilation step to the EVM. jjBjj}jjj}rl(j]j]j]j]j]ujNjhj]rmj)rn}ro(jXnUse the pcsendpkt utility provided to send the simple.eth program compiled in the compilation step to the EVM.rpjjjjj}jjj}rq(j]j]j]j]j]ujMj]rrjXnUse the pcsendpkt utility provided to send the simple.eth program compiled in the compilation step to the EVM.rsrt}ru(jjpjjnubaubaubeubj)rv}rw(jXTo use pcsendpkt:rxjj2jj}jjj}ry(j]j]j]j]j]ujMjhj]rzjXTo use pcsendpkt:r{r|}r}(jjxjjvubaubj)r~}r(jXcd [SDK Install Path]/pdk__/packages/ti/boot/examples/ethernet/Utilities pcsendpkt simple.eth jj2jj}jjj}r(j@jAj]j]j]j]j]ujM1+jhj]rjXcd [SDK Install Path]/pdk__/packages/ti/boot/examples/ethernet/Utilities pcsendpkt simple.eth rr}r(jUjj~ubaubj)r}r(jXC** is the IP address you assigned the EVM in step 3rjj2jj}jjj}r(j]j]j]j]j]ujMjhj]r(jM)r}r(jX**j}r(j]j]j]j]j]ujjj]rjXrr}r(jUjjubajjUubjX1 is the IP address you assigned the EVM in step 3rr}r(jX1 is the IP address you assigned the EVM in step 3jjubeubj)r}r(jX If you are on a Linux Host PC, you may need to recompile pcsendpkt locally with GCC To verify, connect to the EVM's Core 0 via CCS and check that the A1 register is set to 0x11223344jj2jj}jjj}r(j]j]j]j]j]ujNjhj]r(j3)r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXSIf you are on a Linux Host PC, you may need to recompile pcsendpkt locally with GCCrjjjj}jjj}r(j]j]j]j]j]ujMj]rjXSIf you are on a Linux Host PC, you may need to recompile pcsendpkt locally with GCCrr}r(jjjjubaubajj6ubj)r}r(jXbTo verify, connect to the EVM's Core 0 via CCS and check that the A1 register is set to 0x11223344rjjjj}jjj}r(j]j]j]j]j]ujM j]rjXbTo verify, connect to the EVM's Core 0 via CCS and check that the A1 register is set to 0x11223344rr}r(jjjjubaubeubjc)r}r(jUjj2jj}jjfj}r(j]j]j]j]j]ujM#jhj]rji)r}r(jUjlKjjjj}jjj}r(j]j]j]j]j]ujKjhj]ubaubeubeubj)r}r(jUjjjj}jjj}r(j]j]j]j]rU srio-bootraj]rhaujM&jhj]r(j)r}r(jX SRIO Bootrjjjj}jjj}r(j]j]j]j]j]ujM&jhj]rjX SRIO Bootrr}r(jjjjubaubj)r¼}rü(jXdSRIO boot will attempt to load and run a binary image received via SRIO. An example can be found in:rļjjjj}jjj}rż(j]j]j]j]j]ujM(jhj]rƼjXdSRIO boot will attempt to load and run a binary image received via SRIO. An example can be found in:rǼrȼ}rɼ(jjļjj¼ubaubj)rʼ}r˼(jXJ[SDK Install Path]/pdk__/packages/ti/boot/examples/sriojjjj}jjj}r̼(j@jAj]j]j]j]j]ujMF+jhj]rͼjXJ[SDK Install Path]/pdk__/packages/ti/boot/examples/sriorμrϼ}rм(jUjjʼubaubj)rѼ}rҼ(jXFBelow are instructions on compiling and running the SRIO boot example.rӼjjjj}jjj}rԼ(j]j]j]j]j]ujM/jhj]rռjXFBelow are instructions on compiling and running the SRIO boot example.rּr׼}rؼ(jjӼjjѼubaubj)rټ}rڼ(jUjKjjjj}jjj}rۼ(j]rܼX compilationrݼaj]j]j]r޼Uid101r߼aj]ujM2jhj]r(j)r}r(jX Compilationrjjټjj}jjj}r(j]j]j]j]j]ujM2jhj]rjX Compilationrr}r(jjjjubaubj)r}r(jXcd [SDK Install Path]/pdk__/packages/ti/boot/examples/srio/srioboot_ddrinit//build make all cd [SDK Install Path]/pdk__/packages/ti/boot/examples/srio/srioboot_ddrinit//bin ./srioboot_ddrinit_elf2HBin.sh cd [SDK Install Path]/pdk__/packages/ti/boot/examples/srio/srioboot_helloworld//build make all cd [SDK Install Path]/pdk__/packages/ti/boot/examples/srio/srioboot_helloworld//bin ./helloworld_elf2HBin.sh cd [SDK Install Path]/pdk__/packages/ti/boot/examples/srio/srioboot_example//build make alljjټjj}jjj}r(j@jAj]j]j]j]j]ujMO+jhj]rjXcd [SDK Install Path]/pdk__/packages/ti/boot/examples/srio/srioboot_ddrinit//build make all cd [SDK Install Path]/pdk__/packages/ti/boot/examples/srio/srioboot_ddrinit//bin ./srioboot_ddrinit_elf2HBin.sh cd [SDK Install Path]/pdk__/packages/ti/boot/examples/srio/srioboot_helloworld//build make all cd [SDK Install Path]/pdk__/packages/ti/boot/examples/srio/srioboot_helloworld//bin ./helloworld_elf2HBin.sh cd [SDK Install Path]/pdk__/packages/ti/boot/examples/srio/srioboot_example//build make allrr}r(jUjjubaubj)r}r(jXNote: You would need to use srioboot_ddrinit_elf2HBin.bat and helloworld_elf2HBin.bat instead of their \*.sh version respectively if your host system is running on Windows. Compilation of the projects should be done in the order stated above.jjټjj}jjj}r(j]j]j]j]j]ujMAjhj]rjXNote: You would need to use srioboot_ddrinit_elf2HBin.bat and helloworld_elf2HBin.bat instead of their *.sh version respectively if your host system is running on Windows. Compilation of the projects should be done in the order stated above.rr}r(jXNote: You would need to use srioboot_ddrinit_elf2HBin.bat and helloworld_elf2HBin.bat instead of their \*.sh version respectively if your host system is running on Windows. Compilation of the projects should be done in the order stated above.jjubaubeubj)r}r(jUjKjjjj}jjj}r(j]rXusageraj]j]j]rUid102raj]ujMGjhj]r(j)r}r(jXUsagerjjjj}jjj}r(j]j]j]j]j]ujMGjhj]rjXUsagerr}r(jjjjubaubj)r}r(jX`You will need to have 2 EVMs - both should be set to SRIO boot mode. The two EVMs will be connected through the AMC breakout board (lane x of one slot should be connected to lane x of the other breakout slot). One EVM will be acting as the host (referred to as the HOST EVM) and the other EVM will be doing the booting (referred to as the BOOTING EVM).r jjjj}jjj}r (j]j]j]j]j]ujMIjhj]r jX`You will need to have 2 EVMs - both should be set to SRIO boot mode. The two EVMs will be connected through the AMC breakout board (lane x of one slot should be connected to lane x of the other breakout slot). One EVM will be acting as the host (referred to as the HOST EVM) and the other EVM will be doing the booting (referred to as the BOOTING EVM).r r }r(jj jjubaubj )r}r(jUjjjj}jj j}r(jU.j]j]j]jUj]j]jjujMOjhj]r(j{)r}r(jX%Compile srioboot_example_evm66XXl.outrjjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj}jjj}r(j]j]j]j]j]ujMOj]rjX%Compile srioboot_example_evm66XXl.outrr}r(jjjjubaubaubj{)r}r (jXLConnect the BOOTING EVM's UART serial port to your PC using the RS-232 cablejjjj}jjj}r!(j]j]j]j]j]ujNjhj]r"j)r#}r$(jXLConnect the BOOTING EVM's UART serial port to your PC using the RS-232 cabler%jjjj}jjj}r&(j]j]j]j]j]ujMPj]r'jXLConnect the BOOTING EVM's UART serial port to your PC using the RS-232 cabler(r)}r*(jj%jj#ubaubaubj{)r+}r,(jX'Connect a JTAG emulator on the HOST EVMr-jjjj}jjj}r.(j]j]j]j]j]ujNjhj]r/j)r0}r1(jj-jj+jj}jjj}r2(j]j]j]j]j]ujMRj]r3jX'Connect a JTAG emulator on the HOST EVMr4r5}r6(jj-jj0ubaubaubj{)r7}r8(jXPower on both EVMsr9jjjj}jjj}r:(j]j]j]j]j]ujNjhj]r;j)r<}r=(jj9jj7jj}jjj}r>(j]j]j]j]j]ujMSj]r?jXPower on both EVMsr@rA}rB(jj9jj<ubaubaubj{)rC}rD(jXOpen an UART terminal to view the BOOTING EVM's output. (Remember to set the baud rate to 115.2k bps, 8-bit data, no parity, 1-bit stop, and no flow control)jjjj}jjj}rE(j]j]j]j]j]ujNjhj]rFj)rG}rH(jXOpen an UART terminal to view the BOOTING EVM's output. (Remember to set the baud rate to 115.2k bps, 8-bit data, no parity, 1-bit stop, and no flow control)rIjjCjj}jjj}rJ(j]j]j]j]j]ujMTj]rKjXOpen an UART terminal to view the BOOTING EVM's output. (Remember to set the baud rate to 115.2k bps, 8-bit data, no parity, 1-bit stop, and no flow control)rLrM}rN(jjIjjGubaubaubj{)rO}rP(jXConnect to the HOST EVM via Code Composer Studio (CCS is recommended to be version 6 or higher). Launch target configuration for your HOST EVM and connect to DSP0.jjjj}jjj}rQ(j]j]j]j]j]ujNjhj]rRj)rS}rT(jXConnect to the HOST EVM via Code Composer Studio (CCS is recommended to be version 6 or higher). Launch target configuration for your HOST EVM and connect to DSP0.rUjjOjj}jjj}rV(j]j]j]j]j]ujMWj]rWjXConnect to the HOST EVM via Code Composer Studio (CCS is recommended to be version 6 or higher). Launch target configuration for your HOST EVM and connect to DSP0.rXrY}rZ(jjUjjSubaubaubj{)r[}r\(jX<Load and run srioboot_example_evm66xxl.out on your HOST EVM jjjj}jjj}r](j]j]j]j]j]ujNjhj]r^j)r_}r`(jX;Load and run srioboot_example_evm66xxl.out on your HOST EVMrajj[jj}jjj}rb(j]j]j]j]j]ujMZj]rcjX;Load and run srioboot_example_evm66xxl.out on your HOST EVMrdre}rf(jjajj_ubaubaubeubj)rg}rh(jX-CCS console for your HOST EVM should display:rijjjj}jjj}rj(j]j]j]j]j]ujM\jhj]rkjX-CCS console for your HOST EVM should display:rlrm}rn(jjijjgubaubj)ro}rp(jX[C66xx_0] SRIO Boot Host Example Version 01.00.00.01 [C66xx_0] [C66xx_0] Transfer DDR init code via SRIO successfully [C66xx_0] Transfer boot code via SRIO successfullyjjjj}jjj}rq(j@jAj]j]j]j]j]ujMy+jhj]rrjX[C66xx_0] SRIO Boot Host Example Version 01.00.00.01 [C66xx_0] [C66xx_0] Transfer DDR init code via SRIO successfully [C66xx_0] Transfer boot code via SRIO successfullyrsrt}ru(jUjjoubaubj)rv}rw(jX-Terminal for your BOOTING EVM should display:rxjjjj}jjj}ry(j]j]j]j]j]ujMejhj]rzjX-Terminal for your BOOTING EVM should display:r{r|}r}(jjxjjvubaubj)r~}r(jXSRIO Boot Hello World Example Version 01.00.00.01 Booting Hello World image on Core 0 from SRIO ... Booting Hello World image on Core 1 from Core 0 ... Booting Hello World image on Core 2 from Core 0 ... Booting Hello World image on Core 3 from Core 0 ... Booting Hello World image on Core 4 from Core 0 ... Booting Hello World image on Core 5 from Core 0 ... Booting Hello World image on Core 6 from Core 0 ... Booting Hello World image on Core 7 from Core 0 ...jjjj}jjj}r(j@jAj]j]j]j]j]ujM+jhj]rjXSRIO Boot Hello World Example Version 01.00.00.01 Booting Hello World image on Core 0 from SRIO ... Booting Hello World image on Core 1 from Core 0 ... Booting Hello World image on Core 2 from Core 0 ... Booting Hello World image on Core 3 from Core 0 ... Booting Hello World image on Core 4 from Core 0 ... Booting Hello World image on Core 5 from Core 0 ... Booting Hello World image on Core 6 from Core 0 ... Booting Hello World image on Core 7 from Core 0 ...rr}r(jUjj~ubaubeubeubj)r}r(jUjjjj}jjj}r(j]j]j]j]rU pcie-bootraj]rjaujMtjhj]r(j)r}r(jX PCIE Bootrjjjj}jjj}r(j]j]j]j]j]ujMtjhj]rjX PCIE Bootrr}r(jjjjubaubj)r}r(jX[PCIE boot will attempt to load and run a binary image upon enumeration. Example is located:rjjjj}jjj}r(j]j]j]j]j]ujMvjhj]rjX[PCIE boot will attempt to load and run a binary image upon enumeration. Example is located:rr}r(jjjjubaubj)r}r(jXJ[SDK Install Path]/pdk__/packages/ti/boot/examples/pciejjjj}jjj}r(j@jAj]j]j]j]j]ujM+jhj]rjXJ[SDK Install Path]/pdk__/packages/ti/boot/examples/pcierr}r(jUjjubaubj)r}r(jXFBelow are instructions on compiling and running the PCIE boot example.rjjjj}jjj}r(j]j]j]j]j]ujM}jhj]rjXFBelow are instructions on compiling and running the PCIE boot example.rr}r(jjjjubaubj)r}r(jUjKjjjj}jjj}r(j]rX compilationraj]j]j]rUid103raj]ujMjhj]r(j)r}r(jX Compilationrjjjj}jjj}r(j]j]j]j]j]ujMjhj]rjX Compilationrr}r(jjjjubaubj)r}r(jXcd [SDK Install Path]/pdk__/packages/ti/boot/examples/pcie/pcieboot_ddrinit//build make all cd [SDK Install Path]/pdk__/packages/ti/boot/examples/pcie/pcieboot_helloworld//build make alljjjj}jjj}r(j@jAj]j]j]j]j]ujM+jhj]rjXcd [SDK Install Path]/pdk__/packages/ti/boot/examples/pcie/pcieboot_ddrinit//build make all cd [SDK Install Path]/pdk__/packages/ti/boot/examples/pcie/pcieboot_helloworld//build make allrr}r(jUjjubaubj)r½}rý(jXAdditionally for C6678 EVM:rĽjjjj}jjj}rŽ(j]j]j]j]j]ujMjhj]rƽjXAdditionally for C6678 EVM:rǽrȽ}rɽ(jjĽjj½ubaubj)rʽ}r˽(jXcd [SDK Install Path]/pdk__/packages/ti/boot/examples/pcie/pcieboot_interrupt//build make all cd [SDK Install Path]/pdk__/packages/ti/boot/examples/pcie/pcieboot_localreset//build make alljjjj}jjj}r̽(j@jAj]j]j]j]j]ujM+jhj]rͽjXcd [SDK Install Path]/pdk__/packages/ti/boot/examples/pcie/pcieboot_interrupt//build make all cd [SDK Install Path]/pdk__/packages/ti/boot/examples/pcie/pcieboot_localreset//build make allrνrϽ}rн(jUjjʽubaubj)rѽ}rҽ(jXThe POST application can also be used as a PCIE Boot example. Run the corresponding \*_elf2HBin.bat (or .sh) to convert the .out files into PCIE bootable binaries.jjjj}jjj}rӽ(j]j]j]j]j]ujMjhj]rԽjXThe POST application can also be used as a PCIE Boot example. Run the corresponding *_elf2HBin.bat (or .sh) to convert the .out files into PCIE bootable binaries.rսrֽ}r׽(jXThe POST application can also be used as a PCIE Boot example. Run the corresponding \*_elf2HBin.bat (or .sh) to convert the .out files into PCIE bootable binaries.jjѽubaubeubj)rؽ}rٽ(jUjKjjjj}jjj}rڽ(j]r۽Xusagerܽaj]j]j]rݽUid104r޽aj]ujMjhj]r߽(j)r}r(jXUsagerjjؽjj}jjj}r(j]j]j]j]j]ujMjhj]rjXUsagerr}r(jjjjubaubj)r}r(jXAn AMC to PCIE adaptor card, a TMS320C66xxL EVM card and a Linux PC are required to do the test. The test is verified on both TMS320C6670L and TMS320C6678L cards, with both 32-bit and 64-Linux PCs running Ubuntu 10.04. Other Linux OS are expected to work as well.rjjؽjj}jjj}r(j]j]j]j]j]ujMjhj]rjXAn AMC to PCIE adaptor card, a TMS320C66xxL EVM card and a Linux PC are required to do the test. The test is verified on both TMS320C6670L and TMS320C6678L cards, with both 32-bit and 64-Linux PCs running Ubuntu 10.04. Other Linux OS are expected to work as well.rr}r(jjjjubaubjt)r}r(jUjjؽjj}jjwj}r(jyX-j]j]j]j]j]ujMjhj]r(j{)r}r(jXOBefore connect the system, please update IBL with the latest from Processor SDKjjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXOBefore connect the system, please update IBL with the latest from Processor SDKrjjjj}jjj}r(j]j]j]j]j]ujMj]rjXOBefore connect the system, please update IBL with the latest from Processor SDKrr}r(jjjjubaubaubj{)r}r(jX2Set EVM card to PCIE boot (refer to hardware page)rjjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj}jjj}r(j]j]j]j]j]ujMj]rjX2Set EVM card to PCIE boot (refer to hardware page)r r }r (jjjjubaubaubj{)r }r (jX+Assemble the EVM card into the adaptor cardrjjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjj jj}jjj}r(j]j]j]j]j]ujMj]rjX+Assemble the EVM card into the adaptor cardrr}r(jjjjubaubaubj{)r}r(jXNConnect the URAT cable from EVM card to a Linux PC’s USB port or serial portjjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXNConnect the URAT cable from EVM card to a Linux PC’s USB port or serial portrjjjj}jjj}r(j]j]j]j]j]ujMj]r jXNConnect the URAT cable from EVM card to a Linux PC’s USB port or serial portr!r"}r#(jjjjubaubaubj{)r$}r%(jXCompletely shut off the PC power supply (by disconnecting the power cord), insert the AMC adaptor card (with EVM mounted) into an open PCIE slot in PC’s motherboardjjjj}jjj}r&(j]j]j]j]j]ujNjhj]r'j)r(}r)(jXCompletely shut off the PC power supply (by disconnecting the power cord), insert the AMC adaptor card (with EVM mounted) into an open PCIE slot in PC’s motherboardr*jj$jj}jjj}r+(j]j]j]j]j]ujMj]r,jXCompletely shut off the PC power supply (by disconnecting the power cord), insert the AMC adaptor card (with EVM mounted) into an open PCIE slot in PC’s motherboardr-r.}r/(jj*jj(ubaubaubj{)r0}r1(jXCSupply the power to PC, wait for a few seconds and power on the PC.r2jjjj}jjj}r3(j]j]j]j]j]ujNjhj]r4j)r5}r6(jj2jj0jj}jjj}r7(j]j]j]j]j]ujMj]r8jXCSupply the power to PC, wait for a few seconds and power on the PC.r9r:}r;(jj2jj5ubaubaubj{)r<}r=(jXMake sure the PCIE device is correctly enumerated by PC by checking below, note DEVICE_ID field is changed from 0x8888 to 0xb005 which is programmed in IBL.jjjj}jjj}r>(j]j]j]j]j]ujNjhj]r?j)r@}rA(jXMake sure the PCIE device is correctly enumerated by PC by checking below, note DEVICE_ID field is changed from 0x8888 to 0xb005 which is programmed in IBL.rBjj<jj}jjj}rC(j]j]j]j]j]ujMj]rDjXMake sure the PCIE device is correctly enumerated by PC by checking below, note DEVICE_ID field is changed from 0x8888 to 0xb005 which is programmed in IBL.rErF}rG(jjBjj@ubaubaubj{)rH}rI(jXEither enter PC’s BIOS setting when PC is booting up, a new PCIE device should be populated in the PCIE slot where card is inserted, shown as a “Multimedia device”.jjjj}jjj}rJ(j]j]j]j]j]ujNjhj]rKj)rL}rM(jXEither enter PC’s BIOS setting when PC is booting up, a new PCIE device should be populated in the PCIE slot where card is inserted, shown as a “Multimedia device”.rNjjHjj}jjj}rO(j]j]j]j]j]ujMj]rPjXEither enter PC’s BIOS setting when PC is booting up, a new PCIE device should be populated in the PCIE slot where card is inserted, shown as a “Multimedia device”.rQrR}rS(jjNjjLubaubaubj{)rT}rU(jXOr, type “lspci –n” under Linux command shell after Linux OS is loaded, a TI device (VENDOR_ID: 0x104c) should be in the list: jjjj}jjj}rV(j]j]j]j]j]ujNjhj]rWj)rX}rY(jXOr, type “lspci –n” under Linux command shell after Linux OS is loaded, a TI device (VENDOR_ID: 0x104c) should be in the list:rZjjTjj}jjj}r[(j]j]j]j]j]ujMj]r\jXOr, type “lspci –n” under Linux command shell after Linux OS is loaded, a TI device (VENDOR_ID: 0x104c) should be in the list:r]r^}r_(jjZjjXubaubaubeubj)r`}ra(jXlocal-ubuntu:~$ lspci -n 00:00.0 0600: 8086:2774 00:1b.0 0403: 8086:27d8 (rev 01) …. 00:1f.3 0c05: 8086:27da (rev 01) 01:00.0 0480: 104c:b005 (rev 01) 03:00.0 0200: 14e4:1677 (rev 01) Similarly, one can type “lspci”, local-ubuntu:~$ lspci …. 00:1f.3 SMBus: Intel Corporation N10/ICH 7 Family SMBus Controller (rev 01) 01:00.0 Multimedia controller: Texas Instruments Device b005 (rev 01) ....jjؽjj}jjj}rb(j@jAj]j]j]j]j]ujM+jhj]rcjXlocal-ubuntu:~$ lspci -n 00:00.0 0600: 8086:2774 00:1b.0 0403: 8086:27d8 (rev 01) …. 00:1f.3 0c05: 8086:27da (rev 01) 01:00.0 0480: 104c:b005 (rev 01) 03:00.0 0200: 14e4:1677 (rev 01) Similarly, one can type “lspci”, local-ubuntu:~$ lspci …. 00:1f.3 SMBus: Intel Corporation N10/ICH 7 Family SMBus Controller (rev 01) 01:00.0 Multimedia controller: Texas Instruments Device b005 (rev 01) ....rdre}rf(jUjj`ubaubjt)rg}rh(jUjjؽjj}jjwj}ri(jyX-j]j]j]j]j]ujMjhj]rj(j{)rk}rl(jXThe PCIE BARn (n = 0, 1, 2, … , 5) registers are written by Linux PC after enumeration, they should be non-zero. Optionally, if a JTAG emulator is available, one can verify this by looking at address starting from 0x21801010 for 6 32-bit word.jjgjj}jjj}rm(j]j]j]j]j]ujNjhj]rnj)ro}rp(jXThe PCIE BARn (n = 0, 1, 2, … , 5) registers are written by Linux PC after enumeration, they should be non-zero. Optionally, if a JTAG emulator is available, one can verify this by looking at address starting from 0x21801010 for 6 32-bit word.rqjjkjj}jjj}rr(j]j]j]j]j]ujMj]rsjXThe PCIE BARn (n = 0, 1, 2, … , 5) registers are written by Linux PC after enumeration, they should be non-zero. Optionally, if a JTAG emulator is available, one can verify this by looking at address starting from 0x21801010 for 6 32-bit word.rtru}rv(jjqjjoubaubaubj{)rw}rx(jX#Prepare pciedemo.ko in the Linux PCryjjgjj}jjj}rz(j]j]j]j]j]ujNjhj]r{j)r|}r}(jjyjjwjj}jjj}r~(j]j]j]j]j]ujMj]rjX#Prepare pciedemo.ko in the Linux PCrr}r(jjyjj|ubaubaubj{)r}r(jX$On the Linux PC open a new terminal window to run minicom. First run “sudo minicom –s” to set the correct configuration: 115200bps, 8-N-1, Hardware flow control: OFF, Software flow control: OFF, and select the correct Serial Device. Save then run “sudo minicom” to monitor the port.jjgjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX$On the Linux PC open a new terminal window to run minicom. First run “sudo minicom –s” to set the correct configuration: 115200bps, 8-N-1, Hardware flow control: OFF, Software flow control: OFF, and select the correct Serial Device. Save then run “sudo minicom” to monitor the port.rjjjj}jjj}r(j]j]j]j]j]ujMj]rjX$On the Linux PC open a new terminal window to run minicom. First run “sudo minicom –s” to set the correct configuration: 115200bps, 8-N-1, Hardware flow control: OFF, Software flow control: OFF, and select the correct Serial Device. Save then run “sudo minicom” to monitor the port.rr}r(jjjjubaubaubj{)r}r(jX"Type “sudo insmod pciedemo.ko”rjjgjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj}jjj}r(j]j]j]j]j]ujMj]rjX"Type “sudo insmod pciedemo.ko”rr}r(jjjjubaubaubj{)r}r(jXIf a JTAG emulator is available, one can verify that the PC registers for cores other than core 0 should be inside DDR; and magic address for cores other than core 0 should be written with 0xBABEFACE. jjgjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXIf a JTAG emulator is available, one can verify that the PC registers for cores other than core 0 should be inside DDR; and magic address for cores other than core 0 should be written with 0xBABEFACE.rjjjj}jjj}r(j]j]j]j]j]ujMj]rjXIf a JTAG emulator is available, one can verify that the PC registers for cores other than core 0 should be inside DDR; and magic address for cores other than core 0 should be written with 0xBABEFACE.rr}r(jjjjubaubaubeubeubj)r}r(jUjjjj}jjj}r(j]j]j]j]rU,procedure-to-build-and-run-linux-host-loaderraj]rjaujMjhj]r(j)r}r(jX,Procedure to build and run Linux host loaderrjjjj}jjj}r(j]j]j]j]j]ujMjhj]rjX,Procedure to build and run Linux host loaderrr}r(jjjjubaubjt)r}r(jUjjjj}jjwj}r(jyX-j]j]j]j]j]ujMjhj]r(j{)r}r(jXCreate a folder (e.g. pcie_test) in a Linux machine. Copy pciedemo.c, Makefile, pcieDdrInit_66xx.h, pcieBootCode_66xx.h, pcieInterrupt_66xx.h and post_66xx.h from tools\boot_loader\examples\pcie\linux_host_loader to the folder.jjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXCreate a folder (e.g. pcie_test) in a Linux machine. Copy pciedemo.c, Makefile, pcieDdrInit_66xx.h, pcieBootCode_66xx.h, pcieInterrupt_66xx.h and post_66xx.h from tools\boot_loader\examples\pcie\linux_host_loader to the folder.jjjj}jjj}r(j]j]j]j]j]ujMj]rjXCreate a folder (e.g. pcie_test) in a Linux machine. Copy pciedemo.c, Makefile, pcieDdrInit_66xx.h, pcieBootCode_66xx.h, pcieInterrupt_66xx.h and post_66xx.h from toolsboot_loaderexamplespcielinux_host_loader to the folder.r¾rþ}rľ(jXCreate a folder (e.g. pcie_test) in a Linux machine. Copy pciedemo.c, Makefile, pcieDdrInit_66xx.h, pcieBootCode_66xx.h, pcieInterrupt_66xx.h and post_66xx.h from tools\boot_loader\examples\pcie\linux_host_loader to the folder.jjubaubaubj{)rž}rƾ(jX5Type “make”, a pciedemo.ko file should be createdrǾjjjj}jjj}rȾ(j]j]j]j]j]ujNjhj]rɾj)rʾ}r˾(jjǾjjžjj}jjj}r̾(j]j]j]j]j]ujMj]r;jX5Type “make”, a pciedemo.ko file should be createdrξrϾ}rо(jjǾjjʾubaubaubj{)rѾ}rҾ(jXBy default, this will build the “HelloWorld” demo on little endian 6678, which is controlled by the following Marcos in pciedemo.c: jjjj}jjj}rӾ(j]j]j]j]j]ujNjhj]rԾj)rվ}r־(jXBy default, this will build the “HelloWorld” demo on little endian 6678, which is controlled by the following Marcos in pciedemo.c:r׾jjѾjj}jjj}rؾ(j]j]j]j]j]ujMj]rپjXBy default, this will build the “HelloWorld” demo on little endian 6678, which is controlled by the following Marcos in pciedemo.c:rھr۾}rܾ(jj׾jjվubaubaubeubj)rݾ}r޾(jX#define BIG_ENDIAN 0 #define HELLO_WORLD_DEMO 1 #define POST_DEMO 0 #define EDMA_INTC_DEMO 0 #define EVMC6678L 1 #define EVMC6670L 0jjjj}jjj}r߾(j@jAj]j]j]j]j]ujM+jhj]rjX#define BIG_ENDIAN 0 #define HELLO_WORLD_DEMO 1 #define POST_DEMO 0 #define EDMA_INTC_DEMO 0 #define EVMC6678L 1 #define EVMC6670L 0rr}r(jUjjݾubaubj)r}r(jXOne must select the endianness, demo program and target type by toggling between 0 and 1 accordingly. Then, type “make clean” and type “make” to rebuild the pciedemo.ko.rjjjj}jjj}r(j]j]j]j]j]ujMjhj]rjXOne must select the endianness, demo program and target type by toggling between 0 and 1 accordingly. Then, type “make clean” and type “make” to rebuild the pciedemo.ko.rr}r(jjjjubaubj)r}r(jXuNote: “HelloWorld” and EDMA_INTC demos can be run on both endianness. POST demo can be run on little endian only.rjjjj}jjj}r(j]j]j]j]j]ujMjhj]rjXuNote: “HelloWorld” and EDMA_INTC demos can be run on both endianness. POST demo can be run on little endian only.rr}r(jjjjubaubjt)r}r(jUjjjj}jjwj}r(jyX-j]j]j]j]j]ujMjhj]rj{)r}r(jXTo insert the module into kernel, type “sudo insmod pciedemo.ko”; to view the kernel message, type “dmesg”; to remove the module from kernel, type “sudo rmmod jjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXTo insert the module into kernel, type “sudo insmod pciedemo.ko”; to view the kernel message, type “dmesg”; to remove the module from kernel, type “sudo rmmodrjjjj}jjj}r(j]j]j]j]j]ujMj]rjXTo insert the module into kernel, type “sudo insmod pciedemo.ko”; to view the kernel message, type “dmesg”; to remove the module from kernel, type “sudo rmmodrr}r(jjjjubaubaubaubj)r}r(jXpciedemo.ko”rjjjj}jjj}r(j]j]j]j]j]ujMjhj]rjXpciedemo.ko”r r }r (jjjjubaubeubj)r }r (jUjjjj}jjj}r(j]j]j]j]rU!the-role-of-ibl-in-pcie-boot-moderaj]rhPaujMjhj]r(j)r}r(jX!The role of IBL in PCIE boot moderjj jj}jjj}r(j]j]j]j]j]ujMjhj]rjX!The role of IBL in PCIE boot moderr}r(jjjjubaubj)r}r(jXThe Intermediate Boot Loader (IBL) is flashed into I2C EEPROM bus address 0x51. IBL provides a workaround for the PLL lockup issue (please refer to C6678 errata document, February 2011, advisory 8 for details on the PLL lockup issue). For ROM boot modes (EMAC, SRIO, PCIE, Hyperlink, etc) and I2C boot mode with bus address 0x50, DSP will initially boot from I2C EEPROM bus address 0x51 which does the PLL reset workaround, updates the DEVSTAT for appropriate values based on the DIP switch settings (SW3 through SW6 settings) and then re-enters the ROM to accomplish the desired boot mode. Please note that the re-entry is done for all boot modes except for PCIE boot mode and I2C boot mode with bus address 0x51.rjj jj}jjj}r(j]j]j]j]j]ujMjhj]rjXThe Intermediate Boot Loader (IBL) is flashed into I2C EEPROM bus address 0x51. IBL provides a workaround for the PLL lockup issue (please refer to C6678 errata document, February 2011, advisory 8 for details on the PLL lockup issue). For ROM boot modes (EMAC, SRIO, PCIE, Hyperlink, etc) and I2C boot mode with bus address 0x50, DSP will initially boot from I2C EEPROM bus address 0x51 which does the PLL reset workaround, updates the DEVSTAT for appropriate values based on the DIP switch settings (SW3 through SW6 settings) and then re-enters the ROM to accomplish the desired boot mode. Please note that the re-entry is done for all boot modes except for PCIE boot mode and I2C boot mode with bus address 0x51.r r!}r"(jjjjubaubj)r#}r$(jX6Below are the steps done in the IBL in PCIE boot mode:r%jj jj}jjj}r&(j]j]j]j]j]ujMjhj]r'jX6Below are the steps done in the IBL in PCIE boot mode:r(r)}r*(jj%jj#ubaubjt)r+}r,(jUjj jj}jjwj}r-(jyX-j]j]j]j]j]ujMjhj]r.(j{)r/}r0(jXFPGA samples the boot mode pinsr1jj+jj}jjj}r2(j]j]j]j]j]ujNjhj]r3j)r4}r5(jj1jj/jj}jjj}r6(j]j]j]j]j]ujMj]r7jXFPGA samples the boot mode pinsr8r9}r:(jj1jj4ubaubaubj{)r;}r<(jX4FPGA forces the DSP to boot via I2C bus address 0x51r=jj+jj}jjj}r>(j]j]j]j]j]ujNjhj]r?j)r@}rA(jj=jj;jj}jjj}rB(j]j]j]j]j]ujMj]rCjX4FPGA forces the DSP to boot via I2C bus address 0x51rDrE}rF(jj=jj@ubaubaubj{)rG}rH(jX3PLL is initialized correctly by the IBL on the I2C.rIjj+jj}jjj}rJ(j]j]j]j]j]ujNjhj]rKj)rL}rM(jjIjjGjj}jjj}rN(j]j]j]j]j]ujMj]rOjX3PLL is initialized correctly by the IBL on the I2C.rPrQ}rR(jjIjjLubaubaubj{)rS}rT(jX6IBL reads the sampled boot mode from an FPGA register.rUjj+jj}jjj}rV(j]j]j]j]j]ujNjhj]rWj)rX}rY(jjUjjSjj}jjj}rZ(j]j]j]j]j]ujMj]r[jX6IBL reads the sampled boot mode from an FPGA register.r\r]}r^(jjUjjXubaubaubj{)r_}r`(jXIBL checks the boot mode, if it is not I2C boot or it is I2C boot but with bus address 0x50, IBL writes boot mode into the DEVSTAT registerjj+jj}jjj}ra(j]j]j]j]j]ujNjhj]rbj)rc}rd(jXIBL checks the boot mode, if it is not I2C boot or it is I2C boot but with bus address 0x50, IBL writes boot mode into the DEVSTAT registerrejj_jj}jjj}rf(j]j]j]j]j]ujMj]rgjXIBL checks the boot mode, if it is not I2C boot or it is I2C boot but with bus address 0x50, IBL writes boot mode into the DEVSTAT registerrhri}rj(jjejjcubaubaubj{)rk}rl(jX IBL then checks if the boot mode is PCIE boot or not. If it is, it executes some PCIE workaround to configure the PCIE registers (mainly to accept spread spectrum clock) and stays inside IBL by first clearing the magic address and then monitoring it for PCIE boot. jj+jj}jjj}rm(j]j]j]j]j]ujNjhj]rnj)ro}rp(jXIBL then checks if the boot mode is PCIE boot or not. If it is, it executes some PCIE workaround to configure the PCIE registers (mainly to accept spread spectrum clock) and stays inside IBL by first clearing the magic address and then monitoring it for PCIE boot.rqjjkjj}jjj}rr(j]j]j]j]j]ujM j]rsjXIBL then checks if the boot mode is PCIE boot or not. If it is, it executes some PCIE workaround to configure the PCIE registers (mainly to accept spread spectrum clock) and stays inside IBL by first clearing the magic address and then monitoring it for PCIE boot.rtru}rv(jjqjjoubaubaubeubj)rw}rx(jXFor PCIE demos with DDR memory is used, proper DDR configuration is required, this doesn’t need the full IBL functionality. Typically DDR can be initialized in two ways:ryjj jj}jjj}rz(j]j]j]j]j]ujMjhj]r{jXFor PCIE demos with DDR memory is used, proper DDR configuration is required, this doesn’t need the full IBL functionality. Typically DDR can be initialized in two ways:r|r}}r~(jjyjjwubaubjt)r}r(jUjj jj}jjwj}r(jyX-j]j]j]j]j]ujMjhj]r(j{)r}r(jXHThe Linux host initializes the DDR registers directly through PCIE link.jjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXHThe Linux host initializes the DDR registers directly through PCIE link.rjjjj}jjj}r(j]j]j]j]j]ujMj]rjXHThe Linux host initializes the DDR registers directly through PCIE link.rr}r(jjjjubaubaubj{)r}r(jXA DDR initialization image is downloaded in the L2 first to initialize the DDR and then reset the magic address with value 0. And then the application image is downloaded in jjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXA DDR initialization image is downloaded in the L2 first to initialize the DDR and then reset the magic address with value 0. And then the application image is downloaded inrjjjj}jjj}r(j]j]j]j]j]ujMj]rjXA DDR initialization image is downloaded in the L2 first to initialize the DDR and then reset the magic address with value 0. And then the application image is downloaded inrr}r(jjjjubaubaubeubj)r}r(jX7the DDR. In Processor SDK, the second approach is used.rjj jj}jjj}r(j]j]j]j]j]ujMjhj]rjX7the DDR. In Processor SDK, the second approach is used.rr}r(jjjjubaubeubj)r}r(jUjjjj}jjj}r(j]j]j]j]rU!how-helloworld-boot-example-worksraj]rhaujMjhj]r(j)r}r(jX!How HelloWorld boot example worksrjjjj}jjj}r(j]j]j]j]j]ujMjhj]rjX!How HelloWorld boot example worksrr}r(jjjjubaubj)r}r(jXThe Linux host first pushes the DDR init boot image data to L2 memory of core 0, then writes the boot entry address of the DDR init boot image to the magic address on core 0, both via PCIE. When the EVM is in PCIE boot mode, the IBL code running on the DSP core 0 polls the entry address and jumps to that address and starts to boot (initialize the DDR). After DDR is properly initialized, the DDR init code clears the magic address and keeps on polling it.rjjjj}jjj}r(j]j]j]j]j]ujMjhj]rjXThe Linux host first pushes the DDR init boot image data to L2 memory of core 0, then writes the boot entry address of the DDR init boot image to the magic address on core 0, both via PCIE. When the EVM is in PCIE boot mode, the IBL code running on the DSP core 0 polls the entry address and jumps to that address and starts to boot (initialize the DDR). After DDR is properly initialized, the DDR init code clears the magic address and keeps on polling it.rr}r(jjjjubaubj)r}r(jXDLinux host then pushes the HelloWorld boot image data to DDR memory, then writes the boot entry address of the HelloWorld boot image to the magic address on core 0 to boot core 0. Core 0 starts to boot and print the “Hello World” booting information, and then boot all the other cores by writing the address of \_c_int00 to the magic address on other cores and sending an IPC interrupt to other cores. The RBL running on other cores will jump to \_c_int00 and start to boot, each core will write 0xBABEFACE to its magic address by running a function write_boot_magic_number().jjjj}jjj}r(j]j]j]j]j]ujM%jhj]rjXBLinux host then pushes the HelloWorld boot image data to DDR memory, then writes the boot entry address of the HelloWorld boot image to the magic address on core 0 to boot core 0. Core 0 starts to boot and print the “Hello World” booting information, and then boot all the other cores by writing the address of _c_int00 to the magic address on other cores and sending an IPC interrupt to other cores. The RBL running on other cores will jump to _c_int00 and start to boot, each core will write 0xBABEFACE to its magic address by running a function write_boot_magic_number().rr}r(jXDLinux host then pushes the HelloWorld boot image data to DDR memory, then writes the boot entry address of the HelloWorld boot image to the magic address on core 0 to boot core 0. Core 0 starts to boot and print the “Hello World” booting information, and then boot all the other cores by writing the address of \_c_int00 to the magic address on other cores and sending an IPC interrupt to other cores. The RBL running on other cores will jump to \_c_int00 and start to boot, each core will write 0xBABEFACE to its magic address by running a function write_boot_magic_number().jjubaubj)r}r¿(jXNote that host boot application needs to wait for some time after pushing the DDR init boot image and before pushing the HelloWorld boot image to the DDR, this will ensure DDR is properly initialized.rÿjjjj}jjj}rĿ(j]j]j]j]j]ujM/jhj]rſjXNote that host boot application needs to wait for some time after pushing the DDR init boot image and before pushing the HelloWorld boot image to the DDR, this will ensure DDR is properly initialized.rƿrǿ}rȿ(jjÿjjubaubeubj)rɿ}rʿ(jUjjjj}jjj}r˿(j]j]j]j]r̿Uhow-post-boot-example-worksrͿaj]rοhaujM4jhj]rϿ(j)rп}rѿ(jXHow POST boot example worksrҿjjɿjj}jjj}rӿ(j]j]j]j]j]ujM4jhj]rԿjXHow POST boot example worksrտrֿ}r׿(jjҿjjпubaubj)rؿ}rٿ(jX6The POST example uses L2 only. The Linux host first pushes the POST boot image data to L2 memory of core 0, then writes the boot entry address of the POST to the magic address on core 0, both via PCIE. The IBL code running on the DSP core 0 polls the entry address and jumps to that address and starts to boot.rڿjjɿjj}jjj}rۿ(j]j]j]j]j]ujM6jhj]rܿjX6The POST example uses L2 only. The Linux host first pushes the POST boot image data to L2 memory of core 0, then writes the boot entry address of the POST to the magic address on core 0, both via PCIE. The IBL code running on the DSP core 0 polls the entry address and jumps to that address and starts to boot.rݿr޿}r߿(jjڿjjؿubaubeubj)r}r(jUjjjj}jjj}r(j]j]j]j]rU!how-dsp-local-reset-example-worksraj]rj8aujM=jhj]r(j)r}r(jX!How DSP local reset example worksrjjjj}jjj}r(j]j]j]j]j]ujM=jhj]rjX!How DSP local reset example worksrr}r(jjjjubaubj)r}r(jXA user may want to re-run a PCIE demo without power cycle the Linux PC. There is a need to reset the DSP chip from host software. There are several types of resets: hard reset, soft reset and CPU local reset. Hard reset will reset everything on the device except the PLLs, test, emulation logic, and reset isolation modules. Since PCIE doesn’t support reset isolation, a hard reset will reset PCIE module as well and all the configured PCIE registers (PCIE MMRs) will be lost. Soft reset will behave like a hard reset except that the stick bits of PCIE MMRs are retained. The PC can’t communicate with PCIE card anymore in both hard reset and soft reset cases.rjjjj}jjj}r(j]j]j]j]j]ujM?jhj]rjXA user may want to re-run a PCIE demo without power cycle the Linux PC. There is a need to reset the DSP chip from host software. There are several types of resets: hard reset, soft reset and CPU local reset. Hard reset will reset everything on the device except the PLLs, test, emulation logic, and reset isolation modules. Since PCIE doesn’t support reset isolation, a hard reset will reset PCIE module as well and all the configured PCIE registers (PCIE MMRs) will be lost. Soft reset will behave like a hard reset except that the stick bits of PCIE MMRs are retained. The PC can’t communicate with PCIE card anymore in both hard reset and soft reset cases.rr}r(jjjjubaubj)r}r(jX^To reset the DSP while keeping the PCIE untouched, the local reset example does the following:rjjjj}jjj}r(j]j]j]j]j]ujMJjhj]rjX^To reset the DSP while keeping the PCIE untouched, the local reset example does the following:rr}r(jjjjubaubjt)r}r(jUjjjj}jjwj}r(jyX-j]j]j]j]j]ujMMjhj]r(j{)r}r(jXPut all cores in reset via PSCrjjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r (jjjjjj}jjj}r (j]j]j]j]j]ujMMj]r jXPut all cores in reset via PSCr r }r(jjjjubaubaubj{)r}r(jX1Disable all modules except PCIE and cores via PSCrjjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj}jjj}r(j]j]j]j]j]ujMNj]rjX1Disable all modules except PCIE and cores via PSCrr}r(jjjjubaubaubj{)r}r(jXSConfigure chip level registers DSP_BOOT_ADDRn and IPCGRn: Here the header array converted from DSP local reset example is loaded into each core via PCIE; the \_c_int00 is then written to each DSP_BOOT_ADDRn; finally IPCGRn is written to jump start the DSP local reset example program, which simply polls magic address for a secondary boot.jjjj}jjj}r(j]j]j]j]j]ujNjhj]rj)r}r (jXSConfigure chip level registers DSP_BOOT_ADDRn and IPCGRn: Here the header array converted from DSP local reset example is loaded into each core via PCIE; the \_c_int00 is then written to each DSP_BOOT_ADDRn; finally IPCGRn is written to jump start the DSP local reset example program, which simply polls magic address for a secondary boot.jjjj}jjj}r!(j]j]j]j]j]ujMOj]r"jXRConfigure chip level registers DSP_BOOT_ADDRn and IPCGRn: Here the header array converted from DSP local reset example is loaded into each core via PCIE; the _c_int00 is then written to each DSP_BOOT_ADDRn; finally IPCGRn is written to jump start the DSP local reset example program, which simply polls magic address for a secondary boot.r#r$}r%(jXSConfigure chip level registers DSP_BOOT_ADDRn and IPCGRn: Here the header array converted from DSP local reset example is loaded into each core via PCIE; the \_c_int00 is then written to each DSP_BOOT_ADDRn; finally IPCGRn is written to jump start the DSP local reset example program, which simply polls magic address for a secondary boot.jjubaubaubj{)r&}r'(jX,Enable all modules previous disabled via PSCr(jjjj}jjj}r)(j]j]j]j]j]ujNjhj]r*j)r+}r,(jj(jj&jj}jjj}r-(j]j]j]j]j]ujMUj]r.jX,Enable all modules previous disabled via PSCr/r0}r1(jj(jj+ubaubaubj{)r2}r3(jX$Pull all cores out of reset via PSC jjjj}jjj}r4(j]j]j]j]j]ujNjhj]r5j)r6}r7(jX#Pull all cores out of reset via PSCr8jj2jj}jjj}r9(j]j]j]j]j]ujMVj]r:jX#Pull all cores out of reset via PSCr;r<}r=(jj8jj6ubaubaubeubj)r>}r?(jXIt is IBL (in local L2) that monitors magic address and boots the DDR init (in local L2) or POST (in local L2) or EDMA-interrupt (in local L2) in those demos. If one wants to load his/her own boot demo code, then it shouldn’t overlap with the IBL code. As a guideline, the IBL uses memory from 0x00800000 to 0x0081BDFF. To check the exact memory usage, you can re-build the IBL by following the instructions in tools\boot_loader\ibl\doc\build_instructions.txt and check the resulting ibl_c66x_init.map file. In addition, following local L2 is reserved by RBL and shouldn’t be used: for 6678 ROM PG 1.0, 0x00872DC0 – 0x0087FFFF; for 6670 ROM PG 1.0, 0x008F2DC0 – 0x008FFFFF.jjjj}jjj}r@(j]j]j]j]j]ujNjhj]rAj)rB}rC(jXIt is IBL (in local L2) that monitors magic address and boots the DDR init (in local L2) or POST (in local L2) or EDMA-interrupt (in local L2) in those demos. If one wants to load his/her own boot demo code, then it shouldn’t overlap with the IBL code. As a guideline, the IBL uses memory from 0x00800000 to 0x0081BDFF. To check the exact memory usage, you can re-build the IBL by following the instructions in tools\boot_loader\ibl\doc\build_instructions.txt and check the resulting ibl_c66x_init.map file. In addition, following local L2 is reserved by RBL and shouldn’t be used: for 6678 ROM PG 1.0, 0x00872DC0 – 0x0087FFFF; for 6670 ROM PG 1.0, 0x008F2DC0 – 0x008FFFFF.jj>jj}jjj}rD(j]j]j]j]j]ujMYj]rEjXIt is IBL (in local L2) that monitors magic address and boots the DDR init (in local L2) or POST (in local L2) or EDMA-interrupt (in local L2) in those demos. If one wants to load his/her own boot demo code, then it shouldn’t overlap with the IBL code. As a guideline, the IBL uses memory from 0x00800000 to 0x0081BDFF. To check the exact memory usage, you can re-build the IBL by following the instructions in toolsboot_loaderibldocbuild_instructions.txt and check the resulting ibl_c66x_init.map file. In addition, following local L2 is reserved by RBL and shouldn’t be used: for 6678 ROM PG 1.0, 0x00872DC0 – 0x0087FFFF; for 6670 ROM PG 1.0, 0x008F2DC0 – 0x008FFFFF.rFrG}rH(jXIt is IBL (in local L2) that monitors magic address and boots the DDR init (in local L2) or POST (in local L2) or EDMA-interrupt (in local L2) in those demos. If one wants to load his/her own boot demo code, then it shouldn’t overlap with the IBL code. As a guideline, the IBL uses memory from 0x00800000 to 0x0081BDFF. To check the exact memory usage, you can re-build the IBL by following the instructions in tools\boot_loader\ibl\doc\build_instructions.txt and check the resulting ibl_c66x_init.map file. In addition, following local L2 is reserved by RBL and shouldn’t be used: for 6678 ROM PG 1.0, 0x00872DC0 – 0x0087FFFF; for 6670 ROM PG 1.0, 0x008F2DC0 – 0x008FFFFF.jjBubaubaubeubeubeubeubj)rI}rJ(jUjj;jjjjj}rK(j]j]j]j]rLUk2grMaj]rNjVaujK\jhj]rO(j)rP}rQ(jXK2GrRjjIjjjjj}rS(j]j]j]j]j]ujK\jhj]rTjXK2GrUrV}rW(jjRjjPubaubj7)rX}rY(jXChttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_BOOT_K2GjjIjj:XRsource/rtos/PDK_Platform_Software/Boot_Board_and_EVM_Abstractions/BOOT_K2G.rst.incrZr[}r\bjj>j}r](j@jAj]j]j]j]j]ujKjhj]r^jXChttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_BOOT_K2Gr_r`}ra(jUjjXubaubj)rb}rc(jUjKjjIjj[jjj}rd(j]reXoverviewrfaj]j]j]rgUid105rhaj]ujKjhj]ri(j)rj}rk(jXOverviewrljjbjj[jjj}rm(j]j]j]j]j]ujKjhj]rnjXOverviewrorp}rq(jjljjjubaubj)rr}rs(jXuThe Secondary Bootloader (SBL) for K2G does basic hardware initialization for the board to load and run applications.rtjjbjj[jjj}ru(j]j]j]j]j]ujKjhj]rvjXuThe Secondary Bootloader (SBL) for K2G does basic hardware initialization for the board to load and run applications.rwrx}ry(jjtjjrubaubeubj)rz}r{(jUjKjjIjj[jjj}r|(j]r}Xbootloader execution sequencer~aj]j]j]rUid106raj]ujK jhj]r(j)r}r(jXBootloader Execution Sequencerjjzjj[jjj}r(j]j]j]j]j]ujK jhj]rjXBootloader Execution Sequencerr}r(jjjjubaubjt)r}r(jUjjzjj[jjwj}r(jyX-j]j]j]j]j]ujK jhj]r(j{)r}r(jXPower On Reset occursrjjjj[jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj[jjj}r(j]j]j]j]j]ujK j]rjXPower On Reset occursrr}r(jjjjubaubaubj{)r}r(jXjROM Bootloader (RBL) executes. It checks for bootmode and attempts to load+run the SBL from that bootmode.jjjj[jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXjROM Bootloader (RBL) executes. It checks for bootmode and attempts to load+run the SBL from that bootmode.rjjjj[jjj}r(j]j]j]j]j]ujK j]rjXjROM Bootloader (RBL) executes. It checks for bootmode and attempts to load+run the SBL from that bootmode.rr}r(jjjjubaubaubj{)r}r(jXQSBL begins execution from internal memory (MSMC RAM) - Board Initialization is done by a call to **Board_init()** API. For additional details refer to `Processor SDK Board Support `__. - SBL setup includes configuring Pinmux, enable peripheral clocks, set up PLLs, and configure EMIF for DDR. jjjNjjj}r(j]j]j]j]j]ujNjhj]r(j)r}r(jX4SBL begins execution from internal memory (MSMC RAM)rjjjj[jjj}r(j]j]j]j]j]ujKj]rjX4SBL begins execution from internal memory (MSMC RAM)rr}r(jjjjubaubjt)r}r(jUj}r(jyX-j]j]j]j]j]ujjj]r(j{)r}r(jXBoard Initialization is done by a call to **Board_init()** API. For additional details refer to `Processor SDK Board Support `__.j}r(j]j]j]j]j]ujjj]rj)r}r(jXBoard Initialization is done by a call to **Board_init()** API. For additional details refer to `Processor SDK Board Support `__.jjjj[jjj}r(j]j]j]j]j]ujKj]r(jX*Board Initialization is done by a call to rr}r(jX*Board Initialization is done by a call to jjubj)r}r(jX**Board_init()**j}r(j]j]j]j]j]ujjj]rjX Board_init()rr}r(jUjjubajjubjX& API. For additional details refer to rr}r(jX& API. For additional details refer to jjubj)r}r(jX@`Processor SDK Board Support `__j}r(UnameXProcessor SDK Board SupportjXindex_board.html#board-supportj]j]j]j]j]ujjj]rjXProcessor SDK Board Supportrr}r(jUjjubajjubjX.r}r(jX.jjubeubajjubj{)r}r(jXjSBL setup includes configuring Pinmux, enable peripheral clocks, set up PLLs, and configure EMIF for DDR. j}r(j]j]j]j]j]ujjj]rj)r}r(jXiSBL setup includes configuring Pinmux, enable peripheral clocks, set up PLLs, and configure EMIF for DDR.rjjjj[jjj}r(j]j]j]j]j]ujKj]rjXiSBL setup includes configuring Pinmux, enable peripheral clocks, set up PLLs, and configure EMIF for DDR.rr}r(jjjjubaubajjubejjwubeubj{)r}r(jXSBL finishes setup and looks for "app" to execute next. This user-modifiable application may reside in SD card or QSPI memory depending on the bootmode chosen.jjjj[jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXSBL finishes setup and looks for "app" to execute next. This user-modifiable application may reside in SD card or QSPI memory depending on the bootmode chosen.rjjjj[jjj}r(j]j]j]j]j]ujKj]rjXSBL finishes setup and looks for "app" to execute next. This user-modifiable application may reside in SD card or QSPI memory depending on the bootmode chosen.rr}r(jjjjubaubaubj{)r}r(jXoOnce located, app will be loaded into memory and execution will be branched to the application's entry address jjjj[jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXnOnce located, app will be loaded into memory and execution will be branched to the application's entry addressrjjjj[jjj}r(j]j]j]j]j]ujKj]rjXnOnce located, app will be loaded into memory and execution will be branched to the application's entry addressrr}r(jjjjubaubaubeubeubj)r}r(jUjKjjIjj[jjj}r(j]rXtools and binary formatsraj]j]j]rUid107raj]ujKjhj]rj)r}r(jXTools and Binary Formatsrjjjj[jjj}r(j]j]j]j]j]ujKjhj]rjXTools and Binary Formatsrr}r(jjjjubaubaubj)r}r (jUjKjjIjj[jjj}r (j]r Xmaking bootable sbl image (mlo)r aj]j]j]r Umaking-bootable-sbl-image-mloraj]ujK!jhj]r(j)r}r(jXMaking Bootable SBL image (MLO)rjjjj[jjj}r(j]j]j]j]j]ujK!jhj]rjXMaking Bootable SBL image (MLO)rr}r(jjjjubaubj)r}r(jXRBL loads and runs "MLO", which is a .out executable formatted by TI tools. To make a .out, such as SBL, bootable by ROM, you must follow these steps:rjjjj[jjj}r(j]j]j]j]j]ujK#jhj]rjXRBL loads and runs "MLO", which is a .out executable formatted by TI tools. To make a .out, such as SBL, bootable by ROM, you must follow these steps:rr}r(jjjjubaubj )r }r!(jUjjjj[jj j}r"(jU.j]j]j]jUj]j]jjujK'jhj]r#(j{)r$}r%(jXz**armhex [.out file] [.rmd file]** - .out file is the file you want to boot, such as sbl.out - .rmd file is an input file to specify sections information. An example can be found in: /packages/ti/boot/sbl/board/evmK2G/build/sbl.rmd - armhex is a tool in TI ARM CGT compiler. This generates a [hex file], name of which is specified by the .rmd file jj jNjjj}r&(j]j]j]j]j]ujNjhj]r'(j)r(}r)(jX"**armhex [.out file] [.rmd file]**r*jj$jj[jjj}r+(j]j]j]j]j]ujK'j]r,j)r-}r.(jj*j}r/(j]j]j]j]j]ujj(j]r0jXarmhex [.out file] [.rmd file]r1r2}r3(jUjj-ubajjubaubjt)r4}r5(jUj}r6(jyX-j]j]j]j]j]ujj$j]r7(j{)r8}r9(jX7.out file is the file you want to boot, such as sbl.outr:j}r;(j]j]j]j]j]ujj4j]r<j)r=}r>(jj:jj8jj[jjj}r?(j]j]j]j]j]ujK)j]r@jX7.out file is the file you want to boot, such as sbl.outrArB}rC(jj:jj=ubaubajjubj{)rD}rE(jX.rmd file is an input file to specify sections information. An example can be found in: /packages/ti/boot/sbl/board/evmK2G/build/sbl.rmdj}rF(j]j]j]j]j]ujj4j]rGj)rH}rI(jX.rmd file is an input file to specify sections information. An example can be found in: /packages/ti/boot/sbl/board/evmK2G/build/sbl.rmdrJjjDjj[jjj}rK(j]j]j]j]j]ujK*j]rLjX.rmd file is an input file to specify sections information. An example can be found in: /packages/ti/boot/sbl/board/evmK2G/build/sbl.rmdrMrN}rO(jjJjjHubaubajjubj{)rP}rQ(jXrarmhex is a tool in TI ARM CGT compiler. This generates a [hex file], name of which is specified by the .rmd file j}rR(j]j]j]j]j]ujj4j]rSj)rT}rU(jXqarmhex is a tool in TI ARM CGT compiler. This generates a [hex file], name of which is specified by the .rmd filerVjjPjj[jjj}rW(j]j]j]j]j]ujK-j]rXjXqarmhex is a tool in TI ARM CGT compiler. This generates a [hex file], name of which is specified by the .rmd filerYrZ}r[(jjVjjTubaubajjubejjwubeubj{)r\}r](jX{**b2ccs [hex file] [ccs file]** - hex file is the output from the previous step - ccs file can be name of your choosing jj jNjjj}r^(j]j]j]j]j]ujNjhj]r_(j)r`}ra(jX**b2ccs [hex file] [ccs file]**rbjj\jj[jjj}rc(j]j]j]j]j]ujK0j]rdj)re}rf(jjbj}rg(j]j]j]j]j]ujj`j]rhjXb2ccs [hex file] [ccs file]rirj}rk(jUjjeubajjubaubjt)rl}rm(jUj}rn(jyX-j]j]j]j]j]ujj\j]ro(j{)rp}rq(jX-hex file is the output from the previous steprrj}rs(j]j]j]j]j]ujjlj]rtj)ru}rv(jjrjjpjj[jjj}rw(j]j]j]j]j]ujK2j]rxjX-hex file is the output from the previous stepryrz}r{(jjrjjuubaubajjubj{)r|}r}(jX&ccs file can be name of your choosing j}r~(j]j]j]j]j]ujjlj]rj)r}r(jX%ccs file can be name of your choosingrjj|jj[jjj}r(j]j]j]j]j]ujK3j]rjX%ccs file can be name of your choosingrr}r(jjjjubaubajjubejjwubeubj{)r}r(jXz**ccsAddGphdr -infile [ccs file] -outfile [gphdr file] -headerEndian BE** - gphdr file can be the name of your choosing jj jNjjj}r(j]j]j]j]j]ujNjhj]r(j)r}r(jXI**ccsAddGphdr -infile [ccs file] -outfile [gphdr file] -headerEndian BE**rjjjj[jjj}r(j]j]j]j]j]ujK5j]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXEccsAddGphdr -infile [ccs file] -outfile [gphdr file] -headerEndian BErr}r(jUjjubajjubaubjt)r}r(jUj}r(jyX-j]j]j]j]j]ujjj]rj{)r}r(jX,gphdr file can be the name of your choosing j}r(j]j]j]j]j]ujjj]rj)r}r(jX+gphdr file can be the name of your choosingrjjjj[jjj}r(j]j]j]j]j]ujK8j]rjX+gphdr file can be the name of your choosingrr}r(jjjjubaubajjubajjwubeubj{)r}r(jXk**ccsAddGptlr -infile [gphdr file] -outfile [gptlr file]** - gptlr file can be the name of your choosing jj jNjjj}r(j]j]j]j]j]ujNjhj]r(j)r}r(jX:**ccsAddGptlr -infile [gphdr file] -outfile [gptlr file]**rjjjj[jjj}r(j]j]j]j]j]ujK:j]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX6ccsAddGptlr -infile [gphdr file] -outfile [gptlr file]rr}r(jUjjubajjubaubjt)r}r(jUj}r(jyX-j]j]j]j]j]ujjj]rj{)r}r(jX,gptlr file can be the name of your choosing j}r(j]j]j]j]j]ujjj]rj)r}r(jX+gptlr file can be the name of your choosingrjjjj[jjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX'byteswapccs [gptlr file] [MLO ccs file]rr}r(jUjjubajjubaubjt)r}r(jUj}r(jyX-j]j]j]j]j]ujjj]rj{)r}r(jX.MLO ccs file can be the name of your choosing j}r(j]j]j]j]j]ujjj]rj)r}r(jX-MLO ccs file can be the name of your choosingrjjjj[jjj}r(j]j]j]j]j]ujK@j]rjX-MLO ccs file can be the name of your choosingrr}r(jjjjubaubajjubajjwubeubj{)r}r(jXM**ccs2bin -swap [MLO ccs file] MLO** - MLO will be created after this step jj jNjjj}r(j]j]j]j]j]ujNjhj]r(j)r}r(jX$**ccs2bin -swap [MLO ccs file] MLO**rjjjj[jjj}r(j]j]j]j]j]ujKBj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX ccs2bin -swap [MLO ccs file] MLOrr}r(jUjjubajjubaubjt)r}r(jUj}r(jyX-j]j]j]j]j]ujjj]rj{)r}r(jX$MLO will be created after this step j}r(j]j]j]j]j]ujjj]rj)r}r(jX#MLO will be created after this steprjjjj[jjj}r(j]j]j]j]j]ujKDj]rjX#MLO will be created after this steprr}r(jjjjubaubajjubajjwubeubeubj)r}r (jXArmhex is part of TI ARM CGT, in **/tools/compiler/ti-cgt-arm_x.x.x/bin**. The rest of the tools can be found in: **/packages/ti/boot/sbl/tools**jjjj[jjj}r (j]j]j]j]j]ujKFjhj]r (jX!Armhex is part of TI ARM CGT, in r r }r(jX!Armhex is part of TI ARM CGT, in jjubj)r}r(jX9**/tools/compiler/ti-cgt-arm_x.x.x/bin**j}r(j]j]j]j]j]ujjj]rjX5/tools/compiler/ti-cgt-arm_x.x.x/binrr}r(jUjjubajjubjX). The rest of the tools can be found in: rr}r(jX). The rest of the tools can be found in: jjubj)r}r(jX0**/packages/ti/boot/sbl/tools**j}r(j]j]j]j]j]ujjj]rjX,/packages/ti/boot/sbl/toolsrr}r(jUjjubajjubeubeubj)r }r!(jUjKjjIjj[jjj}r"(j]r#X,making loadable user application image (app)r$aj]j]j]r%U*making-loadable-user-application-image-appr&aj]ujKLjhj]r'(j)r(}r)(jX,Making Loadable User Application image (app)r*jj jj[jjj}r+(j]j]j]j]j]ujKLjhj]r,jX,Making Loadable User Application image (app)r-r.}r/(jj*jj(ubaubj)r0}r1(jXFor converting the compiled .out files to a format loadable by TI's Secondary Boot Loader (SBL), **you must follow these two steps:**jj jj[jjj}r2(j]j]j]j]j]ujKNjhj]r3(jXaFor converting the compiled .out files to a format loadable by TI's Secondary Boot Loader (SBL), r4r5}r6(jXaFor converting the compiled .out files to a format loadable by TI's Secondary Boot Loader (SBL), jj0ubj)r7}r8(jX$**you must follow these two steps:**j}r9(j]j]j]j]j]ujj0j]r:jX you must follow these two steps:r;r<}r=(jUjj7ubajjubeubj )r>}r?(jUjj jj[jj j}r@(jU.j]j]j]jUj]j]jjujKQjhj]rA(j{)rB}rC(jX***out2rprc.exe [.out file] [rprc output]**rDjj>jj[jjj}rE(j]j]j]j]j]ujNjhj]rFj)rG}rH(jjDjjBjj[jjj}rI(j]j]j]j]j]ujKQj]rJj)rK}rL(jjDj}rM(j]j]j]j]j]ujjGj]rNjX&out2rprc.exe [.out file] [rprc output]rOrP}rQ(jUjjKubajjubaubaubj{)rR}rS(jX>**MulticoreImageGen.exe LE 55 [output name] 0 [rprc output]** jj>jj[jjj}rT(j]j]j]j]j]ujNjhj]rUj)rV}rW(jX=**MulticoreImageGen.exe LE 55 [output name] 0 [rprc output]**rXjjRjj[jjj}rY(j]j]j]j]j]ujKRj]rZj)r[}r\(jjXj}r](j]j]j]j]j]ujjVj]r^jX9MulticoreImageGen.exe LE 55 [output name] 0 [rprc output]r_r`}ra(jUjj[ubajjubaubaubeubj)rb}rc(jXOut2rprc.exe and MulticoreImageGen.exe are tools supplied by TI and can be located in the **/packages/ti/boot/sbl/tools** folder. "rprc output" can be any spare name of your choosing. "output name" can also be any name of your choosing.jj jj[jjj}rd(j]j]j]j]j]ujKTjhj]re(jXZOut2rprc.exe and MulticoreImageGen.exe are tools supplied by TI and can be located in the rfrg}rh(jXZOut2rprc.exe and MulticoreImageGen.exe are tools supplied by TI and can be located in the jjbubj)ri}rj(jX0**/packages/ti/boot/sbl/tools**j}rk(j]j]j]j]j]ujjbj]rljX,/packages/ti/boot/sbl/toolsrmrn}ro(jUjjiubajjubjXs folder. "rprc output" can be any spare name of your choosing. "output name" can also be any name of your choosing.rprq}rr(jXs folder. "rprc output" can be any spare name of your choosing. "output name" can also be any name of your choosing.jjbubeubj)rs}rt(jXThe '0' used in step 2 refers to the Core ID to boot. By default, '0' is MPU (Cortex A15) core 0. You can input a different value to boot to other cores. Valid values are:rujj jj[jjj}rv(j]j]j]j]j]ujKYjhj]rwjXThe '0' used in step 2 refers to the Core ID to boot. By default, '0' is MPU (Cortex A15) core 0. You can input a different value to boot to other cores. Valid values are:rxry}rz(jjujjsubaubjy )r{}r|(jUjj jj[jj j}r}(j]j]j]j]j]ujNjhj]r~j~ )r}r(jUj}r(j]j]j]j]j]UcolsKujj{j]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthK ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXCorerjjjj[jjj}r(j]j]j]j]j]ujK^j]rjXCorerr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXValuerjjjj[jjj}r(j]j]j]j]j]ujK^j]rjXValuerr}r(jjjjubaubajj ubejj ubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX MPU Core 0rjjjj[jjj}r(j]j]j]j]j]ujK`j]rjX MPU Core 0rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX0jjjj[jjj}r(j]j]j]j]j]ujK`j]rjX0r}r(jX0jjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX DSP Core 0rjjjj[jjj}r(j]j]j]j]j]ujKbj]rjX DSP Core 0rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX5jjjj[jjj}r(j]j]j]j]j]ujKbj]rjX5r}r(jX5jjubaubajj ubejj ubejj ubejj ubaubj)r}r(jXIf MPU SMP is chosen, the same boot image and entry will be used for all MPU cores. SBL can also parse multiple boot images that are concatenated together. Simply use MulticoreImageGen as such:rjj jj[jjj}r(j]j]j]j]j]ujKejhj]rjXIf MPU SMP is chosen, the same boot image and entry will be used for all MPU cores. SBL can also parse multiple boot images that are concatenated together. Simply use MulticoreImageGen as such:rr}r(jjjjubaubj)r}r(jX**MulticoreImageGen.exe LE 55 [output name] [Core ID a] [rprc output a] [Core ID b] [rprc output b] [Core ID c] [rprc output c] ...**rjj jj[jjj}r(j]j]j]j]j]ujKijhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXMulticoreImageGen.exe LE 55 [output name] [Core ID a] [rprc output a] [Core ID b] [rprc output b] [Core ID c] [rprc output c] ...rr}r(jUjjubajjubaubeubj)r}r(jUjKjjIjj[jjj}r(j]rX boot modesraj]j]j]rUid108raj]ujKmjhj]r(j)r}r(jX Boot Modesrjjjj[jjj}r(j]j]j]j]j]ujKmjhj]rjX Boot Modesrr}r(jjjjubaubj)r}r(jX7This release of SBL supports MMCSD and QSPI boot modes.rjjjj[jjj}r(j]j]j]j]j]ujKojhj]r jX7This release of SBL supports MMCSD and QSPI boot modes.r r }r (jjjjubaubj)r }r(jUjKjjjj[jjj}r(j]rXmmcsd boot moderaj]j]j]rUmmcsd-boot-moderaj]ujKrjhj]r(j)r}r(jXMMCSD Boot Moderjj jj[jjj}r(j]j]j]j]j]ujKrjhj]rjXMMCSD Boot Moderr}r(jjjjubaubj)r}r(jUjKjj jj[jjj}r(j]r j͜aj]j]j]r!Uid109r"aj]ujKujhj]r#(j)r$}r%(jXPreparing the SD cardr&jjjj[jjj}r'(j]j]j]j]j]ujKujhj]r(jXPreparing the SD cardr)r*}r+(jj&jj$ubaubj )r,}r-(jUjjjj[jj j}r.(jU.j]j]j]jUj]j]jjujKwjhj]r/(j{)r0}r1(jXTo boot the target, the SD card needs to be bootable. Follow the steps at `Creating bootable SD card in windows `__ or `Creating bootable SD card in Linux `__.jj,jj[jjj}r2(j]j]j]j]j]ujNjhj]r3j)r4}r5(jXTo boot the target, the SD card needs to be bootable. Follow the steps at `Creating bootable SD card in windows `__ or `Creating bootable SD card in Linux `__.jj0jj[jjj}r6(j]j]j]j]j]ujKwj]r7(jXJTo boot the target, the SD card needs to be bootable. Follow the steps at r8r9}r:(jXJTo boot the target, the SD card needs to be bootable. Follow the steps at jj4ubj)r;}r<(jX]`Creating bootable SD card in windows `__j}r=(UnameX$Creating bootable SD card in windowsjX2index_overview.html#windows-sd-card-creation-guidej]j]j]j]j]ujj4j]r>jX$Creating bootable SD card in windowsr?r@}rA(jUjj;ubajjubjX or rBrC}rD(jX or jj4ubj)rE}rF(jXY`Creating bootable SD card in Linux `__j}rG(UnameX"Creating bootable SD card in LinuxjX0index_overview.html#linux-sd-card-creation-guidej]j]j]j]j]ujj4j]rHjX"Creating bootable SD card in LinuxrIrJ}rK(jUjjEubajjubjX.rL}rM(jX.jj4ubeubaubj{)rN}rO(jXCopy "MLO" and "app" to your SD card. - MLO is the SBL formatted by the aforementioned tools. A pre-built MLO can be found at: **/packages/ti/boot/sbl/binary/evmK2G/mmcsd/bin** - app is the target application to be booted and also formatted by the aforementioned tools. (Note that the tools for making the bootable MLO and the loadable app are different). jj,jNjjj}rP(j]j]j]j]j]ujNjhj]rQ(j)rR}rS(jX%Copy "MLO" and "app" to your SD card.rTjjNjj[jjj}rU(j]j]j]j]j]ujKzj]rVjX%Copy "MLO" and "app" to your SD card.rWrX}rY(jjTjjRubaubjt)rZ}r[(jUj}r\(jyX-j]j]j]j]j]ujjNj]r](j{)r^}r_(jXMLO is the SBL formatted by the aforementioned tools. A pre-built MLO can be found at: **/packages/ti/boot/sbl/binary/evmK2G/mmcsd/bin**j}r`(j]j]j]j]j]ujjZj]raj)rb}rc(jXMLO is the SBL formatted by the aforementioned tools. A pre-built MLO can be found at: **/packages/ti/boot/sbl/binary/evmK2G/mmcsd/bin**jj^jj[jjj}rd(j]j]j]j]j]ujK|j]re(jXWMLO is the SBL formatted by the aforementioned tools. A pre-built MLO can be found at: rfrg}rh(jXWMLO is the SBL formatted by the aforementioned tools. A pre-built MLO can be found at: jjbubj)ri}rj(jXB**/packages/ti/boot/sbl/binary/evmK2G/mmcsd/bin**j}rk(j]j]j]j]j]ujjbj]rljX>/packages/ti/boot/sbl/binary/evmK2G/mmcsd/binrmrn}ro(jUjjiubajjubeubajjubj{)rp}rq(jXapp is the target application to be booted and also formatted by the aforementioned tools. (Note that the tools for making the bootable MLO and the loadable app are different). j}rr(j]j]j]j]j]ujjZj]rsj)rt}ru(jXapp is the target application to be booted and also formatted by the aforementioned tools. (Note that the tools for making the bootable MLO and the loadable app are different).rvjjpjj[jjj}rw(j]j]j]j]j]ujKj]rxjXapp is the target application to be booted and also formatted by the aforementioned tools. (Note that the tools for making the bootable MLO and the loadable app are different).ryrz}r{(jjvjjtubaubajjubejjwubeubeubeubj)r|}r}(jUjKjj jj[jjj}r~(j]rXbooting via sd cardraj]j]j]rUid110raj]ujKjhj]r(j)r}r(jXBooting via SD Cardrjj|jj[jjj}r(j]j]j]j]j]ujKjhj]rjXBooting via SD Cardrr}r(jjjjubaubj )r}r(jUjj|jj[jj j}r(jU.j]j]j]jUj]j]jjujKjhj]r(j{)r}r(jX7Insert micro SD card into the SD card slot of the boardrjjjj[jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj[jjj}r(j]j]j]j]j]ujKj]rjX7Insert micro SD card into the SD card slot of the boardrr}r(jjjjubaubaubj{)r}r(jXSet the board to MMC/SD bootmode by configuring the DIP switches to '0111'. Verify the bootmode on the LCD display on your boardjjjj[jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXSet the board to MMC/SD bootmode by configuring the DIP switches to '0111'. Verify the bootmode on the LCD display on your boardrjjjj[jjj}r(j]j]j]j]j]ujKj]rjXSet the board to MMC/SD bootmode by configuring the DIP switches to '0111'. Verify the bootmode on the LCD display on your boardrr}r(jjjjubaubaubj{)r}r(jXvOpen a serial communication terminal (such as TeraTerm, MiniCom, etc.) on host PC and connect to the UART console portjjjj[jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXvOpen a serial communication terminal (such as TeraTerm, MiniCom, etc.) on host PC and connect to the UART console portrjjjj[jjj}r(j]j]j]j]j]ujKj]rjXvOpen a serial communication terminal (such as TeraTerm, MiniCom, etc.) on host PC and connect to the UART console portrr}r(jjjjubaubaubj{)r}r(jXPower on the board jjjj[jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXPower on the boardrjjjj[jjj}r(j]j]j]j]j]ujKj]rjXPower on the boardrr}r(jjjjubaubaubeubjc)r}r(jUjj|jj[jjfj}r(j]j]j]j]j]ujKjhj]rji)r}r(jXOBelow is an example of K2G SBL successfully booting the diagnostic application:rjlKjjjj[jjj}r(j]j]j]j]j]ujKjhj]rjXOBelow is an example of K2G SBL successfully booting the diagnostic application:rr}r(jjjjubaubaubjR)r}r(jX'.. Image:: ../images/K2g_boot_diag.jpg jj|jj[jjZj}r(UuriX rtos/../images/K2g_boot_diag.jpgrj]j]j]j]jX}rU*jsj]ujKjhj]ubeubeubj)r}r(jUjjjj[jjj}r(j]j]j]j]rUqspi-boot-moderaj]rhaujKjhj]r(j)r}r(jXQSPI Boot Moderjjjj[jjj}r(j]j]j]j]j]ujKjhj]rjXQSPI Boot Moderr}r(jjjjubaubj)r}r(jUjjjj[jjj}r(j]j]j]j]rUpreparing-qspi-flashraj]rhMaujKjhj]r(j)r}r(jXPreparing QSPI Flashrjjjj[jjj}r(j]j]j]j]j]ujKjhj]rjXPreparing QSPI Flashrr}r(jjjjubaubj)r}r(jXMLO and app needs to be flashed into QSPI memory so that they can be booted. MLO will reside at offset 0 and app will reside at offset 0x80000. QSPI flash memory map:rjjjj[jjj}r(j]j]j]j]j]ujKjhj]rjXMLO and app needs to be flashed into QSPI memory so that they can be booted. MLO will reside at offset 0 and app will reside at offset 0x80000. QSPI flash memory map:rr}r(jjjjubaubjy )r}r(jUjjjj[jj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujjj]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r }r (jUj}r (j]j]j]j]j]ujjj]r (j )r }r(jUj}r(j]j]j]j]j]ujj j]rj)r}r(jX Offset 0x0rjj jj[jjj}r(j]j]j]j]j]ujKj]rjX Offset 0x0rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj j]rj)r}r(jXMLOrjjjj[jjj}r (j]j]j]j]j]ujKj]r!jXMLOr"r#}r$(jjjjubaubajj ubejj ubj )r%}r&(jUj}r'(j]j]j]j]j]ujjj]r((j )r)}r*(jUj}r+(j]j]j]j]j]ujj%j]r,j)r-}r.(jXOffset 0x80000r/jj)jj[jjj}r0(j]j]j]j]j]ujKj]r1jXOffset 0x80000r2r3}r4(jj/jj-ubaubajj ubj )r5}r6(jUj}r7(j]j]j]j]j]ujj%j]r8j)r9}r:(jXappr;jj5jj[jjj}r<(j]j]j]j]j]ujKj]r=jXappr>r?}r@(jj;jj9ubaubajj ubejj ubejj ubejj ubaubj)rA}rB(jXIThe images can be flashed into QSPI flash by following steps given below:rCjjjj[jjj}rD(j]j]j]j]j]ujKjhj]rEjXIThe images can be flashed into QSPI flash by following steps given below:rFrG}rH(jjCjjAubaubj )rI}rJ(jUjjjj[jj j}rK(jU.j]j]j]jUj]j]jjujKjhj]rL(j{)rM}rN(jXbCopy MLO, app, and config to SD card - MLO is the SBL formatted by the aforementioned tools. A pre-built MLO can be found at: **/packages/ti/boot/sbl/binary/evmK2G/qspi/bin** - app is the target application to be booted and also formatted by the aforementioned tools. (Note that the tools for making the bootable MLO and the loadable app are different). - config helps specify the memory map. The default config file can be found at: **/packages/ti/boot/sbl/tools/flashWriter/qspi**. This config file may be altered to custom user settings if needed. jjIjNjjj}rO(j]j]j]j]j]ujNjhj]rP(j)rQ}rR(jX$Copy MLO, app, and config to SD cardrSjjMjj[jjj}rT(j]j]j]j]j]ujKj]rUjX$Copy MLO, app, and config to SD cardrVrW}rX(jjSjjQubaubjt)rY}rZ(jUj}r[(jyX-j]j]j]j]j]ujjMj]r\(j{)r]}r^(jXMLO is the SBL formatted by the aforementioned tools. A pre-built MLO can be found at: **/packages/ti/boot/sbl/binary/evmK2G/qspi/bin**j}r_(j]j]j]j]j]ujjYj]r`j)ra}rb(jXMLO is the SBL formatted by the aforementioned tools. A pre-built MLO can be found at: **/packages/ti/boot/sbl/binary/evmK2G/qspi/bin**jj]jj[jjj}rc(j]j]j]j]j]ujKj]rd(jXWMLO is the SBL formatted by the aforementioned tools. A pre-built MLO can be found at: rerf}rg(jXWMLO is the SBL formatted by the aforementioned tools. A pre-built MLO can be found at: jjaubj)rh}ri(jXA**/packages/ti/boot/sbl/binary/evmK2G/qspi/bin**j}rj(j]j]j]j]j]ujjaj]rkjX=/packages/ti/boot/sbl/binary/evmK2G/qspi/binrlrm}rn(jUjjhubajjubeubajjubj{)ro}rp(jXapp is the target application to be booted and also formatted by the aforementioned tools. (Note that the tools for making the bootable MLO and the loadable app are different).j}rq(j]j]j]j]j]ujjYj]rrj)rs}rt(jXapp is the target application to be booted and also formatted by the aforementioned tools. (Note that the tools for making the bootable MLO and the loadable app are different).rujjojj[jjj}rv(j]j]j]j]j]ujKj]rwjXapp is the target application to be booted and also formatted by the aforementioned tools. (Note that the tools for making the bootable MLO and the loadable app are different).rxry}rz(jjujjsubaubajjubj{)r{}r|(jXconfig helps specify the memory map. The default config file can be found at: **/packages/ti/boot/sbl/tools/flashWriter/qspi**. This config file may be altered to custom user settings if needed. j}r}(j]j]j]j]j]ujjYj]r~j)r}r(jXconfig helps specify the memory map. The default config file can be found at: **/packages/ti/boot/sbl/tools/flashWriter/qspi**. This config file may be altered to custom user settings if needed.jj{jj[jjj}r(j]j]j]j]j]ujKj]r(jXNconfig helps specify the memory map. The default config file can be found at: rr}r(jXNconfig helps specify the memory map. The default config file can be found at: jjubj)r}r(jXA**/packages/ti/boot/sbl/tools/flashWriter/qspi**j}r(j]j]j]j]j]ujjj]rjX=/packages/ti/boot/sbl/tools/flashWriter/qspirr}r(jUjjubajjubjXD. This config file may be altered to custom user settings if needed.rr}r(jXD. This config file may be altered to custom user settings if needed.jjubeubajjubejjwubeubj{)r}r(jX\In the SD card, rename MLO to "boot". This is the default name specified by the config file.jjIjj[jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX\In the SD card, rename MLO to "boot". This is the default name specified by the config file.rjjjj[jjj}r(j]j]j]j]j]ujKj]rjX\In the SD card, rename MLO to "boot". This is the default name specified by the config file.rr}r(jjjjubaubaubj{)r}r(jX5Insert the SD card into the SD card slot on the boardrjjIjj[jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj[jjj}r(j]j]j]j]j]ujKj]rjX5Insert the SD card into the SD card slot on the boardrr}r(jjjjubaubaubj{)r}r(jXConnect to the board with CCS. Launch target configuration and connect to the ARM A15 core. GEL file will run on-connect and do basic board-level initializationjjIjj[jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXConnect to the board with CCS. Launch target configuration and connect to the ARM A15 core. GEL file will run on-connect and do basic board-level initializationrjjjj[jjj}r(j]j]j]j]j]ujKj]rjXConnect to the board with CCS. Launch target configuration and connect to the ARM A15 core. GEL file will run on-connect and do basic board-level initializationrr}r(jjjjubaubaubj{)r}r(jXLoad the flash writer, qspi_flash_writer.out, to the connected core - A pre-built qspi_flash_writer.out can be found at: **/packages/ti/boot/sbl/tools/flashWriter/qspi/bin/evmK2G** jjIjNjjj}r(j]j]j]j]j]ujNjhj]r(j)r}r(jXCLoad the flash writer, qspi_flash_writer.out, to the connected corerjjjj[jjj}r(j]j]j]j]j]ujKj]rjXCLoad the flash writer, qspi_flash_writer.out, to the connected corerr}r(jjjjubaubjt)r}r(jUj}r(jyX-j]j]j]j]j]ujjj]rj{)r}r(jXA pre-built qspi_flash_writer.out can be found at: **/packages/ti/boot/sbl/tools/flashWriter/qspi/bin/evmK2G** j}r(j]j]j]j]j]ujjj]rj)r}r(jXA pre-built qspi_flash_writer.out can be found at: **/packages/ti/boot/sbl/tools/flashWriter/qspi/bin/evmK2G**jjjj[jjj}r(j]j]j]j]j]ujKj]r(jX3A pre-built qspi_flash_writer.out can be found at: rr}r(jX3A pre-built qspi_flash_writer.out can be found at: jjubj)r}r(jXL**/packages/ti/boot/sbl/tools/flashWriter/qspi/bin/evmK2G**j}r(j]j]j]j]j]ujjj]rjXH/packages/ti/boot/sbl/tools/flashWriter/qspi/bin/evmK2Grr}r(jUjjubajjubeubajjubajjwubeubj{)r}r(jXbRun the QSPI flash writer application. You will see the following logs on the EVM's UART console: jjIjj[jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXaRun the QSPI flash writer application. You will see the following logs on the EVM's UART console:rjjjj[jjj}r(j]j]j]j]j]ujKj]rjXaRun the QSPI flash writer application. You will see the following logs on the EVM's UART console:rr}r(jjjjubaubaubeubj)r}r(jX*** PDK QSPI Flash Writer *** Copying 'boot' to local memory Begin flashing 'boot' into QSPI Finished flashing 'boot' with size 20010 at offset 0 Copying 'app' to local memory Begin flashing 'app' into QSPI Finished flashing 'app' with size 19398 at offset 80000 Flashing completed!jjjj[jjj}r(j@jAj]j]j]j]j]ujMG-jhj]rjX*** PDK QSPI Flash Writer *** Copying 'boot' to local memory Begin flashing 'boot' into QSPI Finished flashing 'boot' with size 20010 at offset 0 Copying 'app' to local memory Begin flashing 'app' into QSPI Finished flashing 'app' with size 19398 at offset 80000 Flashing completed!rr}r(jUjjubaubj)r}r(jXThis application will flash the image at required offset without taking into consideration any overwriting to previously flashed image.rjjjj[jjj}r(j]j]j]j]j]ujKjhj]rjXThis application will flash the image at required offset without taking into consideration any overwriting to previously flashed image.rr}r(jjjjubaubeubj)r}r(jUjKjjjj[jjj}r(j]rXbooting via qspiraj]j]j]rUid111raj]ujKjhj]r(j)r}r(jXBooting via QSPIrjjjj[jjj}r(j]j]j]j]j]ujKjhj]rjXBooting via QSPIrr}r(jjjjubaubj )r}r(jUjjjj[jj j}r(jU.j]j]j]jUj]j]jjujKjhj]r(j{)r}r(jXSet the board to QSPI-48 bootmode by configuring the DIP switches to '1111'. Verify the bootmode on the LCD display on your boardjjjj[jjj}r(j]j]j]j]j]ujNjhj]rj)r }r (jXSet the board to QSPI-48 bootmode by configuring the DIP switches to '1111'. Verify the bootmode on the LCD display on your boardr jjjj[jjj}r (j]j]j]j]j]ujKj]r jXSet the board to QSPI-48 bootmode by configuring the DIP switches to '1111'. Verify the bootmode on the LCD display on your boardrr}r(jj jj ubaubaubj{)r}r(jXvOpen a serial communication terminal (such as TeraTerm, MiniCom, etc.) on host PC and connect to the UART console portjjjj[jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXvOpen a serial communication terminal (such as TeraTerm, MiniCom, etc.) on host PC and connect to the UART console portrjjjj[jjj}r(j]j]j]j]j]ujKj]rjXvOpen a serial communication terminal (such as TeraTerm, MiniCom, etc.) on host PC and connect to the UART console portrr}r(jjjjubaubaubj{)r}r(jXPower on the board jjjj[jjj}r(j]j]j]j]j]ujNjhj]r j)r!}r"(jXPower on the boardr#jjjj[jjj}r$(j]j]j]j]j]ujKj]r%jXPower on the boardr&r'}r((jj#jj!ubaubaubeubeubeubeubj)r)}r*(jUjKjjIjj[jjj}r+(j]r,X memory usager-aj]j]j]r.U memory-usager/aj]ujKjhj]r0(j)r1}r2(jX Memory Usager3jj)jj[jjj}r4(j]j]j]j]j]ujKjhj]r5jX Memory Usager6r7}r8(jj3jj1ubaubj)r9}r:(jX6SBL uses the last 0x40000 memory from MSMC RAM memory.r;jj)jj[jjj}r<(j]j]j]j]j]ujKjhj]r=jX6SBL uses the last 0x40000 memory from MSMC RAM memory.r>r?}r@(jj;jj9ubaubj)rA}rB(jX"The SBL memory map is shown below:rCjj)jj[jjj}rD(j]j]j]j]j]ujKjhj]rEjX"The SBL memory map is shown below:rFrG}rH(jjCjjAubaubjR)rI}rJ(jX%.. Image:: ../images/SBL_mem_k2g.jpg jj)jj[jjZj}rK(UuriXrtos/../images/SBL_mem_k2g.jpgrLj]j]j]j]jX}rMU*jLsj]ujKjhj]ubj)rN}rO(jXapp should not have loadable sections residing in SBL memory region to prevent overwriting SBL during load time. It is, however, free to use SBL memory after it is loaded and running.jj)jj[jjj}rP(j]j]j]j]j]ujNjhj]rQj)rR}rS(jXapp should not have loadable sections residing in SBL memory region to prevent overwriting SBL during load time. It is, however, free to use SBL memory after it is loaded and running.rTjjNjj[jjj}rU(j]j]j]j]j]ujKj]rVjXapp should not have loadable sections residing in SBL memory region to prevent overwriting SBL during load time. It is, however, free to use SBL memory after it is loaded and running.rWrX}rY(jjTjjRubaubaubeubeubj)rZ}r[(jUjj;jjjjj}r\(j]j]j]j]r]U k2h-k2e-k2lr^aj]r_jEaujKajhj]r`(j)ra}rb(jX K2H/K2E/K2LrcjjZjjjjj}rd(j]j]j]j]j]ujKajhj]rejX K2H/K2E/K2Lrfrg}rh(jjcjjaubaubj7)ri}rj(jXGhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_BOOT_K2H/E/LjjZjj:XVsource/rtos/PDK_Platform_Software/Boot_Board_and_EVM_Abstractions/BOOT_K2H_E_L.rst.incrkrl}rmbjj>j}rn(j@jAj]j]j]j]j]ujKjhj]rojXGhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_BOOT_K2H/E/Lrprq}rr(jUjjiubaubj)rs}rt(jUjKjjZjjljjj}ru(j]rvXoverviewrwaj]j]j]rxUid112ryaj]ujKjhj]rz(j)r{}r|(jXOverviewr}jjsjjljjj}r~(j]j]j]j]j]ujKjhj]rjXOverviewrr}r(jj}jj{ubaubj)r}r(jX=K2H/K2E/K2L EVMs uses the Secondary Boot Loader (SBL) to configure board-related settings and execute a user application. The user application can be single core or multicore, and execute on either DSP cores or ARM cores. The only restriction is that the load sections must not overlap the memory space that SBL uses.rjjsjjljjj}r(j]j]j]j]j]ujKjhj]rjX=K2H/K2E/K2L EVMs uses the Secondary Boot Loader (SBL) to configure board-related settings and execute a user application. The user application can be single core or multicore, and execute on either DSP cores or ARM cores. The only restriction is that the load sections must not overlap the memory space that SBL uses.rr}r(jjjjubaubj)r}r(jXThe K2H/K2E/K2L SBL supports ARM master boot using SPI NOR. Please refer to the boot mode dip switch settings in the respective EVM hardware page (`link `__) to configure your EVM for NOR boot.jjsjjljjj}r(j]j]j]j]j]ujK jhj]r(jXThe K2H/K2E/K2L SBL supports ARM master boot using SPI NOR. Please refer to the boot mode dip switch settings in the respective EVM hardware page (rr}r(jXThe K2H/K2E/K2L SBL supports ARM master boot using SPI NOR. Please refer to the boot mode dip switch settings in the respective EVM hardware page (jjubj)r}r(jXG`link `__j}r(UnameXlinkjX<index_release_specific.html#supported-platforms-and-versionsj]j]j]j]j]ujjj]rjXlinkrr}r(jUjjubajjubjX%) to configure your EVM for NOR boot.rr}r(jX%) to configure your EVM for NOR boot.jjubeubeubj)r}r(jUjKjjZjjljjj}r(j]rjbaj]j]j]rUid113raj]ujKjhj]r(j)r}r(jXFlashing the Bootloaderrjjjjljjj}r(j]j]j]j]j]ujKjhj]rjXFlashing the Bootloaderrr}r(jjjjubaubj)r}r(jX:SBL and user application needs to be flashed into SPI NOR.rjjjjljjj}r(j]j]j]j]j]ujKjhj]rjX:SBL and user application needs to be flashed into SPI NOR.rr}r(jjjjubaubj)r}r(jXRefer to `Program EVM Guide `__ for instructions on using the script, program_evm.js, to automatically flash your device.jjjjljjj}r(j]j]j]j]j]ujKjhj]r(jX Refer to rr}r(jX Refer to jjubj)r}r(jXN`Program EVM Guide `__j}r(UnameXProgram EVM GuidejX6http://processors.wiki.ti.com/index.php/Program_EVM_UGj]j]j]j]j]ujjj]rjXProgram EVM Guiderr}r(jUjjubajjubjXZ for instructions on using the script, program_evm.js, to automatically flash your device.rr}r(jXZ for instructions on using the script, program_evm.js, to automatically flash your device.jjubeubeubj)r}r(jUjKjjZjjljjj}r(j]rXusageraj]j]j]rUid114raj]ujKjhj]r(j)r}r(jXUsagerjjjjljjj}r(j]j]j]j]j]ujKjhj]rjXUsagerr}r(jjjjubaubj )r}r(jUjjjjljj j}r(jU.j]j]j]jUj]j]jjujKjhj]r(j{)r}r(jXtFlash the bootloader and user application. This can be done automatically with default files by using program_evm.jsjjjjljjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXtFlash the bootloader and user application. This can be done automatically with default files by using program_evm.jsrjjjjljjj}r(j]j]j]j]j]ujKj]rjXtFlash the bootloader and user application. This can be done automatically with default files by using program_evm.jsrr}r(jjjjubaubaubj{)r}r(jX Set the EVM to ARM SPI boot moderjjjjljjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjljjj}r(j]j]j]j]j]ujKj]rjX Set the EVM to ARM SPI boot moderr}r(jjjjubaubaubj{)r}r(jXConnect UART serial debug cable from EVM to your computer. Open a terminal such as HyperTerminal or TeraTerm to see console outputjjjjljjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXConnect UART serial debug cable from EVM to your computer. Open a terminal such as HyperTerminal or TeraTerm to see console outputrjjjjljjj}r(j]j]j]j]j]ujK j]rjXConnect UART serial debug cable from EVM to your computer. Open a terminal such as HyperTerminal or TeraTerm to see console outputrr}r(jjjjubaubaubj{)r}r(jXPower on the EVM jjjjljjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXPower on the EVMrjjjjljjj}r(j]j]j]j]j]ujK"j]rjXPower on the EVMrr}r(jjjjubaubaubeubeubj)r}r (jUjKjjZjjljjj}r (j]r X compilationr aj]j]j]r Uid115raj]ujK%jhj]r(j)r}r(jX Compilationrjjjjljjj}r(j]j]j]j]j]ujK%jhj]rjX Compilationrr}r(jjjjubaubj)r}r(jXThe recommended rule-of-thumb to compiling projects in the Processor SDK RTOS package is to use the makefiles provided. The makefiles are usable after setting up your shell/terminal/command prompt environment with the setupenv.bat or setupenv.sh script located inrjjjjljjj}r(j]j]j]j]j]ujK'jhj]rjXThe recommended rule-of-thumb to compiling projects in the Processor SDK RTOS package is to use the makefiles provided. The makefiles are usable after setting up your shell/terminal/command prompt environment with the setupenv.bat or setupenv.sh script located inrr}r(jjjjubaubj)r }r!(jX:[SDK Install Path]/processor_sdk_rtos__jjjjljjj}r"(j@jAj]j]j]j]j]ujM-jhj]r#jX:[SDK Install Path]/processor_sdk_rtos__r$r%}r&(jUjj ubaubj)r'}r((jXRefer to `Building RTOS SDK `__ page on how to setup your environment for building within any of the Processor SDK RTOS packages.jjjjljjj}r)(j]j]j]j]j]ujK0jhj]r*(jX Refer to r+r,}r-(jX Refer to jj'ubj)r.}r/(jX<`Building RTOS SDK `__j}r0(UnameXBuilding RTOS SDKjX$index_overview.html#building-the-sdkj]j]j]j]j]ujj'j]r1jXBuilding RTOS SDKr2r3}r4(jUjj.ubajjubjXb page on how to setup your environment for building within any of the Processor SDK RTOS packages.r5r6}r7(jXb page on how to setup your environment for building within any of the Processor SDK RTOS packages.jj'ubeubj)r8}r9(jX The SBL package can be found in:r:jjjjljjj}r;(j]j]j]j]j]ujK4jhj]r<jX The SBL package can be found in:r=r>}r?(jj:jj8ubaubj)r@}rA(jX@[SDK Install Path]/pdk__/packages/ti/boot/sbljjjjljjj}rB(j@jAj]j]j]j]j]ujM-jhj]rCjX@[SDK Install Path]/pdk__/packages/ti/boot/sblrDrE}rF(jUjj@ubaubj)rG}rH(jX To build:rIjjjjljjj}rJ(j]j]j]j]j]ujK:jhj]rKjX To build:rLrM}rN(jjIjjGubaubj)rO}rP(jXtcd [SDK Install Path]/pdk__/packages/ti/boot/sbl make all BOOTMODE=spi BOARD= SOC=jjjjljjj}rQ(j@jAj]j]j]j]j]ujM-jhj]rRjXtcd [SDK Install Path]/pdk__/packages/ti/boot/sbl make all BOOTMODE=spi BOARD= SOC=rSrT}rU(jUjjOubaubj)rV}rW(jXK** can be of values: **evmK2H**, **evmK2E**, **evmK2L**, or **evmK2K**jjjjljjj}rX(j]j]j]j]j]ujKAjhj]rY(jM)rZ}r[(jX**j}r\(j]j]j]j]j]ujjVj]r]jXr^r_}r`(jUjjZubajjUubjX can be of values: rarb}rc(jX can be of values: jjVubj)rd}re(jX **evmK2H**j}rf(j]j]j]j]j]ujjVj]rgjXevmK2Hrhri}rj(jUjjdubajjubjX, rkrl}rm(jX, jjVubj)rn}ro(jX **evmK2E**j}rp(j]j]j]j]j]ujjVj]rqjXevmK2Errrs}rt(jUjjnubajjubjX, rurv}rw(jX, jjVubj)rx}ry(jX **evmK2L**j}rz(j]j]j]j]j]ujjVj]r{jXevmK2Lr|r}}r~(jUjjxubajjubjX, or rr}r(jX, or jjVubj)r}r(jX **evmK2K**j}r(j]j]j]j]j]ujjVj]rjXevmK2Krr}r(jUjjubajjubeubj)r}r(jXD** can be of values: **K2H**, **K2E**, **K2L**, or **K2K**rjjjjljjj}r(j]j]j]j]j]ujKDjhj]r(jM)r}r(jX **j}r(j]j]j]j]j]ujjj]rjX rr}r(jUjjubajjUubjX can be of values: rr}r(jX can be of values: jjubj)r}r(jX**K2H**j}r(j]j]j]j]j]ujjj]rjXK2Hrr}r(jUjjubajjubjX, rr}r(jX, jjubj)r}r(jX**K2E**j}r(j]j]j]j]j]ujjj]rjXK2Err}r(jUjjubajjubjX, rr}r(jX, jjubj)r}r(jX**K2L**j}r(j]j]j]j]j]ujjj]rjXK2Lrr}r(jUjjubajjubjX, or rr}r(jX, or jjubj)r}r(jX**K2K**j}r(j]j]j]j]j]ujjj]rjXK2Krr}r(jUjjubajjubeubj)r}r(jXThe resulting output will be in [SDK Install Path]/pdk__/packages/ti/boot/sbl/binary//spi/bin directory.rjjjjljjj}r(j]j]j]j]j]ujKFjhj]rjXThe resulting output will be in [SDK Install Path]/pdk__/packages/ti/boot/sbl/binary//spi/bin directory.rr}r(jjjjubaubeubj)r}r(jUjKjjZjjljjj}r(j]rj$aj]j]j]rUid116raj]ujKKjhj]r(j)r}r(jX,Making Loadable User Application image (app)rjjjjljjj}r(j]j]j]j]j]ujKKjhj]rjX,Making Loadable User Application image (app)rr}r(jjjjubaubj)r}r(jXFor converting the compiled .out files to a format loadable by TI's Secondary Boot Loader (SBL), you must follow these two steps:rjjjjljjj}r(j]j]j]j]j]ujKMjhj]rjXFor converting the compiled .out files to a format loadable by TI's Secondary Boot Loader (SBL), you must follow these two steps:rr}r(jjjjubaubj )r}r(jUjjjjljj j}r(jU.j]j]j]jUj]j]jjujKPjhj]r(j{)r}r(jX***out2rprc.exe [.out file] [rprc output]**rjjjjljjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjljjj}r(j]j]j]j]j]ujKPj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX&out2rprc.exe [.out file] [rprc output]rr}r(jUjjubajjubaubaubj{)r}r(jX>**MulticoreImageGen.exe LE 55 [output name] 0 [rprc output]** jjjjljjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX=**MulticoreImageGen.exe LE 55 [output name] 0 [rprc output]**rjjjjljjj}r(j]j]j]j]j]ujKQj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX9MulticoreImageGen.exe LE 55 [output name] 0 [rprc output]rr}r(jUjjubajjubaubaubeubj)r}r(jXOut2rprc.exe and MulticoreImageGen.exe are tools supplied by TI and can be located in the **/packages/ti/boot/sbl/tools** folder. "rprc output" can be any spare name of your choosing. "output name" can also be any name of your choosing.jjjjljjj}r(j]j]j]j]j]ujKSjhj]r(jXZOut2rprc.exe and MulticoreImageGen.exe are tools supplied by TI and can be located in the rr}r(jXZOut2rprc.exe and MulticoreImageGen.exe are tools supplied by TI and can be located in the jjubj)r}r(jX0**/packages/ti/boot/sbl/tools**j}r (j]j]j]j]j]ujjj]r jX,/packages/ti/boot/sbl/toolsr r }r (jUjjubajjubjXs folder. "rprc output" can be any spare name of your choosing. "output name" can also be any name of your choosing.rr}r(jXs folder. "rprc output" can be any spare name of your choosing. "output name" can also be any name of your choosing.jjubeubj)r}r(jXThe '0' used in step 2 refers to the Core ID to boot. By default, '0' is MPU (Cortex A15) core 0. You can input a different value to boot to other cores. Valid values are:rjjjjljjj}r(j]j]j]j]j]ujKXjhj]rjXThe '0' used in step 2 refers to the Core ID to boot. By default, '0' is MPU (Cortex A15) core 0. You can input a different value to boot to other cores. Valid values are:rr}r(jjjjubaubjy )r}r(jUjjjjljj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujjj]r (j )r!}r"(jUj}r#(j]j]j]j]j]UcolwidthK ujjj]jj ubj )r$}r%(jUj}r&(j]j]j]j]j]UcolwidthK ujjj]jj ubj )r'}r((jUj}r)(j]j]j]j]j]UcolwidthK ujjj]jj ubj )r*}r+(jUj}r,(j]j]j]j]j]UcolwidthK ujjj]jj ubj )r-}r.(jUj}r/(j]j]j]j]j]UcolwidthK ujjj]jj ubj )r0}r1(jUj}r2(j]j]j]j]j]UcolwidthK ujjj]jj ubj )r3}r4(jUj}r5(j]j]j]j]j]ujjj]r6j )r7}r8(jUj}r9(j]j]j]j]j]ujj3j]r:(j )r;}r<(jUj}r=(j]UmorecolsKj]j]j]j]ujj7j]r>j)r?}r@(jXK2HrAjj;jjljjj}rB(j]j]j]j]j]ujKkj]rCjXK2HrDrE}rF(jjAjj?ubaubajj ubj )rG}rH(jUj}rI(j]UmorecolsKj]j]j]j]ujj7j]rJj)rK}rL(jXK2ErMjjGjjljjj}rN(j]j]j]j]j]ujKkj]rOjXK2ErPrQ}rR(jjMjjKubaubajj ubj )rS}rT(jUj}rU(j]UmorecolsKj]j]j]j]ujj7j]rVj)rW}rX(jXK2LrYjjSjjljjj}rZ(j]j]j]j]j]ujKkj]r[jXK2Lr\r]}r^(jjYjjWubaubajj ubejj ubajj ubj )r_}r`(jUj}ra(j]j]j]j]j]ujjj]rb(j )rc}rd(jUj}re(j]j]j]j]j]ujj_j]rf(j )rg}rh(jUj}ri(j]j]j]j]j]ujjcj]rjj)rk}rl(jX**Core**rmjjgjjljjj}rn(j]j]j]j]j]ujKmj]roj)rp}rq(jjmj}rr(j]j]j]j]j]ujjkj]rsjXCorertru}rv(jUjjpubajjubaubajj ubj )rw}rx(jUj}ry(j]j]j]j]j]ujjcj]rzj)r{}r|(jX **Value**r}jjwjjljjj}r~(j]j]j]j]j]ujKmj]rj)r}r(jj}j}r(j]j]j]j]j]ujj{j]rjXValuerr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjcj]rj)r}r(jX**Core**rjjjjljjj}r(j]j]j]j]j]ujKmj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXCorerr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjcj]rj)r}r(jX **Value**rjjjjljjj}r(j]j]j]j]j]ujKmj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXValuerr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjcj]rj)r}r(jX**Core**rjjjjljjj}r(j]j]j]j]j]ujKmj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXCorerr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjcj]rj)r}r(jX **Value**rjjjjljjj}r(j]j]j]j]j]ujKmj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXValuerr}r(jUjjubajjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujj_j]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX MPU Core 0rjjjjljjj}r(j]j]j]j]j]ujKoj]rjX MPU Core 0rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX0jjjjljjj}r(j]j]j]j]j]ujKoj]rjX0r}r(jX0jjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX MPU Core 0rjjjjljjj}r(j]j]j]j]j]ujKoj]rjX MPU Core 0rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX0jjjjljjj}r(j]j]j]j]j]ujKoj]rjX0r}r(jX0jjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX MPU Core 0rjjjjljjj}r(j]j]j]j]j]ujKoj]rjX MPU Core 0rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX0jjjjljjj}r (j]j]j]j]j]ujKoj]r jX0r }r (jX0jjubaubajj ubejj ubj )r }r(jUj}r(j]j]j]j]j]ujj_j]r(j )r}r(jUj}r(j]j]j]j]j]ujj j]rj)r}r(jX MPU Core 1rjjjjljjj}r(j]j]j]j]j]ujKqj]rjX MPU Core 1rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj j]r j)r!}r"(jX1jjjjljjj}r#(j]j]j]j]j]ujKqj]r$jX1r%}r&(jX1jj!ubaubajj ubj )r'}r((jUj}r)(j]j]j]j]j]ujj j]r*j)r+}r,(jX MPU Core 1r-jj'jjljjj}r.(j]j]j]j]j]ujKqj]r/jX MPU Core 1r0r1}r2(jj-jj+ubaubajj ubj )r3}r4(jUj}r5(j]j]j]j]j]ujj j]r6j)r7}r8(jX1jj3jjljjj}r9(j]j]j]j]j]ujKqj]r:jX1r;}r<(jX1jj7ubaubajj ubj )r=}r>(jUj}r?(j]j]j]j]j]ujj j]r@j)rA}rB(jX MPU Core 1rCjj=jjljjj}rD(j]j]j]j]j]ujKqj]rEjX MPU Core 1rFrG}rH(jjCjjAubaubajj ubj )rI}rJ(jUj}rK(j]j]j]j]j]ujj j]rLj)rM}rN(jX1jjIjjljjj}rO(j]j]j]j]j]ujKqj]rPjX1rQ}rR(jX1jjMubaubajj ubejj ubj )rS}rT(jUj}rU(j]j]j]j]j]ujj_j]rV(j )rW}rX(jUj}rY(j]j]j]j]j]ujjSj]rZj)r[}r\(jX MPU Core 2r]jjWjjljjj}r^(j]j]j]j]j]ujKsj]r_jX MPU Core 2r`ra}rb(jj]jj[ubaubajj ubj )rc}rd(jUj}re(j]j]j]j]j]ujjSj]rfj)rg}rh(jX2jjcjjljjj}ri(j]j]j]j]j]ujKsj]rjjX2rk}rl(jX2jjgubaubajj ubj )rm}rn(jUj}ro(j]j]j]j]j]ujjSj]rpj)rq}rr(jX MPU Core 2rsjjmjjljjj}rt(j]j]j]j]j]ujKsj]rujX MPU Core 2rvrw}rx(jjsjjqubaubajj ubj )ry}rz(jUj}r{(j]j]j]j]j]ujjSj]r|j)r}}r~(jX2jjyjjljjj}r(j]j]j]j]j]ujKsj]rjX2r}r(jX2jj}ubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjSj]rj)r}r(jXMPU SMPrjjjjljjj}r(j]j]j]j]j]ujKsj]rjXMPU SMPrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjSj]rj)r}r(jX4jjjjljjj}r(j]j]j]j]j]ujKsj]rjX4r}r(jX4jjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujj_j]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX MPU Core 3rjjjjljjj}r(j]j]j]j]j]ujKuj]rjX MPU Core 3rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX3jjjjljjj}r(j]j]j]j]j]ujKuj]rjX3r}r(jX3jjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX MPU Core 3rjjjjljjj}r(j]j]j]j]j]ujKuj]rjX MPU Core 3rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX3jjjjljjj}r(j]j]j]j]j]ujKuj]rjX3r}r(jX3jjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX DSP Core 0rjjjjljjj}r(j]j]j]j]j]ujKuj]rjX DSP Core 0rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX5jjjjljjj}r(j]j]j]j]j]ujKuj]rjX5r}r(jX5jjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujj_j]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXMPU SMPrjjjjljjj}r(j]j]j]j]j]ujKwj]rjXMPU SMPrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX4jjjjljjj}r(j]j]j]j]j]ujKwj]rjX4r}r(jX4jjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXMPU SMPrjjjjljjj}r(j]j]j]j]j]ujKwj]rjXMPU SMPrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r }r (jX4jjjjljjj}r (j]j]j]j]j]ujKwj]r jX4r }r(jX4jj ubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX DSP Core 1rjjjjljjj}r(j]j]j]j]j]ujKwj]rjX DSP Core 1rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r (jX6jjjjljjj}r!(j]j]j]j]j]ujKwj]r"jX6r#}r$(jX6jjubaubajj ubejj ubj )r%}r&(jUj}r'(j]j]j]j]j]ujj_j]r((j )r)}r*(jUj}r+(j]j]j]j]j]ujj%j]r,j)r-}r.(jX DSP Core 0r/jj)jjljjj}r0(j]j]j]j]j]ujKyj]r1jX DSP Core 0r2r3}r4(jj/jj-ubaubajj ubj )r5}r6(jUj}r7(j]j]j]j]j]ujj%j]r8j)r9}r:(jX5jj5jjljjj}r;(j]j]j]j]j]ujKyj]r<jX5r=}r>(jX5jj9ubaubajj ubj )r?}r@(jUj}rA(j]j]j]j]j]ujj%j]rBj)rC}rD(jX DSP Core 0rEjj?jjljjj}rF(j]j]j]j]j]ujKyj]rGjX DSP Core 0rHrI}rJ(jjEjjCubaubajj ubj )rK}rL(jUj}rM(j]j]j]j]j]ujj%j]rNj)rO}rP(jX5jjKjjljjj}rQ(j]j]j]j]j]ujKyj]rRjX5rS}rT(jX5jjOubaubajj ubj )rU}rV(jUj}rW(j]j]j]j]j]ujj%j]rXj)rY}rZ(jX DSP Core 2r[jjUjjljjj}r\(j]j]j]j]j]ujKyj]r]jX DSP Core 2r^r_}r`(jj[jjYubaubajj ubj )ra}rb(jUj}rc(j]j]j]j]j]ujj%j]rdj)re}rf(jX7jjajjljjj}rg(j]j]j]j]j]ujKyj]rhjX7ri}rj(jX7jjeubaubajj ubejj ubj )rk}rl(jUj}rm(j]j]j]j]j]ujj_j]rn(j )ro}rp(jUj}rq(j]j]j]j]j]ujjkj]rrj)rs}rt(jX DSP Core 1rujjojjljjj}rv(j]j]j]j]j]ujK{j]rwjX DSP Core 1rxry}rz(jjujjsubaubajj ubj )r{}r|(jUj}r}(j]j]j]j]j]ujjkj]r~j)r}r(jX6jj{jjljjj}r(j]j]j]j]j]ujK{j]rjX6r}r(jX6jjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjkj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjkj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjkj]rj)r}r(jX DSP Core 3rjjjjljjj}r(j]j]j]j]j]ujK{j]rjX DSP Core 3rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjkj]rj)r}r(jX8jjjjljjj}r(j]j]j]j]j]ujK{j]rjX8r}r(jX8jjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujj_j]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX DSP Core 2rjjjjljjj}r(j]j]j]j]j]ujK}j]rjX DSP Core 2rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX7jjjjljjj}r(j]j]j]j]j]ujK}j]rjX7r}r(jX7jjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]jj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujj_j]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX DSP Core 3rjjjjljjj}r(j]j]j]j]j]ujKj]rjX DSP Core 3rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX8jjjjljjj}r(j]j]j]j]j]ujKj]rjX8r}r(jX8jjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]jj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujj_j]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX DSP Core 4rjjjjljjj}r(j]j]j]j]j]ujKj]rjX DSP Core 4rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX9jjjjljjj}r(j]j]j]j]j]ujKj]rjX9r}r(jX9jjubaubajj ubj )r}r(jUj}r (j]j]j]j]j]ujjj]jj ubj )r }r (jUj}r (j]j]j]j]j]ujjj]jj ubj )r }r(jUj}r(j]j]j]j]j]ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]jj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujj_j]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX DSP Core 5rjjjjljjj}r(j]j]j]j]j]ujKj]rjX DSP Core 5r r!}r"(jjjjubaubajj ubj )r#}r$(jUj}r%(j]j]j]j]j]ujjj]r&j)r'}r((jX10r)jj#jjljjj}r*(j]j]j]j]j]ujKj]r+jX10r,r-}r.(jj)jj'ubaubajj ubj )r/}r0(jUj}r1(j]j]j]j]j]ujjj]jj ubj )r2}r3(jUj}r4(j]j]j]j]j]ujjj]jj ubj )r5}r6(jUj}r7(j]j]j]j]j]ujjj]jj ubj )r8}r9(jUj}r:(j]j]j]j]j]ujjj]jj ubejj ubj )r;}r<(jUj}r=(j]j]j]j]j]ujj_j]r>(j )r?}r@(jUj}rA(j]j]j]j]j]ujj;j]rBj)rC}rD(jX DSP Core 6rEjj?jjljjj}rF(j]j]j]j]j]ujKj]rGjX DSP Core 6rHrI}rJ(jjEjjCubaubajj ubj )rK}rL(jUj}rM(j]j]j]j]j]ujj;j]rNj)rO}rP(jX11rQjjKjjljjj}rR(j]j]j]j]j]ujKj]rSjX11rTrU}rV(jjQjjOubaubajj ubj )rW}rX(jUj}rY(j]j]j]j]j]ujj;j]jj ubj )rZ}r[(jUj}r\(j]j]j]j]j]ujj;j]jj ubj )r]}r^(jUj}r_(j]j]j]j]j]ujj;j]jj ubj )r`}ra(jUj}rb(j]j]j]j]j]ujj;j]jj ubejj ubj )rc}rd(jUj}re(j]j]j]j]j]ujj_j]rf(j )rg}rh(jUj}ri(j]j]j]j]j]ujjcj]rjj)rk}rl(jX DSP Core 7rmjjgjjljjj}rn(j]j]j]j]j]ujKj]rojX DSP Core 7rprq}rr(jjmjjkubaubajj ubj )rs}rt(jUj}ru(j]j]j]j]j]ujjcj]rvj)rw}rx(jX12ryjjsjjljjj}rz(j]j]j]j]j]ujKj]r{jX12r|r}}r~(jjyjjwubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjcj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjcj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjcj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjcj]jj ubejj ubejj ubejj ubaubj)r}r(jXIf MPU SMP is chosen, the same boot image and entry will be used for all MPU cores. SBL can also parse multiple boot images that are concatenated together. Simply use MulticoreImageGen as such:rjjjjljjj}r(j]j]j]j]j]ujKjhj]rjXIf MPU SMP is chosen, the same boot image and entry will be used for all MPU cores. SBL can also parse multiple boot images that are concatenated together. Simply use MulticoreImageGen as such:rr}r(jjjjubaubj)r}r(jX**MulticoreImageGen.exe LE 55 [output name] [Core ID a] [rprc output a] [Core ID b] [rprc output b] [Core ID c] [rprc output c] ...**rjjjjljjj}r(j]j]j]j]j]ujKjhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXMulticoreImageGen.exe LE 55 [output name] [Core ID a] [rprc output a] [Core ID b] [rprc output b] [Core ID c] [rprc output c] ...rr}r(jUjjubajjubaubeubj)r}r(jUjKjjZjjljjj}r(j]rjǶaj]j]j]rUid117raj]ujKjhj]r(j)r}r(jX Flash Writersrjjjjljjj}r(j]j]j]j]j]ujKjhj]rjX Flash Writersrr}r(jjjjubaubj)r}r(jUjjjjljjj}r(j]j]j]j]rU spi-writerraj]rhbaujKjhj]r(j)r}r(jX SPI Writerrjjjjljjj}r(j]j]j]j]j]ujKjhj]rjX SPI Writerrr}r(jjjjubaubj)r}r(jXThe SPI flash writer, spi_flash_writer.out, is a part of the SBL package and allows users to flash multiple images at different offsets into the board's SPI NOR flash memory.rjjjjljjj}r(j]j]j]j]j]ujKjhj]rjXThe SPI flash writer, spi_flash_writer.out, is a part of the SBL package and allows users to flash multiple images at different offsets into the board's SPI NOR flash memory.rr}r(jjjjubaubj)r}r(jUjKjjjjljjj}r(j]rX compilationraj]j]j]rUid118raj]ujKjhj]r(j)r}r(jX Compilationrjjjjljjj}r(j]j]j]j]j]ujKjhj]rjX Compilationrr}r(jjjjubaubj)r}r(jXtcd [SDK Install Path]/pdk__/packages/ti/boot/sbl/ make spi_flashwriter BOARD= SOC=jjjjljjj}r(j@jAj]j]j]j]j]ujM.jhj]rjXtcd [SDK Install Path]/pdk__/packages/ti/boot/sbl/ make spi_flashwriter BOARD= SOC=rr}r(jUjjubaubj)r}r(jXThe binary output will be at:rjjjjljjj}r(j]j]j]j]j]ujKjhj]rjXThe binary output will be at:rr}r(jjjjubaubj)r}r(jXe[SDK Install Path]/pdk__/packages/ti/boot/sbl/tools/flashWriter/spi/bin/jjjjljjj}r(j@jAj]j]j]j]j]ujM.jhj]rjXe[SDK Install Path]/pdk__/packages/ti/boot/sbl/tools/flashWriter/spi/bin/rr}r(jUjjubaubeubj)r}r(jUjKjjjjljjj}r(j]rXusageraj]j]j]rUid119raj]ujKjhj]r(j)r}r(jXUsagerjjjjljjj}r(j]j]j]j]j]ujKjhj]rjXUsagerr}r(jjjjubaubj )r}r(jUjjjjljj j}r(jU.j]j]j]jUj]j]jjujKjhj]r(j{)r}r(jXCopy the binaries that you want to flash to: [SDK Install Path]/pdk__/packages/ti/boot/sbl/tools/flashWriter/spi/bin/jjjjljjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXCopy the binaries that you want to flash to: [SDK Install Path]/pdk__/packages/ti/boot/sbl/tools/flashWriter/spi/bin/rjjjjljjj}r(j]j]j]j]j]ujKj]rjXCopy the binaries that you want to flash to: [SDK Install Path]/pdk__/packages/ti/boot/sbl/tools/flashWriter/spi/bin/rr }r (jjjjubaubaubj{)r }r (jXIn that same directory, there is a file named **config**. Edit that file such that each line has 2 parameters: [name of binary to flash] [SPI NOR offset to flash to]jjjjljjj}r (j]j]j]j]j]ujNjhj]rj)r}r(jXIn that same directory, there is a file named **config**. Edit that file such that each line has 2 parameters: [name of binary to flash] [SPI NOR offset to flash to]jj jjljjj}r(j]j]j]j]j]ujKj]r(jX.In that same directory, there is a file named rr}r(jX.In that same directory, there is a file named jjubj)r}r(jX **config**j}r(j]j]j]j]j]ujjj]rjXconfigrr}r(jUjjubajjubjXm. Edit that file such that each line has 2 parameters: [name of binary to flash] [SPI NOR offset to flash to]rr}r(jXm. Edit that file such that each line has 2 parameters: [name of binary to flash] [SPI NOR offset to flash to]jjubeubaubj{)r }r!(jX`Set your EVM to NO BOOT. Power on, launch target configuration in CCS, and connect to DSP Core 0jjjjljjj}r"(j]j]j]j]j]ujNjhj]r#j)r$}r%(jX`Set your EVM to NO BOOT. Power on, launch target configuration in CCS, and connect to DSP Core 0r&jj jjljjj}r'(j]j]j]j]j]ujKj]r(jX`Set your EVM to NO BOOT. Power on, launch target configuration in CCS, and connect to DSP Core 0r)r*}r+(jj&jj$ubaubaubj{)r,}r-(jXLoad and run [SDK Install Path]/pdk__/packages/ti/boot/sbl/tools/flashWriter/spi/bin//spi_flash_writer.outjjjjljjj}r.(j]j]j]j]j]ujNjhj]r/j)r0}r1(jXLoad and run [SDK Install Path]/pdk__/packages/ti/boot/sbl/tools/flashWriter/spi/bin//spi_flash_writer.outr2jj,jjljjj}r3(j]j]j]j]j]ujKj]r4jXLoad and run [SDK Install Path]/pdk__/packages/ti/boot/sbl/tools/flashWriter/spi/bin//spi_flash_writer.outr5r6}r7(jj2jj0ubaubaubj{)r8}r9(jX:You should see the flash progress output on UART terminal jjjjljjj}r:(j]j]j]j]j]ujNjhj]r;j)r<}r=(jX9You should see the flash progress output on UART terminalr>jj8jjljjj}r?(j]j]j]j]j]ujKj]r@jX9You should see the flash progress output on UART terminalrArB}rC(jj>jj<ubaubaubeubjc)rD}rE(jUjjjjljjfj}rF(j]j]j]j]j]ujKjhj]rGji)rH}rI(jUjlKjjDjjljjj}rJ(j]j]j]j]j]ujKjhj]ubaubeubeubeubj)rK}rL(jUjjZjjljjj}rM(j]j]j]j]rNU boot-examplerOaj]rPjtaujKjhj]rQ(j)rR}rS(jX Boot ExamplerTjjKjjljjj}rU(j]j]j]j]j]ujKjhj]rVjX Boot ExamplerWrX}rY(jjTjjRubaubj)rZ}r[(jX^Below is an example output of evmK2H booting after having images flashed in by program_evm.js:r\jjKjjljjj}r](j]j]j]j]j]ujKjhj]r^jX^Below is an example output of evmK2H booting after having images flashed in by program_evm.js:r_r`}ra(jj\jjZubaubj)rb}rc(jX**** PDK SBL **** Boot succesful! Begin parsing user application Jumping to user application... TMDXEVM6636K2H POST Version 01.00.00.08 ------------------------------------------ SOC Information BMC Version: 0000 EFUSE MAC ID is: B4 99 4C B6 E2 5B SA is enabled on this board. PLL Reset Type Status Register: 0x00000001 Platform init return code: 0x00000000 Power On Self Test POST running in progress ... POST I2C EEPROM read test started! POST I2C EEPROM read test passed! POST SPI NOR read test started! POST SPI NOR read test passed! POST EMIF16 NAND read test started! POST EMIF16 NAND read test passed! POST external memory test started! POST external memory test passed! POST done successfully! POST result: PASSjjKjjljjj}rd(j@jAj]j]j]j]j]ujM5.jhj]rejX**** PDK SBL **** Boot succesful! Begin parsing user application Jumping to user application... TMDXEVM6636K2H POST Version 01.00.00.08 ------------------------------------------ SOC Information BMC Version: 0000 EFUSE MAC ID is: B4 99 4C B6 E2 5B SA is enabled on this board. PLL Reset Type Status Register: 0x00000001 Platform init return code: 0x00000000 Power On Self Test POST running in progress ... POST I2C EEPROM read test started! POST I2C EEPROM read test passed! POST SPI NOR read test started! POST SPI NOR read test passed! POST EMIF16 NAND read test started! POST EMIF16 NAND read test passed! POST external memory test started! POST external memory test passed! POST done successfully! POST result: PASSrfrg}rh(jUjjbubaubeubeubj)ri}rj(jUjj;jjjjj}rk(j]j]j]j]rlUomapl137-omapl138-c6748rmaj]rnhaujKfjhj]ro(j)rp}rq(jXOMAPL137/OMAPL138/C6748rrjjijjjjj}rs(j]j]j]j]j]ujKfjhj]rtjXOMAPL137/OMAPL138/C6748rurv}rw(jjrjjpubaubj7)rx}ry(jXHhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_BOOT_OMAPL13xjjijj:XWsource/rtos/PDK_Platform_Software/Boot_Board_and_EVM_Abstractions/BOOT_OMAPL13x.rst.incrzr{}r|bjj>j}r}(j@jAj]j]j]j]j]ujKjhj]r~jXHhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_BOOT_OMAPL13xrr}r(jUjjxubaubj)r}r(jUjKjjijj{jjj}r(j]rXoverviewraj]j]j]rUid120raj]ujKjhj]r(j)r}r(jXOverviewrjjjj{jjj}r(j]j]j]j]j]ujKjhj]rjXOverviewrr}r(jjjjubaubj)r}r(jXThe Secondary Bootloader (SBL) for OMAPL137/OMAPL138/C6748 does basic hardware initialization for the board to load and run applications. Processor SDK boot support for each of these SoC is shown belowrjjjj{jjj}r(j]j]j]j]j]ujKjhj]rjXThe Secondary Bootloader (SBL) for OMAPL137/OMAPL138/C6748 does basic hardware initialization for the board to load and run applications. Processor SDK boot support for each of these SoC is shown belowrr}r(jjjjubaubjy )r}r(jUjjjj{jj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujjj]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthK ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthK ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthK ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthK ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthK ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXDevicerjjjj{jjj}r(j]j]j]j]j]ujK j]rjXDevicerr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXCoresrjjjj{jjj}r(j]j]j]j]j]ujK j]rjXCoresrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX Boot Masterrjjjj{jjj}r(j]j]j]j]j]ujK j]rjX Boot Masterrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXSupported Boot modes in SBLrjjjj{jjj}r(j]j]j]j]j]ujK j]rjXSupported Boot modes in SBLrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX HW Platformsrjjjj{jjj}r(j]j]j]j]j]ujK j]rjX HW Platformsrr}r(jjjjubaubajj ubejj ubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXOMAPL137rjjjj{jjj}r(j]j]j]j]j]ujKj]rjXOMAPL137rr}r(jjjjubaubajj ubj )r }r (jUj}r (j]j]j]j]j]ujjj]r j)r }r(jXARM (ARM9) DSP (C674x)rjj jj{jjj}r(j]j]j]j]j]ujKj]rjXARM (ARM9) DSP (C674x)rr}r(jjjj ubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXDSPrjjjj{jjj}r(j]j]j]j]j]ujKj]rjXDSPrr}r (jjjjubaubajj ubj )r!}r"(jUj}r#(j]j]j]j]j]ujjj]r$j)r%}r&(jXSPIr'jj!jj{jjj}r((j]j]j]j]j]ujKj]r)jXSPIr*r+}r,(jj'jj%ubaubajj ubj )r-}r.(jUj}r/(j]j]j]j]j]ujjj]r0j)r1}r2(jX OMAPL137 EVMr3jj-jj{jjj}r4(j]j]j]j]j]ujKj]r5jX OMAPL137 EVMr6r7}r8(jj3jj1ubaubajj ubejj ubj )r9}r:(jUj}r;(j]j]j]j]j]ujjj]r<(j )r=}r>(jUj}r?(j]j]j]j]j]ujj9j]r@j)rA}rB(jXOMAPL138rCjj=jj{jjj}rD(j]j]j]j]j]ujKj]rEjXOMAPL138rFrG}rH(jjCjjAubaubajj ubj )rI}rJ(jUj}rK(j]j]j]j]j]ujj9j]rLj)rM}rN(jXARM (ARM9) DSP (C674x)rOjjIjj{jjj}rP(j]j]j]j]j]ujKj]rQjXARM (ARM9) DSP (C674x)rRrS}rT(jjOjjMubaubajj ubj )rU}rV(jUj}rW(j]j]j]j]j]ujj9j]rXj)rY}rZ(jXARMr[jjUjj{jjj}r\(j]j]j]j]j]ujKj]r]jXARMr^r_}r`(jj[jjYubaubajj ubj )ra}rb(jUj}rc(j]j]j]j]j]ujj9j]rdj)re}rf(jXMMCSDrgjjajj{jjj}rh(j]j]j]j]j]ujKj]rijXMMCSDrjrk}rl(jjgjjeubaubajj ubj )rm}rn(jUj}ro(j]j]j]j]j]ujj9j]rpj)rq}rr(jX OMAPL138 LCDKrsjjmjj{jjj}rt(j]j]j]j]j]ujKj]rujX OMAPL138 LCDKrvrw}rx(jjsjjqubaubajj ubejj ubj )ry}rz(jUj}r{(j]j]j]j]j]ujjj]r|(j )r}}r~(jUj}r(j]j]j]j]j]ujjyj]rj)r}r(jXC6748rjj}jj{jjj}r(j]j]j]j]j]ujKj]rjXC6748rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjyj]rj)r}r(jX DSP (C674x)rjjjj{jjj}r(j]j]j]j]j]ujKj]rjX DSP (C674x)rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjyj]rj)r}r(jXDSPrjjjj{jjj}r(j]j]j]j]j]ujKj]rjXDSPrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjyj]rj)r}r(jXMMCSDrjjjj{jjj}r(j]j]j]j]j]ujKj]rjXMMCSDrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjyj]rj)r}r(jX C6748 LCDKrjjjj{jjj}r(j]j]j]j]j]ujKj]rjX C6748 LCDKrr}r(jjjjubaubajj ubejj ubejj ubejj ubaubeubj)r}r(jUjKjjijj{jjj}r(j]rXbootloader execution sequenceraj]j]j]rUid121raj]ujKjhj]r(j)r}r(jXBootloader Execution Sequencerjjjj{jjj}r(j]j]j]j]j]ujKjhj]rjXBootloader Execution Sequencerr}r(jjjjubaubjt)r}r(jUjjjj{jjwj}r(jyX-j]j]j]j]j]ujKjhj]r(j{)r}r(jXPower On Reset occursrjjjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj{jjj}r(j]j]j]j]j]ujKj]rjXPower On Reset occursrr}r(jjjjubaubaubj{)r}r(jXjROM Bootloader (RBL) executes. It checks for bootmode and attempts to load+run the SBL from that bootmode.jjjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXjROM Bootloader (RBL) executes. It checks for bootmode and attempts to load+run the SBL from that bootmode.rjjjj{jjj}r(j]j]j]j]j]ujKj]rjXjROM Bootloader (RBL) executes. It checks for bootmode and attempts to load+run the SBL from that bootmode.rr}r(jjjjubaubaubj{)r}r(jXYSBL begins execution from internal memory (Shared RAM) - Board Initialization is done by a call to **Board_init()** API. For additional details refer to `Processor SDK Board Support `__. - SBL setup includes configuring Pinmux, enable peripheral clocks, set up PLLs, and configure EMIF for SDRAM/DDR. jjjNjjj}r(j]j]j]j]j]ujNjhj]r(j)r}r(jX6SBL begins execution from internal memory (Shared RAM)rjjjj{jjj}r(j]j]j]j]j]ujKj]rjX6SBL begins execution from internal memory (Shared RAM)rr}r(jjjjubaubjt)r}r(jUj}r(jyX-j]j]j]j]j]ujjj]r(j{)r}r(jXBoard Initialization is done by a call to **Board_init()** API. For additional details refer to `Processor SDK Board Support `__.j}r(j]j]j]j]j]ujjj]rj)r}r(jXBoard Initialization is done by a call to **Board_init()** API. For additional details refer to `Processor SDK Board Support `__.jjjj{jjj}r(j]j]j]j]j]ujK!j]r(jX*Board Initialization is done by a call to rr}r(jX*Board Initialization is done by a call to jjubj)r}r(jX**Board_init()**j}r(j]j]j]j]j]ujjj]rjX Board_init()rr}r(jUjjubajjubjX& API. For additional details refer to rr}r (jX& API. For additional details refer to jjubj)r }r (jX@`Processor SDK Board Support `__j}r (UnameXProcessor SDK Board SupportjXindex_board.html#board-supportj]j]j]j]j]ujjj]r jXProcessor SDK Board Supportrr}r(jUjj ubajjubjX.r}r(jX.jjubeubajjubj{)r}r(jXpSBL setup includes configuring Pinmux, enable peripheral clocks, set up PLLs, and configure EMIF for SDRAM/DDR. j}r(j]j]j]j]j]ujjj]rj)r}r(jXoSBL setup includes configuring Pinmux, enable peripheral clocks, set up PLLs, and configure EMIF for SDRAM/DDR.rjjjj{jjj}r(j]j]j]j]j]ujK$j]rjXoSBL setup includes configuring Pinmux, enable peripheral clocks, set up PLLs, and configure EMIF for SDRAM/DDR.rr}r(jjjjubaubajjubejjwubeubj{)r}r (jXxSBL finishes setup and looks for "app" to execute next. This user-modifiable application shall reside on the boot media.jjjj{jjj}r!(j]j]j]j]j]ujNjhj]r"j)r#}r$(jXxSBL finishes setup and looks for "app" to execute next. This user-modifiable application shall reside on the boot media.r%jjjj{jjj}r&(j]j]j]j]j]ujK'j]r'jXxSBL finishes setup and looks for "app" to execute next. This user-modifiable application shall reside on the boot media.r(r)}r*(jj%jj#ubaubaubj{)r+}r,(jXoOnce located, app will be loaded into memory and execution will be branched to the application's entry address jjjj{jjj}r-(j]j]j]j]j]ujNjhj]r.j)r/}r0(jXnOnce located, app will be loaded into memory and execution will be branched to the application's entry addressr1jj+jj{jjj}r2(j]j]j]j]j]ujK)j]r3jXnOnce located, app will be loaded into memory and execution will be branched to the application's entry addressr4r5}r6(jj1jj/ubaubaubeubeubj)r7}r8(jUjKjjijj{jjj}r9(j]r:Xtools and binary formatsr;aj]j]j]r<Uid122r=aj]ujK-jhj]r>(j)r?}r@(jXTools and Binary FormatsrAjj7jj{jjj}rB(j]j]j]j]j]ujK-jhj]rCjXTools and Binary FormatsrDrE}rF(jjAjj?ubaubj)rG}rH(jUjKjj7jj{jjj}rI(j]rJj aj]j]j]rKUid123rLaj]ujK0jhj]rM(j)rN}rO(jXMaking Bootable SBL image (MLO)rPjjGjj{jjj}rQ(j]j]j]j]j]ujK0jhj]rRjXMaking Bootable SBL image (MLO)rSrT}rU(jjPjjNubaubj)rV}rW(jXRBL loads and runs "MLO", which is a .out executable formatted by TI tools. HexAIS tool should be used to convert the .out into MLO using the below command.rXjjGjj{jjj}rY(j]j]j]j]j]ujK2jhj]rZjXRBL loads and runs "MLO", which is a .out executable formatted by TI tools. HexAIS tool should be used to convert the .out into MLO using the below command.r[r\}r](jjXjjVubaubj)r^}r_(jX Windows Hostr`jjGjj{jjj}ra(j]j]j]j]j]ujK6jhj]rbjX Windows Hostrcrd}re(jj`jj^ubaubj)rf}rg(jX?** -o -ini **rhjjGjj{jjj}ri(j]j]j]j]j]ujK8jhj]rjj)rk}rl(jjhj}rm(j]j]j]j]j]ujjfj]rnjX; -o -ini rorp}rq(jUjjkubajjubaubj)rr}rs(jX Linux HostrtjjGjj{jjj}ru(j]j]j]j]j]ujK:jhj]rvjX Linux Hostrwrx}ry(jjtjjrubaubj)rz}r{(jXJHexAIS executable can be run on Linux PC by using mono tool as shown belowr|jjGjj{jjj}r}(j]j]j]j]j]ujK -o -ini **rjjGjj{jjj}r(j]j]j]j]j]ujK?jhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX@mono -o -ini rr}r(jUjjubajjubaubjt)r}r(jUjjGjj{jjwj}r(jyX-j]j]j]j]j]ujKAjhj]r(j{)r}r(jX^ is HexAIS_OMAP-L137.exe for OMAPL137 and HexAIS_OMAP-L138.exe for OMAPL138/C6748jjjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX^ is HexAIS_OMAP-L137.exe for OMAPL137 and HexAIS_OMAP-L138.exe for OMAPL138/C6748rjjjj{jjj}r(j]j]j]j]j]ujKAj]rjX^ is HexAIS_OMAP-L137.exe for OMAPL137 and HexAIS_OMAP-L138.exe for OMAPL138/C6748rr}r(jjjjubaubaubj{)r}r(jX>‘output file’ is name of the output file. MLO in this caserjjjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj{jjj}r(j]j]j]j]j]ujKCj]rjX>‘output file’ is name of the output file. MLO in this caserr}r(jjjjubaubaubj{)r}r(jX‘ini file’ is configuration file for defining the boot parameters. This file provides option to instruct RBL to take certain actions before loading the MLO into internal memory. Sample ini file is available at **< PDK_INSTALL_DIR >/packages/ti/boot/sbl/soc/** jjjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX‘ini file’ is configuration file for defining the boot parameters. This file provides option to instruct RBL to take certain actions before loading the MLO into internal memory. Sample ini file is available at **< PDK_INSTALL_DIR >/packages/ti/boot/sbl/soc/**jjjj{jjj}r(j]j]j]j]j]ujKDj]r(jX‘ini file’ is configuration file for defining the boot parameters. This file provides option to instruct RBL to take certain actions before loading the MLO into internal memory. Sample ini file is available at rr}r(jX‘ini file’ is configuration file for defining the boot parameters. This file provides option to instruct RBL to take certain actions before loading the MLO into internal memory. Sample ini file is available at jjubj)r}r(jX9**< PDK_INSTALL_DIR >/packages/ti/boot/sbl/soc/**j}r(j]j]j]j]j]ujjj]rjX5< PDK_INSTALL_DIR >/packages/ti/boot/sbl/soc/rr}r(jUjjubajjubeubaubeubj)r}r(jX+ can be omapl137, omapl138 or c6748rjjGjj{jjj}r(j]j]j]j]j]ujKJjhj]rjX+ can be omapl137, omapl138 or c6748rr}r(jjjjubaubjt)r}r(jUjjGjj{jjwj}r(jyX-j]j]j]j]j]ujKLjhj]rj{)r}r(jXR‘input file’ is the input .out file name which needs to be converted into MLO jjjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXQ‘input file’ is the input .out file name which needs to be converted into MLOrjjjj{jjj}r(j]j]j]j]j]ujKLj]rjXQ‘input file’ is the input .out file name which needs to be converted into MLOrr}r(jjjjubaubaubaubj)r}r(jXOMAPL137 HexAIS tool is available at **< PDK_INSTALL_DIR >/packages/ti/boot/sbl/tools/omapl13x_boot_utils/OMAP-L137/GNU/AISUtils**.jjGjj{jjj}r(j]j]j]j]j]ujKOjhj]r(jX%OMAPL137 HexAIS tool is available at rr}r(jX%OMAPL137 HexAIS tool is available at jjubj)r}r(jX]**< PDK_INSTALL_DIR >/packages/ti/boot/sbl/tools/omapl13x_boot_utils/OMAP-L137/GNU/AISUtils**j}r(j]j]j]j]j]ujjj]rjXY< PDK_INSTALL_DIR >/packages/ti/boot/sbl/tools/omapl13x_boot_utils/OMAP-L137/GNU/AISUtilsrr}r(jUjjubajjubjX.r}r(jX.jjubeubj)r}r(jXOMAPL138/C6748 HexAIS tool is available at **< PDK_INSTALL_DIR >/packages/ti/boot/sbl/tools/omapl13x_boot_utils/OMAP-L138/GNU/AISUtils**jjGjj{jjj}r(j]j]j]j]j]ujKRjhj]r(jX+OMAPL138/C6748 HexAIS tool is available at rr}r(jX+OMAPL138/C6748 HexAIS tool is available at jjubj)r}r(jX]**< PDK_INSTALL_DIR >/packages/ti/boot/sbl/tools/omapl13x_boot_utils/OMAP-L138/GNU/AISUtils**j}r(j]j]j]j]j]ujjj]rjXY< PDK_INSTALL_DIR >/packages/ti/boot/sbl/tools/omapl13x_boot_utils/OMAP-L138/GNU/AISUtilsrr}r(jUjjubajjubeubeubj)r}r(jUjKjj7jj{jjj}r(j]rX,making loadable user application image (app)raj]j]j]rUid124raj]ujKVjhj]r(j)r}r(jX,Making Loadable User Application image (app)rjjjj{jjj}r(j]j]j]j]j]ujKVjhj]rjX,Making Loadable User Application image (app)rr}r(jjjjubaubj)r}r(jXFor converting the compiled .out files to a format loadable by TI's Secondary Boot Loader (SBL), you must follow these two steps:rjjjj{jjj}r(j]j]j]j]j]ujKXjhj]rjXFor converting the compiled .out files to a format loadable by TI's Secondary Boot Loader (SBL), you must follow these two steps:rr}r (jjjjubaubj )r }r (jUjjjj{jj j}r (jU.j]j]j]jUj]j]jjujK[jhj]r (j{)r}r(jX***out2rprc.exe [.out file] [rprc output]**rjj jj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj{jjj}r(j]j]j]j]j]ujK[j]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX&out2rprc.exe [.out file] [rprc output]rr}r(jUjjubajjubaubaubj{)r}r(jXF**MulticoreImageGen.exe LE 55 [output name] [rprc output]** jj jj{jjj}r (j]j]j]j]j]ujNjhj]r!j)r"}r#(jXE**MulticoreImageGen.exe LE 55 [output name] [rprc output]**r$jjjj{jjj}r%(j]j]j]j]j]ujK\j]r&j)r'}r((jj$j}r)(j]j]j]j]j]ujj"j]r*jXAMulticoreImageGen.exe LE 55 [output name] [rprc output]r+r,}r-(jUjj'ubajjubaubaubeubj)r.}r/(jXOut2rprc.exe and MulticoreImageGen.exe are tools supplied by TI and can be located in the **/packages/ti/boot/sbl/tools** folder. "rprc output" can be any spare name of your choosing. "output name" can also be any name of your choosing.jjjj{jjj}r0(j]j]j]j]j]ujK^jhj]r1(jXZOut2rprc.exe and MulticoreImageGen.exe are tools supplied by TI and can be located in the r2r3}r4(jXZOut2rprc.exe and MulticoreImageGen.exe are tools supplied by TI and can be located in the jj.ubj)r5}r6(jX0**/packages/ti/boot/sbl/tools**j}r7(j]j]j]j]j]ujj.j]r8jX,/packages/ti/boot/sbl/toolsr9r:}r;(jUjj5ubajjubjXs folder. "rprc output" can be any spare name of your choosing. "output name" can also be any name of your choosing.r<r=}r>(jXs folder. "rprc output" can be any spare name of your choosing. "output name" can also be any name of your choosing.jj.ubeubj)r?}r@(jXThe used in step 2 refers to the Core ID to boot. Use '0' as Core ID for ARM core and '1' for DSP core. Valid values are:. You can input a different value to boot to other cores. Valid values are:rAjjjj{jjj}rB(j]j]j]j]j]ujKcjhj]rCjXThe used in step 2 refers to the Core ID to boot. Use '0' as Core ID for ARM core and '1' for DSP core. Valid values are:. You can input a different value to boot to other cores. Valid values are:rDrE}rF(jjAjj?ubaubjy )rG}rH(jUjjjj{jj j}rI(j]j]j]j]j]ujNjhj]rJj~ )rK}rL(jUj}rM(j]j]j]j]j]UcolsKujjGj]rN(j )rO}rP(jUj}rQ(j]j]j]j]j]UcolwidthK ujjKj]jj ubj )rR}rS(jUj}rT(j]j]j]j]j]UcolwidthKujjKj]jj ubj )rU}rV(jUj}rW(j]j]j]j]j]ujjKj]rXj )rY}rZ(jUj}r[(j]j]j]j]j]ujjUj]r\(j )r]}r^(jUj}r_(j]j]j]j]j]ujjYj]r`j)ra}rb(jXCorercjj]jj{jjj}rd(j]j]j]j]j]ujKhj]rejXCorerfrg}rh(jjcjjaubaubajj ubj )ri}rj(jUj}rk(j]j]j]j]j]ujjYj]rlj)rm}rn(jXValuerojjijj{jjj}rp(j]j]j]j]j]ujKhj]rqjXValuerrrs}rt(jjojjmubaubajj ubejj ubajj ubj )ru}rv(jUj}rw(j]j]j]j]j]ujjKj]rx(j )ry}rz(jUj}r{(j]j]j]j]j]ujjuj]r|(j )r}}r~(jUj}r(j]j]j]j]j]ujjyj]rj)r}r(jXARM Corerjj}jj{jjj}r(j]j]j]j]j]ujKjj]rjXARM Corerr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjyj]rj)r}r(jX0jjjj{jjj}r(j]j]j]j]j]ujKjj]rjX0r}r(jX0jjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjuj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXDSP Corerjjjj{jjj}r(j]j]j]j]j]ujKlj]rjXDSP Corerr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX1jjjj{jjj}r(j]j]j]j]j]ujKlj]rjX1r}r(jX1jjubaubajj ubejj ubejj ubejj ubaubj)r}r(jX>Program entry point of DSP app images on OMAPL138 platform should be 1KByte aligned for loading and executing the DSP images from ARM core. GPIO LLD LED blink example for C674x core can be used as reference for aligning the DSP entry point to run the DSP code from SBL. Other LLD examples does not work from SBL as is.jjjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX>Program entry point of DSP app images on OMAPL138 platform should be 1KByte aligned for loading and executing the DSP images from ARM core. GPIO LLD LED blink example for C674x core can be used as reference for aligning the DSP entry point to run the DSP code from SBL. Other LLD examples does not work from SBL as is.rjjjj{jjj}r(j]j]j]j]j]ujKpj]rjX>Program entry point of DSP app images on OMAPL138 platform should be 1KByte aligned for loading and executing the DSP images from ARM core. GPIO LLD LED blink example for C674x core can be used as reference for aligning the DSP entry point to run the DSP code from SBL. Other LLD examples does not work from SBL as is.rr}r(jjjjubaubaubeubeubj)r}r(jUjKjjijj{jjj}r(j]rX boot modesraj]j]j]rUid125raj]ujKujhj]r(j)r}r(jX Boot Modesrjjjj{jjj}r(j]j]j]j]j]ujKujhj]rjX Boot Modesrr}r(jjjjubaubj)r}r(jX6This release of SBL supports SPI and MMCSD boot modes.rjjjj{jjj}r(j]j]j]j]j]ujKwjhj]rjX6This release of SBL supports SPI and MMCSD boot modes.rr}r(jjjjubaubj)r}r(jUjjjj{jjj}r(j]j]j]j]rU spi-boot-moderaj]rjaujKzjhj]r(j)r}r(jX SPI Boot Moderjjjj{jjj}r(j]j]j]j]j]ujKzjhj]rjX SPI Boot Moderr}r(jjjjubaubj)r}r(jUjjjj{jjj}r(j]j]j]j]rUpreparing-spi-flashraj]rjaujK}jhj]r(j)r}r(jXPreparing SPI Flashrjjjj{jjj}r(j]j]j]j]j]ujK}jhj]rjXPreparing SPI Flashrr}r(jjjjubaubj)r}r(jXMLO and app needs to be flashed into SPI memory so that they can be booted. MLO will reside at offset 0 and app will reside at offset 0x80000. SPI flash memory map:rjjjj{jjj}r(j]j]j]j]j]ujKjhj]rjXMLO and app needs to be flashed into SPI memory so that they can be booted. MLO will reside at offset 0 and app will reside at offset 0x80000. SPI flash memory map:rr}r(jjjjubaubjy )r}r(jUjjjj{jj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujjj]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r }r (jUj}r (j]j]j]j]j]ujjj]r (j )r }r(jUj}r(j]j]j]j]j]ujj j]rj)r}r(jX Offset 0x0rjj jj{jjj}r(j]j]j]j]j]ujKj]rjX Offset 0x0rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj j]rj)r}r(jXMLOrjjjj{jjj}r (j]j]j]j]j]ujKj]r!jXMLOr"r#}r$(jjjjubaubajj ubejj ubj )r%}r&(jUj}r'(j]j]j]j]j]ujjj]r((j )r)}r*(jUj}r+(j]j]j]j]j]ujj%j]r,j)r-}r.(jXOffset 0x80000r/jj)jj{jjj}r0(j]j]j]j]j]ujKj]r1jXOffset 0x80000r2r3}r4(jj/jj-ubaubajj ubj )r5}r6(jUj}r7(j]j]j]j]j]ujj%j]r8j)r9}r:(jXappr;jj5jj{jjj}r<(j]j]j]j]j]ujKj]r=jXappr>r?}r@(jj;jj9ubaubajj ubejj ubejj ubejj ubaubj)rA}rB(jXHThe images can be flashed into SPI flash by following steps given below:rCjjjj{jjj}rD(j]j]j]j]j]ujKjhj]rEjXHThe images can be flashed into SPI flash by following steps given below:rFrG}rH(jjCjjAubaubj )rI}rJ(jUjjjj{jj j}rK(jU.j]j]j]jUj]j]jjujKjhj]rL(j{)rM}rN(jX!Copy MLO and app to SPI flash writer binary folder - **/packages/ti/boot/sbl/tools/flashWriter/spi/bin/evmOMAPL137**. Make sure config file also present in the SPI flash writer binary folder. - MLO is the SBL formatted by the aforementioned tools. A pre-built MLO can be found at: **/packages/ti/boot/sbl/binary/evmOMAPL137/spi/bin** - app is the target application to be booted and also formatted by the aforementioned tools. (Note that the tools for making the bootable MLO and the loadable app are different). - config helps specify the memory map. The default config file can be found at: **/packages/ti/boot/sbl/tools/flashWriter/spi/bin/evmOMAPL137**. This config file may be altered to custom user settings if needed. jjIjNjjj}rO(j]j]j]j]j]ujNjhj]rP(j)rQ}rR(jXCopy MLO and app to SPI flash writer binary folder - **/packages/ti/boot/sbl/tools/flashWriter/spi/bin/evmOMAPL137**. Make sure config file also present in the SPI flash writer binary folder.jjMjj{jjj}rS(j]j]j]j]j]ujKj]rT(jX5Copy MLO and app to SPI flash writer binary folder - rUrV}rW(jX5Copy MLO and app to SPI flash writer binary folder - jjQubj)rX}rY(jXP**/packages/ti/boot/sbl/tools/flashWriter/spi/bin/evmOMAPL137**j}rZ(j]j]j]j]j]ujjQj]r[jXL/packages/ti/boot/sbl/tools/flashWriter/spi/bin/evmOMAPL137r\r]}r^(jUjjXubajjubjXK. Make sure config file also present in the SPI flash writer binary folder.r_r`}ra(jXK. Make sure config file also present in the SPI flash writer binary folder.jjQubeubjt)rb}rc(jUj}rd(jyX-j]j]j]j]j]ujjMj]re(j{)rf}rg(jXMLO is the SBL formatted by the aforementioned tools. A pre-built MLO can be found at: **/packages/ti/boot/sbl/binary/evmOMAPL137/spi/bin**j}rh(j]j]j]j]j]ujjbj]rij)rj}rk(jXMLO is the SBL formatted by the aforementioned tools. A pre-built MLO can be found at: **/packages/ti/boot/sbl/binary/evmOMAPL137/spi/bin**jjfjj{jjj}rl(j]j]j]j]j]ujKj]rm(jXWMLO is the SBL formatted by the aforementioned tools. A pre-built MLO can be found at: rnro}rp(jXWMLO is the SBL formatted by the aforementioned tools. A pre-built MLO can be found at: jjjubj)rq}rr(jXE**/packages/ti/boot/sbl/binary/evmOMAPL137/spi/bin**j}rs(j]j]j]j]j]ujjjj]rtjXA/packages/ti/boot/sbl/binary/evmOMAPL137/spi/binrurv}rw(jUjjqubajjubeubajjubj{)rx}ry(jXapp is the target application to be booted and also formatted by the aforementioned tools. (Note that the tools for making the bootable MLO and the loadable app are different).j}rz(j]j]j]j]j]ujjbj]r{j)r|}r}(jXapp is the target application to be booted and also formatted by the aforementioned tools. (Note that the tools for making the bootable MLO and the loadable app are different).r~jjxjj{jjj}r(j]j]j]j]j]ujKj]rjXapp is the target application to be booted and also formatted by the aforementioned tools. (Note that the tools for making the bootable MLO and the loadable app are different).rr}r(jj~jj|ubaubajjubj{)r}r(jXconfig helps specify the memory map. The default config file can be found at: **/packages/ti/boot/sbl/tools/flashWriter/spi/bin/evmOMAPL137**. This config file may be altered to custom user settings if needed. j}r(j]j]j]j]j]ujjbj]rj)r}r(jXconfig helps specify the memory map. The default config file can be found at: **/packages/ti/boot/sbl/tools/flashWriter/spi/bin/evmOMAPL137**. This config file may be altered to custom user settings if needed.jjjj{jjj}r(j]j]j]j]j]ujKj]r(jXNconfig helps specify the memory map. The default config file can be found at: rr}r(jXNconfig helps specify the memory map. The default config file can be found at: jjubj)r}r(jXP**/packages/ti/boot/sbl/tools/flashWriter/spi/bin/evmOMAPL137**j}r(j]j]j]j]j]ujjj]rjXL/packages/ti/boot/sbl/tools/flashWriter/spi/bin/evmOMAPL137rr}r(jUjjubajjubjXD. This config file may be altered to custom user settings if needed.rr}r(jXD. This config file may be altered to custom user settings if needed.jjubeubajjubejjwubeubj{)r}r(jXConnect the DB9 port of the EVM to host PC. Open serial communication applications like TeraTerm, MiniCom, etc and configure for ‘115200 8N1’.jjIjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXConnect the DB9 port of the EVM to host PC. Open serial communication applications like TeraTerm, MiniCom, etc and configure for ‘115200 8N1’.rjjjj{jjj}r(j]j]j]j]j]ujKj]rjXConnect the DB9 port of the EVM to host PC. Open serial communication applications like TeraTerm, MiniCom, etc and configure for ‘115200 8N1’.rr}r(jjjjubaubaubj{)r}r(jXConnect to the board with CCS. Launch target configuration and connect to the DSP C674x core. GEL file will run on-connect and do basic board-level initializationjjIjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXConnect to the board with CCS. Launch target configuration and connect to the DSP C674x core. GEL file will run on-connect and do basic board-level initializationrjjjj{jjj}r(j]j]j]j]j]ujKj]rjXConnect to the board with CCS. Launch target configuration and connect to the DSP C674x core. GEL file will run on-connect and do basic board-level initializationrr}r(jjjjubaubaubj{)r}r(jXLoad the flash writer, spi_flash_writer.out, to the connected core - A pre-built spi_flash_writer.out can be found at: **/packages/ti/boot/sbl/tools/flashWriter/spi/bin/evmOMAPL137** jjIjNjjj}r(j]j]j]j]j]ujNjhj]r(j)r}r(jXBLoad the flash writer, spi_flash_writer.out, to the connected corerjjjj{jjj}r(j]j]j]j]j]ujKj]rjXBLoad the flash writer, spi_flash_writer.out, to the connected corerr}r(jjjjubaubjt)r}r(jUj}r(jyX-j]j]j]j]j]ujjj]rj{)r}r(jXA pre-built spi_flash_writer.out can be found at: **/packages/ti/boot/sbl/tools/flashWriter/spi/bin/evmOMAPL137** j}r(j]j]j]j]j]ujjj]rj)r}r(jXA pre-built spi_flash_writer.out can be found at: **/packages/ti/boot/sbl/tools/flashWriter/spi/bin/evmOMAPL137**jjjj{jjj}r(j]j]j]j]j]ujKj]r(jX2A pre-built spi_flash_writer.out can be found at: rr}r(jX2A pre-built spi_flash_writer.out can be found at: jjubj)r}r(jXP**/packages/ti/boot/sbl/tools/flashWriter/spi/bin/evmOMAPL137**j}r(j]j]j]j]j]ujjj]rjXL/packages/ti/boot/sbl/tools/flashWriter/spi/bin/evmOMAPL137rr}r(jUjjubajjubeubajjubajjwubeubj{)r}r(jXaRun the SPI flash writer application. You will see the following logs on the EVM's UART console: jjIjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX`Run the SPI flash writer application. You will see the following logs on the EVM's UART console:rjjjj{jjj}r(j]j]j]j]j]ujKj]rjX`Run the SPI flash writer application. You will see the following logs on the EVM's UART console:rr}r(jjjjubaubaubeubj)r}r(jX1 *** PDK SPI Flash Writer *** Opening SPI handle... SPI handle opened! Parsing config file and flashing content to SPI NOR... Parsed config line, received parameters: filename = MLO, address = 0x0 Size of MLO is 0xc81c Loading binary to memory ... Finished loading binary to memory! Flashed MLO to offset 0x0! Read flash memory at 0x0, checking flashed content... Verified flash data equal expected data! Parsed config line, received parameters: filename = app, address = 0x80000 Size of app is 0x16144 Loading binary to memory ... Finished loading binary to memory! Flashed app to offset 0x80000! Read flash memory at 0x80000, checking flashed content... Verified flash data equal expected data! Successfully flashed memory content!jjjj{jjj}r(j@jAj]j]j]j]j]ujM/jhj]rjX1 *** PDK SPI Flash Writer *** Opening SPI handle... SPI handle opened! Parsing config file and flashing content to SPI NOR... Parsed config line, received parameters: filename = MLO, address = 0x0 Size of MLO is 0xc81c Loading binary to memory ... Finished loading binary to memory! Flashed MLO to offset 0x0! Read flash memory at 0x0, checking flashed content... Verified flash data equal expected data! Parsed config line, received parameters: filename = app, address = 0x80000 Size of app is 0x16144 Loading binary to memory ... Finished loading binary to memory! Flashed app to offset 0x80000! Read flash memory at 0x80000, checking flashed content... Verified flash data equal expected data! Successfully flashed memory content!rr}r(jUjjubaubj)r}r(jXThis application will flash the image at required offset without taking into consideration any overwriting to previously flashed image.jjjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXThis application will flash the image at required offset without taking into consideration any overwriting to previously flashed image.rjjjj{jjj}r(j]j]j]j]j]ujKj]rjXThis application will flash the image at required offset without taking into consideration any overwriting to previously flashed image.rr}r(jjjjubaubaubeubj)r}r(jUjjjj{jjj}r(j]j]j]j]rUbooting-via-spiraj]rhaujKjhj]r(j)r}r(jXBooting via SPIrjjjj{jjj}r(j]j]j]j]j]ujKjhj]rjXBooting via SPIrr}r(jjjjubaubj )r}r(jUjjjj{jj j}r(jU.j]j]j]jUj]j]jjujKjhj]r(j{)r}r(jXSet the OMAPL137 EVM to SPI bootmode by configuring the SW2 DIP switches 1-4 to 'OFF ON OFF ON'. Other switch positions on SW2 are don’t care for SPI boot.jjjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r }r (jXSet the OMAPL137 EVM to SPI bootmode by configuring the SW2 DIP switches 1-4 to 'OFF ON OFF ON'. Other switch positions on SW2 are don’t care for SPI boot.r jjjj{jjj}r (j]j]j]j]j]ujKj]r jXSet the OMAPL137 EVM to SPI bootmode by configuring the SW2 DIP switches 1-4 to 'OFF ON OFF ON'. Other switch positions on SW2 are don’t care for SPI boot.rr}r(jj jj ubaubaubj{)r}r(jXConnect the DB9 port of the EVM to host PC. Open serial communication applications like TeraTerm, MiniCom, etc and configure for ‘115200 8N1’jjjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXConnect the DB9 port of the EVM to host PC. Open serial communication applications like TeraTerm, MiniCom, etc and configure for ‘115200 8N1’rjjjj{jjj}r(j]j]j]j]j]ujKj]rjXConnect the DB9 port of the EVM to host PC. Open serial communication applications like TeraTerm, MiniCom, etc and configure for ‘115200 8N1’rr}r(jjjjubaubaubj{)r}r(jXPower on the board jjjj{jjj}r(j]j]j]j]j]ujNjhj]r j)r!}r"(jXPower on the boardr#jjjj{jjj}r$(j]j]j]j]j]ujKj]r%jXPower on the boardr&r'}r((jj#jj!ubaubaubeubj)r)}r*(jXWBelow is an example of OMAPL137 SBL successfully booting the GPIO LED blink applicationr+jjjj{jjj}r,(j]j]j]j]j]ujKjhj]r-jXWBelow is an example of OMAPL137 SBL successfully booting the GPIO LED blink applicationr.r/}r0(jj+jj)ubaubjR)r1}r2(jX/.. Image:: ../images/Omapl137_boot_example.jpg jjjj{jjZj}r3(UuriX(rtos/../images/Omapl137_boot_example.jpgr4j]j]j]j]jX}r5U*j4sj]ujKjhj]ubjc)r6}r7(jUjjjj{jjfj}r8(j]j]j]j]j]ujKjhj]r9ji)r:}r;(jUjlKjj6jj{jjj}r<(j]j]j]j]j]ujKjhj]ubaubeubeubj)r=}r>(jUjKjjjj{jjj}r?(j]r@jaj]j]j]rAUid126rBaj]ujKjhj]rC(j)rD}rE(jXMMCSD Boot ModerFjj=jj{jjj}rG(j]j]j]j]j]ujKjhj]rHjXMMCSD Boot ModerIrJ}rK(jjFjjDubaubj)rL}rM(jXOMAPL138/C6848 RBL does not support reading the boot images as files from SD card. Secondary Boot loader image should be written to SD card as raw data. Special formatting is needed for SD card to create un-formatted area at the beginning of the card to store SBL.rNjj=jj{jjj}rO(j]j]j]j]j]ujKjhj]rPjXOMAPL138/C6848 RBL does not support reading the boot images as files from SD card. Secondary Boot loader image should be written to SD card as raw data. Special formatting is needed for SD card to create un-formatted area at the beginning of the card to store SBL.rQrR}rS(jjNjjLubaubj)rT}rU(jUjj=jj{jjj}rV(j]j]j]j]rWUformatting-the-sd-cardrXaj]rYjaujKjhj]rZ(j)r[}r\(jXFormatting the SD Cardr]jjTjj{jjj}r^(j]j]j]j]j]ujKjhj]r_jXFormatting the SD Cardr`ra}rb(jj]jj[ubaubj)rc}rd(jXSD card for booting OMAPL138/C6748 needs to be formatted from Linux PC due to un-formatted area requirement. Formatting the SD card from Windows PC is not supported in this release.rejjTjj{jjj}rf(j]j]j]j]j]ujKjhj]rgjXSD card for booting OMAPL138/C6748 needs to be formatted from Linux PC due to un-formatted area requirement. Formatting the SD card from Windows PC is not supported in this release.rhri}rj(jjejjcubaubj)rk}rl(jXKConnect the SD card to Linux PC and use below command to format the SD cardrmjjTjj{jjj}rn(j]j]j]j]j]ujKjhj]rojXKConnect the SD card to Linux PC and use below command to format the SD cardrprq}rr(jjmjjkubaubj)rs}rt(jX2**sudo sh create-sdcard-omapl13x.sh **rujjTjj{jjj}rv(j]j]j]j]j]ujKjhj]rwj)rx}ry(jjuj}rz(j]j]j]j]j]ujjsj]r{jX.sudo sh create-sdcard-omapl13x.sh r|r}}r~(jUjjxubajjubaubjt)r}r(jUjjTjj{jjwj}r(jyX-j]j]j]j]j]ujKjhj]r(j{)r}r(jX is name of the drive on which SD card is mounted. Be cautious while selecting the drive name. Running the script with system drive name will corrupt the file system.jjjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX is name of the drive on which SD card is mounted. Be cautious while selecting the drive name. Running the script with system drive name will corrupt the file system.rjjjj{jjj}r(j]j]j]j]j]ujKj]rjX is name of the drive on which SD card is mounted. Be cautious while selecting the drive name. Running the script with system drive name will corrupt the file system.rr}r(jjjjubaubaubj{)r}r(jXzcreate-sdcard-omapl13x.sh script is available at **/packages/ti/boot/sbl/tools/omapl13x_sd_card_format** jjjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXycreate-sdcard-omapl13x.sh script is available at **/packages/ti/boot/sbl/tools/omapl13x_sd_card_format**jjjj{jjj}r(j]j]j]j]j]ujKj]r(jX1create-sdcard-omapl13x.sh script is available at rr}r(jX1create-sdcard-omapl13x.sh script is available at jjubj)r}r(jXH**/packages/ti/boot/sbl/tools/omapl13x_sd_card_format**j}r(j]j]j]j]j]ujjj]rjXD/packages/ti/boot/sbl/tools/omapl13x_sd_card_formatrr}r(jUjjubajjubeubaubeubeubj)r}r(jUjKjj=jj{jjj}r(j]rXpreparing the sd cardraj]j]j]rUid127raj]ujKjhj]r(j)r}r(jXPreparing the SD Cardrjjjj{jjj}r(j]j]j]j]j]ujKjhj]rjXPreparing the SD Cardrr}r(jjjjubaubj)r}r(jXzFor both OMAPL138 and C6748, MLO needs to be flashed onto SD card un-formatted area and app should be copied onto SD card.rjjjj{jjj}r(j]j]j]j]j]ujKjhj]rjXzFor both OMAPL138 and C6748, MLO needs to be flashed onto SD card un-formatted area and app should be copied onto SD card.rr}r(jjjjubaubj)r}r(jXQMLO can be flashed into SD card un-formatted area by following steps given below:rjjjj{jjj}r(j]j]j]j]j]ujKjhj]rjXQMLO can be flashed into SD card un-formatted area by following steps given below:rr}r(jjjjubaubj )r}r(jUjjjj{jj j}r(jU.j]j]j]jUj]j]jjujKjhj]r(j{)r}r(jXBuild the MMCSD flash writer using below commands - cd /packages/ti/boot/sbl - gmake mmcsd_flashwriter SOC=OMAPL138 BOARD=lcdkOMAPL138 BOOTMODE=mmcsd jjjNjjj}r(j]j]j]j]j]ujNjhj]r(j)r}r(jX1Build the MMCSD flash writer using below commandsrjjjj{jjj}r(j]j]j]j]j]ujKj]rjX1Build the MMCSD flash writer using below commandsrr}r(jjjjubaubjt)r}r(jUj}r(jyX-j]j]j]j]j]ujjj]r(j{)r}r(jX)cd /packages/ti/boot/sblrj}r(j]j]j]j]j]ujjj]rj)r}r(jjjjjj{jjj}r(j]j]j]j]j]ujKj]rjX)cd /packages/ti/boot/sblrr}r(jjjjubaubajjubj{)r}r(jXGgmake mmcsd_flashwriter SOC=OMAPL138 BOARD=lcdkOMAPL138 BOOTMODE=mmcsd j}r(j]j]j]j]j]ujjj]rj)r}r(jXFgmake mmcsd_flashwriter SOC=OMAPL138 BOARD=lcdkOMAPL138 BOOTMODE=mmcsdrjjjj{jjj}r(j]j]j]j]j]ujKj]rjXFgmake mmcsd_flashwriter SOC=OMAPL138 BOARD=lcdkOMAPL138 BOOTMODE=mmcsdrr}r(jjjjubaubajjubejjwubeubj{)r}r(jXFCopy 'app' to SD card and insert the card into MMCSD slot of the boardjjjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXFCopy 'app' to SD card and insert the card into MMCSD slot of the boardrjjjj{jjj}r(j]j]j]j]j]ujKj]rjXFCopy 'app' to SD card and insert the card into MMCSD slot of the boardrr}r(jjjjubaubaubj{)r}r(jX&Copy MLO to MMCSD flash writer binary folder - **/packages/ti/boot/sbl/tools/flashWriter/mmcsd/bin/lcdkOMAPL138**. Make sure config file also present in the MMCSD flash writer binary folder. - MLO is the SBL formatted by the aforementioned tools. A pre-built MLO can be found at: **/packages/ti/boot/sbl/binary/lcdkOMAPL138/mmcsd/bin** - app is the target application to be booted and also formatted by the aforementioned tools. (Note that the tools for making the bootable MLO and the loadable app are different). - config helps specify the memory map. The default config file can be found at: **/packages/ti/boot/sbl/tools/flashWriter/mmcsd/bin/lcdkOMAPL138**. This config file may be altered to custom user settings if needed. jjjNjjj}r(j]j]j]j]j]ujNjhj]r(j)r}r(jXCopy MLO to MMCSD flash writer binary folder - **/packages/ti/boot/sbl/tools/flashWriter/mmcsd/bin/lcdkOMAPL138**. Make sure config file also present in the MMCSD flash writer binary folder.jjjj{jjj}r(j]j]j]j]j]ujMj]r(jX/Copy MLO to MMCSD flash writer binary folder - rr}r(jX/Copy MLO to MMCSD flash writer binary folder - jjubj)r}r(jXS**/packages/ti/boot/sbl/tools/flashWriter/mmcsd/bin/lcdkOMAPL138**j}r(j]j]j]j]j]ujjj]rjXO/packages/ti/boot/sbl/tools/flashWriter/mmcsd/bin/lcdkOMAPL138rr }r (jUjjubajjubjXM. Make sure config file also present in the MMCSD flash writer binary folder.r r }r (jXM. Make sure config file also present in the MMCSD flash writer binary folder.jjubeubjt)r}r(jUj}r(jyX-j]j]j]j]j]ujjj]r(j{)r}r(jXMLO is the SBL formatted by the aforementioned tools. A pre-built MLO can be found at: **/packages/ti/boot/sbl/binary/lcdkOMAPL138/mmcsd/bin**j}r(j]j]j]j]j]ujjj]rj)r}r(jXMLO is the SBL formatted by the aforementioned tools. A pre-built MLO can be found at: **/packages/ti/boot/sbl/binary/lcdkOMAPL138/mmcsd/bin**jjjj{jjj}r(j]j]j]j]j]ujMj]r(jXWMLO is the SBL formatted by the aforementioned tools. A pre-built MLO can be found at: rr}r(jXWMLO is the SBL formatted by the aforementioned tools. A pre-built MLO can be found at: jjubj)r}r(jXH**/packages/ti/boot/sbl/binary/lcdkOMAPL138/mmcsd/bin**j}r(j]j]j]j]j]ujjj]r jXD/packages/ti/boot/sbl/binary/lcdkOMAPL138/mmcsd/binr!r"}r#(jUjjubajjubeubajjubj{)r$}r%(jXapp is the target application to be booted and also formatted by the aforementioned tools. (Note that the tools for making the bootable MLO and the loadable app are different).j}r&(j]j]j]j]j]ujjj]r'j)r(}r)(jXapp is the target application to be booted and also formatted by the aforementioned tools. (Note that the tools for making the bootable MLO and the loadable app are different).r*jj$jj{jjj}r+(j]j]j]j]j]ujMj]r,jXapp is the target application to be booted and also formatted by the aforementioned tools. (Note that the tools for making the bootable MLO and the loadable app are different).r-r.}r/(jj*jj(ubaubajjubj{)r0}r1(jXconfig helps specify the memory map. The default config file can be found at: **/packages/ti/boot/sbl/tools/flashWriter/mmcsd/bin/lcdkOMAPL138**. This config file may be altered to custom user settings if needed. j}r2(j]j]j]j]j]ujjj]r3j)r4}r5(jXconfig helps specify the memory map. The default config file can be found at: **/packages/ti/boot/sbl/tools/flashWriter/mmcsd/bin/lcdkOMAPL138**. This config file may be altered to custom user settings if needed.jj0jj{jjj}r6(j]j]j]j]j]ujM j]r7(jXNconfig helps specify the memory map. The default config file can be found at: r8r9}r:(jXNconfig helps specify the memory map. The default config file can be found at: jj4ubj)r;}r<(jXS**/packages/ti/boot/sbl/tools/flashWriter/mmcsd/bin/lcdkOMAPL138**j}r=(j]j]j]j]j]ujj4j]r>jXO/packages/ti/boot/sbl/tools/flashWriter/mmcsd/bin/lcdkOMAPL138r?r@}rA(jUjj;ubajjubjXD. This config file may be altered to custom user settings if needed.rBrC}rD(jXD. This config file may be altered to custom user settings if needed.jj4ubeubajjubejjwubeubj{)rE}rF(jXConnect the USB serial port of the EVM to host PC. Open serial communication applications like TeraTerm, MiniCom, etc and configure for ‘115200 8N1’.jjjj{jjj}rG(j]j]j]j]j]ujNjhj]rHj)rI}rJ(jXConnect the USB serial port of the EVM to host PC. Open serial communication applications like TeraTerm, MiniCom, etc and configure for ‘115200 8N1’.rKjjEjj{jjj}rL(j]j]j]j]j]ujMj]rMjXConnect the USB serial port of the EVM to host PC. Open serial communication applications like TeraTerm, MiniCom, etc and configure for ‘115200 8N1’.rNrO}rP(jjKjjIubaubaubj{)rQ}rR(jXConnect to the board with CCS. Launch target configuration, connect to ARM core first (not needed for C6748) and then connect to the DSP C674x core. GEL file will run on-connect and do basic board-level initializationjjjj{jjj}rS(j]j]j]j]j]ujNjhj]rTj)rU}rV(jXConnect to the board with CCS. Launch target configuration, connect to ARM core first (not needed for C6748) and then connect to the DSP C674x core. GEL file will run on-connect and do basic board-level initializationrWjjQjj{jjj}rX(j]j]j]j]j]ujMj]rYjXConnect to the board with CCS. Launch target configuration, connect to ARM core first (not needed for C6748) and then connect to the DSP C674x core. GEL file will run on-connect and do basic board-level initializationrZr[}r\(jjWjjUubaubaubj{)r]}r^(jXLoad the flash writer, mmcsd_flash_writer.out, to the connected core - mmcsd_flash_writer.out can be found at: **/packages/ti/boot/sbl/tools/flashWriter/mmcsd/bin/lcdkOMAPL138** jjjNjjj}r_(j]j]j]j]j]ujNjhj]r`(j)ra}rb(jXDLoad the flash writer, mmcsd_flash_writer.out, to the connected corercjj]jj{jjj}rd(j]j]j]j]j]ujMj]rejXDLoad the flash writer, mmcsd_flash_writer.out, to the connected corerfrg}rh(jjcjjaubaubjt)ri}rj(jUj}rk(jyX-j]j]j]j]j]ujj]j]rlj{)rm}rn(jX|mmcsd_flash_writer.out can be found at: **/packages/ti/boot/sbl/tools/flashWriter/mmcsd/bin/lcdkOMAPL138** j}ro(j]j]j]j]j]ujjij]rpj)rq}rr(jX{mmcsd_flash_writer.out can be found at: **/packages/ti/boot/sbl/tools/flashWriter/mmcsd/bin/lcdkOMAPL138**jjmjj{jjj}rs(j]j]j]j]j]ujMj]rt(jX(mmcsd_flash_writer.out can be found at: rurv}rw(jX(mmcsd_flash_writer.out can be found at: jjqubj)rx}ry(jXS**/packages/ti/boot/sbl/tools/flashWriter/mmcsd/bin/lcdkOMAPL138**j}rz(j]j]j]j]j]ujjqj]r{jXO/packages/ti/boot/sbl/tools/flashWriter/mmcsd/bin/lcdkOMAPL138r|r}}r~(jUjjxubajjubeubajjubajjwubeubj{)r}r(jXcRun the MMCSD flash writer application. You will see the following logs on the EVM's UART console: jjjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXbRun the MMCSD flash writer application. You will see the following logs on the EVM's UART console:rjjjj{jjj}r(j]j]j]j]j]ujMj]rjXbRun the MMCSD flash writer application. You will see the following logs on the EVM's UART console:rr}r(jjjjubaubaubeubj)r}r(jXOpening MMCSD handle... MMCSD handle opened! Parsing config file and flashing content to MMCSD... Parsed config line, received parameters: filename = MLO, address = 0x200 Size of MLO is 0xb9b8 Loading binary to memory ... Finished loading binary to memory! Flashed MLO to offset 0x200! Read flash memory at 0x200, checking flashed content... Verified flash data equal expected data! Successfully flashed memory content!jjjj{jjj}r(j@jAj]j]j]j]j]ujM}/jhj]rjXOpening MMCSD handle... MMCSD handle opened! Parsing config file and flashing content to MMCSD... Parsed config line, received parameters: filename = MLO, address = 0x200 Size of MLO is 0xb9b8 Loading binary to memory ... Finished loading binary to memory! Flashed MLO to offset 0x200! Read flash memory at 0x200, checking flashed content... Verified flash data equal expected data! Successfully flashed memory content!rr}r(jUjjubaubj)r}r(jXProcedure to flash the MLO described above is applicable to C6748 also. Use C6748 for OMAPL138 and lcdkC6748 for lcdkOMAPL138 in all the paths mentioned above.rjjjj{jjj}r(j]j]j]j]j]ujM-jhj]rjXProcedure to flash the MLO described above is applicable to C6748 also. Use C6748 for OMAPL138 and lcdkC6748 for lcdkOMAPL138 in all the paths mentioned above.rr}r(jjjjubaubj)r}r(jXBMLO offset in config file is set to 200 by default which indicates that MLO will be written to second sector of the SD card. MLO offset can be any non- zero value which is multiple of 512 and should be within first 2Mbytes of SD card memory. DO NOT set the MLO offset to '0' which will corrupt the file system on the card.jjjj{jjj}r(j@jAj]j]j]j]j]ujM/jhj]rjXBMLO offset in config file is set to 200 by default which indicates that MLO will be written to second sector of the SD card. MLO offset can be any non- zero value which is multiple of 512 and should be within first 2Mbytes of SD card memory. DO NOT set the MLO offset to '0' which will corrupt the file system on the card.rr}r(jUjjubaubj)r}r(jXThis application will flash the image at required offset without taking into consideration any overwriting to previously flashed image.jjjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXThis application will flash the image at required offset without taking into consideration any overwriting to previously flashed image.rjjjj{jjj}r(j]j]j]j]j]ujM8j]rjXThis application will flash the image at required offset without taking into consideration any overwriting to previously flashed image.rr}r(jjjjubaubaubjc)r}r(jUjjjj{jjfj}r(j]j]j]j]j]ujM;jhj]rji)r}r(jUjlKjjjj{jjj}r(j]j]j]j]j]ujKjhj]ubaubeubj)r}r(jUjj=jj{jjj}r(j]j]j]j]rUbooting-via-mmcsdraj]rhhaujM>jhj]r(j)r}r(jXBooting via MMCSDrjjjj{jjj}r(j]j]j]j]j]ujM>jhj]rjXBooting via MMCSDrr}r(jjjjubaubj )r}r(jUjjjj{jj j}r(jU.j]j]j]jUj]j]jjujM@jhj]r(j{)r}r(jXSet the OMAPL138/C6748 LCDK to MMCSD bootmode by configuring the SW1 DIP switches 1-4 to 'OFF OFF OFF ON'. Other switch positions on SW1 are don’t care for MMCSD boot.jjjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXSet the OMAPL138/C6748 LCDK to MMCSD bootmode by configuring the SW1 DIP switches 1-4 to 'OFF OFF OFF ON'. Other switch positions on SW1 are don’t care for MMCSD boot.rjjjj{jjj}r(j]j]j]j]j]ujM@j]rjXSet the OMAPL138/C6748 LCDK to MMCSD bootmode by configuring the SW1 DIP switches 1-4 to 'OFF OFF OFF ON'. Other switch positions on SW1 are don’t care for MMCSD boot.rr}r(jjjjubaubaubj{)r}r(jXConnect the USB serial port of the EVM to host PC. Open serial communication applications like TeraTerm, MiniCom, etc and configure for ‘115200 8N1’jjjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXConnect the USB serial port of the EVM to host PC. Open serial communication applications like TeraTerm, MiniCom, etc and configure for ‘115200 8N1’rjjjj{jjj}r(j]j]j]j]j]ujMCj]rjXConnect the USB serial port of the EVM to host PC. Open serial communication applications like TeraTerm, MiniCom, etc and configure for ‘115200 8N1’rr}r(jjjjubaubaubj{)r}r(jXPower on the board jjjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXPower on the boardrjjjj{jjj}r(j]j]j]j]j]ujMFj]rjXPower on the boardrr}r(jjjjubaubaubeubj)r}r(jXWBelow is an example of OMAPL138 SBL successfully booting the GPIO LED blink applicationrjjjj{jjj}r(j]j]j]j]j]ujMHjhj]rjXWBelow is an example of OMAPL138 SBL successfully booting the GPIO LED blink applicationrr}r(jjjjubaubjR)r}r(jX/.. Image:: ../images/Omapl138_boot_example.png jjjj{jjZj}r(UuriX(rtos/../images/Omapl138_boot_example.pngrj]j]j]j]jX}rU*jsj]ujMLjhj]ubjc)r}r(jUjjjj{jjfj}r(j]j]j]j]j]ujMMjhj]rji)r}r(jUjlKjjjj{jjj}r(j]j]j]j]j]ujKjhj]ubaubeubeubeubj)r}r(jUjKjjijj{jjj}r(j]rj-aj]j]j]rUid128raj]ujMPjhj]r(j)r}r(jX Memory Usagerjjjj{jjj}r (j]j]j]j]j]ujMPjhj]r jX Memory Usager r }r (jjjjubaubj)r}r(jXBSBL uses 0x20000 bytes from shared RAM (0x80000000 to 0x8001FFFF).rjjjj{jjj}r(j]j]j]j]j]ujMRjhj]rjXBSBL uses 0x20000 bytes from shared RAM (0x80000000 to 0x8001FFFF).rr}r(jjjjubaubjc)r}r(jUjjjj{jjfj}r(j]j]j]j]j]ujMTjhj]rji)r}r(jUjlKjjjj{jjj}r(j]j]j]j]j]ujKjhj]ubaubj)r}r(jXapp should not have loadable sections residing in SBL memory region to prevent overwriting SBL during load time. It is, however, free to use SBL memory after it is loaded and running.jjjj{jjj}r(j]j]j]j]j]ujNjhj]r j)r!}r"(jXapp should not have loadable sections residing in SBL memory region to prevent overwriting SBL during load time. It is, however, free to use SBL memory after it is loaded and running.r#jjjj{jjj}r$(j]j]j]j]j]ujMWj]r%jXapp should not have loadable sections residing in SBL memory region to prevent overwriting SBL during load time. It is, however, free to use SBL memory after it is loaded and running.r&r'}r((jj#jj!ubaubaubjc)r)}r*(jUjjjj{jjfj}r+(j]j]j]j]j]ujM[jhj]r,ji)r-}r.(jUjlKjj)jj{jjj}r/(j]j]j]j]j]ujKjhj]ubaubeubj)r0}r1(jUjjijj{jjj}r2(j]j]j]j]r3Uadditional-detailsr4aj]r5haujM^jhj]r6(j)r7}r8(jXAdditional Detailsr9jj0jj{jjj}r:(j]j]j]j]j]ujM^jhj]r;jXAdditional Detailsr<r=}r>(jj9jj7ubaubj)r?}r@(jXCUse below commands to clean and build the SBL and associated tools.rAjj0jj{jjj}rB(j]j]j]j]j]ujM`jhj]rCjXCUse below commands to clean and build the SBL and associated tools.rDrE}rF(jjAjj?ubaubj)rG}rH(jUjj0jj{jjj}rI(j]j]j]j]rJU initial-stepsrKaj]rLhaujMcjhj]rM(j)rN}rO(jX Initial StepsrPjjGjj{jjj}rQ(j]j]j]j]j]ujMcjhj]rRjX Initial StepsrSrT}rU(jjPjjNubaubj)rV}rW(jX<Setup the environment variables to configure the build toolsrXjjGjj{jjj}rY(j]j]j]j]j]ujMejhj]rZjX<Setup the environment variables to configure the build toolsr[r\}r](jjXjjVubaubj)r^}r_(jXcd /packagesr`jjGjj{jjj}ra(j]j]j]j]j]ujMgjhj]rbjXcd /packagesrcrd}re(jj`jj^ubaubj)rf}rg(jXRun pdksetupenv scriptrhjjGjj{jjj}ri(j]j]j]j]j]ujMijhj]rjjXRun pdksetupenv scriptrkrl}rm(jjhjjfubaubj)rn}ro(jXcd ti/boot/sblrpjjGjj{jjj}rq(j]j]j]j]j]ujMkjhj]rrjXcd ti/boot/sblrsrt}ru(jjpjjnubaubeubj)rv}rw(jUjj0jj{jjj}rx(j]j]j]j]ryU cleaning-sblrzaj]r{jaujMnjhj]r|(j)r}}r~(jX Cleaning SBLrjjvjj{jjj}r(j]j]j]j]j]ujMnjhj]rjX Cleaning SBLrr}r(jjjj}ubaubj)r}r(jXBgmake clean SOC= BOARD= BOOTMODE=rjjvjj{jjj}r(j]j]j]j]j]ujMpjhj]rjXBgmake clean SOC= BOARD= BOOTMODE=rr}r(jjjjubaubeubj)r}r(jUjj0jj{jjj}r(j]j]j]j]rU building-sblraj]rhaujMsjhj]r(j)r}r(jX Building SBLrjjjj{jjj}r(j]j]j]j]j]ujMsjhj]rjX Building SBLrr}r(jjjjubaubj)r}r(jX<gmake SOC= BOARD= BOOTMODE=rjjjj{jjj}r(j]j]j]j]j]ujMujhj]rjX<gmake SOC= BOARD= BOOTMODE=rr}r(jjjjubaubeubj)r}r(jUjj0jj{jjj}r(j]j]j]j]rUcleaning-flash-writerraj]rhtaujMxjhj]r(j)r}r(jXCleaning Flash Writerrjjjj{jjj}r(j]j]j]j]j]ujMxjhj]rjXCleaning Flash Writerrr}r(jjjjubaubj)r}r(jXQgmake _clean SOC= BOARD= BOOTMODE=rjjjj{jjj}r(j]j]j]j]j]ujMzjhj]rjXQgmake _clean SOC= BOARD= BOOTMODE=rr}r(jjjjubaubeubj)r}r(jUjj0jj{jjj}r(j]j]j]j]rUbuilding-flash-writerraj]rjaujM~jhj]r(j)r}r(jXbuilding-flash-writerrjjjj{jjj}r(j]j]j]j]j]ujM~jhj]rjXbuilding-flash-writerrr}r(jjjjubaubj)r}r(jXKgmake SOC= BOARD= BOOTMODE=rjjjj{jjj}r(j]j]j]j]j]ujMjhj]rjXKgmake SOC= BOARD= BOOTMODE=rr}r(jjjjubaubjt)r}r(jUjjjj{jjwj}r(jyX-j]j]j]j]j]ujMjhj]r(j{)r}r(jX+use 'make' instead of 'gmake' on Linux hostrjjjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj{jjj}r(j]j]j]j]j]ujMj]rjX+use 'make' instead of 'gmake' on Linux hostrr}r(jjjjubaubaubj{)r}r(jX( - OMAPL137, OMAPL138 or C6748rjjjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj{jjj}r(j]j]j]j]j]ujMj]rjX( - OMAPL137, OMAPL138 or C6748rr}r(jjjjubaubaubj{)r}r(jX5 - evmOMAPL137, lcdkOMAPL138 or lcdkC6748rjjjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj{jjj}r(j]j]j]j]j]ujMj]rjX5 - evmOMAPL137, lcdkOMAPL138 or lcdkC6748rr}r(jjjjubaubaubj{)r}r(jX5 - spi or mmcsd as supported by the devicerjjjj{jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj{jjj}r(j]j]j]j]j]ujMj]rjX5 - spi or mmcsd as supported by the devicerr}r(jjjjubaubaubj{)r}r(jXO - spi_flashwriter for spi boot mmcsd_flashwriter for mmcsd boot jjjj{jjj}r(j]j]j]j]j]ujNjhj]r j)r }r (jXN - spi_flashwriter for spi boot mmcsd_flashwriter for mmcsd bootr jjjj{jjj}r (j]j]j]j]j]ujMj]rjXN - spi_flashwriter for spi boot mmcsd_flashwriter for mmcsd bootrr}r(jj jj ubaubaubeubj)r}r(jXIExamples: Cleaning & Building OMAPL137 SBL gmake clean SOC=OMAPL137 BOARD=evmOMAPL137 BOOTMODE=spi gmake SOC=OMAPL137 BOARD=evmOMAPL137 BOOTMODE=spi Cleaning & Building OMAPL137 flash writer gmake spi_flashwriter_clean SOC=OMAPL137 BOARD=evmOMAPL137 BOOTMODE=spi gmake spi_flashwriter SOC=OMAPL137 BOARD=evmOMAPL137 BOOTMODE=spijjjj{jjj}r(j@jAj]j]j]j]j]ujM/jhj]rjXIExamples: Cleaning & Building OMAPL137 SBL gmake clean SOC=OMAPL137 BOARD=evmOMAPL137 BOOTMODE=spi gmake SOC=OMAPL137 BOARD=evmOMAPL137 BOOTMODE=spi Cleaning & Building OMAPL137 flash writer gmake spi_flashwriter_clean SOC=OMAPL137 BOARD=evmOMAPL137 BOOTMODE=spi gmake spi_flashwriter SOC=OMAPL137 BOARD=evmOMAPL137 BOOTMODE=spirr}r(jUjjubaubj)r}r(jX On successful build, SBL .out and MLO will be created at **/packages/ti/boot/sbl/binary///bin** and flash writer binary will be created at **/packages/ti/boot/sbl/tools/flashWriter//bin/**jjjj{jjj}r(j]j]j]j]j]ujMjhj]r(jX9On successful build, SBL .out and MLO will be created at rr}r(jX9On successful build, SBL .out and MLO will be created at jjubj)r }r!(jXN**/packages/ti/boot/sbl/binary///bin**j}r"(j]j]j]j]j]ujjj]r#jXJ/packages/ti/boot/sbl/binary///binr$r%}r&(jUjj ubajjubjX, and flash writer binary will be created at r'r(}r)(jX, and flash writer binary will be created at jjubj)r*}r+(jXY**/packages/ti/boot/sbl/tools/flashWriter//bin/**j}r,(j]j]j]j]j]ujjj]r-jXU/packages/ti/boot/sbl/tools/flashWriter//bin/r.r/}r0(jUjj*ubajjubeubeubeubeubeubj)r1}r2(jUjjjjjjj}r3(j]j]j]j]r4Ubootloader-debuggingr5aj]r6haujKkjhj]r7(j)r8}r9(jXBootloader Debuggingr:jj1jjjjj}r;(j]j]j]j]j]ujKkjhj]r<jXBootloader Debuggingr=r>}r?(jj:jj8ubaubj)r@}rA(jUjj1jj:XTsource/rtos/PDK_Platform_Software/Boot_Board_and_EVM_Abstractions/Boot_Debug.rst.incrBrC}rDbjjj}rE(j]j]j]j]rFU&common-steps-to-debug-application-bootrGaj]rHhaujKjhj]rI(j)rJ}rK(jX&Common Steps to debug application bootrLjj@jjCjjj}rM(j]j]j]j]j]ujKjhj]rNjX&Common Steps to debug application bootrOrP}rQ(jjLjjJubaubj)rR}rS(jXBootloading an application is a system level issue which is impacted by hardware as well as software setup. There are some common steps that users are expected to check while debugging boot related issues. This section discusses common issues to checkout when debugging application boot.rTjj@jjCjjj}rU(j]j]j]j]j]ujKjhj]rVjXBootloading an application is a system level issue which is impacted by hardware as well as software setup. There are some common steps that users are expected to check while debugging boot related issues. This section discusses common issues to checkout when debugging application boot.rWrX}rY(jjTjjRubaubjc)rZ}r[(jUjj@jjCjjfj}r\(j]j]j]j]j]ujK jhj]r]ji)r^}r_(jUjlKjjZjjCjjj}r`(j]j]j]j]j]ujKjhj]ubaubj)ra}rb(jUjj@jjCjjj}rc(j]j]j]j]rdUhardware-debug-stepsreaj]rfjaujK jhj]rg(j)rh}ri(jXHardware Debug StepsrjjjajjCjjj}rk(j]j]j]j]j]ujK jhj]rljXHardware Debug Stepsrmrn}ro(jjjjjhubaubj)rp}rq(jX-
jjajjCjjj}rr(UformatXhtmlj@jAj]j]j]j]j]ujKjhj]rsjX-
rtru}rv(jUjjpubaubj)rw}rx(jX%**Input clocks and power sequencing**ryjjajjCjjj}rz(j]j]j]j]j]ujKjhj]r{j)r|}r}(jjyj}r~(j]j]j]j]j]ujjwj]rjX!Input clocks and power sequencingrr}r(jUjj|ubajjubaubjt)r}r(jUjjajjCjjwj}r(jyX-j]j]j]j]j]ujKjhj]r(j{)r}r(jXEnsure that correct power sequencing is occurring on your board. Power sequencing specifications can be found in the data manual.jjjjCjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXEnsure that correct power sequencing is occurring on your board. Power sequencing specifications can be found in the data manual.rjjjjCjjj}r(j]j]j]j]j]ujKj]rjXEnsure that correct power sequencing is occurring on your board. Power sequencing specifications can be found in the data manual.rr}r(jjjjubaubaubj{)r}r(jXCheck the system clock and ensure this is outputting the expected frequency and the signal is swinging rail to rail (should be a 1.8V signal). If you have an external oscillator, it should be outputting a square wave at the desired frequency. If you are using a crystal , you should have a sine wave at the desired frequency at XTALIN. XTALOUT should be similar (may be distorted a little).jjjjCjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXCheck the system clock and ensure this is outputting the expected frequency and the signal is swinging rail to rail (should be a 1.8V signal). If you have an external oscillator, it should be outputting a square wave at the desired frequency. If you are using a crystal , you should have a sine wave at the desired frequency at XTALIN. XTALOUT should be similar (may be distorted a little).rjjjjCjjj}r(j]j]j]j]j]ujKj]rjXCheck the system clock and ensure this is outputting the expected frequency and the signal is swinging rail to rail (should be a 1.8V signal). If you have an external oscillator, it should be outputting a square wave at the desired frequency. If you are using a crystal , you should have a sine wave at the desired frequency at XTALIN. XTALOUT should be similar (may be distorted a little).rr}r(jjjjubaubaubj{)r}r(jXCheck the power on reset signal PORZ. This signal should stay low throughout the power sequencing and go high when the power AND high frequency clock are stable.jjjjCjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXCheck the power on reset signal PORZ. This signal should stay low throughout the power sequencing and go high when the power AND high frequency clock are stable.rjjjjCjjj}r(j]j]j]j]j]ujKj]rjXCheck the power on reset signal PORZ. This signal should stay low throughout the power sequencing and go high when the power AND high frequency clock are stable.rr}r(jjjjubaubaubj{)r}r(jXIf the device has an OBSCLK or CLKOUT then ensure that this pin provides the correct output that matches your software configurations. jjjjCjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXIf the device has an OBSCLK or CLKOUT then ensure that this pin provides the correct output that matches your software configurations.rjjjjCjjj}r(j]j]j]j]j]ujK j]rjXIf the device has an OBSCLK or CLKOUT then ensure that this pin provides the correct output that matches your software configurations.rr}r(jjjjubaubaubeubj)r}r(jX**Boot pins:**rjjajjCjjj}r(j]j]j]j]j]ujK$jhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX Boot pins:rr}r(jUjjubajjubaubj)r}r(jXBest way to confirm what the device ROM bootloader reads from the pins is to read the register where the Boot pins are latched into the device:rjjajjCjjj}r(j]j]j]j]j]ujK&jhj]rjXBest way to confirm what the device ROM bootloader reads from the pins is to read the register where the Boot pins are latched into the device:rr}r(jjjjubaubjt)r}r(jUjjajjCjjwj}r(jyX-j]j]j]j]j]ujK)jhj]r(j{)r}r(jX4For AM335x/AM437x: Check the Control_status registerrjjjjCjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjCjjj}r(j]j]j]j]j]ujK)j]rjX4For AM335x/AM437x: Check the Control_status registerrr}r(jjjjubaubaubj{)r}r(jX.For AM57xs: Check CTRL_CORE_BOOTSTRAP registerrjjjjCjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjCjjj}r(j]j]j]j]j]ujK*j]rjX.For AM57xs: Check CTRL_CORE_BOOTSTRAP registerrr}r(jjjjubaubaubj{)r}r(jX0For C66x/K2X devices: Check the DEVSTAT registerrjjjjCjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjCjjj}r(j]j]j]j]j]ujK+j]rjX0For C66x/K2X devices: Check the DEVSTAT registerrr}r(jjjjubaubaubj{)r}r(jX3For OMAPL13x/C674x devices: Check BOOTCFG register jjjjCjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX2For OMAPL13x/C674x devices: Check BOOTCFG registerrjjjjCjjj}r(j]j]j]j]j]ujK,j]rjX2For OMAPL13x/C674x devices: Check BOOTCFG registerrr}r(jjjjubaubaubeubj)r}r(jX**Boot media connectivity**rjjajjCjjj}r(j]j]j]j]j]ujK.jhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXBoot media connectivityrr }r (jUjjubajjubaubj)r }r (jX@Users are required to test their boot interface by running boot loader independent diagnostic tests that confirm that the SOC can read and write from the boot interface. Processor SDK RTOS provides Diagnostic utilities for K2G/AMXX devices and provides POST utility for keystone devices with which the TI EVM was tested.r jjajjCjjj}r(j]j]j]j]j]ujK0jhj]rjX@Users are required to test their boot interface by running boot loader independent diagnostic tests that confirm that the SOC can read and write from the boot interface. Processor SDK RTOS provides Diagnostic utilities for K2G/AMXX devices and provides POST utility for keystone devices with which the TI EVM was tested.rr}r(jj jj ubaubj)r}r(jXzTI Technical documentation like Technical reference manual (AMXX devices), Bootloader USer guide (for C66x/K2X devices) and Bootloader Application notes for OMAPLxx/C674x list default behavior or the ROM bootloader and limitations and constraints for each boot mode. Application developers need to account for this while designing their system to ensure smooth bring up process.rjjajjCjjj}r(j]j]j]j]j]ujK6jhj]rjXzTI Technical documentation like Technical reference manual (AMXX devices), Bootloader USer guide (for C66x/K2X devices) and Bootloader Application notes for OMAPLxx/C674x list default behavior or the ROM bootloader and limitations and constraints for each boot mode. Application developers need to account for this while designing their system to ensure smooth bring up process.rr}r(jjjjubaubj)r}r(jX+**Signalling on boot media and reset pins**rjjajjCjjj}r(j]j]j]j]j]ujK=jhj]rj)r }r!(jjj}r"(j]j]j]j]j]ujjj]r#jX'Signalling on boot media and reset pinsr$r%}r&(jUjj ubajjubaubj)r'}r((jXIf software and other hardware debug steps have not helped identify the issue, you may need to hook up a scope or protocol analyzer to check the clocks and the data transfers from the boot media to check if there is any issues that can be identified. Another commonly known issue that impacts boot is noise on the power lines which may cause the SOC to reset or cause a hang on the boot core. Provide these scope shots to TI on E2E forums so TI engineers can confirm that there are no issues.r)jjajjCjjj}r*(j]j]j]j]j]ujK?jhj]r+jXIf software and other hardware debug steps have not helped identify the issue, you may need to hook up a scope or protocol analyzer to check the clocks and the data transfers from the boot media to check if there is any issues that can be identified. Another commonly known issue that impacts boot is noise on the power lines which may cause the SOC to reset or cause a hang on the boot core. Provide these scope shots to TI on E2E forums so TI engineers can confirm that there are no issues.r,r-}r.(jj)jj'ubaubj)r/}r0(jX
jjajjCjjj}r1(UformatXhtmlj@jAj]j]j]j]j]ujKGjhj]r2jX
r3r4}r5(jUjj/ubaubeubj)r6}r7(jUjj@jjCjjj}r8(j]j]j]j]r9Usoftware-debug-stepsr:aj]r;haujKLjhj]r<(j)r=}r>(jXSoftware Debug Stepsr?jj6jjCjjj}r@(j]j]j]j]j]ujKLjhj]rAjXSoftware Debug StepsrBrC}rD(jj?jj=ubaubj)rE}rF(jX-
jj6jjCjjj}rG(UformatXhtmlj@jAj]j]j]j]j]ujKNjhj]rHjX-
rIrJ}rK(jUjjEubaubjhK)rL}rM(jXSBL and app Entry pointsrNjj6jjCjjlKj}rO(j]rPUsbl-and-app-entry-pointsrQaj]j]j]j]rRhaujNjhj]rSjXSBL and app Entry pointsrTrU}rV(jjNjjLubaubj)rW}rX(jXIf you don`t see your bootloader executing post boot, a good sanity check is for you to look at the map file for the bootloader and ensure that the entry point matches with the location in the TI or GPHeader in the boot image. this can be done by looking at the entry point in the MLO/_ti.bin/GPheader and ensure that it matches with the location of symbol Entry in the .out/map file for the bootloader.rYjj6jjCjjj}rZ(j]j]j]j]j]ujKUjhj]r[jXIf you don`t see your bootloader executing post boot, a good sanity check is for you to look at the map file for the bootloader and ensure that the entry point matches with the location in the TI or GPHeader in the boot image. this can be done by looking at the entry point in the MLO/_ti.bin/GPheader and ensure that it matches with the location of symbol Entry in the .out/map file for the bootloader.r\r]}r^(jjYjjWubaubjhK)r_}r`(jXSBL and App memory maprajj6jjCjjlKj}rb(j]rcUsbl-and-app-memory-maprdaj]j]j]j]rehaujNjhj]rfjXSBL and App memory maprgrh}ri(jjajj_ubaubj)rj}rk(jXXThe SBL execute from device onchip memory so if your application is also using Onchip memory in addition to DDR memory, developers need to ensure that the code sections in the application do not overlap with memory sections that are used by the SBL. This can cause the SBL to hang during the application boot process and go into an abort state.rljj6jjCjjj}rm(j]j]j]j]j]ujK_jhj]rnjXXThe SBL execute from device onchip memory so if your application is also using Onchip memory in addition to DDR memory, developers need to ensure that the code sections in the application do not overlap with memory sections that are used by the SBL. This can cause the SBL to hang during the application boot process and go into an abort state.rorp}rq(jjljjjubaubj)rr}rs(jXoTo check what memory region is used by the SBL please locate the map file created from building the bootloader.rtjj6jjCjjj}ru(j]j]j]j]j]ujKejhj]rvjXoTo check what memory region is used by the SBL please locate the map file created from building the bootloader.rwrx}ry(jjtjjrubaubjhK)rz}r{(jXFlash Programming verificationr|jj6jjCjjlKj}r}(j]r~Uflash-programming-verificationraj]j]j]j]rhaujNjhj]rjXFlash Programming verificationrr}r(jj|jjzubaubj)r}r(jXIt is essential to understand that the flash programmer that you use has not just the ability to write the image to flash but should also be able to verify that the image written to flash matches the image that you have created on your host machine. you can use TI flash programming utilities as reference and ensure that the production flashing tools use a method to erase, write and then verify the boot image that is written to the flash.rjj6jjCjjj}r(j]j]j]j]j]ujKkjhj]rjXIt is essential to understand that the flash programmer that you use has not just the ability to write the image to flash but should also be able to verify that the image written to flash matches the image that you have created on your host machine. you can use TI flash programming utilities as reference and ensure that the production flashing tools use a method to erase, write and then verify the boot image that is written to the flash.rr}r(jjjjubaubjc)r}r(jUjj6jjCjjfj}r(j]j]j]j]j]ujKsjhj]rji)r}r(jUjlKjjjjCjjj}r(j]j]j]j]j]ujKjhj]ubaubjhK)r}r(jX"DDR timings and configuration /SBLrjj6jjCjjlKj}r(j]rU!ddr-timings-and-configuration-sblraj]j]j]j]rhXaujNjhj]rjX"DDR timings and configuration /SBLrr}r(jjjjubaubj)r}r(jXThe Processor SDK bootloader ships with DDR clock and timing settings that apply to the external memory devices that have been used in TI evaluation platforms. When running the code on custom platforms, users may be required to change these setting to match the timings required by custom design. We highly recommend that users create a GEL script similar to one provided by TI and test the memory interface with the new settings before using them in the secondary bootloader to setup external memory. `**Processor SDK Diagnostics** `__ provides a mem_test that can be used to test read and writes to the entire DDR address space for confirming the SOC EMIF settings.jj6jjCjjj}r(j]j]j]j]j]ujKxjhj]r(jXThe Processor SDK bootloader ships with DDR clock and timing settings that apply to the external memory devices that have been used in TI evaluation platforms. When running the code on custom platforms, users may be required to change these setting to match the timings required by custom design. We highly recommend that users create a GEL script similar to one provided by TI and test the memory interface with the new settings before using them in the secondary bootloader to setup external memory. rr}r(jXThe Processor SDK bootloader ships with DDR clock and timing settings that apply to the external memory devices that have been used in TI evaluation platforms. When running the code on custom platforms, users may be required to change these setting to match the timings required by custom design. We highly recommend that users create a GEL script similar to one provided by TI and test the memory interface with the new settings before using them in the secondary bootloader to setup external memory. jjubj)r}r(jX@`**Processor SDK Diagnostics** `__j}r(UnameX**Processor SDK Diagnostics**jXindex_board.html#diagnosticsj]j]j]j]j]ujjj]rjX**Processor SDK Diagnostics**rr}r(jUjjubajjubjX provides a mem_test that can be used to test read and writes to the entire DDR address space for confirming the SOC EMIF settings.rr}r(jX provides a mem_test that can be used to test read and writes to the entire DDR address space for confirming the SOC EMIF settings.jjubeubjhK)r}r(jX Emulator based debugging of bootrjj6jjCjjlKj}r(j]rU emulator-based-debugging-of-bootraj]j]j]j]rhyaujNjhj]rjX Emulator based debugging of bootrr}r(jjjjubaubj)r}r(jXDThe processor SDK RTOS bootloader is like any other application that can be loaded over the emulator and debugged. Steps to connect an emulator to the EVM have been described in the `**Hardware Setup Guides** `__ that is linked to the Processor SDK RTOS documentation.jj6jjCjjj}r(j]j]j]j]j]ujKjhj]r(jXThe processor SDK RTOS bootloader is like any other application that can be loaded over the emulator and debugged. Steps to connect an emulator to the EVM have been described in the rr}r(jXThe processor SDK RTOS bootloader is like any other application that can be loaded over the emulator and debugged. Steps to connect an emulator to the EVM have been described in the jjubj)r}r(jXV`**Hardware Setup Guides** `__j}r(UnameX**Hardware Setup Guides**jX6Release_Specific.html#supported-platforms-and-versionsj]j]j]j]j]ujjj]rjX**Hardware Setup Guides**rr}r(jUjjubajjubjX8 that is linked to the Processor SDK RTOS documentation.rr}r(jX8 that is linked to the Processor SDK RTOS documentation.jjubeubj)r}r(jXLoading the bootloader over emulator can be very useful step in debugging the system boot. Before generating the final binary for bootloader, the build generates the .out file for the bootloader which is then formatted in a boot format that the ROM bootloader(RBL) can interpret. This .out can be loaded over the emulator similar to any other application. If you load the debug version of the bootloader, you can single step through the code that initializes the SOC and also part of the SBL code that loads the app from the boot media.rjj6jjCjjj}r(j]j]j]j]j]ujKjhj]rjXLoading the bootloader over emulator can be very useful step in debugging the system boot. Before generating the final binary for bootloader, the build generates the .out file for the bootloader which is then formatted in a boot format that the ROM bootloader(RBL) can interpret. This .out can be loaded over the emulator similar to any other application. If you load the debug version of the bootloader, you can single step through the code that initializes the SOC and also part of the SBL code that loads the app from the boot media.rr}r(jjjjubaubj)r}r(jXSBL runs from onchip memory so users can load the SBL.out even without using the GEL file but using the GEL sometimes helps with putting the core in a clean state so usage of the GEL is optionaljj6jjCjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXSBL runs from onchip memory so users can load the SBL.out even without using the GEL file but using the GEL sometimes helps with putting the core in a clean state so usage of the GEL is optionalrjjjjCjjj}r(j]j]j]j]j]ujKj]rjXSBL runs from onchip memory so users can load the SBL.out even without using the GEL file but using the GEL sometimes helps with putting the core in a clean state so usage of the GEL is optionalrr}r(jjjjubaubaubj)r}r(jX**Alternate Approach:**rjj6jjCjjj}r(j]j]j]j]j]ujKjhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXAlternate Approach:rr}r(jUjjubajjubaubj)r}r(jX**Add a spinlock in SBL main**rjj6jjCjjj}r(j]j]j]j]j]ujKjhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXAdd a spinlock in SBL mainrr}r(jUjjubajjubaubj)r}r(jX\In some occasions the RBL may load the SBL but there may be some issue that you need to debug in the SBL. In this case you can add a spinlock loop at the start of main in SBL and allow the first stage boot to complete normally and then connect to the core when you connect the core will be held in the spinlock condition waiting for you to connect.rjj6jjCjjj}r(j]j]j]j]j]ujKjhj]rjX\In some occasions the RBL may load the SBL but there may be some issue that you need to debug in the SBL. In this case you can add a spinlock loop at the start of main in SBL and allow the first stage boot to complete normally and then connect to the core when you connect the core will be held in the spinlock condition waiting for you to connect.rr}r(jjjjubaubj)r}r(jXExample:rjj6jjCjjj}r(j]j]j]j]j]ujKjhj]rjXExample:rr}r(jjjjubaubj)r}r (jX^volatile int exitSpinLock = 0; void Debug_spinLock(void) { while (exitSpinLock == 0) { } }jj6jjCjjj}r (j@jAj]j]j]j]j]ujM0jhj]r jX^volatile int exitSpinLock = 0; void Debug_spinLock(void) { while (exitSpinLock == 0) { } }r r }r(jUjjubaubj)r}r(jX#You will then have to "release" the core by toggling the variable which the while loop is blocking on. You can either do this manually by halting CCS, examining the variable in the watch window and then changing the value before continuing execution on the core, or you can use a GEL script.rjj6jjCjjj}r(j]j]j]j]j]ujKjhj]rjX#You will then have to "release" the core by toggling the variable which the while loop is blocking on. You can either do this manually by halting CCS, examining the variable in the watch window and then changing the value before continuing execution on the core, or you can use a GEL script.rr}r(jjjjubaubj)r}r(jXC**Use an IO input to stall the core until user input is received:**rjj6jjCjjj}r(j]j]j]j]j]ujKjhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX?Use an IO input to stall the core until user input is received:r r!}r"(jUjjubajjubaubj)r#}r$(jX,printf("Hit enter to continue:"); getchar();jj6jjCjjj}r%(j@jAj]j]j]j]j]ujM0jhj]r&jX,printf("Hit enter to continue:"); getchar();r'r(}r)(jUjj#ubaubjhK)r*}r+(jXSystem state at boot failurer,jj6jjCjjlKj}r-(j]r.Usystem-state-at-boot-failurer/aj]j]j]j]r0hcaujNjhj]r1jXSystem state at boot failurer2r3}r4(jj,jj*ubaubj)r5}r6(jXA useful data point for TI to debug boot related issues is to isolate commonly known initialization and to understand how far the bootloader has executed correctly before it runs into any issues. Users are required to capture ARM/DSP clocks, Program counter value, Entry points detected, pinmux configuration and confirm DDR initialization and slave core states. This helps minimize the number of variables in the system boot and helps us zero in on the most likely cause for the boot failure.r7jj6jjCjjj}r8(j]j]j]j]j]ujKjhj]r9jXA useful data point for TI to debug boot related issues is to isolate commonly known initialization and to understand how far the bootloader has executed correctly before it runs into any issues. Users are required to capture ARM/DSP clocks, Program counter value, Entry points detected, pinmux configuration and confirm DDR initialization and slave core states. This helps minimize the number of variables in the system boot and helps us zero in on the most likely cause for the boot failure.r:r;}r<(jj7jj5ubaubeubeubeubj)r=}r>(jUjjjjjjj}r?(j]j]j]j]r@Uuart-apploaderrAaj]rBjaujKojhj]rC(j)rD}rE(jXUART AppLoaderrFjj=jjjjj}rG(j]j]j]j]j]ujKojhj]rHjXUART AppLoaderrIrJ}rK(jjFjjDubaubj)rL}rM(jUjKjj=jj:XXsource/rtos/PDK_Platform_Software/Boot_Board_and_EVM_Abstractions/UART_Apploader.rst.incrNrO}rPbjjj}rQ(j]rRXoverviewrSaj]j]j]rTUid129rUaj]ujKjhj]rV(j)rW}rX(jXOverviewrYjjLjjOjjj}rZ(j]j]j]j]j]ujKjhj]r[jXOverviewr\r]}r^(jjYjjWubaubj)r_}r`(jXUART AppLoader is a standalone application used to download application image over UART from the host PC. Host PC uses the serial console utility to transfer application image to apploader.rajjLjjOjjj}rb(j]j]j]j]j]ujKjhj]rcjXUART AppLoader is a standalone application used to download application image over UART from the host PC. Host PC uses the serial console utility to transfer application image to apploader.rdre}rf(jjajj_ubaubj)rg}rh(jXsThe Apploader application loads and executes the application binary to be tested, over UART on the target platform.rijjLjjOjjj}rj(j]j]j]j]j]ujKjhj]rkjXsThe Apploader application loads and executes the application binary to be tested, over UART on the target platform.rlrm}rn(jjijjgubaubeubj)ro}rp(jUjj=jjOjjj}rq(j]j]j]j]rrUsupported-platformsrsaj]rtjoaujK jhj]ru(j)rv}rw(jXSupported PlatformsrxjjojjOjjj}ry(j]j]j]j]j]ujK jhj]rzjXSupported Platformsr{r|}r}(jjxjjvubaubjy )r~}r(jUjjojjOjj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujj~j]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXSOCrjjjjOjjj}r(j]j]j]j]j]ujKj]rjXSOCrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXPLATFORMrjjjjOjjj}r(j]j]j]j]j]ujKj]rjXPLATFORMrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXVerified Boot ModesrjjjjOjjj}r(j]j]j]j]j]ujKj]rjXVerified Boot Modesrr}r(jjjjubaubajj ubejj ubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]UmorerowsKj]ujjj]rj)r}r(jXAM335xrjjjjOjjj}r(j]j]j]j]j]ujKj]rjXAM335xrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX AM335x GP EVMrjjjjOjjj}r(j]j]j]j]j]ujKj]rjX AM335x GP EVMrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXMMCSDrjjjjOjjj}r(j]j]j]j]j]ujKj]rjXMMCSDrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX AM335x ICEv2rjjjjOjjj}r(j]j]j]j]j]ujKj]rjX AM335x ICEv2rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXMMCSDrjjjjOjjj}r(j]j]j]j]j]ujKj]rjXMMCSDrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r (j]j]j]j]j]ujjj]r j)r }r (jX AMIC110 ICEr jjjjOjjj}r(j]j]j]j]j]ujKj]rjX AMIC110 ICErr}r(jj jj ubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXSPIrjjjjOjjj}r(j]j]j]j]j]ujKj]rjXSPIrr}r(jjjjubaubajj ubejj ubj )r}r (jUj}r!(j]j]j]j]j]ujjj]r"(j )r#}r$(jUj}r%(j]j]j]j]UmorerowsKj]ujjj]r&j)r'}r((jXAM437xr)jj#jjOjjj}r*(j]j]j]j]j]ujKj]r+jXAM437xr,r-}r.(jj)jj'ubaubajj ubj )r/}r0(jUj}r1(j]j]j]j]j]ujjj]r2j)r3}r4(jX AM437x EVMr5jj/jjOjjj}r6(j]j]j]j]j]ujKj]r7jX AM437x EVMr8r9}r:(jj5jj3ubaubajj ubj )r;}r<(jUj}r=(j]j]j]j]j]ujjj]r>j)r?}r@(jXMMCSDrAjj;jjOjjj}rB(j]j]j]j]j]ujKj]rCjXMMCSDrDrE}rF(jjAjj?ubaubajj ubejj ubj )rG}rH(jUj}rI(j]j]j]j]j]ujjj]rJ(j )rK}rL(jUj}rM(j]j]j]j]j]ujjGj]rNj)rO}rP(jX AM437x IDKrQjjKjjOjjj}rR(j]j]j]j]j]ujKj]rSjX AM437x IDKrTrU}rV(jjQjjOubaubajj ubj )rW}rX(jUj}rY(j]j]j]j]j]ujjGj]rZj)r[}r\(jXMMCSDr]jjWjjOjjj}r^(j]j]j]j]j]ujKj]r_jXMMCSDr`ra}rb(jj]jj[ubaubajj ubejj ubj )rc}rd(jUj}re(j]j]j]j]j]ujjj]rf(j )rg}rh(jUj}ri(j]j]j]j]j]ujjcj]rjj)rk}rl(jXAM571xrmjjgjjOjjj}rn(j]j]j]j]j]ujKj]rojXAM571xrprq}rr(jjmjjkubaubajj ubj )rs}rt(jUj}ru(j]j]j]j]j]ujjcj]rvj)rw}rx(jX AM571x IDKryjjsjjOjjj}rz(j]j]j]j]j]ujKj]r{jX AM571x IDKr|r}}r~(jjyjjwubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjcj]rj)r}r(jXMMCSDrjjjjOjjj}r(j]j]j]j]j]ujKj]rjXMMCSDrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]UmorerowsKj]ujjj]rj)r}r(jXAM572xrjjjjOjjj}r(j]j]j]j]j]ujKj]rjXAM572xrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX AM572x EVMrjjjjOjjj}r(j]j]j]j]j]ujKj]rjX AM572x EVMrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXMMCSDrjjjjOjjj}r(j]j]j]j]j]ujKj]rjXMMCSDrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX AM572x IDKrjjjjOjjj}r(j]j]j]j]j]ujKj]rjX AM572x IDKrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXMMCSDrjjjjOjjj}r(j]j]j]j]j]ujKj]rjXMMCSDrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXAM574xrjjjjOjjj}r(j]j]j]j]j]ujK!j]rjXAM574xrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX AM574x IDKrjjjjOjjj}r(j]j]j]j]j]ujK!j]rjX AM574x IDKrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXMMCSDrjjjjOjjj}r(j]j]j]j]j]ujK!j]rjXMMCSDrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]UmorerowsKj]ujjj]rj)r}r(jXK2GrjjjjOjjj}r(j]j]j]j]j]ujK#j]rjXK2Grr}r(jjjjubaubajj ubj )r}r(jUj}r (j]j]j]j]j]ujjj]r j)r }r (jX K2G GP EVMr jjjjOjjj}r(j]j]j]j]j]ujK#j]rjX K2G GP EVMrr}r(jj jj ubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXMMCSDrjjjjOjjj}r(j]j]j]j]j]ujK#j]rjXMMCSDrr}r(jjjjubaubajj ubejj ubj )r}r (jUj}r!(j]j]j]j]j]ujjj]r"(j )r#}r$(jUj}r%(j]j]j]j]j]ujjj]r&j)r'}r((jXK2G ICEr)jj#jjOjjj}r*(j]j]j]j]j]ujK%j]r+jXK2G ICEr,r-}r.(jj)jj'ubaubajj ubj )r/}r0(jUj}r1(j]j]j]j]j]ujjj]r2j)r3}r4(jXMMCSDr5jj/jjOjjj}r6(j]j]j]j]j]ujK%j]r7jXMMCSDr8r9}r:(jj5jj3ubaubajj ubejj ubj )r;}r<(jUj}r=(j]j]j]j]j]ujjj]r>(j )r?}r@(jUj}rA(j]j]j]j]j]ujj;j]rBj)rC}rD(jXOMAPL137rEjj?jjOjjj}rF(j]j]j]j]j]ujK'j]rGjXOMAPL137rHrI}rJ(jjEjjCubaubajj ubj )rK}rL(jUj}rM(j]j]j]j]j]ujj;j]rNj)rO}rP(jX OMAPL137 EVMrQjjKjjOjjj}rR(j]j]j]j]j]ujK'j]rSjX OMAPL137 EVMrTrU}rV(jjQjjOubaubajj ubj )rW}rX(jUj}rY(j]j]j]j]j]ujj;j]rZj)r[}r\(jXSPIr]jjWjjOjjj}r^(j]j]j]j]j]ujK'j]r_jXSPIr`ra}rb(jj]jj[ubaubajj ubejj ubj )rc}rd(jUj}re(j]j]j]j]j]ujjj]rf(j )rg}rh(jUj}ri(j]j]j]j]j]ujjcj]rjj)rk}rl(jXOMAPL138rmjjgjjOjjj}rn(j]j]j]j]j]ujK)j]rojXOMAPL138rprq}rr(jjmjjkubaubajj ubj )rs}rt(jUj}ru(j]j]j]j]j]ujjcj]rvj)rw}rx(jX OMAPL138 LCDKryjjsjjOjjj}rz(j]j]j]j]j]ujK)j]r{jX OMAPL138 LCDKr|r}}r~(jjyjjwubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjcj]rj)r}r(jXMMCSDrjjjjOjjj}r(j]j]j]j]j]ujK)j]rjXMMCSDrr}r(jjjjubaubajj ubejj ubejj ubejj ubaubeubj)r}r(jUjj=jjOjjj}r(j]j]j]j]rUapploader-load-addressraj]rhaujK-jhj]r(j)r}r(jXApploader Load AddressrjjjjOjjj}r(j]j]j]j]j]ujK-jhj]rjXApploader Load Addressrr}r(jjjjubaubjy )r}r(jUjjjjOjj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujjj]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXSOCrjjjjOjjj}r(j]j]j]j]j]ujK0j]rjXSOCrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXPLATFORMrjjjjOjjj}r(j]j]j]j]j]ujK0j]rjXPLATFORMrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXDDR SizerjjjjOjjj}r(j]j]j]j]j]ujK0j]rjXDDR Sizerr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXDDR Start AddressrjjjjOjjj}r(j]j]j]j]j]ujK0j]rjXDDR Start Addressrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXApploader Load AddressrjjjjOjjj}r(j]j]j]j]j]ujK0j]rjXApploader Load Addressrr}r(jjjjubaubajj ubejj ubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]UmorerowsKj]ujjj]rj)r}r(jXAM335xrjjjjOjjj}r(j]j]j]j]j]ujK2j]rjXAM335xrr}r(jjjjubaubajj ubj )r }r (jUj}r (j]j]j]j]j]ujjj]r j)r }r(jX AM335x GP EVMrjj jjOjjj}r(j]j]j]j]j]ujK2j]rjX AM335x GP EVMrr}r(jjjj ubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX1GBrjjjjOjjj}r(j]j]j]j]j]ujK2j]rjX1GBrr}r (jjjjubaubajj ubj )r!}r"(jUj}r#(j]j]j]j]j]ujjj]r$j)r%}r&(jX 0x80010000r'jj!jjOjjj}r((j]j]j]j]j]ujK2j]r)jX 0x80010000r*r+}r,(jj'jj%ubaubajj ubj )r-}r.(jUj}r/(j]j]j]j]j]ujjj]r0j)r1}r2(jX 0xBFE00000r3jj-jjOjjj}r4(j]j]j]j]j]ujK2j]r5jX 0xBFE00000r6r7}r8(jj3jj1ubaubajj ubejj ubj )r9}r:(jUj}r;(j]j]j]j]j]ujjj]r<(j )r=}r>(jUj}r?(j]j]j]j]j]ujj9j]r@j)rA}rB(jX AM335x ICEv2rCjj=jjOjjj}rD(j]j]j]j]j]ujK4j]rEjX AM335x ICEv2rFrG}rH(jjCjjAubaubajj ubj )rI}rJ(jUj}rK(j]j]j]j]j]ujj9j]rLj)rM}rN(jX256MBrOjjIjjOjjj}rP(j]j]j]j]j]ujK4j]rQjX256MBrRrS}rT(jjOjjMubaubajj ubj )rU}rV(jUj}rW(j]j]j]j]j]ujj9j]rXj)rY}rZ(jX 0x80010000r[jjUjjOjjj}r\(j]j]j]j]j]ujK4j]r]jX 0x80010000r^r_}r`(jj[jjYubaubajj ubj )ra}rb(jUj}rc(j]j]j]j]j]ujj9j]rdj)re}rf(jX 0x8FD00000rgjjajjOjjj}rh(j]j]j]j]j]ujK4j]rijX 0x8FD00000rjrk}rl(jjgjjeubaubajj ubejj ubj )rm}rn(jUj}ro(j]j]j]j]j]ujjj]rp(j )rq}rr(jUj}rs(j]j]j]j]j]ujjmj]rtj)ru}rv(jX AMIC110 ICErwjjqjjOjjj}rx(j]j]j]j]j]ujK6j]ryjX AMIC110 ICErzr{}r|(jjwjjuubaubajj ubj )r}}r~(jUj}r(j]j]j]j]j]ujjmj]rj)r}r(jX512MBrjj}jjOjjj}r(j]j]j]j]j]ujK6j]rjX512MBrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjmj]rj)r}r(jX 0x80010000rjjjjOjjj}r(j]j]j]j]j]ujK6j]rjX 0x80010000rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjmj]rj)r}r(jX 0x9FE00000rjjjjOjjj}r(j]j]j]j]j]ujK6j]rjX 0x9FE00000rr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]UmorerowsKj]ujjj]rj)r}r(jXAM437xrjjjjOjjj}r(j]j]j]j]j]ujK8j]rjXAM437xrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX AM437x EVMrjjjjOjjj}r(j]j]j]j]j]ujK8j]rjX AM437x EVMrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX2GBrjjjjOjjj}r(j]j]j]j]j]ujK8j]rjX2GBrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX 0x80000000rjjjjOjjj}r(j]j]j]j]j]ujK8j]rjX 0x80000000rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX 0xFFE00000rjjjjOjjj}r(j]j]j]j]j]ujK8j]rjX 0xFFE00000rr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX AM437x IDKrjjjjOjjj}r(j]j]j]j]j]ujK:j]rjX AM437x IDKrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX1GBrjjjjOjjj}r(j]j]j]j]j]ujK:j]rjX1GBrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX 0x80000000rjjjjOjjj}r(j]j]j]j]j]ujK:j]rjX 0x80000000rr}r(jjjjubaubajj ubj )r }r (jUj}r (j]j]j]j]j]ujjj]r j)r }r(jX 0xBFE00000rjj jjOjjj}r(j]j]j]j]j]ujK:j]rjX 0xBFE00000rr}r(jjjj ubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXAM571xrjjjjOjjj}r (j]j]j]j]j]ujK(jUj}r?(j]j]j]j]j]ujjj]r@j)rA}rB(jX 0x80000000rCjj=jjOjjj}rD(j]j]j]j]j]ujKj]rajXAM572xrbrc}rd(jj_jj]ubaubajj ubj )re}rf(jUj}rg(j]j]j]j]j]ujjUj]rhj)ri}rj(jX AM572x EVMrkjjejjOjjj}rl(j]j]j]j]j]ujK>j]rmjX AM572x EVMrnro}rp(jjkjjiubaubajj ubj )rq}rr(jUj}rs(j]j]j]j]j]ujjUj]rtj)ru}rv(jX2GBrwjjqjjOjjj}rx(j]j]j]j]j]ujK>j]ryjX2GBrzr{}r|(jjwjjuubaubajj ubj )r}}r~(jUj}r(j]j]j]j]j]ujjUj]rj)r}r(jX 0x80000000rjj}jjOjjj}r(j]j]j]j]j]ujK>j]rjX 0x80000000rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjUj]rj)r}r(jX 0xFFDFFFFFrjjjjOjjj}r(j]j]j]j]j]ujK>j]rjX 0xFFDFFFFFrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX AM572x IDKrjjjjOjjj}r(j]j]j]j]j]ujK@j]rjX AM572x IDKrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX2GBrjjjjOjjj}r(j]j]j]j]j]ujK@j]rjX2GBrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX 0x80000000rjjjjOjjj}r(j]j]j]j]j]ujK@j]rjX 0x80000000rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX 0xFFDFFFFFrjjjjOjjj}r(j]j]j]j]j]ujK@j]rjX 0xFFDFFFFFrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXAM574xrjjjjOjjj}r(j]j]j]j]j]ujKBj]rjXAM574xrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX AM574x IDKrjjjjOjjj}r(j]j]j]j]j]ujKBj]rjX AM574x IDKrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX2GBrjjjjOjjj}r(j]j]j]j]j]ujKBj]rjX2GBrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX 0x80000000rjjjjOjjj}r(j]j]j]j]j]ujKBj]rjX 0x80000000rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX 0xFFDFFFFFrjjjjOjjj}r(j]j]j]j]j]ujKBj]rjX 0xFFDFFFFFrr}r(jjjjubaubajj ubejj ubj )r }r (jUj}r (j]j]j]j]j]ujjj]r (j )r }r(jUj}r(j]j]j]j]UmorerowsKj]ujj j]rj)r}r(jXK2Grjj jjOjjj}r(j]j]j]j]j]ujKDj]rjXK2Grr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj j]rj)r}r(jX K2G GP EVMrjjjjOjjj}r (j]j]j]j]j]ujKDj]r!jX K2G GP EVMr"r#}r$(jjjjubaubajj ubj )r%}r&(jUj}r'(j]j]j]j]j]ujj j]r(j)r)}r*(jX2GBr+jj%jjOjjj}r,(j]j]j]j]j]ujKDj]r-jX2GBr.r/}r0(jj+jj)ubaubajj ubj )r1}r2(jUj}r3(j]j]j]j]j]ujj j]r4j)r5}r6(jX 0x80000000r7jj1jjOjjj}r8(j]j]j]j]j]ujKDj]r9jX 0x80000000r:r;}r<(jj7jj5ubaubajj ubj )r=}r>(jUj}r?(j]j]j]j]j]ujj j]r@j)rA}rB(jX 0xFFD00000rCjj=jjOjjj}rD(j]j]j]j]j]ujKDj]rEjX 0xFFD00000rFrG}rH(jjCjjAubaubajj ubejj ubj )rI}rJ(jUj}rK(j]j]j]j]j]ujjj]rL(j )rM}rN(jUj}rO(j]j]j]j]j]ujjIj]rPj)rQ}rR(jXK2G ICErSjjMjjOjjj}rT(j]j]j]j]j]ujKFj]rUjXK2G ICErVrW}rX(jjSjjQubaubajj ubj )rY}rZ(jUj}r[(j]j]j]j]j]ujjIj]r\j)r]}r^(jX512MBr_jjYjjOjjj}r`(j]j]j]j]j]ujKFj]rajX512MBrbrc}rd(jj_jj]ubaubajj ubj )re}rf(jUj}rg(j]j]j]j]j]ujjIj]rhj)ri}rj(jX 0x80000000rkjjejjOjjj}rl(j]j]j]j]j]ujKFj]rmjX 0x80000000rnro}rp(jjkjjiubaubajj ubj )rq}rr(jUj}rs(j]j]j]j]j]ujjIj]rtj)ru}rv(jX 0x9FE00000rwjjqjjOjjj}rx(j]j]j]j]j]ujKFj]ryjX 0x9FE00000rzr{}r|(jjwjjuubaubajj ubejj ubj )r}}r~(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujj}j]rj)r}r(jXOMAPL137rjjjjOjjj}r(j]j]j]j]j]ujKHj]rjXOMAPL137rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj}j]rj)r}r(jX OMAPL137 EVMrjjjjOjjj}r(j]j]j]j]j]ujKHj]rjX OMAPL137 EVMrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj}j]rj)r}r(jX64MBrjjjjOjjj}r(j]j]j]j]j]ujKHj]rjX64MBrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj}j]rj)r}r(jX 0xC3000000rjjjjOjjj}r(j]j]j]j]j]ujKHj]rjX 0xC3000000rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj}j]rj)r}r(jX 0xC6E00000rjjjjOjjj}r(j]j]j]j]j]ujKHj]rjX 0xC6E00000rr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXOMAPL138rjjjjOjjj}r(j]j]j]j]j]ujKJj]rjXOMAPL138rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX OMAPL138 LCDKrjjjjOjjj}r(j]j]j]j]j]ujKJj]rjX OMAPL138 LCDKrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX128MBrjjjjOjjj}r(j]j]j]j]j]ujKJj]rjX128MBrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX 0xC0000000rjjjjOjjj}r(j]j]j]j]j]ujKJj]rjX 0xC0000000rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX 0xC7E00000rjjjjOjjj}r(j]j]j]j]j]ujKJj]rjX 0xC7E00000rr}r(jjjjubaubajj ubejj ubejj ubejj ubaubeubj)r}r(jUjj=jjOjjj}r(j]j]j]j]rUpre-requisitesraj]rjaujKNjhj]r(j)r}r(jXPre-RequisitesrjjjjOjjj}r(j]j]j]j]j]ujKNjhj]rjXPre-Requisitesr r }r (jjjjubaubj )r }r (jUjjjjOjj j}r(jU.j]j]j]jUj]j]jjujKOjhj]rj{)r}r(jXDownload and install the Processor-SDK RTOS package. See the software product page for your device to get the latest version of this software: jj jjOjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXDownload and install the Processor-SDK RTOS package. See the software product page for your device to get the latest version of this software:rjjjjOjjj}r(j]j]j]j]j]ujKOj]rjXDownload and install the Processor-SDK RTOS package. See the software product page for your device to get the latest version of this software:rr}r(jjjjubaubaubaubjt)r}r(jUjjjjOjjwj}r(jyX-j]j]j]j]j]ujKQjhj]r(j{)r }r!(jXJ`Processor SDK for AM335x `__jjjjOjjj}r"(j]j]j]j]j]ujNjhj]r#j)r$}r%(jXJ`Processor SDK for AM335x `__r&jj jjOjjj}r'(j]j]j]j]j]ujKQj]r(j)r)}r*(jj&j}r+(UnameXProcessor SDK for AM335xjX+http://www.ti.com/tool/processor-sdk-am335xj]j]j]j]j]ujj$j]r,jXProcessor SDK for AM335xr-r.}r/(jUjj)ubajjubaubaubj{)r0}r1(jXJ`Processor SDK for AM437x `__jjjjOjjj}r2(j]j]j]j]j]ujNjhj]r3j)r4}r5(jXJ`Processor SDK for AM437x `__r6jj0jjOjjj}r7(j]j]j]j]j]ujKSj]r8j)r9}r:(jj6j}r;(UnameXProcessor SDK for AM437xjX+http://www.ti.com/tool/processor-sdk-am437xj]j]j]j]j]ujj4j]r<jXProcessor SDK for AM437xr=r>}r?(jUjj9ubajjubaubaubj{)r@}rA(jXI`Processor SDK for AM57xx `__jjjjOjjj}rB(j]j]j]j]j]ujNjhj]rCj)rD}rE(jXI`Processor SDK for AM57xx `__rFjj@jjOjjj}rG(j]j]j]j]j]ujKUj]rHj)rI}rJ(jjFj}rK(UnameXProcessor SDK for AM57xxjX*http://www.ti.com/tool/processor-sdk-am57xj]j]j]j]j]ujjDj]rLjXProcessor SDK for AM57xxrMrN}rO(jUjjIubajjubaubaubj{)rP}rQ(jXL`Processor SDK for AMIC110 `__jjjjOjjj}rR(j]j]j]j]j]ujNjhj]rSj)rT}rU(jXL`Processor SDK for AMIC110 `__rVjjPjjOjjj}rW(j]j]j]j]j]ujKWj]rXj)rY}rZ(jjVj}r[(UnameXProcessor SDK for AMIC110jX,http://www.ti.com/tool/PROCESSOR-SDK-AMIC110j]j]j]j]j]ujjTj]r\jXProcessor SDK for AMIC110r]r^}r_(jUjjYubajjubaubaubj{)r`}ra(jXY`Processor SDK RTOS for C6747/OMAP-L17 `__jjjjOjjj}rb(j]j]j]j]j]ujNjhj]rcj)rd}re(jXY`Processor SDK RTOS for C6747/OMAP-L17 `__rfjj`jjOjjj}rg(j]j]j]j]j]ujKYj]rhj)ri}rj(jjfj}rk(UnameX%Processor SDK RTOS for C6747/OMAP-L17jX-http://www.ti.com/tool/processor-sdk-omapl137j]j]j]j]j]ujjdj]rljX%Processor SDK RTOS for C6747/OMAP-L17rmrn}ro(jUjjiubajjubaubaubj{)rp}rq(jXZ`Processor SDK RTOS for C6748/OMAP-L138 `__jjjjOjjj}rr(j]j]j]j]j]ujNjhj]rsj)rt}ru(jXZ`Processor SDK RTOS for C6748/OMAP-L138 `__rvjjpjjOjjj}rw(j]j]j]j]j]ujK[j]rxj)ry}rz(jjvj}r{(UnameX&Processor SDK RTOS for C6748/OMAP-L138jX-http://www.ti.com/tool/processor-sdk-omapl138j]j]j]j]j]ujjtj]r|jX&Processor SDK RTOS for C6748/OMAP-L138r}r~}r(jUjjyubajjubaubaubj{)r}r(jX`Processor SDK RTOS for K2G `__ From the appropriate software product page, go to the download page by clicking "Get Software" for the RTOS package. jjjjOjjj}r(j]j]j]j]j]ujNjhj]r(j)r}r(jXI`Processor SDK RTOS for K2G `__rjjjjOjjj}r(j]j]j]j]j]ujK]j]rj)r}r(jjj}r(UnameXProcessor SDK RTOS for K2GjX(http://www.ti.com/tool/PROCESSOR-SDK-K2Gj]j]j]j]j]ujjj]rjXProcessor SDK RTOS for K2Grr}r(jUjjubajjubaubj)r}r(jXtFrom the appropriate software product page, go to the download page by clicking "Get Software" for the RTOS package.rjjjjOjjj}r(j]j]j]j]j]ujK`j]rjXtFrom the appropriate software product page, go to the download page by clicking "Get Software" for the RTOS package.rr}r(jjjjubaubeubeubj )r}r(jUjjjjOjj j}r(jU.jO3Kj]j]j]jUj]j]jjujKcjhj]rj{)r}r(jXThe Uart Apploader binaries are found under /packages/ti/board/utils/uartAppLoader/bin//sd/apploader_Test jjjjOjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXThe Uart Apploader binaries are found under /packages/ti/board/utils/uartAppLoader/bin//sd/apploader_TestrjjjjOjjj}r(j]j]j]j]j]ujKcj]rjXThe Uart Apploader binaries are found under /packages/ti/board/utils/uartAppLoader/bin//sd/apploader_Testrr}r(jjjjubaubaubaubj)r}r(jX**Serial Connection**rjjjjOjjj}r(j]j]j]j]j]ujKejhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXSerial Connectionrr}r(jUjjubajjubaubj)r}r(jXDLaunch the serial console utility with the following configurations:rjjjjOjjj}r(j]j]j]j]j]ujKgjhj]rjXDLaunch the serial console utility with the following configurations:rr}r(jjjjubaubjt)r}r(jUjjjjOjjwj}r(jyX*j]j]j]j]j]ujKjjhj]r(j{)r}r(jXBaud Rate: 115200 jjjjOjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXBaud Rate: 115200rjjjjOjjj}r(j]j]j]j]j]ujKjj]rjXBaud Rate: 115200rr}r(jjjjubaubaubj{)r}r(jXData : 8 bits jjjjOjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX Data : 8 bitsrjjjjOjjj}r(j]j]j]j]j]ujKlj]rjX Data : 8 bitsrr}r(jjjjubaubaubj{)r}r(jXParity : None jjjjOjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX Parity : NonerjjjjOjjj}r(j]j]j]j]j]ujKnj]rjX Parity : Nonerr}r(jjjjubaubaubj{)r}r(jX Stop : 1 bit jjjjOjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX Stop : 1 bitrjjjjOjjj}r(j]j]j]j]j]ujKpj]rjX Stop : 1 bitrr}r(jjjjubaubaubj{)r}r(jXFlow Control : None jjjjOjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXFlow Control : NonerjjjjOjjj}r(j]j]j]j]j]ujKrj]rjXFlow Control : Nonerr}r(jjjjubaubaubeubj)r}r(jXbAny Serial Console utility that supports xmodem protocol can be used. Verified utility is TeratermjjjjOjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXbAny Serial Console utility that supports xmodem protocol can be used. Verified utility is TeratermrjjjjOjjj}r(j]j]j]j]j]ujKtj]rjXbAny Serial Console utility that supports xmodem protocol can be used. Verified utility is Teratermrr}r(jjjjubaubaubj)r}r (jXTI Binaries does not work with Apploader on AM335x/AM437x platforms. Make sure to use non TI binaries for testing on these platforms.jjjjOjjj}r (j]j]j]j]j]ujNjhj]r j)r }r (jXTI Binaries does not work with Apploader on AM335x/AM437x platforms. Make sure to use non TI binaries for testing on these platforms.rjjjjOjjj}r(j]j]j]j]j]ujKwj]rjXTI Binaries does not work with Apploader on AM335x/AM437x platforms. Make sure to use non TI binaries for testing on these platforms.rr}r(jjjj ubaubaubeubj)r}r(jUjj=jjOjjj}r(j]j]j]j]rUapploader-usageraj]rh aujK{jhj]r(j)r}r(jXAppLoader UsagerjjjjOjjj}r(j]j]j]j]j]ujK{jhj]rjXAppLoader Usager r!}r"(jjjjubaubj )r#}r$(jUjjjjOjj j}r%(jU.j]j]j]jUj]j]jjujK|jhj]r&(j{)r'}r((jX<Set the sysboot pins to the relevant boot mode(SPI / MMCSD).r)jj#jjOjjj}r*(j]j]j]j]j]ujNjhj]r+j)r,}r-(jj)jj'jjOjjj}r.(j]j]j]j]j]ujK|j]r/jX<Set the sysboot pins to the relevant boot mode(SPI / MMCSD).r0r1}r2(jj)jj,ubaubaubj{)r3}r4(jXMMake sure UART connection is established between Target platform and Host PC.r5jj#jjOjjj}r6(j]j]j]j]j]ujNjhj]r7j)r8}r9(jj5jj3jjOjjj}r:(j]j]j]j]j]ujK}j]r;jXMMake sure UART connection is established between Target platform and Host PC.r<r=}r>(jj5jj8ubaubaubj{)r?}r@(jXPower cycle the board.rAjj#jjOjjj}rB(j]j]j]j]j]ujNjhj]rCj)rD}rE(jjAjj?jjOjjj}rF(j]j]j]j]j]ujK~j]rGjXPower cycle the board.rHrI}rJ(jjAjjDubaubaubj{)rK}rL(jX[Check the below output on the serial console. The application starts sending character 'C' jj#jjOjjj}rM(j]j]j]j]j]ujNjhj]rNj)rO}rP(jXZCheck the below output on the serial console. The application starts sending character 'C'rQjjKjjOjjj}rR(j]j]j]j]j]ujKj]rSjXZCheck the below output on the serial console. The application starts sending character 'C'rTrU}rV(jjQjjOubaubaubeubj)rW}rX(jX,**** PDK SBL **** SBL Revision: 01.00.09.00 (May 10 2018 - 15:48:57) Begin parsing user application SD Boot - file open completed successfully Jumping to user application... ********* PDK UART Apploader ******** version 0.1 (May 14 2018 - 21:40:11) Please transfer file with XMODEM protocol... CCCCjjjjOjjj}rY(j@jAj]j]j]j]j]ujMM1jhj]rZjX,**** PDK SBL **** SBL Revision: 01.00.09.00 (May 10 2018 - 15:48:57) Begin parsing user application SD Boot - file open completed successfully Jumping to user application... ********* PDK UART Apploader ******** version 0.1 (May 14 2018 - 21:40:11) Please transfer file with XMODEM protocol... CCCCr[r\}r](jUjjWubaubj)r^}r_(jX{The above log is for reference purpose and content might change based on latest software available in processor SDK releaser`jjjjOjjj}ra(j]j]j]j]j]ujNjhj]rbj)rc}rd(jj`jj^jjOjjj}re(j]j]j]j]j]ujKj]rfjX{The above log is for reference purpose and content might change based on latest software available in processor SDK releasergrh}ri(jj`jjcubaubaubj )rj}rk(jUjjjjOjj j}rl(jU.jO3Kj]j]j]jUj]j]jjujKjhj]rmj{)rn}ro(jXYNow transfer the application binary to be tested over UART using serial console utility. jjjjjOjjj}rp(j]j]j]j]j]ujNjhj]rqj)rr}rs(jXXNow transfer the application binary to be tested over UART using serial console utility.rtjjnjjOjjj}ru(j]j]j]j]j]ujKj]rvjXXNow transfer the application binary to be tested over UART using serial console utility.rwrx}ry(jjtjjrubaubaubaubj)rz}r{(jXxFor example in Teraterm, use the following option to transfer the application binary. File -> Transfer -> XMODEM -> SendjjjjOjjj}r|(j]j]j]j]j]ujNjhj]r}j)r~}r(jXxFor example in Teraterm, use the following option to transfer the application binary. File -> Transfer -> XMODEM -> SendrjjzjjOjjj}r(j]j]j]j]j]ujKj]rjXxFor example in Teraterm, use the following option to transfer the application binary. File -> Transfer -> XMODEM -> Sendrr}r(jjjj~ubaubaubj )r}r(jUjjjjOjj j}r(jU.jO3Kj]j]j]jUj]j]jjujKjhj]r(j{)r}r(jX?Upon success, the apploader loads and executes the application.rjjjjOjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjOjjj}r(j]j]j]j]j]ujKj]rjX?Upon success, the apploader loads and executes the application.rr}r(jjjjubaubaubj{)r}r(jX[Following is the sample output (using UART Diagnostic application), on the serial console. jjjjOjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXZFollowing is the sample output (using UART Diagnostic application), on the serial console.rjjjjOjjj}r(j]j]j]j]j]ujKj]rjXZFollowing is the sample output (using UART Diagnostic application), on the serial console.rr}r(jjjjubaubaubeubj)r}r(jXXmodem received 46848 bytes Copying application image from UART to RAM is done Begin parsing user application Jumping to user application... ********************************************* * UART Test * ********************************************* Testing UART print to console at 115.2k baud rate Press 'y' to verify pass: y Received: y Test PASSED!jjjjOjjj}r(j@jAj]j]j]j]j]ujMe1jhj]rjXXmodem received 46848 bytes Copying application image from UART to RAM is done Begin parsing user application Jumping to user application... ********************************************* * UART Test * ********************************************* Testing UART print to console at 115.2k baud rate Press 'y' to verify pass: y Received: y Test PASSED!rr}r(jUjjubaubj)r}r(jXFor SPI Boot Mode: 1. Program Apploader to SPI flash using `Uniflash `__ and boot the device from SPI flash. 2. Set the sysboot pins to SPI Boot modejjjjOjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXFor SPI Boot Mode: 1. Program Apploader to SPI flash using `Uniflash `__ and boot the device from SPI flash. 2. Set the sysboot pins to SPI Boot modejjjjOjjj}r(j]j]j]j]j]ujKj]r(jX;For SPI Boot Mode: 1. Program Apploader to SPI flash using rr}r(jX;For SPI Boot Mode: 1. Program Apploader to SPI flash using jjubj)r}r(jXD`Uniflash `__j}r(UnameXUniflashjX5index_board.html#programming-binaries-to-flash-devicej]j]j]j]j]ujjj]rjXUniflashrr}r(jUjjubajjubjXM and boot the device from SPI flash. 2. Set the sysboot pins to SPI Boot moderr}r(jXM and boot the device from SPI flash. 2. Set the sysboot pins to SPI Boot modejjubeubaubj)r}r(jXFor MMCSD Boot Mode: 1. Copy MLO to SD card. 2. Rename apploader_Test to app and copy to SD card. 3. Set the sysboot pins to MMCSD Boot modejjjjOjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXFor MMCSD Boot Mode: 1. Copy MLO to SD card. 2. Rename apploader_Test to app and copy to SD card. 3. Set the sysboot pins to MMCSD Boot moderjjjjOjjj}r(j]j]j]j]j]ujKj]rjXFor MMCSD Boot Mode: 1. Copy MLO to SD card. 2. Rename apploader_Test to app and copy to SD card. 3. Set the sysboot pins to MMCSD Boot moderr}r(jjjjubaubaubeubj)r}r(jUjj=jjOjjj}r(j]j]j]j]rUrebuilding-apploaderraj]rjSaujKjhj]r(j)r}r(jXRebuilding AppLoaderrjjjjOjjj}r(j]j]j]j]j]ujKjhj]rjXRebuilding AppLoaderrr}r(jjjjubaubj)r}r(jXApploader pre-built binaries are currently not available for OMAPL137/L138 platforms. Binaries needs to be manually built for these platforms.rjjjjOjjj}r(j]j]j]j]j]ujKjhj]rjXApploader pre-built binaries are currently not available for OMAPL137/L138 platforms. Binaries needs to be manually built for these platforms.rr}r(jjjjubaubj)r}r(jXfRefer `Rebuilding Board Utils `__ section to build Apploader.rjjjjOjjj}r(j]j]j]j]j]ujKjhj]r(jXRefer rr}r(jXRefer jjubj)r}r(jXD`Rebuilding Board Utils `__j}r(UnameXRebuilding Board UtilsjX'index_board.html#rebuilding-board-utilsj]j]j]j]j]ujjj]rjXRebuilding Board Utilsrr}r(jUjjubajjubjX section to build Apploader.rr}r(jX section to build Apploader.jjubeubeubeubeubjjj}rh9jsjjj}r(j]rXoverviewraj]j]j]r(jUid66rej]rh9aujKjhj"}rjjsj]r(j)r}r(jXOverviewrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXOverviewrr}r(jjjjubaubj)r}r(jXeThis page provides an overview about the Secondary Bootloader support provided in Processor SDK RTOS.rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXeThis page provides an overview about the Secondary Bootloader support provided in Processor SDK RTOS.r r }r (jjjjubaubj)r }r (jX=The Secondary Bootloader (SBL) sets-up the PLL clocks, powers on the I/O Peripherals, initializes the DDR, loads the application image into DDR & brings the slave cores for applicable SOCs out of reset. Additional details including execution boot flow is covered in more elaborate detail under individual SOC section.rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjX=The Secondary Bootloader (SBL) sets-up the PLL clocks, powers on the I/O Peripherals, initializes the DDR, loads the application image into DDR & brings the slave cores for applicable SOCs out of reset. Additional details including execution boot flow is covered in more elaborate detail under individual SOC section.rr}r(jjjj ubaubeubjjjjv~j}r(j]UlevelKj]j]rjaUsourcejj]j]UlineKUtypej~ujKjhj]rj)r}r(jX+Duplicate implicit target name: "overview".j}r(j]j]j]j]j]ujjj]rjX+Duplicate implicit target name: "overview".rr}r(jUjjubajjubaubjs~)r}r(jUjjcjj\jjv~j}r (j]UlevelKj]j]r!jiaUsourcej\j]j]UlineKUtypej~ujKjhj]r"j)r#}r$(jX+Duplicate implicit target name: "overview".j}r%(j]j]j]j]j]ujjj]r&jX+Duplicate implicit target name: "overview".r'r(}r)(jUjj#ubajjubaubjs~)r*}r+(jUjj"jj\jjv~j}r,(j]UlevelKj]j]Usourcejj]j]UlineKUtypej~ujKjhj]r-j)r.}r/(jX:Enumerated list start value not ordinal-1: "2" (ordinal 2)j}r0(j]j]j]j]j]ujj*j]r1jX:Enumerated list start value not ordinal-1: "2" (ordinal 2)r2r3}r4(jUjj.ubajjubaubjs~)r5}r6(jUjj"jj\jjv~j}r7(j]UlevelKj]j]Usourcejj]j]UlineKUtypej~ujKjhj]r8j)r9}r:(jX:Enumerated list start value not ordinal-1: "3" (ordinal 3)j}r;(j]j]j]j]j]ujj5j]r<jX:Enumerated list start value not ordinal-1: "3" (ordinal 3)r=r>}r?(jUjj9ubajjubaubjs~)r@}rA(jUjj4jj\jjv~j}rB(j]UlevelKj]j]rCj9aUsourcej\j]j]UlineMIUtypej~ujMIjhj]rDj)rE}rF(jX-Duplicate implicit target name: "boot modes".j}rG(j]j]j]j]j]ujj@j]rHjX-Duplicate implicit target name: "boot modes".rIrJ}rK(jUjjEubajjubaubjs~)rL}rM(jUjjBjXsinternal padding after source/rtos/PDK_Platform_Software/Boot_Board_and_EVM_Abstractions/BOOT_AM335x_AM437x.rst.incrNjjv~j}rO(j]UlevelKj]j]Usourcej\j]j]UlineMRUtypeUERRORrPujMTjhj]rQ(j)rR}rS(jX;Content block expected for the "raw" directive; none found.j}rT(j]j]j]j]j]ujjLj]rUjX;Content block expected for the "raw" directive; none found.rVrW}rX(jUjjRubajjubj)rY}rZ(jX.. raw:: html j}r[(j@jAj]j]j]j]j]ujjLj]r\jX.. raw:: html r]r^}r_(jUjjYubajjubeubjs~)r`}ra(jUjjyjjrjjv~j}rb(j]UlevelKj]j]rcjaUsourcejrj]j]UlineKUtypej~ujKjhj]rdj)re}rf(jX+Duplicate implicit target name: "overview".j}rg(j]j]j]j]j]ujj`j]rhjX+Duplicate implicit target name: "overview".rirj}rk(jUjjeubajjubaubjs~)rl}rm(jUjjjjrjjv~j}rn(j]UlevelKj]j]rojaUsourcejrj]j]UlineK Utypej~ujK jhj]rpj)rq}rr(jX@Duplicate implicit target name: "bootloader execution sequence".j}rs(j]j]j]j]j]ujjlj]rtjX@Duplicate implicit target name: "bootloader execution sequence".rurv}rw(jUjjqubajjubaubjs~)rx}ry(jUjjhjjrjjv~j}rz(j]UlevelKj]j]r{jmaUsourcejrj]j]UlineKUUtypej~ujKUjhj]r|j)r}}r~(jX;Duplicate implicit target name: "tools and binary formats".j}r(j]j]j]j]j]ujjxj]rjX;Duplicate implicit target name: "tools and binary formats".rr}r(jUjj}ubajjubaubjs~)r}r(jUjjhjjrjjv~j}r(j]UlevelKj]j]Usourcejrj]j]UlineKbUtypejx~ujKajhj]rj)r}r(jX%Line block ends without a blank line.j}r(j]j]j]j]j]ujjj]rjX%Line block ends without a blank line.rr}r(jUjjubajjubaubjs~)r}r(jUjjhjjrjjv~j}r(j]UlevelKj]j]Usourcejrj]j]UlineKUtypejx~ujKjhj]rj)r}r(jX%Line block ends without a blank line.j}r(j]j]j]j]j]ujjj]rjX%Line block ends without a blank line.rr}r(jUjjubajjubaubjs~)r}r(jUjjjjrjjv~j}r(j]UlevelKj]j]rjaUsourcejrj]j]UlineM Utypej~ujM jhj]rj)r}r(jX6Duplicate implicit target name: "booting via sd card".j}r(j]j]j]j]j]ujjj]rjX6Duplicate implicit target name: "booting via sd card".rr}r(jUjjubajjubaubjs~)r}r(jUjjjjrjjv~j}r(j]UlevelKj]j]rjaUsourcejrj]j]UlineM=Utypej~ujM=jhj]rj)r}r(jX5Duplicate implicit target name: "booting the target".j}r(j]j]j]j]j]ujjj]rjX5Duplicate implicit target name: "booting the target".rr}r(jUjjubajjubaubjs~)r}r(jUjjBjjrjjv~j}r(j]UlevelKj]j]rjGaUsourcejrj]j]UlineMGUtypej~ujMGjhj]rj)r}r(jX3Duplicate implicit target name: "booting via qspi".j}r(j]j]j]j]j]ujjj]rjX3Duplicate implicit target name: "booting via qspi".rr}r(jUjjubajjubaubjs~)r}r(jUjjujjrjjv~j}r(j]UlevelKj]j]rjzaUsourcejrj]j]UlineMNUtypej~ujMNjhj]rj)r}r(jX9Duplicate implicit target name: "preparing flash device".j}r(j]j]j]j]j]ujjj]rjX9Duplicate implicit target name: "preparing flash device".rr}r(jUjjubajjubaubjs~)r}r(jUjjjjrjjv~j}r(j]UlevelKj]j]rjaUsourcejrj]j]UlineMUtypej~ujMjhj]rj)r}r(jX3Duplicate implicit target name: "test application".j}r(j]j]j]j]j]ujjj]rjX3Duplicate implicit target name: "test application".rr}r(jUjjubajjubaubjs~)r}r(jUjjjjrjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineKUtypej~ujMjhj]rj)r}r(jX:Enumerated list start value not ordinal-1: "4" (ordinal 4)j}r(j]j]j]j]j]ujjj]rjX:Enumerated list start value not ordinal-1: "4" (ordinal 4)rr}r(jUjjubajjubaubjs~)r}r(jUjjƠjjrjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineKUtypej~ujM!jhj]rj)r}r(jX:Enumerated list start value not ordinal-1: "4" (ordinal 4)j}r(j]j]j]j]j]ujjj]rjX:Enumerated list start value not ordinal-1: "4" (ordinal 4)rr}r(jUjjubajjubaubjs~)r}r(jUjjƠjjrjjv~j}r(j]UlevelKj]j]Usourcejrj]j]UlineM$Utypej~ujM$jhj]rj)r}r(jXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.j}r(j]j]j]j]j]ujjj]rjXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rr}r(jUjjubajjubaubjs~)r}r(jUjjijjrjjv~j}r(j]UlevelKj]j]Usourcejrj]j]UlineMUtypejPujMjhj]rj)r}r(jXUnexpected indentation.j}r(j]j]j]j]j]ujjj]rjXUnexpected indentation.rr}r(jUjjubajjubaubjs~)r}r(jUjjijjrjjv~j}r(j]UlevelKj]j]Usourcejrj]j]UlineMUtypejx~ujNjhj]rj)r}r(jX;Block quote ends without a blank line; unexpected unindent.j}r(j]j]j]j]j]ujjj]r jX;Block quote ends without a blank line; unexpected unindent.r r }r (jUjjubajjubaubjs~)r }r(jUjjjjrjjv~j}r(j]UlevelKj]j]Usourcejrj]j]UlineMUtypejx~ujMjhj]rj)r}r(jX?Explicit markup ends without a blank line; unexpected unindent.j}r(j]j]j]j]j]ujj j]rjX?Explicit markup ends without a blank line; unexpected unindent.rr}r(jUjjubajjubaubjs~)r}r(jUjj8jjrjjv~j}r(j]UlevelKj]j]rj=aUsourcejrj]j]UlineMUtypej~ujMjhj]rj)r}r(jX.Duplicate implicit target name: "usage notes".j}r(j]j]j]j]j]ujjj]r jX.Duplicate implicit target name: "usage notes".r!r"}r#(jUjjubajjubaubjs~)r$}r%(jUjjjjrjjv~j}r&(j]UlevelKj]j]r'jaUsourcejrj]j]UlineMUtypej~ujMjhj]r(j)r)}r*(jX=Duplicate implicit target name: "debugging application boot".j}r+(j]j]j]j]j]ujj$j]r,jX=Duplicate implicit target name: "debugging application boot".r-r.}r/(jUjj)ubajjubaubjs~)r0}r1(jUjjjXkinternal padding after source/rtos/PDK_Platform_Software/Boot_Board_and_EVM_Abstractions/BOOT_AM57x.rst.incr2jjv~j}r3(j]UlevelKj]j]Usourcejrj]j]UlineMUtypejPujMjhj]r4(j)r5}r6(jX;Content block expected for the "raw" directive; none found.j}r7(j]j]j]j]j]ujj0j]r8jX;Content block expected for the "raw" directive; none found.r9r:}r;(jUjj5ubajjubj)r<}r=(jX.. raw:: html j}r>(j@jAj]j]j]j]j]ujj0j]r?jX.. raw:: html r@rA}rB(jUjj<ubajjubeubjs~)rC}rD(jUjjjjjjv~j}rE(j]UlevelKj]j]rFjģaUsourcejj]j]UlineKUtypej~ujKjhj]rGj)rH}rI(jX+Duplicate implicit target name: "overview".j}rJ(j]j]j]j]j]ujjCj]rKjX+Duplicate implicit target name: "overview".rLrM}rN(jUjjHubajjubaubjs~)rO}rP(jUjj6jjjjv~j}rQ(j]UlevelKj]j]rRj<aUsourcejj]j]UlineKnUtypej~ujKnjhj]rSj)rT}rU(jX-Duplicate implicit target name: "memory map".j}rV(j]j]j]j]j]ujjOj]rWjX-Duplicate implicit target name: "memory map".rXrY}rZ(jUjjTubajjubaubjs~)r[}r\(jUjjQjjjjv~j}r](j]UlevelKj]j]r^jWaUsourcejj]j]UlineKvUtypej~ujKvjhj]r_j)r`}ra(jX6Duplicate implicit target name: "directory structure".j}rb(j]j]j]j]j]ujj[j]rcjX6Duplicate implicit target name: "directory structure".rdre}rf(jUjj`ubajjubaubjs~)rg}rh(jUjj*jjjjv~j}ri(j]UlevelKj]j]Usourcejj]j]UlineMhUtypejx~ujMgjhj]rjj)rk}rl(jX;Bullet list ends without a blank line; unexpected unindent.j}rm(j]j]j]j]j]ujjgj]rnjX;Bullet list ends without a blank line; unexpected unindent.rorp}rq(jUjjkubajjubaubjs~)rr}rs(jUjj*jjjjv~j}rt(j]UlevelKj]j]Usourcejj]j]UlineMzUtypej~ujMzjhj]ruj)rv}rw(jXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.j}rx(j]j]j]j]j]ujjrj]ryjXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rzr{}r|(jUjjvubajjubaubjs~)r}}r~(jUjj*jjjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineMUtypejx~ujMjhj]rj)r}r(jX;Bullet list ends without a blank line; unexpected unindent.j}r(j]j]j]j]j]ujj}j]rjX;Bullet list ends without a blank line; unexpected unindent.rr}r(jUjjubajjubaubjs~)r}r(jUjj*jjjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineMUtypejx~ujMjhj]rj)r}r(jX;Bullet list ends without a blank line; unexpected unindent.j}r(j]j]j]j]j]ujjj]rjX;Bullet list ends without a blank line; unexpected unindent.rr}r(jUjjubajjubaubjs~)r}r(jUjj*jjjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineMUtypejx~ujMjhj]rj)r}r(jX=Literal block ends without a blank line; unexpected unindent.j}r(j]j]j]j]j]ujjj]rjX=Literal block ends without a blank line; unexpected unindent.rr}r(jUjjubajjubaubjs~)r}r(jUjj*jjjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineMUtypejx~ujMjhj]rj)r}r(jX;Bullet list ends without a blank line; unexpected unindent.j}r(j]j]j]j]j]ujjj]rjX;Bullet list ends without a blank line; unexpected unindent.rr}r(jUjjubajjubaubjs~)r}r(jUjj*jjjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineMUtypej~ujMjhj]rj)r}r(jXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.j}r(j]j]j]j]j]ujjj]rjXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rr}r(jUjjubajjubaubjs~)r}r(jUjj*jjjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineMUtypejx~ujMjhj]rj)r}r(jX=Literal block ends without a blank line; unexpected unindent.j}r(j]j]j]j]j]ujjj]rjX=Literal block ends without a blank line; unexpected unindent.rr}r(jUjjubajjubaubjs~)r}r(jUjj*jjjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineMUtypej~ujMjhj]rj)r}r(jXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.j}r(j]j]j]j]j]ujjj]rjXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rr}r(jUjjubajjubaubjs~)r}r(jUjj*jjjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineM_Utypejx~ujM^jhj]rj)r}r(jX;Bullet list ends without a blank line; unexpected unindent.j}r(j]j]j]j]j]ujjj]rjX;Bullet list ends without a blank line; unexpected unindent.rr}r(jUjjubajjubaubjs~)r}r(jUjjjjjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineMUtypej~ujMjhj]rj)r}r(jXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.j}r(j]j]j]j]j]ujjj]rjXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rr}r(jUjjubajjubaubjs~)r}r(jUjjjjjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineMUtypej~ujMjhj]rj)r}r(jXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.j}r(j]j]j]j]j]ujjj]rjXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rr}r(jUjjubajjubaubjs~)r}r(jUjjjjjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineMUtypej~ujMjhj]rj)r}r(jXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.j}r(j]j]j]j]j]ujjj]rjXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rr}r(jUjjubajjubaubjs~)r}r(jUjjjjjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineMUtypej~ujMjhj]rj)r}r(jXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.j}r(j]j]j]j]j]ujjj]rjXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rr}r(jUjjubajjubaubjs~)r}r(jUjjIjjjjv~j}r(j]UlevelKj]j]rjOaUsourcejj]j]UlineMUtypej~ujMjhj]rj)r}r(jX-Duplicate implicit target name: "boot modes".j}r(j]j]j]j]j]ujjj]r jX-Duplicate implicit target name: "boot modes".r r }r (jUjjubajjubaubjs~)r }r(jUjjjj}jjv~j}r(j]UlevelKj]j]rjaUsourcej}j]j]UlineKUtypej~ujKjhj]rj)r}r(jX+Duplicate implicit target name: "overview".j}r(j]j]j]j]j]ujj j]rjX+Duplicate implicit target name: "overview".rr}r(jUjjubajjubaubjs~)r}r(jUjjjj}jjv~j}r(j]UlevelKj]j]rjaUsourcej}j]j]UlineK6Utypej~ujK6jhj]rj)r}r(jX@Duplicate implicit target name: "bootloader execution sequence".j}r (j]j]j]j]j]ujjj]r!jX@Duplicate implicit target name: "bootloader execution sequence".r"r#}r$(jUjjubajjubaubjs~)r%}r&(jUjjjj}jjv~j}r'(j]UlevelKj]j]r(jaUsourcej}j]j]UlineKUtypej~ujKjhj]r)j)r*}r+(jX.Duplicate implicit target name: "compilation".j}r,(j]j]j]j]j]ujj%j]r-jX.Duplicate implicit target name: "compilation".r.r/}r0(jUjj*ubajjubaubjs~)r1}r2(jUjjjj}jjv~j}r3(j]UlevelKj]j]r4jƷaUsourcej}j]j]UlineKUtypej~ujKjhj]r5j)r6}r7(jX.Duplicate implicit target name: "compilation".j}r8(j]j]j]j]j]ujj1j]r9jX.Duplicate implicit target name: "compilation".r:r;}r<(jUjj6ubajjubaubjs~)r=}r>(jUjj׷jj}jjv~j}r?(j]UlevelKj]j]r@jܷaUsourcej}j]j]UlineKUtypej~ujKjhj]rAj)rB}rC(jX(Duplicate implicit target name: "usage".j}rD(j]j]j]j]j]ujj=j]rEjX(Duplicate implicit target name: "usage".rFrG}rH(jUjjBubajjubaubjs~)rI}rJ(jUjjrjj}jjv~j}rK(j]UlevelKj]j]rLjxaUsourcej}j]j]UlineKUtypej~ujKjhj]rMj)rN}rO(jX.Duplicate implicit target name: "compilation".j}rP(j]j]j]j]j]ujjIj]rQjX.Duplicate implicit target name: "compilation".rRrS}rT(jUjjNubajjubaubjs~)rU}rV(jUjjjj}jjv~j}rW(j]UlevelKj]j]rXjaUsourcej}j]j]UlineKUtypej~ujKjhj]rYj)rZ}r[(jX(Duplicate implicit target name: "usage".j}r\(j]j]j]j]j]ujjUj]r]jX(Duplicate implicit target name: "usage".r^r_}r`(jUjjZubajjubaubjs~)ra}rb(jUjjjj}jjv~j}rc(j]UlevelKj]j]rdjaUsourcej}j]j]UlineMUtypej~ujMjhj]rej)rf}rg(jX-Duplicate implicit target name: "boot modes".j}rh(j]j]j]j]j]ujjaj]rijX-Duplicate implicit target name: "boot modes".rjrk}rl(jUjjfubajjubaubjs~)rm}rn(jUjjںjj}jjv~j}ro(j]UlevelKj]j]rpjaUsourcej}j]j]UlineMUtypej~ujMjhj]rqj)rr}rs(jX.Duplicate implicit target name: "compilation".j}rt(j]j]j]j]j]ujjmj]rujX.Duplicate implicit target name: "compilation".rvrw}rx(jUjjrubajjubaubjs~)ry}rz(jUjjjj}jjv~j}r{(j]UlevelKj]j]r|jaUsourcej}j]j]UlineMUtypej~ujMjhj]r}j)r~}r(jX(Duplicate implicit target name: "usage".j}r(j]j]j]j]j]ujjyj]rjX(Duplicate implicit target name: "usage".rr}r(jUjj~ubajjubaubjs~)r}r(jUjjwjj}jjv~j}r(j]UlevelKj]j]rj}aUsourcej}j]j]UlineMUtypej~ujMjhj]rj)r}r(jX.Duplicate implicit target name: "compilation".j}r(j]j]j]j]j]ujjj]rjX.Duplicate implicit target name: "compilation".rr}r(jUjjubajjubaubjs~)r}r(jUjjjj}jjv~j}r(j]UlevelKj]j]rjaUsourcej}j]j]UlineMUtypej~ujMjhj]rj)r}r(jX(Duplicate implicit target name: "usage".j}r(j]j]j]j]j]ujjj]rjX(Duplicate implicit target name: "usage".rr}r(jUjjubajjubaubjs~)r}r(jUjjjj}jjv~j}r(j]UlevelKj]j]rj!aUsourcej}j]j]UlineMUtypej~ujMjhj]rj)r}r(jX.Duplicate implicit target name: "compilation".j}r(j]j]j]j]j]ujjj]rjX.Duplicate implicit target name: "compilation".rr}r(jUjjubajjubaubjs~)r}r(jUjj2jj}jjv~j}r(j]UlevelKj]j]rj8aUsourcej}j]j]UlineMUtypej~ujMjhj]rj)r}r(jX(Duplicate implicit target name: "usage".j}r(j]j]j]j]j]ujjj]rjX(Duplicate implicit target name: "usage".rr}r(jUjjubajjubaubjs~)r}r(jUjjټjj}jjv~j}r(j]UlevelKj]j]rj߼aUsourcej}j]j]UlineM2Utypej~ujM2jhj]rj)r}r(jX.Duplicate implicit target name: "compilation".j}r(j]j]j]j]j]ujjj]rjX.Duplicate implicit target name: "compilation".rr}r(jUjjubajjubaubjs~)r}r(jUjjjj}jjv~j}r(j]UlevelKj]j]rjaUsourcej}j]j]UlineMGUtypej~ujMGjhj]rj)r}r(jX(Duplicate implicit target name: "usage".j}r(j]j]j]j]j]ujjj]rjX(Duplicate implicit target name: "usage".rr}r(jUjjubajjubaubjs~)r}r(jUjjjj}jjv~j}r(j]UlevelKj]j]rjaUsourcej}j]j]UlineMUtypej~ujMjhj]rj)r}r(jX.Duplicate implicit target name: "compilation".j}r(j]j]j]j]j]ujjj]rjX.Duplicate implicit target name: "compilation".rr}r(jUjjubajjubaubjs~)r}r(jUjjؽjj}jjv~j}r(j]UlevelKj]j]rj޽aUsourcej}j]j]UlineMUtypej~ujMjhj]rj)r}r(jX(Duplicate implicit target name: "usage".j}r(j]j]j]j]j]ujjj]rjX(Duplicate implicit target name: "usage".rr}r(jUjjubajjubaubjs~)r}r(jUjjjXjinternal padding after source/rtos/PDK_Platform_Software/Boot_Board_and_EVM_Abstractions/BOOT_C66x.rst.incrjjv~j}r(j]UlevelKj]j]Usourcej}j]j]UlineMeUtypejPujMgjhj]r(j)r}r(jX;Content block expected for the "raw" directive; none found.j}r(j]j]j]j]j]ujjj]rjX;Content block expected for the "raw" directive; none found.rr}r(jUjjubajjubj)r}r(jX.. raw:: html j}r(j@jAj]j]j]j]j]ujjj]rjX.. raw:: html rr}r(jUjjubajjubeubjs~)r}r(jUjjbjj[jjv~j}r(j]UlevelKj]j]rjhaUsourcej[j]j]UlineKUtypej~ujKjhj]rj)r}r(jX+Duplicate implicit target name: "overview".j}r(j]j]j]j]j]ujjj]rjX+Duplicate implicit target name: "overview".rr}r(jUjjubajjubaubjs~)r}r(jUjjzjj[jjv~j}r(j]UlevelKj]j]rjaUsourcej[j]j]UlineK Utypej~ujK jhj]rj)r }r (jX@Duplicate implicit target name: "bootloader execution sequence".j}r (j]j]j]j]j]ujjj]r jX@Duplicate implicit target name: "bootloader execution sequence".r r}r(jUjj ubajjubaubjs~)r}r(jUjjjj[jjv~j}r(j]UlevelKj]j]rjaUsourcej[j]j]UlineKUtypej~ujKjhj]rj)r}r(jX;Duplicate implicit target name: "tools and binary formats".j}r(j]j]j]j]j]ujjj]rjX;Duplicate implicit target name: "tools and binary formats".rr}r(jUjjubajjubaubjs~)r}r(jUjjjj[jjv~j}r(j]UlevelKj]j]rjaUsourcej[j]j]UlineKmUtypej~ujKmjhj]r j)r!}r"(jX-Duplicate implicit target name: "boot modes".j}r#(j]j]j]j]j]ujjj]r$jX-Duplicate implicit target name: "boot modes".r%r&}r'(jUjj!ubajjubaubjs~)r(}r)(jUjjjj[jjv~j}r*(j]UlevelKj]j]r+j"aUsourcej[j]j]UlineKuUtypej~ujKujhj]r,j)r-}r.(jX8Duplicate implicit target name: "preparing the sd card".j}r/(j]j]j]j]j]ujj(j]r0jX8Duplicate implicit target name: "preparing the sd card".r1r2}r3(jUjj-ubajjubaubjs~)r4}r5(jUjj|jj[jjv~j}r6(j]UlevelKj]j]r7jaUsourcej[j]j]UlineKUtypej~ujKjhj]r8j)r9}r:(jX6Duplicate implicit target name: "booting via sd card".j}r;(j]j]j]j]j]ujj4j]r<jX6Duplicate implicit target name: "booting via sd card".r=r>}r?(jUjj9ubajjubaubjs~)r@}rA(jUjj|jj[jjv~j}rB(j]UlevelKj]j]Usourcej[j]j]UlineKUtypejx~ujKjhj]rCj)rD}rE(jX%Line block ends without a blank line.j}rF(j]j]j]j]j]ujj@j]rGjX%Line block ends without a blank line.rHrI}rJ(jUjjDubajjubaubjs~)rK}rL(jUjjjj[jjv~j}rM(j]UlevelKj]j]Usourcej[j]j]UlineKUtypejPujKjhj]rN(j)rO}rP(jX<Content block expected for the "note" directive; none found.j}rQ(j]j]j]j]j]ujjKj]rRjX<Content block expected for the "note" directive; none found.rSrT}rU(jUjjOubajjubj)rV}rW(jX .. note::rXj}rY(j@jAj]j]j]j]j]ujjKj]rZjX .. note::r[r\}r](jUjjVubajjubeubjs~)r^}r_(jUjjjj[jjv~j}r`(j]UlevelKj]j]Usourcej[j]j]UlineKUtypejx~ujKjhj]raj)rb}rc(jX?Explicit markup ends without a blank line; unexpected unindent.j}rd(j]j]j]j]j]ujj^j]rejX?Explicit markup ends without a blank line; unexpected unindent.rfrg}rh(jUjjbubajjubaubjs~)ri}rj(jUjjjj[jjv~j}rk(j]UlevelKj]j]rljaUsourcej[j]j]UlineKUtypej~ujKjhj]rmj)rn}ro(jX3Duplicate implicit target name: "booting via qspi".j}rp(j]j]j]j]j]ujjij]rqjX3Duplicate implicit target name: "booting via qspi".rrrs}rt(jUjjnubajjubaubjs~)ru}rv(jUjj)jXiinternal padding after source/rtos/PDK_Platform_Software/Boot_Board_and_EVM_Abstractions/BOOT_K2G.rst.incrwjjv~j}rx(j]UlevelKj]j]Usourcej[j]j]UlineKUtypejPujKjhj]ry(j)rz}r{(jX;Content block expected for the "raw" directive; none found.j}r|(j]j]j]j]j]ujjuj]r}jX;Content block expected for the "raw" directive; none found.r~r}r(jUjjzubajjubj)r}r(jX.. raw:: html j}r(j@jAj]j]j]j]j]ujjuj]rjX.. raw:: html rr}r(jUjjubajjubeubjs~)r}r(jUjjsjjljjv~j}r(j]UlevelKj]j]rjyaUsourcejlj]j]UlineKUtypej~ujKjhj]rj)r}r(jX+Duplicate implicit target name: "overview".j}r(j]j]j]j]j]ujjj]rjX+Duplicate implicit target name: "overview".rr}r(jUjjubajjubaubjs~)r}r(jUjjjjljjv~j}r(j]UlevelKj]j]rjaUsourcejlj]j]UlineKUtypej~ujKjhj]rj)r}r(jX:Duplicate implicit target name: "flashing the bootloader".j}r(j]j]j]j]j]ujjj]rjX:Duplicate implicit target name: "flashing the bootloader".rr}r(jUjjubajjubaubjs~)r}r(jUjjjjljjv~j}r(j]UlevelKj]j]rjaUsourcejlj]j]UlineKUtypej~ujKjhj]rj)r}r(jX(Duplicate implicit target name: "usage".j}r(j]j]j]j]j]ujjj]rjX(Duplicate implicit target name: "usage".rr}r(jUjjubajjubaubjs~)r}r(jUjjjjljjv~j}r(j]UlevelKj]j]rjaUsourcejlj]j]UlineK%Utypej~ujK%jhj]rj)r}r(jX.Duplicate implicit target name: "compilation".j}r(j]j]j]j]j]ujjj]rjX.Duplicate implicit target name: "compilation".rr}r(jUjjubajjubaubjs~)r}r(jUjjjjljjv~j}r(j]UlevelKj]j]rjaUsourcejlj]j]UlineKKUtypej~ujKKjhj]rj)r}r(jXODuplicate implicit target name: "making loadable user application image (app)".j}r(j]j]j]j]j]ujjj]rjXODuplicate implicit target name: "making loadable user application image (app)".rr}r(jUjjubajjubaubjs~)r}r(jUjjjjljjv~j}r(j]UlevelKj]j]Usourcejlj]j]UlineK\UtypejPujNjhj]r(j)r}r(jX]Error parsing content block for the "list-table" directive: exactly one bullet list expected.j}r(j]j]j]j]j]ujjj]rjX]Error parsing content block for the "list-table" directive: exactly one bullet list expected.rr}r(jUjjubajjubj)r}r(jX.. list-table:: Title :widths: 25 25 50 :header-rows: 2 * - Heading row 1, column 1 - Heading row 1, column 2 - Heading row 1, column 3 * - Row 1, column 1 - - Row 1, column 3 * - Row 2, column 1 - Row 2, column 2 - Row 2, column 3 j}r(j@jAj]j]j]j]j]ujjj]rjX.. list-table:: Title :widths: 25 25 50 :header-rows: 2 * - Heading row 1, column 1 - Heading row 1, column 2 - Heading row 1, column 3 * - Row 1, column 1 - - Row 1, column 3 * - Row 2, column 1 - Row 2, column 2 - Row 2, column 3 rr}r(jUjjubajjubeubjs~)r}r(jUjjjjljjv~j}r(j]UlevelKj]j]rjaUsourcejlj]j]UlineKUtypej~ujKjhj]rj)r}r(jX0Duplicate implicit target name: "flash writers".j}r(j]j]j]j]j]ujjj]rjX0Duplicate implicit target name: "flash writers".rr}r(jUjjubajjubaubjs~)r}r(jUjjjjljjv~j}r(j]UlevelKj]j]rjaUsourcejlj]j]UlineKUtypej~ujKjhj]rj)r}r(jX.Duplicate implicit target name: "compilation".j}r(j]j]j]j]j]ujjj]rjX.Duplicate implicit target name: "compilation".rr}r(jUjjubajjubaubjs~)r}r(jUjjjjljjv~j}r(j]UlevelKj]j]rjaUsourcejlj]j]UlineKUtypej~ujKjhj]rj)r}r(jX(Duplicate implicit target name: "usage".j}r(j]j]j]j]j]ujjj]rjX(Duplicate implicit target name: "usage".rr}r(jUjjubajjubaubjs~)r}r(jUjjKjXminternal padding after source/rtos/PDK_Platform_Software/Boot_Board_and_EVM_Abstractions/BOOT_K2H_E_L.rst.incrjjv~j}r(j]UlevelKj]j]Usourcejlj]j]UlineKUtypejPujKjhj]r(j)r}r(jX;Content block expected for the "raw" directive; none found.j}r(j]j]j]j]j]ujjj]rjX;Content block expected for the "raw" directive; none found.rr}r(jUjjubajjubj)r}r(jX.. raw:: html j}r(j@jAj]j]j]j]j]ujjj]r jX.. raw:: html r r }r (jUjjubajjubeubjs~)r }r(jUjjjj{jjv~j}r(j]UlevelKj]j]rjaUsourcej{j]j]UlineKUtypej~ujKjhj]rj)r}r(jX+Duplicate implicit target name: "overview".j}r(j]j]j]j]j]ujj j]rjX+Duplicate implicit target name: "overview".rr}r(jUjjubajjubaubjs~)r}r(jUjjjj{jjv~j}r(j]UlevelKj]j]rjaUsourcej{j]j]UlineKUtypej~ujKjhj]rj)r}r(jX@Duplicate implicit target name: "bootloader execution sequence".j}r (j]j]j]j]j]ujjj]r!jX@Duplicate implicit target name: "bootloader execution sequence".r"r#}r$(jUjjubajjubaubjs~)r%}r&(jUjj7jj{jjv~j}r'(j]UlevelKj]j]r(j=aUsourcej{j]j]UlineK-Utypej~ujK-jhj]r)j)r*}r+(jX;Duplicate implicit target name: "tools and binary formats".j}r,(j]j]j]j]j]ujj%j]r-jX;Duplicate implicit target name: "tools and binary formats".r.r/}r0(jUjj*ubajjubaubjs~)r1}r2(jUjjGjj{jjv~j}r3(j]UlevelKj]j]r4jLaUsourcej{j]j]UlineK0Utypej~ujK0jhj]r5j)r6}r7(jXBDuplicate implicit target name: "making bootable sbl image (mlo)".j}r8(j]j]j]j]j]ujj1j]r9jXBDuplicate implicit target name: "making bootable sbl image (mlo)".r:r;}r<(jUjj6ubajjubaubjs~)r=}r>(jUjjjj{jjv~j}r?(j]UlevelKj]j]r@jaUsourcej{j]j]UlineKVUtypej~ujKVjhj]rAj)rB}rC(jXODuplicate implicit target name: "making loadable user application image (app)".j}rD(j]j]j]j]j]ujj=j]rEjXODuplicate implicit target name: "making loadable user application image (app)".rFrG}rH(jUjjBubajjubaubjs~)rI}rJ(jUjjjj{jjv~j}rK(j]UlevelKj]j]rLjaUsourcej{j]j]UlineKuUtypej~ujKujhj]rMj)rN}rO(jX-Duplicate implicit target name: "boot modes".j}rP(j]j]j]j]j]ujjIj]rQjX-Duplicate implicit target name: "boot modes".rRrS}rT(jUjjNubajjubaubjs~)rU}rV(jUjj=jj{jjv~j}rW(j]UlevelKj]j]rXjBaUsourcej{j]j]UlineKUtypej~ujKjhj]rYj)rZ}r[(jX2Duplicate implicit target name: "mmcsd boot mode".j}r\(j]j]j]j]j]ujjUj]r]jX2Duplicate implicit target name: "mmcsd boot mode".r^r_}r`(jUjjZubajjubaubjs~)ra}rb(jUjjjj{jjv~j}rc(j]UlevelKj]j]rdjaUsourcej{j]j]UlineKUtypej~ujKjhj]rej)rf}rg(jX8Duplicate implicit target name: "preparing the sd card".j}rh(j]j]j]j]j]ujjaj]rijX8Duplicate implicit target name: "preparing the sd card".rjrk}rl(jUjjfubajjubaubjs~)rm}rn(jUjjjj{jjv~j}ro(j]UlevelKj]j]rpjaUsourcej{j]j]UlineMPUtypej~ujMPjhj]rqj)rr}rs(jX/Duplicate implicit target name: "memory usage".j}rt(j]j]j]j]j]ujjmj]rujX/Duplicate implicit target name: "memory usage".rvrw}rx(jUjjrubajjubaubjs~)ry}rz(jUjjjXninternal padding after source/rtos/PDK_Platform_Software/Boot_Board_and_EVM_Abstractions/BOOT_OMAPL13x.rst.incr{jjv~j}r|(j]UlevelKj]j]Usourcej{j]j]UlineMUtypejPujMjhj]r}(j)r~}r(jX;Content block expected for the "raw" directive; none found.j}r(j]j]j]j]j]ujjyj]rjX;Content block expected for the "raw" directive; none found.rr}r(jUjj~ubajjubj)r}r(jX.. raw:: html j}r(j@jAj]j]j]j]j]ujjyj]rjX.. raw:: html rr}r(jUjjubajjubeubjs~)r}r(jUjj6jXkinternal padding after source/rtos/PDK_Platform_Software/Boot_Board_and_EVM_Abstractions/Boot_Debug.rst.incrjjv~j}r(j]UlevelKj]j]UsourcejCj]j]UlineKUtypejPujKjhj]r(j)r}r(jX;Content block expected for the "raw" directive; none found.j}r(j]j]j]j]j]ujjj]rjX;Content block expected for the "raw" directive; none found.rr}r(jUjjubajjubj)r}r(jX.. raw:: html j}r(j@jAj]j]j]j]j]ujjj]rjX.. raw:: html rr}r(jUjjubajjubeubjs~)r}r(jUjjLjjOjjv~j}r(j]UlevelKj]j]rjUaUsourcejOj]j]UlineKUtypej~ujKjhj]rj)r}r(jX+Duplicate implicit target name: "overview".j}r(j]j]j]j]j]ujjj]rjX+Duplicate implicit target name: "overview".rr}r(jUjjubajjubaubjs~)r}r(jUjjjjOjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineKUtypej~ujKcjhj]rj)r}r(jX:Enumerated list start value not ordinal-1: "2" (ordinal 2)j}r(j]j]j]j]j]ujjj]rjX:Enumerated list start value not ordinal-1: "2" (ordinal 2)rr}r(jUjjubajjubaubjs~)r}r(jUjjjjOjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineKUtypej~ujKjhj]rj)r}r(jX:Enumerated list start value not ordinal-1: "5" (ordinal 5)j}r(j]j]j]j]j]ujjj]rjX:Enumerated list start value not ordinal-1: "5" (ordinal 5)rr}r(jUjjubajjubaubjs~)r}r(jUjjjjOjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineKUtypej~ujKjhj]rj)r}r(jX:Enumerated list start value not ordinal-1: "6" (ordinal 6)j}r(j]j]j]j]j]ujjj]rjX:Enumerated list start value not ordinal-1: "6" (ordinal 6)rr}r(jUjjubajjubaubjs~)r}r(jUjjjXointernal padding after source/rtos/PDK_Platform_Software/Boot_Board_and_EVM_Abstractions/UART_Apploader.rst.incrjjv~j}r(j]UlevelKj]j]UsourcejOj]j]UlineKUtypejPujKjhj]r(j)r}r(jX;Content block expected for the "raw" directive; none found.j}r(j]j]j]j]j]ujjj]rjX;Content block expected for the "raw" directive; none found.rr}r(jUjjubajjubj)r}r(jX.. raw:: html j}r(j@jAj]j]j]j]j]ujjj]rjX.. raw:: html rr}r(jUjjubajjubeubjs~)r}r(jUjjjX/internal padding after source/rtos/Boot.rst.incrjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineKrUtypejPujKsjhj]r(j)r}r(jX;Content block expected for the "raw" directive; none found.j}r(j]j]j]j]j]ujjj]rjX;Content block expected for the "raw" directive; none found.rr}r(jUjjubajjubj)r}r(jX.. raw:: html j}r(j@jAj]j]j]j]j]ujjj]rjX.. raw:: html rr}r(jUjjubajjubeubjs~)r}r(jUjj)r}r(jUjhjjjjj}r(j]j]j]j]rUmpmraj]rhaujKjhj]r(j)r}r(jXMPMrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXMPMrr}r(jjjjubaubj7)r}r(jX4http://processors.wiki.ti.com/index.php/MultiprocMgrjjjj:Xsource/rtos/MPM.rst.incrr}rbjj>j}r(j@jAj]j]j]j]j]ujKjhj]r jX4http://processors.wiki.ti.com/index.php/MultiprocMgrr r }r (jUjjubaubjhK)r }r(jX IntroductionrjKjjjjjjlKj}r(j]rUid130raj]j]rX introductionraj]j]ujNjhj]rjX Introductionrr}r(jjjj ubaubjc)r}r(jUjjjjjjfj}r(j]j]j]j]j]ujKjhj]r(ji)r}r(jXtThe Multiple Proc Manager (MPM) Package distributed with Processor SDK RTOS installer has multiple software modules.rjlKjjjjjjj}r (j]j]j]j]j]ujKjhj]r!jXtThe Multiple Proc Manager (MPM) Package distributed with Processor SDK RTOS installer has multiple software modules.r"r#}r$(jjjjubaubji)r%}r&(jX7Broadly the modules can be grouped into two categories:r'jlKjjjjjjj}r((j]j]j]j]j]ujKjhj]r)jX7Broadly the modules can be grouped into two categories:r*r+}r,(jj'jj%ubaubeubjt)r-}r.(jUjjjjjjwj}r/(jyX-j]j]j]j]j]ujK jhj]r0(j{)r1}r2(jXMulti Proc Manager Linux moduler3jj-jjjjj}r4(j]j]j]j]j]ujNjhj]r5j)r6}r7(jj3jj1jjjjj}r8(j]j]j]j]j]ujK j]r9jXMulti Proc Manager Linux moduler:r;}r<(jj3jj6ubaubaubj{)r=}r>(jXOModules that facilitate Interprocess communication between the multiple cores. jj-jjjjj}r?(j]j]j]j]j]ujNjhj]r@j)rA}rB(jXNModules that facilitate Interprocess communication between the multiple cores.rCjj=jjjjj}rD(j]j]j]j]j]ujK j]rEjXNModules that facilitate Interprocess communication between the multiple cores.rFrG}rH(jjCjjAubaubaubeubjhK)rI}rJ(jXMulti Proc Manager Linux modulerKjjjjjjlKj}rL(j]rMUmulti-proc-manager-linux-modulerNaj]j]j]j]rOjJaujNjhj]rPjXMulti Proc Manager Linux modulerQrR}rS(jjKjjIubaubj)rT}rU(jXThe Multi Proc Manager Linux module is used to load and run DSP images from ARM Linux user space. The download and run operations can be exercised by using user space API calls. MPM also provides a MPM Client Application which can be used to load and run DSP through command line.rVjjjjjjj}rW(j]j]j]j]j]ujKjhj]rXjXThe Multi Proc Manager Linux module is used to load and run DSP images from ARM Linux user space. The download and run operations can be exercised by using user space API calls. MPM also provides a MPM Client Application which can be used to load and run DSP through command line.rYrZ}r[(jjVjjTubaubjhK)r\}r](jX-Interprocessor Communication related packagesr^jjjjjjlKj}r_(j]r`U-interprocessor-communication-related-packagesraaj]j]j]j]rbhaujNjhj]rcjX-Interprocessor Communication related packagesrdre}rf(jj^jj\ubaubj)rg}rh(jXThe Multi Proc Manager package also includes couple of software modules that facilitates Inter processor communication between ARM running linux and DSP running RTOS. These components provide APIs in both ARM linux as well as on DSP RTOS.rijjjjjjj}rj(j]j]j]j]j]ujKjhj]rkjXThe Multi Proc Manager package also includes couple of software modules that facilitates Inter processor communication between ARM running linux and DSP running RTOS. These components provide APIs in both ARM linux as well as on DSP RTOS.rlrm}rn(jjijjgubaubjhK)ro}rp(jXMPM Mailbox modulerqjjjjjjlKj}rr(j]rsUmpm-mailbox-modulertaj]j]j]j]ruh^aujNjhj]rvjXMPM Mailbox modulerwrx}ry(jjqjjoubaubj)rz}r{(jXZMailbox is used for exchanging control messages between the host and individual DSP cores.r|jjjjjjj}r}(j]j]j]j]j]ujK!jhj]r~jXZMailbox is used for exchanging control messages between the host and individual DSP cores.rr}r(jj|jjzubaubjhK)r}r(jXMPM Sync modulerjjjjjjlKj}r(j]rUmpm-sync-moduleraj]j]j]j]rj9aujNjhj]rjXMPM Sync modulerr}r(jjjjubaubj)r}r(jX@Sync Module implements support for Multicore Barriers and Locks.rjjjjjjj}r(j]j]j]j]j]ujK'jhj]rjX@Sync Module implements support for Multicore Barriers and Locks.rr}r(jjjjubaubeubjX.internal padding after source/rtos/MPM.rst.incrjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineK)UtypejPujK*jhj]r(j)r}r(jX;Content block expected for the "raw" directive; none found.j}r(j]j]j]j]j]ujjj]rjX;Content block expected for the "raw" directive; none found.rr}r(jUjjubajjubj)r}r(jX.. raw:: html j}r(j@jAj]j]j]j]j]ujjj]rjX.. raw:: html rr}r(jUjjubajjubeubjs~)r}r(jUj}r(j]UlevelKj]j]rUid131raUsourcejj]j]UlineKUtypejx~ujjhK)r}r(jX IntroductionrjKjj)r}r(jUjhjjjjj}r(j]j]j]j]rUopenmpraj]rj_aujKjhj]r(j)r}r(jXOpenMPrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXOpenMPrr}r(jjjjubaubj7)r}r(jX7http://processors.wiki.ti.com/index.php/OpenMP_on_C6000jjjj:X"source/rtos/Compute/OpenMP.rst.incrr}rbjj>j}r(j@jAj]j]j]j]j]ujKjhj]rjX7http://processors.wiki.ti.com/index.php/OpenMP_on_C6000rr}r(jUjjubaubjj)r}r(jXAs of April 2016, this article is out of date. Please visit `here `__.jjjjjjj}r(j]j]j]j]j]ujKjhj]r(jX<As of April 2016, this article is out of date. Please visit rr}r(jX<As of April 2016, this article is out of date. Please visit jjubj)r}r(jXI`here `__j}r(UnameXherejX>http://downloads.ti.com/mctools/esd/docs/openmp-dsp/index.htmlj]j]j]j]j]ujjj]rjXhererr}r(jUjjubajjubjX.r}r(jX.jjubeubj)r}r(jXThis page is intended to be the starting point for all information about OpenMP on C6000. However, at this writing, that is not the case. The information in this article is correct if you are using C667x devices which only contain C66x CorePac DSPs, and not any ARM cores. If you are using a 66AK2H device, then please see `MCSDK HPC 3.x OpenMP `__. OpenMP is not supported on any other C6000 devices.jjjjjjj}r(j]j]j]j]j]ujK jhj]r(jXCThis page is intended to be the starting point for all information about OpenMP on C6000. However, at this writing, that is not the case. The information in this article is correct if you are using C667x devices which only contain C66x CorePac DSPs, and not any ARM cores. If you are using a 66AK2H device, then please see rr}r(jXCThis page is intended to be the starting point for all information about OpenMP on C6000. However, at this writing, that is not the case. The information in this article is correct if you are using C667x devices which only contain C66x CorePac DSPs, and not any ARM cores. If you are using a 66AK2H device, then please see jjubj)r}r(jXW`MCSDK HPC 3.x OpenMP `__j}r(UnameXMCSDK HPC 3.x OpenMPjX<http://processors.wiki.ti.com/index.php/MCSDK_HPC_3.x_OpenMPj]j]j]j]j]ujjj]rjXMCSDK HPC 3.x OpenMPrr}r(jUjjubajjubjX5. OpenMP is not supported on any other C6000 devices.rr}r(jX5. OpenMP is not supported on any other C6000 devices.jjubeubj)r}r(jXStill here? After reading this article, you will be able to execute your own OpenMP code on C6000 under control of Code Composer Studio.rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXStill here? After reading this article, you will be able to execute your own OpenMP code on C6000 under control of Code Composer Studio.rr}r(jjjjubaubjhK)r}r(jX PresumptionsrjjjjjjlKj}r(j]rU presumptionsraj]j]j]j]rh#aujNjhj]rjX Presumptionsrr}r(jjjjubaubjt)r}r(jUjjjjjjwj}r(jyX-j]j]j]j]j]ujKjhj]r(j{)r}r(jXdYou are experienced at programming OpenMP applications on hosted systems like Windows or Linux PC's.jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXdYou are experienced at programming OpenMP applications on hosted systems like Windows or Linux PC's.rjjjjjjj}r(j]j]j]j]j]ujKj]rjXdYou are experienced at programming OpenMP applications on hosted systems like Windows or Linux PC's.rr }r (jjjjubaubaubj{)r }r (jX[You have never programmed anything on an embedded system like those that use C6000 devices.jjjjjjj}r (j]j]j]j]j]ujNjhj]rj)r}r(jX[You have never programmed anything on an embedded system like those that use C6000 devices.rjj jjjjj}r(j]j]j]j]j]ujKj]rjX[You have never programmed anything on an embedded system like those that use C6000 devices.rr}r(jjjjubaubaubj{)r}r(jXQYou have never used any TI development tools such as Code Composer Studio (CCS). jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXPYou have never used any TI development tools such as Code Composer Studio (CCS).rjjjjjjj}r(j]j]j]j]j]ujKj]rjXPYou have never used any TI development tools such as Code Composer Studio (CCS).r r!}r"(jjjjubaubaubeubjhK)r#}r$(jXAcronyms Used in This Articler%jjjjjjlKj}r&(j]r'Uacronyms-used-in-this-articler(aj]j]j]j]r)h8aujNjhj]r*jXAcronyms Used in This Articler+r,}r-(jj%jj#ubaubjt)r.}r/(jUjjjjjjwj}r0(jyX-j]j]j]j]j]ujK!jhj]r1(j{)r2}r3(jXhCCS - Code Composer Studio. Software development environment for creating code to execute on TI devices.jj.jjjjj}r4(j]j]j]j]j]ujNjhj]r5j)r6}r7(jXhCCS - Code Composer Studio. Software development environment for creating code to execute on TI devices.r8jj2jjjjj}r9(j]j]j]j]j]ujK!j]r:jXhCCS - Code Composer Studio. Software development environment for creating code to execute on TI devices.r;r<}r=(jj8jj6ubaubaubj{)r>}r?(jXNSYS/BIOS - Or BIOS for short. Scalable real-time kernel which runs on the DSP.jj.jjjjj}r@(j]j]j]j]j]ujNjhj]rAj)rB}rC(jXNSYS/BIOS - Or BIOS for short. Scalable real-time kernel which runs on the DSP.rDjj>jjjjj}rE(j]j]j]j]j]ujK#j]rFjXNSYS/BIOS - Or BIOS for short. Scalable real-time kernel which runs on the DSP.rGrH}rI(jjDjjBubaubaubj{)rJ}rK(jXkMCSDK - Multicore Software Development Kit. Bundles all the software supplied by TI which runs on the DSP. jj.jjjjj}rL(j]j]j]j]j]ujNjhj]rMj)rN}rO(jXjMCSDK - Multicore Software Development Kit. Bundles all the software supplied by TI which runs on the DSP.rPjjJjjjjj}rQ(j]j]j]j]j]ujK%j]rRjXjMCSDK - Multicore Software Development Kit. Bundles all the software supplied by TI which runs on the DSP.rSrT}rU(jjPjjNubaubaubeubjhK)rV}rW(jXConceptual OverviewrXjjjjjjlKj}rY(j]rZUconceptual-overviewr[aj]j]j]j]r\haujNjhj]r]jXConceptual Overviewr^r_}r`(jjXjjVubaubj)ra}rb(jX|This section discusses, at a high level, how different pieces of software from TI work together to form the OpenMP solution.rcjjjjjjj}rd(j]j]j]j]j]ujK+jhj]rejX|This section discusses, at a high level, how different pieces of software from TI work together to form the OpenMP solution.rfrg}rh(jjcjjaubaubj)ri}rj(jXThe OpenMP source code, at the level of OpenMP pragmas and function calls, is the same. Your code must be organized into a *project*, as that term is defined by CCS. A central element of this project is the SYS/BIOS configuration. SYS/BIOS (or BIOS for short) is a scalable real-time kernel produced by TI. BIOS implements the multi-threading features of OpenMP. An initial BIOS configuration (*.cfg) is supplied. Changing this BIOS configuration may never be required. The build is done within CCS. At the start, system execution is also done within CCS. Besides BIOS, many other software components execute on the DSP to comprise the OpenMP solution. All of these components are delivered together under the name Multicore Software Development Kit (MCSDK).jjjjjjj}rk(j]j]j]j]j]ujK.jhj]rl(jX{The OpenMP source code, at the level of OpenMP pragmas and function calls, is the same. Your code must be organized into a rmrn}ro(jX{The OpenMP source code, at the level of OpenMP pragmas and function calls, is the same. Your code must be organized into a jjiubjM)rp}rq(jX *project*j}rr(j]j]j]j]j]ujjij]rsjXprojectrtru}rv(jUjjpubajjUubjX, as that term is defined by CCS. A central element of this project is the SYS/BIOS configuration. SYS/BIOS (or BIOS for short) is a scalable real-time kernel produced by TI. BIOS implements the multi-threading features of OpenMP. An initial BIOS configuration (rwrx}ry(jX, as that term is defined by CCS. A central element of this project is the SYS/BIOS configuration. SYS/BIOS (or BIOS for short) is a scalable real-time kernel produced by TI. BIOS implements the multi-threading features of OpenMP. An initial BIOS configuration (jjiubj )rz}r{(jX*j}r|(j]r}Uid133r~aj]j]j]j]UrefidUid132rujjij]rjX*r}r(jUjjzubajj ubjXk.cfg) is supplied. Changing this BIOS configuration may never be required. The build is done within CCS. At the start, system execution is also done within CCS. Besides BIOS, many other software components execute on the DSP to comprise the OpenMP solution. All of these components are delivered together under the name Multicore Software Development Kit (MCSDK).rr}r(jXk.cfg) is supplied. Changing this BIOS configuration may never be required. The build is done within CCS. At the start, system execution is also done within CCS. Besides BIOS, many other software components execute on the DSP to comprise the OpenMP solution. All of these components are delivered together under the name Multicore Software Development Kit (MCSDK).jjiubeubjhK)r}r(jX InstallationrjjjjjjlKj}r(j]rU installationraj]j]j]j]rj)aujNjhj]rjX Installationrr}r(jjjjubaubj)r}r(jXyGetting the MCSDK installed calls for you to install and configure everything else, so this section focuses on the MCSDK.rjjjjjjj}r(j]j]j]j]j]ujK=jhj]rjXyGetting the MCSDK installed calls for you to install and configure everything else, so this section focuses on the MCSDK.rr}r(jjjjubaubj)r}r(jXStart with the `general download page `__ for all flavors of the MCSDK. Follow the link for *SYS/BIOS MCSDK for C66x*. Get MCSDK version 2.1 or later. That page includes a link to a *Getting Started Guide*. That is where you will find directions on hardware setup, installing CCS, and so on. Follow all the steps in the Getting Started Guide, up to Running the Demonstration Application. (Actually, go ahead and run the Demo if you want. But it isn't required.)jjjjjjj}r(j]j]j]j]j]ujK@jhj]r(jXStart with the rr}r(jXStart with the jjubj)r}r(jXA`general download page `__j}r(UnameXgeneral download pagejX%http://www.ti.com/tool/bioslinuxmcsdkj]j]j]j]j]ujjj]rjXgeneral download pagerr}r(jUjjubajjubjX3 for all flavors of the MCSDK. Follow the link for rr}r(jX3 for all flavors of the MCSDK. Follow the link for jjubjM)r}r(jX*SYS/BIOS MCSDK for C66x*j}r(j]j]j]j]j]ujjj]rjXSYS/BIOS MCSDK for C66xrr}r(jUjjubajjUubjXA. Get MCSDK version 2.1 or later. That page includes a link to a rr}r(jXA. Get MCSDK version 2.1 or later. That page includes a link to a jjubjM)r}r(jX*Getting Started Guide*j}r(j]j]j]j]j]ujjj]rjXGetting Started Guiderr}r(jUjjubajjUubjX. That is where you will find directions on hardware setup, installing CCS, and so on. Follow all the steps in the Getting Started Guide, up to Running the Demonstration Application. (Actually, go ahead and run the Demo if you want. But it isn't required.)rr}r(jX. That is where you will find directions on hardware setup, installing CCS, and so on. Follow all the steps in the Getting Started Guide, up to Running the Demonstration Application. (Actually, go ahead and run the Demo if you want. But it isn't required.)jjubeubjhK)r}r(jXConfidence TestrjjjjjjlKj}r(j]rUconfidence-testraj]j]j]j]rjaujNjhj]rjXConfidence Testrr}r(jjjjubaubj)r}r(jXvIf you are familiar with CCS, you may skip over this section. But, installing and configuring all that software may leave you wondering if you did it all correctly. In this section, simplify things by pretending your system only has one core. This allows you to check whether you have installed most of the software correctly, while ignoring many of the complicated details.rjjjjjjj}r(j]j]j]j]j]ujKLjhj]rjXvIf you are familiar with CCS, you may skip over this section. But, installing and configuring all that software may leave you wondering if you did it all correctly. In this section, simplify things by pretending your system only has one core. This allows you to check whether you have installed most of the software correctly, while ignoring many of the complicated details.rr}r(jjjjubaubj)r}r(jX9Please check out `this set of Getting Started Guides `__ just for CCS. You only need to go through one of them. Choose the one that seems best for you. These guides provide a gentle introduction to those who are new to CCS.jjjjjjj}r(j]j]j]j]j]ujKSjhj]r(jXPlease check out rr}r(jXPlease check out jjubj)r}r(jX`this set of Getting Started Guides `__j}r(UnameX"this set of Getting Started GuidesjXXhttp://processors.wiki.ti.com/index.php/Category:Code_Composer_Studio_v5#Getting_Startedj]j]j]j]j]ujjj]rjX"this set of Getting Started Guidesrr}r(jUjjubajjubjX just for CCS. You only need to go through one of them. Choose the one that seems best for you. These guides provide a gentle introduction to those who are new to CCS.rr}r(jX just for CCS. You only need to go through one of them. Choose the one that seems best for you. These guides provide a gentle introduction to those who are new to CCS.jjubeubj)r}r(jX{When you load and run your first program, CCS needs to know which core to run it on. You see a dialog box similar this one:rjjjjjjj}r(j]j]j]j]j]ujKYjhj]rjX{When you load and run your first program, CCS needs to know which core to run it on. You see a dialog box similar this one:rr}r(jjjjubaubjR)r}r(jX%.. Image:: ../images/Select_core.JPG jjjjjjZj}r(UuriXrtos/../images/Select_core.JPGrj]j]j]j]jX}rU*jsj]ujK]jhj]ubj)r}r(jXCheck the box only for core 0.rjjjjjjj}r(j]j]j]j]j]ujK^jhj]rjXCheck the box only for core 0.rr}r(jjjjubaubjhK)r}r(jXFirst OpenMP ProjectrjjjjjjlKj}r(j]rUfirst-openmp-projectraj]j]j]j]rhaujNjhj]rjXFirst OpenMP Projectrr}r(jjjjubaubj)r}r(jXThis section walks through a simple hello world example project. Four threads run concurrently. Each thread prints hello world and the thread ID.rjjjjjjj}r(j]j]j]j]j]ujKcjhj]rjXThis section walks through a simple hello world example project. Four threads run concurrently. Each thread prints hello world and the thread ID.rr}r (jjjjubaubjhK)r }r (jXVersion and HW Informationr jjjjjjlKj}r (j]rUversion-and-hw-informationraj]j]j]j]rhaujNjhj]rjXVersion and HW Informationrr}r(jj jj ubaubj)r}r(jXThis section was developed with CCS version 5.2.0.00069, MCSDK version 2.1.0.3, and executed on an C6678 EVM. If your environment differs, you may have to make a few adjustments.rjjjjjjj}r(j]j]j]j]j]ujKjjhj]rjXThis section was developed with CCS version 5.2.0.00069, MCSDK version 2.1.0.3, and executed on an C6678 EVM. If your environment differs, you may have to make a few adjustments.rr}r(jjjjubaubjhK)r}r(jX Project SetuprjjjjjjlKj}r (j]r!U project-setupr"aj]j]j]j]r#haujNjhj]r$jX Project Setupr%r&}r'(jjjjubaubj)r(}r)(jXIn this section you create a new CCS project. This project is not written from scratch, but uses example source files that come with CCS.r*jjjjjjj}r+(j]j]j]j]j]ujKqjhj]r,jXIn this section you create a new CCS project. This project is not written from scratch, but uses example source files that come with CCS.r-r.}r/(jj*jj(ubaubj)r0}r1(jX;Put CCS in the Edit Perspective. Select: **Window \| Open Perspective \| Other \| CCS Edit**. To start this new project select: **Project \| New CCS Project**. Enter a **Project Name**. For **Family** select **C6000**. For **Variant**, ignore the first drop-down box, and in the second choose **Generic C66xx Device**. In the box just under **Project templates and examples** type in *hello*. Under *OMP Examples* you will see some *Hello world example* projects. Select the best one for your HW platform. In this screen shot, the selection is for C6678. Select **Next**.jjjjjjj}r2(j]j]j]j]j]ujKtjhj]r3(jX)Put CCS in the Edit Perspective. Select: r4r5}r6(jX)Put CCS in the Edit Perspective. Select: jj0ubj)r7}r8(jX3**Window \| Open Perspective \| Other \| CCS Edit**j}r9(j]j]j]j]j]ujj0j]r:jX,Window | Open Perspective | Other | CCS Editr;r<}r=(jUjj7ubajjubjX$. To start this new project select: r>r?}r@(jX$. To start this new project select: jj0ubj)rA}rB(jX**Project \| New CCS Project**j}rC(j]j]j]j]j]ujj0j]rDjXProject | New CCS ProjectrErF}rG(jUjjAubajjubjX . Enter a rHrI}rJ(jX . Enter a jj0ubj)rK}rL(jX**Project Name**j}rM(j]j]j]j]j]ujj0j]rNjX Project NamerOrP}rQ(jUjjKubajjubjX. For rRrS}rT(jX. For jj0ubj)rU}rV(jX **Family**j}rW(j]j]j]j]j]ujj0j]rXjXFamilyrYrZ}r[(jUjjUubajjubjX select r\r]}r^(jX select jj0ubj)r_}r`(jX **C6000**j}ra(j]j]j]j]j]ujj0j]rbjXC6000rcrd}re(jUjj_ubajjubjX. For rfrg}rh(jX. For jj0ubj)ri}rj(jX **Variant**j}rk(j]j]j]j]j]ujj0j]rljXVariantrmrn}ro(jUjjiubajjubjX;, ignore the first drop-down box, and in the second choose rprq}rr(jX;, ignore the first drop-down box, and in the second choose jj0ubj)rs}rt(jX**Generic C66xx Device**j}ru(j]j]j]j]j]ujj0j]rvjXGeneric C66xx Devicerwrx}ry(jUjjsubajjubjX. In the box just under rzr{}r|(jX. In the box just under jj0ubj)r}}r~(jX"**Project templates and examples**j}r(j]j]j]j]j]ujj0j]rjXProject templates and examplesrr}r(jUjj}ubajjubjX type in rr}r(jX type in jj0ubjM)r}r(jX*hello*j}r(j]j]j]j]j]ujj0j]rjXhellorr}r(jUjjubajjUubjX. Under rr}r(jX. Under jj0ubjM)r}r(jX*OMP Examples*j}r(j]j]j]j]j]ujj0j]rjX OMP Examplesrr}r(jUjjubajjUubjX you will see some rr}r(jX you will see some jj0ubjM)r}r(jX*Hello world example*j}r(j]j]j]j]j]ujj0j]rjXHello world examplerr}r(jUjjubajjUubjXm projects. Select the best one for your HW platform. In this screen shot, the selection is for C6678. Select rr}r(jXm projects. Select the best one for your HW platform. In this screen shot, the selection is for C6678. Select jj0ubj)r}r(jX**Next**j}r(j]j]j]j]j]ujj0j]rjXNextrr}r(jUjjubajjubjX.r}r(jX.jj0ubeubjR)r}r(jX... Image:: ../images/Omp_h1_project_setup.jpg jjjjjjZj}r(UuriX'rtos/../images/Omp_h1_project_setup.jpgrj]j]j]j]jX}rU*jsj]ujKjhj]ubj)r}r(jXdThe next dialog shows the RTSC Configuration Settings. If only one version of the MCSDK is installed, then nothing more is required. If more than one version of the MCSDK is installed, review the version numbers of the selected packages and insure they are from the desired MCSDK. Do not forget the drop-down box at the top for the version of the XDCtools.rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXdThe next dialog shows the RTSC Configuration Settings. If only one version of the MCSDK is installed, then nothing more is required. If more than one version of the MCSDK is installed, review the version numbers of the selected packages and insure they are from the desired MCSDK. Do not forget the drop-down box at the top for the version of the XDCtools.rr}r(jjjjubaubj)r}r(jX{Click **Finish**. CCS creates the project, complete with source code, and adds an entry to the **Project Explorer** window.jjjjjjj}r(j]j]j]j]j]ujKjhj]r(jXClick rr}r(jXClick jjubj)r}r(jX **Finish**j}r(j]j]j]j]j]ujjj]rjXFinishrr}r(jUjjubajjubjXO. CCS creates the project, complete with source code, and adds an entry to the rr}r(jXO. CCS creates the project, complete with source code, and adds an entry to the jjubj)r}r(jX**Project Explorer**j}r(j]j]j]j]j]ujjj]rjXProject Explorerrr}r(jUjjubajjubjX window.rr}r(jX window.jjubeubjhK)r}r(jXProject ModificationsrjjjjjjlKj}r(j]rUproject-modificationsraj]j]j]j]rhaujNjhj]rjXProject Modificationsrr}r(jjjjubaubj)r}r(jX4One modification to the example project is required.rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjX4One modification to the example project is required.rr}r(jjjjubaubj)r}r(jX3In the **Project Explorer** window, expand the set of files available under the new project. Open the file *omp_config.cfg* by double-clicking on it. The edit window has two tabs on the bottom left. Select the **Source** tab. Find the source line which begins *var OpenMP ...* Change the code as follows ...jjjjjjj}r(j]j]j]j]j]ujKjhj]r(jXIn the rr}r(jXIn the jjubj)r}r(jX**Project Explorer**j}r(j]j]j]j]j]ujjj]rjXProject Explorerrr}r(jUjjubajjubjXP window, expand the set of files available under the new project. Open the file rr}r(jXP window, expand the set of files available under the new project. Open the file jjubjM)r}r(jX*omp_config.cfg*j}r(j]j]j]j]j]ujjj]rjXomp_config.cfgrr}r(jUjjubajjUubjXW by double-clicking on it. The edit window has two tabs on the bottom left. Select the rr}r(jXW by double-clicking on it. The edit window has two tabs on the bottom left. Select the jjubj)r}r(jX **Source**j}r(j]j]j]j]j]ujjj]rjXSourcerr }r (jUjjubajjubjX( tab. Find the source line which begins r r }r (jX( tab. Find the source line which begins jjubjM)r}r(jX*var OpenMP ...*j}r(j]j]j]j]j]ujjj]rjXvar OpenMP ...rr}r(jUjjubajjUubjX Change the code as follows ...rr}r(jX Change the code as follows ...jjubeubj)r}r(jXvar OpenMP = xdc.useModule('ti.omp.utils.OpenMP'); // no change OpenMP.setNumProcessors(4); // no change OpenMP.autoDnldCore = false; // add this linejjjjjjj}r(j@jAj]j]j]j]j]ujMW2jhj]rjXvar OpenMP = xdc.useModule('ti.omp.utils.OpenMP'); // no change OpenMP.setNumProcessors(4); // no change OpenMP.autoDnldCore = false; // add this linerr}r(jUjjubaubj)r}r (jX{The new line disables the feature called auto-download. A side effect of auto-download is that printf works only on core 0.r!jjjjjjj}r"(j]j]j]j]j]ujKjhj]r#jX{The new line disables the feature called auto-download. A side effect of auto-download is that printf works only on core 0.r$r%}r&(jj!jjubaubj)r'}r((jX^Save the change to the configuration file by entering control+S or selecting **File \| Save**.jjjjjjj}r)(j]j]j]j]j]ujKjhj]r*(jXMSave the change to the configuration file by entering control+S or selecting r+r,}r-(jXMSave the change to the configuration file by entering control+S or selecting jj'ubj)r.}r/(jX**File \| Save**j}r0(j]j]j]j]j]ujj'j]r1jX File | Saver2r3}r4(jUjj.ubajjubjX.r5}r6(jX.jj'ubeubjhK)r7}r8(jXBuild and Loadr9jjjjjjlKj}r:(j]r;Ubuild-and-loadr<aj]j]j]j]r=haujNjhj]r>jXBuild and Loadr?r@}rA(jj9jj7ubaubj)rB}rC(jXThe target configuration that should launch when this OpenMP project is debugged is the same one used for previous single core projects. To check on this detail, choose **View \| Target Configurations**. Find that target configuration and insure it is the default.jjjjjjj}rD(j]j]j]j]j]ujKjhj]rE(jXThe target configuration that should launch when this OpenMP project is debugged is the same one used for previous single core projects. To check on this detail, choose rFrG}rH(jXThe target configuration that should launch when this OpenMP project is debugged is the same one used for previous single core projects. To check on this detail, choose jjBubj)rI}rJ(jX!**View \| Target Configurations**j}rK(j]j]j]j]j]ujjBj]rLjXView | Target ConfigurationsrMrN}rO(jUjjIubajjubjX>. Find that target configuration and insure it is the default.rPrQ}rR(jX>. Find that target configuration and insure it is the default.jjBubeubj)rS}rT(jXGIn the **Project Explorer** window, insure the new project is selected.rUjjjjjjj}rV(j]j]j]j]j]ujKjhj]rW(jXIn the rXrY}rZ(jXIn the jjSubj)r[}r\(jX**Project Explorer**j}r](j]j]j]j]j]ujjSj]r^jXProject Explorerr_r`}ra(jUjj[ubajjubjX, window, insure the new project is selected.rbrc}rd(jX, window, insure the new project is selected.jjSubeubj)re}rf(jXSelect the Debug icon.rgjjjjjjj}rh(j]j]j]j]j]ujKjhj]rijXSelect the Debug icon.rjrk}rl(jjgjjeubaubjR)rm}rn(jX+.. Image:: ../images/Omp_h2_debug_icon.JPG jjjjjjZj}ro(UuriX$rtos/../images/Omp_h2_debug_icon.JPGrpj]j]j]j]jX}rqU*jpsj]ujKjhj]ubj)rr}rs(jXNext a dialog will come up which asks which CPU cores to load the program on. Select cores 0-3, then click **OK**. It will appear similar to this ...jjjjjjj}rt(j]j]j]j]j]ujKjhj]ru(jXkNext a dialog will come up which asks which CPU cores to load the program on. Select cores 0-3, then click rvrw}rx(jXkNext a dialog will come up which asks which CPU cores to load the program on. Select cores 0-3, then click jjrubj)ry}rz(jX**OK**j}r{(j]j]j]j]j]ujjrj]r|jXOKr}r~}r(jUjjyubajjubjX$. It will appear similar to this ...rr}r(jX$. It will appear similar to this ...jjrubeubjR)r}r(jX-.. Image:: ../images/Omp_h3_select_cores.JPG jjjjjjZj}r(UuriX&rtos/../images/Omp_h3_select_cores.JPGrj]j]j]j]jX}rU*jsj]ujKjhj]ubj)r}r(jX/The following actions take place automatically:rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjX/The following actions take place automatically:rr}r(jjjjubaubjt)r}r(jUjjjjjjwj}r(jyX-j]j]j]j]j]ujKjhj]r(j{)r}r(jX$CCS changes to the Debug perspectiverjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujKj]rjX$CCS changes to the Debug perspectiverr}r(jjjjubaubaubj{)r}r(jXThe project is builtrjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujKj]rjXThe project is builtrr}r(jjjjubaubaubj{)r}r(jX$The target configuration is launchedrjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujKj]rjX$The target configuration is launchedrr}r(jjjjubaubaubj{)r}r(jXThe target connection is maderjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujKj]rjXThe target connection is maderr}r(jjjjubaubaubj{)r}r(jX"The program is loaded on cores 0-3rjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujKj]rjX"The program is loaded on cores 0-3rr}r(jjjjubaubaubj{)r}r(jXDThe system begins execution and runs to the start of main on core 0 jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXCThe system begins execution and runs to the start of main on core 0rjjjjjjj}r(j]j]j]j]j]ujKj]rjXCThe system begins execution and runs to the start of main on core 0rr}r(jjjjubaubaubeubjhK)r}r(jXExecute and See OutputrjjjjjjlKj}r(j]rUexecute-and-see-outputraj]j]j]j]rjaujNjhj]rjXExecute and See Outputrr}r(jjjjubaubj)r}r(jXSNow you are ready to execute. In the Debug window, click the Resume execution icon.rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXSNow you are ready to execute. In the Debug window, click the Resume execution icon.rr}r(jjjjubaubjR)r}r(jX,.. Image:: ../images/Omp_h4_resume_icon.JPG jjjjjjZj}r(UuriX%rtos/../images/Omp_h4_resume_icon.JPGrj]j]j]j]jX}rU*jsj]ujKjhj]ubj)r}r(jX^The console window will show output similar to, but not exactly the same as, the following ...rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjX^The console window will show output similar to, but not exactly the same as, the following ...rr}r(jjjjubaubj)r}r(jX[C66xx_0] Hello World from thread = 0 [C66xx_0] Number of threads = 4 [C66xx_1] Hello World from thread = 1 [C66xx_2] Hello World from thread = 2 [C66xx_3] Hello World from thread = 3jjjjjjj}r(j@jAj]j]j]j]j]ujM2jhj]rjX[C66xx_0] Hello World from thread = 0 [C66xx_0] Number of threads = 4 [C66xx_1] Hello World from thread = 1 [C66xx_2] Hello World from thread = 2 [C66xx_3] Hello World from thread = 3rr}r(jUjjubaubj)r}r(jXBecause the threads are executing on the cores concurrently, there is no control over the order in which the output appears. But you should see all of these lines.rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXBecause the threads are executing on the cores concurrently, there is no control over the order in which the output appears. But you should see all of these lines.rr }r (jjjjubaubjhK)r }r (jXTips on System Startupr jjjjjjlKj}r(j]rUtips-on-system-startupraj]j]j]j]rhaujNjhj]rjXTips on System Startuprr}r(jj jj ubaubj)r}r(jXIf things do not go smoothly, please see the article `SystemAnalyzerTutorial7 `__. That article is about running a tutorial for a tool named Unified Instrumentation Architecture (UIA). UIA is for analyzing system performance and behavior. This tutorial contains several tips on how to use CCS to run OpenMP programs. It is relevant to the versions of the MCSDK components listed near the beginning.jjjjjjj}r(j]j]j]j]j]ujKjhj]r(jX5If things do not go smoothly, please see the article rr}r(jX5If things do not go smoothly, please see the article jjubj)r}r(jX]`SystemAnalyzerTutorial7 `__j}r(UnameXSystemAnalyzerTutorial7jX?http://processors.wiki.ti.com/index.php/SystemAnalyzerTutorial7j]j]j]j]j]ujjj]r jXSystemAnalyzerTutorial7r!r"}r#(jUjjubajjubjX=. That article is about running a tutorial for a tool named Unified Instrumentation Architecture (UIA). UIA is for analyzing system performance and behavior. This tutorial contains several tips on how to use CCS to run OpenMP programs. It is relevant to the versions of the MCSDK components listed near the beginning.r$r%}r&(jX=. That article is about running a tutorial for a tool named Unified Instrumentation Architecture (UIA). UIA is for analyzing system performance and behavior. This tutorial contains several tips on how to use CCS to run OpenMP programs. It is relevant to the versions of the MCSDK components listed near the beginning.jjubeubjhK)r'}r((jXSecond OpenMP Projectr)jjjjjjlKj}r*(j]r+Usecond-openmp-projectr,aj]j]j]j]r-jaujNjhj]r.jXSecond OpenMP Projectr/r0}r1(jj)jj'ubaubj)r2}r3(jXNow try another project like hello world, but a bit more complicated. It will serve as the basis for your future OpenMP projects.r4jjjjjjj}r5(j]j]j]j]j]ujKjhj]r6jXNow try another project like hello world, but a bit more complicated. It will serve as the basis for your future OpenMP projects.r7r8}r9(jj4jj2ubaubjhK)r:}r;(jX Project Setupr<jjjjjjlKj}r=(j]r>Uproject-setup-1r?aj]j]j]j]r@jaujNjhj]rAjX Project SetuprBrC}rD(jj<jj:ubaubj)rE}rF(jXStart it the same way as the hello world project. But give it a different name, look for *matrix* among the examples, and choose the *OpenMP matrix vector multiplication example* for your system.jjjjjjj}rG(j]j]j]j]j]ujKjhj]rH(jXYStart it the same way as the hello world project. But give it a different name, look for rIrJ}rK(jXYStart it the same way as the hello world project. But give it a different name, look for jjEubjM)rL}rM(jX*matrix*j}rN(j]j]j]j]j]ujjEj]rOjXmatrixrPrQ}rR(jUjjLubajjUubjX$ among the examples, and choose the rSrT}rU(jX$ among the examples, and choose the jjEubjM)rV}rW(jX-*OpenMP matrix vector multiplication example*j}rX(j]j]j]j]j]ujjEj]rYjX+OpenMP matrix vector multiplication examplerZr[}r\(jUjjVubajjUubjX for your system.r]r^}r_(jX for your system.jjEubeubjR)r`}ra(jX-.. Image:: ../images/Omp_h5_matvec_setup.JPG jjjjjjZj}rb(UuriX&rtos/../images/Omp_h5_matvec_setup.JPGrcj]j]j]j]jX}rdU*jcsj]ujKjhj]ubjhK)re}rf(jXBuild and ExecutergjjjjjjlKj}rh(j]riUbuild-and-executerjaj]j]j]j]rkjaujNjhj]rljXBuild and Executermrn}ro(jjgjjeubaubj)rp}rq(jXEAll the remaining steps are the same as with the hello world project.rrjjjjjjj}rs(j]j]j]j]j]ujKjhj]rtjXEAll the remaining steps are the same as with the hello world project.rurv}rw(jjrjjpubaubj)rx}ry(jXIUpon executing, output in the console window should appear similar to ...rzjjjjjjj}r{(j]j]j]j]j]ujKjhj]r|jXIUpon executing, output in the console window should appear similar to ...r}r~}r(jjzjjxubaubj)r}r(jX9[C66xx_0] [C66xx_0] Starting values of matrix A and vector b: [C66xx_0] A[0]= 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 b[0]= 1.0 [C66xx_0] A[1]= 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 b[1]= 2.0 [C66xx_0] A[2]= 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 b[2]= 3.0 [C66xx_0] A[3]= 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 b[3]= 4.0 [C66xx_0] A[4]= 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 b[4]= 5.0 [C66xx_0] A[5]= 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 b[5]= 6.0 [C66xx_0] A[6]= 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 b[6]= 7.0 [C66xx_0] A[7]= 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 b[7]= 8.0 [C66xx_0] A[8]= 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 b[8]= 9.0 [C66xx_0] A[9]= 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 b[9]= 10.0 [C66xx_0] [C66xx_0] Results by thread/row: [C66xx_0] thread 0 did row 0 c[0]=55.00 Running total= 55.00 [C66xx_3] thread 3 did row 9 c[9]=550.00 Running total= 605.00 [C66xx_1] thread 1 did row 3 c[3]=220.00 Running total= 825.00 [C66xx_0] thread 0 did row 1 c[1]=110.00 Running total= 935.00 [C66xx_1] thread 1 did row 4 c[4]=275.00 Running total= 1210.00 [C66xx_2] thread 2 did row 6 c[6]=385.00 Running total= 1595.00 [C66xx_0] thread 0 did row 2 c[2]=165.00 Running total= 1760.00 [C66xx_1] thread 1 did row 5 c[5]=330.00 Running total= 2090.00 [C66xx_2] thread 2 did row 7 c[7]=440.00 Running total= 2530.00 [C66xx_2] thread 2 did row 8 c[8]=495.00 Running total= 3025.00 [C66xx_0] [C66xx_0] Matrix-vector total - sum of all c[] = 3025.00 [C66xx_0]jjjjjjj}r(j@jAj]j]j]j]j]ujM2jhj]rjX9[C66xx_0] [C66xx_0] Starting values of matrix A and vector b: [C66xx_0] A[0]= 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 b[0]= 1.0 [C66xx_0] A[1]= 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 b[1]= 2.0 [C66xx_0] A[2]= 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 b[2]= 3.0 [C66xx_0] A[3]= 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 b[3]= 4.0 [C66xx_0] A[4]= 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 b[4]= 5.0 [C66xx_0] A[5]= 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 b[5]= 6.0 [C66xx_0] A[6]= 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 b[6]= 7.0 [C66xx_0] A[7]= 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 b[7]= 8.0 [C66xx_0] A[8]= 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 b[8]= 9.0 [C66xx_0] A[9]= 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 b[9]= 10.0 [C66xx_0] [C66xx_0] Results by thread/row: [C66xx_0] thread 0 did row 0 c[0]=55.00 Running total= 55.00 [C66xx_3] thread 3 did row 9 c[9]=550.00 Running total= 605.00 [C66xx_1] thread 1 did row 3 c[3]=220.00 Running total= 825.00 [C66xx_0] thread 0 did row 1 c[1]=110.00 Running total= 935.00 [C66xx_1] thread 1 did row 4 c[4]=275.00 Running total= 1210.00 [C66xx_2] thread 2 did row 6 c[6]=385.00 Running total= 1595.00 [C66xx_0] thread 0 did row 2 c[2]=165.00 Running total= 1760.00 [C66xx_1] thread 1 did row 5 c[5]=330.00 Running total= 2090.00 [C66xx_2] thread 2 did row 7 c[7]=440.00 Running total= 2530.00 [C66xx_2] thread 2 did row 8 c[8]=495.00 Running total= 3025.00 [C66xx_0] [C66xx_0] Matrix-vector total - sum of all c[] = 3025.00 [C66xx_0]rr}r(jUjjubaubj)r}r(jXThe parts before and after *Results by thread/row* should match, particularly the final result of 3025.00. The *thread N* lines will vary, but there should be one line for each row 0-9.jjjjjjj}r(j]j]j]j]j]ujMjhj]r(jXThe parts before and after rr}r(jXThe parts before and after jjubjM)r}r(jX*Results by thread/row*j}r(j]j]j]j]j]ujjj]rjXResults by thread/rowrr}r(jUjjubajjUubjX= should match, particularly the final result of 3025.00. The rr}r(jX= should match, particularly the final result of 3025.00. The jjubjM)r}r(jX *thread N*j}r(j]j]j]j]j]ujjj]rjXthread Nrr}r(jUjjubajjUubjX@ lines will vary, but there should be one line for each row 0-9.rr}r(jX@ lines will vary, but there should be one line for each row 0-9.jjubeubjhK)r}r(jXStart Your OpenMP ProjectrjjjjjjlKj}r(j]rUstart-your-openmp-projectraj]j]j]j]rjiaujNjhj]rjXStart Your OpenMP Projectrr}r(jjjjubaubj)r}r(jXBuild your OpenMP project out of the matrix multiply project. In the **Project Explorer** window, select the matrix multiply project, right-click and choose **Copy**. Right-click again and choose **Paste**. Give the new project a name. It starts as a copy of the matrix multiply project in every respect, except the name. Remove files, add files, and make the project your own. Modifications to the omp_config.cfg file are not required for base functionality.jjjjjjj}r(j]j]j]j]j]ujMjhj]r(jXEBuild your OpenMP project out of the matrix multiply project. In the rr}r(jXEBuild your OpenMP project out of the matrix multiply project. In the jjubj)r}r(jX**Project Explorer**j}r(j]j]j]j]j]ujjj]rjXProject Explorerrr}r(jUjjubajjubjXD window, select the matrix multiply project, right-click and choose rr}r(jXD window, select the matrix multiply project, right-click and choose jjubj)r}r(jX**Copy**j}r(j]j]j]j]j]ujjj]rjXCopyrr}r(jUjjubajjubjX. Right-click again and choose rr}r(jX. Right-click again and choose jjubj)r}r(jX **Paste**j}r(j]j]j]j]j]ujjj]rjXPasterr}r(jUjjubajjubjX. Give the new project a name. It starts as a copy of the matrix multiply project in every respect, except the name. Remove files, add files, and make the project your own. Modifications to the omp_config.cfg file are not required for base functionality.rr}r(jX. Give the new project a name. It starts as a copy of the matrix multiply project in every respect, except the name. Remove files, add files, and make the project your own. Modifications to the omp_config.cfg file are not required for base functionality.jjubeubjhK)r}r(jXDebugging TipsrjjjjjjlKj}r(j]rUdebugging-tipsraj]j]j]j]rhaujNjhj]rjXDebugging Tipsrr}r(jjjjubaubj)r}r(jXSuppose you want to immediately execute one of those example projects again. You need to reset the CPU cores, reload the program, and run again. Here is a good way to do that.rjjjjjjj}r(j]j]j]j]j]ujM'jhj]rjXSuppose you want to immediately execute one of those example projects again. You need to reset the CPU cores, reload the program, and run again. Here is a good way to do that.rr}r(jjjjubaubj)r}r(jXTIn the **Debug** window, select cores 0-3, right-click and choose **Group Core(s)**.jjjjjjj}r(j]j]j]j]j]ujM+jhj]r(jXIn the rr}r(jXIn the jjubj)r}r(jX **Debug**j}r(j]j]j]j]j]ujjj]rjXDebugrr}r(jUjjubajjubjX2 window, select cores 0-3, right-click and choose rr}r(jX2 window, select cores 0-3, right-click and choose jjubj)r}r(jX**Group Core(s)**j}r(j]j]j]j]j]ujjj]rjX Group Core(s)rr}r(jUjjubajjubjX.r}r(jX.jjubeubjR)r}r(jX,.. Image:: ../images/Omp_h6_group_cores.JPG jjjjjjZj}r(UuriX%rtos/../images/Omp_h6_group_cores.JPGrj]j]j]j]jX}rU*jsj]ujM/jhj]ubj)r}r(jXNow reset the cores in the newly formed group. Select the group and click the **CPU Reset** icon near the top right of the **Debug** window.jjjjjjj}r(j]j]j]j]j]ujM0jhj]r(jXNNow reset the cores in the newly formed group. Select the group and click the rr }r (jXNNow reset the cores in the newly formed group. Select the group and click the jjubj)r }r (jX **CPU Reset**j}r (j]j]j]j]j]ujjj]rjX CPU Resetrr}r(jUjj ubajjubjX icon near the top right of the rr}r(jX icon near the top right of the jjubj)r}r(jX **Debug**j}r(j]j]j]j]j]ujjj]rjXDebugrr}r(jUjjubajjubjX window.rr}r(jX window.jjubeubj)r}r (jXCPU Reset iconr!jjjjjjj}r"(j]j]j]j]j]ujM3jhj]r#jXCPU Reset iconr$r%}r&(jj!jjubaubjR)r'}r((jX*.. Image:: ../images/Omp_h7_cpu_reset.JPG jjjjjjZj}r)(UuriX#rtos/../images/Omp_h7_cpu_reset.JPGr*j]j]j]j]jX}r+U*j*sj]ujM6jhj]ubj)r,}r-(jXThen reload the program with the menu selection **Run \| Load \| Reload Program**. Now you are ready to resume execution as before. Compare with the output you got last time, and see how some lines are in a different order.jjjjjjj}r.(j]j]j]j]j]ujM7jhj]r/(jX0Then reload the program with the menu selection r0r1}r2(jX0Then reload the program with the menu selection jj,ubj)r3}r4(jX!**Run \| Load \| Reload Program**j}r5(j]j]j]j]j]ujj,j]r6jXRun | Load | Reload Programr7r8}r9(jUjj3ubajjubjX. Now you are ready to resume execution as before. Compare with the output you got last time, and see how some lines are in a different order.r:r;}r<(jX. Now you are ready to resume execution as before. Compare with the output you got last time, and see how some lines are in a different order.jj,ubeubjhK)r=}r>(jXHow to Obtain Supportr?jjjjjjlKj}r@(j]rAUhow-to-obtain-supportrBaj]j]j]j]rCjaujNjhj]rDjXHow to Obtain SupportrErF}rG(jj?jj=ubaubj)rH}rI(jX)Post your questions and suspected bugs to the `compiler forum `__ with the tag ``openmp``. Please use the tag. Use of the tag triggers an e-mail to the current support team. Without the tag, the issue may go unnoticed for some time.jjjjjjj}rJ(j]j]j]j]j]ujM?jhj]rK(jX.Post your questions and suspected bugs to the rLrM}rN(jX.Post your questions and suspected bugs to the jjHubj)rO}rP(jXT`compiler forum `__j}rQ(UnameXcompiler forumjX?http://e2e.ti.com/support/development_tools/compiler/f/343.aspxj]j]j]j]j]ujjHj]rRjXcompiler forumrSrT}rU(jUjjOubajjubjX with the tag rVrW}rX(jX with the tag jjHubj)rY}rZ(jX ``openmp``j}r[(j]j]j]j]j]ujjHj]r\jXopenmpr]r^}r_(jUjjYubajjubjX. Please use the tag. Use of the tag triggers an e-mail to the current support team. Without the tag, the issue may go unnoticed for some time.r`ra}rb(jX. Please use the tag. Use of the tag triggers an e-mail to the current support team. Without the tag, the issue may go unnoticed for some time.jjHubeubeubjjjjlKj}rc(j]rdjaj]j]rejaj]j]ujNjhj]rfjX Introductionrgrh}ri(jjjjubaubj]rjj)rk}rl(jX/Duplicate explicit target name: "introduction".j}rm(j]j]j]j]j]ujjj]rnjX/Duplicate explicit target name: "introduction".rorp}rq(jUjjkubajjubajjv~ubjs~)rr}rs(jUjjjjjjv~j}rt(j]UlevelKj]rujaj]rvj~aUsourcejj]j]UlineK.Utypejx~ujK8jhj]rwj)rx}ry(jX0Inline emphasis start-string without end-string.j}rz(j]j]j]j]j]ujjrj]r{jX0Inline emphasis start-string without end-string.r|r}}r~(jUjjxubajjubaubjs~)r}r(jUjjjjjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineKUtypej~ujKjhj]rj)r}r(jXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.j}r(j]j]j]j]j]ujjj]rjXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rr}r(jUjjubajjubaubjs~)r}r(jUjjjX9internal padding after source/rtos/Compute/OpenMP.rst.incrjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineMEUtypejPujMGjhj]r(j)r}r(jX;Content block expected for the "raw" directive; none found.j}r(j]j]j]j]j]ujjj]rjX;Content block expected for the "raw" directive; none found.rr}r(jUjjubajjubj)r}r(jX.. raw:: html j}r(j@jAj]j]j]j]j]ujjj]rjX.. raw:: html rr}r(jUjjubajjubeubjs~)r}r(jUj}r(j]UlevelKj]j]rUid134raUsourcejj]j]UlineKUtypejx~ujjhK)r}r(jX IntroductionrjKjj)r}r(jUjhjjjjj}r(j]j]j]j]rUpktlibraj]rjaujKjhj]r(j)r}r(jXPKTLIBrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXPKTLIBrr}r(jjjjubaubj7)r}r(jXAhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_PKTLIBjjjj:X?source/rtos/PDK_Platform_Software/Device_Drivers/PKTLIB.rst.incrr}rbjj>j}r(j@jAj]j]j]j]j]ujKjhj]rjXAhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_PKTLIBrr}r(jUjjubaubjj)r}r(jXThe packet library (PKTLIB) provides higher layer of abstraction for underlying CPPI hardware descriptors to application layer. Functionalities include:rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXThe packet library (PKTLIB) provides higher layer of abstraction for underlying CPPI hardware descriptors to application layer. Functionalities include:rr}r(jjjjubaubjt)r}r(jUjjjjjjwj}r(jyX-j]j]j]j]j]ujK jhj]r(j{)r}r(jXZero copy operation for: - Packet split/merge operations - Cloning operations - Headroom/Tail room addition through merge operation jjjNjjj}r(j]j]j]j]j]ujNjhj]r(j)r}r(jXZero copy operation for:rjjjjjjj}r(j]j]j]j]j]ujK j]rjXZero copy operation for:rr}r(jjjjubaubjt)r}r(jUj}r(jyX-j]j]j]j]j]ujjj]r(j{)r}r(jXPacket split/merge operationsrj}r(j]j]j]j]j]ujjj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujK j]rjXPacket split/merge operationsrr}r(jjjjubaubajjubj{)r}r(jXCloning operationsrj}r(j]j]j]j]j]ujjj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujK j]rjXCloning operationsrr}r(jjjjubaubajjubj{)r}r(jX4Headroom/Tail room addition through merge operation j}r(j]j]j]j]j]ujjj]rj)r}r(jX3Headroom/Tail room addition through merge operationrjjjjjjj}r(j]j]j]j]j]ujKj]rjX3Headroom/Tail room addition through merge operationrr}r(jjjjubaubajjubejjwubeubj{)r}r(jX@Allocations of packet buffer and descriptors during startup timerjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujKj]rjX@Allocations of packet buffer and descriptors during startup timerr}r (jjjjubaubaubj{)r }r (jX-Allows packet allocation by HW at Rx CPPI DMAr jjjjjjj}r (j]j]j]j]j]ujNjhj]rj)r}r(jj jj jjjjj}r(j]j]j]j]j]ujKj]rjX-Allows packet allocation by HW at Rx CPPI DMArr}r(jj jjubaubaubj{)r}r(jXpEfficient recycling of data buffers including the case of buffers being referenced by multiple CPPI descriptors jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXoEfficient recycling of data buffers including the case of buffers being referenced by multiple CPPI descriptorsrjjjjjjj}r(j]j]j]j]j]ujKj]rjXoEfficient recycling of data buffers including the case of buffers being referenced by multiple CPPI descriptorsrr }r!(jjjjubaubaubeubjhK)r"}r#(jXModes of Operationr$jKjjjjjjlKj}r%(j]r&Uid135r'aj]j]r(Xmodes-of-operationr)aj]j]ujNjhj]r*jXModes of Operationr+r,}r-(jj$jj"ubaubj)r.}r/(jX>A pktlib heap can be created in on of the following two modes:r0jjjjjjj}r1(j]j]j]j]j]ujKjhj]r2jX>A pktlib heap can be created in on of the following two modes:r3r4}r5(jj0jj.ubaubjt)r6}r7(jUjjjjjjwj}r8(jyX-j]j]j]j]j]ujKjhj]r9(j{)r:}r;(jX<Private: only visible on the core where the heap was createdr<jj6jjjjj}r=(j]j]j]j]j]ujNjhj]r>j)r?}r@(jj<jj:jjjjj}rA(j]j]j]j]j]ujKj]rBjX<Private: only visible on the core where the heap was createdrCrD}rE(jj<jj?ubaubaubj{)rF}rG(jX&Shared: visible across multiple cores jj6jjjjj}rH(j]j]j]j]j]ujNjhj]rIj)rJ}rK(jX%Shared: visible across multiple coresrLjjFjjjjj}rM(j]j]j]j]j]ujKj]rNjX%Shared: visible across multiple coresrOrP}rQ(jjLjjJubaubaubeubjhK)rR}rS(jXDriver ConfigurationrTjjjjjjlKj}rU(j]rVUdriver-configuration-pktlibrWaj]j]j]j]rXhaujNjhj]rYjXDriver ConfigurationrZr[}r\(jjTjjRubaubj)r]}r^(jXApplications can use Pktlib_createHeap() API to create heap(s) in the system and heap properties are specified by the Pktlib_HeapCfg configuration structure. This configuration structure should be populated by the application and passed to the PKTLIB module when a heap is being created via the Pktlib_createHeap() API. Multiple heaps can exist in the system where each heaps properties are specified by the Pktlib_HeapCfg configuration structure.r_jjjjjjj}r`(j]j]j]j]j]ujK jhj]rajXApplications can use Pktlib_createHeap() API to create heap(s) in the system and heap properties are specified by the Pktlib_HeapCfg configuration structure. This configuration structure should be populated by the application and passed to the PKTLIB module when a heap is being created via the Pktlib_createHeap() API. Multiple heaps can exist in the system where each heaps properties are specified by the Pktlib_HeapCfg configuration structure.rbrc}rd(jj_jj]ubaubj)re}rf(jXFor details about individual fields of this structure, see the Doxygen help by opening /packages/ti/runtime/pktlib/docs/doxygen/html/index.html.rgjjjjjjj}rh(j]j]j]j]j]ujK(jhj]rijXFor details about individual fields of this structure, see the Doxygen help by opening /packages/ti/runtime/pktlib/docs/doxygen/html/index.html.rjrk}rl(jjgjjeubaubjhK)rm}rn(jX**APIs**rojKjjjjjjlKj}rp(j]rqUid136rraj]j]rsXapisrtaj]j]ujNjhj]ruj)rv}rw(jjoj}rx(j]j]j]j]j]ujjmj]ryjXAPIsrzr{}r|(jUjjvubajjubaubj)r}}r~(jX9API reference for application can be found in below file:rjjjjjjj}r(j]j]j]j]j]ujK/jhj]rjX9API reference for application can be found in below file:rr}r(jjjj}ubaubj)r}r(jX%#include jjjjjjj}r(j@jAj]j]j]j]j]ujM@3jhj]rjX%#include rr}r(jUjjubaubjhK)r}r(jXExamplerjKjjjjjjlKj}r(j]rUid137raj]j]rXexampleraj]j]ujNjhj]rjXExamplerr}r(jjjjubaubjy )r}r(jUjjjjjj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujjj]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXNamerjjjjjjj}r(j]j]j]j]j]ujK9j]rjXNamerr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX Descriptionrjjjjjjj}r(j]j]j]j]j]ujK9j]rjX Descriptionrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXExpected Resultsrjjjjjjj}r(j]j]j]j]j]ujK9j]rjXExpected Resultsrr}r(jjjjubaubajj ubejj ubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXpktlibUnitTest Applicationrjjjjjjj}r(j]j]j]j]j]ujK;j]rjXpktlibUnitTest Applicationrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rjc)r}r(jUj}r(j]j]j]j]j]ujjj]rji)r}r(jX&Unit Test application to test all APIsrjlKjjjjjjj}r(j]j]j]j]j]ujKj]rjX&Unit Test application to test all APIsrr}r(jjjjubaubajjfubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rjc)r}r(jUj}r(j]j]j]j]j]ujjj]rji)r}r(jX5User observes the output printed over the CCS consolerjlKjjjjjjj}r(j]j]j]j]j]ujKj]rjX5User observes the output printed over the CCS consolerr}r(jjjjubaubajjfubajj ubejj ubajj ubejj ubaubjhK)r }r (jXAdditional Referencesr jKjjjjjjlKj}r (j]r Uid138raj]j]rXadditional-referencesraj]j]ujNjhj]rjXAdditional Referencesrr}r(jj jj ubaubjy )r}r(jUjjjjjj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujjj]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthK#ujjj]jj ubj )r }r!(jUj}r"(j]j]j]j]j]UcolwidthK#ujjj]jj ubj )r#}r$(jUj}r%(j]j]j]j]j]ujjj]r&(j )r'}r((jUj}r)(j]j]j]j]j]ujj#j]r*(j )r+}r,(jUj}r-(j]j]j]j]j]ujj'j]r.j)r/}r0(jX **Document**r1jj+jjjjj}r2(j]j]j]j]j]ujKDj]r3j)r4}r5(jj1j}r6(j]j]j]j]j]ujj/j]r7jXDocumentr8r9}r:(jUjj4ubajjubaubajj ubj )r;}r<(jUj}r=(j]j]j]j]j]ujj'j]r>j)r?}r@(jX **Location**rAjj;jjjjj}rB(j]j]j]j]j]ujKDj]rCj)rD}rE(jjAj}rF(j]j]j]j]j]ujj?j]rGjXLocationrHrI}rJ(jUjjDubajjubaubajj ubejj ubj )rK}rL(jUj}rM(j]j]j]j]j]ujj#j]rN(j )rO}rP(jUj}rQ(j]j]j]j]j]ujjKj]rRj)rS}rT(jXAPI Reference ManualrUjjOjjjjj}rV(j]j]j]j]j]ujKFj]rWjXAPI Reference ManualrXrY}rZ(jjUjjSubaubajj ubj )r[}r\(jUj}r](j]j]j]j]j]ujjKj]r^j)r_}r`(jXO$(TI_PDK_INSTALL_DIR)/packages/ti /runtime/pktlib/docs/doxygen/html /index.htmlrajj[jjjjj}rb(j]j]j]j]j]ujKFj]rcjXO$(TI_PDK_INSTALL_DIR)/packages/ti /runtime/pktlib/docs/doxygen/html /index.htmlrdre}rf(jjajj_ubaubajj ubejj ubj )rg}rh(jUj}ri(j]j]j]j]j]ujj#j]rj(j )rk}rl(jUj}rm(j]j]j]j]j]ujjgj]rnj)ro}rp(jX Release Notesrqjjkjjjjj}rr(j]j]j]j]j]ujKJj]rsjX Release Notesrtru}rv(jjqjjoubaubajj ubj )rw}rx(jUj}ry(j]j]j]j]j]ujjgj]rzj)r{}r|(jXO$(TI_PDK_INSTALL_DIR)/packages/ti /runtime/pktlib/docs/ReleaseNotes _pktlib.pdfr}jjwjjjjj}r~(j]j]j]j]j]ujKJj]rjXO$(TI_PDK_INSTALL_DIR)/packages/ti /runtime/pktlib/docs/ReleaseNotes _pktlib.pdfrr}r(jj}jj{ubaubajj ubejj ubejj ubejj ubaubeubjjjjlKj}r(j]rjaj]j]rX introductionraj]j]ujNjhj]rjX Introductionrr}r(jjjjubaubj]rj)r}r(jX/Duplicate explicit target name: "introduction".j}r(j]j]j]j]j]ujjj]rjX/Duplicate explicit target name: "introduction".rr}r(jUjjubajjubajjv~ubjs~)r}r(jUj}r(j]UlevelKj]j]rjaUsourcejj]j]UlineKUtypej~ujjj]rj)r}r(jX*Duplicate implicit target name: "example".j}r(j]j]j]j]j]ujjj]rjX*Duplicate implicit target name: "example".rr}r(jUjjubajjubajjv~ubjs~)r}r(jUjjjXVinternal padding after source/rtos/PDK_Platform_Software/Device_Drivers/PKTLIB.rst.incrjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineKOUtypejPujKQjhj]r(j)r}r(jX;Content block expected for the "raw" directive; none found.j}r(j]j]j]j]j]ujjj]rjX;Content block expected for the "raw" directive; none found.rr}r(jUjjubajjubj)r}r(jX.. raw:: html j}r(j@jAj]j]j]j]j]ujjj]rjX.. raw:: html rr}r(jUjjubajjubeubjs~)r}r(jUjj)r}r(jUjKjj)r}r(jUjj)r}r(jUjhjjjjj}r(j]j]j]j]rUnetworkraj]rhaujKjhj]r(j)r}r(jXNetworkrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXNetworkrr}r(jjjjubaubjj)r}r(jUjjjjjjj}r(j]j]j]j]rUndkraj]rjaujKjhj]r(j)r}r(jXNDKrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXNDKrr}r(jjjjubaubj7)r}r(jX>http://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_NDKjjjj:XCsource/rtos/PDK_Platform_Software/Network_and_Transport/NDK.rst.incrr}rbjj>j}r(j@jAj]j]j]j]j]ujKjhj]rjX>http://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_NDKrr}r(jUjjubaubj)r}r(jUjjjjjjj}r(j]j]j]j]rU ndk-overviewraj]rhxaujKjhj]r(j)r}r(jX NDK Overviewrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjX NDK Overviewrr}r(jjjjubaubj)r}r(jX_The Network Development Kit (NDK) is a platform for development and demonstration of network enabled RTOS applications on TI processors and includes demonstration software showcasing capabilities across a range of network enabled applications. The NDK serves as a rapid prototype platform for the development of network and packet processing applications, or to add network connectivity to existing applications for communications, configuration, and control. Using the components provided in the NDK, developers can quickly move from development concepts to working implementations attached to the network.rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjX_The Network Development Kit (NDK) is a platform for development and demonstration of network enabled RTOS applications on TI processors and includes demonstration software showcasing capabilities across a range of network enabled applications. The NDK serves as a rapid prototype platform for the development of network and packet processing applications, or to add network connectivity to existing applications for communications, configuration, and control. Using the components provided in the NDK, developers can quickly move from development concepts to working implementations attached to the network.rr}r(jjjjubaubj)r}r(jXThe NDK provides an IPv6 and IPv4 compliant TCP/IP stack working with the TI-RTOS Kernel real-time operating system. Its primary focus is on providing the core Layer 3 and Layer 4 stack services along with additional higher-level network applications such as HTTP server and DHCP.rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXThe NDK provides an IPv6 and IPv4 compliant TCP/IP stack working with the TI-RTOS Kernel real-time operating system. Its primary focus is on providing the core Layer 3 and Layer 4 stack services along with additional higher-level network applications such as HTTP server and DHCP.rr}r(jjjjubaubj)r}r(jXThe NDK itself does not include any platform or device specific software. The NDK interfaces through well-defined transport interface, Network Interface Management UNIT(NIMU) to the PDK and platform software elements needed for operation. NIMU support. NIMU provides an interface between the stack and the device drivers through which the stack can talk to multiple instances of a single or various device drivers concurrently.rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXThe NDK itself does not include any platform or device specific software. The NDK interfaces through well-defined transport interface, Network Interface Management UNIT(NIMU) to the PDK and platform software elements needed for operation. NIMU support. NIMU provides an interface between the stack and the device drivers through which the stack can talk to multiple instances of a single or various device drivers concurrently.rr}r(jjjjubaubjy )r}r(jUjjjjjj j}r (j]j]j]j]j]ujNjhj]r j~ )r }r (jUj}r (j]j]j]j]j]UcolsKujjj]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthKujj j]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKGujj j]jj ubj )r}r(jUj}r(j]j]j]j]j]ujj j]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj )r}r(jUj}r(j]UmorecolsKj]j]j]j]ujjj]r j)r!}r"(jX#**Network Development Kit Summary**r#jjjjjjj}r$(j]j]j]j]j]ujKj]r%j)r&}r'(jj#j}r((j]j]j]j]j]ujj!j]r)jXNetwork Development Kit Summaryr*r+}r,(jUjj&ubajjubaubajj ubajj ubj )r-}r.(jUj}r/(j]j]j]j]j]ujjj]r0(j )r1}r2(jUj}r3(j]j]j]j]j]ujj-j]r4j)r5}r6(jX**Component Type**r7jj1jjjjj}r8(j]j]j]j]j]ujK!j]r9j)r:}r;(jj7j}r<(j]j]j]j]j]ujj5j]r=jXComponent Typer>r?}r@(jUjj:ubajjubaubajj ubj )rA}rB(jUj}rC(j]j]j]j]j]ujj-j]rDj)rE}rF(jXLibraryrGjjAjjjjj}rH(j]j]j]j]j]ujK!j]rIjXLibraryrJrK}rL(jjGjjEubaubajj ubejj ubj )rM}rN(jUj}rO(j]j]j]j]j]ujjj]rP(j )rQ}rR(jUj}rS(j]j]j]j]j]ujjMj]rTj)rU}rV(jX**Install Package**rWjjQjjjjj}rX(j]j]j]j]j]ujK#j]rYj)rZ}r[(jjWj}r\(j]j]j]j]j]ujjUj]r]jXInstall Packager^r_}r`(jUjjZubajjubaubajj ubj )ra}rb(jUj}rc(j]j]j]j]j]ujjMj]rdj)re}rf(jXNDKrgjjajjjjj}rh(j]j]j]j]j]ujK#j]rijXNDKrjrk}rl(jjgjjeubaubajj ubejj ubj )rm}rn(jUj}ro(j]j]j]j]j]ujjj]rp(j )rq}rr(jUj}rs(j]j]j]j]j]ujjmj]rtj)ru}rv(jX**Install Directory**rwjjqjjjjj}rx(j]j]j]j]j]ujK%j]ryj)rz}r{(jjwj}r|(j]j]j]j]j]ujjuj]r}jXInstall Directoryr~r}r(jUjjzubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjmj]rj)r}r(jXndk_\packages\ti\ndkjjjjjjj}r(j]j]j]j]j]ujK%j]rjXndk_packagestindkrr}r(jXndk_\packages\ti\ndkjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX**Project Type**rjjjjjjj}r(j]j]j]j]j]ujK'j]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX Project Typerr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX/`Eclipse RTSC `__rjjjjjjj}r(j]j]j]j]j]ujK'j]rj)r}r(jjj}r(UnameX Eclipse RTSCjXhttp://www.eclipse.org/rtsc/j]j]j]j]j]ujjj]rjX Eclipse RTSCrr}r(jUjjubajjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX**Endian Support**rjjjjjjj}r(j]j]j]j]j]ujK)j]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXEndian Supportrr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXLittlerjjjjjjj}r(j]j]j]j]j]ujK)j]rjXLittlerr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX**Library Name**rjjjjjjj}r(j]j]j]j]j]ujK+j]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX Library Namerr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXFor details of the libraries delivered as part of the NDK component, please refer to `[1] `__jjjjjjj}r(j]j]j]j]j]ujK+j]r(jXUFor details of the libraries delivered as part of the NDK component, please refer to rr}r(jXUFor details of the libraries delivered as part of the NDK component, please refer to jjubj)r}r(jX4`[1] `__j}r(UnameX[1]jX*http://www-s.ti.com/sc/techlit/spru523.pdfj]j]j]j]j]ujjj]rjX[1]rr}r(jUjjubajjubeubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX**Library Path**rjjjjjjj}r(j]j]j]j]j]ujK.j]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX Library Pathrr}r (jUjjubajjubaubajj ubj )r }r (jUj}r (j]j]j]j]j]ujjj]r j)r}r(jX"$(NDK_INSTALL_DIR)\packages\ti\ndkjj jjjjj}r(j]j]j]j]j]ujK.j]rjX$(NDK_INSTALL_DIR)packagestindkrr}r(jX"$(NDK_INSTALL_DIR)\packages\ti\ndkjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX**Include Paths**rjjjjjjj}r (j]j]j]j]j]ujK0j]r!j)r"}r#(jjj}r$(j]j]j]j]j]ujjj]r%jX Include Pathsr&r'}r((jUjj"ubajjubaubajj ubj )r)}r*(jUj}r+(j]j]j]j]j]ujjj]r,j)r-}r.(jXNDK_INSTALL_DIR is set automatically by CCS based on the version of NDK you have checked to build with. ${NDK_INSTALL_DIR}\packages\ti\ndk\inc ${NDK_INSTALL_DIR}\packages\ti\ndk\inc\toolsjj)jjjjj}r/(j]j]j]j]j]ujK0j]r0jXNDK_INSTALL_DIR is set automatically by CCS based on the version of NDK you have checked to build with. ${NDK_INSTALL_DIR}packagestindkinc ${NDK_INSTALL_DIR}packagestindkinctoolsr1r2}r3(jXNDK_INSTALL_DIR is set automatically by CCS based on the version of NDK you have checked to build with. ${NDK_INSTALL_DIR}\packages\ti\ndk\inc ${NDK_INSTALL_DIR}\packages\ti\ndk\inc\toolsjj-ubaubajj ubejj ubejj ubejj ubaubjc)r4}r5(jUjjjjjjfj}r6(j]j]j]j]j]ujK6jhj]r7ji)r8}r9(jUjlKjj4jjjjj}r:(j]j]j]j]j]ujKjhj]ubaubeubj)r;}r<(jUjjjjjjj}r=(j]j]j]j]r>Unimu-transportr?aj]r@jQaujK9jhj]rA(j)rB}rC(jXNIMU TransportrDjj;jjjjj}rE(j]j]j]j]j]ujK9jhj]rFjXNIMU TransportrGrH}rI(jjDjjBubaubj)rJ}rK(jXThe NDK transport component of the PDK currently provided 2 implementations for the NIMU layer as described in the sections below. The following diagram is a high level depiction of the NDK/NIMU architecture with reference to the NIMU implementations. For details for the NDK/NIMU architecture, please refer to NDK Programmer's Reference Guide `[2] `__jj;jjjjj}rL(j]j]j]j]j]ujK;jhj]rM(jXXThe NDK transport component of the PDK currently provided 2 implementations for the NIMU layer as described in the sections below. The following diagram is a high level depiction of the NDK/NIMU architecture with reference to the NIMU implementations. For details for the NDK/NIMU architecture, please refer to NDK Programmer's Reference Guide rNrO}rP(jXXThe NDK transport component of the PDK currently provided 2 implementations for the NIMU layer as described in the sections below. The following diagram is a high level depiction of the NDK/NIMU architecture with reference to the NIMU implementations. For details for the NDK/NIMU architecture, please refer to NDK Programmer's Reference Guide jjJubj)rQ}rR(jX4`[2] `__j}rS(UnameX[2]jX*http://www-s.ti.com/sc/techlit/spru524.pdfj]j]j]j]j]ujjJj]rTjX[2]rUrV}rW(jUjjQubajjubeubjR)rX}rY(jX".. Image:: ../images/NDK_ARCH.png jj;jjjjZj}rZ(UuriXrtos/../images/NDK_ARCH.pngr[j]j]j]j]jX}r\U*j[sj]ujKCjhj]ubeubj)r]}r^(jUjjjjjjj}r_(j]j]j]j]r`U nimu-for-cpswraaj]rbhZaujKEjhj]rc(j)rd}re(jX NIMU for CPSWrfjj]jjjjj}rg(j]j]j]j]j]ujKEjhj]rhjX NIMU for CPSWrirj}rk(jjfjjdubaubj)rl}rm(jXyNIMU for CPSW provides a common CPSW interface library for NDK to communicate with when network stack is being implemented in the TI's Common Platform Ethernet Switch for ethernet packet processing. The library uses the CSL-R based API interfaces to provide NIMU interface for NDK. This package has NDK unit test examples for all supported EVMS as indicated in the table above.rnjj]jjjjj}ro(j]j]j]j]j]ujKGjhj]rpjXyNIMU for CPSW provides a common CPSW interface library for NDK to communicate with when network stack is being implemented in the TI's Common Platform Ethernet Switch for ethernet packet processing. The library uses the CSL-R based API interfaces to provide NIMU interface for NDK. This package has NDK unit test examples for all supported EVMS as indicated in the table above.rqrr}rs(jjnjjlubaubj)rt}ru(jXgThis module is only intended to be used with NDK. As such, users should not tie up to its API directly.jj]jjjjj}rv(j]j]j]j]j]ujNjhj]rwj)rx}ry(jXgThis module is only intended to be used with NDK. As such, users should not tie up to its API directly.rzjjtjjjjj}r{(j]j]j]j]j]ujKPj]r|jXgThis module is only intended to be used with NDK. As such, users should not tie up to its API directly.r}r~}r(jjzjjxubaubaubjy )r}r(jUjj]jjjj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujjj]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKGujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj )r}r(jUj}r(j]UmorecolsKj]j]j]j]ujjj]rj)r}r(jX**NIMU for CPSW Summary**rjjjjjjj}r(j]j]j]j]j]ujKUj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXNIMU for CPSW Summaryrr}r(jUjjubajjubaubajj ubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX**Component Type**rjjjjjjj}r(j]j]j]j]j]ujKWj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXComponent Typerr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXLibraryrjjjjjjj}r(j]j]j]j]j]ujKWj]rjXLibraryrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX**Install Package**rjjjjjjj}r(j]j]j]j]j]ujKYj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXInstall Packagerr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXPDKrjjjjjjj}r(j]j]j]j]j]ujKYj]rjXPDKrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX**Install Directory**rjjjjjjj}r(j]j]j]j]j]ujK[j]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXInstall Directoryrr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX4$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimurjjjjjjj}r(j]j]j]j]j]ujK[j]rjX4$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimurr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r (j )r }r (jUj}r (j]j]j]j]j]ujjj]r j)r}r(jX**Project Type**rjj jjjjj}r(j]j]j]j]j]ujK]j]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX Project Typerr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX/`Eclipse RTSC `__r jjjjjjj}r!(j]j]j]j]j]ujK]j]r"j)r#}r$(jj j}r%(UnameX Eclipse RTSCjXhttp://www.eclipse.org/rtsc/j]j]j]j]j]ujjj]r&jX Eclipse RTSCr'r(}r)(jUjj#ubajjubaubajj ubejj ubj )r*}r+(jUj}r,(j]j]j]j]j]ujjj]r-(j )r.}r/(jUj}r0(j]j]j]j]j]ujj*j]r1j)r2}r3(jX**Endian Support**r4jj.jjjjj}r5(j]j]j]j]j]ujK_j]r6j)r7}r8(jj4j}r9(j]j]j]j]j]ujj2j]r:jXEndian Supportr;r<}r=(jUjj7ubajjubaubajj ubj )r>}r?(jUj}r@(j]j]j]j]j]ujj*j]rAj)rB}rC(jXLittlerDjj>jjjjj}rE(j]j]j]j]j]ujK_j]rFjXLittlerGrH}rI(jjDjjBubaubajj ubejj ubj )rJ}rK(jUj}rL(j]j]j]j]j]ujjj]rM(j )rN}rO(jUj}rP(j]j]j]j]j]ujjJj]rQj)rR}rS(jX**Library Path**rTjjNjjjjj}rU(j]j]j]j]j]ujKaj]rVj)rW}rX(jjTj}rY(j]j]j]j]j]ujjRj]rZjX Library Pathr[r\}r](jUjjWubajjubaubajj ubj )r^}r_(jUj}r`(j]j]j]j]j]ujjJj]raj)rb}rc(jX8$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu/librdjj^jjjjj}re(j]j]j]j]j]ujKaj]rfjX8$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu/librgrh}ri(jjdjjbubaubajj ubejj ubj )rj}rk(jUj}rl(j]j]j]j]j]ujjj]rm(j )rn}ro(jUj}rp(j]j]j]j]j]ujjjj]rqj)rr}rs(jX**Reference Guides**rtjjnjjjjj}ru(j]j]j]j]j]ujKcj]rvj)rw}rx(jjtj}ry(j]j]j]j]j]ujjrj]rzjXReference Guidesr{r|}r}(jUjjwubajjubaubajj ubj )r~}r(jUj}r(j]j]j]j]j]ujjjj]rj)r}r(jXNonerjj~jjjjj}r(j]j]j]j]j]ujKcj]rjXNonerr}r(jjjjubaubajj ubejj ubejj ubejj ubaubjc)r}r(jUjj]jjjjfj}r(j]j]j]j]j]ujKfjhj]rji)r}r(jUjlKjjjjjjj}r(j]j]j]j]j]ujKjhj]ubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rU nimu-for-icssraj]rhaujKijhj]r(j)r}r(jX NIMU for ICSSrjjjjjjj}r(j]j]j]j]j]ujKijhj]rjX NIMU for ICSSrr}r(jjjjubaubj)r}r(jXXNIMU for ICSS (PRU-ICSS is Programmable Real-Time Unit Industrial Communications Subsystem) provides a common PRU-ICSS interface library for NDK to communicate with when network stack is being implemented in the PRU-ICSS subsytem for ethernet packet processing (firmware based switch running on PRU's which are part of the ICSS). The library used the ICSS_EMAC LLD to provide NIMU interface for NDK. This package has NDK unit test examples for all supported Devices as indicated in the table above. For details of the PRU-ICSS, please refer to `ICCS-EMAC `__.jjjjjjj}r(j]j]j]j]j]ujKkjhj]r(jX NIMU for ICSS (PRU-ICSS is Programmable Real-Time Unit Industrial Communications Subsystem) provides a common PRU-ICSS interface library for NDK to communicate with when network stack is being implemented in the PRU-ICSS subsytem for ethernet packet processing (firmware based switch running on PRU's which are part of the ICSS). The library used the ICSS_EMAC LLD to provide NIMU interface for NDK. This package has NDK unit test examples for all supported Devices as indicated in the table above. For details of the PRU-ICSS, please refer to rr}r(jX NIMU for ICSS (PRU-ICSS is Programmable Real-Time Unit Industrial Communications Subsystem) provides a common PRU-ICSS interface library for NDK to communicate with when network stack is being implemented in the PRU-ICSS subsytem for ethernet packet processing (firmware based switch running on PRU's which are part of the ICSS). The library used the ICSS_EMAC LLD to provide NIMU interface for NDK. This package has NDK unit test examples for all supported Devices as indicated in the table above. For details of the PRU-ICSS, please refer to jjubj)r}r(jX7`ICCS-EMAC `__j}r(UnameX ICCS-EMACjX'/index.php/Processor_SDK_RTOS_ICSS-EMACj]j]j]j]j]ujjj]rjX ICCS-EMACrr}r(jUjjubajjubjX.r}r(jX.jjubeubjc)r}r(jUjjjjjjfj}r(j]j]j]j]j]ujKujhj]rji)r}r(jX**Note**: This module is only intended to be used with NDK and requires ICSS-EMAC low level driver. As such, users should not tie up to its API directly.jlKjjjjjjj}r(j]j]j]j]j]ujKwjhj]r(j)r}r(jX**Note**j}r(j]j]j]j]j]ujjj]rjXNoterr}r(jUjjubajjubjX: This module is only intended to be used with NDK and requires ICSS-EMAC low level driver. As such, users should not tie up to its API directly.rr}r(jX: This module is only intended to be used with NDK and requires ICSS-EMAC low level driver. As such, users should not tie up to its API directly.jjubeubaubjy )r}r(jUjjjjjj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujjj]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKGujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj )r}r(jUj}r(j]UmorecolsKj]j]j]j]ujjj]rj)r}r(jX**NIMU for ICSS Summary**rjjjjjjj}r(j]j]j]j]j]ujK{j]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXNIMU for ICSS Summaryrr}r(jUjjubajjubaubajj ubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX**Component Type**rjjjjjjj}r(j]j]j]j]j]ujK}j]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXComponent Typerr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXLibraryrjjjjjjj}r(j]j]j]j]j]ujK}j]rjXLibraryrr}r(jjjjubaubajj ubejj ubj )r}r (jUj}r (j]j]j]j]j]ujjj]r (j )r }r (jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX**Install Package**rjj jjjjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXInstall Packagerr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r }r!(jXPDKr"jjjjjjj}r#(j]j]j]j]j]ujKj]r$jXPDKr%r&}r'(jj"jj ubaubajj ubejj ubj )r(}r)(jUj}r*(j]j]j]j]j]ujjj]r+(j )r,}r-(jUj}r.(j]j]j]j]j]ujj(j]r/j)r0}r1(jX**Install Directory**r2jj,jjjjj}r3(j]j]j]j]j]ujKj]r4j)r5}r6(jj2j}r7(j]j]j]j]j]ujj0j]r8jXInstall Directoryr9r:}r;(jUjj5ubajjubaubajj ubj )r<}r=(jUj}r>(j]j]j]j]j]ujj(j]r?j)r@}rA(jX9$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu_icssrBjj<jjjjj}rC(j]j]j]j]j]ujKj]rDjX9$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu_icssrErF}rG(jjBjj@ubaubajj ubejj ubj )rH}rI(jUj}rJ(j]j]j]j]j]ujjj]rK(j )rL}rM(jUj}rN(j]j]j]j]j]ujjHj]rOj)rP}rQ(jX**Project Type**rRjjLjjjjj}rS(j]j]j]j]j]ujKj]rTj)rU}rV(jjRj}rW(j]j]j]j]j]ujjPj]rXjX Project TyperYrZ}r[(jUjjUubajjubaubajj ubj )r\}r](jUj}r^(j]j]j]j]j]ujjHj]r_j)r`}ra(jX/`Eclipse RTSC `__rbjj\jjjjj}rc(j]j]j]j]j]ujKj]rdj)re}rf(jjbj}rg(UnameX Eclipse RTSCjXhttp://www.eclipse.org/rtsc/j]j]j]j]j]ujj`j]rhjX Eclipse RTSCrirj}rk(jUjjeubajjubaubajj ubejj ubj )rl}rm(jUj}rn(j]j]j]j]j]ujjj]ro(j )rp}rq(jUj}rr(j]j]j]j]j]ujjlj]rsj)rt}ru(jX**Endian Support**rvjjpjjjjj}rw(j]j]j]j]j]ujKj]rxj)ry}rz(jjvj}r{(j]j]j]j]j]ujjtj]r|jXEndian Supportr}r~}r(jUjjyubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjlj]rj)r}r(jXLittlerjjjjjjj}r(j]j]j]j]j]ujKj]rjXLittlerr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX**Library Path**rjjjjjjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjX Library Pathrr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX=$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu_icss/librjjjjjjj}r(j]j]j]j]j]ujKj]rjX=$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu_icss/librr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX**Reference Guides**rjjjjjjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXReference Guidesrr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXNonerjjjjjjj}r(j]j]j]j]j]ujKj]rjXNonerr}r(jjjjubaubajj ubejj ubejj ubejj ubaubjc)r}r(jUjjjjjjfj}r(j]j]j]j]j]ujKjhj]rji)r}r(jUjlKjjjjjjj}r(j]j]j]j]j]ujKjhj]ubaubeubj)r}r(jUjKjjjjjjj}r(j]rjqRaj]j]j]rUid140raj]ujKjhj]r(j)r}r(jXExamplesrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXExamplesrr}r(jjjjubaubj)r}r(jUjjjjjjj}r(j]j]j]j]rU ping-exampleraj]rh/aujKjhj]r(j)r}r(jX PING Examplerjjjjjjj}r(j]j]j]j]j]ujKjhj]rjX PING Examplerr}r(jjjjubaubj)r}r(jXMAll NDK examples using CPSW interface can be found at the following location:rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXMAll NDK examples using CPSW interface can be found at the following location:rr}r(jjjjubaubjt)r}r(jUjjjjjjwj}r(jyX-j]j]j]j]j]ujKjhj]rj{)r}r(jX=$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu/example jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX<$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu/examplerjjjjjjj}r(j]j]j]j]j]ujKj]rjX<$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu/examplerr}r(jjjjubaubaubaubj)r }r (jXQAll NDK examples using PRU-ICSS interface can be found at the following location:r jjjjjjj}r (j]j]j]j]j]ujKjhj]r jXQAll NDK examples using PRU-ICSS interface can be found at the following location:rr}r(jj jj ubaubjt)r}r(jUjjjjjjwj}r(jyX-j]j]j]j]j]ujKjhj]rj{)r}r(jXB$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu_icss/example jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXA$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu_icss/examplerjjjjjjj}r(j]j]j]j]j]ujKj]rjXA$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu_icss/examplerr}r (jjjjubaubaubaubj)r!}r"(jUjjjjjjj}r#(j]j]j]j]r$Ubuilding-the-ndk-examplesr%aj]r&jaujKjhj]r'(j)r(}r)(jXBuilding the NDK examplesr*jj!jjjjj}r+(j]j]j]j]j]ujKjhj]r,jXBuilding the NDK examplesr-r.}r/(jj*jj(ubaubjc)r0}r1(jUjj!jjjjfj}r2(j]j]j]j]j]ujKjhj]r3(ji)r4}r5(jXRUse pdkProjectCreate.sh for Linux environment or pdkProjectCreate.bat for Windows.r6jlKjj0jjjjj}r7(j]j]j]j]j]ujKjhj]r8jXRUse pdkProjectCreate.sh for Linux environment or pdkProjectCreate.bat for Windows.r9r:}r;(jj6jj4ubaubji)r<}r=(jXThis can be found under the /packages folder. The only modification to these scripts, if any, is to update the CCS_INSTALL_PATH variable to point to CCS location if its not in the c:/ti/ccsv6 directory . Please refer to `Rebuilding PDK `__ for details of example project creation and how to run the example projects using CCS.jlKjj0jjjjj}r>(j]j]j]j]j]ujKjhj]r?(jXThis can be found under the /packages folder. The only modification to these scripts, if any, is to update the CCS_INSTALL_PATH variable to point to CCS location if its not in the c:/ti/ccsv6 directory . Please refer to r@rA}rB(jXThis can be found under the /packages folder. The only modification to these scripts, if any, is to update the CCS_INSTALL_PATH variable to point to CCS location if its not in the c:/ti/ccsv6 directory . Please refer to jj<ubj)rC}rD(jXP`Rebuilding PDK `__j}rE(UnameXRebuilding PDKjX;index_how_to_guides.html#rebuild-drivers-from-pdk-directoryj]j]j]j]j]ujj<j]rFjXRebuilding PDKrGrH}rI(jUjjCubajjubjXW for details of example project creation and how to run the example projects using CCS.rJrK}rL(jXW for details of example project creation and how to run the example projects using CCS.jj<ubeubeubeubj)rM}rN(jUjjjjjjj}rO(j]j]j]j]rPUndk-example-descriptionrQaj]rRjaujKjhj]rS(j)rT}rU(jXNDK Example DescriptionrVjjMjjjjj}rW(j]j]j]j]j]ujKjhj]rXjXNDK Example DescriptionrYrZ}r[(jjVjjTubaubj)r\}r](jXFor each EVM Type supported, there is a example which demonstates "ping" use case. Once the application is loaded via CCS and run, you will be able to ping the configured IP address as specificed int he examples config file. For example, the config file for NIMU for CPSW for idkAM572x, can be found in ti/transport/ndk/nimu/example/am572x/armv7/bios/nimu_idk.cfg. If you wish to re-configure the IP address of the CPSW interface you will need to modify the following configuration parametersr^jjMjjjjj}r_(j]j]j]j]j]ujKjhj]r`jXFor each EVM Type supported, there is a example which demonstates "ping" use case. Once the application is loaded via CCS and run, you will be able to ping the configured IP address as specificed int he examples config file. For example, the config file for NIMU for CPSW for idkAM572x, can be found in ti/transport/ndk/nimu/example/am572x/armv7/bios/nimu_idk.cfg. If you wish to re-configure the IP address of the CPSW interface you will need to modify the following configuration parametersrarb}rc(jj^jj\ubaubjt)rd}re(jUjjMjjjjwj}rf(jyX-j]j]j]j]j]ujKjhj]rg(j{)rh}ri(jXIp.address = "new ip address"rjjjdjjjjj}rk(j]j]j]j]j]ujNjhj]rlj)rm}rn(jjjjjhjjjjj}ro(j]j]j]j]j]ujKj]rpjXIp.address = "new ip address"rqrr}rs(jjjjjmubaubaubj{)rt}ru(jXIp.mask = "new ip mask"rvjjdjjjjj}rw(j]j]j]j]j]ujNjhj]rxj)ry}rz(jjvjjtjjjjj}r{(j]j]j]j]j]ujKj]r|jXIp.mask = "new ip mask"r}r~}r(jjvjjyubaubaubj{)r}r(jX'Ip.gatewayIpAddr = "new gatewayIpAddr" jjdjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX&Ip.gatewayIpAddr = "new gatewayIpAddr"rjjjjjjj}r(j]j]j]j]j]ujKj]rjX&Ip.gatewayIpAddr = "new gatewayIpAddr"rr}r(jjjjubaubaubeubjc)r}r(jUjjMjjjjfj}r(j]j]j]j]j]ujKjhj]rji)r}r(jXdIf you you do change these settings, you will be required to re-build the Example Project using CCS.rjlKjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXdIf you you do change these settings, you will be required to re-build the Example Project using CCS.rr}r(jjjjubaubaubjy )r}r(jUjjMjjjj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujjj]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthK ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXNamerjjjjjjj}r(j]j]j]j]j]ujKj]rjXNamerr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX Descriptionrjjjjjjj}r(j]j]j]j]j]ujKj]rjX Descriptionrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXEVM Configurationrjjjjjjj}r(j]j]j]j]j]ujKj]rjXEVM Configurationrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXExpected Resultsrjjjjjjj}r(j]j]j]j]j]ujKj]rjXExpected Resultsrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX SOC Supportedrjjjjjjj}r(j]j]j]j]j]ujKj]rjX SOC Supportedrr}r(jjjjubaubajj ubejj ubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX0NIMU_BasicExamp le_evmXXXX_exampleprojectrjjjjjjj}r(j]j]j]j]j]ujKj]rjX0NIMU_BasicExamp le_evmXXXX_exampleprojectrr}r(jjjjubaubajj ubj )r}r(jUj}r (j]j]j]j]j]ujjj]r j)r }r (jXOExample demonstrates ping from external source to Gigabit Ethernet port on EVM.r jjjjjjj}r(j]j]j]j]j]ujKj]rjXOExample demonstrates ping from external source to Gigabit Ethernet port on EVM.rr}r(jj jj ubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX?icev2AM335x: Jumpers J18 and J19 need to be set properly to select CPSW or ICSS mode. Pin2 and Pin3 need to be connected for ICSS mode and Pin1 and Pin2 for CPSW mode. Update \*.cfg file with static IP to test. NIMU for CPSW test requires connection of configured Ethernet port under test to external PC on same subnet.jjjjjjj}r(j]j]j]j]j]ujKj]rjX>icev2AM335x: Jumpers J18 and J19 need to be set properly to select CPSW or ICSS mode. Pin2 and Pin3 need to be connected for ICSS mode and Pin1 and Pin2 for CPSW mode. Update *.cfg file with static IP to test. NIMU for CPSW test requires connection of configured Ethernet port under test to external PC on same subnet.rr}r(jX?icev2AM335x: Jumpers J18 and J19 need to be set properly to select CPSW or ICSS mode. Pin2 and Pin3 need to be connected for ICSS mode and Pin1 and Pin2 for CPSW mode. Update \*.cfg file with static IP to test. NIMU for CPSW test requires connection of configured Ethernet port under test to external PC on same subnet.jjubaubajj ubj )r}r(jUj}r (j]j]j]j]j]ujjj]r!(j)r"}r#(jX.Run ping from any other PC in the same subnet,r$jjjjjjj}r%(j]j]j]j]j]ujKj]r&jX.Run ping from any other PC in the same subnet,r'r(}r)(jj$jj"ubaubj)r*}r+(jXDPing response from the EVM verifies successful execution of example.r,jjjjjjj}r-(j]j]j]j]j]ujKj]r.jXDPing response from the EVM verifies successful execution of example.r/r0}r1(jj,jj*ubaubejj ubj )r2}r3(jUj}r4(j]j]j]j]j]ujjj]r5j)r6}r7(jXAM335x AM437x AM57x K2Gr8jj2jjjjj}r9(j]j]j]j]j]ujKj]r:jXAM335x AM437x AM57x K2Gr;r<}r=(jj8jj6ubaubajj ubejj ubj )r>}r?(jUj}r@(j]j]j]j]j]ujjj]rA(j )rB}rC(jUj}rD(j]j]j]j]j]ujj>j]rEj)rF}rG(jX6NIMU_ICSS_Basic Example_evmXXXX _Examplep rojectrHjjBjjjjj}rI(j]j]j]j]j]ujKj]rJjX6NIMU_ICSS_Basic Example_evmXXXX _Examplep rojectrKrL}rM(jjHjjFubaubajj ubj )rN}rO(jUj}rP(j]j]j]j]j]ujj>j]rQj)rR}rS(jXPExample demonstrates ping from external source to PRU-ICSS Ethernet port on EVM.rTjjNjjjjj}rU(j]j]j]j]j]ujKj]rVjXPExample demonstrates ping from external source to PRU-ICSS Ethernet port on EVM.rWrX}rY(jjTjjRubaubajj ubj )rZ}r[(jUj}r\(j]j]j]j]j]ujj>j]r]j)r^}r_(jX?icev2AM335x: Jumpers J18 and J19 need to be set properly to select CPSW or ICSS mode. Pin2 and Pin3 need to be connected for ICSS mode and Pin1 and Pin2 for CPSW mode. Update \*.cfg file with static IP to test. NIMU for CPSW test requires connection of configured Ethernet port under test to external PC on same subnet.jjZjjjjj}r`(j]j]j]j]j]ujKj]rajX>icev2AM335x: Jumpers J18 and J19 need to be set properly to select CPSW or ICSS mode. Pin2 and Pin3 need to be connected for ICSS mode and Pin1 and Pin2 for CPSW mode. Update *.cfg file with static IP to test. NIMU for CPSW test requires connection of configured Ethernet port under test to external PC on same subnet.rbrc}rd(jX?icev2AM335x: Jumpers J18 and J19 need to be set properly to select CPSW or ICSS mode. Pin2 and Pin3 need to be connected for ICSS mode and Pin1 and Pin2 for CPSW mode. Update \*.cfg file with static IP to test. NIMU for CPSW test requires connection of configured Ethernet port under test to external PC on same subnet.jj^ubaubajj ubj )re}rf(jUj}rg(j]j]j]j]j]ujj>j]rh(j)ri}rj(jX.Run ping from any other PC in the same subnet.rkjjejjjjj}rl(j]j]j]j]j]ujKj]rmjX.Run ping from any other PC in the same subnet.rnro}rp(jjkjjiubaubj)rq}rr(jXDPing response from the EVM verifies successful execution of example.rsjjejjjjj}rt(j]j]j]j]j]ujKj]rujXDPing response from the EVM verifies successful execution of example.rvrw}rx(jjsjjqubaubejj ubj )ry}rz(jUj}r{(j]j]j]j]j]ujj>j]r|j)r}}r~(jXAMIC110 AM335x AM437x AM57x K2Grjjyjjjjj}r(j]j]j]j]j]ujKj]rjXAMIC110 AM335x AM437x AM57x K2Grr}r(jjjj}ubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXNIMU_Cpsw_ ExampleAppjjjjjjj}r(j]j]j]j]j]ujKj]r(j )r}r(jX NIMU_Cpsw_rj}r(j]rUid152raj]j]j]j]UrefidUid151rujjj]rjX NIMU_Cpsw_rr}r(jUjjubajj ubjX ExampleApprr}r(jX ExampleAppjjubeubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXOExample demonstrates ping from external source to Gigabit Ethernet port on EVM.rjjjjjjj}r(j]j]j]j]j]ujKj]rjXOExample demonstrates ping from external source to Gigabit Ethernet port on EVM.rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXUpdate \*.cfg file with static IP to test. NIMU for CPSW test requires connection of configured Ethernet port under test to external PC on same subnet.jjjjjjj}r(j]j]j]j]j]ujKj]rjXUpdate *.cfg file with static IP to test. NIMU for CPSW test requires connection of configured Ethernet port under test to external PC on same subnet.rr}r(jXUpdate \*.cfg file with static IP to test. NIMU for CPSW test requires connection of configured Ethernet port under test to external PC on same subnet.jjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j)r}r(jX.Run ping from any other PC in the same subnet.rjjjjjjj}r(j]j]j]j]j]ujKj]rjX.Run ping from any other PC in the same subnet.rr}r(jjjjubaubj)r}r(jXDPing response from the EVM verifies successful execution of example.rjjjjjjj}r(j]j]j]j]j]ujKj]rjXDPing response from the EVM verifies successful execution of example.rr}r(jjjjubaubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX AM65x J721Erjjjjjjj}r(j]j]j]j]j]ujKj]rjX AM65x J721Err}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXNIMU_Icssg ExampleApprjjjjjjj}r(j]j]j]j]j]ujMj]rjXNIMU_Icssg ExampleApprr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXPExample demonstrates ping from external source to PRU-ICSS Ethernet port on EVM.rjjjjjjj}r(j]j]j]j]j]ujMj]rjXPExample demonstrates ping from external source to PRU-ICSS Ethernet port on EVM.rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXUpdate \*.cfg file with static IP to test. NIMU for CPSW test requires connection of configured Ethernet port under test to external PC on same subnet.jjjjjjj}r(j]j]j]j]j]ujMj]rjXUpdate *.cfg file with static IP to test. NIMU for CPSW test requires connection of configured Ethernet port under test to external PC on same subnet.rr}r(jXUpdate \*.cfg file with static IP to test. NIMU for CPSW test requires connection of configured Ethernet port under test to external PC on same subnet.jjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j)r}r(jX.Run ping from any other PC in the same subnet.rjjjjjjj}r(j]j]j]j]j]ujMj]rjX.Run ping from any other PC in the same subnet.rr}r(jjjjubaubj)r }r (jXDPing response from the EVM verifies successful execution of example.r jjjjjjj}r (j]j]j]j]j]ujMj]r jXDPing response from the EVM verifies successful execution of example.rr}r(jj jj ubaubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXAM65xrjjjjjjj}r(j]j]j]j]j]ujMj]rjXAM65xrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r (j )r!}r"(jUj}r#(j]j]j]j]j]ujjj]r$j)r%}r&(jX7NIMU_BasicClient Example_evmXXXX _Example projectr'jj!jjjjj}r((j]j]j]j]j]ujMj]r)jX7NIMU_BasicClient Example_evmXXXX _Example projectr*r+}r,(jj'jj%ubaubajj ubj )r-}r.(jUj}r/(j]j]j]j]j]ujjj]r0j)r1}r2(jXKExample demonstrates creating local servers: TCP, UDP , data, null and OOB.r3jj-jjjjj}r4(j]j]j]j]j]ujMj]r5jXKExample demonstrates creating local servers: TCP, UDP , data, null and OOB.r6r7}r8(jj3jj1ubaubajj ubj )r9}r:(jUj}r;(j]j]j]j]j]ujjj]r<j)r=}r>(jX#Same as above. Use DHCP by default.r?jj9jjjjj}r@(j]j]j]j]j]ujMj]rAjX#Same as above. Use DHCP by default.rBrC}rD(jj?jj=ubaubajj ubj )rE}rF(jUj}rG(j]j]j]j]j]ujjj]rHj)rI}rJ(jXFSee TI NDK user guide, section 2 Example Applications for how to test.rKjjEjjjjj}rL(j]j]j]j]j]ujMj]rMjXFSee TI NDK user guide, section 2 Example Applications for how to test.rNrO}rP(jjKjjIubaubajj ubj )rQ}rR(jUj}rS(j]j]j]j]j]ujjj]rTj)rU}rV(jXAM57xrWjjQjjjjj}rX(j]j]j]j]j]ujMj]rYjXAM57xrZr[}r\(jjWjjUubaubajj ubejj ubj )r]}r^(jUj}r_(j]j]j]j]j]ujjj]r`(j )ra}rb(jUj}rc(j]j]j]j]j]ujj]j]rdj)re}rf(jX6NIMU_emacExample Client_evmXXXX _Example projectrgjjajjjjj}rh(j]j]j]j]j]ujMj]rijX6NIMU_emacExample Client_evmXXXX _Example projectrjrk}rl(jjgjjeubaubajj ubj )rm}rn(jUj}ro(j]j]j]j]j]ujj]j]rpj)rq}rr(jXKExample demonstrates creating local servers: TCP, UDP , data, null and OOB.rsjjmjjjjj}rt(j]j]j]j]j]ujMj]rujXKExample demonstrates creating local servers: TCP, UDP , data, null and OOB.rvrw}rx(jjsjjqubaubajj ubj )ry}rz(jUj}r{(j]j]j]j]j]ujj]j]r|j)r}}r~(jX#Same as above. Use DHCP by default.rjjyjjjjj}r(j]j]j]j]j]ujMj]rjX#Same as above. Use DHCP by default.rr}r(jjjj}ubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj]j]rj)r}r(jXFSee TI NDK user guide, section 2 Example Applications for how to test.rjjjjjjj}r(j]j]j]j]j]ujMj]rjXFSee TI NDK user guide, section 2 Example Applications for how to test.rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujj]j]rj)r}r(jXC665x C667x OMAP-L137/8rjjjjjjj}r(j]j]j]j]j]ujMj]rjXC665x C667x OMAP-L137/8rr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX;NIMU_BasicHello WorldExample_ evmXXXX_ Exampleprojectjjjjjjj}r(j]j]j]j]j]ujMj]r(jXNIMU_BasicHello rr}r(jXNIMU_BasicHello jjubj )r}r(jX WorldExample_rj}r(j]rUid154raj]j]j]j]UrefidUid153rujjj]rjX WorldExample_rr}r(jUjjubajj ubjX evmXXXX_ Exampleprojectrr}r(jX evmXXXX_ Exampleprojectjjubeubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX.Example demonstrates UDP helloworld echo test.rjjjjjjj}r(j]j]j]j]j]ujMj]rjX.Example demonstrates UDP helloworld echo test.rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX#Same as above. Use DHCP by default.rjjjjjjj}r(j]j]j]j]j]ujMj]rjX#Same as above. Use DHCP by default.rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXFSee TI NDK user guide, section 2 Example Applications for how to test.rjjjjjjj}r(j]j]j]j]j]ujMj]rjXFSee TI NDK user guide, section 2 Example Applications for how to test.rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXAM57xrjjjjjjj}r(j]j]j]j]j]ujMj]rjXAM57xrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX.NIMU_emacExample evmXXXX_ Exampleprojectrjjjjjjj}r(j]j]j]j]j]ujM%j]rjX.NIMU_emacExample evmXXXX_ Exampleprojectrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX.Example demonstrates UDP helloworld echo test.rjjjjjjj}r(j]j]j]j]j]ujM%j]rjX.Example demonstrates UDP helloworld echo test.rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r j)r }r (jX#Same as above. Use DHCP by default.r jjjjjjj}r (j]j]j]j]j]ujM%j]rjX#Same as above. Use DHCP by default.rr}r(jj jj ubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXFSee TI NDK user guide, section 2 Example Applications for how to test.rjjjjjjj}r(j]j]j]j]j]ujM%j]rjXFSee TI NDK user guide, section 2 Example Applications for how to test.rr}r(jjjjubaubajj ubj )r}r(jUj}r (j]j]j]j]j]ujjj]r!j)r"}r#(jX!C665x C667x K2H/K/E/L OMAP-L137/8r$jjjjjjj}r%(j]j]j]j]j]ujM%j]r&jX!C665x C667x K2H/K/E/L OMAP-L137/8r'r(}r)(jj$jj"ubaubajj ubejj ubj )r*}r+(jUj}r,(j]j]j]j]j]ujjj]r-(j )r.}r/(jUj}r0(j]j]j]j]j]ujj*j]r1j)r2}r3(jX3NIMU_DualMac Example_evmXXXX _Example projectr4jj.jjjjj}r5(j]j]j]j]j]ujM+j]r6jX3NIMU_DualMac Example_evmXXXX _Example projectr7r8}r9(jj4jj2ubaubajj ubj )r:}r;(jUj}r<(j]j]j]j]j]ujj*j]r=j)r>}r?(jXAExample demonstrates using two EMAC ports with different subnets.r@jj:jjjjj}rA(j]j]j]j]j]ujM+j]rBjXAExample demonstrates using two EMAC ports with different subnets.rCrD}rE(jj@jj>ubaubajj ubj )rF}rG(jUj}rH(j]j]j]j]j]ujj*j]rIj)rJ}rK(jX(Same as above. Use static IP by default.rLjjFjjjjj}rM(j]j]j]j]j]ujM+j]rNjX(Same as above. Use static IP by default.rOrP}rQ(jjLjjJubaubajj ubj )rR}rS(jUj}rT(j]j]j]j]j]ujj*j]rUj)rV}rW(jXsRun ping from any other PC in the same subnet. Ping response from the EVM verifies successful execution of example.rXjjRjjjjj}rY(j]j]j]j]j]ujM+j]rZjXsRun ping from any other PC in the same subnet. Ping response from the EVM verifies successful execution of example.r[r\}r](jjXjjVubaubajj ubj )r^}r_(jUj}r`(j]j]j]j]j]ujj*j]raj)rb}rc(jXAM57xrdjj^jjjjj}re(j]j]j]j]j]ujM+j]rfjXAM57xrgrh}ri(jjdjjbubaubajj ubejj ubj )rj}rk(jUj}rl(j]j]j]j]j]ujjj]rm(j )rn}ro(jUj}rp(j]j]j]j]j]ujjjj]rqj)rr}rs(jX.NIMU_FtpExample_ evmXXXX_ Exampleprojectjjnjjjjj}rt(j]j]j]j]j]ujM5j]ru(j )rv}rw(jXNIMU_FtpExample_rxj}ry(j]rzUid156r{aj]j]j]j]UrefidUid155r|ujjrj]r}jXNIMU_FtpExample_r~r}r(jUjjvubajj ubjX evmXXXX_ Exampleprojectrr}r(jX evmXXXX_ Exampleprojectjjrubeubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjjj]rj)r}r(jX1Example demonstrates FTP server with put and get.rjjjjjjj}r(j]j]j]j]j]ujM5j]rjX1Example demonstrates FTP server with put and get.rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjjj]rj)r}r(jX(Same as above. Use static IP by default.rjjjjjjj}r(j]j]j]j]j]ujM5j]rjX(Same as above. Use static IP by default.rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjjj]rj)r}r(jXFrom host PC make a FTP connection to EVM: ftp . User:user Password:password Test put and get command and show the throughput.rjjjjjjj}r(j]j]j]j]j]ujM5j]rjXFrom host PC make a FTP connection to EVM: ftp . User:user Password:password Test put and get command and show the throughput.rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjjj]rj)r}r(jXAM335x AM437x AM57x K2Grjjjjjjj}r(j]j]j]j]j]ujM5j]rjXAM335x AM437x AM57x K2Grr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX3NIMU_ICSS FtpExample_ evmXXXX_ Exampleprojectjjjjjjj}r(j]j]j]j]j]ujM?j]r(jX NIMU_ICSS rr}r(jX NIMU_ICSS jjubj )r}r(jX FtpExample_rj}r(j]rUid158raj]j]j]j]UrefidUid157rujjj]rjX FtpExample_rr}r(jUjjubajj ubjX evmXXXX_ Exampleprojectrr}r(jX evmXXXX_ Exampleprojectjjubeubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX1Example demonstrates FTP server with put and get.rjjjjjjj}r(j]j]j]j]j]ujM?j]rjX1Example demonstrates FTP server with put and get.rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX(Same as above. Use static IP by default.rjjjjjjj}r(j]j]j]j]j]ujM?j]rjX(Same as above. Use static IP by default.rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXFrom host PC make a FTP connection to EVM: ftp . User:user Password:password Test put and get command and show the throughput.rjjjjjjj}r(j]j]j]j]j]ujM?j]rjXFrom host PC make a FTP connection to EVM: ftp . User:user Password:password Test put and get command and show the throughput.rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXAM335x AM437x AM57x K2Grjjjjjjj}r(j]j]j]j]j]ujM?j]rjXAM335x AM437x AM57x K2Grr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r }r (jXNIMU_FtpCpsw_ ExampleAppjjjjjjj}r (j]j]j]j]j]ujMIj]r (j )r }r(jX NIMU_FtpCpsw_rj}r(j]rUid160raj]j]j]j]UrefidUid159rujj j]rjX NIMU_FtpCpsw_rr}r(jUjj ubajj ubjX ExampleApprr}r(jX ExampleAppjj ubeubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r (jX1Example demonstrates FTP server with put and get.r!jjjjjjj}r"(j]j]j]j]j]ujMIj]r#jX1Example demonstrates FTP server with put and get.r$r%}r&(jj!jjubaubajj ubj )r'}r((jUj}r)(j]j]j]j]j]ujjj]r*j)r+}r,(jX(Same as above. Use static IP by default.r-jj'jjjjj}r.(j]j]j]j]j]ujMIj]r/jX(Same as above. Use static IP by default.r0r1}r2(jj-jj+ubaubajj ubj )r3}r4(jUj}r5(j]j]j]j]j]ujjj]r6j)r7}r8(jXFrom host PC make a FTP connection to EVM: ftp . User:user Password:password Test put and get command and show the throughput.r9jj3jjjjj}r:(j]j]j]j]j]ujMIj]r;jXFrom host PC make a FTP connection to EVM: ftp . User:user Password:password Test put and get command and show the throughput.r<r=}r>(jj9jj7ubaubajj ubj )r?}r@(jUj}rA(j]j]j]j]j]ujjj]rBj)rC}rD(jXAM65x J7rEjj?jjjjj}rF(j]j]j]j]j]ujMIj]rGjXAM65x J7rHrI}rJ(jjEjjCubaubajj ubejj ubj )rK}rL(jUj}rM(j]j]j]j]j]ujjj]rN(j )rO}rP(jUj}rQ(j]j]j]j]j]ujjKj]rRj)rS}rT(jXNIMU_FtpIcssg_ ExampleAppjjOjjjjj}rU(j]j]j]j]j]ujMSj]rV(j )rW}rX(jXNIMU_FtpIcssg_rYj}rZ(j]r[Uid162r\aj]j]j]j]UrefidUid161r]ujjSj]r^jXNIMU_FtpIcssg_r_r`}ra(jUjjWubajj ubjX ExampleApprbrc}rd(jX ExampleAppjjSubeubajj ubj )re}rf(jUj}rg(j]j]j]j]j]ujjKj]rhj)ri}rj(jX1Example demonstrates FTP server with put and get.rkjjejjjjj}rl(j]j]j]j]j]ujMSj]rmjX1Example demonstrates FTP server with put and get.rnro}rp(jjkjjiubaubajj ubj )rq}rr(jUj}rs(j]j]j]j]j]ujjKj]rtj)ru}rv(jX(Same as above. Use static IP by default.rwjjqjjjjj}rx(j]j]j]j]j]ujMSj]ryjX(Same as above. Use static IP by default.rzr{}r|(jjwjjuubaubajj ubj )r}}r~(jUj}r(j]j]j]j]j]ujjKj]rj)r}r(jXFrom host PC make a FTP connection to EVM: ftp . User:user Password:password Test put and get command and show the throughput.rjj}jjjjj}r(j]j]j]j]j]ujMSj]rjXFrom host PC make a FTP connection to EVM: ftp . User:user Password:password Test put and get command and show the throughput.rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjKj]rj)r}r(jXAM65xrjjjjjjj}r(j]j]j]j]j]ujMSj]rjXAM65xrr}r(jjjjubaubajj ubejj ubejj ubejj ubaubj)r}r(jX.Note: Not all the test examples are supported on all the platforms. The NDK code is hardware agnostic, the NIMU driver however depends on the specific SOC. The NDK code can be ported to different platforms. Some Windows host test applications are available under ndk_3_xx_xx_xx\packages\ti\ndk\winapps.rjjMjjjjj}r(j]j]j]j]j]ujM_jhj]rjX*Note: Not all the test examples are supported on all the platforms. The NDK code is hardware agnostic, the NIMU driver however depends on the specific SOC. The NDK code can be ported to different platforms. Some Windows host test applications are available under ndk_3_xx_xx_xxpackagestindkwinapps.rr}r(jX.Note: Not all the test examples are supported on all the platforms. The NDK code is hardware agnostic, the NIMU driver however depends on the specific SOC. The NDK code can be ported to different platforms. Some Windows host test applications are available under ndk_3_xx_xx_xx\packages\ti\ndk\winapps.jjubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rU6running-ndk-example-on-arm-core-of-keystone-ii-devicesraj]rj0aujMcjhj]r(j)r}r(jX6Running NDK example on ARM core of Keystone II devicesrjjjjjjj}r(j]j]j]j]j]ujMcjhj]rjX6Running NDK example on ARM core of Keystone II devicesrr}r(jjjjubaubj)r}r(jXwBefore running the NDK example on ARM core of Keystone II devices(K2H/L/E/G), the following steps need to be performed.rjjjjjjj}r(j]j]j]j]j]ujMejhj]rjXwBefore running the NDK example on ARM core of Keystone II devices(K2H/L/E/G), the following steps need to be performed.rr}r(jjjjubaubjt)r}r(jUjjjjjjwj}r(jyX-j]j]j]j]j]ujMhjhj]rj{)r}r(jX?Increase the NS_BootTask stack from 2048 to 4096 in netctrl.c: jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX>Increase the NS_BootTask stack from 2048 to 4096 in netctrl.c:rjjjjjjj}r(j]j]j]j]j]ujMhj]rjX>Increase the NS_BootTask stack from 2048 to 4096 in netctrl.c:rr}r(jjjjubaubaubaubj)r}r(jXQTaskCreate( NS_BootTask, "ConfigBoot", OS_TASKPRINORM, 4096,(UINT32)hCfg, 0, 0 );jjjjjjj}r(j@jAj]j]j]j]j]ujM5jhj]rjXQTaskCreate( NS_BootTask, "ConfigBoot", OS_TASKPRINORM, 4096,(UINT32)hCfg, 0, 0 );rr}r(jUjjubaubjt)r}r(jUjjjjjjwj}r(jyX-j]j]j]j]j]ujMnjhj]r(j{)r}r(jXRebuild the NDKrjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujMnj]rjXRebuild the NDKrr}r(jjjjubaubaubj{)r}r(jXRebuild NIMU driver jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXRebuild NIMU driverrjjjjjjj}r(j]j]j]j]j]ujMoj]rjXRebuild NIMU driverrr}r(jjjjubaubaubeubjc)r}r(jUjjjjjjfj}r(j]j]j]j]j]ujMqjhj]rji)r}r(jUjlKjjjjjjj}r(j]j]j]j]j]ujKjhj]ubaubeubeubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rUcclink-exampleraj]rjaujMtjhj]r(j)r}r(jXCCLink Examplerjjjjjjj}r(j]j]j]j]j]ujMtjhj]rjXCCLink Examplerr}r(jjjjubaubj)r}r(jXRefer `Processor_SDK_RTOS_CCLINK `__ for details on steps for running cclink master and slave examples on NDK.jjjjjjj}r(j]j]j]j]j]ujMvjhj]r(jXRefer rr}r(jXRefer jjubj)r}r(jXI`Processor_SDK_RTOS_CCLINK `__j}r(UnameXProcessor_SDK_RTOS_CCLINKjX)index_Foundational_Components.html#cclinkj]j]j]j]j]ujjj]rjXProcessor_SDK_RTOS_CCLINKrr }r (jUjjubajjubjXJ for details on steps for running cclink master and slave examples on NDK.r r }r (jXJ for details on steps for running cclink master and slave examples on NDK.jjubeubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rUfaqraj]rh~aujM{jhj]r(j)r}r(jXFAQrjjjjjjj}r(j]j]j]j]j]ujM{jhj]rjXFAQrr}r(jjjjubaubj)r}r(jUjjjjjjj}r(j]j]j]j]r U8how-to-check-which-versions-of-nimu-driver-is-for-my-socr!aj]r"haujM~jhj]r#(j)r$}r%(jX9How to check which versions of NIMU driver is for my SOC?r&jjjjjjj}r'(j]j]j]j]j]ujM~jhj]r(jX9How to check which versions of NIMU driver is for my SOC?r)r*}r+(jj&jj$ubaubj)r,}r-(jX{There are several versions of NIMU driver for different SOCs. Please check packages\ti\transport\ndk\nimu\build\makefile.mkjjjjjjj}r.(j]j]j]j]j]ujMjhj]r/jXuThere are several versions of NIMU driver for different SOCs. Please check packagestitransportndknimubuildmakefile.mkr0r1}r2(jX{There are several versions of NIMU driver for different SOCs. Please check packages\ti\transport\ndk\nimu\build\makefile.mkjj,ubaubjt)r3}r4(jUjjjjjjwj}r5(jyX-j]j]j]j]j]ujMjhj]r6(j{)r7}r8(jX V0: C6657r9jj3jjjjj}r:(j]j]j]j]j]ujNjhj]r;j)r<}r=(jj9jj7jjjjj}r>(j]j]j]j]j]ujMj]r?jX V0: C6657r@rA}rB(jj9jj<ubaubaubj{)rC}rD(jX V1: C6678rEjj3jjjjj}rF(j]j]j]j]j]ujNjhj]rGj)rH}rI(jjEjjCjjjjj}rJ(j]j]j]j]j]ujMj]rKjX V1: C6678rLrM}rN(jjEjjHubaubaubj{)rO}rP(jX V2: K2H, K2KrQjj3jjjjj}rR(j]j]j]j]j]ujNjhj]rSj)rT}rU(jjQjjOjjjjj}rV(j]j]j]j]j]ujMj]rWjX V2: K2H, K2KrXrY}rZ(jjQjjTubaubaubj{)r[}r\(jX V3: K2L, K2Er]jj3jjjjj}r^(j]j]j]j]j]ujNjhj]r_j)r`}ra(jj]jj[jjjjj}rb(j]j]j]j]j]ujMj]rcjX V3: K2L, K2Erdre}rf(jj]jj`ubaubaubj{)rg}rh(jX"V4: AM572x, AM571x, AM437x, AM335xrijj3jjjjj}rj(j]j]j]j]j]ujNjhj]rkj)rl}rm(jjijjgjjjjj}rn(j]j]j]j]j]ujMj]rojX"V4: AM572x, AM571x, AM437x, AM335xrprq}rr(jjijjlubaubaubj{)rs}rt(jXV5: K2Grujj3jjjjj}rv(j]j]j]j]j]ujNjhj]rwj)rx}ry(jjujjsjjjjj}rz(j]j]j]j]j]ujMj]r{jXV5: K2Gr|r}}r~(jjujjxubaubaubj{)r}r(jXV6: OMAP-L137/138rjj3jjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujMj]rjXV6: OMAP-L137/138rr}r(jjjjubaubaubj{)r}r(jX V7: AM65x, J7rjj3jjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujMj]rjX V7: AM65x, J7rr}r(jjjjubaubaubeubjc)r}r(jUjjjjjjfj}r(j]j]j]j]j]ujMjhj]rji)r}r(jUjlKjjjjjjj}r(j]j]j]j]j]ujKjhj]ubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rU7is-there-any-multicast-streams-limitation-using-the-ndkraj]rhkaujMjhj]r(j)r}r(jX8Is there any multicast streams limitation using the NDK?rjjjjjjj}r(j]j]j]j]j]ujMjhj]rjX8Is there any multicast streams limitation using the NDK?rr}r(jjjjubaubj)r}r(jXIn the NDK, the limit is defined by a macro at ti/ndk/stack/igmp/igmp.c: #define IGMP_MAX_GROUP 32 It is then used to create an array of IGMP records: static IGMP_REC igmp[IGMP_MAX_GROUP]; The IGMP_MAX_GROUP value can be increased, then rebuild the NDK stack.rjjjjjjj}r(j]j]j]j]j]ujMjhj]rjXIn the NDK, the limit is defined by a macro at ti/ndk/stack/igmp/igmp.c: #define IGMP_MAX_GROUP 32 It is then used to create an array of IGMP records: static IGMP_REC igmp[IGMP_MAX_GROUP]; The IGMP_MAX_GROUP value can be increased, then rebuild the NDK stack.rr}r(jjjjubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rU)how-to-share-a-tcp-ip-socket-across-tasksraj]rh!aujMjhj]r(j)r}r(jX*How to share a TCP/IP socket across tasks?rjjjjjjj}r(j]j]j]j]j]ujMjhj]rjX*How to share a TCP/IP socket across tasks?rr}r(jjjjubaubj)r}r(jXThe basic building block of NDK stack code internally is an object handle. Internally to the stack, both sockets and pipes are addressed by object handles. However, at the application level, sockets and pipes are treated as file descriptors. To share a SOCKET, i.e. a file descriptor, a task must first allocate a file descriptor table by calling the function fdOpenSession(), then use the function fdShare() to share the file descriptor among multiple tasks. As described in NDK API reference guide, fdShare() is useful in a case where Task A opens a session and calls recv() in a loop on a socket. Task B has a loop that calls send() on the same socket. The call to send() from Task B will fail and then fdError() will return -1 if you do not call fdOpenSession() and then fdShare() from the second Task after the first Task has opened the socket. For an example that calls fdShare(), see the contest.c file in the /packages/ti/ndk/tools/console directory.rjjjjjjj}r(j]j]j]j]j]ujMjhj]rjXThe basic building block of NDK stack code internally is an object handle. Internally to the stack, both sockets and pipes are addressed by object handles. However, at the application level, sockets and pipes are treated as file descriptors. To share a SOCKET, i.e. a file descriptor, a task must first allocate a file descriptor table by calling the function fdOpenSession(), then use the function fdShare() to share the file descriptor among multiple tasks. As described in NDK API reference guide, fdShare() is useful in a case where Task A opens a session and calls recv() in a loop on a socket. Task B has a loop that calls send() on the same socket. The call to send() from Task B will fail and then fdError() will return -1 if you do not call fdOpenSession() and then fdShare() from the second Task after the first Task has opened the socket. For an example that calls fdShare(), see the contest.c file in the /packages/ti/ndk/tools/console directory.rr}r(jjjjubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rU5how-to-tune-tcp-buffer-size-for-an-optimal-throughputraj]rjaujMjhj]r(j)r}r(jX6How to tune TCP buffer size for an optimal throughput?rjjjjjjj}r(j]j]j]j]j]ujMjhj]rjX6How to tune TCP buffer size for an optimal throughput?rr}r(jjjjubaubj)r}r(jXThe default TCP buffer size, CFGITEM_IP_SOCKTCPTXBUF/CFGITEM_IP_SOCKTCPRXBUF is 8192 defined in packages/ti/ndk/inc/stack/inc/resif.h of NDK package and can be re-configured in RTOS config file,e.g. Tcp.transmitBufSize = 16384; Tcp.receiveBufSize = 65536; NDK also provides a global TCP statistics counter structure NDK_tcps (ti/ndk/inc/stack/inc/tcpif.h) that can be analyzed in CCS View Expressions window, similaly, there is a global IP statistics counter structure NDK_ips (ti/ndk/inc/stack/inc/ipif.h).rjjjjjjj}r(j]j]j]j]j]ujMjhj]rjXThe default TCP buffer size, CFGITEM_IP_SOCKTCPTXBUF/CFGITEM_IP_SOCKTCPRXBUF is 8192 defined in packages/ti/ndk/inc/stack/inc/resif.h of NDK package and can be re-configured in RTOS config file,e.g. Tcp.transmitBufSize = 16384; Tcp.receiveBufSize = 65536; NDK also provides a global TCP statistics counter structure NDK_tcps (ti/ndk/inc/stack/inc/tcpif.h) that can be analyzed in CCS View Expressions window, similaly, there is a global IP statistics counter structure NDK_ips (ti/ndk/inc/stack/inc/ipif.h).rr}r(jjjjubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rU/why-a-pipe-creation-fails-and-fderror-returns-1raj]rjaujMjhj]r(j)r}r(jX3Why a pipe creation fails and fdError() returns -1?rjjjjjjj}r(j]j]j]j]j]ujMjhj]rjX3Why a pipe creation fails and fdError() returns -1?rr}r(jjjjubaubj)r}r(jXAlthough sockets can be used for inter-task communications, it is not the most efficient method. The stack provides a second data communications model called pipes, which allow for local connection oriented communications. As a pipe is a full duplex connection oriented file descriptor, fdOpenSession() needs to be called, which opens a file descriptor session on a task thread so that the task can begin using file descriptor and other stream IO functions.rjjjjjjj}r(j]j]j]j]j]ujMjhj]rjXAlthough sockets can be used for inter-task communications, it is not the most efficient method. The stack provides a second data communications model called pipes, which allow for local connection oriented communications. As a pipe is a full duplex connection oriented file descriptor, fdOpenSession() needs to be called, which opens a file descriptor session on a task thread so that the task can begin using file descriptor and other stream IO functions.rr}r(jjjjubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rUhow-do-i-change-the-pbm-bufferraj]rhaujMjhj]r(j)r}r(jXHow do I change the PBM buffer?rjjjjjjj}r(j]j]j]j]j]ujMjhj]rjXHow do I change the PBM buffer?rr}r(jjjjubaubj)r }r (jXYou can configure the PBM buffer used by the NDK by opening the .cfg file with XGCONF, then clicking the Buffers button. This page lets you configure the buffer size, number of buffers and locations of the NDK Packet Buffer Manager (PBM) and the Memory Manager Buffer. Or, you can edit ndk_3_xx_xx_xx\packages\ti\ndk\stack\pbm\pbm_data.c (PKT_NUM_FRAMEBUF and PKT_SIZE_FRAMEBUF) and rebuild the NDK.r jjjjjjj}r (j]j]j]j]j]ujMjhj]r jXYou can configure the PBM buffer used by the NDK by opening the .cfg file with XGCONF, then clicking the Buffers button. This page lets you configure the buffer size, number of buffers and locations of the NDK Packet Buffer Manager (PBM) and the Memory Manager Buffer. Or, you can edit ndk_3_xx_xx_xxpackagestindkstackpbmpbm_data.c (PKT_NUM_FRAMEBUF and PKT_SIZE_FRAMEBUF) and rebuild the NDK.rr}r(jXYou can configure the PBM buffer used by the NDK by opening the .cfg file with XGCONF, then clicking the Buffers button. This page lets you configure the buffer size, number of buffers and locations of the NDK Packet Buffer Manager (PBM) and the Memory Manager Buffer. Or, you can edit ndk_3_xx_xx_xx\packages\ti\ndk\stack\pbm\pbm_data.c (PKT_NUM_FRAMEBUF and PKT_SIZE_FRAMEBUF) and rebuild the NDK.jj ubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rU"do-you-have-any-raw-packet-exampleraj]rj@aujMjhj]r(j)r}r(jX#Do you have any raw packet example?rjjjjjjj}r(j]j]j]j]j]ujMjhj]rjX#Do you have any raw packet example?rr}r(jjjjubaubj)r }r!(jXA raw socket is used to receive raw packets. This means packets received at the Ethernet layer will directly pass to the raw socket. Stating it precisely, a raw socket bypasses the normal TCP/IP processing and sends the packets to the specific user application. Please check the TI Network Developer's Kit (NDK) API Reference Guide http://www-s.ti.com/sc/techlit/spru524.pdf A.15 Raw Ethernet Module for details. Code example available in NIMU_emacClientExample_evmXXXX_ExampleProjectr"jjjjjjj}r#(j]j]j]j]j]ujMjhj]r$(jXLA raw socket is used to receive raw packets. This means packets received at the Ethernet layer will directly pass to the raw socket. Stating it precisely, a raw socket bypasses the normal TCP/IP processing and sends the packets to the specific user application. Please check the TI Network Developer's Kit (NDK) API Reference Guide r%r&}r'(jXLA raw socket is used to receive raw packets. This means packets received at the Ethernet layer will directly pass to the raw socket. Stating it precisely, a raw socket bypasses the normal TCP/IP processing and sends the packets to the specific user application. Please check the TI Network Developer's Kit (NDK) API Reference Guide jj ubj)r(}r)(jX*http://www-s.ti.com/sc/techlit/spru524.pdfr*j}r+(Urefurij*j]j]j]j]j]ujj j]r,jX*http://www-s.ti.com/sc/techlit/spru524.pdfr-r.}r/(jUjj(ubajjubjXs A.15 Raw Ethernet Module for details. Code example available in NIMU_emacClientExample_evmXXXX_ExampleProjectr0r1}r2(jXs A.15 Raw Ethernet Module for details. Code example available in NIMU_emacClientExample_evmXXXX_ExampleProjectjj ubeubeubj)r3}r4(jUjjjjjjj}r5(j]j]j]j]r6U(how-do-i-enable-the-jumbo-packet-supportr7aj]r8haujMjhj]r9(j)r:}r;(jX)How do I enable the jumbo packet support?r<jj3jjjjj}r=(j]j]j]j]j]ujMjhj]r>jX)How do I enable the jumbo packet support?r?r@}rA(jj<jj:ubaubj)rB}rC(jXJumbo frames have packet sizes larger than 1500 bytes. Jumbo frame support can be built into an application by linking with libraries compiled for Jumbo frame support. Two parts of changes are needed for NDK/NIMU example: 1. NDK libraries: The NDK libraries would have to be recompiled with the following pre-processor definition added: _INCLUDE_JUMBOFRAME_SUPPORT. 2. NIMU library: the CPSW switch has to be configured to support jumbo packet size and rebuilt. The coding is SOC specific, V0, V4, V5, V6 and V7 NIMU drivers use structure EMAC_OpenConfigInfo and pass the maximum packet size into max_pkt_size field. V1, V2 and V3 NIMU drivers use structure NETIF_DEVICE and pass the maximum packet size into mtu field. Finally, please rebuild the test application with updated NDK and NIMU libraries. A reference example for C6678 is available at: http://processors.wiki.ti.com/index.php/Enabling_Jumbo_Packet_Support_for_C6678. Note the work was implemented on earlier BIOS MCSDK package which was obsolete.jj3jjjjj}rD(j]j]j]j]j]ujMjhj]rE(jXRJumbo frames have packet sizes larger than 1500 bytes. Jumbo frame support can be built into an application by linking with libraries compiled for Jumbo frame support. Two parts of changes are needed for NDK/NIMU example: 1. NDK libraries: The NDK libraries would have to be recompiled with the following pre-processor definition added: _INCLUDE_JUMBOFRAME_SUPPORT. 2. NIMU library: the CPSW switch has to be configured to support jumbo packet size and rebuilt. The coding is SOC specific, V0, V4, V5, V6 and V7 NIMU drivers use structure EMAC_OpenConfigInfo and pass the maximum packet size into max_pkt_size field. V1, V2 and V3 NIMU drivers use structure NETIF_DEVICE and pass the maximum packet size into mtu field. Finally, please rebuild the test application with updated NDK and NIMU libraries. A reference example for C6678 is available at: rFrG}rH(jXRJumbo frames have packet sizes larger than 1500 bytes. Jumbo frame support can be built into an application by linking with libraries compiled for Jumbo frame support. Two parts of changes are needed for NDK/NIMU example: 1. NDK libraries: The NDK libraries would have to be recompiled with the following pre-processor definition added: _INCLUDE_JUMBOFRAME_SUPPORT. 2. NIMU library: the CPSW switch has to be configured to support jumbo packet size and rebuilt. The coding is SOC specific, V0, V4, V5, V6 and V7 NIMU drivers use structure EMAC_OpenConfigInfo and pass the maximum packet size into max_pkt_size field. V1, V2 and V3 NIMU drivers use structure NETIF_DEVICE and pass the maximum packet size into mtu field. Finally, please rebuild the test application with updated NDK and NIMU libraries. A reference example for C6678 is available at: jjBubj)rI}rJ(jXOhttp://processors.wiki.ti.com/index.php/Enabling_Jumbo_Packet_Support_for_C6678rKj}rL(UrefurijKj]j]j]j]j]ujjBj]rMjXOhttp://processors.wiki.ti.com/index.php/Enabling_Jumbo_Packet_Support_for_C6678rNrO}rP(jUjjIubajjubjXQ. Note the work was implemented on earlier BIOS MCSDK package which was obsolete.rQrR}rS(jXQ. Note the work was implemented on earlier BIOS MCSDK package which was obsolete.jjBubeubeubj)rT}rU(jUjjjjjjj}rV(j]j]j]j]rWUZkeystone-pa-or-ndk-example-doesnt-work-in-other-boot-mode-than-no-boot-mode-using-ccs-jtagrXaj]rYj aujMjhj]rZ(j)r[}r\(jX^Keystone PA or NDK example doesn’t work in other boot mode than no-boot mode using CCS/JTAG?r]jjTjjjjj}r^(j]j]j]j]j]ujMjhj]r_jX^Keystone PA or NDK example doesn’t work in other boot mode than no-boot mode using CCS/JTAG?r`ra}rb(jj]jj[ubaubj)rc}rd(jXgWhen running the program with CCS/JTAG, the default GEL file initializes the SOC. Same initialization, like turning on all the relevant power domains, and configuring the SGMII, Serdes, may not be implemented in other boot modes. First check GEL file under ccs_base\emulation\boards\\gel, function Global_Default_Setup() function to add the missing initializations into the application. Next, look for any boot mode dependent code in the application. For example, passPowerUp() is called in no_boot mode to turn on PA, this has to be executed in your application when booting from other boot modes as well.rejjTjjjjj}rf(j]j]j]j]j]ujMjhj]rgjXcWhen running the program with CCS/JTAG, the default GEL file initializes the SOC. Same initialization, like turning on all the relevant power domains, and configuring the SGMII, Serdes, may not be implemented in other boot modes. First check GEL file under ccs_baseemulationboardsgel, function Global_Default_Setup() function to add the missing initializations into the application. Next, look for any boot mode dependent code in the application. For example, passPowerUp() is called in no_boot mode to turn on PA, this has to be executed in your application when booting from other boot modes as well.rhri}rj(jXgWhen running the program with CCS/JTAG, the default GEL file initializes the SOC. Same initialization, like turning on all the relevant power domains, and configuring the SGMII, Serdes, may not be implemented in other boot modes. First check GEL file under ccs_base\emulation\boards\\gel, function Global_Default_Setup() function to add the missing initializations into the application. Next, look for any boot mode dependent code in the application. For example, passPowerUp() is called in no_boot mode to turn on PA, this has to be executed in your application when booting from other boot modes as well.jjcubaubeubeubj)rk}rl(jUjjjjjjj}rm(j]j]j]j]rnU#additional-documentation-referencesroaj]rpjaujMjhj]rq(j)rr}rs(jX#Additional Documentation Referencesrtjjkjjjjj}ru(j]j]j]j]j]ujMjhj]rvjX#Additional Documentation Referencesrwrx}ry(jjtjjrubaubjy )rz}r{(jUjjkjjjj j}r|(j]j]j]j]j]ujNjhj]r}j~ )r~}r(jUj}r(j]j]j]j]j]UcolsKujjzj]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthK#ujj~j]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthK,ujj~j]jj ubj )r}r(jUj}r(j]j]j]j]j]ujj~j]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX **Document**rjjjjjjj}r(j]j]j]j]j]ujMj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXDocumentrr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX **Location**rjjjjjjj}r(j]j]j]j]j]ujMj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXLocationrr}r(jUjjubajjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX NDK Programmer's Reference Guiderjjjjjjj}r(j]j]j]j]j]ujMj]rjX NDK Programmer's Reference Guiderr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX*http://www-s.ti.com/sc/techlit/spru524.pdfrjjjjjjj}r(j]j]j]j]j]ujMj]rj)r}r(jjj}r(Urefurijj]j]j]j]j]ujjj]rjX*http://www-s.ti.com/sc/techlit/spru524.pdfrr}r(jUjjubajjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXNDK User's Guiderjjjjjjj}r(j]j]j]j]j]ujMj]rjXNDK User's Guiderr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX*http://www-s.ti.com/sc/techlit/spru523.pdfrjjjjjjj}r(j]j]j]j]j]ujMj]rj)r}r(jjj}r(Urefurijj]j]j]j]j]ujjj]rjX*http://www-s.ti.com/sc/techlit/spru523.pdfrr}r(jUjjubajjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXNetwork Developers Kit FAQrjjjjjjj}r(j]j]j]j]j]ujMj]rjXNetwork Developers Kit FAQrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX`Network Developers Kit FAQ`_rjjjjjjj}r(j]j]j]j]j]ujMj]rj)r }r (jjjKjjjjj}r (UnameXNetwork Developers Kit FAQjXBhttp://processors.wiki.ti.com/index.php/Network_Developers_Kit_FAQr j]j]j]j]j]uj]r jXNetwork Developers Kit FAQrr}r(jUjj ubaubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX0NDK Support Package Ethernet Driver Design Guiderjjjjjjj}r(j]j]j]j]j]ujMj]rjX0NDK Support Package Ethernet Driver Design Guiderr}r (jjjjubaubajj ubj )r!}r"(jUj}r#(j]j]j]j]j]ujjj]r$j)r%}r&(jX*http://www-s.ti.com/sc/techlit/sprufp2.pdfr'jj!jjjjj}r((j]j]j]j]j]ujMj]r)j)r*}r+(jj'j}r,(Urefurij'j]j]j]j]j]ujj%j]r-jX*http://www-s.ti.com/sc/techlit/sprufp2.pdfr.r/}r0(jUjj*ubajjubaubajj ubejj ubj )r1}r2(jUj}r3(j]j]j]j]j]ujjj]r4(j )r5}r6(jUj}r7(j]j]j]j]j]ujj1j]r8j)r9}r:(jX+Rebuilding_the_NDK_Core Rebuilding NDK Corer;jj5jjjjj}r<(j]j]j]j]j]ujMj]r=jX+Rebuilding_the_NDK_Core Rebuilding NDK Corer>r?}r@(jj;jj9ubaubajj ubj )rA}rB(jUj}rC(j]j]j]j]j]ujj1j]rDj)rE}rF(jX@http://processors.wiki.ti.com/index.php/ Rebuilding_the_NDK_CorejjAjjjjj}rG(j]j]j]j]j]ujMj]rH(j)rI}rJ(jX(http://processors.wiki.ti.com/index.php/rKj}rL(UrefurijKj]j]j]j]j]ujjEj]rMjX(http://processors.wiki.ti.com/index.php/rNrO}rP(jUjjIubajjubjX Rebuilding_the_NDK_CorerQrR}rS(jX Rebuilding_the_NDK_CorejjEubeubajj ubejj ubejj ubejj ubaubj)rT}rU(jXb.. _Network Developers Kit FAQ: http://processors.wiki.ti.com/index.php/Network_Developers_Kit_FAQjKjjkjjjj j}rV(jj j]rWUnetwork-developers-kit-faqrXaj]j]j]j]rYhraujM,6jhj]ubj7)rZ}r[(jX?http://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_NWALjjkjj:X=source/rtos/PDK_Platform_Software/Device_Drivers/NWAL.rst.incr\r]}r^bjj>j}r_(j@jAj]j]j]j]j]ujKjhj]r`jX?http://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_NWALrarb}rc(jUjjZubaubjc)rd}re(jUjjkjj]jjfj}rf(j]j]j]j]j]ujKjhj]rgji)rh}ri(jUjlKjjdjj]jjj}rj(j]j]j]j]j]ujKjhj]ubaubjhK)rk}rl(jX IntroductionrmjKjjkjj]jjlKj}rn(j]roUid141rpaj]j]rqX introductionrraj]j]ujNjhj]rsjX Introductionrtru}rv(jjmjjkubaubjc)rw}rx(jUjjkjj]jjfj}ry(j]j]j]j]j]ujKjhj]rzji)r{}r|(jXThe NWAL (Network Adaptation Layer) driver provides a well-defined set of APIs which could be used for applications interfacing with NetCP (Network Coprocessor) module in Keystone family of SOCs (C66x, K2x).r}jlKjjwjj]jjj}r~(j]j]j]j]j]ujK jhj]rjXThe NWAL (Network Adaptation Layer) driver provides a well-defined set of APIs which could be used for applications interfacing with NetCP (Network Coprocessor) module in Keystone family of SOCs (C66x, K2x).rr}r(jj}jj{ubaubaubjhK)r}r(jXDriver Featuresrjjkjj]jjlKj}r(j]rUdriver-featuresraj]j]j]j]rjFaujNjhj]rjXDriver Featuresrr}r(jjjjubaubjt)r}r(jUjjkjj]jjwj}r(jyX-j]j]j]j]j]ujKjhj]r(j{)r}r(jX2Initialization of NetCP low level driver resourcesrjjjj]jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj]jjj}r(j]j]j]j]j]ujKj]rjX2Initialization of NetCP low level driver resourcesrr}r(jjjjubaubaubj{)r}r(jXDInitialization of Packet DMA related resources associated with NetCPrjjjj]jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj]jjj}r(j]j]j]j]j]ujKj]rjXDInitialization of Packet DMA related resources associated with NetCPrr}r(jjjjubaubaubj{)r}r(jXAClassification of incoming packets based on L2: MAC header fieldsrjjjj]jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj]jjj}r(j]j]j]j]j]ujKj]rjXAClassification of incoming packets based on L2: MAC header fieldsrr}r(jjjjubaubaubj{)r}r(jXGClassification of incoming packets based on L3: IPv4/IPv6 header fieldsjjjj]jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXGClassification of incoming packets based on L3: IPv4/IPv6 header fieldsrjjjj]jjj}r(j]j]j]j]j]ujKj]rjXGClassification of incoming packets based on L3: IPv4/IPv6 header fieldsrr}r(jjjjubaubaubj{)r}r(jX5Routing of packets to host based on L4: UDP/TCP/GTP-Urjjjj]jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj]jjj}r(j]j]j]j]j]ujKj]rjX5Routing of packets to host based on L4: UDP/TCP/GTP-Urr}r(jjjjubaubaubj{)r}r(jX-Unidirectional IPSec SA creation and deletionrjjjj]jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj]jjj}r(j]j]j]j]j]ujKj]rjX-Unidirectional IPSec SA creation and deletionrr}r(jjjjubaubaubj{)r}r(jXGIn band offload of IPSec encryption/decryption for the outgoing packetsjjjj]jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXGIn band offload of IPSec encryption/decryption for the outgoing packetsrjjjj]jjj}r(j]j]j]j]j]ujKj]rjXGIn band offload of IPSec encryption/decryption for the outgoing packetsrr}r(jjjjubaubaubj{)r}r(jX@Access to SA data mode acceleration for data plane applications.rjjjj]jjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjj]jjj}r(j]j]j]j]j]ujKj]rjX@Access to SA data mode acceleration for data plane applications.rr}r(jjjjubaubaubj{)r}r(jXSupports offload of the following features to NETCP Hardware during transmission of packets: - IPv4 checksum/L4:TCP/UDP checksum/IPSec Encryption - Redirection of packets through a specific MAC port - Software Insertion of L2/L3/L4 header jjjNjjj}r(j]j]j]j]j]ujNjhj]r(j)r}r(jX\Supports offload of the following features to NETCP Hardware during transmission of packets:rjjjj]jjj}r(j]j]j]j]j]ujKj]rjX\Supports offload of the following features to NETCP Hardware during transmission of packets:rr}r(jjjjubaubjt)r}r(jUj}r(jyX-j]j]j]j]j]ujjj]r(j{)r}r(jX2IPv4 checksum/L4:TCP/UDP checksum/IPSec Encryptionrj}r(j]j]j]j]j]ujjj]rj)r}r(jjjjjj]jjj}r (j]j]j]j]j]ujKj]r jX2IPv4 checksum/L4:TCP/UDP checksum/IPSec Encryptionr r }r (jjjjubaubajjubj{)r}r(jX2Redirection of packets through a specific MAC portrj}r(j]j]j]j]j]ujjj]rj)r}r(jjjjjj]jjj}r(j]j]j]j]j]ujKj]rjX2Redirection of packets through a specific MAC portrr}r(jjjjubaubajjubj{)r}r(jX&Software Insertion of L2/L3/L4 header j}r(j]j]j]j]j]ujjj]rj)r}r(jX%Software Insertion of L2/L3/L4 headerr jjjj]jjj}r!(j]j]j]j]j]ujKj]r"jX%Software Insertion of L2/L3/L4 headerr#r$}r%(jj jjubaubajjubejjwubeubj{)r&}r'(jX-Upon reception of packet, module provides additional meta data details including: - Status of IP checksum/UDP/TCP checksum results - Offset to L2/L3/L4 protocol offsets. Appropriate layer offset will be valid only if classification or routing is enabled at NETCP - Ingress MAC port information jjjNjjj}r((j]j]j]j]j]ujNjhj]r)(j)r*}r+(jXQUpon reception of packet, module provides additional meta data details including:r,jj&jj]jjj}r-(j]j]j]j]j]ujK j]r.jXQUpon reception of packet, module provides additional meta data details including:r/r0}r1(jj,jj*ubaubjt)r2}r3(jUj}r4(jyX-j]j]j]j]j]ujj&j]r5(j{)r6}r7(jX.Status of IP checksum/UDP/TCP checksum resultsr8j}r9(j]j]j]j]j]ujj2j]r:j)r;}r<(jj8jj6jj]jjj}r=(j]j]j]j]j]ujK#j]r>jX.Status of IP checksum/UDP/TCP checksum resultsr?r@}rA(jj8jj;ubaubajjubj{)rB}rC(jXOffset to L2/L3/L4 protocol offsets. Appropriate layer offset will be valid only if classification or routing is enabled at NETCPj}rD(j]j]j]j]j]ujj2j]rEj)rF}rG(jXOffset to L2/L3/L4 protocol offsets. Appropriate layer offset will be valid only if classification or routing is enabled at NETCPrHjjBjj]jjj}rI(j]j]j]j]j]ujK$j]rJjXOffset to L2/L3/L4 protocol offsets. Appropriate layer offset will be valid only if classification or routing is enabled at NETCPrKrL}rM(jjHjjFubaubajjubj{)rN}rO(jXIngress MAC port information j}rP(j]j]j]j]j]ujj2j]rQj)rR}rS(jXIngress MAC port informationrTjjNjj]jjj}rU(j]j]j]j]j]ujK&j]rVjXIngress MAC port informationrWrX}rY(jjTjjRubaubajjubejjwubeubeubjhK)rZ}r[(jXModes of Operationr\jKjjkjj]jjlKj}r](j]r^Uid142r_aj]j]r`j)aj]j]ujNjhj]rajXModes of Operationrbrc}rd(jj\jjZubaubj)re}rf(jXFollowing modes of operations are supported by NWAL when sending control configuration request to configure NetCP firmware. **BLOCKING Mode**: In this mode, status of API request used to configure NetCP is returned back in API call context.jjkjj]jjj}rg(j]j]j]j]j]ujK+jhj]rh(jX|Following modes of operations are supported by NWAL when sending control configuration request to configure NetCP firmware. rirj}rk(jX|Following modes of operations are supported by NWAL when sending control configuration request to configure NetCP firmware. jjeubj)rl}rm(jX**BLOCKING Mode**j}rn(j]j]j]j]j]ujjej]rojX BLOCKING Moderprq}rr(jUjjlubajjubjXc: In this mode, status of API request used to configure NetCP is returned back in API call context.rsrt}ru(jXc: In this mode, status of API request used to configure NetCP is returned back in API call context.jjeubeubj)rv}rw(jXw**Non-BLOCKING Mode**: In this mode, application can invoke a separate poll routine to retrieve status response result.jjkjj]jjj}rx(j]j]j]j]j]ujK0jhj]ry(j)rz}r{(jX**Non-BLOCKING Mode**j}r|(j]j]j]j]j]ujjvj]r}jXNon-BLOCKING Moder~r}r(jUjjzubajjubjXb: In this mode, application can invoke a separate poll routine to retrieve status response result.rr}r(jXb: In this mode, application can invoke a separate poll routine to retrieve status response result.jjvubeubjc)r}r(jUjjkjj]jjfj}r(j]j]j]j]j]ujK3jhj]rji)r}r(jUjlKjjjj]jjj}r(j]j]j]j]j]ujKjhj]ubaubjhK)r}r(jXDriver Configurationrjjkjj]jjlKj}r(j]rUdriver-configuration-nwalraj]j]j]j]rjaujNjhj]rjXDriver Configurationrr}r(jjjjubaubj)r}r(jXKThe driver configures the NWAL subsystem using the nwalGlobCfg_t structure.rjjkjj]jjj}r(j]j]j]j]j]ujK8jhj]rjXKThe driver configures the NWAL subsystem using the nwalGlobCfg_t structure.rr}r(jjjjubaubj)r}r(jXThis structure must be initialized before the nwal_create() function API is called and cannot be changed afterwards. For details regarding individual fields of this structure, see the Doxygen help by opening PDK_INSTALL_DIR/packages/ti/drv/nwal/docs/doxygen/html/index.html.rjjkjj]jjj}r(j]j]j]j]j]ujK;jhj]rjXThis structure must be initialized before the nwal_create() function API is called and cannot be changed afterwards. For details regarding individual fields of this structure, see the Doxygen help by opening PDK_INSTALL_DIR/packages/ti/drv/nwal/docs/doxygen/html/index.html.rr}r(jjjjubaubjhK)r}r(jX**APIs**rjKjjkjj]jjlKj}r(j]rUid143raj]j]rjtaj]j]ujNjhj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXAPIsrr}r(jUjjubajjubaubj)r}r(jX9API reference for application can be found in below file:rjjkjj]jjj}r(j]j]j]j]j]ujKCjhj]rjX9API reference for application can be found in below file:rr}r(jjjjubaubj)r}r(jX#include jjkjj]jjj}r(j@jAj]j]j]j]j]ujM{6jhj]rjX#include rr}r(jUjjubaubjhK)r}r(jXExamplerjKjjkjj]jjlKj}r(j]rUid144raj]j]rjaj]j]ujNjhj]rjXExamplerr}r(jjjjubaubjy )r}r(jUjjkjj]jj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujjj]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXNamerjjjj]jjj}r(j]j]j]j]j]ujKMj]rjXNamerr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX Descriptionrjjjj]jjj}r(j]j]j]j]j]ujKMj]rjX Descriptionrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXExpected Resultsrjjjj]jjj}r(j]j]j]j]j]ujKMj]rjXExpected Resultsr r }r (jjjjubaubajj ubejj ubajj ubj )r }r (jUj}r(j]j]j]j]j]ujjj]rj )r}r(jUj}r(j]j]j]j]j]ujj j]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXnwalUnitTest Applicationrjjjj]jjj}r(j]j]j]j]j]ujKOj]rjXnwalUnitTest Applicationrr}r(jjjjubaubajj ubj )r }r!(jUj}r"(j]j]j]j]j]ujjj]r#jc)r$}r%(jUj}r&(j]j]j]j]j]ujj j]r'ji)r(}r)(jX&Unit Test application to test all APIsr*jlKjj$jj]jjj}r+(j]j]j]j]j]ujKj]r,jX&Unit Test application to test all APIsr-r.}r/(jj*jj(ubaubajjfubajj ubj )r0}r1(jUj}r2(j]j]j]j]j]ujjj]r3jc)r4}r5(jUj}r6(j]j]j]j]j]ujj0j]r7ji)r8}r9(jX5User observes the output printed over the CCS consoler:jlKjj4jj]jjj}r;(j]j]j]j]j]ujKj]r<jX5User observes the output printed over the CCS consoler=r>}r?(jj:jj8ubaubajjfubajj ubejj ubajj ubejj ubaubjhK)r@}rA(jXAdditional ReferencesrBjKjjkjj]jjlKj}rC(j]rDUid145rEaj]j]rFjaj]j]ujNjhj]rGjXAdditional ReferencesrHrI}rJ(jjBjj@ubaubjy )rK}rL(jUjjkjj]jj j}rM(j]j]j]j]j]ujNjhj]rNj~ )rO}rP(jUj}rQ(j]j]j]j]j]UcolsKujjKj]rR(j )rS}rT(jUj}rU(j]j]j]j]j]UcolwidthK#ujjOj]jj ubj )rV}rW(jUj}rX(j]j]j]j]j]UcolwidthK#ujjOj]jj ubj )rY}rZ(jUj}r[(j]j]j]j]j]ujjOj]r\(j )r]}r^(jUj}r_(j]j]j]j]j]ujjYj]r`(j )ra}rb(jUj}rc(j]j]j]j]j]ujj]j]rdj)re}rf(jX **Document**rgjjajj]jjj}rh(j]j]j]j]j]ujKXj]rij)rj}rk(jjgj}rl(j]j]j]j]j]ujjej]rmjXDocumentrnro}rp(jUjjjubajjubaubajj ubj )rq}rr(jUj}rs(j]j]j]j]j]ujj]j]rtj)ru}rv(jX **Location**rwjjqjj]jjj}rx(j]j]j]j]j]ujKXj]ryj)rz}r{(jjwj}r|(j]j]j]j]j]ujjuj]r}jXLocationr~r}r(jUjjzubajjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjYj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXAPI Reference Manualrjjjj]jjj}r(j]j]j]j]j]ujKZj]rjXAPI Reference Manualrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXI$(TI_PDK_INSTALL_DIR)/packages/ti /drv/nwal/docs/doxygen/html/index .htmlrjjjj]jjj}r(j]j]j]j]j]ujKZj]rjXI$(TI_PDK_INSTALL_DIR)/packages/ti /drv/nwal/docs/doxygen/html/index .htmlrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjYj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX Release Notesrjjjj]jjj}r(j]j]j]j]j]ujK^j]rjX Release Notesrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXK$(TI_PDK_INSTALL_DIR)/packages/ti /drv/nwal/docs/ReleaseNotes_NWAL_ LLD.pdfjjjj]jjj}r(j]j]j]j]j]ujK^j]r(jX1$(TI_PDK_INSTALL_DIR)/packages/ti /drv/nwal/docs/rr}r(jX1$(TI_PDK_INSTALL_DIR)/packages/ti /drv/nwal/docs/jjubj )r}r(jXReleaseNotes_NWAL_rj}r(j]rUid164raj]j]j]j]UrefidUid163rujjj]rjXReleaseNotes_NWAL_rr}r(jUjjubajj ubjX LLD.pdfrr}r(jX LLD.pdfjjubeubajj ubejj ubejj ubejj ubaubeubeubeubjjjjj}r(j]j]j]j]rUcclinkraj]rjraujKjhj]r(j)r}r(jXCCLinkrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXCCLinkrr}r(jjjjubaubj7)r}r(jXAhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_CCLINKjjjj:XFsource/rtos/PDK_Platform_Software/Network_and_Transport/CCLink.rst.incrr}rbjj>j}r(j@jAj]j]j]j]j]ujKjhj]rjXAhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_CCLINKrr}r(jUjjubaubjj)r}r(jUjjjjjjj}r(j]j]j]j]rUprotocol-overviewraj]rhaujKjhj]r(j)r}r(jXProtocol Overviewrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXProtocol Overviewrr}r(jjjjubaubj)r}r(jXThe implementation will demonstrate how to create, run and test CC-Link IE Field Network Basic examples on TI platforms. The following shows the CC-Link IE Field Network Basic Overview:rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXThe implementation will demonstrate how to create, run and test CC-Link IE Field Network Basic examples on TI platforms. The following shows the CC-Link IE Field Network Basic Overview:rr}r(jjjjubaubjt)r}r(jUjjjjjjwj}r(jyX-j]j]j]j]j]ujKjhj]r(j{)r}r(jX1 Gbit/s Ethernet based networkrjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujKj]rjX1 Gbit/s Ethernet based networkrr}r(jjjjubaubaubj{)r}r(jX7Ethernet physical layer (Cat5e cable & RJ45 connectors)rjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r }r (jjjjjjjjj}r (j]j]j]j]j]ujKj]r jX7Ethernet physical layer (Cat5e cable & RJ45 connectors)r r}r(jjjj ubaubaubj{)r}r(jX254 stations per networkrjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujKj]rjX254 stations per networkrr}r(jjjjubaubaubj{)r}r(jX100 meters between stationsrjjjjjjj}r(j]j]j]j]j]ujNjhj]r j)r!}r"(jjjjjjjjj}r#(j]j]j]j]j]ujKj]r$jX100 meters between stationsr%r&}r'(jjjj!ubaubaubj{)r(}r)(jX/Completely deterministic without using switchesr*jjjjjjj}r+(j]j]j]j]j]ujNjhj]r,j)r-}r.(jj*jj(jjjjj}r/(j]j]j]j]j]ujKj]r0jX/Completely deterministic without using switchesr1r2}r3(jj*jj-ubaubaubeubjc)r4}r5(jUjjjjjjfj}r6(j]j]j]j]j]ujKjhj]r7ji)r8}r9(jUjlKjj4jjjjj}r:(j]j]j]j]j]ujKjhj]ubaubeubj)r;}r<(jUjjjjjjj}r=(j]j]j]j]r>Ucode-organizationr?aj]r@haujKjhj]rA(j)rB}rC(jXCode OrganizationrDjj;jjjjj}rE(j]j]j]j]j]ujKjhj]rFjXCode OrganizationrGrH}rI(jjDjjBubaubj)rJ}rK(jXThe Directory structure for CC-Link IE Field Network Basic source code and examples for both NIMU and NIMU_ICSS is shown in the following table.rLjj;jjjjj}rM(j]j]j]j]j]ujK jhj]rNjXThe Directory structure for CC-Link IE Field Network Basic source code and examples for both NIMU and NIMU_ICSS is shown in the following table.rOrP}rQ(jjLjjJubaubjy )rR}rS(jUjj;jjjj j}rT(j]j]j]j]j]ujNjhj]rUj~ )rV}rW(jUj}rX(j]j]j]j]j]UcolsKujjRj]rY(j )rZ}r[(jUj}r\(j]j]j]j]j]UcolwidthKujjVj]jj ubj )r]}r^(jUj}r_(j]j]j]j]j]UcolwidthKSujjVj]jj ubj )r`}ra(jUj}rb(j]j]j]j]j]ujjVj]rc(j )rd}re(jUj}rf(j]j]j]j]j]ujj`j]rgj )rh}ri(jUj}rj(j]UmorecolsKj]j]j]j]ujjdj]rkj)rl}rm(jX**CCLink for CPSW i.e. NIMU**rnjjhjjjjj}ro(j]j]j]j]j]ujK%j]rpj)rq}rr(jjnj}rs(j]j]j]j]j]ujjlj]rtjXCCLink for CPSW i.e. NIMUrurv}rw(jUjjqubajjubaubajj ubajj ubj )rx}ry(jUj}rz(j]j]j]j]j]ujj`j]r{(j )r|}r}(jUj}r~(j]j]j]j]UmorerowsKj]ujjxj]rj)r}r(jX**Master Station Source code**rjj|jjjjj}r(j]j]j]j]j]ujK'j]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXMaster Station Source coderr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]UmorerowsKj]ujjxj]rj)r}r(jXQ$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu/example/CCLink/cclink_masterrjjjjjjj}r(j]j]j]j]j]ujK'j]rjXQ$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu/example/CCLink/cclink_masterrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujj`j]jj ubj )r}r(jUj}r(j]j]j]j]j]ujj`j]r(j )r}r(jUj}r(j]j]j]j]UmorerowsKj]ujjj]rj)r}r(jX**SLave Station Source code**rjjjjjjj}r(j]j]j]j]j]ujK)j]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXSLave Station Source coderr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]UmorerowsKj]ujjj]rj)r}r(jXP$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu/example/CCLink/cclink_slaverjjjjjjj}r(j]j]j]j]j]ujK)j]rjXP$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu/example/CCLink/cclink_slaverr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujj`j]jj ubj )r}r(jUj}r(j]j]j]j]j]ujj`j]r(j )r}r(jUj}r(j]j]j]j]UmorerowsKj]ujjj]rj)r}r(jX**Test Examples script**rjjjjjjj}r(j]j]j]j]j]ujK+j]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXTest Examples scriptrr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]UmorerowsKj]ujjj]rj)r}r(jXI$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu/example/CCLink/rjjjjjjj}r(j]j]j]j]j]ujK+j]rjXI$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu/example/CCLink/rr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujj`j]jj ubj )r}r(jUj}r(j]j]j]j]j]ujj`j]r(j )r}r(jUj}r(j]j]j]j]UmorerowsKj]ujjj]rj)r}r(jX**Test Examples main code**rjjjjjjj}r(j]j]j]j]j]ujK-j]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXTest Examples main coderr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]UmorerowsKj]ujjj]rj)r}r(jXG$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu/example/CCLink/srcrjjjjjjj}r(j]j]j]j]j]ujK-j]rjXG$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu/example/CCLink/srcrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujj`j]jj ubejj ubejj ubaubjy )r}r(jUjj;jjjj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r (jUj}r (j]j]j]j]j]UcolsKujjj]r (j )r }r (jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKXujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj )r}r(jUj}r(j]UmorecolsKj]j]j]j]ujjj]rj)r}r(jX"**CCLink for ICSS i.e. NIMU_ICSS**r jjjjjjj}r!(j]j]j]j]j]ujK2j]r"j)r#}r$(jj j}r%(j]j]j]j]j]ujjj]r&jXCCLink for ICSS i.e. NIMU_ICSSr'r(}r)(jUjj#ubajjubaubajj ubajj ubj )r*}r+(jUj}r,(j]j]j]j]j]ujjj]r-(j )r.}r/(jUj}r0(j]j]j]j]UmorerowsKj]ujj*j]r1j)r2}r3(jX**Master Station Source code**r4jj.jjjjj}r5(j]j]j]j]j]ujK4j]r6j)r7}r8(jj4j}r9(j]j]j]j]j]ujj2j]r:jXMaster Station Source coder;r<}r=(jUjj7ubajjubaubajj ubj )r>}r?(jUj}r@(j]j]j]j]UmorerowsKj]ujj*j]rAj)rB}rC(jXV$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu_icss/example/CCLink/cclink_masterrDjj>jjjjj}rE(j]j]j]j]j]ujK4j]rFjXV$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu_icss/example/CCLink/cclink_masterrGrH}rI(jjDjjBubaubajj ubejj ubj )rJ}rK(jUj}rL(j]j]j]j]j]ujjj]jj ubj )rM}rN(jUj}rO(j]j]j]j]j]ujjj]rP(j )rQ}rR(jUj}rS(j]j]j]j]UmorerowsKj]ujjMj]rTj)rU}rV(jX**Slave Station Source code**rWjjQjjjjj}rX(j]j]j]j]j]ujK6j]rYj)rZ}r[(jjWj}r\(j]j]j]j]j]ujjUj]r]jXSlave Station Source coder^r_}r`(jUjjZubajjubaubajj ubj )ra}rb(jUj}rc(j]j]j]j]UmorerowsKj]ujjMj]rdj)re}rf(jXU$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu_icss/example/CCLink/cclink_slavergjjajjjjj}rh(j]j]j]j]j]ujK6j]rijXU$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu_icss/example/CCLink/cclink_slaverjrk}rl(jjgjjeubaubajj ubejj ubj )rm}rn(jUj}ro(j]j]j]j]j]ujjj]jj ubj )rp}rq(jUj}rr(j]j]j]j]j]ujjj]rs(j )rt}ru(jUj}rv(j]j]j]j]UmorerowsKj]ujjpj]rwj)rx}ry(jX**Test Examples script**rzjjtjjjjj}r{(j]j]j]j]j]ujK8j]r|j)r}}r~(jjzj}r(j]j]j]j]j]ujjxj]rjXTest Examples scriptrr}r(jUjj}ubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]UmorerowsKj]ujjpj]rj)r}r(jXN$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu_icss/example/CCLink/rjjjjjjj}r(j]j]j]j]j]ujK8j]rjXN$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu_icss/example/CCLink/rr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]UmorerowsKj]ujjj]rj)r}r(jX**Test Examples main code**rjjjjjjj}r(j]j]j]j]j]ujK:j]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXTest Examples main coderr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]UmorerowsKj]ujjj]rj)r}r(jXL$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu_icss/example/CCLink/srcrjjjjjjj}r(j]j]j]j]j]ujK:j]rjXL$(TI_PDK_INSTALL_DIR)/packages/ti/transport/ndk/nimu_icss/example/CCLink/srcrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]jj ubejj ubejj ubaubjc)r}r(jUjj;jjjjfj}r(j]j]j]j]j]ujK=jhj]rji)r}r(jUjlKjjjjjjj}r(j]j]j]j]j]ujKjhj]ubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rUbuilding-the-examplesraj]rhaujK@jhj]r(j)r}r(jXBuilding the Examplesrjjjjjjj}r(j]j]j]j]j]ujK@jhj]rjXBuilding the Examplesrr}r(jjjjubaubj)r}r(jXUse pdkProjectCreate.sh for Linux environment or pdkProjectCreate.bat for Windows. This can be found under the /packages folder. The only modification to these scripts, if any, is to update the CCS_INSTALL_PATH variable to point to CCS location if its not in the c:\ti\ccsv6 directory . Please refer to `Rebuilding PDK `__ for details of example project creation and how to run the example projects using CCS.jjjjjjj}r(j]j]j]j]j]ujKBjhj]r(jX2Use pdkProjectCreate.sh for Linux environment or pdkProjectCreate.bat for Windows. This can be found under the /packages folder. The only modification to these scripts, if any, is to update the CCS_INSTALL_PATH variable to point to CCS location if its not in the c:ticcsv6 directory . Please refer to rr}r(jX4Use pdkProjectCreate.sh for Linux environment or pdkProjectCreate.bat for Windows. This can be found under the /packages folder. The only modification to these scripts, if any, is to update the CCS_INSTALL_PATH variable to point to CCS location if its not in the c:\ti\ccsv6 directory . Please refer to jjubj)r}r(jXP`Rebuilding PDK `__j}r(UnameXRebuilding PDKjX;index_how_to_guides.html#rebuild-drivers-from-pdk-directoryj]j]j]j]j]ujjj]rjXRebuilding PDKrr}r(jUjjubajjubjXW for details of example project creation and how to run the example projects using CCS.rr}r(jXW for details of example project creation and how to run the example projects using CCS.jjubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rU2cc-link-ie-field-network-basic-example-descriptionraj]rhwaujKLjhj]r(j)r}r(jX2CC-Link IE Field Network Basic Example Descriptionrjjjjjjj}r(j]j]j]j]j]ujKLjhj]rjX2CC-Link IE Field Network Basic Example Descriptionrr}r(jjjjubaubj)r}r(jXFor each EVM Type supported, there is a cclink example which demonstates cyclic data communication between master and slave station. Once the application is loaded via CCS and run, you will be able to see master sending cyclic data packets and slave receiving the packet. For example, the config file for NIMU for CPSW for idkAM572x, can be found in ti/transport/ndk/nimu/example/CCLink/am572x/armv7/bios/cclink_idkAM572x.cfg. The default IP address for master is 192.168.3.100 and for slave it is 192.168.3.4. If you wish to re-configure the IP address of the CPSW interface you will need to modify the following configuration parameters. make sure master and slave are in same network.rjjjjjjj}r(j]j]j]j]j]ujKNjhj]rjXFor each EVM Type supported, there is a cclink example which demonstates cyclic data communication between master and slave station. Once the application is loaded via CCS and run, you will be able to see master sending cyclic data packets and slave receiving the packet. For example, the config file for NIMU for CPSW for idkAM572x, can be found in ti/transport/ndk/nimu/example/CCLink/am572x/armv7/bios/cclink_idkAM572x.cfg. The default IP address for master is 192.168.3.100 and for slave it is 192.168.3.4. If you wish to re-configure the IP address of the CPSW interface you will need to modify the following configuration parameters. make sure master and slave are in same network.rr}r(jjjjubaubjt)r}r(jUjjjjjjwj}r(jyX-j]j]j]j]j]ujKYjhj]r(j{)r}r(jXIp.address = "new ip address"rjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujKYj]rjXIp.address = "new ip address"rr}r(jjjjubaubaubj{)r}r(jXIp.mask = "new ip mask"rjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r }r (jjjjjjjjj}r (j]j]j]j]j]ujKZj]r jXIp.mask = "new ip mask"r r}r(jjjj ubaubaubj{)r}r(jX'Ip.gatewayIpAddr = "new gatewayIpAddr" jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX&Ip.gatewayIpAddr = "new gatewayIpAddr"rjjjjjjj}r(j]j]j]j]j]ujK[j]rjX&Ip.gatewayIpAddr = "new gatewayIpAddr"rr}r(jjjjubaubaubeubj)r}r(jX`If you do change these settings, you will be required to re-build the Example Project using CCS.rjjjjjjj}r(j]j]j]j]j]ujK]jhj]r jX`If you do change these settings, you will be required to re-build the Example Project using CCS.r!r"}r#(jjjjubaubjy )r$}r%(jUjjjjjj j}r&(j]j]j]j]j]ujNjhj]r'j~ )r(}r)(jUj}r*(j]j]j]j]j]UcolsKujj$j]r+(j )r,}r-(jUj}r.(j]j]j]j]j]UcolwidthKujj(j]jj ubj )r/}r0(jUj}r1(j]j]j]j]j]UcolwidthKujj(j]jj ubj )r2}r3(jUj}r4(j]j]j]j]j]UcolwidthKujj(j]jj ubj )r5}r6(jUj}r7(j]j]j]j]j]ujj(j]r8j )r9}r:(jUj}r;(j]j]j]j]j]ujj5j]r<(j )r=}r>(jUj}r?(j]j]j]j]j]ujj9j]r@j)rA}rB(jXNamerCjj=jjjjj}rD(j]j]j]j]j]ujKaj]rEjXNamerFrG}rH(jjCjjAubaubajj ubj )rI}rJ(jUj}rK(j]j]j]j]j]ujj9j]rLj)rM}rN(jX DescriptionrOjjIjjjjj}rP(j]j]j]j]j]ujKaj]rQjX DescriptionrRrS}rT(jjOjjMubaubajj ubj )rU}rV(jUj}rW(j]j]j]j]j]ujj9j]rXj)rY}rZ(jXEVM Configurationr[jjUjjjjj}r\(j]j]j]j]j]ujKaj]r]jXEVM Configurationr^r_}r`(jj[jjYubaubajj ubejj ubajj ubj )ra}rb(jUj}rc(j]j]j]j]j]ujj(j]rd(j )re}rf(jUj}rg(j]j]j]j]j]ujjaj]rh(j )ri}rj(jUj}rk(j]j]j]j]j]ujjej]rlj)rm}rn(jXANIMU_CCLinkMaster_XXXX_Exampleproject.txtrojjijjjjj}rp(j]j]j]j]j]ujKcj]rqjXANIMU_CCLinkMaster_XXXX_Exampleproject.txtrrrs}rt(jjojjmubaubajj ubj )ru}rv(jUj}rw(j]j]j]j]j]ujjej]rxjc)ry}rz(jUj}r{(j]j]j]j]j]ujjuj]r|ji)r}}r~(jXJExample demonstrates CCLink master station sending cyclic packet to slave.rjlKjjyjjjjj}r(j]j]j]j]j]ujKj]rjXJExample demonstrates CCLink master station sending cyclic packet to slave.rr}r(jjjj}ubaubajjfubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjej]r(jc)r}r(jUj}r(j]j]j]j]j]ujjj]rji)r}r(jXUicev2AM335x: Jumpers J18 and J19 need to be set properly to select CPSW or ICSS mode.rjlKjjjjjjj}r(j]j]j]j]j]ujKj]rjXUicev2AM335x: Jumpers J18 and J19 need to be set properly to select CPSW or ICSS mode.rr}r(jjjjubaubajjfubjc)r}r(jUj}r(j]j]j]j]j]ujjj]rji)r}r(jXQPin2 and Pin3 need to be connected for ICSS mode and Pin1 and Pin2 for CPSW mode.rjlKjjjjjjj}r(j]j]j]j]j]ujKj]rjXQPin2 and Pin3 need to be connected for ICSS mode and Pin1 and Pin2 for CPSW mode.rr}r(jjjjubaubajjfubj)r}r(jXUpdate \*.cfg file with static IP to test. NIMU for CPSW test Tests requires connection of configured Ethernet port under test to external PC on same subnet.jjjjjjj}r(j]j]j]j]j]ujKoj]rjXUpdate *.cfg file with static IP to test. NIMU for CPSW test Tests requires connection of configured Ethernet port under test to external PC on same subnet.rr}r(jXUpdate \*.cfg file with static IP to test. NIMU for CPSW test Tests requires connection of configured Ethernet port under test to external PC on same subnet.jjubaubejj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjaj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX@NIMU_CCLinkSlave_XXXX_Exampleproject.txtrjjjjjjj}r(j]j]j]j]j]ujKyj]rjX@NIMU_CCLinkSlave_XXXX_Exampleproject.txtrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rjc)r}r(jUj}r(j]j]j]j]j]ujjj]rji)r}r(jXjExample demonstrates CCLink slave station receiving cyclic packet from master and sending a response back.rjlKjjjjjjj}r(j]j]j]j]j]ujKj]rjXjExample demonstrates CCLink slave station receiving cyclic packet from master and sending a response back.rr}r(jjjjubaubajjfubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(jc)r}r(jUj}r(j]j]j]j]j]ujjj]rji)r}r(jXUicev2AM335x: Jumpers J18 and J19 need to be set properly to select CPSW or ICSS mode.rjlKjjjjjjj}r(j]j]j]j]j]ujKj]rjXUicev2AM335x: Jumpers J18 and J19 need to be set properly to select CPSW or ICSS mode.rr}r(jjjjubaubajjfubjc)r}r(jUj}r(j]j]j]j]j]ujjj]rji)r}r(jXQPin2 and Pin3 need to be connected for ICSS mode and Pin1 and Pin2 for CPSW mode.rjlKjjjjjjj}r(j]j]j]j]j]ujKj]rjXQPin2 and Pin3 need to be connected for ICSS mode and Pin1 and Pin2 for CPSW mode.rr}r(jjjjubaubajjfubj)r}r(jXUpdate \*.cfg file with static IP to test. NIMU for CPSW test Tests requires connection of configured PRU-ICSS Ethernet port under test to external PC on same subnet.jjjjjjj}r(j]j]j]j]j]ujKj]rjXUpdate *.cfg file with static IP to test. NIMU for CPSW test Tests requires connection of configured PRU-ICSS Ethernet port under test to external PC on same subnet.rr}r(jXUpdate \*.cfg file with static IP to test. NIMU for CPSW test Tests requires connection of configured PRU-ICSS Ethernet port under test to external PC on same subnet.jjubaubejj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjaj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXGNIMU_ICSS_CCLinkMaste r_XXXX_Exampleprojec t.txtrjjjjjjj}r(j]j]j]j]j]ujKj]rjXGNIMU_ICSS_CCLinkMaste r_XXXX_Exampleprojec t.txtrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rjc)r}r(jUj}r(j]j]j]j]j]ujjj]rji)r}r(jXJExample demonstrates CCLink master station sending cyclic packet to slave.rjlKjjjjjjj}r(j]j]j]j]j]ujKj]rjXJExample demonstrates CCLink master station sending cyclic packet to slave.rr }r (jjjjubaubajjfubajj ubj )r }r (jUj}r (j]j]j]j]j]ujjj]r(jc)r}r(jUj}r(j]j]j]j]j]ujj j]rji)r}r(jXUicev2AM335x: Jumpers J18 and J19 need to be set properly to select CPSW or ICSS mode.rjlKjjjjjjj}r(j]j]j]j]j]ujKj]rjXUicev2AM335x: Jumpers J18 and J19 need to be set properly to select CPSW or ICSS mode.rr}r(jjjjubaubajjfubjc)r}r(jUj}r(j]j]j]j]j]ujj j]rji)r}r (jXQPin2 and Pin3 need to be connected for ICSS mode and Pin1 and Pin2 for CPSW mode.r!jlKjjjjjjj}r"(j]j]j]j]j]ujKj]r#jXQPin2 and Pin3 need to be connected for ICSS mode and Pin1 and Pin2 for CPSW mode.r$r%}r&(jj!jjubaubajjfubj)r'}r((jXUpdate \*.cfg file with static IP to test. NIMU for CPSW test Tests requires connection of configured Ethernet port under test to external PC on same subnet.jj jjjjj}r)(j]j]j]j]j]ujKj]r*jXUpdate *.cfg file with static IP to test. NIMU for CPSW test Tests requires connection of configured Ethernet port under test to external PC on same subnet.r+r,}r-(jXUpdate \*.cfg file with static IP to test. NIMU for CPSW test Tests requires connection of configured Ethernet port under test to external PC on same subnet.jj'ubaubejj ubejj ubj )r.}r/(jUj}r0(j]j]j]j]j]ujjaj]r1(j )r2}r3(jUj}r4(j]j]j]j]j]ujj.j]r5j)r6}r7(jXFNIMU_ICSS_CCLinkSlave _XXXX_Exampleproject .txtr8jj2jjjjj}r9(j]j]j]j]j]ujKj]r:jXFNIMU_ICSS_CCLinkSlave _XXXX_Exampleproject .txtr;r<}r=(jj8jj6ubaubajj ubj )r>}r?(jUj}r@(j]j]j]j]j]ujj.j]rAjc)rB}rC(jUj}rD(j]j]j]j]j]ujj>j]rEji)rF}rG(jXjExample demonstrates CCLink slave station receiving cyclic packet from master and sending a response back.rHjlKjjBjjjjj}rI(j]j]j]j]j]ujKj]rJjXjExample demonstrates CCLink slave station receiving cyclic packet from master and sending a response back.rKrL}rM(jjHjjFubaubajjfubajj ubj )rN}rO(jUj}rP(j]j]j]j]j]ujj.j]rQ(jc)rR}rS(jUj}rT(j]j]j]j]j]ujjNj]rUji)rV}rW(jXUicev2AM335x: Jumpers J18 and J19 need to be set properly to select CPSW or ICSS mode.rXjlKjjRjjjjj}rY(j]j]j]j]j]ujKj]rZjXUicev2AM335x: Jumpers J18 and J19 need to be set properly to select CPSW or ICSS mode.r[r\}r](jjXjjVubaubajjfubjc)r^}r_(jUj}r`(j]j]j]j]j]ujjNj]raji)rb}rc(jXQPin2 and Pin3 need to be connected for ICSS mode and Pin1 and Pin2 for CPSW mode.rdjlKjj^jjjjj}re(j]j]j]j]j]ujKj]rfjXQPin2 and Pin3 need to be connected for ICSS mode and Pin1 and Pin2 for CPSW mode.rgrh}ri(jjdjjbubaubajjfubj)rj}rk(jXUpdate \*.cfg file with static IP to test. NIMU for CPSW test Tests requires connection of configured PRU-ICSS Ethernet port under test to external PC on same subnet.jjNjjjjj}rl(j]j]j]j]j]ujKj]rmjXUpdate *.cfg file with static IP to test. NIMU for CPSW test Tests requires connection of configured PRU-ICSS Ethernet port under test to external PC on same subnet.rnro}rp(jXUpdate \*.cfg file with static IP to test. NIMU for CPSW test Tests requires connection of configured PRU-ICSS Ethernet port under test to external PC on same subnet.jjjubaubejj ubejj ubejj ubejj ubaubjc)rq}rr(jUjjjjjjfj}rs(j]j]j]j]j]ujKjhj]rtji)ru}rv(jUjlKjjqjjjjj}rw(j]j]j]j]j]ujKjhj]ubaubeubj)rx}ry(jUjjjjjjj}rz(j]j]j]j]r{U.running-cc-link-ie-field-network-basic-exampler|aj]r}jaujKjhj]r~(j)r}r(jX.Running CC-Link IE Field Network Basic examplerjjxjjjjj}r(j]j]j]j]j]ujKjhj]rjX.Running CC-Link IE Field Network Basic examplerr}r(jjjjubaubj)r}r(jXThe following is the test setup needed to run the example for CCLink demonstration on TI platform. Connect the tested eth port of the evm to a switch for master station. Do the same connection for slave station to same switch.rjjxjjjjj}r(j]j]j]j]j]ujKjhj]rjXThe following is the test setup needed to run the example for CCLink demonstration on TI platform. Connect the tested eth port of the evm to a switch for master station. Do the same connection for slave station to same switch.rr}r(jjjjubaubjR)r}r(jX*.. Image:: ../images/Cclink_setup_pic.PNG jjxjjjjZj}r(UuriX#rtos/../images/Cclink_setup_pic.PNGrj]j]j]j]jX}rU*jsj]ujKjhj]ubjc)r}r(jUjjxjjjjfj}r(j]j]j]j]j]ujKjhj]r(ji)r}r(jUjlKjjjjjjj}r(j]j]j]j]j]ujKjhj]ubji)r}r(jXOnce the connection is done, load master and slave station code on both evm and run them simultaneously. You would see following output on uart port of master station.rjlKjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXOnce the connection is done, load master and slave station code on both evm and run them simultaneously. You would see following output on uart port of master station.rr}r(jjjjubaubeubjR)r}r(jX7.. Image:: ../images/Cclink_master_screeshot_linux.png jjxjjjjZj}r(UuriX0rtos/../images/Cclink_master_screeshot_linux.pngrj]j]j]j]jX}rU*jsj]ujKjhj]ubj)r}r(jX=You would see following output on uart port of slave station.rjjxjjjjj}r(j]j]j]j]j]ujKjhj]rjX=You would see following output on uart port of slave station.rr}r(jjjjubaubjR)r}r(jX7.. Image:: ../images/Cclink_slave_screenshot_linux.png jjxjjjjZj}r(UuriX0rtos/../images/Cclink_slave_screenshot_linux.pngrj]j]j]j]jX}rU*jsj]ujKjhj]ubjc)r}r(jUjjxjjjjfj}r(j]j]j]j]j]ujKjhj]rji)r}r(jUjlKjjjjjjj}r(j]j]j]j]j]ujKjhj]ubaubeubeubeubjjjjj}r(j]rX introductionraj]j]j]rUid139raj]ujKjhj]r(j)r}r(jX Introductionrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjX Introductionrr}r(jjjjubaubj)r}r(jXICC-Link is an open-architecture network that was originally developed by the Mitsubishi Electric Corporation.It have been widely used in Process control, building automation etc. CLPA (CC-Link Partner Association) maintains the network technology and support many manufacturer supporting the application. CC-Link is available in multiple flavours i.e. CC-Link, CC-Link LT, CC-Link Safety, CC-Link IE (Industrial Ethernet) - Control and CC-Link IE Field. For further details regarding CCLink and its flavours please refer the CLPA website.\ `[1] `__jjjjjjj}r(j]j]j]j]j]ujKjhj]r(jXCC-Link is an open-architecture network that was originally developed by the Mitsubishi Electric Corporation.It have been widely used in Process control, building automation etc. CLPA (CC-Link Partner Association) maintains the network technology and support many manufacturer supporting the application. CC-Link is available in multiple flavours i.e. CC-Link, CC-Link LT, CC-Link Safety, CC-Link IE (Industrial Ethernet) - Control and CC-Link IE Field. For further details regarding CCLink and its flavours please refer the CLPA website.rr}r(jXCC-Link is an open-architecture network that was originally developed by the Mitsubishi Electric Corporation.It have been widely used in Process control, building automation etc. CLPA (CC-Link Partner Association) maintains the network technology and support many manufacturer supporting the application. CC-Link is available in multiple flavours i.e. CC-Link, CC-Link LT, CC-Link Safety, CC-Link IE (Industrial Ethernet) - Control and CC-Link IE Field. For further details regarding CCLink and its flavours please refer the CLPA website.\ jjubj)r}r(jX-`[1] `__j}r(UnameX[1]jX#http://am.cc-link.org/en/index.htmlj]j]j]j]j]ujjj]rjX[1]rr}r(jUjjubajjubeubeubjjjjv~j}r(j]UlevelKj]j]rjaUsourcejj]j]UlineKUtypej~ujKjhj]rj)r}r(jX/Duplicate implicit target name: "introduction".j}r(j]j]j]j]j]ujjj]rjX/Duplicate implicit target name: "introduction".rr}r(jUjjubajjubaubjs~)r}r(jUjjjjjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineKUtypejx~ujKjhj]rj)r}r(jX;Bullet list ends without a blank line; unexpected unindent.j}r(j]j]j]j]j]ujjj]rjX;Bullet list ends without a blank line; unexpected unindent.rr}r(jUjjubajjubaubjs~)r}r(jUjjjjjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineKUtypejx~ujKjhj]rj)r}r(jX%Line block ends without a blank line.j}r(j]j]j]j]j]ujjj]rjX%Line block ends without a blank line.rr}r(jUjjubajjubaubjs~)r}r(jUjjxjX]internal padding after source/rtos/PDK_Platform_Software/Network_and_Transport/CCLink.rst.incrjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineKUtypejPujKjhj]r(j)r}r(jX;Content block expected for the "raw" directive; none found.j}r(j]j]j]j]j]ujjj]rjX;Content block expected for the "raw" directive; none found.rr}r(jUjjubajjubj)r}r(jX.. raw:: html j}r(j@jAj]j]j]j]j]ujjj]rjX.. raw:: html rr }r (jUjjubajjubeubjs~)r }r (jUjjjjjjv~j}r (j]UlevelKj]j]rjaUsourcejj]j]UlineKUtypej~ujKjhj]rj)r}r(jX+Duplicate implicit target name: "examples".j}r(j]j]j]j]j]ujj j]rjX+Duplicate implicit target name: "examples".rr}r(jUjjubajjubaubjs~)r}r(jUjjjjjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineMUtypejx~ujMjhj]rj)r}r(jX;Bullet list ends without a blank line; unexpected unindent.j}r(j]j]j]j]j]ujjj]rjX;Bullet list ends without a blank line; unexpected unindent.rr }r!(jUjjubajjubaubjs~)r"}r#(jUj}r$(j]UlevelKj]j]Usourcejj]j]UlineMUtypejx~uj]r%(j)r&}r'(jUj}r((j]j]j]j]j]ujj"j]r)jXTitle underline too short.r*r+}r,(jUjj&ubajjubj)r-}r.(jXKeystone PA or NDK example doesn’t work in other boot mode than no-boot mode using CCS/JTAG? ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^j}r/(j@jAj]j]j]j]j]ujj"j]r0jXKeystone PA or NDK example doesn’t work in other boot mode than no-boot mode using CCS/JTAG? ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^r1r2}r3(jUjj-ubajjubejjv~ubjs~)r4}r5(jUjjTjjjjv~j}r6(j]UlevelKj]j]Usourcejj]j]UlineMUtypejx~ujMjhj]r7(j)r8}r9(jXTitle underline too short.j}r:(j]j]j]j]j]ujj4j]r;jXTitle underline too short.r<r=}r>(jUjj8ubajjubj)r?}r@(jXKeystone PA or NDK example doesn’t work in other boot mode than no-boot mode using CCS/JTAG? ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^j}rA(j@jAj]j]j]j]j]ujj4j]rBjXKeystone PA or NDK example doesn’t work in other boot mode than no-boot mode using CCS/JTAG? ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^rCrD}rE(jUjj?ubajjubeubjs~)rF}rG(jUjjkjXZinternal padding after source/rtos/PDK_Platform_Software/Network_and_Transport/NDK.rst.incrHjjv~j}rI(j]UlevelKj]j]Usourcejj]j]UlineMUtypejPujMjhj]rJ(j)rK}rL(jX;Content block expected for the "raw" directive; none found.j}rM(j]j]j]j]j]ujjFj]rNjX;Content block expected for the "raw" directive; none found.rOrP}rQ(jUjjKubajjubj)rR}rS(jX.. raw:: html j}rT(j@jAj]j]j]j]j]ujjFj]rUjX.. raw:: html rVrW}rX(jUjjRubajjubeubjs~)rY}rZ(jUjjkjjjjv~j}r[(j]UlevelKj]j]Usourcejj]j]UlineKUtypeUSEVEREr\ujKjhj]r](j)r^}r_(jXTitle level inconsistent:j}r`(j]j]j]j]j]ujjYj]rajXTitle level inconsistent:rbrc}rd(jUjj^ubajjubj)re}rf(jXNWAL ***************j}rg(j@jAj]j]j]j]j]ujjYj]rhjXNWAL ***************rirj}rk(jUjjeubajjubeubjs~)rl}rm(jUj}rn(j]UlevelKj]j]rojpaUsourcejj]j]UlineKUtypejx~ujjkj]rpj)rq}rr(jX/Duplicate explicit target name: "introduction".j}rs(j]j]j]j]j]ujjlj]rtjX/Duplicate explicit target name: "introduction".rurv}rw(jUjjqubajjubajjv~ubjs~)rx}ry(jUj}rz(j]UlevelKj]j]r{j_aUsourcejj]j]UlineKUtypejx~ujjZj]r|j)r}}r~(jX5Duplicate explicit target name: "modes-of-operation".j}r(j]j]j]j]j]ujjxj]rjX5Duplicate explicit target name: "modes-of-operation".rr}r(jUjj}ubajjubajjv~ubjs~)r}r(jUj}r(j]UlevelKj]j]rjaUsourcejj]j]UlineKUtypejx~ujjj]rj)r}r(jX'Duplicate explicit target name: "apis".j}r(j]j]j]j]j]ujjj]rjX'Duplicate explicit target name: "apis".rr}r(jUjjubajjubajjv~ubjs~)r}r(jUj}r(j]UlevelKj]j]rjaUsourcejj]j]UlineKUtypejx~ujjj]rj)r}r(jX*Duplicate explicit target name: "example".j}r(j]j]j]j]j]ujjj]rjX*Duplicate explicit target name: "example".rr}r(jUjjubajjubajjv~ubjs~)r}r(jUj}r(j]UlevelKj]j]rjEaUsourcejj]j]UlineKUtypejx~ujj@j]rj)r}r(jX8Duplicate explicit target name: "additional-references".j}r(j]j]j]j]j]ujjj]rjX8Duplicate explicit target name: "additional-references".rr}r(jUjjubajjubajjv~ubjs~)r}r(jUjjkjXTinternal padding after source/rtos/PDK_Platform_Software/Device_Drivers/NWAL.rst.incrjjv~j}r(j]UlevelKj]j]Usourcej]j]j]UlineKcUtypejPujKejhj]r(j)r}r(jX;Content block expected for the "raw" directive; none found.j}r(j]j]j]j]j]ujjj]rjX;Content block expected for the "raw" directive; none found.rr}r(jUjjubajjubj)r}r(jX.. raw:: html j}r(j@jAj]j]j]j]j]ujjj]rjX.. raw:: html rr}r(jUjjubajjubeubjs~)r}r(jUjj)r}r(jUjKjj)r}r(jUjj)r}r(jUjhjjjjj}r(j]j]j]j]rU transportraj]rjaujKjhj]r(j)r}r(jX Transportrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjX Transportrr}r(jjjjubaubjeubjjjjj}r(j]j]j]j]rU timesync-ptpraj]rjkaujKjhj]r(j)r}r(jXTimeSync (PTP)rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXTimeSync (PTP)rr}r(jjjjubaubj7)r}r(jXHhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_TIMESYNC(PTP)jjjj:XHsource/rtos/PDK_Platform_Software/Network_and_Transport/TimeSync.rst.incrr}rbjj>j}r(j@jAj]j]j]j]j]ujKjhj]rjXHhttp://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_TIMESYNC(PTP)rr}r(jUjjubaubjj)r}r(jUjKjjjjjjj}r(j]rj'aj]j]j]rUid149raj]ujKjhj]r(j)r}r(jXAdditional Referencesrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXAdditional Referencesrr}r(jjjjubaubjy )r}r(jUjjjjjj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujjj]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthK-ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r (jUj}r (j]j]j]j]j]ujjj]r (j )r }r (jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX **Document**rjj jjjjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(j]j]j]j]j]ujjj]rjXDocumentrr}r(jUjjubajjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r }r!(jX **Location**r"jjjjjjj}r#(j]j]j]j]j]ujKj]r$j)r%}r&(jj"j}r'(j]j]j]j]j]ujj j]r(jXLocationr)r*}r+(jUjj%ubajjubaubajj ubejj ubj )r,}r-(jUj}r.(j]j]j]j]j]ujjj]r/(j )r0}r1(jUj}r2(j]j]j]j]j]ujj,j]r3j)r4}r5(jXAPI Reference Manualr6jj0jjjjj}r7(j]j]j]j]j]ujKj]r8jXAPI Reference Manualr9r:}r;(jj6jj4ubaubajj ubj )r<}r=(jUj}r>(j]j]j]j]j]ujj,j]r?j)r@}rA(jXS$(TI_PDK_INSTALL_DIR)/packages/ti /transport/timeSync/docs/doxygen/html/index .htmlrBjj<jjjjj}rC(j]j]j]j]j]ujKj]rDjXS$(TI_PDK_INSTALL_DIR)/packages/ti /transport/timeSync/docs/doxygen/html/index .htmlrErF}rG(jjBjj@ubaubajj ubejj ubejj ubejj ubaubeubeubjjjjj}rH(j]rIXoverviewrJaj]j]j]rKUid146rLaj]ujKjhj]rM(j)rN}rO(jXOverviewrPjjjjjjj}rQ(j]j]j]j]j]ujKjhj]rRjXOverviewrSrT}rU(jjPjjNubaubj)rV}rW(jUjjjjjjj}rX(j]j]j]j]rYUterms-and-abbreviationsrZaj]r[haujKjhj]r\(j)r]}r^(jXTerms and Abbreviationsr_jjVjjjjj}r`(j]j]j]j]j]ujKjhj]rajXTerms and Abbreviationsrbrc}rd(jj_jj]ubaubjy )re}rf(jUjjVjjjj j}rg(j]j]j]j]j]ujNjhj]rhj~ )ri}rj(jUj}rk(j]j]j]j]j]UcolsKujjej]rl(j )rm}rn(jUj}ro(j]j]j]j]j]UcolwidthKujjij]jj ubj )rp}rq(jUj}rr(j]j]j]j]j]UcolwidthK"ujjij]jj ubj )rs}rt(jUj}ru(j]j]j]j]j]ujjij]rvj )rw}rx(jUj}ry(j]j]j]j]j]ujjsj]rz(j )r{}r|(jUj}r}(j]j]j]j]j]ujjwj]r~j)r}r(jXAcronymrjj{jjjjj}r(j]j]j]j]j]ujK j]rjXAcronymrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjwj]rj)r}r(jX Descriptionrjjjjjjj}r(j]j]j]j]j]ujK j]rjX Descriptionrr}r(jjjjubaubajj ubejj ubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjij]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXPTPrjjjjjjj}r(j]j]j]j]j]ujK j]rjXPTPrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXPrecision Time Protocolrjjjjjjj}r(j]j]j]j]j]ujK j]rjXPrecision Time Protocolrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXP2Prjjjjjjj}r(j]j]j]j]j]ujKj]rjXP2Prr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX Peer to Peerrjjjjjjj}r(j]j]j]j]j]ujKj]rjX Peer to Peerrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXE2Erjjjjjjj}r(j]j]j]j]j]ujKj]rjXE2Err}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX End to Endrjjjjjjj}r(j]j]j]j]j]ujKj]rjX End to Endrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXTCrjjjjjjj}r(j]j]j]j]j]ujKj]rjXTCrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXTransparent Clockrjjjjjjj}r(j]j]j]j]j]ujKj]rjXTransparent Clockrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r (j]j]j]j]j]ujjj]r (j )r }r (jUj}r (j]j]j]j]j]ujjj]rj)r}r(jXOCrjj jjjjj}r(j]j]j]j]j]ujKj]rjXOCrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXOrdinary Clockrjjjjjjj}r(j]j]j]j]j]ujKj]rjXOrdinary Clockr r!}r"(jjjjubaubajj ubejj ubj )r#}r$(jUj}r%(j]j]j]j]j]ujjj]r&(j )r'}r((jUj}r)(j]j]j]j]j]ujj#j]r*j)r+}r,(jXBCr-jj'jjjjj}r.(j]j]j]j]j]ujKj]r/jXBCr0r1}r2(jj-jj+ubaubajj ubj )r3}r4(jUj}r5(j]j]j]j]j]ujj#j]r6j)r7}r8(jXBoundary Clockr9jj3jjjjj}r:(j]j]j]j]j]ujKj]r;jXBoundary Clockr<r=}r>(jj9jj7ubaubajj ubejj ubj )r?}r@(jUj}rA(j]j]j]j]j]ujjj]rB(j )rC}rD(jUj}rE(j]j]j]j]j]ujj?j]rFj)rG}rH(jXMasterrIjjCjjjjj}rJ(j]j]j]j]j]ujKj]rKjXMasterrLrM}rN(jjIjjGubaubajj ubj )rO}rP(jUj}rQ(j]j]j]j]j]ujj?j]rRj)rS}rT(jX PTP masterrUjjOjjjjj}rV(j]j]j]j]j]ujKj]rWjX PTP masterrXrY}rZ(jjUjjSubaubajj ubejj ubj )r[}r\(jUj}r](j]j]j]j]j]ujjj]r^(j )r_}r`(jUj}ra(j]j]j]j]j]ujj[j]rbj)rc}rd(jXSlaverejj_jjjjj}rf(j]j]j]j]j]ujKj]rgjXSlaverhri}rj(jjejjcubaubajj ubj )rk}rl(jUj}rm(j]j]j]j]j]ujj[j]rnj)ro}rp(jX PTP Slaverqjjkjjjjj}rr(j]j]j]j]j]ujKj]rsjX PTP Slavertru}rv(jjqjjoubaubajj ubejj ubj )rw}rx(jUj}ry(j]j]j]j]j]ujjj]rz(j )r{}r|(jUj}r}(j]j]j]j]j]ujjwj]r~j)r}r(jXBMCArjj{jjjjj}r(j]j]j]j]j]ujKj]rjXBMCArr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjwj]rj)r}r(jXBest Master Clock Algorithmrjjjjjjj}r(j]j]j]j]j]ujKj]rjXBest Master Clock Algorithmrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXRCFrjjjjjjj}r(j]j]j]j]j]ujKj]rjXRCFrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX/Synchronization/(Frequency Compensation) Factorrjjjjjjj}r(j]j]j]j]j]ujKj]rjX/Synchronization/(Frequency Compensation) Factorrr}r(jjjjubaubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX IEC 61558rjjjjjjj}r(j]j]j]j]j]ujK!j]rjX IEC 61558rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jX'PTP profile for network control systemsrjjjjjjj}r(j]j]j]j]j]ujK!j]rjX'PTP profile for network control systemsrr}r(jjjjubaubajj ubejj ubejj ubejj ubaubeubj)r}r(jUjKjjjjjjj}r(j]rX introductionraj]j]j]rUid147raj]ujK&jhj]r(j)r}r(jX Introductionrjjjjjjj}r(j]j]j]j]j]ujK&jhj]rjX Introductionrr}r(jjjjubaubj)r}r(jXdThis document details the user guide aspects of PTP/1588 v2 master/slave implementation on PRU-ICSS.rjjjjjjj}r(j]j]j]j]j]ujK(jhj]rjXdThis document details the user guide aspects of PTP/1588 v2 master/slave implementation on PRU-ICSS.rr}r(jjjjubaubj)r}r(jXDual EMAC firmware implementation supports P2P and the implementation is unique to Emac. The master capability added to the TimeSync driver is currently limitted to sending Sync and Announce frames. The BMCA/Management part of PTP master is not implemented.rjjjjjjj}r(j]j]j]j]j]ujK*jhj]rjXDual EMAC firmware implementation supports P2P and the implementation is unique to Emac. The master capability added to the TimeSync driver is currently limitted to sending Sync and Announce frames. The BMCA/Management part of PTP master is not implemented.rr}r(jjjjubaubj)r}r(jX&TimeSync (PTP) driver does the task ofrjjjjjjj}r(j]j]j]j]j]ujK/jhj]rjX&TimeSync (PTP) driver does the task ofrr}r(jjjjubaubj )r}r(jUjjjjjj j}r(jU.j]j]j]jUj]j]jjujK1jhj]r(j{)r}r(jX Running BMCArjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujK1j]rjX Running BMCArr}r(jjjjubaubaubj{)r}r(jX)Calculating RCF and Sync packet interval.rjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r (jjjjjjjjj}r (j]j]j]j]j]ujK2j]r jX)Calculating RCF and Sync packet interval.r r }r(jjjjubaubaubj{)r}r(jX Performing clock synchronizationrjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujK3j]rjX Performing clock synchronizationrr}r(jjjjubaubaubj{)r}r(jXCalculating peer and line delayrjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r }r!(jjjjjjjjj}r"(j]j]j]j]j]ujK4j]r#jXCalculating peer and line delayr$r%}r&(jjjj ubaubaubj{)r'}r((jXVSending Delay Request and Delay Response frames (includes Pdelay Req and Pdelay Res) jjjjjjj}r)(j]j]j]j]j]ujNjhj]r*j)r+}r,(jXTSending Delay Request and Delay Response frames (includes Pdelay Req and Pdelay Res)r-jj'jjjjj}r.(j]j]j]j]j]ujK5j]r/jXTSending Delay Request and Delay Response frames (includes Pdelay Req and Pdelay Res)r0r1}r2(jj-jj+ubaubaubeubjhK)r3}r4(jXDriver Configurationr5jjjjjjlKj}r6(j]r7Udriver-configuration-timesyncr8aj]j]j]j]r9h=aujNjhj]r:jXDriver Configurationr;r<}r=(jj5jj3ubaubjhK)r>}r?(jX **Board Specific Configuration**r@jjjjjjlKj}rA(j]rBUboard-specific-configurationrCaj]j]j]j]rDjRaujNjhj]rEj)rF}rG(jj@j}rH(j]j]j]j]j]ujj>j]rIjXBoard Specific ConfigurationrJrK}rL(jUjjFubajjubaubj)rM}rN(jXAll board specific configurations like enabling clock and pin-mux are required before calling any driver APIs. By default Board_Init() API available under board module supports all initialization sequence for TI supported EVMs. In addition it initializes UART instance for Console/STDIO. Refer `Processor SDK RTOS Board Support `__ for additional details.jjjjjjj}rO(j]j]j]j]j]ujK>jhj]rP(jX&All board specific configurations like enabling clock and pin-mux are required before calling any driver APIs. By default Board_Init() API available under board module supports all initialization sequence for TI supported EVMs. In addition it initializes UART instance for Console/STDIO. Refer rQrR}rS(jX&All board specific configurations like enabling clock and pin-mux are required before calling any driver APIs. By default Board_Init() API available under board module supports all initialization sequence for TI supported EVMs. In addition it initializes UART instance for Console/STDIO. Refer jjMubj)rT}rU(jXE`Processor SDK RTOS Board Support `__j}rV(UnameX Processor SDK RTOS Board SupportjXindex_board.html#board-supportj]j]j]j]j]ujjMj]rWjX Processor SDK RTOS Board SupportrXrY}rZ(jUjjTubajjubjX for additional details.r[r\}r](jX for additional details.jjMubeubjhK)r^}r_(jX$**TimeSync Configuration Structure**r`jjjjjjlKj}ra(j]rbU timesync-configuration-structurercaj]j]j]j]rdjmaujNjhj]rej)rf}rg(jj`j}rh(j]j]j]j]j]ujj^j]rijX TimeSync Configuration Structurerjrk}rl(jUjjfubajjubaubj)rm}rn(jXpThe TimeSync driver needs to be initialized/configured with initial parameters during the driver initialization.rojjjjjjj}rp(j]j]j]j]j]ujKIjhj]rqjXpThe TimeSync driver needs to be initialized/configured with initial parameters during the driver initialization.rrrs}rt(jjojjmubaubj)ru}rv(jX;icss_timeSync_init.c binds driver with TimeSync parameters.rwjjjjjjj}rx(j]j]j]j]j]ujKKjhj]ryjX;icss_timeSync_init.c binds driver with TimeSync parameters.rzr{}r|(jjwjjuubaubj)r}}r~(jXTimeSync_drvInit() API triggers all static configuration information available through parameters. Once initialization is complete the driver is ready for use.rjjjjjjj}r(j]j]j]j]j]ujKMjhj]rjXTimeSync_drvInit() API triggers all static configuration information available through parameters. Once initialization is complete the driver is ready for use.rr}r(jjjj}ubaubj)r}r(jXPlease refer to TimeSync_ParamsHandle structure defined under '/packages/ti/transport/timeSync/include/icss_timeSyncApi.h'rjjjjjjj}r(j]j]j]j]j]ujKOjhj]rjXPlease refer to TimeSync_ParamsHandle structure defined under '/packages/ti/transport/timeSync/include/icss_timeSyncApi.h'rr}r(jjjjubaubeubj)r}r(jUjKjjjjjjj}r(j]rXapisraj]j]j]rUid148raj]ujKSjhj]r(j)r}r(jXAPIsrjjjjjjj}r(j]j]j]j]j]ujKSjhj]rjXAPIsrr}r(jjjjubaubj)r}r(jXAPI reference for Application:rjjjjjjj}r(j]j]j]j]j]ujKUjhj]rjXAPI reference for Application:rr}r(jjjjubaubj)r}r(jX0#include jjjjjjj}r(j@jAj]j]j]j]j]ujM6jhj]rjX0#include rr}r(jUjjubaubj)r}r(jX`Below sequence indicates API calling sequence for a simple use case of timeSync master operationrjjjjjjj}r(j]j]j]j]j]ujK[jhj]rjX`Below sequence indicates API calling sequence for a simple use case of timeSync master operationrr}r(jjjjubaubj)r}r(jX_... Board_init(boardCfg); timeSync_example_configureInterrupts(EMAC_PORT_NUM, &emacCfg); ICSS_EmacSocSetInitCfg(instance, emacBaseAddr); ICSS_EmacInit(); /* Assumption: firmware is downloaded and ICSS_EMAC driver is initialized */ TimeSync_drvInit(timeSyncHandle); TimeSync_drvEnable(timeSyncHandle); TimeSync_enableMaster(); While(1) { Delay(); }jjjjjjj}r(jjXcj@jAj]j]j]j}j]j]ujK^jhj]rjX_... Board_init(boardCfg); timeSync_example_configureInterrupts(EMAC_PORT_NUM, &emacCfg); ICSS_EmacSocSetInitCfg(instance, emacBaseAddr); ICSS_EmacInit(); /* Assumption: firmware is downloaded and ICSS_EMAC driver is initialized */ TimeSync_drvInit(timeSyncHandle); TimeSync_drvEnable(timeSyncHandle); TimeSync_enableMaster(); While(1) { Delay(); }rr}r(jUjjubaubj)r}r(jX_Below sequence indicates API calling sequence for a simple use case of timeSync slave operationrjjjjjjj}r(j]j]j]j]j]ujKnjhj]rjX_Below sequence indicates API calling sequence for a simple use case of timeSync slave operationrr}r(jjjjubaubj)r}r(jX`... Board_init(boardCfg); timeSync_example_configureInterrupts(EMAC_PORT_NUM, &emacCfg); ICSS_EmacSocSetInitCfg(instance, emacBaseAddr); ICSS_EmacInit(); /* Assumption: firmware is downloaded and ICSS_EMAC driver is initialized */ TimeSync_drvInit(timeSyncHandle); TimeSync_drvEnable(timeSyncHandle); TimeSync_disableMaster(); While(1) { Delay(); }jjjjjjj}r(jjXcj@jAj]j]j]j}j]j]ujKqjhj]rjX`... Board_init(boardCfg); timeSync_example_configureInterrupts(EMAC_PORT_NUM, &emacCfg); ICSS_EmacSocSetInitCfg(instance, emacBaseAddr); ICSS_EmacInit(); /* Assumption: firmware is downloaded and ICSS_EMAC driver is initialized */ TimeSync_drvInit(timeSyncHandle); TimeSync_drvEnable(timeSyncHandle); TimeSync_disableMaster(); While(1) { Delay(); }rr}r(jUjjubaubj)r}r(jX **NOTE** :jjjjjjj}r(j]j]j]j]j]ujKjhj]r(j)r}r(jX**NOTE**j}r(j]j]j]j]j]ujjj]rjXNOTErr}r(jUjjubajjubjX :rr}r(jX :jjubeubj )r}r(jUjjjjjj j}r(jU.j]j]j]jUj]j]jjujKjhj]r(j{)r}r(jXThe TimeSync Tx callback interrupt is mapped to the ISR TimeSync_txTSIsr(), where the two PRU interrupts configured to ARM interrupt txIntNum are PRU_ARM_EVENT_6 and PRU_ARM_EVENT_7.rjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujKj]rjXThe TimeSync Tx callback interrupt is mapped to the ISR TimeSync_txTSIsr(), where the two PRU interrupts configured to ARM interrupt txIntNum are PRU_ARM_EVENT_6 and PRU_ARM_EVENT_7.rr}r(jjjjubaubaubj{)r}r(jXThe PTP frames are received via the Real Time (RT) call back from ICSS_EMAC driver and hence RT call back needs to be implemented at the application for ICSS-EMAC driver. jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXThe PTP frames are received via the Real Time (RT) call back from ICSS_EMAC driver and hence RT call back needs to be implemented at the application for ICSS-EMAC driver.rjjjjjjj}r(j]j]j]j]j]ujKj]rjXThe PTP frames are received via the Real Time (RT) call back from ICSS_EMAC driver and hence RT call back needs to be implemented at the application for ICSS-EMAC driver.rr}r(jjjjubaubaubeubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rU.tasks-internally-created-from-timesync-drvinitraj]rhNaujKjhj]r(j)r}r(jX0Tasks Internally created from TimeSync_drvInit()rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjX0Tasks Internally created from TimeSync_drvInit()rr}r(jjjjubaubj)r}r(jXBelow tasks would be created after Application calls TimeSync_drvInit() function. The sample osal implementation is provided under /packages/ti/transport/timeSync/example/src/common/timeSync_example_osal.c implementing these tasks.rjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXBelow tasks would be created after Application calls TimeSync_drvInit() function. The sample osal implementation is provided under /packages/ti/transport/timeSync/example/src/common/timeSync_example_osal.c implementing these tasks.rr }r (jjjjubaubjy )r }r (jUjjjjjj j}r (j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujj j]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthK"ujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthK)ujjj]jj ubj )r}r (jUj}r!(j]j]j]j]j]ujjj]r"j )r#}r$(jUj}r%(j]j]j]j]j]ujjj]r&(j )r'}r((jUj}r)(j]j]j]j]j]ujj#j]r*j)r+}r,(jX Handle Namer-jj'jjjjj}r.(j]j]j]j]j]ujKj]r/jX Handle Namer0r1}r2(jj-jj+ubaubajj ubj )r3}r4(jUj}r5(j]j]j]j]j]ujj#j]r6jc)r7}r8(jUj}r9(j]j]j]j]j]ujj3j]r:ji)r;}r<(jX Function Namer=jlKjj7jjjjj}r>(j]j]j]j]j]ujKj]r?jX Function Namer@rA}rB(jj=jj;ubaubajjfubajj ubj )rC}rD(jUj}rE(j]UmorecolsKj]j]j]j]ujj#j]rFjc)rG}rH(jUj}rI(j]j]j]j]j]ujjCj]rJji)rK}rL(jX What it doesrMjlKjjGjjjjj}rN(j]j]j]j]j]ujKj]rOjX What it doesrPrQ}rR(jjMjjKubaubajjfubajj ubejj ubajj ubj )rS}rT(jUj}rU(j]j]j]j]j]ujjj]rV(j )rW}rX(jUj}rY(j]j]j]j]j]ujjSj]rZ(j )r[}r\(jUj}r](j]j]j]j]j]ujjWj]r^j)r_}r`(jXtimeSync_pDelayReqSendTaskrajj[jjjjj}rb(j]j]j]j]j]ujKj]rcjXtimeSync_pDelayReqSendTaskrdre}rf(jjajj_ubaubajj ubj )rg}rh(jUj}ri(j]j]j]j]j]ujjWj]rjj)rk}rl(jXTimeSync_PdelayReqSendTask()rmjjgjjjjj}rn(j]j]j]j]j]ujKj]rojXTimeSync_PdelayReqSendTask()rprq}rr(jjmjjkubaubajj ubj )rs}rt(jUj}ru(j]UmorecolsKj]j]j]j]ujjWj]rvjc)rw}rx(jUj}ry(j]j]j]j]j]ujjsj]rzji)r{}r|(jXqSend Peer Delay Requests periodically on both ports. Delay is configurable. Only applicable for P2P configurationr}jlKjjwjjjjj}r~(j]j]j]j]j]ujKj]rjXqSend Peer Delay Requests periodically on both ports. Delay is configurable. Only applicable for P2P configurationrr}r(jj}jj{ubaubajjfubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjSj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXtimeSync_delayReqSendTaskrjjjjjjj}r(j]j]j]j]j]ujKj]rjXtimeSync_delayReqSendTaskrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXTimeSync_delayReqSendTask()rjjjjjjj}r(j]j]j]j]j]ujKj]rjXTimeSync_delayReqSendTask()rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]UmorecolsKj]j]j]j]ujjj]rjc)r}r(jUj}r(j]j]j]j]j]ujjj]rji)r}r(jXrSend Delay requests to PTP Master. This is currently done for every Sync frame. Pends indefinitely on a semaphore.rjlKjjjjjjj}r(j]j]j]j]j]ujKj]rjXrSend Delay requests to PTP Master. This is currently done for every Sync frame. Pends indefinitely on a semaphore.rr}r(jjjjubaubajjfubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjSj]r(j )r}r(jUj}r(j]j]j]j]UmorerowsKj]ujjj]rj)r}r(jXtimeSync_TxTSTaskP1rjjjjjjj}r(j]j]j]j]j]ujKj]rjXtimeSync_TxTSTaskP1rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]UmorerowsKj]ujjj]rj)r}r(jXTimeSync_TxTSTask_P1()rjjjjjjj}r(j]j]j]j]j]ujKj]rjXTimeSync_TxTSTask_P1()rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]UmorecolsKj]j]j]UmorerowsKj]ujjj]rjc)r}r(jUj}r(j]j]j]j]j]ujjj]rji)r}r(jXQProcess Tx timestamp for Port 1. Pends on an event posted by Tx ISR indefinitely.rjlKjjjjjjj}r(j]j]j]j]j]ujKj]rjXQProcess Tx timestamp for Port 1. Pends on an event posted by Tx ISR indefinitely.rr}r(jjjjubaubajjfubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjSj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjSj]r(j )r}r(jUj}r(j]j]j]j]UmorerowsKj]ujjj]rj)r}r(jXtimeSync_TxTSTaskP2rjjjjjjj}r(j]j]j]j]j]ujKj]rjXtimeSync_TxTSTaskP2rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]UmorerowsKj]ujjj]rj)r}r(jXTimeSync_TxTSTask_P2()rjjjjjjj}r(j]j]j]j]j]ujKj]rjXTimeSync_TxTSTask_P2()rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]UmorecolsKj]j]j]UmorerowsKj]ujjj]rjc)r}r(jUj}r(j]j]j]j]j]ujjj]rji)r}r(jXQProcess Tx timestamp for Port 2. Pends on an event posted by Tx ISR indefinitely.rjlKjjjjjjj}r(j]j]j]j]j]ujKj]rjXQProcess Tx timestamp for Port 2. Pends on an event posted by Tx ISR indefinitely.rr}r (jjjjubaubajjfubajj ubejj ubj )r }r (jUj}r (j]j]j]j]j]ujjSj]jj ubj )r }r(jUj}r(j]j]j]j]j]ujjSj]r(j )r}r(jUj}r(j]j]j]j]UmorerowsKj]ujj j]rj)r}r(jXtimeSync_syncTxTaskrjjjjjjj}r(j]j]j]j]j]ujKj]rjXtimeSync_syncTxTaskrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]UmorerowsKj]ujj j]r j)r!}r"(jXTimeSync_SyncTxTask()r#jjjjjjj}r$(j]j]j]j]j]ujKj]r%jXTimeSync_SyncTxTask()r&r'}r((jj#jj!ubaubajj ubj )r)}r*(jUj}r+(j]UmorecolsKj]j]j]UmorerowsKj]ujj j]r,jc)r-}r.(jUj}r/(j]j]j]j]j]ujj)j]r0ji)r1}r2(jXlSends Sync frames on both ports in Master mode. Pends indefinitely on a semaphore posted by the DM Timer ISRr3jlKjj-jjjjj}r4(j]j]j]j]j]ujKj]r5jXlSends Sync frames on both ports in Master mode. Pends indefinitely on a semaphore posted by the DM Timer ISRr6r7}r8(jj3jj1ubaubajjfubajj ubejj ubj )r9}r:(jUj}r;(j]j]j]j]j]ujjSj]jj ubj )r<}r=(jUj}r>(j]j]j]j]j]ujjSj]r?(j )r@}rA(jUj}rB(j]j]j]j]j]ujj<j]rCj)rD}rE(jXtimeSync_announceTxTaskrFjj@jjjjj}rG(j]j]j]j]j]ujKj]rHjXtimeSync_announceTxTaskrIrJ}rK(jjFjjDubaubajj ubj )rL}rM(jUj}rN(j]j]j]j]j]ujj<j]rOj)rP}rQ(jXTimeSync_AnnounceTxTask()rRjjLjjjjj}rS(j]j]j]j]j]ujKj]rTjXTimeSync_AnnounceTxTask()rUrV}rW(jjRjjPubaubajj ubj )rX}rY(jUj}rZ(j]UmorecolsKj]j]j]j]ujj<j]r[jc)r\}r](jUj}r^(j]j]j]j]j]ujjXj]r_ji)r`}ra(jX0Sends Announce frames on both ports periodicallyrbjlKjj\jjjjj}rc(j]j]j]j]j]ujKj]rdjX0Sends Announce frames on both ports periodicallyrerf}rg(jjbjj`ubaubajjfubajj ubejj ubj )rh}ri(jUj}rj(j]j]j]j]j]ujjSj]rk(j )rl}rm(jUj}rn(j]j]j]j]j]ujjhj]roj)rp}rq(jXtimeSync_NRT_Taskrrjjljjjjj}rs(j]j]j]j]j]ujKj]rtjXtimeSync_NRT_Taskrurv}rw(jjrjjpubaubajj ubj )rx}ry(jUj}rz(j]j]j]j]j]ujjhj]r{j)r|}r}(jXTimeSync_NRT_Task()r~jjxjjjjj}r(j]j]j]j]j]ujKj]rjXTimeSync_NRT_Task()rr}r(jj~jj|ubaubajj ubj )r}r(jUj}r(j]UmorecolsKj]j]j]j]ujjhj]rjc)r}r(jUj}r(j]j]j]j]j]ujjj]rji)r}r(jXeNRT stands for non real time. Processes Peer delay frames in the background and calculate peer delay.rjlKjjjjjjj}r(j]j]j]j]j]ujKj]rjXeNRT stands for non real time. Processes Peer delay frames in the background and calculate peer delay.rr}r(jjjjubaubajjfubajj ubejj ubj )r}r(jUj}r(j]j]j]j]j]ujjSj]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXtimeSync_backgroundTaskrjjjjjjj}r(j]j]j]j]j]ujKj]rjXtimeSync_backgroundTaskrr}r(jjjjubaubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r}r(jXTimeSync_BackgroundTask()rjjjjjjj}r(j]j]j]j]j]ujKj]rjXTimeSync_BackgroundTask()rr}r(jjjjubaubajj ubj )r}r(jUj}r(j]UmorecolsKj]j]j]j]ujjj]rjc)r}r(jUj}r(j]j]j]j]j]ujjj]rji)r}r(jX:Checks for Sync timeout and performs offset stabilization.rjlKjjjjjjj}r(j]j]j]j]j]ujKj]rjX:Checks for Sync timeout and performs offset stabilization.rr}r(jjjjubaubajjfubajj ubejj ubejj ubejj ubaubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rU$building-timesync-examples-unit-testraj]rj>aujKjhj]r(j)r}r(jX$Building timeSync Examples/Unit Testrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjX$Building timeSync Examples/Unit Testrr}r(jjjjubaubjt)r}r(jUjjjjjjwj}r(jyX-j]j]j]j]j]ujKjhj]r(j{)r}r(jXSetup the build environment `SetupBuildEnvironment `__rjjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jjjjjjjjj}r(j]j]j]j]j]ujKj]r(jXSetup the build environment rr}r(jXSetup the build environment jjubj)r}r(jX`SetupBuildEnvironment `__j}r(UnameXSetupBuildEnvironmentjXghttp://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_overview.html#setup-environmentj]j]j]j]j]ujjj]rjXSetupBuildEnvironmentrr}r(jUjjubajjubeubaubj{)r}r(jXFollow the steps as mentioned under `SDK example and test CCS Project Creation `__ for creating the CCS based example and test projects creation jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXFollow the steps as mentioned under `SDK example and test CCS Project Creation `__ for creating the CCS based example and test projects creationjjjjjjj}r(j]j]j]j]j]ujKj]r(jX$Follow the steps as mentioned under rr}r(jX$Follow the steps as mentioned under jjubj)r}r(jX`SDK example and test CCS Project Creation `__j}r(UnameX)SDK example and test CCS Project CreationjX{http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_overview.html#pdk-example-and-test-project-creationj]j]j]j]j]ujjj]rjX)SDK example and test CCS Project Creationrr}r(jUjjubajjubjX? for creating the CCS based example and test projects creationrr}r(jX? for creating the CCS based example and test projects creationjjubeubaubeubeubj)r}r(jUjjjjjjj}r(j]j]j]j]rUsample-examplesraj]rjaujKjhj]r(j)r}r(jXSample Examplesrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXSample Examplesrr}r (jjjjubaubjy )r }r (jUjjjjjj j}r (j]j]j]j]j]ujNjhj]r j~ )r}r(jUj}r(j]j]j]j]j]UcolsKujj j]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]UcolwidthKujjj]jj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj )r}r (jUj}r!(j]j]j]j]j]ujjj]r"(j )r#}r$(jUj}r%(j]j]j]j]j]ujjj]r&j)r'}r((jXNamer)jj#jjjjj}r*(j]j]j]j]j]ujKj]r+jXNamer,r-}r.(jj)jj'ubaubajj ubj )r/}r0(jUj}r1(j]j]j]j]j]ujjj]r2j)r3}r4(jX Descriptionr5jj/jjjjj}r6(j]j]j]j]j]ujKj]r7jX Descriptionr8r9}r:(jj5jj3ubaubajj ubj )r;}r<(jUj}r=(j]j]j]j]j]ujjj]r>jc)r?}r@(jUj}rA(j]j]j]j]j]ujj;j]rBji)rC}rD(jXExpected ResultsrEjlKjj?jjjjj}rF(j]j]j]j]j]ujKj]rGjXExpected ResultsrHrI}rJ(jjEjjCubaubajjfubajj ubejj ubajj ubj )rK}rL(jUj}rM(j]j]j]j]j]ujjj]rNj )rO}rP(jUj}rQ(j]j]j]j]j]ujjKj]rR(j )rS}rT(jUj}rU(j]j]j]j]j]ujjOj]rVj)rW}rX(jXtimeSync_BasicExamplerYjjSjjjjj}rZ(j]j]j]j]j]ujKj]r[jXtimeSync_BasicExampler\r]}r^(jjYjjWubaubajj ubj )r_}r`(jUj}ra(j]j]j]j]j]ujjOj]rbj)rc}rd(jXCSimple timeSync example demonstrating sync between Master and Slaverejj_jjjjj}rf(j]j]j]j]j]ujKj]rgjXCSimple timeSync example demonstrating sync between Master and Slaverhri}rj(jjejjcubaubajj ubj )rk}rl(jUj}rm(j]j]j]j]j]ujjOj]rnjc)ro}rp(jUj}rq(j]j]j]j]j]ujjkj]rrji)rs}rt(jXClock Sync results at SlaverujlKjjojjjjj}rv(j]j]j]j]j]ujKj]rwjXClock Sync results at Slaverxry}rz(jjujjsubaubajjfubajj ubejj ubajj ubejj ubaubeubeubjjjjv~j}r{(j]UlevelKj]j]r|jLaUsourcejj]j]UlineKUtypej~ujKjhj]r}j)r~}r(jX+Duplicate implicit target name: "overview".j}r(j]j]j]j]j]ujjj]rjX+Duplicate implicit target name: "overview".rr}r(jUjj~ubajjubaubjs~)r}r(jUjjjjjjv~j}r(j]UlevelKj]j]rjaUsourcejj]j]UlineK&Utypej~ujK&jhj]rj)r}r(jX/Duplicate implicit target name: "introduction".j}r(j]j]j]j]j]ujjj]rjX/Duplicate implicit target name: "introduction".rr}r(jUjjubajjubaubjs~)r}r(jUjjjjjjv~j}r(j]UlevelKj]j]rjaUsourcejj]j]UlineKSUtypej~ujKSjhj]rj)r}r(jX'Duplicate implicit target name: "apis".j}r(j]j]j]j]j]ujjj]rjX'Duplicate implicit target name: "apis".rr}r(jUjjubajjubaubjs~)r}r(jUjjjjjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineKUtypej~ujKjhj]rj)r}r(jXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.j}r(j]j]j]j]j]ujjj]rjXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rr}r(jUjjubajjubaubjs~)r}r(jUj}r(j]UlevelKj]j]Usourcejj]j]UlineKUtypejx~uj]r(j)r}r(jUj}r(j]j]j]j]j]ujjj]rjXTitle underline too short.rr}r(jUjjubajjubj)r}r(jXCBuilding timeSync Examples/Unit Test ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^j}r(j@jAj]j]j]j]j]ujjj]rjXCBuilding timeSync Examples/Unit Test ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^rr}r(jUjjubajjubejjv~ubjs~)r}r(jUjjjjjjv~j}r(j]UlevelKj]j]Usourcejj]j]UlineKUtypejx~ujKjhj]r(j)r}r(jXTitle underline too short.j}r(j]j]j]j]j]ujjj]rjXTitle underline too short.rr}r(jUjjubajjubj)r}r(jXCBuilding timeSync Examples/Unit Test ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^j}r(j@jAj]j]j]j]j]ujjj]rjXCBuilding timeSync Examples/Unit Test ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^rr}r(jUjjubajjubeubjs~)r}r(jUjjjjjjv~j}r(j]UlevelKj]j]rjaUsourcejj]j]UlineKUtypej~ujKjhj]rj)r}r(jX8Duplicate implicit target name: "additional references".j}r(j]j]j]j]j]ujjj]rjX8Duplicate implicit target name: "additional references".rr}r(jUjjubajjubaubjs~)r}r(jUjj)r}r(jUjKjhjjjjj}r(j]rj aj]j]j]rUid150raj]ujKjhj]r(j)r}r(jXToolsrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXToolsrr}r(jjjjubaubjt)r}r(jUjjjjjjwj}r(jyX-j]j]j]j]j]ujKjhj]rj{)r}r(jXa`Processor SDK RTOS Tools `__ jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jX_`Processor SDK RTOS Tools `__rjjjjjjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(UnameXProcessor SDK RTOS ToolsjX@http://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_Toolsj]j]j]j]j]ujjj]rjXProcessor SDK RTOS Toolsrr}r(jUjjubajjubaubaubaubjy )r}r(jUjjjjjj j}r(j]j]j]j]j]ujNjhj]rj~ )r}r(jUj}r(j]j]j]j]j]UcolsKujjj]r(j )r}r(jUj}r(j]j]j]j]j]UcolwidthK ujjj]jj ubj )r}r (jUj}r (j]j]j]j]j]UcolwidthKbujjj]jj ubj )r }r (jUj}r (j]j]j]j]j]ujjj]rj )r}r(jUj}r(j]j]j]j]j]ujj j]r(j )r}r(jUj}r(j]j]j]j]j]ujjj]rjR)r}r(jX.. Image:: ../images/E2e.jpgj}r(UuriXrtos/../images/E2e.jpgrj]j]j]j]jX}rU*jsj]ujjj]jjZubajj ubj )r}r(jUj}r(j]j]j]j]j]ujjj]rj)r }r!(jX_For technical support please post your questions at `http://e2e.ti.com `__.r"jjjjjjj}r#(j]j]j]j]j]ujKj]r$(jX4For technical support please post your questions at r%r&}r'(jX4For technical support please post your questions at jj ubj)r(}r)(jX*`http://e2e.ti.com `__j}r*(UnameXhttp://e2e.ti.comjXhttp://e2e.ti.com/j]j]j]j]j]ujj j]r+jXhttp://e2e.ti.comr,r-}r.(jUjj(ubajjubjX.r/}r0(jX.jj ubeubajj ubejj ubajj ubejj ubaubeubjjjjv~j}r1(j]UlevelKj]j]r2jaUsourcejj]j]UlineKUtypej~ujKjhj]r3j)r4}r5(jX(Duplicate implicit target name: "tools".j}r6(j]j]j]j]j]ujjj]r7jX(Duplicate implicit target name: "tools".r8r9}r:(jUjj4ubajjubaubeUcurrent_sourcer;NU decorationr<NUautofootnote_startr=KUnameidsr>}r?(hNhjUhNh j$h jh jh j3h jW]hjahjjhj2hjhjUhjhj@hjhjhjahjhjGhjhjhj~hjhjJthj%fh jh!jh"j{uh#jh$j )h%Nh&j1(h'joh(jXh)joPh*jh+jh,Uxdaisr@h-j`Fh.Nh/jh0j.h1jdYh2jYh3jnh4j/4h5jh6jh7Nh8j(h9jh:j#h;jehjh?Nh@jihAj' hBNhCNhDjmhEjhFj`hGNhHjF,hIj/hJjghKjhLjnhMjhNjhOjVhPjhQjhRj7 hSNhTj?hUjohVjhWjlhXjhYNhZjah[jwh\jh]jh^jth_jduh`jKhajʠhbjhcj/hdjNhejNShfj,hgNhhjhijg hjNhkjhljg`hmjwhnjhojhpjuhqjhrjXhsj*htjhuj hvj]hwjhxjhyjhzj\h{Nh|j_h}jSOh~jhNhjXhj`hjUhjNJhjVhjhja1hj^hjuhNhjhj!hjLhjZ_hj]KhjQhjhjِhjkMhjFhjWhj!}hj}hjhjvhjhj0khj1`hj)hjGhNhNhjhjZhjvhjKhjhjFhjhj@zhjhjhjLhju/hj2hjhj|hjhjhj@lhj?hNhjhjmhUfcrAhjohjhjhjhj"hNhj4hjhj#phjhjEhjxhjSohjLhj}hj]hNhj>hjhjhj5hjЂhjhjJhj_hjͿhjhj.hjNhNhNhjhj7hj"hj:hNhjuhjhNhjehjFhjhjhjPhjDhjXhj'hj hjhNhjhjhUti-rtos-kernelrBhj_hjhj hjdhjZGhj!hjshjhj<hNhjhj hjhjlhjKhj[hjahNhjhjz#jjjjj]jjeWjNjjHjjjj?jjGjj{j jEj j']j jV j jYj jXjjjjljNjj/Njjxjj~jNjjMjj(jjIjjjjjNjjjNjj4gjjDjjHHj Nj!jlj"jvj#jdj$jCrj%j j&j<j'jNIj(j>uj)jj*jYj+jj,j*j-j]j.j j/jFj0jj1jyj2jij3jj4jj5jj6jj7j"j8jj9jj:Nj;j5j<jj=j@1j>jj?jij@jjAjsjBjHjCjjDjMjEj^jFjjGj_jHNjINjJjNjKjjLNjMjIjNj;LjONjPjr`jQj?jRjCjSjjTNjUj(jVjMjWjIjXUopenclrCjYjjZj j[jj\Nj]Nj^jj_jj`jGjajjbjrZjcjjdjjejjfjjgj jhj]Jjijjjjmjkjjljyjmjcjnjdjojsjpj'jqj?jrjjsjdmjtjOjuj3jvjWjwjNjxNjyjDjzjvHj{j Xj|jNWj}jtj~j jNjjGjjJjNjjQjjjjjNjjjjO`jjjjWjj{{jjojjXPjjjj|jjjjfjj&jjjjxjNjj,jjkjNjj`__ jjSjjjjj}rY(j]j]j]j]j]ujNjhj]rZj)r[}r\(jXL`SYSBIOS `__r]jjWjjjjj}r^(j]j]j]j]j]ujKj]r_j)r`}ra(jj]j}rb(UnameXSYSBIOSjX>http://processors.wiki.ti.com/index.php?title=Category:SYSBIOSj]j]j]j]j]ujj[j]rcjXSYSBIOSrdre}rf(jUjj`ubajjubaubaubaubeubj)rg}rh(jUjhjjjjj}ri(j]j]j]j]rjj@aj]rkh,aujK jhj]rl(j)rm}rn(jXXDAISrojjgjjjjj}rp(j]j]j]j]j]ujK jhj]rqjXXDAISrrrs}rt(jjojjmubaubjt)ru}rv(jUjjgjjjjwj}rw(jyX-j]j]j]j]j]ujK jhj]rxj{)ry}rz(jXJ`XDAIS `__ jjujjjjj}r{(j]j]j]j]j]ujNjhj]r|j)r}}r~(jXH`XDAIS `__rjjyjjjjj}r(j]j]j]j]j]ujK j]rj)r}r(jjj}r(UnameXXDAISjX<http://processors.wiki.ti.com/index.php?title=Category:XDAISj]j]j]j]j]ujj}j]rjXXDAISrr}r(jUjjubajjubaubaubaubeubj)r}r(jUjhjjjjj}r(j]j]j]j]rjAaj]rhaujKjhj]r(j)r}r(jXFCrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXFCrr}r(jjjjubaubjt)r}r(jUjjjjjjwj}r(jyX-j]j]j]j]j]ujKjhj]rj{)r}r(jXg`Framework Components `__ jjjjjjj}r(j]j]j]j]j]ujNjhj]rj)r}r(jXf`Framework Components `__rjjjjjjj}r(j]j]j]j]j]ujKj]rj)r}r(jjj}r(UnameXFramework ComponentsjXKhttp://processors.wiki.ti.com/index.php?title=Category:Framework_Componentsj]j]j]j]j]ujjj]rjXFramework Componentsrr}r(jUjjubajjubaubaubaubeubjj)r}r(jUjhjjjjj}r(j]j]j]j]rjCaj]rjXaujKjhj]r(j)r}r(jXOpenCLrjjjjjjj}r(j]j]j]j]j]ujKjhj]rjXOpenCLrr}r(jjjjubaubj)r}r(jXG`OpenCL `__rjjjjjjj}r(j]j]j]j]j]ujKjhj]rj)r}r(jjj}r(UnameXOpenCLjX:http://downloads.ti.com/mctools/esd/docs/opencl/index.htmlj]j]j]j]j]ujjj]rjXOpenCLrr}r(jUjjubajjubaubeubjjjjjjjejUU transformerrNU footnote_refsr}rUrefnamesr}r(Xnetwork developers kit faq]rj aX nimu_cpswr]rj)r}r(jjj}r(UnameX NIMU_Cpswj]j]j]Urefnamerjj]j]ujjj]rjX NIMU_Cpswrr}r(jUjjubajjubaXnimu_ftpexampler]rj)r}r(jjxj}r(UnameXNIMU_FtpExamplej]j]j]jjj]j]ujjrj]rjXNIMU_FtpExamplerr}r(jUjjubajjubaXipc 3.x vs ipc lld]rjaX nimu_ftpicssgr]rj)r}r(jjYj}r(UnameX NIMU_FtpIcssgj]j]j]jjj]j]ujjSj]rjX NIMU_FtpIcssgrr}r(jUjjubajjubaXreleasenotes_nwalr]rj)r}r(jjj}r(UnameXReleaseNotes_NWALj]j]j]jjj]j]ujjj]rjXReleaseNotes_NWALrr}r(jUjjubajjubaX ftpexampler]rj)r}r(jjj}r(UnameX FtpExamplej]j]j]jjj]j]ujjj]rjX FtpExamplerr}r(jUjjubajjubaX nimu_ftpcpswr]rj)r}r(jjj}r(UnameX NIMU_FtpCpswj]j]j]jjj]j]ujj j]rjX NIMU_FtpCpswrr}r(jUjjubajjubaX worldexampler]rj)r}r(jjj}r(UnameX WorldExamplej]j]j]jjj]j]ujjj]rjX WorldExampler r }r (jUjjubajjubaX am437x trm]r j0aj]r jauUsymbol_footnotesr]rUautofootnote_refsr]rUsymbol_footnote_refsr]rU citationsr]rjhU current_linerNUtransform_messagesr]r(js~)r}r(jUj}r(j]UlevelKj]rjaj]rjaUsourcejj]j]UlineKUtypejPuj]rj)r}r (jUj}r!(j]j]j]j]j]ujjj]r"jX!Unknown target name: "nimu_cpsw".r#r$}r%(jUjjubajjubajjv~ubjs~)r&}r'(jUj}r((j]UlevelKj]r)jaj]r*jaUsourcejj]j]UlineMUtypejPuj]r+j)r,}r-(jUj}r.(j]j]j]j]j]ujj&j]r/jX$Unknown target name: "worldexample".r0r1}r2(jUjj,ubajjubajjv~ubjs~)r3}r4(jUj}r5(j]UlevelKj]r6j|aj]r7j{aUsourcejj]j]UlineM5UtypejPuj]r8j)r9}r:(jUj}r;(j]j]j]j]j]ujj3j]r<jX'Unknown target name: "nimu_ftpexample".r=r>}r?(jUjj9ubajjubajjv~ubjs~)r@}rA(jUj}rB(j]UlevelKj]rCjaj]rDjaUsourcejj]j]UlineM?UtypejPuj]rEj)rF}rG(jUj}rH(j]j]j]j]j]ujj@j]rIjX"Unknown target name: "ftpexample".rJrK}rL(jUjjFubajjubajjv~ubjs~)rM}rN(jUj}rO(j]UlevelKj]rPjaj]rQjaUsourcejj]j]UlineMIUtypejPuj]rRj)rS}rT(jUj}rU(j]j]j]j]j]ujjMj]rVjX$Unknown target name: "nimu_ftpcpsw".rWrX}rY(jUjjSubajjubajjv~ubjs~)rZ}r[(jUj}r\(j]UlevelKj]r]j]aj]r^j\aUsourcejj]j]UlineMSUtypejPuj]r_j)r`}ra(jUj}rb(j]j]j]j]j]ujjZj]rcjX%Unknown target name: "nimu_ftpicssg".rdre}rf(jUjj`ubajjubajjv~ubjs~)rg}rh(jUj}ri(j]UlevelKj]rjjaj]rkjaUsourcej]j]j]UlineK^UtypejPuj]rlj)rm}rn(jUj}ro(j]j]j]j]j]ujjgj]rpjX)Unknown target name: "releasenotes_nwal".rqrr}rs(jUjjmubajjubajjv~ubjs~)rt}ru(jUj}rv(j]UlevelKj]j]Usourcejj]j]UlineM:Utypej~uj]rwj)rx}ry(jUj}rz(j]j]j]j]j]ujjtj]r{jX3Hyperlink target "fc-boot-label" is not referenced.r|r}}r~(jUjjxubajjubajjv~ubjs~)r}r(jUj}r(j]UlevelKj]j]Usourcejj]j]UlineM6&Utypej~uj]rj)r}r(jUj}r(j]j]j]j]j]ujjj]rjX@Hyperlink target "am655x-sbl-high-level-arch" is not referenced.rr}r(jUjjubajjubajjv~ubjs~)r}r(jUj}r(j]UlevelKj]j]Usourcejj]j]UlineME&Utypej~uj]rj)r}r(jUj}r(j]j]j]j]j]ujjj]rjXDHyperlink target "am655x-sbl-directory-structure" is not referenced.rr}r(jUjjubajjubajjv~ubjs~)r}r(jUj}r(j]UlevelKj]j]Usourcejj]j]UlineM&Utypej~uj]rj)r}r(jUj}r(j]j]j]j]j]ujjj]rjX:Hyperlink target "am655x-image-formats" is not referenced.rr}r(jUjjubajjubajjv~ubjs~)r}r(jUj}r(j]UlevelKj]j]Usourcejj]j]UlineM'Utypej~uj]rj)r}r(jUj}r(j]j]j]j]j]ujjj]rjXCHyperlink target "am655x-compiling-apps-for-sbl" is not referenced.rr}r(jUjjubajjubajjv~ubeUreporterrNUid_startrKU autofootnotesr]rU citation_refsr}rUindirect_targetsr]rUsettingsr(cdocutils.frontend Values ror}r(Ufootnote_backlinksrKUrecord_dependenciesrNU rfc_base_urlrUhttps://tools.ietf.org/html/rU tracebackrUpep_referencesrNUstrip_commentsrNU toc_backlinksrj U language_coderUenrU datestamprNU report_levelrKU _destinationrNU halt_levelrKU strip_classesrNjNUerror_encoding_error_handlerrUbackslashreplacerUdebugrNUembed_stylesheetrUoutput_encoding_error_handlerrUstrictrU sectnum_xformrKUdump_transformsrNU docinfo_xformrKUwarning_streamrNUpep_file_url_templaterUpep-%04drUexit_status_levelrKUconfigrNUstrict_visitorrNUcloak_email_addressesrUtrim_footnote_reference_spacerUenvrNUdump_pseudo_xmlrNUexpose_internalsrNUsectsubtitle_xformrU source_linkrNUrfc_referencesrNUoutput_encodingrUutf-8rU source_urlrNUinput_encodingrU utf-8-sigrU_disable_configrNU id_prefixrUU tab_widthrKUerror_encodingrUUTF-8rU_sourcerjUgettext_compactrU generatorrNUdump_internalsrNU smart_quotesrU pep_base_urlrU https://www.python.org/dev/peps/rUsyntax_highlightrUlongrUinput_encoding_error_handlerrjUauto_id_prefixrUidrUdoctitle_xformrUstrip_elements_with_classesrNU _config_filesr]Ufile_insertion_enabledrU raw_enabledrKU dump_settingsrNubUsymbol_footnote_startrKUidsr}r(j )j )jjjrjmjiSjcSj'Qj!QjPjPj4gj0gjJjJj~jzjHjHjGjGj5Gj0GjDjDjujujjjjjIjCjaj\j$ j j 4j4j_j_jCrj?rjJjJjjzjcj_jjj/Jj)Jjjjjjj jyjuj']j#]jjj)j)jFjFjjjjjLjLj/4j+4jDjDjjjxjxjjjjj@jgjSOjNOj!j!jdYj_YjYjYjjj(j#jjjjjXjTj8j3jjjjjijij&j"j}j}jHjBjjjmjnj`j`j{ujwujMjIjF,jB,jjgjjj/j/j}jwjjjojkjϜjɜjDjDj j jjj@ljuj:ujRjRjj jsjsjJjJj]JjYJjvjvjjjj jZ_jU_jQjMjojojXPjTPjjjkMjfMja1j]1jWjRjzjujjjDj>jmjhjvjqjjyjjjjjGjBjjj.j(j?j;jmjmjjjjj1`j-`j:j6j_j[jjjjjj9jIjIjVjRjjjjjjj#pjpjWjWj~j~jtjtjЂĵjjj3j3jGjGjFjFjj j?j;j} jw j1j1j3j3j*1j$1j|1jv1j/j/j 1j1j)j)jt*jo*j(j(jK)jE)j"jj jjaj]jYjUjjjjjHjHjBjEj{jvjj@jjjXjXjjjj&jjjjj`j`jjjjj#j#j@j<jij ijύjɍjW]jS]j' j# jjjjj^jZjDj@jYjYj'j'jAj=jdj_jjjfjjjjjdj`jjj<j7jduj`ujMjMj jjjjKjKj[jVjwjwjjjujujjj{{jj]KjYKj 'j'jGjGjxjxjajajjjejnj njjjKjGj j j%fj!fjkjkjSQjMQj_j_j7j3jvjvjjjj{jjj j jjjdj^jIjIjeWjaWj\jWjYjYjjjjj!jjGjGjƷjjܷj׷jxjrjjjjjjںjjj}jwj3j3jjjjj j jyjsjjjj|jjjjjjjjjjjnjnj^j^jijcjjj]j ]j\j\jK]jG]jL]jfjjjHHjDHjjjjjjjljlj/Nj*Njc)j])jQjLj"j"jejejjMjjjjjFjFjjjjjjjojoj5j1j2j.jz#jv#jV jR j/j*jjjjjjj!jjjSDj?j:jjjjjjjjj]jYj.aj(ajjjjjUjQjj|jjjNIjJIj)j)jjj5j6j Xj Xj@1j<1j*[j$[jV[jP[jljlj8Wj2WjZj ZjZjZjZjZjSjSjTjSj0Tj+TjVjVjFjFjMjMjjj j jjjWjSjNjIjjj9j4js&jm&j%j%jjj.j.j j j j j(#j##j"j"j#j#j]j]jI%jC%j$j$j;Lj6LjjjCj>j j jUjQj(j(jpjpj@zj