€cdocutils.nodes document q)q}q(U nametypesq}q(Xcpsw/cpts ethernet driverqNXbc-gmac-icss1-prpqˆXtest setup/procedureqNXphy-delay-compensationq ˆXoverviewq NXgenerating 1 ppsq NX preparation-on-the-am57xx-bc-idkq ˆXam572x/am574x mod listq ˆXstarting-the-bc-applicationsqˆXhardwareqNX=test 2. without a hybrid clock between master and slave clockqNXam572x-1qˆX hsr oc tcqNXredundancy (hsr/prp)qNX pps output latency configurationqNXam571x-idk modificationsqˆXhardware overviewqNX0forcing-bc-port-state-change-for-testing-purposeqˆXsoftware componentsqNX dut_3_log,txtqˆX dut_2_log.txtqˆXptp oc, tc in hsr networkqNX#am572x-idk/am574x-idk modificationsqˆXplsdk_ptp_oc-labelqˆXptp ordinary clockqNX procedureqNXapplication linuxptp ptp4lq NX bc-gmac-icss1q!ˆXinternal clock synchronizationq"NXicss pru firmwareq#NXpru-icss-port-configurationsq$ˆX bc-icss1-gmacq%ˆX known issuesq&NXhereq'ˆX)test-with-oregano-syn1588-network-adaptorq(ˆX bc-icss2-gmacq)ˆX pru-icss iepq*NXhardware-modificationsq+ˆXsoftware overviewq,NXbc-icss2-icss1q-ˆX test resultsq.NXptpq/NXptp boundary clockq0NX limitationsq1ˆX setup_hsr.shq2ˆXvlanq3NXgmac-port-configurationsq4ˆX&oregano-network-adaptor-configurationsq5ˆXsupported-platformsq6ˆX%phy delay compensation for am57xx idkq7NXlinuxptp overviewq8NXe2e/ipv4 (telecom profile)q9NX!a sample 3 hsr hybrid clock setupq:NXpru-icssq;NXbc-gmac-icss1-hsrq<ˆXicss-pru/iep ethernet driverq=NX ptpinfo.shq>ˆXplsdk_ptp_hw_mods-labelq?ˆXapplication linuxptp phc2sysq@NXa sample 2 hybrid clock setupqANXptp ordinary clock on pru-icssqBNXBtest 1. with a hybrid clock (oc+tc) between master and slave clockqCNXgmacqDNX(bc internal clock sync monitoring driverqENX bc-gmac-icss2qFˆXhardware modificationsqGNXam572x and am574xqHNXsample bc setupsqINX ptp roadmapqJNX test setupqKNXsetupqLˆX getting-a-ptp-master-clock-readyqMˆXdevice tree setupqNNXbc-icss1-icss2qOˆX5using-1-pps-to-measure-synchronization-accuracyoffsetqPˆX2required hardware and software to setup hsr oc, tcqQNXam571x mod listqRˆX am571x-1 idkqSˆXptp ordinary clock on gmacqTNX dut_1_log.txtqUˆXsome useful commandsqVNX0hardware modifications for am57xx idk hsr oc, tcqWNXam571xqXNXsoftwareqYNuUsubstitution_defsqZ}q[Uparse_messagesq\]q](cdocutils.nodes system_message q^)q_}q`(U rawsourceqaUUparentqbcdocutils.nodes section qc)qd}qe(haUhbhc)qf}qg(haUhbhc)qh}qi(haUhbhUsourceqjXX/home/gtbldadm/nightlybuilds/processor-sdk-doc/source/linux/Industrial_Protocols_PTP.rstqkUtagnameqlUsectionqmU attributesqn}qo(Udupnamesqp]Uclassesqq]Ubackrefsqr]Uidsqs]qtUptpquaUnamesqv]qwh/auUlineqxKUdocumentqyhUchildrenqz]q{(cdocutils.nodes title q|)q}}q~(haXPTPqhbhhhjhkhlUtitleq€hn}q(hp]hq]hr]hs]hv]uhxKhyhhz]q‚cdocutils.nodes Text qƒXPTPq„…q…}q†(hahhbh}ubaubcdocutils.nodes comment q‡)qˆ}q‰(haX?http://processors.wiki.ti.com/index.php/Processor_SDK_LINUX_PTPhbhhhjcdocutils.nodes reprunicode qŠX1source/linux/Industrial_Protocols/PTP/PTP.rst.incq‹…qŒ}qbhlUcommentqŽhn}q(U xml:spaceqUpreserveq‘hs]hr]hp]hq]hv]uhxKhyhhz]q’hƒX?http://processors.wiki.ti.com/index.php/Processor_SDK_LINUX_PTPq“…q”}q•(haUhbhˆubaubhc)q–}q—(haUU referencedq˜KhbhhhjhŒhlhmhn}q™(hp]qšXoverviewq›ahq]hr]hs]qœUoverviewqahv]uhxKhyhhz]qž(h|)qŸ}q (haXOverviewq¡hbh–hjhŒhlh€hn}q¢(hp]hq]hr]hs]hv]uhxKhyhhz]q£hƒXOverviewq¤…q¥}q¦(hah¡hbhŸubaubcdocutils.nodes paragraph q§)q¨}q©(haX;The Precision Time Protocol (PTP), defined in IEEE 1588, is a protocol used to synchronize clocks throughout a network. Many applications in Industrial automation, Grid Infrastructure, Motion Control, AVB, and Telecom markets require nano-second accuracy/precision, varied update rates, rapid reconfiguration after network changes, fault tolerance. TI's Sitara hardware platforms have dedicated hardware/firmware that help us meet these stringent requirements for synchronizing the distributed real-time clocks, in conjunction with LinuxPTP Application Stack. This page is specific to the PTP implementation in Linux, and the following sections provide details about the Software Architecture, Supported platforms, test setup and details about the support for Ordinary Clock (OC), Boundary Clock (BC) And Transparent Clock (TC)qªhbh–hjhŒhlU paragraphq«hn}q¬(hp]hq]hr]hs]hv]uhxKhyhhz]q­hƒX;The Precision Time Protocol (PTP), defined in IEEE 1588, is a protocol used to synchronize clocks throughout a network. Many applications in Industrial automation, Grid Infrastructure, Motion Control, AVB, and Telecom markets require nano-second accuracy/precision, varied update rates, rapid reconfiguration after network changes, fault tolerance. TI's Sitara hardware platforms have dedicated hardware/firmware that help us meet these stringent requirements for synchronizing the distributed real-time clocks, in conjunction with LinuxPTP Application Stack. This page is specific to the PTP implementation in Linux, and the following sections provide details about the Software Architecture, Supported platforms, test setup and details about the support for Ordinary Clock (OC), Boundary Clock (BC) And Transparent Clock (TC)q®…q¯}q°(hahªhbh¨ubaubh§)q±}q²(haXFeatures supportedq³hbh–hjhŒhlh«hn}q´(hp]hq]hr]hs]hv]uhxKhyhhz]qµhƒXFeatures supportedq¶…q·}q¸(hah³hbh±ubaubcdocutils.nodes bullet_list q¹)qº}q»(haUhbh–hjhŒhlU bullet_listq¼hn}q½(Ubulletq¾X-hs]hr]hp]hq]hv]uhxKhyhhz]q¿(cdocutils.nodes list_item qÀ)qÁ}qÂ(haXâPTP/1588 - PTP Slave and Master mode - Supports P2P delay measurement - Supports E2E delay measurement (GMAC, DualEMAC (slave only)) - PTP over IPv4 (Annex D) (GMAC, DualEMAC (slave only)) - PTP over 802.3 (Annex F) hbhºhjNhlU list_itemqÃhn}qÄ(hp]hq]hr]hs]hv]uhxNhyhhz]qÅcdocutils.nodes definition_list qÆ)qÇ}qÈ(haUhn}qÉ(hp]hq]hr]hs]hv]uhbhÁhz]qÊcdocutils.nodes definition_list_item qË)qÌ}qÍ(haXÝPTP/1588 - PTP Slave and Master mode - Supports P2P delay measurement - Supports E2E delay measurement (GMAC, DualEMAC (slave only)) - PTP over IPv4 (Annex D) (GMAC, DualEMAC (slave only)) - PTP over 802.3 (Annex F) hbhÇhjhŒhlUdefinition_list_itemqÎhn}qÏ(hp]hq]hr]hs]hv]uhxKhz]qÐ(cdocutils.nodes term qÑ)qÒ}qÓ(haXPTP/1588qÔhbhÌhjhŒhlUtermqÕhn}qÖ(hp]hq]hr]hs]hv]uhxKhz]q×hƒXPTP/1588qØ…qÙ}qÚ(hahÔhbhÒubaubcdocutils.nodes definition qÛ)qÜ}qÝ(haUhn}qÞ(hp]hq]hr]hs]hv]uhbhÌhz]qßh¹)qà}qá(haUhn}qâ(h¾X-hs]hr]hp]hq]hv]uhbhÜhz]qã(hÀ)qä}qå(haXPTP Slave and Master modeqæhn}qç(hp]hq]hr]hs]hv]uhbhàhz]qèh§)qé}qê(hahæhbhähjhŒhlh«hn}që(hp]hq]hr]hs]hv]uhxKhz]qìhƒXPTP Slave and Master modeqí…qî}qï(hahæhbhéubaubahlhÃubhÀ)qð}qñ(haXSupports P2P delay measurementqòhn}qó(hp]hq]hr]hs]hv]uhbhàhz]qôh§)qõ}qö(hahòhbhðhjhŒhlh«hn}q÷(hp]hq]hr]hs]hv]uhxKhz]qøhƒXSupports P2P delay measurementqù…qú}qû(hahòhbhõubaubahlhÃubhÀ)qü}qý(haX<Supports E2E delay measurement (GMAC, DualEMAC (slave only))qþhn}qÿ(hp]hq]hr]hs]hv]uhbhàhz]rh§)r}r(hahþhbhühjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxKhz]rhƒX<Supports E2E delay measurement (GMAC, DualEMAC (slave only))r…r}r(hahþhbjubaubahlhÃubhÀ)r}r (haX5PTP over IPv4 (Annex D) (GMAC, DualEMAC (slave only))r hn}r (hp]hq]hr]hs]hv]uhbhàhz]r h§)r }r(haj hbjhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxKhz]rhƒX5PTP over IPv4 (Annex D) (GMAC, DualEMAC (slave only))r…r}r(haj hbj ubaubahlhÃubhÀ)r}r(haXPTP over 802.3 (Annex F) hn}r(hp]hq]hr]hs]hv]uhbhàhz]rh§)r}r(haXPTP over 802.3 (Annex F)rhbjhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxKhz]rhƒXPTP over 802.3 (Annex F)r…r}r(hajhbjubaubahlhÃubehlh¼ubahlU definitionr ubeubahlUdefinition_listr!ubaubhÀ)r"}r#(haXbSAN Clock - Ordinary Clock (GMAC/PRU port) - Boundary Clock supported - Two-step clock only hbhºhjNhlhÃhn}r$(hp]hq]hr]hs]hv]uhxNhyhhz]r%hÆ)r&}r'(haUhn}r((hp]hq]hr]hs]hv]uhbj"hz]r)hË)r*}r+(haX_SAN Clock - Ordinary Clock (GMAC/PRU port) - Boundary Clock supported - Two-step clock only hbj&hjhŒhlhÎhn}r,(hp]hq]hr]hs]hv]uhxKhz]r-(hÑ)r.}r/(haX SAN Clockr0hbj*hjhŒhlhÕhn}r1(hp]hq]hr]hs]hv]uhxKhz]r2hƒX SAN Clockr3…r4}r5(haj0hbj.ubaubhÛ)r6}r7(haUhn}r8(hp]hq]hr]hs]hv]uhbj*hz]r9h¹)r:}r;(haUhn}r<(h¾X-hs]hr]hp]hq]hv]uhbj6hz]r=(hÀ)r>}r?(haXOrdinary Clock (GMAC/PRU port)r@hn}rA(hp]hq]hr]hs]hv]uhbj:hz]rBh§)rC}rD(haj@hbj>hjhŒhlh«hn}rE(hp]hq]hr]hs]hv]uhxKhz]rFhƒXOrdinary Clock (GMAC/PRU port)rG…rH}rI(haj@hbjCubaubahlhÃubhÀ)rJ}rK(haXBoundary Clock supportedrLhn}rM(hp]hq]hr]hs]hv]uhbj:hz]rNh§)rO}rP(hajLhbjJhjhŒhlh«hn}rQ(hp]hq]hr]hs]hv]uhxKhz]rRhƒXBoundary Clock supportedrS…rT}rU(hajLhbjOubaubahlhÃubhÀ)rV}rW(haXTwo-step clock only hn}rX(hp]hq]hr]hs]hv]uhbj:hz]rYh§)rZ}r[(haXTwo-step clock onlyr\hbjVhjhŒhlh«hn}r](hp]hq]hr]hs]hv]uhxKhz]r^hƒXTwo-step clock onlyr_…r`}ra(haj\hbjZubaubahlhÃubehlh¼ubahlj ubeubahlj!ubaubhÀ)rb}rc(haXDAN Clock - Ordinary Clock (HSR/PRP port) - Transparent clock as per IEC62439-3 Annex C - Transparent clock one-step to two-step conversion (HSR node) hbhºhjNhlhÃhn}rd(hp]hq]hr]hs]hv]uhxNhyhhz]rehÆ)rf}rg(haUhn}rh(hp]hq]hr]hs]hv]uhbjbhz]rihË)rj}rk(haXšDAN Clock - Ordinary Clock (HSR/PRP port) - Transparent clock as per IEC62439-3 Annex C - Transparent clock one-step to two-step conversion (HSR node) hbjfhjhŒhlhÎhn}rl(hp]hq]hr]hs]hv]uhxK$hz]rm(hÑ)rn}ro(haX DAN ClockrphbjjhjhŒhlhÕhn}rq(hp]hq]hr]hs]hv]uhxK$hz]rrhƒX DAN Clockrs…rt}ru(hajphbjnubaubhÛ)rv}rw(haUhn}rx(hp]hq]hr]hs]hv]uhbjjhz]ryh¹)rz}r{(haUhn}r|(h¾X-hs]hr]hp]hq]hv]uhbjvhz]r}(hÀ)r~}r(haXOrdinary Clock (HSR/PRP port)r€hn}r(hp]hq]hr]hs]hv]uhbjzhz]r‚h§)rƒ}r„(haj€hbj~hjhŒhlh«hn}r…(hp]hq]hr]hs]hv]uhxK"hz]r†hƒXOrdinary Clock (HSR/PRP port)r‡…rˆ}r‰(haj€hbjƒubaubahlhÃubhÀ)rŠ}r‹(haX+Transparent clock as per IEC62439-3 Annex CrŒhn}r(hp]hq]hr]hs]hv]uhbjzhz]rŽh§)r}r(hajŒhbjŠhjhŒhlh«hn}r‘(hp]hq]hr]hs]hv]uhxK#hz]r’hƒX+Transparent clock as per IEC62439-3 Annex Cr“…r”}r•(hajŒhbjubaubahlhÃubhÀ)r–}r—(haX=Transparent clock one-step to two-step conversion (HSR node) hn}r˜(hp]hq]hr]hs]hv]uhbjzhz]r™h§)rš}r›(haX<Transparent clock one-step to two-step conversion (HSR node)rœhbj–hjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxK$hz]ržhƒX<Transparent clock one-step to two-step conversion (HSR node)rŸ…r }r¡(hajœhbjšubaubahlhÃubehlh¼ubahlj ubeubahlj!ubaubeubeubhc)r¢}r£(haUh˜KhbhhhjhŒhlhmhn}r¤(hp]r¥Xsoftware overviewr¦ahq]hr]hs]r§Usoftware-overviewr¨ahv]uhxK'hyhhz]r©(h|)rª}r«(haXSoftware Overviewr¬hbj¢hjhŒhlh€hn}r­(hp]hq]hr]hs]hv]uhxK'hyhhz]r®hƒXSoftware Overviewr¯…r°}r±(haj¬hbjªubaubh§)r²}r³(haXQThe picture below shows the Linux software stack of HSR/PRP/PTP in Processor SDK.r´hbj¢hjhŒhlh«hn}rµ(hp]hq]hr]hs]hv]uhxK)hyhhz]r¶hƒXQThe picture below shows the Linux software stack of HSR/PRP/PTP in Processor SDK.r·…r¸}r¹(haj´hbj²ubaubcdocutils.nodes image rº)r»}r¼(haX*.. Image:: ../images/Software-arch-v1.jpg hbj¢hjhŒhlUimager½hn}r¾(UuriX$linux/../images/Software-arch-v1.jpgr¿hs]hr]hp]hq]U candidatesrÀ}rÁU*j¿shv]uhxK-hyhhz]ubh§)rÂ}rÃ(haXPPTP is supported via the PRP firmware (in PRP EMAC mode) and Dual EMAC firmware.rÄhbj¢hjhŒhlh«hn}rÅ(hp]hq]hr]hs]hv]uhxK.hyhhz]rÆhƒXPPTP is supported via the PRP firmware (in PRP EMAC mode) and Dual EMAC firmware.rÇ…rÈ}rÉ(hajÄhbjÂubaubhc)rÊ}rË(haUhbj¢hjhŒhlhmhn}rÌ(hp]hq]hr]hs]rÍUsoftware-componentsrÎahv]rÏhauhxK1hyhhz]rÐ(h|)rÑ}rÒ(haXSoftware ComponentsrÓhbjÊhjhŒhlh€hn}rÔ(hp]hq]hr]hs]hv]uhxK1hyhhz]rÕhƒXSoftware ComponentsrÖ…r×}rØ(hajÓhbjÑubaubh¹)rÙ}rÚ(haUhbjÊhjhŒhlh¼hn}rÛ(h¾X-hs]hr]hp]hq]hv]uhxK3hyhhz]rÜ(hÀ)rÝ}rÞ(haX?PRUETH driver – Kernel driver abstracts PRU hardware/firmwarerßhbjÙhjhŒhlhÃhn}rà(hp]hq]hr]hs]hv]uhxNhyhhz]ráh§)râ}rã(hajßhbjÝhjhŒhlh«hn}rä(hp]hq]hr]hs]hv]uhxK3hz]råhƒX?PRUETH driver – Kernel driver abstracts PRU hardware/firmwareræ…rç}rè(hajßhbjâubaubaubhÀ)ré}rê(haXDPRUPTP driver – Kernel driver abstracts PRU-ICSS based PTP supportrëhbjÙhjhŒhlhÃhn}rì(hp]hq]hr]hs]hv]uhxNhyhhz]ríh§)rî}rï(hajëhbjéhjhŒhlh«hn}rð(hp]hq]hr]hs]hv]uhxK4hz]rñhƒXDPRUPTP driver – Kernel driver abstracts PRU-ICSS based PTP supportrò…ró}rô(hajëhbjîubaubaubhÀ)rõ}rö(haXACPTS driver - Kernel driver abstracts CPSW/CPTS based PTP supportr÷hbjÙhjhŒhlhÃhn}rø(hp]hq]hr]hs]hv]uhxNhyhhz]rùh§)rú}rû(haj÷hbjõhjhŒhlh«hn}rü(hp]hq]hr]hs]hv]uhxK5hz]rýhƒXACPTS driver - Kernel driver abstracts CPSW/CPTS based PTP supportrþ…rÿ}r(haj÷hbjúubaubaubhÀ)r}r(haXFBC driver – Responsible for port state changes, IO Pad configurationrhbjÙhjhŒhlhÃhn}r(hp]hq]hr]hs]hv]uhxNhyhhz]rh§)r}r(hajhbjhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxK6hz]r hƒXFBC driver – Responsible for port state changes, IO Pad configurationr …r }r (hajhbjubaubaubhÀ)r }r(haXQHSR/PRP driver – Upstream HSR driver, with PRP support and additional bug fixeshbjÙhjhŒhlhÃhn}r(hp]hq]hr]hs]hv]uhxNhyhhz]rh§)r}r(haXQHSR/PRP driver – Upstream HSR driver, with PRP support and additional bug fixesrhbj hjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxK7hz]rhƒXQHSR/PRP driver – Upstream HSR driver, with PRP support and additional bug fixesr…r}r(hajhbjubaubaubhÀ)r}r(haXäiproute2 - a collection of userspace utilities for controlling and monitoring various aspects of networking in the Linux kernel, including routing, network interfaces, tunnels, traffic control, and network-related device drivershbjÙhjhŒhlhÃhn}r(hp]hq]hr]hs]hv]uhxNhyhhz]rh§)r}r(haXäiproute2 - a collection of userspace utilities for controlling and monitoring various aspects of networking in the Linux kernel, including routing, network interfaces, tunnels, traffic control, and network-related device driversrhbjhjhŒhlh«hn}r (hp]hq]hr]hs]hv]uhxK9hz]r!hƒXäiproute2 - a collection of userspace utilities for controlling and monitoring various aspects of networking in the Linux kernel, including routing, network interfaces, tunnels, traffic control, and network-related device driversr"…r#}r$(hajhbjubaubaubhÀ)r%}r&(haXHnet-snmp - a suite of software for using and deploying the SNMP protocolhbjÙhjhŒhlhÃhn}r'(hp]hq]hr]hs]hv]uhxNhyhhz]r(h§)r)}r*(haXHnet-snmp - a suite of software for using and deploying the SNMP protocolr+hbj%hjhŒhlh«hn}r,(hp]hq]hr]hs]hv]uhxK=hz]r-hƒXHnet-snmp - a suite of software for using and deploying the SNMP protocolr.…r/}r0(haj+hbj)ubaubaubhÀ)r1}r2(haXlinuxptp (ptp4l, phc2sys)r3hbjÙhjhŒhlhÃhn}r4(hp]hq]hr]hs]hv]uhxNhyhhz]r5h§)r6}r7(haj3hbj1hjhŒhlh«hn}r8(hp]hq]hr]hs]hv]uhxK?hz]r9hƒXlinuxptp (ptp4l, phc2sys)r:…r;}r<(haj3hbj6ubaubaubhÀ)r=}r>(haX"Filesystem (/dev/ppsX, /dev/ptpX) hbjÙhjhŒhlhÃhn}r?(hp]hq]hr]hs]hv]uhxNhyhhz]r@h§)rA}rB(haX!Filesystem (/dev/ppsX, /dev/ptpX)rChbj=hjhŒhlh«hn}rD(hp]hq]hr]hs]hv]uhxK@hz]rEhƒX!Filesystem (/dev/ppsX, /dev/ptpX)rF…rG}rH(hajChbjAubaubaubeubeubhc)rI}rJ(haUhbj¢hjhŒhlhmhn}rK(hp]hq]hr]hs]rLUlinuxptp-overviewrMahv]rNh8auhxKChyhhz]rO(h|)rP}rQ(haXlinuxptp OverviewrRhbjIhjhŒhlh€hn}rS(hp]hq]hr]hs]hv]uhxKChyhhz]rThƒXlinuxptp OverviewrU…rV}rW(hajRhbjPubaubh§)rX}rY(haX+The Linux PTP Project is a software implementation of the PTP according to the IEEE 1588 Standard. This software is licensed under GNU GPL License, as described in the Processor SDK Software Manifest. For more details on Linux PTP framework and implementation refer: http://linuxptp.sourceforge.net/hbjIhjhŒhlh«hn}rZ(hp]hq]hr]hs]hv]uhxKEhyhhz]r[(hƒX The Linux PTP Project is a software implementation of the PTP according to the IEEE 1588 Standard. This software is licensed under GNU GPL License, as described in the Processor SDK Software Manifest. For more details on Linux PTP framework and implementation refer: r\…r]}r^(haX The Linux PTP Project is a software implementation of the PTP according to the IEEE 1588 Standard. This software is licensed under GNU GPL License, as described in the Processor SDK Software Manifest. For more details on Linux PTP framework and implementation refer: hbjXubcdocutils.nodes reference r_)r`}ra(haX http://linuxptp.sourceforge.net/rbhn}rc(Urefurijbhs]hr]hp]hq]hv]uhbjXhz]rdhƒX http://linuxptp.sourceforge.net/re…rf}rg(haUhbj`ubahlU referencerhubeubh§)ri}rj(haX’LinuxPTP provides the four user applications - ptp4l, phc2sys, hwstamp\_ctl and pmc. The definition and usage of these applications is as follows:hbjIhjhŒhlh«hn}rk(hp]hq]hr]hs]hv]uhxKKhyhhz]rlhƒX‘LinuxPTP provides the four user applications - ptp4l, phc2sys, hwstamp_ctl and pmc. The definition and usage of these applications is as follows:rm…rn}ro(haX’LinuxPTP provides the four user applications - ptp4l, phc2sys, hwstamp\_ctl and pmc. The definition and usage of these applications is as follows:hbjiubaubh¹)rp}rq(haUhbjIhjhŒhlh¼hn}rr(h¾X-hs]hr]hp]hq]hv]uhxKOhyhhz]rs(hÀ)rt}ru(haXptp4l: It is the main program that implements the Precision Time Protocol (PTP) according to IEEE standard 1588 for Linux, as a Boundary Clock (BC) and Ordinary Clock (OC). The 'slave' and 'master' roles are determined for each port automatically using the BMChbjphjhŒhlhÃhn}rv(hp]hq]hr]hs]hv]uhxNhyhhz]rwh§)rx}ry(haXptp4l: It is the main program that implements the Precision Time Protocol (PTP) according to IEEE standard 1588 for Linux, as a Boundary Clock (BC) and Ordinary Clock (OC). The 'slave' and 'master' roles are determined for each port automatically using the BMCrzhbjthjhŒhlh«hn}r{(hp]hq]hr]hs]hv]uhxKOhz]r|hƒXptp4l: It is the main program that implements the Precision Time Protocol (PTP) according to IEEE standard 1588 for Linux, as a Boundary Clock (BC) and Ordinary Clock (OC). The 'slave' and 'master' roles are determined for each port automatically using the BMCr}…r~}r(hajzhbjxubaubaubhÀ)r€}r(haXSphc2sys: It is a utility program to synchronize the normal Linux system time to a PTP Hardware Clock - which itself is synchronized by the ptp4l program/application. For phc2sys, the terms 'slave' and 'master' are not about the PTP, but rather about two local clocks. Usually, the Linux system time is the slave, and the PHC is the master.hbjphjhŒhlhÃhn}r‚(hp]hq]hr]hs]hv]uhxNhyhhz]rƒh§)r„}r…(haXSphc2sys: It is a utility program to synchronize the normal Linux system time to a PTP Hardware Clock - which itself is synchronized by the ptp4l program/application. For phc2sys, the terms 'slave' and 'master' are not about the PTP, but rather about two local clocks. Usually, the Linux system time is the slave, and the PHC is the master.r†hbj€hjhŒhlh«hn}r‡(hp]hq]hr]hs]hv]uhxKShz]rˆhƒXSphc2sys: It is a utility program to synchronize the normal Linux system time to a PTP Hardware Clock - which itself is synchronized by the ptp4l program/application. For phc2sys, the terms 'slave' and 'master' are not about the PTP, but rather about two local clocks. Usually, the Linux system time is the slave, and the PHC is the master.r‰…rŠ}r‹(haj†hbj„ubaubaubhÀ)rŒ}r(haXápmc: This is a utility program for sending PTP management queries. The program reads from the standard input actions specified by name and management ID, sends them over the selected transport and prints any received replies.hbjphjhŒhlhÃhn}rŽ(hp]hq]hr]hs]hv]uhxNhyhhz]rh§)r}r‘(haXápmc: This is a utility program for sending PTP management queries. The program reads from the standard input actions specified by name and management ID, sends them over the selected transport and prints any received replies.r’hbjŒhjhŒhlh«hn}r“(hp]hq]hr]hs]hv]uhxKYhz]r”hƒXápmc: This is a utility program for sending PTP management queries. The program reads from the standard input actions specified by name and management ID, sends them over the selected transport and prints any received replies.r•…r–}r—(haj’hbjubaubaubhÀ)r˜}r™(haX’hwstamp\_ctl: It is just a test program for the SIOCSHWTSTAMP ioctl, used for debugging. The ptp4l program does not need this program to function hbjphjhŒhlhÃhn}rš(hp]hq]hr]hs]hv]uhxNhyhhz]r›h§)rœ}r(haX‘hwstamp\_ctl: It is just a test program for the SIOCSHWTSTAMP ioctl, used for debugging. The ptp4l program does not need this program to functionhbj˜hjhŒhlh«hn}rž(hp]hq]hr]hs]hv]uhxK]hz]rŸhƒXhwstamp_ctl: It is just a test program for the SIOCSHWTSTAMP ioctl, used for debugging. The ptp4l program does not need this program to functionr …r¡}r¢(haX‘hwstamp\_ctl: It is just a test program for the SIOCSHWTSTAMP ioctl, used for debugging. The ptp4l program does not need this program to functionhbjœubaubaubeubh§)r£}r¤(haX‰TI has forked LinuxPTP to add support for Sitara family of devices, and the repo is hosted here: http://git.ti.com/processor-sdk/linuxptphbjIhjhŒhlh«hn}r¥(hp]hq]hr]hs]hv]uhxKahyhhz]r¦(hƒXaTI has forked LinuxPTP to add support for Sitara family of devices, and the repo is hosted here: r§…r¨}r©(haXaTI has forked LinuxPTP to add support for Sitara family of devices, and the repo is hosted here: hbj£ubj_)rª}r«(haX(http://git.ti.com/processor-sdk/linuxptpr¬hn}r­(Urefurij¬hs]hr]hp]hq]hv]uhbj£hz]r®hƒX(http://git.ti.com/processor-sdk/linuxptpr¯…r°}r±(haUhbjªubahljhubeubeubeubhc)r²}r³(haUh˜KhbhhhjhŒhlhmhn}r´(hp]rµXhardware overviewr¶ahq]hr]hs]r·Uhardware-overviewr¸ahv]uhxKehyhhz]r¹(h|)rº}r»(haXHardware Overviewr¼hbj²hjhŒhlh€hn}r½(hp]hq]hr]hs]hv]uhxKehyhhz]r¾hƒXHardware Overviewr¿…rÀ}rÁ(haj¼hbjºubaubh§)rÂ}rÃ(haX\TI’s Sitara devices have support for GMAC and PRU-ICSS ports, as shown in the table below.rÄhbj²hjhŒhlh«hn}rÅ(hp]hq]hr]hs]hv]uhxKghyhhz]rÆhƒX\TI’s Sitara devices have support for GMAC and PRU-ICSS ports, as shown in the table below.rÇ…rÈ}rÉ(hajÄhbjÂubaubcdocutils.nodes table rÊ)rË}rÌ(haUhbj²hjhŒhlUtablerÍhn}rÎ(hp]hq]hr]hs]hv]uhxNhyhhz]rÏcdocutils.nodes tgroup rÐ)rÑ}rÒ(haUhn}rÓ(hs]hr]hp]hq]hv]UcolsKuhbjËhz]rÔ(cdocutils.nodes colspec rÕ)rÖ}r×(haUhn}rØ(hs]hr]hp]hq]hv]UcolwidthKuhbjÑhz]hlUcolspecrÙubjÕ)rÚ}rÛ(haUhn}rÜ(hs]hr]hp]hq]hv]UcolwidthKuhbjÑhz]hljÙubjÕ)rÝ}rÞ(haUhn}rß(hs]hr]hp]hq]hv]UcolwidthKuhbjÑhz]hljÙubjÕ)rà}rá(haUhn}râ(hs]hr]hp]hq]hv]UcolwidthKuhbjÑhz]hljÙubcdocutils.nodes thead rã)rä}rå(haUhn}ræ(hp]hq]hr]hs]hv]uhbjÑhz]rçcdocutils.nodes row rè)ré}rê(haUhn}rë(hp]hq]hr]hs]hv]uhbjähz]rì(cdocutils.nodes entry rí)rî}rï(haUhn}rð(hp]hq]hr]hs]hv]uhbjéhz]rñh§)rò}ró(haXSoCrôhbjîhjhŒhlh«hn}rõ(hp]hq]hr]hs]hv]uhxKkhz]röhƒXSoCr÷…rø}rù(hajôhbjòubaubahlUentryrúubjí)rû}rü(haUhn}rý(hp]hq]hr]hs]hv]uhbjéhz]rþh§)rÿ}r(haX# of GMAC portsrhbjûhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxKkhz]rhƒX# of GMAC portsr…r}r(hajhbjÿubaubahljúubjí)r}r(haUhn}r (hp]hq]hr]hs]hv]uhbjéhz]r h§)r }r (haX# of PRU-ICSS portsr hbjhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxKkhz]rhƒX# of PRU-ICSS portsr…r}r(haj hbj ubaubahljúubjí)r}r(haUhn}r(hp]hq]hr]hs]hv]uhbjéhz]rh§)r}r(haXPRU Firmware SupportedrhbjhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxKkhz]rhƒXPRU Firmware Supportedr…r}r(hajhbjubaubahljúubehlUrowrubahlUtheadr ubcdocutils.nodes tbody r!)r"}r#(haUhn}r$(hp]hq]hr]hs]hv]uhbjÑhz]r%(jè)r&}r'(haUhn}r((hp]hq]hr]hs]hv]uhbj"hz]r)(jí)r*}r+(haUhn}r,(hp]hq]hr]hs]hv]uhbj&hz]r-h§)r.}r/(haXAM335xr0hbj*hjhŒhlh«hn}r1(hp]hq]hr]hs]hv]uhxKmhz]r2hƒXAM335xr3…r4}r5(haj0hbj.ubaubahljúubjí)r6}r7(haUhn}r8(hp]hq]hr]hs]hv]uhbj&hz]r9h§)r:}r;(haX1hbj6hjhŒhlh«hn}r<(hp]hq]hr]hs]hv]uhxKmhz]r=hƒX1…r>}r?(haX1hbj:ubaubahljúubjí)r@}rA(haUhn}rB(hp]hq]hr]hs]hv]uhbj&hz]rCh§)rD}rE(haX 2(at 100Mbps)rFhbj@hjhŒhlh«hn}rG(hp]hq]hr]hs]hv]uhxKmhz]rHhƒX 2(at 100Mbps)rI…rJ}rK(hajFhbjDubaubahljúubjí)rL}rM(haUhn}rN(hp]hq]hr]hs]hv]uhbj&hz]rOh§)rP}rQ(haXDual EMAC / HSR / PRPrRhbjLhjhŒhlh«hn}rS(hp]hq]hr]hs]hv]uhxKmhz]rThƒXDual EMAC / HSR / PRPrU…rV}rW(hajRhbjPubaubahljúubehljubjè)rX}rY(haUhn}rZ(hp]hq]hr]hs]hv]uhbj"hz]r[(jí)r\}r](haUhn}r^(hp]hq]hr]hs]hv]uhbjXhz]r_h§)r`}ra(haXAM437xrbhbj\hjhŒhlh«hn}rc(hp]hq]hr]hs]hv]uhxKohz]rdhƒXAM437xre…rf}rg(hajbhbj`ubaubahljúubjí)rh}ri(haUhn}rj(hp]hq]hr]hs]hv]uhbjXhz]rkh§)rl}rm(haX1hbjhhjhŒhlh«hn}rn(hp]hq]hr]hs]hv]uhxKohz]rohƒX1…rp}rq(haX1hbjlubaubahljúubjí)rr}rs(haUhn}rt(hp]hq]hr]hs]hv]uhbjXhz]ruh§)rv}rw(haX 2(at 100Mbps)rxhbjrhjhŒhlh«hn}ry(hp]hq]hr]hs]hv]uhxKohz]rzhƒX 2(at 100Mbps)r{…r|}r}(hajxhbjvubaubahljúubjí)r~}r(haUhn}r€(hp]hq]hr]hs]hv]uhbjXhz]rh§)r‚}rƒ(haXDual EMAC / HSR / PRPr„hbj~hjhŒhlh«hn}r…(hp]hq]hr]hs]hv]uhxKohz]r†hƒXDual EMAC / HSR / PRPr‡…rˆ}r‰(haj„hbj‚ubaubahljúubehljubjè)rŠ}r‹(haUhn}rŒ(hp]hq]hr]hs]hv]uhbj"hz]r(jí)rŽ}r(haUhn}r(hp]hq]hr]hs]hv]uhbjŠhz]r‘h§)r’}r“(haXAM571xr”hbjŽhjhŒhlh«hn}r•(hp]hq]hr]hs]hv]uhxKqhz]r–hƒXAM571xr—…r˜}r™(haj”hbj’ubaubahljúubjí)rš}r›(haUhn}rœ(hp]hq]hr]hs]hv]uhbjŠhz]rh§)rž}rŸ(haX1hbjšhjhŒhlh«hn}r (hp]hq]hr]hs]hv]uhxKqhz]r¡hƒX1…r¢}r£(haX1hbjžubaubahljúubjí)r¤}r¥(haUhn}r¦(hp]hq]hr]hs]hv]uhbjŠhz]r§h§)r¨}r©(haX 4(at 100Mbps)rªhbj¤hjhŒhlh«hn}r«(hp]hq]hr]hs]hv]uhxKqhz]r¬hƒX 4(at 100Mbps)r­…r®}r¯(hajªhbj¨ubaubahljúubjí)r°}r±(haUhn}r²(hp]hq]hr]hs]hv]uhbjŠhz]r³h§)r´}rµ(haXDual EMAC / HSR / PRPr¶hbj°hjhŒhlh«hn}r·(hp]hq]hr]hs]hv]uhxKqhz]r¸hƒXDual EMAC / HSR / PRPr¹…rº}r»(haj¶hbj´ubaubahljúubehljubjè)r¼}r½(haUhn}r¾(hp]hq]hr]hs]hv]uhbj"hz]r¿(jí)rÀ}rÁ(haUhn}rÂ(hp]hq]hr]hs]hv]uhbj¼hz]rÃh§)rÄ}rÅ(haXAM572xrÆhbjÀhjhŒhlh«hn}rÇ(hp]hq]hr]hs]hv]uhxKshz]rÈhƒXAM572xrÉ…rÊ}rË(hajÆhbjÄubaubahljúubjí)rÌ}rÍ(haUhn}rÎ(hp]hq]hr]hs]hv]uhbj¼hz]rÏh§)rÐ}rÑ(haX1hbjÌhjhŒhlh«hn}rÒ(hp]hq]hr]hs]hv]uhxKshz]rÓhƒX1…rÔ}rÕ(haX1hbjÐubaubahljúubjí)rÖ}r×(haUhn}rØ(hp]hq]hr]hs]hv]uhbj¼hz]rÙh§)rÚ}rÛ(haX 2(at 100Mbps)rÜhbjÖhjhŒhlh«hn}rÝ(hp]hq]hr]hs]hv]uhxKshz]rÞhƒX 2(at 100Mbps)rß…rà}rá(hajÜhbjÚubaubahljúubjí)râ}rã(haUhn}rä(hp]hq]hr]hs]hv]uhbj¼hz]råh§)ræ}rç(haXDual EMAC / HSR / PRPrèhbjâhjhŒhlh«hn}ré(hp]hq]hr]hs]hv]uhxKshz]rêhƒXDual EMAC / HSR / PRPrë…rì}rí(hajèhbjæubaubahljúubehljubjè)rî}rï(haUhn}rð(hp]hq]hr]hs]hv]uhbj"hz]rñ(jí)rò}ró(haUhn}rô(hp]hq]hr]hs]hv]uhbjîhz]rõh§)rö}r÷(haXAM574xrøhbjòhjhŒhlh«hn}rù(hp]hq]hr]hs]hv]uhxKuhz]rúhƒXAM574xrû…rü}rý(hajøhbjöubaubahljúubjí)rþ}rÿ(haUhn}r(hp]hq]hr]hs]hv]uhbjîhz]rh§)r}r(haX1hbjþhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxKuhz]rhƒX1…r}r(haX1hbjubaubahljúubjí)r}r (haUhn}r (hp]hq]hr]hs]hv]uhbjîhz]r h§)r }r (haX 2(at 100Mbps)rhbjhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxKuhz]rhƒX 2(at 100Mbps)r…r}r(hajhbj ubaubahljúubjí)r}r(haUhn}r(hp]hq]hr]hs]hv]uhbjîhz]rh§)r}r(haXDual EMAC / HSR / PRPrhbjhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxKuhz]rhƒXDual EMAC / HSR / PRPr…r}r(hajhbjubaubahljúubehljubjè)r }r!(haUhn}r"(hp]hq]hr]hs]hv]uhbj"hz]r#(jí)r$}r%(haUhn}r&(hp]hq]hr]hs]hv]uhbj hz]r'h§)r(}r)(haXK2Gr*hbj$hjhŒhlh«hn}r+(hp]hq]hr]hs]hv]uhxKwhz]r,hƒXK2Gr-…r.}r/(haj*hbj(ubaubahljúubjí)r0}r1(haUhn}r2(hp]hq]hr]hs]hv]uhbj hz]r3h§)r4}r5(haX1hbj0hjhŒhlh«hn}r6(hp]hq]hr]hs]hv]uhxKwhz]r7hƒX1…r8}r9(haX1hbj4ubaubahljúubjí)r:}r;(haUhn}r<(hp]hq]hr]hs]hv]uhbj hz]r=h§)r>}r?(haX 4(at 100Mbps)r@hbj:hjhŒhlh«hn}rA(hp]hq]hr]hs]hv]uhxKwhz]rBhƒX 4(at 100Mbps)rC…rD}rE(haj@hbj>ubaubahljúubjí)rF}rG(haUhn}rH(hp]hq]hr]hs]hv]uhbj hz]rIh§)rJ}rK(haXDual EMAC / HSR / PRPrLhbjFhjhŒhlh«hn}rM(hp]hq]hr]hs]hv]uhxKwhz]rNhƒXDual EMAC / HSR / PRPrO…rP}rQ(hajLhbjJubaubahljúubehljubehlUtbodyrRubehlUtgrouprSubaubh§)rT}rU(haX@When using PTP as SAN port, only 1 port of each PRU-ICSS can independently support PTP at a time e.g. on AM571x, there are 4 PRU-ICSS ports, but only 1 from each of the 2 PRU-ICSS can be used as SAN PTP ports independently (as OC slaves) for a total of 2 ports since each PRU-ICSS functions as a single PTP clock entity.rVhbj²hjhŒhlh«hn}rW(hp]hq]hr]hs]hv]uhxKzhyhhz]rXhƒX@When using PTP as SAN port, only 1 port of each PRU-ICSS can independently support PTP at a time e.g. on AM571x, there are 4 PRU-ICSS ports, but only 1 from each of the 2 PRU-ICSS can be used as SAN PTP ports independently (as OC slaves) for a total of 2 ports since each PRU-ICSS functions as a single PTP clock entity.rY…rZ}r[(hajVhbjTubaubhc)r\}r](haUh˜Khbj²hjhŒhlhmhn}r^(hp]r_Xgmacr`ahq]hr]hs]raUgmacrbahv]uhxKhyhhz]rc(h|)rd}re(haXGMACrfhbj\hjhŒhlh€hn}rg(hp]hq]hr]hs]hv]uhxKhyhhz]rhhƒXGMACri…rj}rk(hajfhbjdubaubh§)rl}rm(haXýGMAC interface can be configured to run at either 100 Mbps or 1 Gbps. CPTS hardware block helps with timestamping of packets. Refer to `here `__ for details.hbj\hjhŒhlh«hn}rn(hp]hq]hr]hs]hv]uhxKƒhyhhz]ro(hƒX‡GMAC interface can be configured to run at either 100 Mbps or 1 Gbps. CPTS hardware block helps with timestamping of packets. Refer to rp…rq}rr(haX‡GMAC interface can be configured to run at either 100 Mbps or 1 Gbps. CPTS hardware block helps with timestamping of packets. Refer to hbjlubj_)rs}rt(haXi`here `__hn}ru(UnameXhereUrefurirvX^Foundational_Components/Kernel/Kernel_Drivers/Network/CPSW.html#common-platform-time-sync-cptshs]hr]hp]hq]hv]uhbjlhz]rwhƒXhererx…ry}rz(haUhbjsubahljhubhƒX for details.r{…r|}r}(haX for details.hbjlubeubeubhc)r~}r(haUhbj²hjhŒhlhmhn}r€(hp]hq]hr]hs]rUpru-icssr‚ahv]rƒh;auhxK‰hyhhz]r„(h|)r…}r†(haXPRU-ICSSr‡hbj~hjhŒhlh€hn}rˆ(hp]hq]hr]hs]hv]uhxK‰hyhhz]r‰hƒXPRU-ICSSrŠ…r‹}rŒ(haj‡hbj…ubaubh§)r}rŽ(haXTThe processing load is shared between firmware (PRU) and Host (ARM) with the firmware doing most of the time critical activities. The IEP hardware block in the PRU-ICSS sub-system is responsible for timestamping of packets. Memory map for the firmware interface for HSR/PRP firmware can be found in :ref:`HSR_PRP_Firmware_Memory_Map_label`.hbj~hjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxK‹hyhhz]r(hƒX+The processing load is shared between firmware (PRU) and Host (ARM) with the firmware doing most of the time critical activities. The IEP hardware block in the PRU-ICSS sub-system is responsible for timestamping of packets. Memory map for the firmware interface for HSR/PRP firmware can be found in r‘…r’}r“(haX+The processing load is shared between firmware (PRU) and Host (ARM) with the firmware doing most of the time critical activities. The IEP hardware block in the PRU-ICSS sub-system is responsible for timestamping of packets. Memory map for the firmware interface for HSR/PRP firmware can be found in hbjubcsphinx.addnodes pending_xref r”)r•}r–(haX(:ref:`HSR_PRP_Firmware_Memory_Map_label`r—hbjhjhŒhlU pending_xrefr˜hn}r™(UreftypeXrefUrefwarnršˆU reftargetr›X!hsr_prp_firmware_memory_map_labelU refdomainXstdrœhs]hr]U refexplicit‰hp]hq]hv]UrefdocrXlinux/Industrial_Protocols_PTPržuhxK‹hz]rŸcdocutils.nodes inline r )r¡}r¢(haj—hn}r£(hp]hq]r¤(Uxrefr¥jœXstd-refr¦ehr]hs]hv]uhbj•hz]r§hƒX!HSR_PRP_Firmware_Memory_Map_labelr¨…r©}rª(haUhbj¡ubahlUinliner«ubaubhƒX.…r¬}r­(haX.hbjubeubcdocutils.nodes target r®)r¯}r°(haX.. _PLSDK_PTP_HW_Mods-label:hbj~hjhŒhlUtargetr±hn}r²(hs]hr]hp]hq]hv]Urefidr³Uplsdk-ptp-hw-mods-labelr´uhxK–hyhhz]ubeubhc)rµ}r¶(haUhbj²hjhŒUexpect_referenced_by_namer·}r¸h?j¯shlhmhn}r¹(hp]hq]hr]hs]rº(Uhardware-modificationsr»j´ehv]r¼(hGh?euhxK”hyhUexpect_referenced_by_idr½}r¾j´j¯shz]r¿(h|)rÀ}rÁ(haXHardware ModificationsrÂhbjµhjhŒhlh€hn}rÃ(hp]hq]hr]hs]hv]uhxK”hyhhz]rÄhƒXHardware ModificationsrÅ…rÆ}rÇ(hajÂhbjÀubaubh¹)rÈ}rÉ(haUhbjµhjhŒhlh¼hn}rÊ(h¾X-hs]hr]hp]hq]hv]uhxK•hyhhz]rË(hÀ)rÌ}rÍ(haX›Hardware modifications are required on the AM57xx IDK platforms to provide access points to 1 PPS sync and latch signals for CPSW/CPTS and PRU-ICSS moduleshbjÈhjhŒhlhÃhn}rÎ(hp]hq]hr]hs]hv]uhxNhyhhz]rÏh§)rÐ}rÑ(haX›Hardware modifications are required on the AM57xx IDK platforms to provide access points to 1 PPS sync and latch signals for CPSW/CPTS and PRU-ICSS modulesrÒhbjÌhjhŒhlh«hn}rÓ(hp]hq]hr]hs]hv]uhxK•hz]rÔhƒX›Hardware modifications are required on the AM57xx IDK platforms to provide access points to 1 PPS sync and latch signals for CPSW/CPTS and PRU-ICSS modulesrÕ…rÖ}r×(hajÒhbjÐubaubaubhÀ)rØ}rÙ(haXFor Boundary Clock, since PPS generated by one internal clock needs to be latched into another internal clock, hardware, mainly blue wire, modifications are needed in order to achieive the latching of the PPS generated by one internal clock into another internal clock. hbjÈhjhŒhlhÃhn}rÚ(hp]hq]hr]hs]hv]uhxNhyhhz]rÛh§)rÜ}rÝ(haX For Boundary Clock, since PPS generated by one internal clock needs to be latched into another internal clock, hardware, mainly blue wire, modifications are needed in order to achieive the latching of the PPS generated by one internal clock into another internal clock.rÞhbjØhjhŒhlh«hn}rß(hp]hq]hr]hs]hv]uhxK—hz]ràhƒX For Boundary Clock, since PPS generated by one internal clock needs to be latched into another internal clock, hardware, mainly blue wire, modifications are needed in order to achieive the latching of the PPS generated by one internal clock into another internal clock.rá…râ}rã(hajÞhbjÜubaubaubeubh§)rä}rå(haXOPlease refer to `AM571x-IDK modifications `_ and `AM572x-IDK/AM574x-IDK modifications `_ documents and make the recommended changes to verify OC and BC, and to get access to 1 PPS signalshbjµhjhŒhlh«hn}ræ(hp]hq]hr]hs]hv]uhxKœhyhhz]rç(hƒXPlease refer to rè…ré}rê(haXPlease refer to hbjäubj_)rë}rì(haXb`AM571x-IDK modifications `_hn}rí(UnameXAM571x-IDK modificationsjvXDhttp://processors.wiki.ti.com/images/3/34/Am571x_idk_pps_ModList.pdfrîhs]hr]hp]hq]hv]uhbjähz]rïhƒXAM571x-IDK modificationsrð…rñ}rò(haUhbjëubahljhubj®)ró}rô(haXG h˜Khbjählj±hn}rõ(Urefurijîhs]röUam571x-idk-modificationsr÷ahr]hp]hq]hv]røhauhz]ubhƒX and rù…rú}rû(haX and hbjäubj_)rü}rý(haXu`AM572x-IDK/AM574x-IDK modifications `_hn}rþ(UnameX#AM572x-IDK/AM574x-IDK modificationsjvXKhttp://processors.wiki.ti.com/images/2/2f/Am572x_am574x_idk_pps_ModList.pdfrÿhs]hr]hp]hq]hv]uhbjähz]rhƒX$AM572x-IDK/AM574x-IDK modificationsr…r}r(haUhbjüubahljhubj®)r}r(haXN h˜Khbjählj±hn}r(Urefurijÿhs]rU#am572x-idk-am574x-idk-modificationsrahr]hp]hq]hv]r hauhz]ubhƒXc documents and make the recommended changes to verify OC and BC, and to get access to 1 PPS signalsr …r }r (haXc documents and make the recommended changes to verify OC and BC, and to get access to 1 PPS signalshbjäubeubeubeubhfhc)r }r(haUhbhhhjhŒj·}rhj®)r}r(haX.. _PLSDK_PTP_OC-label:hbhc)r}r(haUhbhfhjhŒhlhmhn}r(hp]hq]hr]hs]rU pps-output-latency-configurationrahv]rhauhxMhyhhz]r(h|)r}r(haX PPS Output Latency ConfigurationrhbjhjhŒhlh€hn}r(hp]hq]hr]hs]hv]uhxMhyhhz]rhƒX PPS Output Latency Configurationr…r}r (hajhbjubaubh§)r!}r"(haXIt should be possible to configure the latency of the 1PPS output of GMAC, PRU_ICSS to compensate for local propagation delay or for testing purpose. A new PTP interface has been defined and implemented to allow the PPS output latency to be adjusted in unit of ns.r#hbjhjhŒhlh«hn}r$(hp]hq]hr]hs]hv]uhxMhyhhz]r%hƒXIt should be possible to configure the latency of the 1PPS output of GMAC, PRU_ICSS to compensate for local propagation delay or for testing purpose. A new PTP interface has been defined and implemented to allow the PPS output latency to be adjusted in unit of ns.r&…r'}r((haj#hbj!ubaubh§)r)}r*(haXThe PPS output latency adjustment called PPS Offset can be set through the command interface or as the port configuration parameter of linuxptp.r+hbjhjhŒhlh«hn}r,(hp]hq]hr]hs]hv]uhxM!hyhhz]r-hƒXThe PPS output latency adjustment called PPS Offset can be set through the command interface or as the port configuration parameter of linuxptp.r.…r/}r0(haj+hbj)ubaubh§)r1}r2(haXITo set PPS offset to -10ns on PRU-ICSS port, enter the following command:r3hbjhjhŒhlh«hn}r4(hp]hq]hr]hs]hv]uhxM$hyhhz]r5hƒXITo set PPS offset to -10ns on PRU-ICSS port, enter the following command:r6…r7}r8(haj3hbj1ubaubcdocutils.nodes literal_block r9)r:}r;(haX?echo -10 > /sys/devices/platform/pruss2_eth/ptp/ptp1/pps_offsethbjhjhŒhlU literal_blockr<hn}r=(hh‘hs]hr]hp]hq]hv]uhxM-hyhhz]r>hƒX?echo -10 > /sys/devices/platform/pruss2_eth/ptp/ptp1/pps_offsetr?…r@}rA(haUhbj:ubaubh§)rB}rC(haXITo set PPS offset to 10ns on GMAC/CPTS port, enter the following command:rDhbjhjhŒhlh«hn}rE(hp]hq]hr]hs]hv]uhxM+hyhhz]rFhƒXITo set PPS offset to 10ns on GMAC/CPTS port, enter the following command:rG…rH}rI(hajDhbjBubaubj9)rJ}rK(haXRecho 10 > /sys/devices/platform/44000000.ocp/48484000.ethernet/ptp/ptp0/pps_offsethbjhjhŒhlj<hn}rL(hh‘hs]hr]hp]hq]hv]uhxM4hyhhz]rMhƒXRecho 10 > /sys/devices/platform/44000000.ocp/48484000.ethernet/ptp/ptp0/pps_offsetrN…rO}rP(haUhbjJubaubh§)rQ}rR(haXcTo configure the PPS offset of eth2 to 20ns, add the following line to the OC/BC configuration filerShbjhjhŒhlh«hn}rT(hp]hq]hr]hs]hv]uhxM1hyhhz]rUhƒXcTo configure the PPS offset of eth2 to 20ns, add the following line to the OC/BC configuration filerV…rW}rX(hajShbjQubaubj9)rY}rZ(haX[eth2] ppsOffset 20hbjhjhŒhlj<hn}r[(hh‘hs]hr]hp]hq]hv]uhxM;hyhhz]r\hƒX[eth2] ppsOffset 20r]…r^}r_(haUhbjYubaubjeubhjhŒhlj±hn}r`(hs]hr]hp]hq]hv]j³Uplsdk-ptp-oc-labelrauhxM?hyhhz]ubshlhmhn}rb(hp]hq]hr]hs]rc(Uptp-ordinary-clockrdjaehv]re(hheuhxM=hyhj½}rfjajshz]rg(h|)rh}ri(haXPTP Ordinary Clockrjhbj hjhŒhlh€hn}rk(hp]hq]hr]hs]hv]uhxM=hyhhz]rlhƒXPTP Ordinary Clockrm…rn}ro(hajjhbjhubaubh§)rp}rq(haXXPTP ordinary clock (OC) is supported on both the CPSW GMAC ports and the PRU-ICSS ports.rrhbj hjhŒhlh«hn}rs(hp]hq]hr]hs]hv]uhxM?hyhhz]rthƒXXPTP ordinary clock (OC) is supported on both the CPSW GMAC ports and the PRU-ICSS ports.ru…rv}rw(hajrhbjpubaubh§)rx}ry(haX0The **IEEE-1588-2009** standard defines **ordinary clock** as "A clock that has a single Precision Time Protocol (PTP) port in a domain and maintains the timescale used in the domain. It may serve as a source of time, i.e., be a master clock, or may synchronize to another clock, i.e., be a slave clock."hbj hjhŒhlh«hn}rz(hp]hq]hr]hs]hv]uhxMBhyhhz]r{(hƒXThe r|…r}}r~(haXThe hbjxubcdocutils.nodes strong r)r€}r(haX**IEEE-1588-2009**hn}r‚(hp]hq]hr]hs]hv]uhbjxhz]rƒhƒXIEEE-1588-2009r„…r…}r†(haUhbj€ubahlUstrongr‡ubhƒX standard defines rˆ…r‰}rŠ(haX standard defines hbjxubj)r‹}rŒ(haX**ordinary clock**hn}r(hp]hq]hr]hs]hv]uhbjxhz]rŽhƒXordinary clockr…r}r‘(haUhbj‹ubahlj‡ubhƒXö as "A clock that has a single Precision Time Protocol (PTP) port in a domain and maintains the timescale used in the domain. It may serve as a source of time, i.e., be a master clock, or may synchronize to another clock, i.e., be a slave clock."r’…r“}r”(haXö as "A clock that has a single Precision Time Protocol (PTP) port in a domain and maintains the timescale used in the domain. It may serve as a source of time, i.e., be a master clock, or may synchronize to another clock, i.e., be a slave clock."hbjxubeubh§)r•}r–(haXNAt the heart of the ordinary clock support is the capability of being able to timestamp the PTP event messages that passes through the different Ethernet ports. It is the CPTS module that does the timestamping for the CPSW GMAC ports. For PRU-ICSS ports, it is the IEP module together with the PRU firmware that does the timestamping.r—hbj hjhŒhlh«hn}r˜(hp]hq]hr]hs]hv]uhxMHhyhhz]r™hƒXNAt the heart of the ordinary clock support is the capability of being able to timestamp the PTP event messages that passes through the different Ethernet ports. It is the CPTS module that does the timestamping for the CPSW GMAC ports. For PRU-ICSS ports, it is the IEP module together with the PRU firmware that does the timestamping.rš…r›}rœ(haj—hbj•ubaubcdocutils.nodes rubric r)rž}rŸ(haXPHY Delay Compensationr hbj hjhŒhlUrubricr¡hn}r¢(hs]r£Uphy-delay-compensationr¤ahr]hp]hq]hv]r¥h auhxNhyhhz]r¦hƒXPHY Delay Compensationr§…r¨}r©(haj hbjžubaubh§)rª}r«(haXÍThe IEEE1588 timestamp should be measured at the Ethernet wire and therefore the ideal place to measure the egress/ingress timestamp of the Ethernet packets is at the Ethernet PHY. Unfortunately it is usually not the case. The delay between the actual timestamp location and the ideal location at the Ethernet wire will add to the path delay and create error of the path delay and offset of the system timestamp if the egress and ingress delay is not symmetric.r¬hbj hjhŒhlh«hn}r­(hp]hq]hr]hs]hv]uhxMQhyhhz]r®hƒXÍThe IEEE1588 timestamp should be measured at the Ethernet wire and therefore the ideal place to measure the egress/ingress timestamp of the Ethernet packets is at the Ethernet PHY. Unfortunately it is usually not the case. The delay between the actual timestamp location and the ideal location at the Ethernet wire will add to the path delay and create error of the path delay and offset of the system timestamp if the egress and ingress delay is not symmetric.r¯…r°}r±(haj¬hbjªubaubh§)r²}r³(haXThe Linux PTP software stack is designed to handle those delays with environment variable egressLatency and ingressLatency. Both delay number should be calculated or measured and used at the PTP configuration file. In the case that those two number are not available, use the following formulas to adjust those two variables as long as the measured path delay by Linux PTP is positive.r´hbj hjhŒhlh«hn}rµ(hp]hq]hr]hs]hv]uhxMYhyhhz]r¶hƒXThe Linux PTP software stack is designed to handle those delays with environment variable egressLatency and ingressLatency. Both delay number should be calculated or measured and used at the PTP configuration file. In the case that those two number are not available, use the following formulas to adjust those two variables as long as the measured path delay by Linux PTP is positive.r·…r¸}r¹(haj´hbj²ubaubj9)rº}r»(haX©To reduce the 1PPS offset by x, increase the asymmetry delay compensation by 2x To reduce the end-to-end delay by y, increase both ingressLatency and egressLatency by y.hbj hjhŒhlj<hn}r¼(hh‘hs]hr]hp]hq]hv]uhxMghyhhz]r½hƒX©To reduce the 1PPS offset by x, increase the asymmetry delay compensation by 2x To reduce the end-to-end delay by y, increase both ingressLatency and egressLatency by y.r¾…r¿}rÀ(haUhbjºubaubhc)rÁ}rÂ(haUhbj hjhŒhlhmhn}rÃ(hp]hq]hr]hs]rÄUptp-ordinary-clock-on-pru-icssrÅahv]rÆhBauhxMfhyhhz]rÇ(h|)rÈ}rÉ(haXPTP Ordinary Clock on PRU-ICSSrÊhbjÁhjhŒhlh€hn}rË(hp]hq]hr]hs]hv]uhxMfhyhhz]rÌhƒXPTP Ordinary Clock on PRU-ICSSrÍ…rÎ}rÏ(hajÊhbjÈubaubh§)rÐ}rÑ(haX$Timestamping of PTP event messages at the PRU-ICSS ports is provided by the PRU-ICSS IEP module together with the PRU firmware. PTP is supported via the Dual EMAC firmware, PRP firmware (configured in SAN (Single Attached Node). PTP with redundancy is supported via both HSR and PRP firmware.rÒhbjÁhjhŒhlh«hn}rÓ(hp]hq]hr]hs]hv]uhxMhhyhhz]rÔhƒX$Timestamping of PTP event messages at the PRU-ICSS ports is provided by the PRU-ICSS IEP module together with the PRU firmware. PTP is supported via the Dual EMAC firmware, PRP firmware (configured in SAN (Single Attached Node). PTP with redundancy is supported via both HSR and PRP firmware.rÕ…rÖ}r×(hajÒhbjÐubaubh§)rØ}rÙ(haX’In this Linux PRU-ICSS OC implementation, the PRU firmware stores timestamps (IEP counter values) of PTP event messages in specific shared memory locations. The PRU IEP driver retrieves the timestamps and converts them into PTP time values (in nanoseconds) before they are passed to upper layer for further processing. The current PRU-ICSS PTP clock frequency and time scale are kept in the IEP driver.rÚhbjÁhjhŒhlh«hn}rÛ(hp]hq]hr]hs]hv]uhxMnhyhhz]rÜhƒX’In this Linux PRU-ICSS OC implementation, the PRU firmware stores timestamps (IEP counter values) of PTP event messages in specific shared memory locations. The PRU IEP driver retrieves the timestamps and converts them into PTP time values (in nanoseconds) before they are passed to upper layer for further processing. The current PRU-ICSS PTP clock frequency and time scale are kept in the IEP driver.rÝ…rÞ}rß(hajÚhbjØubaubh§)rà}rá(haXSince the PRU IEP drivers implements the Linux PTP hardware clock subsystem APIs, the PRU-ICSS PTP clock can therefore be adjusted by using those standard APIs. See `PTP hardware clock infrastructure for Linux `__ for more details.hbjÁhjhŒhlh«hn}râ(hp]hq]hr]hs]hv]uhxMuhyhhz]rã(hƒX¥Since the PRU IEP drivers implements the Linux PTP hardware clock subsystem APIs, the PRU-ICSS PTP clock can therefore be adjusted by using those standard APIs. See rä…rå}ræ(haX¥Since the PRU IEP drivers implements the Linux PTP hardware clock subsystem APIs, the PRU-ICSS PTP clock can therefore be adjusted by using those standard APIs. See hbjàubj_)rç}rè(haXg`PTP hardware clock infrastructure for Linux `__hn}ré(UnameX+PTP hardware clock infrastructure for LinuxjvX5https://www.kernel.org/doc/Documentation/ptp/ptp.txt#hs]hr]hp]hq]hv]uhbjàhz]rêhƒX+PTP hardware clock infrastructure for Linuxrë…rì}rí(haUhbjçubahljhubhƒX for more details.rî…rï}rð(haX for more details.hbjàubeubh§)rñ}rò(haX<The PTP OC protocol is provided by the linuxptp application.róhbjÁhjhŒhlh«hn}rô(hp]hq]hr]hs]hv]uhxM{hyhhz]rõhƒX<The PTP OC protocol is provided by the linuxptp application.rö…r÷}rø(hajóhbjñubaubh§)rù}rú(haXzIf using PRP firmware for SAN, follow the steps at :ref:`PLSDK_PRP_EMAC_Mode-label` to boot up the AM57xx IDK and configure the PRU-PRP firmware to run in **PRP\_EMAC** mode (not needed if using Dual EMAC firmware). Once the AM57xx IDK is boot into Linux kernel prompt and the PRU-ICSS Ethernet ports are properly configured, to run linuxptp over the PRU-ICSS Ethernet ports, dohbjÁhjhŒhlh«hn}rû(hp]hq]hr]hs]hv]uhxM}hyhhz]rü(hƒX3If using PRP firmware for SAN, follow the steps at rý…rþ}rÿ(haX3If using PRP firmware for SAN, follow the steps at hbjùubj”)r}r(haX :ref:`PLSDK_PRP_EMAC_Mode-label`rhbjùhjhŒhlj˜hn}r(UreftypeXrefjšˆj›Xplsdk_prp_emac_mode-labelU refdomainXstdrhs]hr]U refexplicit‰hp]hq]hv]jjžuhxM}hz]rj )r}r(hajhn}r(hp]hq]r (j¥jXstd-refr ehr]hs]hv]uhbjhz]r hƒXPLSDK_PRP_EMAC_Mode-labelr …r }r(haUhbjubahlj«ubaubhƒXH to boot up the AM57xx IDK and configure the PRU-PRP firmware to run in r…r}r(haXH to boot up the AM57xx IDK and configure the PRU-PRP firmware to run in hbjùubj)r}r(haX **PRP\_EMAC**hn}r(hp]hq]hr]hs]hv]uhbjùhz]rhƒXPRP_EMACr…r}r(haUhbjubahlj‡ubhƒXÒ mode (not needed if using Dual EMAC firmware). Once the AM57xx IDK is boot into Linux kernel prompt and the PRU-ICSS Ethernet ports are properly configured, to run linuxptp over the PRU-ICSS Ethernet ports, dor…r}r(haXÒ mode (not needed if using Dual EMAC firmware). Once the AM57xx IDK is boot into Linux kernel prompt and the PRU-ICSS Ethernet ports are properly configured, to run linuxptp over the PRU-ICSS Ethernet ports, dohbjùubeubj9)r}r(haXptp4l -f oc.cfghbjÁhjhŒhlj<hn}r(hh‘hs]hr]hp]hq]hv]uhxMŠhyhhz]rhƒXptp4l -f oc.cfgr …r!}r"(haUhbjubaubh§)r#}r$(haX%oc.cfg is a ptp4l configuration file.r%hbjÁhjhŒhlh«hn}r&(hp]hq]hr]hs]hv]uhxM‡hyhhz]r'hƒX%oc.cfg is a ptp4l configuration file.r(…r)}r*(haj%hbj#ubaubh§)r+}r,(haXExample oc.cfg for OC,r-hbjÁhjhŒhlh«hn}r.(hp]hq]hr]hs]hv]uhxM‰hyhhz]r/hƒXExample oc.cfg for OC,r0…r1}r2(haj-hbj+ubaubj9)r3}r4(haXÄ[global] tx_timestamp_timeout 10 logMinPdelayReqInterval -3 logSyncInterval -3 twoStepFlag 1 summary_interval 0 [eth2] egressLatency 726 ingressLatency 186 delay_mechanism P2P network_transport L2hbjÁhjhŒhlj<hn}r5(hh‘hs]hr]hp]hq]hv]uhxM’hyhhz]r6hƒXÄ[global] tx_timestamp_timeout 10 logMinPdelayReqInterval -3 logSyncInterval -3 twoStepFlag 1 summary_interval 0 [eth2] egressLatency 726 ingressLatency 186 delay_mechanism P2P network_transport L2r7…r8}r9(haUhbj3ubaubh§)r:}r;(haXbwhere **eth2** is the intended PRU-ICSS Ethernet port over which the OC functionality is provided.hbjÁhjhŒhlh«hn}r<(hp]hq]hr]hs]hv]uhxM™hyhhz]r=(hƒXwhere r>…r?}r@(haXwhere hbj:ubj)rA}rB(haX**eth2**hn}rC(hp]hq]hr]hs]hv]uhbj:hz]rDhƒXeth2rE…rF}rG(haUhbjAubahlj‡ubhƒXT is the intended PRU-ICSS Ethernet port over which the OC functionality is provided.rH…rI}rJ(haXT is the intended PRU-ICSS Ethernet port over which the OC functionality is provided.hbj:ubeubh§)rK}rL(haXÎSee `The Linux PTP Project `__ for more details about linuxptp in general and `ptp4l(8) - Linux man page `__ about ptp4l configurations in particular.hbjÁhjhŒhlh«hn}rM(hp]hq]hr]hs]hv]uhxMœhyhhz]rN(hƒXSee rO…rP}rQ(haXSee hbjKubj_)rR}rS(haX<`The Linux PTP Project `__hn}rT(UnameXThe Linux PTP ProjectjvX http://linuxptp.sourceforge.net#hs]hr]hp]hq]hv]uhbjKhz]rUhƒXThe Linux PTP ProjectrV…rW}rX(haUhbjRubahljhubhƒX0 for more details about linuxptp in general and rY…rZ}r[(haX0 for more details about linuxptp in general and hbjKubj_)r\}r](haX4`ptp4l(8) - Linux man page `__hn}r^(UnameXptp4l(8) - Linux man pagejvXhttps://man.cx/ptp4lhs]hr]hp]hq]hv]uhbjKhz]r_hƒXptp4l(8) - Linux man pager`…ra}rb(haUhbj\ubahljhubhƒX* about ptp4l configurations in particular.rc…rd}re(haX* about ptp4l configurations in particular.hbjKubeubh§)rf}rg(haX\Here is a sample screen display of ptp4l for PRU-ICSS Ethernet port as PTP/OC in slave mode:rhhbjÁhjhŒhlh«hn}ri(hp]hq]hr]hs]hv]uhxM hyhhz]rjhƒX\Here is a sample screen display of ptp4l for PRU-ICSS Ethernet port as PTP/OC in slave mode:rk…rl}rm(hajhhbjfubaubj9)rn}ro(haXÊptp4l -f oc.txt -s -m & [1] 1153 root@am57xx-evm:~# ptp4l[3777.676]: selected /dev/ptp1 as PTP clock ptp4l[3777.740]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE ptp4l[3777.743]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE ptp4l[3777.744]: port 1: received PDELAY_REQ without timestamp ptp4l[3778.727]: port 1: new foreign master 8ca5a1.fffe.0000c2-1 ptp4l[3782.727]: selected best master clock 8ca5a1.fffe.0000c2 ptp4l[3782.727]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE ptp4l[3783.028]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED ptp4l[3783.653]: rms 756344481817248256 max 1512688963634496512 ( -31, 1512688963634496512) freq +2319 +/- 877 delay 12 +/- 0 ptp4l[3784.653]: rms 28 max 32 ( -32, -22) freq +2612 +/- 9 delay 12 +/- 0 ptp4l[3785.778]: rms 16 max 24 ( -24, -11) freq +2604 +/- 3 delay 12 +/- 0 ptp4l[3786.778]: rms 6 max 9 ( -9, -1) freq +2607 +/- 3 delay 12 +/- 1 ptp4l[3787.904]: rms 3 max 6 ( -6, 4) freq +2612 +/- 5 delay 12 +/- 0 ptp4l[3788.904]: rms 6 max 11 ( 4, 11) freq +2624 +/- 2 delay 12 +/- 0 ptp4l[3789.904]: rms 4 max 7 ( -2, 7) freq +2621 +/- 5 delay 12 +/- 0 ptp4l[3790.904]: rms 5 max 10 ( -10, 2) freq +2613 +/- 5 delay 11 +/- 0 ptp4l[3791.904]: rms 6 max 10 ( -10, 0) freq +2606 +/- 4 delay 12 +/- 1 ptp4l[3792.904]: rms 3 max 6 ( -4, 6) freq +2610 +/- 4 delay 11 +/- 1 ptp4l[3793.904]: rms 6 max 11 ( 0, 11) freq +2618 +/- 6 delay 12 +/- 0 ptp4l[3794.904]: rms 4 max 8 ( -5, 8) freq +2618 +/- 5 delay 11 +/- 1 ptp4l[3796.029]: rms 3 max 6 ( -6, 4) freq +2614 +/- 4 delay 12 +/- 1 ptp4l[3797.029]: rms 3 max 5 ( -5, 5) freq +2614 +/- 4 delay 12 +/- 1 ptp4l[3798.030]: rms 2 max 4 ( -4, 3) freq +2614 +/- 3 delay 12 +/- 0 ptp4l[3799.030]: rms 3 max 6 ( -4, 6) freq +2616 +/- 4 delay 12 +/- 0 ptp4l[3800.030]: rms 3 max 5 ( -5, 5) freq +2615 +/- 4 delay 10 +/- 0 ptp4l[3801.030]: rms 4 max 8 ( -8, 2) freq +2609 +/- 5 delay 10 +/- 1 ptp4l[3802.030]: rms 7 max 12 ( -12, 3) freq +2603 +/- 7 delay 11 +/- 0 ptp4l[3803.030]: rms 4 max 7 ( -7, 3) freq +2601 +/- 4 delay 12 +/- 0 ptp4l[3804.030]: rms 4 max 7 ( -7, 4) freq +2599 +/- 5 delay 13 +/- 1 ptp4l[3805.030]: rms 6 max 9 ( -8, 9) freq +2600 +/- 8 delay 12 +/- 0 ptp4l[3806.030]: rms 5 max 10 ( 0, 10) freq +2609 +/- 4 delay 12 +/- 0 ptp4l[3807.030]: rms 5 max 10 ( -10, 6) freq +2604 +/- 7 delay 12 +/- 0 ptp4l[3808.030]: rms 6 max 8 ( -8, -1) freq +2594 +/- 3 delay 11 +/- 0 ptp4l[3809.031]: rms 7 max 10 ( -10, -2) freq +2587 +/- 4 delay 12 +/- 1 ptp4l[3810.156]: rms 4 max 8 ( -8, 0) freq +2587 +/- 4 delay 12 +/- 0 ptp4l[3811.156]: rms 2 max 4 ( -1, 4) freq +2591 +/- 3 delay 12 +/- 1 ptp4l[3812.156]: rms 4 max 7 ( -2, 7) freq +2596 +/- 4 delay 11 +/- 0 ptp4l[3813.406]: rms 3 max 6 ( -6, 1) freq +2588 +/- 3 delay 12 +/- 0 ptp4l[3814.406]: rms 6 max 7 ( -7, 1) freq +2582 +/- 5 delay 12 +/- 0 ptp4l[3815.406]: rms 4 max 7 ( -4, 7) freq +2588 +/- 5 delay 11 +/- 0 ptp4l[3816.406]: rms 3 max 4 ( -4, 4) freq +2587 +/- 4 delay 12 +/- 1 ptp4l[3817.531]: rms 4 max 6 ( -6, 6) freq +2590 +/- 5 delay 12 +/- 1 ptp4l[3818.531]: rms 3 max 5 ( -5, 5) freq +2587 +/- 4 delay 11 +/- 0 ptp4l[3819.532]: rms 4 max 5 ( -5, 4) freq +2584 +/- 4 delay 12 +/- 0 ptp4l[3820.657]: rms 4 max 7 ( -1, 7) freq +2592 +/- 3 delay 11 +/- 0 ptp4l[3821.782]: rms 4 max 9 ( -2, 9) freq +2594 +/- 5 delay 11 +/- 0 ptp4l[3822.782]: rms 3 max 5 ( -5, 2) freq +2589 +/- 4 delay 11 +/- 0 ...hbjÁhjhŒhlj<hn}rp(hh‘hs]hr]hp]hq]hv]uhxMªhyhhz]rqhƒXÊptp4l -f oc.txt -s -m & [1] 1153 root@am57xx-evm:~# ptp4l[3777.676]: selected /dev/ptp1 as PTP clock ptp4l[3777.740]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE ptp4l[3777.743]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE ptp4l[3777.744]: port 1: received PDELAY_REQ without timestamp ptp4l[3778.727]: port 1: new foreign master 8ca5a1.fffe.0000c2-1 ptp4l[3782.727]: selected best master clock 8ca5a1.fffe.0000c2 ptp4l[3782.727]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE ptp4l[3783.028]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED ptp4l[3783.653]: rms 756344481817248256 max 1512688963634496512 ( -31, 1512688963634496512) freq +2319 +/- 877 delay 12 +/- 0 ptp4l[3784.653]: rms 28 max 32 ( -32, -22) freq +2612 +/- 9 delay 12 +/- 0 ptp4l[3785.778]: rms 16 max 24 ( -24, -11) freq +2604 +/- 3 delay 12 +/- 0 ptp4l[3786.778]: rms 6 max 9 ( -9, -1) freq +2607 +/- 3 delay 12 +/- 1 ptp4l[3787.904]: rms 3 max 6 ( -6, 4) freq +2612 +/- 5 delay 12 +/- 0 ptp4l[3788.904]: rms 6 max 11 ( 4, 11) freq +2624 +/- 2 delay 12 +/- 0 ptp4l[3789.904]: rms 4 max 7 ( -2, 7) freq +2621 +/- 5 delay 12 +/- 0 ptp4l[3790.904]: rms 5 max 10 ( -10, 2) freq +2613 +/- 5 delay 11 +/- 0 ptp4l[3791.904]: rms 6 max 10 ( -10, 0) freq +2606 +/- 4 delay 12 +/- 1 ptp4l[3792.904]: rms 3 max 6 ( -4, 6) freq +2610 +/- 4 delay 11 +/- 1 ptp4l[3793.904]: rms 6 max 11 ( 0, 11) freq +2618 +/- 6 delay 12 +/- 0 ptp4l[3794.904]: rms 4 max 8 ( -5, 8) freq +2618 +/- 5 delay 11 +/- 1 ptp4l[3796.029]: rms 3 max 6 ( -6, 4) freq +2614 +/- 4 delay 12 +/- 1 ptp4l[3797.029]: rms 3 max 5 ( -5, 5) freq +2614 +/- 4 delay 12 +/- 1 ptp4l[3798.030]: rms 2 max 4 ( -4, 3) freq +2614 +/- 3 delay 12 +/- 0 ptp4l[3799.030]: rms 3 max 6 ( -4, 6) freq +2616 +/- 4 delay 12 +/- 0 ptp4l[3800.030]: rms 3 max 5 ( -5, 5) freq +2615 +/- 4 delay 10 +/- 0 ptp4l[3801.030]: rms 4 max 8 ( -8, 2) freq +2609 +/- 5 delay 10 +/- 1 ptp4l[3802.030]: rms 7 max 12 ( -12, 3) freq +2603 +/- 7 delay 11 +/- 0 ptp4l[3803.030]: rms 4 max 7 ( -7, 3) freq +2601 +/- 4 delay 12 +/- 0 ptp4l[3804.030]: rms 4 max 7 ( -7, 4) freq +2599 +/- 5 delay 13 +/- 1 ptp4l[3805.030]: rms 6 max 9 ( -8, 9) freq +2600 +/- 8 delay 12 +/- 0 ptp4l[3806.030]: rms 5 max 10 ( 0, 10) freq +2609 +/- 4 delay 12 +/- 0 ptp4l[3807.030]: rms 5 max 10 ( -10, 6) freq +2604 +/- 7 delay 12 +/- 0 ptp4l[3808.030]: rms 6 max 8 ( -8, -1) freq +2594 +/- 3 delay 11 +/- 0 ptp4l[3809.031]: rms 7 max 10 ( -10, -2) freq +2587 +/- 4 delay 12 +/- 1 ptp4l[3810.156]: rms 4 max 8 ( -8, 0) freq +2587 +/- 4 delay 12 +/- 0 ptp4l[3811.156]: rms 2 max 4 ( -1, 4) freq +2591 +/- 3 delay 12 +/- 1 ptp4l[3812.156]: rms 4 max 7 ( -2, 7) freq +2596 +/- 4 delay 11 +/- 0 ptp4l[3813.406]: rms 3 max 6 ( -6, 1) freq +2588 +/- 3 delay 12 +/- 0 ptp4l[3814.406]: rms 6 max 7 ( -7, 1) freq +2582 +/- 5 delay 12 +/- 0 ptp4l[3815.406]: rms 4 max 7 ( -4, 7) freq +2588 +/- 5 delay 11 +/- 0 ptp4l[3816.406]: rms 3 max 4 ( -4, 4) freq +2587 +/- 4 delay 12 +/- 1 ptp4l[3817.531]: rms 4 max 6 ( -6, 6) freq +2590 +/- 5 delay 12 +/- 1 ptp4l[3818.531]: rms 3 max 5 ( -5, 5) freq +2587 +/- 4 delay 11 +/- 0 ptp4l[3819.532]: rms 4 max 5 ( -5, 4) freq +2584 +/- 4 delay 12 +/- 0 ptp4l[3820.657]: rms 4 max 7 ( -1, 7) freq +2592 +/- 3 delay 11 +/- 0 ptp4l[3821.782]: rms 4 max 9 ( -2, 9) freq +2594 +/- 5 delay 11 +/- 0 ptp4l[3822.782]: rms 3 max 5 ( -5, 2) freq +2589 +/- 4 delay 11 +/- 0 ...rr…rs}rt(haUhbjnubaubcdocutils.nodes line_block ru)rv}rw(haUhbjÁhjhŒhlU line_blockrxhn}ry(hp]hq]hr]hs]hv]uhxMØhyhhz]rzcdocutils.nodes line r{)r|}r}(haUUindentr~KhbjvhjhŒhlhxhn}r(hp]hq]hr]hs]hv]uhxKhyhhz]ubaubhc)r€}r(haUhbjÁhjhŒhlhmhn}r‚(hp]hq]hr]hs]rƒUredundancy-hsr-prpr„ahv]r…hauhxMÛhyhhz]r†(h|)r‡}rˆ(haXRedundancy (HSR/PRP)r‰hbj€hjhŒhlh€hn}rŠ(hp]hq]hr]hs]hv]uhxMÛhyhhz]r‹hƒXRedundancy (HSR/PRP)rŒ…r}rŽ(haj‰hbj‡ubaubh§)r}r(haX®To set up PTP OC over HSR/PRP redundant interface, first setup HSR/PRP interface as detailed in `HSR/PRP Linux Software `__.hbj€hjhŒhlh«hn}r‘(hp]hq]hr]hs]hv]uhxMÝhyhhz]r’(hƒX`To set up PTP OC over HSR/PRP redundant interface, first setup HSR/PRP interface as detailed in r“…r”}r•(haX`To set up PTP OC over HSR/PRP redundant interface, first setup HSR/PRP interface as detailed in hbjubj_)r–}r—(haXM`HSR/PRP Linux Software `__hn}r˜(UnameXHSR/PRP Linux SoftwarejvX0Industrial_Protocols_HSR_PRP.html#linux-softwarehs]hr]hp]hq]hv]uhbjhz]r™hƒXHSR/PRP Linux Softwarerš…r›}rœ(haUhbj–ubahljhubhƒX.…r}rž(haX.hbjubeubh§)rŸ}r (haX¡Start PTP with the same command listed above, but using a different configuration file: (where eth2/eth3 are the slave interfaces used for the HSR/PRP interface)r¡hbj€hjhŒhlh«hn}r¢(hp]hq]hr]hs]hv]uhxMàhyhhz]r£hƒX¡Start PTP with the same command listed above, but using a different configuration file: (where eth2/eth3 are the slave interfaces used for the HSR/PRP interface)r¤…r¥}r¦(haj¡hbjŸubaubh§)r§}r¨(haXHSR: ::hbj€hjhŒhlh«hn}r©(hp]hq]hr]hs]hv]uhxMähyhhz]rªhƒXHSR:r«…r¬}r­(haXHSR:hbj§ubaubj9)r®}r¯(haX [global] sanity_freq_limit 0 step_threshold 0.00002 tx_timestamp_timeout 20 domainNumber 0 priority1 128 priority2 128 slaveOnly 0 twoStepFlag 1 summary_interval 0 doubly_attached_clock 1 [hsr0] redundancy 1 delay_mechanism P2P network_transport L2 [eth2] redundancy 1 redundancy_master_interface hsr0 redundancy_slave_number 1 logAnnounceInterval 0 logSyncInterval 0 logMinPdelayReqInterval 0 announceReceiptTimeout 3 syncReceiptTimeout 2 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0 [eth3] redundancy 1 redundancy_master_interface hsr0 redundancy_slave_number 2 logAnnounceInterval 0 logSyncInterval 0 logMinPdelayReqInterval 0 announceReceiptTimeout 3 syncReceiptTimeout 2 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0hbj€hjhŒhlj<hn}r°(hh‘hs]hr]hp]hq]hv]uhxMìhyhhz]r±hƒX [global] sanity_freq_limit 0 step_threshold 0.00002 tx_timestamp_timeout 20 domainNumber 0 priority1 128 priority2 128 slaveOnly 0 twoStepFlag 1 summary_interval 0 doubly_attached_clock 1 [hsr0] redundancy 1 delay_mechanism P2P network_transport L2 [eth2] redundancy 1 redundancy_master_interface hsr0 redundancy_slave_number 1 logAnnounceInterval 0 logSyncInterval 0 logMinPdelayReqInterval 0 announceReceiptTimeout 3 syncReceiptTimeout 2 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0 [eth3] redundancy 1 redundancy_master_interface hsr0 redundancy_slave_number 2 logAnnounceInterval 0 logSyncInterval 0 logMinPdelayReqInterval 0 announceReceiptTimeout 3 syncReceiptTimeout 2 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0r²…r³}r´(haUhbj®ubaubh§)rµ}r¶(haXPRP: ::hbj€hjhŒhlh«hn}r·(hp]hq]hr]hs]hv]uhxMhyhhz]r¸hƒXPRP:r¹…rº}r»(haXPRP:hbjµubaubj9)r¼}r½(haX[global] sanity_freq_limit 0 step_threshold 0.00002 tx_timestamp_timeout 10 domainNumber 0 priority1 128 priority2 123 slaveOnly 0 twoStepFlag 1 summary_interval 0 doubly_attached_clock 1 [prp0] redundancy 2 delay_mechanism P2P network_transport L2 [eth2] redundancy 2 redundancy_master_interface prp0 redundancy_slave_number 1 logAnnounceInterval 0 logSyncInterval 0 logMinPdelayReqInterval 0 announceReceiptTimeout 3 syncReceiptTimeout 2 delay_mechanism P2P egressLatency 726 ingressLatency 186 network_transport L2 fault_reset_interval 0 [eth3] redundancy 2 redundancy_master_interface prp0 redundancy_slave_number 2 logAnnounceInterval 0 logSyncInterval 0 logMinPdelayReqInterval 0 announceReceiptTimeout 3 syncReceiptTimeout 2 delay_mechanism P2P egressLatency 726 ingressLatency 186 network_transport L2 fault_reset_interval 0hbj€hjhŒhlj<hn}r¾(hh‘hs]hr]hp]hq]hv]uhxM$hyhhz]r¿hƒX[global] sanity_freq_limit 0 step_threshold 0.00002 tx_timestamp_timeout 10 domainNumber 0 priority1 128 priority2 123 slaveOnly 0 twoStepFlag 1 summary_interval 0 doubly_attached_clock 1 [prp0] redundancy 2 delay_mechanism P2P network_transport L2 [eth2] redundancy 2 redundancy_master_interface prp0 redundancy_slave_number 1 logAnnounceInterval 0 logSyncInterval 0 logMinPdelayReqInterval 0 announceReceiptTimeout 3 syncReceiptTimeout 2 delay_mechanism P2P egressLatency 726 ingressLatency 186 network_transport L2 fault_reset_interval 0 [eth3] redundancy 2 redundancy_master_interface prp0 redundancy_slave_number 2 logAnnounceInterval 0 logSyncInterval 0 logMinPdelayReqInterval 0 announceReceiptTimeout 3 syncReceiptTimeout 2 delay_mechanism P2P egressLatency 726 ingressLatency 186 network_transport L2 fault_reset_interval 0rÀ…rÁ}rÂ(haUhbj¼ubaubeubhc)rÃ}rÄ(haUhbjÁhjhŒhlhmhn}rÅ(hp]hq]hr]hs]rÆUe2e-ipv4-telecom-profilerÇahv]rÈh9auhxMUhyhhz]rÉ(h|)rÊ}rË(haXE2E/IPv4 (Telecom Profile)rÌhbjÃhjhŒhlh€hn}rÍ(hp]hq]hr]hs]hv]uhxMUhyhhz]rÎhƒXE2E/IPv4 (Telecom Profile)rÏ…rÐ}rÑ(hajÌhbjÊubaubh§)rÒ}rÓ(haX.Support for E2E message types, IPv4 transport, and unicast negotation enables use of the Telecom profile. This is also supported by LinuxPTP, and may be configured using a configuration file similar to the one below: (Note: only supported on PRU-ICSS ports using DualEMAC, and supports slave side only)rÔhbjÃhjhŒhlh«hn}rÕ(hp]hq]hr]hs]hv]uhxMWhyhhz]rÖhƒX.Support for E2E message types, IPv4 transport, and unicast negotation enables use of the Telecom profile. This is also supported by LinuxPTP, and may be configured using a configuration file similar to the one below: (Note: only supported on PRU-ICSS ports using DualEMAC, and supports slave side only)r×…rØ}rÙ(hajÔhbjÒubaubh§)rÚ}rÛ(haX Telecom: ::hbjÃhjhŒhlh«hn}rÜ(hp]hq]hr]hs]hv]uhxM\hyhhz]rÝhƒXTelecom:rÞ…rß}rà(haXTelecom:hbjÚubaubj9)rá}râ(haXÿ# Telecom Profile (G.8275.x) PTP Config File [global] tx_timestamp_timeout 10 logMinPdelayReqInterval -4 logSyncInterval -4 twoStepFlag 1 logMinDelayReqInterval -4 logAnnounceInterval -3 dataset_comparison G.8275.x G.8275.defaultDS.localPriority 128 G.8275.portDS.localPriority 128 hybrid_e2e 1 inhibit_multicast_service 1 unicast_listen 1 unicast_req_duration 60 [unicast_master_table] table_id 94 logQueryInterval 2 UDPv4 192.168.1.94 [eth3] egressLatency 726 ingressLatency 186 unicast_master_table 94hbjÃhjhŒhlj<hn}rã(hh‘hs]hr]hp]hq]hv]uhxMdhyhhz]rähƒXÿ# Telecom Profile (G.8275.x) PTP Config File [global] tx_timestamp_timeout 10 logMinPdelayReqInterval -4 logSyncInterval -4 twoStepFlag 1 logMinDelayReqInterval -4 logAnnounceInterval -3 dataset_comparison G.8275.x G.8275.defaultDS.localPriority 128 G.8275.portDS.localPriority 128 hybrid_e2e 1 inhibit_multicast_service 1 unicast_listen 1 unicast_req_duration 60 [unicast_master_table] table_id 94 logQueryInterval 2 UDPv4 192.168.1.94 [eth3] egressLatency 726 ingressLatency 186 unicast_master_table 94rå…ræ}rç(haUhbjáubaubh§)rè}ré(haXRIn above example config, 192.168.1.94 is the IP of the PTP master for this device.rêhbjÃhjhŒhlh«hn}rë(hp]hq]hr]hs]hv]uhxM{hyhhz]rìhƒXRIn above example config, 192.168.1.94 is the IP of the PTP master for this device.rí…rî}rï(hajêhbjèubaubeubhc)rð}rñ(haUhbjÁhjhŒhlhmhn}rò(hp]hq]hr]hs]róUvlanrôahv]rõh3auhxMhyhhz]rö(h|)r÷}rø(haXVLANrùhbjðhjhŒhlh€hn}rú(hp]hq]hr]hs]hv]uhxMhyhhz]rûhƒXVLANrü…rý}rþ(hajùhbj÷ubaubh§)rÿ}r(haXJPTP can also operate over VLAN interfaces, which can either be standard ethernet or HSR/PRP VLAN interfaces. In both cases, the only change needed is to specify the VLAN interface as the PTP interface in the PTP config file. In the case of HSR/PRP VLAN, the HSR/PRP interface will be the VLAN enabled interface (not the slave interfaces) and is the only interface that would need to be changed in the config file. For example, in the above HSR/PRP PTP config files, the only change needed would to change "[hsr0]" or "[prp0]" to appropriate VLAN interfaces e.g. "[hsr0.2]" or "[prp0.2]"rhbjðhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxM€hyhhz]rhƒXJPTP can also operate over VLAN interfaces, which can either be standard ethernet or HSR/PRP VLAN interfaces. In both cases, the only change needed is to specify the VLAN interface as the PTP interface in the PTP config file. In the case of HSR/PRP VLAN, the HSR/PRP interface will be the VLAN enabled interface (not the slave interfaces) and is the only interface that would need to be changed in the config file. For example, in the above HSR/PRP PTP config files, the only change needed would to change "[hsr0]" or "[prp0]" to appropriate VLAN interfaces e.g. "[hsr0.2]" or "[prp0.2]"r…r}r(hajhbjÿubaubeubhc)r}r(haUhbjÁhjhŒhlhmhn}r (hp]hq]hr]hs]r Usome-useful-commandsr ahv]r hVauhxMŠhyhhz]r (h|)r}r(haXSome useful commandsrhbjhjhŒhlh€hn}r(hp]hq]hr]hs]hv]uhxMŠhyhhz]rhƒXSome useful commandsr…r}r(hajhbjubaubh§)r}r(haX:To see the availability of ICSS-PRU1 and ICSS-PRU2 on SoC:rhbjhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxMŒhyhhz]rhƒX:To see the availability of ICSS-PRU1 and ICSS-PRU2 on SoC:r…r}r(hajhbjubaubj9)r}r(haX,root@am57xx-evm:~# ls /sys/devices/platform/hbjhjhŒhlj<hn}r (hh‘hs]hr]hp]hq]hv]uhxM•hyhhz]r!hƒX,root@am57xx-evm:~# ls /sys/devices/platform/r"…r#}r$(haUhbjubaubh§)r%}r&(haX4and look for **pruss1\_eth** and/or **pruss2\_eth**.r'hbjhjhŒhlh«hn}r((hp]hq]hr]hs]hv]uhxM’hyhhz]r)(hƒX and look for r*…r+}r,(haX and look for hbj%ubj)r-}r.(haX**pruss1\_eth**hn}r/(hp]hq]hr]hs]hv]uhbj%hz]r0hƒX pruss1_ethr1…r2}r3(haUhbj-ubahlj‡ubhƒX and/or r4…r5}r6(haX and/or hbj%ubj)r7}r8(haX**pruss2\_eth**hn}r9(hp]hq]hr]hs]hv]uhbj%hz]r:hƒX pruss2_ethr;…r<}r=(haUhbj7ubahlj‡ubhƒX.…r>}r?(haX.hbj%ubeubh§)r@}rA(haXCTo see which interface is configured under, for example, ICSS-PRU2:rBhbjhjhŒhlh«hn}rC(hp]hq]hr]hs]hv]uhxM”hyhhz]rDhƒXCTo see which interface is configured under, for example, ICSS-PRU2:rE…rF}rG(hajBhbj@ubaubj9)rH}rI(haXFroot@am57xx-evm:~# ls /sys/devices/platform/pruss2_eth/net eth2/ eth3/hbjhjhŒhlj<hn}rJ(hh‘hs]hr]hp]hq]hv]uhxMhyhhz]rKhƒXFroot@am57xx-evm:~# ls /sys/devices/platform/pruss2_eth/net eth2/ eth3/rL…rM}rN(haUhbjHubaubh§)rO}rP(haX7To see what is available under an ICSS-PRU ptp support:rQhbjhjhŒhlh«hn}rR(hp]hq]hr]hs]hv]uhxM›hyhhz]rShƒX7To see what is available under an ICSS-PRU ptp support:rT…rU}rV(hajQhbjOubaubj9)rW}rX(haX@root@am57xx-evm:~# ls /sys/devices/platform/pruss2_eth/ptp ptp1/hbjhjhŒhlj<hn}rY(hh‘hs]hr]hp]hq]hv]uhxM¤hyhhz]rZhƒX@root@am57xx-evm:~# ls /sys/devices/platform/pruss2_eth/ptp ptp1/r[…r\}r](haUhbjWubaubj9)r^}r_(haX~root@am57xx-evm:~# ls /sys/devices/platform/pruss2_eth/ptp/ptp1 clock_name fifo n_periodic_outputs pps_available dev max_adjustment n_programmable_pins pps_enable device@ n_alarms period subsystem@ extts_enable n_external_timestamps power/ ueventhbjhjhŒhlj<hn}r`(hh‘hs]hr]hp]hq]hv]uhxM©hyhhz]rahƒX~root@am57xx-evm:~# ls /sys/devices/platform/pruss2_eth/ptp/ptp1 clock_name fifo n_periodic_outputs pps_available dev max_adjustment n_programmable_pins pps_enable device@ n_alarms period subsystem@ extts_enable n_external_timestamps power/ ueventrb…rc}rd(haUhbj^ubaubj9)re}rf(haXXroot@am57xx-evm:~# cat /sys/devices/platform/pruss1_eth/ptp/ptp2/clock_name PRUSS1 timerhbjhjhŒhlj<hn}rg(hh‘hs]hr]hp]hq]hv]uhxM±hyhhz]rhhƒXXroot@am57xx-evm:~# cat /sys/devices/platform/pruss1_eth/ptp/ptp2/clock_name PRUSS1 timerri…rj}rk(haUhbjeubaubj9)rl}rm(haXProot@am57xx-evm:~# cat /sys/devices/platform/pruss2_eth/ptp/ptp1/pps_available 1hbjhjhŒhlj<hn}rn(hh‘hs]hr]hp]hq]hv]uhxM¶hyhhz]rohƒXProot@am57xx-evm:~# cat /sys/devices/platform/pruss2_eth/ptp/ptp1/pps_available 1rp…rq}rr(haUhbjlubaubh§)rs}rt(haXÔIf ptp4l is started in the background and without the "-m" option to print any message to standard output, the system log file /var/log/messages can be used to get a glimpse of the progress of ptp4l. For example,ruhbjhjhŒhlh«hn}rv(hp]hq]hr]hs]hv]uhxM´hyhhz]rwhƒXÔIf ptp4l is started in the background and without the "-m" option to print any message to standard output, the system log file /var/log/messages can be used to get a glimpse of the progress of ptp4l. For example,rx…ry}rz(hajuhbjsubaubj9)r{}r|(haXÜroot@am57xx-evm:~# ptp4l -2 -P -f oc.cfg & root@am57xx-evm:~# root@am57xx-evm:~# tail -n 30 /var/log/messages Dec 5 20:45:14 am57xx-evm daemon.info thttpd[946]: fdwatch - 729 polls (0.2025/sec) Dec 5 20:45:14 am57xx-evm daemon.info thttpd[946]: timers - 3 allocated, 3 active, 0 free Dec 5 20:58:06 am57xx-evm user.notice ptp4l: [83598.805] selected best master clock 70ff76.fffe.1c0f99 Dec 5 20:58:06 am57xx-evm user.notice ptp4l: [83598.805] port 2: MASTER to UNCALIBRATED on RS_SLAVE Dec 5 20:58:06 am57xx-evm user.notice ptp4l: [83599.177] port 2: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED Dec 5 20:58:06 am57xx-evm user.info ptp4l: [83599.427] rms 36120 max 72251 (-72251, 8) freq -7075 +/- 88 delay 8 +/- 0 Dec 5 20:58:08 am57xx-evm user.info ptp4l: [83600.552] rms 15 max 19 ( 11, 19) freq -7141 +/- 8 delay 8 +/- 0 Dec 5 20:58:09 am57xx-evm user.info ptp4l: [83601.553] rms 8 max 13 ( 1, 13) freq -7139 +/- 5 delay 8 +/- 0 Dec 5 20:58:10 am57xx-evm user.info ptp4l: [83602.553] rms 3 max 4 ( -4, 4) freq -7144 +/- 4 delay 7 +/- 0 Dec 5 20:58:11 am57xx-evm user.info ptp4l: [83603.553] rms 7 max 11 ( -11, -4) freq -7157 +/- 5 delay 8 +/- 0 Dec 5 20:58:12 am57xx-evm user.info ptp4l: [83604.554] rms 5 max 10 ( -10, 3) freq -7159 +/- 5 delay 7 +/- 0 Dec 5 20:58:13 am57xx-evm user.info ptp4l: [83605.554] rms 2 max 4 ( -4, 2) freq -7156 +/- 3 delay 7 +/- 0 Dec 5 20:58:14 am57xx-evm user.info ptp4l: [83606.680] rms 3 max 7 ( -7, 1) freq -7160 +/- 3 delay 8 +/- 0 Dec 5 20:58:15 am57xx-evm user.info ptp4l: [83607.680] rms 5 max 9 ( -4, 9) freq -7154 +/- 6 delay 8 +/- 0 Dec 5 20:58:16 am57xx-evm user.info ptp4l: [83608.680] rms 5 max 9 ( 0, 9) freq -7148 +/- 5 delay 7 +/- 0 Dec 5 20:58:17 am57xx-evm user.info ptp4l: [83609.681] rms 4 max 6 ( -4, 6) freq -7149 +/- 5 delay 7 +/- 0 Dec 5 20:58:18 am57xx-evm user.info ptp4l: [83610.681] rms 2 max 4 ( -2, 4) freq -7149 +/- 3 delay 7 +/- 0 Dec 5 20:58:19 am57xx-evm user.info ptp4l: [83611.806] rms 3 max 7 ( -7, 2) freq -7151 +/- 4 delay 7 +/- 0 Dec 5 20:58:20 am57xx-evm user.info ptp4l: [83612.807] rms 2 max 4 ( -4, 4) freq -7150 +/- 3 delay 8 +/- 0 Dec 5 20:58:21 am57xx-evm user.info ptp4l: [83613.807] rms 3 max 6 ( -2, 6) freq -7148 +/- 4 delay 8 +/- 0 Dec 5 20:58:22 am57xx-evm user.info ptp4l: [83614.807] rms 5 max 9 ( -1, 9) freq -7141 +/- 5 delay 8 +/- 0 Dec 5 20:58:23 am57xx-evm user.info ptp4l: [83615.808] rms 3 max 6 ( -4, 6) freq -7143 +/- 4 delay 8 +/- 0 Dec 5 20:58:24 am57xx-evm user.info ptp4l: [83616.808] rms 2 max 5 ( -5, 1) freq -7147 +/- 2 delay 7 +/- 0 Dec 5 20:58:25 am57xx-evm user.info ptp4l: [83617.934] rms 5 max 8 ( -8, 5) freq -7150 +/- 7 delay 8 +/- 0 Dec 5 20:58:26 am57xx-evm user.info ptp4l: [83618.934] rms 3 max 5 ( -5, 3) freq -7153 +/- 3 delay 8 +/- 0 Dec 5 20:58:27 am57xx-evm user.info ptp4l: [83619.934] rms 5 max 8 ( -1, 8) freq -7145 +/- 5 delay 7 +/- 1 Dec 5 20:58:28 am57xx-evm user.info ptp4l: [83620.935] rms 6 max 10 ( 2, 10) freq -7136 +/- 2 delay 6 +/- 0 Dec 5 20:58:29 am57xx-evm user.info ptp4l: [83621.935] rms 4 max 7 ( -1, 7) freq -7135 +/- 3 delay 8 +/- 1 Dec 5 20:58:30 am57xx-evm user.info ptp4l: [83622.935] rms 2 max 3 ( -1, 3) freq -7136 +/- 2 delay 9 +/- 0 Dec 5 20:58:31 am57xx-evm user.info ptp4l: [83624.061] rms 4 max 6 ( 0, 6) freq -7131 +/- 3 delay 8 +/- 0 root@am57xx-evm:~#hbjhjhŒhlj<hn}r}(hh‘hs]hr]hp]hq]hv]uhxMÀhyhhz]r~hƒXÜroot@am57xx-evm:~# ptp4l -2 -P -f oc.cfg & root@am57xx-evm:~# root@am57xx-evm:~# tail -n 30 /var/log/messages Dec 5 20:45:14 am57xx-evm daemon.info thttpd[946]: fdwatch - 729 polls (0.2025/sec) Dec 5 20:45:14 am57xx-evm daemon.info thttpd[946]: timers - 3 allocated, 3 active, 0 free Dec 5 20:58:06 am57xx-evm user.notice ptp4l: [83598.805] selected best master clock 70ff76.fffe.1c0f99 Dec 5 20:58:06 am57xx-evm user.notice ptp4l: [83598.805] port 2: MASTER to UNCALIBRATED on RS_SLAVE Dec 5 20:58:06 am57xx-evm user.notice ptp4l: [83599.177] port 2: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED Dec 5 20:58:06 am57xx-evm user.info ptp4l: [83599.427] rms 36120 max 72251 (-72251, 8) freq -7075 +/- 88 delay 8 +/- 0 Dec 5 20:58:08 am57xx-evm user.info ptp4l: [83600.552] rms 15 max 19 ( 11, 19) freq -7141 +/- 8 delay 8 +/- 0 Dec 5 20:58:09 am57xx-evm user.info ptp4l: [83601.553] rms 8 max 13 ( 1, 13) freq -7139 +/- 5 delay 8 +/- 0 Dec 5 20:58:10 am57xx-evm user.info ptp4l: [83602.553] rms 3 max 4 ( -4, 4) freq -7144 +/- 4 delay 7 +/- 0 Dec 5 20:58:11 am57xx-evm user.info ptp4l: [83603.553] rms 7 max 11 ( -11, -4) freq -7157 +/- 5 delay 8 +/- 0 Dec 5 20:58:12 am57xx-evm user.info ptp4l: [83604.554] rms 5 max 10 ( -10, 3) freq -7159 +/- 5 delay 7 +/- 0 Dec 5 20:58:13 am57xx-evm user.info ptp4l: [83605.554] rms 2 max 4 ( -4, 2) freq -7156 +/- 3 delay 7 +/- 0 Dec 5 20:58:14 am57xx-evm user.info ptp4l: [83606.680] rms 3 max 7 ( -7, 1) freq -7160 +/- 3 delay 8 +/- 0 Dec 5 20:58:15 am57xx-evm user.info ptp4l: [83607.680] rms 5 max 9 ( -4, 9) freq -7154 +/- 6 delay 8 +/- 0 Dec 5 20:58:16 am57xx-evm user.info ptp4l: [83608.680] rms 5 max 9 ( 0, 9) freq -7148 +/- 5 delay 7 +/- 0 Dec 5 20:58:17 am57xx-evm user.info ptp4l: [83609.681] rms 4 max 6 ( -4, 6) freq -7149 +/- 5 delay 7 +/- 0 Dec 5 20:58:18 am57xx-evm user.info ptp4l: [83610.681] rms 2 max 4 ( -2, 4) freq -7149 +/- 3 delay 7 +/- 0 Dec 5 20:58:19 am57xx-evm user.info ptp4l: [83611.806] rms 3 max 7 ( -7, 2) freq -7151 +/- 4 delay 7 +/- 0 Dec 5 20:58:20 am57xx-evm user.info ptp4l: [83612.807] rms 2 max 4 ( -4, 4) freq -7150 +/- 3 delay 8 +/- 0 Dec 5 20:58:21 am57xx-evm user.info ptp4l: [83613.807] rms 3 max 6 ( -2, 6) freq -7148 +/- 4 delay 8 +/- 0 Dec 5 20:58:22 am57xx-evm user.info ptp4l: [83614.807] rms 5 max 9 ( -1, 9) freq -7141 +/- 5 delay 8 +/- 0 Dec 5 20:58:23 am57xx-evm user.info ptp4l: [83615.808] rms 3 max 6 ( -4, 6) freq -7143 +/- 4 delay 8 +/- 0 Dec 5 20:58:24 am57xx-evm user.info ptp4l: [83616.808] rms 2 max 5 ( -5, 1) freq -7147 +/- 2 delay 7 +/- 0 Dec 5 20:58:25 am57xx-evm user.info ptp4l: [83617.934] rms 5 max 8 ( -8, 5) freq -7150 +/- 7 delay 8 +/- 0 Dec 5 20:58:26 am57xx-evm user.info ptp4l: [83618.934] rms 3 max 5 ( -5, 3) freq -7153 +/- 3 delay 8 +/- 0 Dec 5 20:58:27 am57xx-evm user.info ptp4l: [83619.934] rms 5 max 8 ( -1, 8) freq -7145 +/- 5 delay 7 +/- 1 Dec 5 20:58:28 am57xx-evm user.info ptp4l: [83620.935] rms 6 max 10 ( 2, 10) freq -7136 +/- 2 delay 6 +/- 0 Dec 5 20:58:29 am57xx-evm user.info ptp4l: [83621.935] rms 4 max 7 ( -1, 7) freq -7135 +/- 3 delay 8 +/- 1 Dec 5 20:58:30 am57xx-evm user.info ptp4l: [83622.935] rms 2 max 3 ( -1, 3) freq -7136 +/- 2 delay 9 +/- 0 Dec 5 20:58:31 am57xx-evm user.info ptp4l: [83624.061] rms 4 max 6 ( 0, 6) freq -7131 +/- 3 delay 8 +/- 0 root@am57xx-evm:~#r…r€}r(haUhbj{ubaubeubhc)r‚}rƒ(haUh˜KhbjÁhjhŒhlhmhn}r„(hp]r…X%phy delay compensation for am57xx idkr†ahq]hr]hs]r‡U%phy-delay-compensation-for-am57xx-idkrˆahv]uhxMßhyhhz]r‰(h|)rŠ}r‹(haX%PHY Delay Compensation for AM57xx IDKrŒhbj‚hjhŒhlh€hn}r(hp]hq]hr]hs]hv]uhxMßhyhhz]rŽhƒX%PHY Delay Compensation for AM57xx IDKr…r}r‘(hajŒhbjŠubaubh§)r’}r“(haXËThe accuracy of PTP time provided by an OC depends in part on the accountability of the latencies introduced by the Ethernet of PHY and the timestamping point at which a PTP event message is timestamped.r”hbj‚hjhŒhlh«hn}r•(hp]hq]hr]hs]hv]uhxMáhyhhz]r–hƒXËThe accuracy of PTP time provided by an OC depends in part on the accountability of the latencies introduced by the Ethernet of PHY and the timestamping point at which a PTP event message is timestamped.r—…r˜}r™(haj”hbj’ubaubh§)rš}r›(haXãIEEE-1588-2009 specifies that timestamp should be taken right after the SOF (start of frame). For Ethernet this is right after the SFD (start frame delimiter) or right before the destination MAC address. In the case of PRU-PRP firmware, only SOF timestampping is available for a TX PTP event message. And because in a 100 mbps line speed, 1 bit time is equivalent to 10ns, hence 640 ns ( (7 bytes preamble + 1 byte SFD) \* 8 bits \* 10ns) needs to be compensated in the TX direction.hbj‚hjhŒhlh«hn}rœ(hp]hq]hr]hs]hv]uhxMåhyhhz]rhƒXáIEEE-1588-2009 specifies that timestamp should be taken right after the SOF (start of frame). For Ethernet this is right after the SFD (start frame delimiter) or right before the destination MAC address. In the case of PRU-PRP firmware, only SOF timestampping is available for a TX PTP event message. And because in a 100 mbps line speed, 1 bit time is equivalent to 10ns, hence 640 ns ( (7 bytes preamble + 1 byte SFD) * 8 bits * 10ns) needs to be compensated in the TX direction.rž…rŸ}r (haXãIEEE-1588-2009 specifies that timestamp should be taken right after the SOF (start of frame). For Ethernet this is right after the SFD (start frame delimiter) or right before the destination MAC address. In the case of PRU-PRP firmware, only SOF timestampping is available for a TX PTP event message. And because in a 100 mbps line speed, 1 bit time is equivalent to 10ns, hence 640 ns ( (7 bytes preamble + 1 byte SFD) \* 8 bits \* 10ns) needs to be compensated in the TX direction.hbjšubaubh§)r¡}r¢(haXzFurthermore, the PRU-ICSS PHY TLK110 on AM57xx IDK introduces a latency of 86 ns in the TX and 186 ns in the RX direction.r£hbj‚hjhŒhlh«hn}r¤(hp]hq]hr]hs]hv]uhxMíhyhhz]r¥hƒXzFurthermore, the PRU-ICSS PHY TLK110 on AM57xx IDK introduces a latency of 86 ns in the TX and 186 ns in the RX direction.r¦…r§}r¨(haj£hbj¡ubaubh§)r©}rª(haXnThus a total of 640 + 86 = 726 ns in the TX direction and 186 ns in the RX direction need to be accounted for.r«hbj‚hjhŒhlh«hn}r¬(hp]hq]hr]hs]hv]uhxMðhyhhz]r­hƒXnThus a total of 640 + 86 = 726 ns in the TX direction and 186 ns in the RX direction need to be accounted for.r®…r¯}r°(haj«hbj©ubaubh§)r±}r²(haXœWhen linuxptp's ptp4l is used as the PTP protocol application, the following should be used for IngressLatency and EgressLatency configuration respectively.r³hbj‚hjhŒhlh«hn}r´(hp]hq]hr]hs]hv]uhxMóhyhhz]rµhƒXœWhen linuxptp's ptp4l is used as the PTP protocol application, the following should be used for IngressLatency and EgressLatency configuration respectively.r¶…r·}r¸(haj³hbj±ubaubjÊ)r¹}rº(haUhbj‚hjhŒhljÍhn}r»(hp]hq]hr]hs]hv]uhxNhyhhz]r¼jÐ)r½}r¾(haUhn}r¿(hs]hr]hp]hq]hv]UcolsKuhbj¹hz]rÀ(jÕ)rÁ}rÂ(haUhn}rÃ(hs]hr]hp]hq]hv]UcolwidthKuhbj½hz]hljÙubjÕ)rÄ}rÅ(haUhn}rÆ(hs]hr]hp]hq]hv]UcolwidthKuhbj½hz]hljÙubjÕ)rÇ}rÈ(haUhn}rÉ(hs]hr]hp]hq]hv]UcolwidthKuhbj½hz]hljÙubjã)rÊ}rË(haUhn}rÌ(hp]hq]hr]hs]hv]uhbj½hz]rÍjè)rÎ}rÏ(haUhn}rÐ(hp]hq]hr]hs]hv]uhbjÊhz]rÑ(jí)rÒ}rÓ(haUhn}rÔ(hp]hq]hr]hs]hv]uhbjÎhz]rÕh§)rÖ}r×(haXSpeedrØhbjÒhjhŒhlh«hn}rÙ(hp]hq]hr]hs]hv]uhxMøhz]rÚhƒXSpeedrÛ…rÜ}rÝ(hajØhbjÖubaubahljúubjí)rÞ}rß(haUhn}rà(hp]hq]hr]hs]hv]uhbjÎhz]ráh§)râ}rã(haXEgress Latency (ns)rähbjÞhjhŒhlh«hn}rå(hp]hq]hr]hs]hv]uhxMøhz]ræhƒXEgress Latency (ns)rç…rè}ré(hajähbjâubaubahljúubjí)rê}rë(haUhn}rì(hp]hq]hr]hs]hv]uhbjÎhz]ríh§)rî}rï(haXIngress Latency (ns)rðhbjêhjhŒhlh«hn}rñ(hp]hq]hr]hs]hv]uhxMøhz]ròhƒXIngress Latency (ns)ró…rô}rõ(hajðhbjîubaubahljúubehljubahlj ubj!)rö}r÷(haUhn}rø(hp]hq]hr]hs]hv]uhbj½hz]rùjè)rú}rû(haUhn}rü(hp]hq]hr]hs]hv]uhbjöhz]rý(jí)rþ}rÿ(haUhn}r(hp]hq]hr]hs]hv]uhbjúhz]rh§)r}r(haX100MbrhbjþhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxMúhz]rhƒX100Mbr…r}r (hajhbjubaubahljúubjí)r }r (haUhn}r (hp]hq]hr]hs]hv]uhbjúhz]r h§)r}r(haX726rhbj hjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxMúhz]rhƒX726r…r}r(hajhbjubaubahljúubjí)r}r(haUhn}r(hp]hq]hr]hs]hv]uhbjúhz]rh§)r}r(haX186rhbjhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxMúhz]rhƒX186r…r }r!(hajhbjubaubahljúubehljubahljRubehljSubaubh§)r"}r#(haXŸThis also explains the two lines that corresponds to egressLatency and ingressLatency in the sample ptp4l configuration file oc.cfg in the ptp4l example above.r$hbj‚hjhŒhlh«hn}r%(hp]hq]hr]hs]hv]uhxMýhyhhz]r&hƒXŸThis also explains the two lines that corresponds to egressLatency and ingressLatency in the sample ptp4l configuration file oc.cfg in the ptp4l example above.r'…r(}r)(haj$hbj"ubaubeubhc)r*}r+(haUh˜KhbjÁhjhŒhlhmhn}r,(hp]r-X limitationsr.ahq]hr]hs]r/U limitationsr0ahv]uhxMhyhhz]r1(h|)r2}r3(haX Limitationsr4hbj*hjhŒhlh€hn}r5(hp]hq]hr]hs]hv]uhxMhyhhz]r6hƒX Limitationsr7…r8}r9(haj4hbj2ubaubh§)r:}r;(haXðAlthough there are two Ethernet ports available on each ICSS-PRU present, ICSS-PRU PTP OC can only be supported on at most **ONE** such port. It cannot provide PTP OC functionality on both Ethernet ports on the same ICSS-PRU simultaneously.hbj*hjhŒhlh«hn}r<(hp]hq]hr]hs]hv]uhxMhyhhz]r=(hƒX{Although there are two Ethernet ports available on each ICSS-PRU present, ICSS-PRU PTP OC can only be supported on at most r>…r?}r@(haX{Although there are two Ethernet ports available on each ICSS-PRU present, ICSS-PRU PTP OC can only be supported on at most hbj:ubj)rA}rB(haX**ONE**hn}rC(hp]hq]hr]hs]hv]uhbj:hz]rDhƒXONErE…rF}rG(haUhbjAubahlj‡ubhƒXn such port. It cannot provide PTP OC functionality on both Ethernet ports on the same ICSS-PRU simultaneously.rH…rI}rJ(haXn such port. It cannot provide PTP OC functionality on both Ethernet ports on the same ICSS-PRU simultaneously.hbj:ubeubeubeubhc)rK}rL(haUhbj hjhŒhlhmhn}rM(hp]hq]hr]hs]rNUptp-ordinary-clock-on-gmacrOahv]rPhTauhxM hyhhz]rQ(h|)rR}rS(haXPTP Ordinary Clock on GMACrThbjKhjhŒhlh€hn}rU(hp]hq]hr]hs]hv]uhxM hyhhz]rVhƒXPTP Ordinary Clock on GMACrW…rX}rY(hajThbjRubaubh§)rZ}r[(haXõRefer to `here `__ for more details about the CPTS driver and how to run **linuxptp** over the CPSW GMAC port for providing the PTP OC functionality.hbjKhjhŒhlh«hn}r\(hp]hq]hr]hs]hv]uhxM hyhhz]r](hƒX Refer to r^…r_}r`(haX Refer to hbjZubj_)ra}rb(haXi`here `__hn}rc(UnameXherejvX^Foundational_Components/Kernel/Kernel_Drivers/Network/CPSW.html#common-platform-time-sync-cptshs]hr]hp]hq]hv]uhbjZhz]rdhƒXherere…rf}rg(haUhbjaubahljhubhƒX7 for more details about the CPTS driver and how to run rh…ri}rj(haX7 for more details about the CPTS driver and how to run hbjZubj)rk}rl(haX **linuxptp**hn}rm(hp]hq]hr]hs]hv]uhbjZhz]rnhƒXlinuxptpro…rp}rq(haUhbjkubahlj‡ubhƒX@ over the CPSW GMAC port for providing the PTP OC functionality.rr…rs}rt(haX@ over the CPSW GMAC port for providing the PTP OC functionality.hbjZubeubh§)ru}rv(haX™For example, once the AM57xx IDK is boot into Linux kernel prompt and the CPSW GMAC ports are properly configured, to run linuxptp over the GMAC port, dorwhbjKhjhŒhlh«hn}rx(hp]hq]hr]hs]hv]uhxMhyhhz]ryhƒX™For example, once the AM57xx IDK is boot into Linux kernel prompt and the CPSW GMAC ports are properly configured, to run linuxptp over the GMAC port, dorz…r{}r|(hajwhbjuubaubj9)r}}r~(haX ptp4l -2 -P -f oc_eth1.cfg -s -mhbjKhjhŒhlj<hn}r(hh‘hs]hr]hp]hq]hv]uhxMhyhhz]r€hƒX ptp4l -2 -P -f oc_eth1.cfg -s -mr…r‚}rƒ(haUhbj}ubaubh§)r„}r…(haX+oc\_eth1.cfg is a ptp4l configuration file.r†hbjKhjhŒhlh«hn}r‡(hp]hq]hr]hs]hv]uhxMhyhhz]rˆhƒX*oc_eth1.cfg is a ptp4l configuration file.r‰…rŠ}r‹(haX+oc\_eth1.cfg is a ptp4l configuration file.hbj„ubaubh§)rŒ}r(haXExample oc\_eth1.cfg for OC,rŽhbjKhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxMhyhhz]rhƒXExample oc_eth1.cfg for OC,r‘…r’}r“(haXExample oc\_eth1.cfg for OC,hbjŒubaubj9)r”}r•(haXš[global] tx_timestamp_timeout 10 logMinPdelayReqInterval -3 logSyncInterval -3 twoStepFlag 1 summary_interval 0 [et1] egressLatency 146 ingressLatency 246hbjKhjhŒhlj<hn}r–(hh‘hs]hr]hp]hq]hv]uhxM"hyhhz]r—hƒXš[global] tx_timestamp_timeout 10 logMinPdelayReqInterval -3 logSyncInterval -3 twoStepFlag 1 summary_interval 0 [et1] egressLatency 146 ingressLatency 246r˜…r™}rš(haUhbj”ubaubh§)r›}rœ(haXUwhere **eth1** is the intended GMAC port over which the OC functionality is provided.hbjKhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxM'hyhhz]rž(hƒXwhere rŸ…r }r¡(haXwhere hbj›ubj)r¢}r£(haX**eth1**hn}r¤(hp]hq]hr]hs]hv]uhbj›hz]r¥hƒXeth1r¦…r§}r¨(haUhbj¢ubahlj‡ubhƒXG is the intended GMAC port over which the OC functionality is provided.r©…rª}r«(haXG is the intended GMAC port over which the OC functionality is provided.hbj›ubeubh§)r¬}r­(haXOHere is a sample screen display of ptp4l for GMAC port as PTP/OC in slave mode:r®hbjKhjhŒhlh«hn}r¯(hp]hq]hr]hs]hv]uhxM*hyhhz]r°hƒXOHere is a sample screen display of ptp4l for GMAC port as PTP/OC in slave mode:r±…r²}r³(haj®hbj¬ubaubj9)r´}rµ(haX) root@am57xx-evm:~# ptp4l -2 -P -f oc_eth1.txt -s -m & [1] 1201 root@am57xx-evm:~# ptp4l[235215.373]: selected /dev/ptp0 as PTP clock ptp4l[235215.461]: port 1: INITIALIZING to LISTENING on INITIALIZE ptp4l[235215.462]: port 0: INITIALIZING to LISTENING on INITIALIZE ptp4l[235215.463]: port 1: link up ptp4l[235216.399]: port 1: new foreign master 8ca5a1.fffe.0000c2-1 ptp4l[235220.400]: selected best master clock 8ca5a1.fffe.0000c2 ptp4l[235220.400]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE ptp4l[235220.701]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED ptp4l[235221.451]: rms 3003 max 3986 (-3986, -1007) freq -883 +/- 2090 delay 55 +/- 1 ptp4l[235222.451]: rms 562 max 873 (-612, 873) freq +943 +/- 756 delay 54 +/- 1 ptp4l[235223.451]: rms 935 max 980 ( 838, 980) freq +2627 +/- 243 delay 54 +/- 0 ptp4l[235224.451]: rms 593 max 787 ( 366, 787) freq +2958 +/- 24 delay 54 +/- 0 ptp4l[235225.451]: rms 192 max 318 ( 54, 318) freq +2777 +/- 69 delay 54 +/- 0 ptp4l[235226.451]: rms 39 max 62 ( -62, 28) freq +2572 +/- 50 delay 55 +/- 1 ptp4l[235227.451]: rms 60 max 68 ( -68, -52) freq +2468 +/- 13 delay 55 +/- 0 ptp4l[235228.452]: rms 36 max 46 ( -46, -24) freq +2451 +/- 4 delay 54 +/- 1 ptp4l[235229.452]: rms 11 max 17 ( -17, 4) freq +2466 +/- 8 delay 53 +/- 0 ptp4l[235230.452]: rms 6 max 11 ( 2, 11) freq +2485 +/- 5 delay 54 +/- 0 ptp4l[235231.452]: rms 11 max 17 ( 3, 17) freq +2501 +/- 4 delay 54 +/- 0 ptp4l[235232.452]: rms 6 max 8 ( -6, 8) freq +2496 +/- 7 delay 55 +/- 1 ptp4l[235233.452]: rms 3 max 4 ( -4, 4) freq +2492 +/- 4 delay 56 +/- 0 ptp4l[235234.452]: rms 5 max 9 ( -7, 9) freq +2492 +/- 7 delay 55 +/- 1 ptp4l[235235.452]: rms 7 max 10 ( -10, 1) freq +2481 +/- 4 delay 55 +/- 1 ptp4l[235236.452]: rms 3 max 6 ( -6, 2) freq +2482 +/- 4 delay 53 +/- 0 ptp4l[235237.452]: rms 5 max 8 ( -8, 3) freq +2478 +/- 5 delay 54 +/- 0 ptp4l[235238.452]: rms 4 max 7 ( -7, 7) freq +2482 +/- 6 delay 54 +/- 0 ptp4l[235239.453]: rms 5 max 9 ( -6, 9) freq +2486 +/- 6 delay 54 +/- 0 ptp4l[235240.453]: rms 5 max 9 ( -9, 4) freq +2480 +/- 6 delay 55 +/- 0 ptp4l[235241.453]: rms 5 max 10 ( -10, 4) freq +2475 +/- 5 delay 56 +/- 0 ptp4l[235242.453]: rms 3 max 5 ( -1, 5) freq +2483 +/- 3 delay 56 +/- 0 ptp4l[235243.453]: rms 2 max 4 ( -1, 4) freq +2483 +/- 2 delay 56 +/- 0 ptp4l[235244.453]: rms 5 max 10 ( -10, -1) freq +2473 +/- 3 delay 55 +/- 0 ptp4l[235245.453]: rms 4 max 7 ( -6, 7) freq +2479 +/- 5 delay 55 +/- 0 ptp4l[235246.453]: rms 5 max 9 ( -1, 9) freq +2486 +/- 4 delay 54 +/- 1 ptp4l[235247.453]: rms 3 max 7 ( -7, 4) freq +2483 +/- 5 delay 55 +/- 0 ptp4l[235248.453]: rms 6 max 9 ( 2, 9) freq +2492 +/- 4 delay 55 +/- 0 ptp4l[235249.453]: rms 4 max 7 ( -3, 7) freq +2493 +/- 4 delay 57 +/- 0 ptp4l[235250.454]: rms 3 max 5 ( -5, 1) freq +2486 +/- 3 delay 55 +/- 1 ptp4l[235251.454]: rms 8 max 16 ( -16, -2) freq +2476 +/- 7 delay 54 +/- 1 ...hbjKhjhŒhlj<hn}r¶(hh‘hs]hr]hp]hq]hv]uhxM4hyhhz]r·hƒX) root@am57xx-evm:~# ptp4l -2 -P -f oc_eth1.txt -s -m & [1] 1201 root@am57xx-evm:~# ptp4l[235215.373]: selected /dev/ptp0 as PTP clock ptp4l[235215.461]: port 1: INITIALIZING to LISTENING on INITIALIZE ptp4l[235215.462]: port 0: INITIALIZING to LISTENING on INITIALIZE ptp4l[235215.463]: port 1: link up ptp4l[235216.399]: port 1: new foreign master 8ca5a1.fffe.0000c2-1 ptp4l[235220.400]: selected best master clock 8ca5a1.fffe.0000c2 ptp4l[235220.400]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE ptp4l[235220.701]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED ptp4l[235221.451]: rms 3003 max 3986 (-3986, -1007) freq -883 +/- 2090 delay 55 +/- 1 ptp4l[235222.451]: rms 562 max 873 (-612, 873) freq +943 +/- 756 delay 54 +/- 1 ptp4l[235223.451]: rms 935 max 980 ( 838, 980) freq +2627 +/- 243 delay 54 +/- 0 ptp4l[235224.451]: rms 593 max 787 ( 366, 787) freq +2958 +/- 24 delay 54 +/- 0 ptp4l[235225.451]: rms 192 max 318 ( 54, 318) freq +2777 +/- 69 delay 54 +/- 0 ptp4l[235226.451]: rms 39 max 62 ( -62, 28) freq +2572 +/- 50 delay 55 +/- 1 ptp4l[235227.451]: rms 60 max 68 ( -68, -52) freq +2468 +/- 13 delay 55 +/- 0 ptp4l[235228.452]: rms 36 max 46 ( -46, -24) freq +2451 +/- 4 delay 54 +/- 1 ptp4l[235229.452]: rms 11 max 17 ( -17, 4) freq +2466 +/- 8 delay 53 +/- 0 ptp4l[235230.452]: rms 6 max 11 ( 2, 11) freq +2485 +/- 5 delay 54 +/- 0 ptp4l[235231.452]: rms 11 max 17 ( 3, 17) freq +2501 +/- 4 delay 54 +/- 0 ptp4l[235232.452]: rms 6 max 8 ( -6, 8) freq +2496 +/- 7 delay 55 +/- 1 ptp4l[235233.452]: rms 3 max 4 ( -4, 4) freq +2492 +/- 4 delay 56 +/- 0 ptp4l[235234.452]: rms 5 max 9 ( -7, 9) freq +2492 +/- 7 delay 55 +/- 1 ptp4l[235235.452]: rms 7 max 10 ( -10, 1) freq +2481 +/- 4 delay 55 +/- 1 ptp4l[235236.452]: rms 3 max 6 ( -6, 2) freq +2482 +/- 4 delay 53 +/- 0 ptp4l[235237.452]: rms 5 max 8 ( -8, 3) freq +2478 +/- 5 delay 54 +/- 0 ptp4l[235238.452]: rms 4 max 7 ( -7, 7) freq +2482 +/- 6 delay 54 +/- 0 ptp4l[235239.453]: rms 5 max 9 ( -6, 9) freq +2486 +/- 6 delay 54 +/- 0 ptp4l[235240.453]: rms 5 max 9 ( -9, 4) freq +2480 +/- 6 delay 55 +/- 0 ptp4l[235241.453]: rms 5 max 10 ( -10, 4) freq +2475 +/- 5 delay 56 +/- 0 ptp4l[235242.453]: rms 3 max 5 ( -1, 5) freq +2483 +/- 3 delay 56 +/- 0 ptp4l[235243.453]: rms 2 max 4 ( -1, 4) freq +2483 +/- 2 delay 56 +/- 0 ptp4l[235244.453]: rms 5 max 10 ( -10, -1) freq +2473 +/- 3 delay 55 +/- 0 ptp4l[235245.453]: rms 4 max 7 ( -6, 7) freq +2479 +/- 5 delay 55 +/- 0 ptp4l[235246.453]: rms 5 max 9 ( -1, 9) freq +2486 +/- 4 delay 54 +/- 1 ptp4l[235247.453]: rms 3 max 7 ( -7, 4) freq +2483 +/- 5 delay 55 +/- 0 ptp4l[235248.453]: rms 6 max 9 ( 2, 9) freq +2492 +/- 4 delay 55 +/- 0 ptp4l[235249.453]: rms 4 max 7 ( -3, 7) freq +2493 +/- 4 delay 57 +/- 0 ptp4l[235250.454]: rms 3 max 5 ( -5, 1) freq +2486 +/- 3 delay 55 +/- 1 ptp4l[235251.454]: rms 8 max 16 ( -16, -2) freq +2476 +/- 7 delay 54 +/- 1 ...r¸…r¹}rº(haUhbj´ubaubju)r»}r¼(haUhbjKhjhŒhljxhn}r½(hp]hq]hr]hs]hv]uhxMZhyhhz]r¾j{)r¿}rÀ(haUj~Khbj»hjhŒhlhxhn}rÁ(hp]hq]hr]hs]hv]uhxKhyhhz]ubaubhc)rÂ}rÃ(haUh˜KhbjKhjhŒhlhmhn}rÄ(hp]rÅj†ahq]hr]hs]rÆUid2rÇahv]uhxM]hyhhz]rÈ(h|)rÉ}rÊ(haX%PHY Delay Compensation for AM57xx IDKrËhbjÂhjhŒhlh€hn}rÌ(hp]hq]hr]hs]hv]uhxM]hyhhz]rÍhƒX%PHY Delay Compensation for AM57xx IDKrÎ…rÏ}rÐ(hajËhbjÉubaubh§)rÑ}rÒ(haX¡The theoretical values to use for GMAC PHY, which is KSZ9031RN, on AM57xx IDKs, are not yet available. The following experimental values are recommended for now.rÓhbjÂhjhŒhlh«hn}rÔ(hp]hq]hr]hs]hv]uhxM_hyhhz]rÕhƒX¡The theoretical values to use for GMAC PHY, which is KSZ9031RN, on AM57xx IDKs, are not yet available. The following experimental values are recommended for now.rÖ…r×}rØ(hajÓhbjÑubaubjÊ)rÙ}rÚ(haUhbjÂhjhŒhljÍhn}rÛ(hp]hq]hr]hs]hv]uhxNhyhhz]rÜjÐ)rÝ}rÞ(haUhn}rß(hs]hr]hp]hq]hv]UcolsKuhbjÙhz]rà(jÕ)rá}râ(haUhn}rã(hs]hr]hp]hq]hv]UcolwidthKuhbjÝhz]hljÙubjÕ)rä}rå(haUhn}ræ(hs]hr]hp]hq]hv]UcolwidthKuhbjÝhz]hljÙubjÕ)rç}rè(haUhn}ré(hs]hr]hp]hq]hv]UcolwidthKuhbjÝhz]hljÙubjã)rê}rë(haUhn}rì(hp]hq]hr]hs]hv]uhbjÝhz]ríjè)rî}rï(haUhn}rð(hp]hq]hr]hs]hv]uhbjêhz]rñ(jí)rò}ró(haUhn}rô(hp]hq]hr]hs]hv]uhbjîhz]rõh§)rö}r÷(haXSpeedrøhbjòhjhŒhlh«hn}rù(hp]hq]hr]hs]hv]uhxMdhz]rúhƒXSpeedrû…rü}rý(hajøhbjöubaubahljúubjí)rþ}rÿ(haUhn}r (hp]hq]hr]hs]hv]uhbjîhz]r h§)r }r (haXEgress Latency (ns)r hbjþhjhŒhlh«hn}r (hp]hq]hr]hs]hv]uhxMdhz]r hƒXEgress Latency (ns)r …r }r (haj hbj ubaubahljúubjí)r }r (haUhn}r (hp]hq]hr]hs]hv]uhbjîhz]r h§)r }r (haXIngress Latency (ns)r hbj hjhŒhlh«hn}r (hp]hq]hr]hs]hv]uhxMdhz]r hƒXIngress Latency (ns)r …r }r (haj hbj ubaubahljúubehljubahlj ubj!)r }r (haUhn}r (hp]hq]hr]hs]hv]uhbjÝhz]r (jè)r }r (haUhn}r (hp]hq]hr]hs]hv]uhbj hz]r (jí)r }r (haUhn}r (hp]hq]hr]hs]hv]uhbj hz]r! h§)r" }r# (haX100Mbr$ hbj hjhŒhlh«hn}r% (hp]hq]hr]hs]hv]uhxMfhz]r& hƒX100Mbr' …r( }r) (haj$ hbj" ubaubahljúubjí)r* }r+ (haUhn}r, (hp]hq]hr]hs]hv]uhbj hz]r- h§)r. }r/ (haX546r0 hbj* hjhŒhlh«hn}r1 (hp]hq]hr]hs]hv]uhxMfhz]r2 hƒX546r3 …r4 }r5 (haj0 hbj. ubaubahljúubjí)r6 }r7 (haUhn}r8 (hp]hq]hr]hs]hv]uhbj hz]r9 h§)r: }r; (haX646r< hbj6 hjhŒhlh«hn}r= (hp]hq]hr]hs]hv]uhxMfhz]r> hƒX646r? …r@ }rA (haj< hbj: ubaubahljúubehljubjè)rB }rC (haUhn}rD (hp]hq]hr]hs]hv]uhbj hz]rE (jí)rF }rG (haUhn}rH (hp]hq]hr]hs]hv]uhbjB hz]rI h§)rJ }rK (haX1000MbrL hbjF hjhŒhlh«hn}rM (hp]hq]hr]hs]hv]uhxMhhz]rN hƒX1000MbrO …rP }rQ (hajL hbjJ ubaubahljúubjí)rR }rS (haUhn}rT (hp]hq]hr]hs]hv]uhbjB hz]rU h§)rV }rW (haX146rX hbjR hjhŒhlh«hn}rY (hp]hq]hr]hs]hv]uhxMhhz]rZ hƒX146r[ …r\ }r] (hajX hbjV ubaubahljúubjí)r^ }r_ (haUhn}r` (hp]hq]hr]hs]hv]uhbjB hz]ra h§)rb }rc (haX346rd hbj^ hjhŒhlh«hn}re (hp]hq]hr]hs]hv]uhxMhhz]rf hƒX346rg …rh }ri (hajd hbjb ubaubahljúubehljubehljRubehljSubaubeubeubhc)rj }rk (haUhbj hjhŒhlhmhn}rl (hp]hq]hr]hs]rm U test-setuprn ahv]ro hKauhxMlhyhhz]rp (h|)rq }rr (haX Test Setuprs hbjj hjhŒhlh€hn}rt (hp]hq]hr]hs]hv]uhxMlhyhhz]ru hƒX Test Setuprv …rw }rx (hajs hbjq ubaubj)ry }rz (haXSupported Platformsr{ hbjj hjhŒhlj¡hn}r| (hs]r} Usupported-platformsr~ ahr]hp]hq]hv]r h6auhxNhyhhz]r€ hƒXSupported Platformsr …r‚ }rƒ (haj{ hbjy ubaubh¹)r„ }r… (haUhbjj hjhŒhlh¼hn}r† (h¾X-hs]hr]hp]hq]hv]uhxMqhyhhz]r‡ (hÀ)rˆ }r‰ (haX AM335x ICE (PRU-ICSS0:eth0-eth1)rŠ hbj„ hjhŒhlhÃhn}r‹ (hp]hq]hr]hs]hv]uhxNhyhhz]rŒ h§)r }rŽ (hajŠ hbjˆ hjhŒhlh«hn}r (hp]hq]hr]hs]hv]uhxMqhz]r hƒX AM335x ICE (PRU-ICSS0:eth0-eth1)r‘ …r’ }r“ (hajŠ hbj ubaubaubhÀ)r” }r• (haX AM437x IDK (PRU-ICSS0:eth1-eth2)r– hbj„ hjhŒhlhÃhn}r— (hp]hq]hr]hs]hv]uhxNhyhhz]r˜ h§)r™ }rš (haj– hbj” hjhŒhlh«hn}r› (hp]hq]hr]hs]hv]uhxMrhz]rœ hƒX AM437x IDK (PRU-ICSS0:eth1-eth2)r …rž }rŸ (haj– hbj™ ubaubaubhÀ)r  }r¡ (haXJAM571x IDK (GMAC/CPTS: eth0-eth1, PRU-ICSS2:eth2-eth3,PRU-ICSS1:eth4-eth5)r¢ hbj„ hjhŒhlhÃhn}r£ (hp]hq]hr]hs]hv]uhxNhyhhz]r¤ h§)r¥ }r¦ (haj¢ hbj  hjhŒhlh«hn}r§ (hp]hq]hr]hs]hv]uhxMshz]r¨ hƒXJAM571x IDK (GMAC/CPTS: eth0-eth1, PRU-ICSS2:eth2-eth3,PRU-ICSS1:eth4-eth5)r© …rª }r« (haj¢ hbj¥ ubaubaubhÀ)r¬ }r­ (haX6AM572x IDK (GMAC/CPTS: eth0-eth1, PRU-ICSS2:eth2-eth3)r® hbj„ hjhŒhlhÃhn}r¯ (hp]hq]hr]hs]hv]uhxNhyhhz]r° h§)r± }r² (haj® hbj¬ hjhŒhlh«hn}r³ (hp]hq]hr]hs]hv]uhxMthz]r´ hƒX6AM572x IDK (GMAC/CPTS: eth0-eth1, PRU-ICSS2:eth2-eth3)rµ …r¶ }r· (haj® hbj± ubaubaubhÀ)r¸ }r¹ (haX2K2G ICE (PRU-ICSS2:eth1-eth2,PRU-ICSS1:eth3-eth4) hbj„ hjhŒhlhÃhn}rº (hp]hq]hr]hs]hv]uhxNhyhhz]r» h§)r¼ }r½ (haX1K2G ICE (PRU-ICSS2:eth1-eth2,PRU-ICSS1:eth3-eth4)r¾ hbj¸ hjhŒhlh«hn}r¿ (hp]hq]hr]hs]hv]uhxMuhz]rÀ hƒX1K2G ICE (PRU-ICSS2:eth1-eth2,PRU-ICSS1:eth3-eth4)rÁ …r }rà (haj¾ hbj¼ ubaubaubeubj)rÄ }rÅ (haXHardware ModificationsrÆ hbjj hjhŒhlj¡hn}rÇ (hs]rÈ Uid3rÉ ahr]hp]hq]hv]rÊ h+auhxNhyhhz]rË hƒXHardware ModificationsrÌ …rÍ }rÎ (hajÆ hbjÄ ubaubh§)rÏ }rÐ (haX+Refer to the :ref:`PLSDK_PTP_HW_Mods-label`rÑ hbjj hjhŒhlh«hn}rÒ (hp]hq]hr]hs]hv]uhxMzhyhhz]rÓ (hƒX Refer to the rÔ …rÕ }rÖ (haX Refer to the hbjÏ ubj”)r× }rØ (haX:ref:`PLSDK_PTP_HW_Mods-label`rÙ hbjÏ hjhŒhlj˜hn}rÚ (UreftypeXrefjšˆj›Xplsdk_ptp_hw_mods-labelU refdomainXstdrÛ hs]hr]U refexplicit‰hp]hq]hv]jjžuhxMzhz]rÜ j )rÝ }rÞ (hajÙ hn}rß (hp]hq]rà (j¥jÛ Xstd-refrá ehr]hs]hv]uhbj× hz]râ hƒXPLSDK_PTP_HW_Mods-labelrã …rä }rå (haUhbjÝ ubahlj«ubaubeubj)ræ }rç (haX6Using 1 PPS to measure synchronization accuracy/offsetrè hbjj hjhŒhlj¡hn}ré (hs]rê U5using-1-pps-to-measure-synchronization-accuracyoffsetrë ahr]hp]hq]hv]rì hPauhxNhyhhz]rí hƒX6Using 1 PPS to measure synchronization accuracy/offsetrî …rï }rð (hajè hbjæ ubaubh§)rñ }rò (haX­Some PTP test equipment and PTP-enabled Network adaptors provide 1PPS signal be used to measure the offset and jitters of the system time between the master and slave clock.ró hbjj hjhŒhlh«hn}rô (hp]hq]hr]hs]hv]uhxMhyhhz]rõ hƒX­Some PTP test equipment and PTP-enabled Network adaptors provide 1PPS signal be used to measure the offset and jitters of the system time between the master and slave clock.rö …r÷ }rø (hajó hbjñ ubaubj)rù }rú (haX)Test with Oregano Syn1588 Network Adaptorrû hbjj hjhŒhlj¡hn}rü (hs]rý U)test-with-oregano-syn1588-network-adaptorrþ ahr]hp]hq]hv]rÿ h(auhxNhyhhz]r hƒX)Test with Oregano Syn1588 Network Adaptorr …r }r (hajû hbjù ubaubh§)r }r (haX§The Oregano Syn1588 network adaptor `[2] `__\ is configured to be the PTP master clock with the Linux PTP/Ethernet utilities.hbjj hjhŒhlh«hn}r (hp]hq]hr]hs]hv]uhxM†hyhhz]r (hƒX$The Oregano Syn1588 network adaptor r …r }r (haX$The Oregano Syn1588 network adaptor hbj ubj_)r }r (haX2`[2] `__hn}r (UnameX[2]jvX(http://www.oreganosystems.at/?page_id=19hs]hr]hp]hq]hv]uhbj hz]r hƒX[2]r …r }r (haUhbj ubahljhubhƒXOis configured to be the PTP master clock with the Linux PTP/Ethernet utilities.r …r }r (haXQ\ is configured to be the PTP master clock with the Linux PTP/Ethernet utilities.hbj ubeubj)r }r (haX&Oregano Network Adaptor Configurationsr hbjj hjhŒhlj¡hn}r (hs]r U&oregano-network-adaptor-configurationsr ahr]hp]hq]hv]r h5auhxNhyhhz]r hƒX&Oregano Network Adaptor Configurationsr …r }r (haj hbj ubaubh§)r }r! (haXFEnter the regular ifconfig command to configure the desired IP addressr" hbjj hjhŒhlh«hn}r# (hp]hq]hr]hs]hv]uhxMhyhhz]r$ hƒXFEnter the regular ifconfig command to configure the desired IP addressr% …r& }r' (haj" hbj ubaubj9)r( }r) (haX#ifconfig enp4s0 192.168.3.20hbjj hjhŒhlj<hn}r* (hh‘hs]hr]hp]hq]hv]uhxM–hyhhz]r+ hƒX#ifconfig enp4s0 192.168.3.20r, …r- }r. (haUhbj( ubaubh§)r/ }r0 (haXlSpecify the network speed only if it is required, auto negotiation should be enabled for all other use casesr1 hbjj hjhŒhlh«hn}r2 (hp]hq]hr]hs]hv]uhxM“hyhhz]r3 hƒXlSpecify the network speed only if it is required, auto negotiation should be enabled for all other use casesr4 …r5 }r6 (haj1 hbj/ ubaubj9)r7 }r8 (haX„//Specify the Link Speed #ethtool -s np4s0 speed 100 duplex half autoneg off //enable auto negotiation #ethtool -s nep4s0 autoneg onhbjj hjhŒhlj<hn}r9 (hh‘hs]hr]hp]hq]hv]uhxMhyhhz]r: hƒX„//Specify the Link Speed #ethtool -s np4s0 speed 100 duplex half autoneg off //enable auto negotiation #ethtool -s nep4s0 autoneg onr; …r< }r= (haUhbj7 ubaubh§)r> }r? (haX^To configure the Oregano Network Adaptor as a PTP/OC master clock, enter the following commandr@ hbjj hjhŒhlh«hn}rA (hp]hq]hr]hs]hv]uhxMhyhhz]rB hƒX^To configure the Oregano Network Adaptor as a PTP/OC master clock, enter the following commandrC …rD }rE (haj@ hbj> ubaubj9)rF }rG (haX$#./ptp -i enp4s0 -L -CM_EXT -s-3 -DPhbjj hjhŒhlj<hn}rH (hh‘hs]hr]hp]hq]hv]uhxM§hyhhz]rI hƒX$#./ptp -i enp4s0 -L -CM_EXT -s-3 -DPrJ …rK }rL (haUhbjF ubaubj)rM }rN (haXPRU-ICSS Port ConfigurationsrO hbjj hjhŒhlj¡hn}rP (hs]rQ Upru-icss-port-configurationsrR ahr]hp]hq]hv]rS h$auhxNhyhhz]rT hƒXPRU-ICSS Port ConfigurationsrU …rV }rW (hajO hbjM ubaubh§)rX }rY (haX¡Follow the steps at :ref:`PLSDK_PRP_EMAC_Mode-label` to boot up the AM57xx IDK and configure the PRU-PRP firmware to run in PRP\_EMAC mode if using PRP firmware.hbjj hjhŒhlh«hn}rZ (hp]hq]hr]hs]hv]uhxM§hyhhz]r[ (hƒXFollow the steps at r\ …r] }r^ (haXFollow the steps at hbjX ubj”)r_ }r` (haX :ref:`PLSDK_PRP_EMAC_Mode-label`ra hbjX hjhŒhlj˜hn}rb (UreftypeXrefjšˆj›Xplsdk_prp_emac_mode-labelU refdomainXstdrc hs]hr]U refexplicit‰hp]hq]hv]jjžuhxM§hz]rd j )re }rf (haja hn}rg (hp]hq]rh (j¥jc Xstd-refri ehr]hs]hv]uhbj_ hz]rj hƒXPLSDK_PRP_EMAC_Mode-labelrk …rl }rm (haUhbje ubahlj«ubaubhƒXl to boot up the AM57xx IDK and configure the PRU-PRP firmware to run in PRP_EMAC mode if using PRP firmware.rn …ro }rp (haXm to boot up the AM57xx IDK and configure the PRU-PRP firmware to run in PRP\_EMAC mode if using PRP firmware.hbjX ubeubh§)rq }rr (haXIUse the ifconfig command to configure the desired IP address, for examplers hbjj hjhŒhlh«hn}rt (hp]hq]hr]hs]hv]uhxM«hyhhz]ru hƒXIUse the ifconfig command to configure the desired IP address, for examplerv …rw }rx (hajs hbjq ubaubj9)ry }rz (haX#ifconfig eth2 192.168.3.30hbjj hjhŒhlj<hn}r{ (hh‘hs]hr]hp]hq]hv]uhxM´hyhhz]r| hƒX#ifconfig eth2 192.168.3.30r} …r~ }r (haUhbjy ubaubh§)r€ }r (haXKVerify the Ethernet connection by pinging the IP address of the master portr‚ hbjj hjhŒhlh«hn}rƒ (hp]hq]hr]hs]hv]uhxM±hyhhz]r„ hƒXKVerify the Ethernet connection by pinging the IP address of the master portr… …r† }r‡ (haj‚ hbj€ ubaubj9)rˆ }r‰ (haX#ping 192.168.3.20hbjj hjhŒhlj<hn}rŠ (hh‘hs]hr]hp]hq]hv]uhxM»hyhhz]r‹ hƒX#ping 192.168.3.20rŒ …r }rŽ (haUhbjˆ ubaubju)r }r (haUhbjj hjhŒhljxhn}r‘ (hp]hq]hr]hs]hv]uhxM¸hyhhz]r’ (j{)r“ }r” (haUj~Khbj hjhŒhlhxhn}r• (hp]hq]hr]hs]hv]uhxKhyhhz]ubj{)r– }r— (haXkTo configure the PRU-ICSS port as a PTP/OC slave clock and enable 1PPS signal, enter the following commandsr˜ j~Khbj hjhŒhlhxhn}r™ (hp]hq]hr]hs]hv]uhxMºhyhhz]rš hƒXkTo configure the PRU-ICSS port as a PTP/OC slave clock and enable 1PPS signal, enter the following commandsr› …rœ }r (haj˜ hbj– ubaubeubj9)rž }rŸ (haXb#ptp4l -2 -P -f oc_eth2.txt -s -m & #echo 1 > /sys/devices/platform/pruss2_eth/ptp/ptp1/pps_enablehbjj hjhŒhlj<hn}r  (hh‘hs]hr]hp]hq]hv]uhxMÃhyhhz]r¡ hƒXb#ptp4l -2 -P -f oc_eth2.txt -s -m & #echo 1 > /sys/devices/platform/pruss2_eth/ptp/ptp1/pps_enabler¢ …r£ }r¤ (haUhbjž ubaubj)r¥ }r¦ (haXGMAC Port Configurationsr§ hbjj hjhŒhlj¡hn}r¨ (hs]r© Ugmac-port-configurationsrª ahr]hp]hq]hv]r« h4auhxNhyhhz]r¬ hƒXGMAC Port Configurationsr­ …r® }r¯ (haj§ hbj¥ ubaubh§)r° }r± (haXIUse the ifconfig command to configure the desired IP address, for exampler² hbjj hjhŒhlh«hn}r³ (hp]hq]hr]hs]hv]uhxMÄhyhhz]r´ hƒXIUse the ifconfig command to configure the desired IP address, for examplerµ …r¶ }r· (haj² hbj° ubaubj9)r¸ }r¹ (haX#ifconfig eth1 192.168.3.40hbjj hjhŒhlj<hn}rº (hh‘hs]hr]hp]hq]hv]uhxMÍhyhhz]r» hƒX#ifconfig eth1 192.168.3.40r¼ …r½ }r¾ (haUhbj¸ ubaubju)r¿ }rÀ (haUhbjj hjhŒhljxhn}rÁ (hp]hq]hr]hs]hv]uhxMÊhyhhz]r (j{)rà }rÄ (haUj~Khbj¿ hjhŒhlhxhn}rÅ (hp]hq]hr]hs]hv]uhxKhyhhz]ubj{)rÆ }rÇ (haXKVerify the Ethernet connection by pinging the IP address of the master portrÈ j~Khbj¿ hjhŒhlhxhn}rÉ (hp]hq]hr]hs]hv]uhxMÌhyhhz]rÊ hƒXKVerify the Ethernet connection by pinging the IP address of the master portrË …rÌ }rÍ (hajÈ hbjÆ ubaubeubj9)rÎ }rÏ (haX#ping 192.168.3.20hbjj hjhŒhlj<hn}rÐ (hh‘hs]hr]hp]hq]hv]uhxMÕhyhhz]rÑ hƒX#ping 192.168.3.20rÒ …rÓ }rÔ (haUhbjÎ ubaubju)rÕ }rÖ (haUhbjj hjhŒhljxhn}r× (hp]hq]hr]hs]hv]uhxMÒhyhhz]rØ (j{)rÙ }rÚ (haUj~KhbjÕ hjhŒhlhxhn}rÛ (hp]hq]hr]hs]hv]uhxKhyhhz]ubj{)rÜ }rÝ (haXgTo configure the GMAC port as a PTP/OC slave clock and enable 1PPS signal, enter the following commandsrÞ j~KhbjÕ hjhŒhlhxhn}rß (hp]hq]hr]hs]hv]uhxMÔhyhhz]rà hƒXgTo configure the GMAC port as a PTP/OC slave clock and enable 1PPS signal, enter the following commandsrá …râ }rã (hajÞ hbjÜ ubaubeubj9)rä }rå (haXv#ptp4l -2 -P -f oc_eth1.txt -s -m & #echo 1 > /sys/devices/platform/44000000.ocp/48484000.ethernet/ptp/ptp0/pps_enablehbjj hjhŒhlj<hn}ræ (hh‘hs]hr]hp]hq]hv]uhxMÝhyhhz]rç hƒXv#ptp4l -2 -P -f oc_eth1.txt -s -m & #echo 1 > /sys/devices/platform/44000000.ocp/48484000.ethernet/ptp/ptp0/pps_enablerè …ré }rê (haUhbjä ubaubeubhc)rë }rì (haUh˜Khbj hjhŒhlhmhn}rí (hp]rî X test resultsrï ahq]hr]hs]rð U test-resultsrñ ahv]uhxMÜhyhhz]rò (h|)ró }rô (haX Test Resultsrõ hbjë hjhŒhlh€hn}rö (hp]hq]hr]hs]hv]uhxMÜhyhhz]r÷ hƒX Test Resultsrø …rù }rú (hajõ hbjó ubaubh§)rû }rü (haXmThe following scope captures show the offset and jitters of the PPS signal between master and slave OC clock.rý hbjë hjhŒhlh«hn}rþ (hp]hq]hr]hs]hv]uhxMÞhyhhz]rÿ hƒXmThe following scope captures show the offset and jitters of the PPS signal between master and slave OC clock.r …r }r (hajý hbjû ubaubjº)r }r (haX*.. Image:: ../images/Pic_1pps_pruicss.png hbjë hjhŒhlj½hn}r (UuriX$linux/../images/Pic_1pps_pruicss.pngr hs]hr]hp]hq]jÀ}r U*j shv]uhxMâhyhhz]ubj9)r }r (haX5Figure 1: PPS: Oregano Master vs. PRU-ICSS Slave Porthbjë hjhŒhlj<hn}r (hh‘hs]hr]hp]hq]hv]uhxMêhyhhz]r hƒX5Figure 1: PPS: Oregano Master vs. PRU-ICSS Slave Portr …r }r (haUhbj ubaubju)r }r (haUhbjë hjhŒhljxhn}r (hp]hq]hr]hs]hv]uhxMçhyhhz]r j{)r }r (haUj~Khbj hjhŒhlhxhn}r (hp]hq]hr]hs]hv]uhxKhyhhz]ubaubjº)r }r (haX'.. Image:: ../images/Pic_1pps_cpts.png hbjë hjhŒhlj½hn}r (UuriX!linux/../images/Pic_1pps_cpts.pngr hs]hr]hp]hq]jÀ}r U*j shv]uhxMêhyhhz]ubj9)r }r (haX1Figure 2: PPS: Oregano Master vs. GMAC Slave Porthbjë hjhŒhlj<hn}r (hh‘hs]hr]hp]hq]hv]uhxMòhyhhz]r hƒX1Figure 2: PPS: Oregano Master vs. GMAC Slave Portr …r }r! (haUhbj ubaubeubeubhc)r" }r# (haUhbhhhjhŒhlhmhn}r$ (hp]hq]hr]hs]r% Uptp-boundary-clockr& ahv]r' h0auhxMðhyhhz]r( (h|)r) }r* (haXPTP Boundary Clockr+ hbj" hjhŒhlh€hn}r, (hp]hq]hr]hs]hv]uhxMðhyhhz]r- hƒXPTP Boundary Clockr. …r/ }r0 (haj+ hbj) ubaubh§)r1 }r2 (haXŒPTP boundary clock (BC) is supported on AM571x, AM572x and AM574x IDKs. In the case of AM571x IDK, BC with two to five ports is supported. These five ports can be any combination of GMAC and PRU ports, i.e., GMAC port, one or two ICSS1 PRU ports and one or two ICSS2 PRU ports. In the case of AM572x or AM574x IDK, BC with three ports, i.e., GMAC port and one or two ICSS2 PRU port, is supported.r3 hbj" hjhŒhlh«hn}r4 (hp]hq]hr]hs]hv]uhxMòhyhhz]r5 hƒXŒPTP boundary clock (BC) is supported on AM571x, AM572x and AM574x IDKs. In the case of AM571x IDK, BC with two to five ports is supported. These five ports can be any combination of GMAC and PRU ports, i.e., GMAC port, one or two ICSS1 PRU ports and one or two ICSS2 PRU ports. In the case of AM572x or AM574x IDK, BC with three ports, i.e., GMAC port and one or two ICSS2 PRU port, is supported.r6 …r7 }r8 (haj3 hbj1 ubaubhc)r9 }r: (haUh˜Khbj" hjhŒhlhmhn}r; (hp]r< j¦ahq]hr]hs]r= Uid4r> ahv]uhxMúhyhhz]r? (h|)r@ }rA (haXSoftware OverviewrB hbj9 hjhŒhlh€hn}rC (hp]hq]hr]hs]hv]uhxMúhyhhz]rD hƒXSoftware OverviewrE …rF }rG (hajB hbj@ ubaubh§)rH }rI (haXThere are four main components to the software together to provide the boundary clock functionality. These are, from low to high level, the ICSS PRU firmware, the related kernel ethernet drivers, the linuxptp ptp4l application and the linuxptp phc2sys application.rJ hbj9 hjhŒhlh«hn}rK (hp]hq]hr]hs]hv]uhxMühyhhz]rL hƒXThere are four main components to the software together to provide the boundary clock functionality. These are, from low to high level, the ICSS PRU firmware, the related kernel ethernet drivers, the linuxptp ptp4l application and the linuxptp phc2sys application.rM …rN }rO (hajJ hbjH ubaubhc)rP }rQ (haUhbj9 hjhŒhlhmhn}rR (hp]hq]hr]hs]rS Uicss-pru-firmwarerT ahv]rU h#auhxMhyhhz]rV (h|)rW }rX (haXICSS PRU FirmwarerY hbjP hjhŒhlh€hn}rZ (hp]hq]hr]hs]hv]uhxMhyhhz]r[ hƒXICSS PRU Firmwarer\ …r] }r^ (hajY hbjW ubaubh§)r_ }r` (haXÝThe ICSS PRU firmware used in BC is the PRP firmware (with PTP timestamping capability enabled) configured to run in Single Attached Node (SAN) mode or Dual Attached Node (DAN), the HSR firmware or the Dual EMAC firmware.ra hbjP hjhŒhlh«hn}rb (hp]hq]hr]hs]hv]uhxMhyhhz]rc hƒXÝThe ICSS PRU firmware used in BC is the PRP firmware (with PTP timestamping capability enabled) configured to run in Single Attached Node (SAN) mode or Dual Attached Node (DAN), the HSR firmware or the Dual EMAC firmware.rd …re }rf (haja hbj_ ubaubeubhc)rg }rh (haUhbj9 hjhŒhlhmhn}ri (hp]hq]hr]hs]rj Ucpsw-cpts-ethernet-driverrk ahv]rl hauhxM hyhhz]rm (h|)rn }ro (haXCPSW/CPTS Ethernet Driverrp hbjg hjhŒhlh€hn}rq (hp]hq]hr]hs]hv]uhxM hyhhz]rr hƒXCPSW/CPTS Ethernet Driverrs …rt }ru (hajp hbjn ubaubh§)rv }rw (haXGThis is the same CPSW/CPTS Ethernet driver implemented for GMAC PTP OC.rx hbjg hjhŒhlh«hn}ry (hp]hq]hr]hs]hv]uhxM hyhhz]rz hƒXGThis is the same CPSW/CPTS Ethernet driver implemented for GMAC PTP OC.r{ …r| }r} (hajx hbjv ubaubeubhc)r~ }r (haUhbj9 hjhŒhlhmhn}r€ (hp]hq]hr]hs]r Uicss-pru-iep-ethernet-driverr‚ ahv]rƒ h=auhxMhyhhz]r„ (h|)r… }r† (haXICSS-PRU/IEP Ethernet Driverr‡ hbj~ hjhŒhlh€hn}rˆ (hp]hq]hr]hs]hv]uhxMhyhhz]r‰ hƒXICSS-PRU/IEP Ethernet DriverrŠ …r‹ }rŒ (haj‡ hbj… ubaubh§)r }rŽ (haXAThis is the same ICSS PRU Ethernet driver implemented for PTP OC.r hbj~ hjhŒhlh«hn}r (hp]hq]hr]hs]hv]uhxMhyhhz]r‘ hƒXAThis is the same ICSS PRU Ethernet driver implemented for PTP OC.r’ …r“ }r” (haj hbj ubaubeubhc)r• }r– (haUhbj9 hjhŒhlhmhn}r— (hp]hq]hr]hs]r˜ U(bc-internal-clock-sync-monitoring-driverr™ ahv]rš hEauhxMhyhhz]r› (h|)rœ }r (haX(BC Internal Clock Sync Monitoring Driverrž hbj• hjhŒhlh€hn}rŸ (hp]hq]hr]hs]hv]uhxMhyhhz]r  hƒX(BC Internal Clock Sync Monitoring Driverr¡ …r¢ }r£ (hajž hbjœ ubaubh§)r¤ }r¥ (haXôA thin PTP BC driver layer is added on top of the ICSS-PRU/IEP and CPSW/CPTS Ethernet drivers in order to support the BC internal clock synchronization. This thin layer of driver is responsible for keeping track of which internal clock has its PPS enabled and giving permission to the requests by the internal clocks to generate PPS. Keeping track of PPS enablement is necessary because, at any instance of time, at most one clock can enable its PPS. For otherwise the SoC may be permanently damaged.r¦ hbj• hjhŒhlh«hn}r§ (hp]hq]hr]hs]hv]uhxMhyhhz]r¨ hƒXôA thin PTP BC driver layer is added on top of the ICSS-PRU/IEP and CPSW/CPTS Ethernet drivers in order to support the BC internal clock synchronization. This thin layer of driver is responsible for keeping track of which internal clock has its PPS enabled and giving permission to the requests by the internal clocks to generate PPS. Keeping track of PPS enablement is necessary because, at any instance of time, at most one clock can enable its PPS. For otherwise the SoC may be permanently damaged.r© …rª }r« (haj¦ hbj¤ ubaubeubhc)r¬ }r­ (haUhbj9 hjhŒhlhmhn}r® (hp]hq]hr]hs]r¯ Uapplication-linuxptp-ptp4lr° ahv]r± h auhxM hyhhz]r² (h|)r³ }r´ (haXApplication linuxptp ptp4lrµ hbj¬ hjhŒhlh€hn}r¶ (hp]hq]hr]hs]hv]uhxM hyhhz]r· hƒXApplication linuxptp ptp4lr¸ …r¹ }rº (hajµ hbj³ ubaubh§)r» }r¼ (haXThis is the application provides the BC PTP functionality. In the AM57xx BC, the linuxptp ptp4l program is configured to run in jbod (just a bunch of device) mode, i.e., the BC PTP clock is modelled on more than one internal clocks instead of one single clock.r½ hbj¬ hjhŒhlh«hn}r¾ (hp]hq]hr]hs]hv]uhxM"hyhhz]r¿ hƒXThis is the application provides the BC PTP functionality. In the AM57xx BC, the linuxptp ptp4l program is configured to run in jbod (just a bunch of device) mode, i.e., the BC PTP clock is modelled on more than one internal clocks instead of one single clock.rÀ …rÁ }r (haj½ hbj» ubaubeubhc)rà }rÄ (haUhbj9 hjhŒhlhmhn}rÅ (hp]hq]hr]hs]rÆ Uapplication-linuxptp-phc2sysrÇ ahv]rÈ h@auhxM(hyhhz]rÉ (h|)rÊ }rË (haXApplication linuxptp phc2sysrÌ hbjà hjhŒhlh€hn}rÍ (hp]hq]hr]hs]hv]uhxM(hyhhz]rÎ hƒXApplication linuxptp phc2sysrÏ …rÐ }rÑ (hajÌ hbjÊ ubaubh§)rÒ }rÓ (haXTThe linuxptp phc2sys is used to perform synchronization of the internal clocks of a BC in jbod mode. For AM57xx BC, the phc2sys is enhanced to support the synchronization of the BC internal clocks by reading the timestamps of the PPS generated by the internal master clock and captured by the internal slave clocks. phc2sys then feeds the timestamps into linuxptp's servo algorithm. The algorithm then produces the needed clock adjustment, usually in ppb of the nominal clock frequency, which is then passed to the kernel driver for clock adjustment by calling Linux PTP subsystem's standard API.rÔ hbjà hjhŒhlh«hn}rÕ (hp]hq]hr]hs]hv]uhxM*hyhhz]rÖ hƒXTThe linuxptp phc2sys is used to perform synchronization of the internal clocks of a BC in jbod mode. For AM57xx BC, the phc2sys is enhanced to support the synchronization of the BC internal clocks by reading the timestamps of the PPS generated by the internal master clock and captured by the internal slave clocks. phc2sys then feeds the timestamps into linuxptp's servo algorithm. The algorithm then produces the needed clock adjustment, usually in ppb of the nominal clock frequency, which is then passed to the kernel driver for clock adjustment by calling Linux PTP subsystem's standard API.r× …rØ }rÙ (hajÔ hbjÒ ubaubeubhc)rÚ }rÛ (haUhbj9 hjhŒhlhmhn}rÜ (hp]hq]hr]hs]rÝ Uinternal-clock-synchronizationrÞ ahv]rß h"auhxM5hyhhz]rà (h|)rá }râ (haXInternal Clock Synchronizationrã hbjÚ hjhŒhlh€hn}rä (hp]hq]hr]hs]hv]uhxM5hyhhz]rå hƒXInternal Clock Synchronizationræ …rç }rè (hajã hbjá ubaubh§)ré }rê (haXgAlthough the PTP clock time in the PTP network of the BC appears coming from one clock source, the PTP clock time available on the AM57xx ethernet ports are actually generated by different clocks internally. In particular, the PTP clock time on the CPSW GMAC port is generated by the CPTS module, and the PTP clock time on the ICSS PRU ports is generated by the corresponding IEP module on the respective ICSS. Since these clocks are running on their own separately, thus some internal synchronization mechanism is needed in order to make the AM57xx BC internal clocks appear as one clock source in the PTP network.rë hbjÚ hjhŒhlh«hn}rì (hp]hq]hr]hs]hv]uhxM7hyhhz]rí hƒXgAlthough the PTP clock time in the PTP network of the BC appears coming from one clock source, the PTP clock time available on the AM57xx ethernet ports are actually generated by different clocks internally. In particular, the PTP clock time on the CPSW GMAC port is generated by the CPTS module, and the PTP clock time on the ICSS PRU ports is generated by the corresponding IEP module on the respective ICSS. Since these clocks are running on their own separately, thus some internal synchronization mechanism is needed in order to make the AM57xx BC internal clocks appear as one clock source in the PTP network.rî …rï }rð (hajë hbjé ubaubh§)rñ }rò (haXÊThe internal clock synchronization can be considered in two parts. The first part is the alignment of the clock time up to within one second. This can easily be done by just reading one internal clock's time and write it to the other internal clock by application software alone under the assumption that the whole read and write operation takes less than one second. The other part of synchronization is to align the two clocks' time to the second boundary.ró hbjÚ hjhŒhlh«hn}rô (hp]hq]hr]hs]hv]uhxMAhyhhz]rõ hƒXÊThe internal clock synchronization can be considered in two parts. The first part is the alignment of the clock time up to within one second. This can easily be done by just reading one internal clock's time and write it to the other internal clock by application software alone under the assumption that the whole read and write operation takes less than one second. The other part of synchronization is to align the two clocks' time to the second boundary.rö …r÷ }rø (hajó hbjñ ubaubh§)rù }rú (haXÞIn this AM57xx BC implementation, the alignment of two internal clocks' time to the second boundary is done by using the PPS generated by one internal (master) clock latched into another internal (slave) clock. This means that the PPS received by an internal clock is timestamped. This timestamp is then consumed by a servo application in the calculation of the adjustment needed in order to align the internal slave clock's second boundary to that of the internal master clock.rû hbjÚ hjhŒhlh«hn}rü (hp]hq]hr]hs]hv]uhxMIhyhhz]rý hƒXÞIn this AM57xx BC implementation, the alignment of two internal clocks' time to the second boundary is done by using the PPS generated by one internal (master) clock latched into another internal (slave) clock. This means that the PPS received by an internal clock is timestamped. This timestamp is then consumed by a servo application in the calculation of the adjustment needed in order to align the internal slave clock's second boundary to that of the internal master clock.rþ …rÿ }r (hajû hbjù ubaubh§)r }r (haXÁHere the internal master clock of the BC is the internal clock that is synchronized to a PTP master clock over the PTP network, i.e., the corresponding ethernet port is in PTP slave port state.r hbjÚ hjhŒhlh«hn}r (hp]hq]hr]hs]hv]uhxMQhyhhz]r hƒXÁHere the internal master clock of the BC is the internal clock that is synchronized to a PTP master clock over the PTP network, i.e., the corresponding ethernet port is in PTP slave port state.r …r }r (haj hbj ubaubeubeubhc)r }r (haUh˜Khbj" hjhŒhlhmhn}r (hp]r j¶ahq]hr]hs]r Uid5r ahv]uhxMVhyhhz]r (h|)r }r (haXHardware Overviewr hbj hjhŒhlh€hn}r (hp]hq]hr]hs]hv]uhxMVhyhhz]r hƒXHardware Overviewr …r }r (haj hbj ubaubh§)r }r (haX For AM57xx IDK BC, since PPS generated by one internal clock needs to be latched into another internal clock, hardware, mainly blue wire, modifications are needed in order to achieve the latching of the PPS generated by one internal clock into another internal clock.r hbj hjhŒhlh«hn}r (hp]hq]hr]hs]hv]uhxMXhyhhz]r hƒX For AM57xx IDK BC, since PPS generated by one internal clock needs to be latched into another internal clock, hardware, mainly blue wire, modifications are needed in order to achieve the latching of the PPS generated by one internal clock into another internal clock.r …r }r (haj hbj ubaubh§)r }r! (haX+Refer to the :ref:`PLSDK_PTP_HW_Mods-label`r" hbj hjhŒhlh«hn}r# (hp]hq]hr]hs]hv]uhxM]hyhhz]r$ (hƒX Refer to the r% …r& }r' (haX Refer to the hbj ubj”)r( }r) (haX:ref:`PLSDK_PTP_HW_Mods-label`r* hbj hjhŒhlj˜hn}r+ (UreftypeXrefjšˆj›Xplsdk_ptp_hw_mods-labelU refdomainXstdr, hs]hr]U refexplicit‰hp]hq]hv]jjžuhxM]hz]r- j )r. }r/ (haj* hn}r0 (hp]hq]r1 (j¥j, Xstd-refr2 ehr]hs]hv]uhbj( hz]r3 hƒXPLSDK_PTP_HW_Mods-labelr4 …r5 }r6 (haUhbj. ubahlj«ubaubeubeubhc)r7 }r8 (haUh˜Khbj" hjhŒhlhmhn}r9 (hp]r: Xtest setup/procedurer; ahq]hr]hs]r< Utest-setup-procedurer= ahv]uhxM`hyhhz]r> (h|)r? }r@ (haXTest Setup/ProcedurerA hbj7 hjhŒhlh€hn}rB (hp]hq]hr]hs]hv]uhxM`hyhhz]rC hƒXTest Setup/ProcedurerD …rE }rF (hajA hbj? ubaubhc)rG }rH (haUhbj7 hjhŒhlhmhn}rI (hp]hq]hr]hs]rJ Usample-bc-setupsrK ahv]rL hIauhxMchyhhz]rM (h|)rN }rO (haXSample BC SetupsrP hbjG hjhŒhlh€hn}rQ (hp]hq]hr]hs]hv]uhxMchyhhz]rR hƒXSample BC SetupsrS …rT }rU (hajP hbjN ubaubh§)rV }rW (haXAA sample set up for 3-port BC for testing purpose is shown below.rX hbjG hjhŒhlh«hn}rY (hp]hq]hr]hs]hv]uhxMehyhhz]rZ hƒXAA sample set up for 3-port BC for testing purpose is shown below.r[ …r\ }r] (hajX hbjV ubaubjº)r^ }r_ (haX$.. Image:: ../images/Bc_connect.jpg hbjG hjhŒhlj½hn}r` (UuriXlinux/../images/Bc_connect.jpgra hs]hr]hp]hq]jÀ}rb U*ja shv]uhxMhhyhhz]ubh§)rc }rd (haXIn this scenario, the BC ICSS2 PRU port (interface eth2) is in PTP slave state (ICSS2-IEP is the BC internal master clock). The other two ports, BC ICSS1 (interface eth4) and BC CPSW/CPTS (interface eth1) are in PTP master state (ICSS1-IEP and CPTS are the BC internal slave clocks).re hbjG hjhŒhlh«hn}rf (hp]hq]hr]hs]hv]uhxMihyhhz]rg hƒXIn this scenario, the BC ICSS2 PRU port (interface eth2) is in PTP slave state (ICSS2-IEP is the BC internal master clock). The other two ports, BC ICSS1 (interface eth4) and BC CPSW/CPTS (interface eth1) are in PTP master state (ICSS1-IEP and CPTS are the BC internal slave clocks).rh …ri }rj (haje hbjc ubaubh§)rk }rl (haXMA sample set up for BC with HSR/PRP ports for testing purpose is shown below.rm hbjG hjhŒhlh«hn}rn (hp]hq]hr]hs]hv]uhxMohyhhz]ro hƒXMA sample set up for BC with HSR/PRP ports for testing purpose is shown below.rp …rq }rr (hajm hbjk ubaubjº)rs }rt (haX(.. Image:: ../images/Bc_dan_connect.jpg hbjG hjhŒhlj½hn}ru (UuriX"linux/../images/Bc_dan_connect.jpgrv hs]hr]hp]hq]jÀ}rw U*jv shv]uhxMshyhhz]ubh§)rx }ry (haXIn this scenario, the BC CPSW/CPTS (interface eth1) is in PTP slave state (CPTS is the BC internal master clock). The other two ports, BC ICSS1 (interface eth4/eth5) and BC ICSS2 (interface eth2/3) are in PTP master state (ICSS1-IEP and ICSS2-IEP are the BC internal slave clocks).rz hbjG hjhŒhlh«hn}r{ (hp]hq]hr]hs]hv]uhxMthyhhz]r| hƒXIn this scenario, the BC CPSW/CPTS (interface eth1) is in PTP slave state (CPTS is the BC internal master clock). The other two ports, BC ICSS1 (interface eth4/eth5) and BC ICSS2 (interface eth2/3) are in PTP master state (ICSS1-IEP and ICSS2-IEP are the BC internal slave clocks).r} …r~ }r (hajz hbjx ubaubj)r€ }r (haX Getting a PTP master clock readyr‚ hbjG hjhŒhlj¡hn}rƒ (hs]r„ U getting-a-ptp-master-clock-readyr… ahr]hp]hq]hv]r† hMauhxNhyhhz]r‡ hƒX Getting a PTP master clock readyrˆ …r‰ }rŠ (haj‚ hbj€ ubaubh§)r‹ }rŒ (haX}Start a reference PTP master clock that is connected in the PTP network as shown in the `sample setup <#sample-bc-setups>`__.hbjG hjhŒhlh«hn}r (hp]hq]hr]hs]hv]uhxM~hyhhz]rŽ (hƒXXStart a reference PTP master clock that is connected in the PTP network as shown in the r …r }r‘ (haXXStart a reference PTP master clock that is connected in the PTP network as shown in the hbj‹ ubj_)r’ }r“ (haX$`sample setup <#sample-bc-setups>`__hn}r” (UnameX sample setupjvX#sample-bc-setupshs]hr]hp]hq]hv]uhbj‹ hz]r• hƒX sample setupr– …r— }r˜ (haUhbj’ ubahljhubhƒX.…r™ }rš (haX.hbj‹ ubeubh§)r› }rœ (haXgIf the PTP master clock is an AM572x OC running linuxptp ptp4l, and for testing purpose, a line such asr hbjG hjhŒhlh«hn}rž (hp]hq]hr]hs]hv]uhxMhyhhz]rŸ hƒXgIf the PTP master clock is an AM572x OC running linuxptp ptp4l, and for testing purpose, a line such asr  …r¡ }r¢ (haj hbj› ubaubj9)r£ }r¤ (haX clockClass 6hbjG hjhŒhlj<hn}r¥ (hh‘hs]hr]hp]hq]hv]uhxM‹hyhhz]r¦ hƒX clockClass 6r§ …r¨ }r© (haUhbj£ ubaubh§)rª }r« (haX½in the [global] section of the OC's linuxptp configuration file can be helpful to make sure that the OC will be a master clock. Refer to :ref:`PLSDK_PTP_OC-label` for starting an AM57xx OC.hbjG hjhŒhlh«hn}r¬ (hp]hq]hr]hs]hv]uhxMˆhyhhz]r­ (hƒX‰in the [global] section of the OC's linuxptp configuration file can be helpful to make sure that the OC will be a master clock. Refer to r® …r¯ }r° (haX‰in the [global] section of the OC's linuxptp configuration file can be helpful to make sure that the OC will be a master clock. Refer to hbjª ubj”)r± }r² (haX:ref:`PLSDK_PTP_OC-label`r³ hbjª hjhŒhlj˜hn}r´ (UreftypeXrefjšˆj›Xplsdk_ptp_oc-labelU refdomainXstdrµ hs]hr]U refexplicit‰hp]hq]hv]jjžuhxMˆhz]r¶ j )r· }r¸ (haj³ hn}r¹ (hp]hq]rº (j¥jµ Xstd-refr» ehr]hs]hv]uhbj± hz]r¼ hƒXPLSDK_PTP_OC-labelr½ …r¾ }r¿ (haUhbj· ubahlj«ubaubhƒX for starting an AM57xx OC.rÀ …rÁ }r (haX for starting an AM57xx OC.hbjª ubeubju)rà }rÄ (haUhbjG hjhŒhljxhn}rÅ (hp]hq]hr]hs]hv]uhxMŒhyhhz]rÆ j{)rÇ }rÈ (haUj~Khbjà hjhŒhlhxhn}rÉ (hp]hq]hr]hs]hv]uhxKhyhhz]ubaubj)rÊ }rË (haX Preparation on the AM57xx BC IDKrÌ hbjG hjhŒhlj¡hn}rÍ (hs]rÎ U preparation-on-the-am57xx-bc-idkrÏ ahr]hp]hq]hv]rÐ h auhxNhyhhz]rÑ hƒX Preparation on the AM57xx BC IDKrÒ …rÓ }rÔ (hajÌ hbjÊ ubaubh§)rÕ }rÖ (haX°This section assumes that an AM571x is used. It should be similar for AM572x (or AM574x IDK) except that information about ICSS1 PRU (PRUSS1), eth4 and eth5 are not applicable.r× hbjG hjhŒhlh«hn}rØ (hp]hq]hr]hs]hv]uhxM‘hyhhz]rÙ hƒX°This section assumes that an AM571x is used. It should be similar for AM572x (or AM574x IDK) except that information about ICSS1 PRU (PRUSS1), eth4 and eth5 are not applicable.rÚ …rÛ }rÜ (haj× hbjÕ ubaubeubhc)rÝ }rÞ (haUh˜Khbj7 hjhŒhlhmhn}rß (hp]rà Xhardwarerá ahq]hr]hs]râ Uhardwarerã ahv]uhxM–hyhhz]rä (h|)rå }ræ (haXHardwarerç hbjÝ hjhŒhlh€hn}rè (hp]hq]hr]hs]hv]uhxM–hyhhz]ré hƒXHardwarerê …rë }rì (hajç hbjå ubaubj)rí }rî (haX AM571x IDKrï hbjÝ hjhŒhlj¡hn}rð (hs]rñ U am571x-1-idkrò ahr]hp]hq]hv]ró hSauhxNhyhhz]rô hƒX AM571x IDKrõ …rö }r÷ (hajï hbjí ubaubh§)rø }rù (haXšConnect the following 4 pins together. See the `AM571x Mod List `__ for more details.hbjÝ hjhŒhlh«hn}rú (hp]hq]hr]hs]hv]uhxM›hyhhz]rû (hƒX/Connect the following 4 pins together. See the rü …rý }rþ (haX/Connect the following 4 pins together. See the hbjø ubj_)rÿ }r (haXY`AM571x Mod List `__hn}r (UnameXAM571x Mod ListjvXChttp://processors.wiki.ti.com/images/6/66/Am571x_idk_bc_ModList.pdfhs]hr]hp]hq]hv]uhbjø hz]r hƒXAM571x Mod Listr …r }r (haUhbjÿ ubahljhubhƒX for more details.r …r }r (haX for more details.hbjø ubeubjÊ)r }r (haUhbjÝ hjNhljÍhn}r (hp]hq]hr]hs]hv]uhxNhyhhz]r jÐ)r }r (haUhn}r (hs]hr]hp]hq]hv]UcolsKuhbj hz]r (jÕ)r }r (haUhn}r (hs]hr]hp]hq]hv]UcolwidthK&uhbj hz]hljÙubjÕ)r }r (haUhn}r (hs]hr]hp]hq]hv]UcolwidthK&uhbj hz]hljÙubjã)r }r (haUhn}r (hp]hq]hr]hs]hv]uhbj hz]r jè)r }r (haUhn}r (hp]hq]hr]hs]hv]uhbj hz]r (jí)r }r (haUhn}r! (hp]hq]hr]hs]hv]uhbj hz]r" h§)r# }r$ (haXWire on AM571x IDKr% hbj hjhŒhlh«hn}r& (hp]hq]hr]hs]hv]uhxM hz]r' hƒXWire on AM571x IDKr( …r) }r* (haj% hbj# ubaubahljúubjí)r+ }r, (haUhn}r- (hp]hq]hr]hs]hv]uhbj hz]r. h§)r/ }r0 (haXSignalr1 hbj+ hjhŒhlh«hn}r2 (hp]hq]hr]hs]hv]uhxM hz]r3 hƒXSignalr4 …r5 }r6 (haj1 hbj/ ubaubahljúubehljubahlj ubj!)r7 }r8 (haUhn}r9 (hp]hq]hr]hs]hv]uhbj hz]r: (jè)r; }r< (haUhn}r= (hp]hq]hr]hs]hv]uhbj7 hz]r> (jí)r? }r@ (haUhn}rA (hp]hq]hr]hs]hv]uhbj; hz]rB h§)rC }rD (haXlower yellow wirerE hbj? hjhŒhlh«hn}rF (hp]hq]hr]hs]hv]uhxM¢hz]rG hƒXlower yellow wirerH …rI }rJ (hajE hbjC ubaubahljúubjí)rK }rL (haUhn}rM (hp]hq]hr]hs]hv]uhbj; hz]rN (cdocutils.nodes raw rO )rP }rQ (haX!
hbjK hjhŒhlUrawrR hn}rS (UformatXhtmlhh‘hs]hr]hp]hq]hv]uhxM¢hz]rT hƒX!
rU …rV }rW (haUhbjP ubaubh§)rX }rY (haXtimer15rZ hbjK hjhŒhlh«hn}r[ (hp]hq]hr]hs]hv]uhxM¦hz]r\ hƒXtimer15r] …r^ }r_ (hajZ hbjX ubaubjO )r` }ra (haX
hbjK hjhŒhljR hn}rb (UformatXhtmlhh‘hs]hr]hp]hq]hv]uhxM¨hz]rc hƒX
rd …re }rf (haUhbj` ubaubehljúubehljubjè)rg }rh (haUhn}ri (hp]hq]hr]hs]hv]uhbj7 hz]rj (jí)rk }rl (haUhn}rm (hp]hq]hr]hs]hv]uhbjg hz]rn h§)ro }rp (haXJ21-18 right blue wirerq hbjk hjhŒhlh«hn}rr (hp]hq]hr]hs]hv]uhxM¬hz]rs hƒXJ21-18 right blue wirert …ru }rv (hajq hbjo ubaubahljúubjí)rw }rx (haUhn}ry (hp]hq]hr]hs]hv]uhbjg hz]rz (jO )r{ }r| (haX!
hbjw hjhŒhljR hn}r} (UformatXhtmlhh‘hs]hr]hp]hq]hv]uhxM¬hz]r~ hƒX!
r …r€ }r (haUhbj{ ubaubh§)r‚ }rƒ (haXpr2\_edc\_latch0\_outhbjw hjhŒhlh«hn}r„ (hp]hq]hr]hs]hv]uhxM°hz]r… hƒXpr2_edc_latch0_outr† …r‡ }rˆ (haXpr2\_edc\_latch0\_outhbj‚ ubaubjO )r‰ }rŠ (haX
hbjw hjhŒhljR hn}r‹ (UformatXhtmlhh‘hs]hr]hp]hq]hv]uhxM²hz]rŒ hƒX
r …rŽ }r (haUhbj‰ ubaubehljúubehljubjè)r }r‘ (haUhn}r’ (hp]hq]hr]hs]hv]uhbj7 hz]r“ (jí)r” }r• (haUhn}r– (hp]hq]hr]hs]hv]uhbj hz]r— h§)r˜ }r™ (haXJ21-20 purple wirerš hbj” hjhŒhlh«hn}r› (hp]hq]hr]hs]hv]uhxM¶hz]rœ hƒXJ21-20 purple wirer …rž }rŸ (hajš hbj˜ ubaubahljúubjí)r  }r¡ (haUhn}r¢ (hp]hq]hr]hs]hv]uhbj hz]r£ (jO )r¤ }r¥ (haX!
hbj  hjhŒhljR hn}r¦ (UformatXhtmlhh‘hs]hr]hp]hq]hv]uhxM¶hz]r§ hƒX!
r¨ …r© }rª (haUhbj¤ ubaubh§)r« }r¬ (haXpr1\_edc\_latch0\_outhbj  hjhŒhlh«hn}r­ (hp]hq]hr]hs]hv]uhxMºhz]r® hƒXpr1_edc_latch0_outr¯ …r° }r± (haXpr1\_edc\_latch0\_outhbj« ubaubjO )r² }r³ (haX
hbj  hjhŒhljR hn}r´ (UformatXhtmlhh‘hs]hr]hp]hq]hv]uhxM¼hz]rµ hƒX
r¶ …r· }r¸ (haUhbj² ubaubehljúubehljubjè)r¹ }rº (haUhn}r» (hp]hq]hr]hs]hv]uhbj7 hz]r¼ (jí)r½ }r¾ (haUhn}r¿ (hp]hq]hr]hs]hv]uhbj¹ hz]rÀ h§)rÁ }r (haXJ21-54 left blue wirerà hbj½ hjhŒhlh«hn}rÄ (hp]hq]hr]hs]hv]uhxMÀhz]rÅ hƒXJ21-54 left blue wirerÆ …rÇ }rÈ (hajà hbjÁ ubaubahljúubjí)rÉ }rÊ (haUhn}rË (hp]hq]hr]hs]hv]uhbj¹ hz]rÌ (jO )rÍ }rÎ (haX!
hbjÉ hjhŒhljR hn}rÏ (UformatXhtmlhh‘hs]hr]hp]hq]hv]uhxMÀhz]rÐ hƒX!
rÑ …rÒ }rÓ (haUhbjÍ ubaubh§)rÔ }rÕ (haXpr1\_edc\_sync0\_outhbjÉ hjhŒhlh«hn}rÖ (hp]hq]hr]hs]hv]uhxMÄhz]r× hƒXpr1_edc_sync0_outrØ …rÙ }rÚ (haXpr1\_edc\_sync0\_outhbjÔ ubaubjO )rÛ }rÜ (haX
hbjÉ hjhŒhljR hn}rÝ (UformatXhtmlhh‘hs]hr]hp]hq]hv]uhxMÆhz]rÞ hƒX
rß …rà }rá (haUhbjÛ ubaubehljúubehljubehljRubehljSubaubh§)râ }rã (haXKExample: See below pictures (J21 is the connector along the top right edge)rä hbjÝ hjhŒhlh«hn}rå (hp]hq]hr]hs]hv]uhxMËhyhhz]ræ hƒXKExample: See below pictures (J21 is the connector along the top right edge)rç …rè }ré (hajä hbjâ ubaubjº)rê }rë (haX-.. Image:: ../images/Am571x_whole_small2.png hbjÝ hjhŒhlj½hn}rì (UuriX'linux/../images/Am571x_whole_small2.pngrí hs]hr]hp]hq]jÀ}rî U*jí shv]uhxMÎhyhhz]ubh§)rï }rð (haX3and this more J21 focused of the same picture aboverñ hbjÝ hjhŒhlh«hn}rò (hp]hq]hr]hs]hv]uhxMÏhyhhz]ró hƒX3and this more J21 focused of the same picture aboverô …rõ }rö (hajñ hbjï ubaubjº)r÷ }rø (haX$.. Image:: ../images/Am571x_j21.png hbjÝ hjhŒhlj½hn}rù (UuriXlinux/../images/Am571x_j21.pngrú hs]hr]hp]hq]jÀ}rû U*jú shv]uhxMÒhyhhz]ubj)rü }rý (haXAM572x and AM574x IDKrþ hbjÝ hjhŒhlj¡hn}rÿ (hs]rUam572x-1rahr]hp]hq]hv]rhauhxNhyhhz]rhƒXAM572x and AM574x IDKr…r}r(hajþ hbjü ubaubh§)r}r(haXšConnect the following 3 pins together. See the `AM572x Mod List `__ for more details.hbjÝ hjhŒhlh«hn}r (hp]hq]hr]hs]hv]uhxMÖhyhhz]r (hƒX/Connect the following 3 pins together. See the r …r }r (haX/Connect the following 3 pins together. See the hbjubj_)r}r(haXY`AM572x Mod List `__hn}r(UnameXAM572x Mod ListjvXChttp://processors.wiki.ti.com/images/c/c3/Am572x_idk_bc_ModList.pdfhs]hr]hp]hq]hv]uhbjhz]rhƒXAM572x Mod Listr…r}r(haUhbjubahljhubhƒX for more details.r…r}r(haX for more details.hbjubeubjÊ)r}r(haUhbjÝ hjNhljÍhn}r(hp]hq]hr]hs]hv]uhxNhyhhz]rjÐ)r}r(haUhn}r(hs]hr]hp]hq]hv]UcolsKuhbjhz]r(jÕ)r }r!(haUhn}r"(hs]hr]hp]hq]hv]UcolwidthK&uhbjhz]hljÙubjÕ)r#}r$(haUhn}r%(hs]hr]hp]hq]hv]UcolwidthK&uhbjhz]hljÙubjã)r&}r'(haUhn}r((hp]hq]hr]hs]hv]uhbjhz]r)jè)r*}r+(haUhn}r,(hp]hq]hr]hs]hv]uhbj&hz]r-(jí)r.}r/(haUhn}r0(hp]hq]hr]hs]hv]uhbj*hz]r1h§)r2}r3(haXWire on AM574x IDKr4hbj.hjhŒhlh«hn}r5(hp]hq]hr]hs]hv]uhxMÜhz]r6hƒXWire on AM574x IDKr7…r8}r9(haj4hbj2ubaubahljúubjí)r:}r;(haUhn}r<(hp]hq]hr]hs]hv]uhbj*hz]r=h§)r>}r?(haXSignalr@hbj:hjhŒhlh«hn}rA(hp]hq]hr]hs]hv]uhxMÜhz]rBhƒXSignalrC…rD}rE(haj@hbj>ubaubahljúubehljubahlj ubj!)rF}rG(haUhn}rH(hp]hq]hr]hs]hv]uhbjhz]rI(jè)rJ}rK(haUhn}rL(hp]hq]hr]hs]hv]uhbjFhz]rM(jí)rN}rO(haUhn}rP(hp]hq]hr]hs]hv]uhbjJhz]rQh§)rR}rS(haXCenter left black wirerThbjNhjhŒhlh«hn}rU(hp]hq]hr]hs]hv]uhxMÞhz]rVhƒXCenter left black wirerW…rX}rY(hajThbjRubaubahljúubjí)rZ}r[(haUhn}r\(hp]hq]hr]hs]hv]uhbjJhz]r](jO )r^}r_(haX!
hbjZhjhŒhljR hn}r`(UformatXhtmlhh‘hs]hr]hp]hq]hv]uhxMÞhz]rahƒX!
rb…rc}rd(haUhbj^ubaubh§)re}rf(haXtimer15rghbjZhjhŒhlh«hn}rh(hp]hq]hr]hs]hv]uhxMâhz]rihƒXtimer15rj…rk}rl(hajghbjeubaubjO )rm}rn(haX
hbjZhjhŒhljR hn}ro(UformatXhtmlhh‘hs]hr]hp]hq]hv]uhxMähz]rphƒX
rq…rr}rs(haUhbjmubaubehljúubehljubjè)rt}ru(haUhn}rv(hp]hq]hr]hs]hv]uhbjFhz]rw(jí)rx}ry(haUhn}rz(hp]hq]hr]hs]hv]uhbjthz]r{h§)r|}r}(haXJ21-13 black wirer~hbjxhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxMèhz]r€hƒXJ21-13 black wirer…r‚}rƒ(haj~hbj|ubaubahljúubjí)r„}r…(haUhn}r†(hp]hq]hr]hs]hv]uhbjthz]r‡(jO )rˆ}r‰(haX!
hbj„hjhŒhljR hn}rŠ(UformatXhtmlhh‘hs]hr]hp]hq]hv]uhxMèhz]r‹hƒX!
rŒ…r}rŽ(haUhbjˆubaubh§)r}r(haXpr2\_edc\_latch0\_outhbj„hjhŒhlh«hn}r‘(hp]hq]hr]hs]hv]uhxMìhz]r’hƒXpr2_edc_latch0_outr“…r”}r•(haXpr2\_edc\_latch0\_outhbjubaubjO )r–}r—(haX
hbj„hjhŒhljR hn}r˜(UformatXhtmlhh‘hs]hr]hp]hq]hv]uhxMîhz]r™hƒX
rš…r›}rœ(haUhbj–ubaubehljúubehljubjè)r}rž(haUhn}rŸ(hp]hq]hr]hs]hv]uhbjFhz]r (jí)r¡}r¢(haUhn}r£(hp]hq]hr]hs]hv]uhbjhz]r¤h§)r¥}r¦(haXJ21-17 white wirer§hbj¡hjhŒhlh«hn}r¨(hp]hq]hr]hs]hv]uhxMòhz]r©hƒXJ21-17 white wirerª…r«}r¬(haj§hbj¥ubaubahljúubjí)r­}r®(haUhn}r¯(hp]hq]hr]hs]hv]uhbjhz]r°(jO )r±}r²(haX!
hbj­hjhŒhljR hn}r³(UformatXhtmlhh‘hs]hr]hp]hq]hv]uhxMòhz]r´hƒX!
rµ…r¶}r·(haUhbj±ubaubh§)r¸}r¹(haXpr1\_edc\_sync0\_outhbj­hjhŒhlh«hn}rº(hp]hq]hr]hs]hv]uhxMöhz]r»hƒXpr1_edc_sync0_outr¼…r½}r¾(haXpr1\_edc\_sync0\_outhbj¸ubaubjO )r¿}rÀ(haX
hbj­hjhŒhljR hn}rÁ(UformatXhtmlhh‘hs]hr]hp]hq]hv]uhxMøhz]rÂhƒX
rÃ…rÄ}rÅ(haUhbj¿ubaubehljúubehljubehljRubehljSubaubh§)rÆ}rÇ(haXKExample: See below pictures (J21 is the connector along the top right edge)rÈhbjÝ hjhŒhlh«hn}rÉ(hp]hq]hr]hs]hv]uhxMýhyhhz]rÊhƒXKExample: See below pictures (J21 is the connector along the top right edge)rË…rÌ}rÍ(hajÈhbjÆubaubjº)rÎ}rÏ(haX-.. Image:: ../images/Am574x_whole_small2.png hbjÝ hjhŒhlj½hn}rÐ(UuriX'linux/../images/Am574x_whole_small2.pngrÑhs]hr]hp]hq]jÀ}rÒU*jÑshv]uhxMhyhhz]ubh§)rÓ}rÔ(haX3and this more J21 focused of the same picture aboverÕhbjÝ hjhŒhlh«hn}rÖ(hp]hq]hr]hs]hv]uhxMhyhhz]r×hƒX3and this more J21 focused of the same picture aboverØ…rÙ}rÚ(hajÕhbjÓubaubjº)rÛ}rÜ(haX$.. Image:: ../images/Am574x_j21.png hbjÝ hjhŒhlj½hn}rÝ(UuriXlinux/../images/Am574x_j21.pngrÞhs]hr]hp]hq]jÀ}rßU*jÞshv]uhxMhyhhz]ubeubhc)rà}rá(haUh˜Khbj7 hjhŒhlhmhn}râ(hp]rãXsoftwareräahq]hr]hs]råUsoftwareræahv]uhxMhyhhz]rç(h|)rè}ré(haXSoftwarerêhbjàhjhŒhlh€hn}rë(hp]hq]hr]hs]hv]uhxMhyhhz]rìhƒXSoftwarerí…rî}rï(hajêhbjèubaubh§)rð}rñ(haXxSee a complete sample log for AM571x BC log `here `__. As is shown in the log, right after the root login, the content of some shell scripts are displayed. Some of the scrits are for retrieving system information while others are for performing configurations. These sample scripts are for informational purpose only.hbjàhjhŒhlh«hn}rò(hp]hq]hr]hs]hv]uhxMhyhhz]ró(hƒX,See a complete sample log for AM571x BC log rô…rõ}rö(haX,See a complete sample log for AM571x BC log hbjðubj_)r÷}rø(haXD`here `__hn}rù(UnameXherejvX9http://processors.wiki.ti.com/images/2/20/Bc_20180112.pdfhs]hr]hp]hq]hv]uhbjðhz]rúhƒXhererû…rü}rý(haUhbj÷ubahljhubhƒX. As is shown in the log, right after the root login, the content of some shell scripts are displayed. Some of the scrits are for retrieving system information while others are for performing configurations. These sample scripts are for informational purpose only.rþ…rÿ}r(haX. As is shown in the log, right after the root login, the content of some shell scripts are displayed. Some of the scrits are for retrieving system information while others are for performing configurations. These sample scripts are for informational purpose only.hbjðubeubh§)r}r(haXNIf using the PRP firmware, make sure to boot up the kernel with the parametersrhbjàhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxMhyhhz]rhƒXNIf using the PRP firmware, make sure to boot up the kernel with the parametersr…r}r(hajhbjubaubh¹)r }r (haUhbjàhjhŒhlh¼hn}r (h¾X-hs]hr]hp]hq]hv]uhxMhyhhz]r (hÀ)r }r(haXti\_prueth.pruss1\_ethtype=2rhbj hjhŒhlhÃhn}r(hp]hq]hr]hs]hv]uhxNhyhhz]rh§)r}r(hajhbj hjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxMhz]rhƒXti_prueth.pruss1_ethtype=2r…r}r(haXti\_prueth.pruss1\_ethtype=2hbjubaubaubhÀ)r}r(haXti\_prueth.pruss2\_ethtype=2 hbj hjhŒhlhÃhn}r(hp]hq]hr]hs]hv]uhxNhyhhz]rh§)r}r(haXti\_prueth.pruss2\_ethtype=2hbjhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxMhz]r hƒXti_prueth.pruss2_ethtype=2r!…r"}r#(haXti\_prueth.pruss2\_ethtype=2hbjubaubaubeubh§)r$}r%(haXin the bootargs. The firmwarer&hbjàhjhŒhlh«hn}r'(hp]hq]hr]hs]hv]uhxMhyhhz]r(hƒXin the bootargs. The firmwarer)…r*}r+(haj&hbj$ubaubh¹)r,}r-(haUhbjàhjhŒhlh¼hn}r.(h¾X-hs]hr]hp]hq]hv]uhxMhyhhz]r/(hÀ)r0}r1(haXam57xx-pru0-pruprp-fw.elfr2hbj,hjhŒhlhÃhn}r3(hp]hq]hr]hs]hv]uhxNhyhhz]r4h§)r5}r6(haj2hbj0hjhŒhlh«hn}r7(hp]hq]hr]hs]hv]uhxMhz]r8hƒXam57xx-pru0-pruprp-fw.elfr9…r:}r;(haj2hbj5ubaubaubhÀ)r<}r=(haXam57xx-pru1-pruprp-fw.elf hbj,hjhŒhlhÃhn}r>(hp]hq]hr]hs]hv]uhxNhyhhz]r?h§)r@}rA(haXam57xx-pru1-pruprp-fw.elfrBhbj<hjhŒhlh«hn}rC(hp]hq]hr]hs]hv]uhxMhz]rDhƒXam57xx-pru1-pruprp-fw.elfrE…rF}rG(hajBhbj@ubaubaubeubh§)rH}rI(haXwill be loaded.rJhbjàhjhŒhlh«hn}rK(hp]hq]hr]hs]hv]uhxMhyhhz]rLhƒXwill be loaded.rM…rN}rO(hajJhbjHubaubh§)rP}rQ(haX=Make sure the following two lines appear in the start up log:rRhbjàhjhŒhlh«hn}rS(hp]hq]hr]hs]hv]uhxMhyhhz]rThƒX=Make sure the following two lines appear in the start up log:rU…rV}rW(hajRhbjPubaubj9)rX}rY(haX}prueth pruss2_eth: TI PRU ethernet (type 2) driver initialized prueth pruss1_eth: TI PRU ethernet (type 2) driver initializedhbjàhjhŒhlj<hn}rZ(hh‘hs]hr]hp]hq]hv]uhxM$hyhhz]r[hƒX}prueth pruss2_eth: TI PRU ethernet (type 2) driver initialized prueth pruss1_eth: TI PRU ethernet (type 2) driver initializedr\…r]}r^(haUhbjXubaubh§)r_}r`(haXIOnce the AM57xx IDK is boot into kernel prompt, use command, for example,rahbjàhjhŒhlh«hn}rb(hp]hq]hr]hs]hv]uhxM"hyhhz]rchƒXIOnce the AM57xx IDK is boot into kernel prompt, use command, for example,rd…re}rf(hajahbj_ubaubj9)rg}rh(haX8$ ls /sys/devices/platform/pruss1_eth/net eth4/ eth5/hbjàhjhŒhlj<hn}ri(hh‘hs]hr]hp]hq]hv]uhxM,hyhhz]rjhƒX8$ ls /sys/devices/platform/pruss1_eth/net eth4/ eth5/rk…rl}rm(haUhbjgubaubh§)rn}ro(haXQto see which interface is available on which ICSS. For GMAC port, use the commandrphbjàhjhŒhlh«hn}rq(hp]hq]hr]hs]hv]uhxM*hyhhz]rrhƒXQto see which interface is available on which ICSS. For GMAC port, use the commandrs…rt}ru(hajphbjnubaubj9)rv}rw(haXK$ ls /sys/devices/platform/44000000.ocp/48484000.ethernet/net eth0/ eth1/hbjàhjhŒhlj<hn}rx(hh‘hs]hr]hp]hq]hv]uhxM4hyhhz]ryhƒXK$ ls /sys/devices/platform/44000000.ocp/48484000.ethernet/net eth0/ eth1/rz…r{}r|(haUhbjvubaubh§)r}}r~(haX«If using PRP firmware configured to run in SAN mode, enable EMAC mode on each of the ICSS PRU interfaces (assuming eth2 and eth3 are on ICSS2, eth4 and eth5 are on ICSS1):rhbjàhjhŒhlh«hn}r€(hp]hq]hr]hs]hv]uhxM2hyhhz]rhƒX«If using PRP firmware configured to run in SAN mode, enable EMAC mode on each of the ICSS PRU interfaces (assuming eth2 and eth3 are on ICSS2, eth4 and eth5 are on ICSS1):r‚…rƒ}r„(hajhbj}ubaubj9)r…}r†(haX $ echo 1 > /sys/devices/platform/pruss2_eth/net/eth2/prp_emac_mode $ echo 1 > /sys/devices/platform/pruss2_eth/net/eth3/prp_emac_mode $ echo 1 > /sys/devices/platform/pruss1_eth/net/eth4/prp_emac_mode $ echo 1 > /sys/devices/platform/pruss1_eth/net/eth5/prp_emac_modehbjàhjhŒhlj<hn}r‡(hh‘hs]hr]hp]hq]hv]uhxM=hyhhz]rˆhƒX $ echo 1 > /sys/devices/platform/pruss2_eth/net/eth2/prp_emac_mode $ echo 1 > /sys/devices/platform/pruss2_eth/net/eth3/prp_emac_mode $ echo 1 > /sys/devices/platform/pruss1_eth/net/eth4/prp_emac_mode $ echo 1 > /sys/devices/platform/pruss1_eth/net/eth5/prp_emac_moder‰…rŠ}r‹(haUhbj…ubaubh§)rŒ}r(haXHNext, configure each BC interface with a proper IP address. For example,rŽhbjàhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxM=hyhhz]rhƒXHNext, configure each BC interface with a proper IP address. For example,r‘…r’}r“(hajŽhbjŒubaubj9)r”}r•(haX$ ifconfig eth1 192.168.1.1hbjàhjhŒhlj<hn}r–(hh‘hs]hr]hp]hq]hv]uhxMFhyhhz]r—hƒX$ ifconfig eth1 192.168.1.1r˜…r™}rš(haUhbj”ubaubj9)r›}rœ(haX$ ifconfig eth2 192.168.2.1hbjàhjhŒhlj<hn}r(hh‘hs]hr]hp]hq]hv]uhxMJhyhhz]ržhƒX$ ifconfig eth2 192.168.2.1rŸ…r }r¡(haUhbj›ubaubj9)r¢}r£(haX$ ifconfig eth4 192.168.4.1hbjàhjhŒhlj<hn}r¤(hh‘hs]hr]hp]hq]hv]uhxMNhyhhz]r¥hƒX$ ifconfig eth4 192.168.4.1r¦…r§}r¨(haUhbj¢ubaubh§)r©}rª(haXwIf using PRP firmware configured to run in DAN mode, configure each BC interface with a proper IP address. For example,r«hbjàhjhŒhlh«hn}r¬(hp]hq]hr]hs]hv]uhxMKhyhhz]r­hƒXwIf using PRP firmware configured to run in DAN mode, configure each BC interface with a proper IP address. For example,r®…r¯}r°(haj«hbj©ubaubj9)r±}r²(haX$ ifconfig eth1 192.168.1.1hbjàhjhŒhlj<hn}r³(hh‘hs]hr]hp]hq]hv]uhxMUhyhhz]r´hƒX$ ifconfig eth1 192.168.1.1rµ…r¶}r·(haUhbj±ubaubj9)r¸}r¹(haX1$ ifconfig eth2 hw ether 70:FF:76:1C:0E:8C $ ifconfig eth3 hw ether 70:FF:76:1C:0E:8C $ ethtool -K eth2 prp-rx-offload on $ ethtool -K eth3 prp-rx-offload on $ ifconfig eth2 up $ ifconfig eth3 up $ ip link add name prp0 type prp slave1 eth2 slave2 eth3 supervision 45 version 1 $ ifconfig prp0 192.168.2.1hbjàhjhŒhlj<hn}rº(hh‘hs]hr]hp]hq]hv]uhxMYhyhhz]r»hƒX1$ ifconfig eth2 hw ether 70:FF:76:1C:0E:8C $ ifconfig eth3 hw ether 70:FF:76:1C:0E:8C $ ethtool -K eth2 prp-rx-offload on $ ethtool -K eth3 prp-rx-offload on $ ifconfig eth2 up $ ifconfig eth3 up $ ip link add name prp0 type prp slave1 eth2 slave2 eth3 supervision 45 version 1 $ ifconfig prp0 192.168.2.1r¼…r½}r¾(haUhbj¸ubaubj9)r¿}rÀ(haX1$ ifconfig eth4 hw ether 70:FF:76:1C:0E:90 $ ifconfig eth5 hw ether 70:FF:76:1C:0E:90 $ ethtool -K eth4 prp-rx-offload on $ ethtool -K eth5 prp-rx-offload on $ ifconfig eth4 up $ ifconfig eth5 up $ ip link add name prp1 type prp slave1 eth4 slave2 eth5 supervision 45 version 1 $ ifconfig prp1 192.168.4.1hbjàhjhŒhlj<hn}rÁ(hh‘hs]hr]hp]hq]hv]uhxMdhyhhz]rÂhƒX1$ ifconfig eth4 hw ether 70:FF:76:1C:0E:90 $ ifconfig eth5 hw ether 70:FF:76:1C:0E:90 $ ethtool -K eth4 prp-rx-offload on $ ethtool -K eth5 prp-rx-offload on $ ifconfig eth4 up $ ifconfig eth5 up $ ip link add name prp1 type prp slave1 eth4 slave2 eth5 supervision 45 version 1 $ ifconfig prp1 192.168.4.1rÃ…rÄ}rÅ(haUhbj¿ubaubh§)rÆ}rÇ(haXNIf using the HSR firmware, make sure to boot up the kernel with the parametersrÈhbjàhjhŒhlh«hn}rÉ(hp]hq]hr]hs]hv]uhxMihyhhz]rÊhƒXNIf using the HSR firmware, make sure to boot up the kernel with the parametersrË…rÌ}rÍ(hajÈhbjÆubaubh¹)rÎ}rÏ(haUhbjàhjhŒhlh¼hn}rÐ(h¾X-hs]hr]hp]hq]hv]uhxMkhyhhz]rÑ(hÀ)rÒ}rÓ(haXti\_prueth.pruss1\_ethtype=1rÔhbjÎhjhŒhlhÃhn}rÕ(hp]hq]hr]hs]hv]uhxNhyhhz]rÖh§)r×}rØ(hajÔhbjÒhjhŒhlh«hn}rÙ(hp]hq]hr]hs]hv]uhxMkhz]rÚhƒXti_prueth.pruss1_ethtype=1rÛ…rÜ}rÝ(haXti\_prueth.pruss1\_ethtype=1hbj×ubaubaubhÀ)rÞ}rß(haXti\_prueth.pruss2\_ethtype=1 hbjÎhjhŒhlhÃhn}rà(hp]hq]hr]hs]hv]uhxNhyhhz]ráh§)râ}rã(haXti\_prueth.pruss2\_ethtype=1hbjÞhjhŒhlh«hn}rä(hp]hq]hr]hs]hv]uhxMlhz]råhƒXti_prueth.pruss2_ethtype=1ræ…rç}rè(haXti\_prueth.pruss2\_ethtype=1hbjâubaubaubeubh§)ré}rê(haXin the bootargs. The firmwarerëhbjàhjhŒhlh«hn}rì(hp]hq]hr]hs]hv]uhxMnhyhhz]ríhƒXin the bootargs. The firmwarerî…rï}rð(hajëhbjéubaubh¹)rñ}rò(haUhbjàhjhŒhlh¼hn}ró(h¾X-hs]hr]hp]hq]hv]uhxMphyhhz]rô(hÀ)rõ}rö(haXam57xx-pru0-pruhsr-fw.elfr÷hbjñhjhŒhlhÃhn}rø(hp]hq]hr]hs]hv]uhxNhyhhz]rùh§)rú}rû(haj÷hbjõhjhŒhlh«hn}rü(hp]hq]hr]hs]hv]uhxMphz]rýhƒXam57xx-pru0-pruhsr-fw.elfrþ…rÿ}r(haj÷hbjúubaubaubhÀ)r}r(haXam57xx-pru1-pruhsr-fw.elf hbjñhjhŒhlhÃhn}r(hp]hq]hr]hs]hv]uhxNhyhhz]rh§)r}r(haXam57xx-pru1-pruhsr-fw.elfrhbjhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxMqhz]r hƒXam57xx-pru1-pruhsr-fw.elfr …r }r (hajhbjubaubaubeubh§)r }r(haXwill be loaded.rhbjàhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxMshyhhz]rhƒXwill be loaded.r…r}r(hajhbj ubaubh§)r}r(haX=Make sure the following two lines appear in the start up log:rhbjàhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxMuhyhhz]rhƒX=Make sure the following two lines appear in the start up log:r…r}r(hajhbjubaubj9)r}r(haX}prueth pruss2_eth: TI PRU ethernet (type 1) driver initialized prueth pruss1_eth: TI PRU ethernet (type 1) driver initializedhbjàhjhŒhlj<hn}r(hh‘hs]hr]hp]hq]hv]uhxM~hyhhz]r hƒX}prueth pruss2_eth: TI PRU ethernet (type 1) driver initialized prueth pruss1_eth: TI PRU ethernet (type 1) driver initializedr!…r"}r#(haUhbjubaubh§)r$}r%(haXIOnce the AM57xx IDK is boot into kernel prompt, use command, for example,r&hbjàhjhŒhlh«hn}r'(hp]hq]hr]hs]hv]uhxM|hyhhz]r(hƒXIOnce the AM57xx IDK is boot into kernel prompt, use command, for example,r)…r*}r+(haj&hbj$ubaubj9)r,}r-(haX8$ ls /sys/devices/platform/pruss1_eth/net eth4/ eth5/hbjàhjhŒhlj<hn}r.(hh‘hs]hr]hp]hq]hv]uhxM†hyhhz]r/hƒX8$ ls /sys/devices/platform/pruss1_eth/net eth4/ eth5/r0…r1}r2(haUhbj,ubaubh§)r3}r4(haXQto see which interface is available on which ICSS. For GMAC port, use the commandr5hbjàhjhŒhlh«hn}r6(hp]hq]hr]hs]hv]uhxM„hyhhz]r7hƒXQto see which interface is available on which ICSS. For GMAC port, use the commandr8…r9}r:(haj5hbj3ubaubj9)r;}r<(haXK$ ls /sys/devices/platform/44000000.ocp/48484000.ethernet/net eth0/ eth1/hbjàhjhŒhlj<hn}r=(hh‘hs]hr]hp]hq]hv]uhxMŽhyhhz]r>hƒXK$ ls /sys/devices/platform/44000000.ocp/48484000.ethernet/net eth0/ eth1/r?…r@}rA(haUhbj;ubaubh§)rB}rC(haXHNext, configure each BC interface with a proper IP address. For example,rDhbjàhjhŒhlh«hn}rE(hp]hq]hr]hs]hv]uhxMhyhhz]rFhƒXHNext, configure each BC interface with a proper IP address. For example,rG…rH}rI(hajDhbjBubaubj9)rJ}rK(haX$ ifconfig eth1 192.168.1.1hbjàhjhŒhlj<hn}rL(hh‘hs]hr]hp]hq]hv]uhxM–hyhhz]rMhƒX$ ifconfig eth1 192.168.1.1rN…rO}rP(haUhbjJubaubj9)rQ}rR(haX1$ ifconfig eth2 hw ether 70:FF:76:1C:0E:8C $ ifconfig eth3 hw ether 70:FF:76:1C:0E:8C $ ethtool -K eth2 hsr-rx-offload on $ ethtool -K eth3 hsr-rx-offload on $ ifconfig eth2 up $ ifconfig eth3 up $ ip link add name hsr0 type hsr slave1 eth2 slave2 eth3 supervision 45 version 1 $ ifconfig hsr0 192.168.2.1hbjàhjhŒhlj<hn}rS(hh‘hs]hr]hp]hq]hv]uhxMšhyhhz]rThƒX1$ ifconfig eth2 hw ether 70:FF:76:1C:0E:8C $ ifconfig eth3 hw ether 70:FF:76:1C:0E:8C $ ethtool -K eth2 hsr-rx-offload on $ ethtool -K eth3 hsr-rx-offload on $ ifconfig eth2 up $ ifconfig eth3 up $ ip link add name hsr0 type hsr slave1 eth2 slave2 eth3 supervision 45 version 1 $ ifconfig hsr0 192.168.2.1rU…rV}rW(haUhbjQubaubj9)rX}rY(haX1$ ifconfig eth4 hw ether 70:FF:76:1C:0E:90 $ ifconfig eth5 hw ether 70:FF:76:1C:0E:90 $ ethtool -K eth4 hsr-rx-offload on $ ethtool -K eth5 hsr-rx-offload on $ ifconfig eth4 up $ ifconfig eth5 up $ ip link add name hsr1 type hsr slave1 eth4 slave2 eth5 supervision 45 version 1 $ ifconfig hsr1 192.168.4.1hbjàhjhŒhlj<hn}rZ(hh‘hs]hr]hp]hq]hv]uhxM¥hyhhz]r[hƒX1$ ifconfig eth4 hw ether 70:FF:76:1C:0E:90 $ ifconfig eth5 hw ether 70:FF:76:1C:0E:90 $ ethtool -K eth4 hsr-rx-offload on $ ethtool -K eth5 hsr-rx-offload on $ ifconfig eth4 up $ ifconfig eth5 up $ ip link add name hsr1 type hsr slave1 eth4 slave2 eth5 supervision 45 version 1 $ ifconfig hsr1 192.168.4.1r\…r]}r^(haUhbjXubaubj)r_}r`(haXStarting the BC applicationsrahbjàhjhŒhlj¡hn}rb(hs]rcUstarting-the-bc-applicationsrdahr]hp]hq]hv]rehauhxNhyhhz]rfhƒXStarting the BC applicationsrg…rh}ri(hajahbj_ubaubh§)rj}rk(haXiRefer to the sample linuxptp BC configuration files bc.cfg, bc_hsr.cfg and bc_prp.cfg as described below:rlhbjàhjhŒhlh«hn}rm(hp]hq]hr]hs]hv]uhxM­hyhhz]rnhƒXiRefer to the sample linuxptp BC configuration files bc.cfg, bc_hsr.cfg and bc_prp.cfg as described below:ro…rp}rq(hajlhbjjubaubh§)rr}rs(haX+bc.cfg: BC with GMAC and four ICSS ports ::hbjàhjhŒhlh«hn}rt(hp]hq]hr]hs]hv]uhxM°hyhhz]ruhƒX(bc.cfg: BC with GMAC and four ICSS portsrv…rw}rx(haX(bc.cfg: BC with GMAC and four ICSS portshbjrubaubj9)ry}rz(haX4[global] sanity_freq_limit 0 step_threshold 0.000002 tx_timestamp_timeout 10 logMinPdelayReqInterval 0 logSyncInterval 0 logAnnounceInterval 0 announceReceiptTimeout 3 syncReceiptTimeout 2 twoStepFlag 1 summary_interval 0 doubly_attached_clock 2 [eth1] boundary_clock_jbod 1 egressLatency 146 ingressLatency 346 delay_mechanism P2P network_transport L2 [eth2] boundary_clock_jbod 1 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0 [eth3] boundary_clock_jbod 1 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0 [eth4] boundary_clock_jbod 1 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0 [eth5] boundary_clock_jbod 1 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0hbjàhjhŒhlj<hn}r{(hh‘hs]hr]hp]hq]hv]uhxM¸hyhhz]r|hƒX4[global] sanity_freq_limit 0 step_threshold 0.000002 tx_timestamp_timeout 10 logMinPdelayReqInterval 0 logSyncInterval 0 logAnnounceInterval 0 announceReceiptTimeout 3 syncReceiptTimeout 2 twoStepFlag 1 summary_interval 0 doubly_attached_clock 2 [eth1] boundary_clock_jbod 1 egressLatency 146 ingressLatency 346 delay_mechanism P2P network_transport L2 [eth2] boundary_clock_jbod 1 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0 [eth3] boundary_clock_jbod 1 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0 [eth4] boundary_clock_jbod 1 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0 [eth5] boundary_clock_jbod 1 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0r}…r~}r(haUhbjyubaubh§)r€}r(haX.bc_prp.cfg: BC with GMAC and two PRP ports: ::hbjàhjhŒhlh«hn}r‚(hp]hq]hr]hs]hv]uhxMèhyhhz]rƒhƒX+bc_prp.cfg: BC with GMAC and two PRP ports:r„…r…}r†(haX+bc_prp.cfg: BC with GMAC and two PRP ports:hbj€ubaubj9)r‡}rˆ(haXÆ[global] sanity_freq_limit 0 step_threshold 0.000002 tx_timestamp_timeout 10 logMinPdelayReqInterval 0 logSyncInterval 0 logAnnounceInterval 0 announceReceiptTimeout 3 syncReceiptTimeout 2 twoStepFlag 1 summary_interval 0 doubly_attached_clock 2 [eth1] boundary_clock_jbod 1 egressLatency 146 ingressLatency 346 delay_mechanism P2P network_transport L2 [prp0] boundary_clock_jbod 1 redundancy 2 delay_mechanism P2P network_transport L2 [eth2] boundary_clock_jbod 1 redundancy 2 redundancy_master_interface prp0 redundancy_slave_number 1 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0 [eth3] boundary_clock_jbod 1 redundancy 2 redundancy_master_interface prp0 redundancy_slave_number 2 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0 [prp1] boundary_clock_jbod 1 redundancy 2 delay_mechanism P2P network_transport L2 [eth4] boundary_clock_jbod 1 redundancy 2 redundancy_master_interface prp1 redundancy_slave_number 1 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0 [eth5] boundary_clock_jbod 1 redundancy 2 redundancy_master_interface prp1 redundancy_slave_number 2 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0hbjàhjhŒhlj<hn}r‰(hh‘hs]hr]hp]hq]hv]uhxMðhyhhz]rŠhƒXÆ[global] sanity_freq_limit 0 step_threshold 0.000002 tx_timestamp_timeout 10 logMinPdelayReqInterval 0 logSyncInterval 0 logAnnounceInterval 0 announceReceiptTimeout 3 syncReceiptTimeout 2 twoStepFlag 1 summary_interval 0 doubly_attached_clock 2 [eth1] boundary_clock_jbod 1 egressLatency 146 ingressLatency 346 delay_mechanism P2P network_transport L2 [prp0] boundary_clock_jbod 1 redundancy 2 delay_mechanism P2P network_transport L2 [eth2] boundary_clock_jbod 1 redundancy 2 redundancy_master_interface prp0 redundancy_slave_number 1 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0 [eth3] boundary_clock_jbod 1 redundancy 2 redundancy_master_interface prp0 redundancy_slave_number 2 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0 [prp1] boundary_clock_jbod 1 redundancy 2 delay_mechanism P2P network_transport L2 [eth4] boundary_clock_jbod 1 redundancy 2 redundancy_master_interface prp1 redundancy_slave_number 1 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0 [eth5] boundary_clock_jbod 1 redundancy 2 redundancy_master_interface prp1 redundancy_slave_number 2 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0r‹…rŒ}r(haUhbj‡ubaubh§)rŽ}r(haX.bc_hsr.cfg: BC with GMAC and two HSR ports: ::hbjàhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxM=hyhhz]r‘hƒX+bc_hsr.cfg: BC with GMAC and two HSR ports:r’…r“}r”(haX+bc_hsr.cfg: BC with GMAC and two HSR ports:hbjŽubaubj9)r•}r–(haXÆ[global] sanity_freq_limit 0 step_threshold 0.000002 tx_timestamp_timeout 10 logMinPdelayReqInterval 0 logSyncInterval 0 logAnnounceInterval 0 announceReceiptTimeout 3 syncReceiptTimeout 2 twoStepFlag 1 summary_interval 0 doubly_attached_clock 2 [eth1] boundary_clock_jbod 1 egressLatency 146 ingressLatency 346 delay_mechanism P2P network_transport L2 [hsr0] boundary_clock_jbod 1 redundancy 1 delay_mechanism P2P network_transport L2 [eth2] boundary_clock_jbod 1 redundancy 1 redundancy_master_interface hsr0 redundancy_slave_number 1 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0 [eth3] boundary_clock_jbod 1 redundancy 1 redundancy_master_interface hsr0 redundancy_slave_number 2 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0 [hsr1] boundary_clock_jbod 1 redundancy 1 delay_mechanism P2P network_transport L2 [eth4] boundary_clock_jbod 1 redundancy 1 redundancy_master_interface hsr1 redundancy_slave_number 1 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0 [eth5] boundary_clock_jbod 1 redundancy 1 redundancy_master_interface hsr1 redundancy_slave_number 2 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0hbjàhjhŒhlj<hn}r—(hh‘hs]hr]hp]hq]hv]uhxMEhyhhz]r˜hƒXÆ[global] sanity_freq_limit 0 step_threshold 0.000002 tx_timestamp_timeout 10 logMinPdelayReqInterval 0 logSyncInterval 0 logAnnounceInterval 0 announceReceiptTimeout 3 syncReceiptTimeout 2 twoStepFlag 1 summary_interval 0 doubly_attached_clock 2 [eth1] boundary_clock_jbod 1 egressLatency 146 ingressLatency 346 delay_mechanism P2P network_transport L2 [hsr0] boundary_clock_jbod 1 redundancy 1 delay_mechanism P2P network_transport L2 [eth2] boundary_clock_jbod 1 redundancy 1 redundancy_master_interface hsr0 redundancy_slave_number 1 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0 [eth3] boundary_clock_jbod 1 redundancy 1 redundancy_master_interface hsr0 redundancy_slave_number 2 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0 [hsr1] boundary_clock_jbod 1 redundancy 1 delay_mechanism P2P network_transport L2 [eth4] boundary_clock_jbod 1 redundancy 1 redundancy_master_interface hsr1 redundancy_slave_number 1 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0 [eth5] boundary_clock_jbod 1 redundancy 1 redundancy_master_interface hsr1 redundancy_slave_number 2 delay_mechanism P2P network_transport L2 egressLatency 726 ingressLatency 186 fault_reset_interval 0r™…rš}r›(haUhbj•ubaubh§)rœ}r(haXEStart ptp4l in the background and with display log to stdout enabled:ržhbjàhjhŒhlh«hn}rŸ(hp]hq]hr]hs]hv]uhxM“hyhhz]r hƒXEStart ptp4l in the background and with display log to stdout enabled:r¡…r¢}r£(hajžhbjœubaubj9)r¤}r¥(haX$ ptp4l -f bc.cfg -m &hbjàhjhŒhlj<hn}r¦(hh‘hs]hr]hp]hq]hv]uhxMœhyhhz]r§hƒX$ ptp4l -f bc.cfg -m &r¨…r©}rª(haUhbj¤ubaubh§)r«}r¬(haX_Wait to see the PTP slave port clock is sync and stabilized, for example, seeing similar lines:r­hbjàhjhŒhlh«hn}r®(hp]hq]hr]hs]hv]uhxM™hyhhz]r¯hƒX_Wait to see the PTP slave port clock is sync and stabilized, for example, seeing similar lines:r°…r±}r²(haj­hbj«ubaubj9)r³}r´(haXptp4l[304.713]: rms 7 max 12 ( -12, 1) freq -8253 +/- 4 delay 7 +/- 1 ptp4l[305.714]: rms 2 max 4 ( -4, 2) freq -8248 +/- 3 delay 8 +/- 0 ptp4l[306.714]: rms 2 max 3 ( -3, 3) freq -8248 +/- 3 delay 8 +/- 0hbjàhjhŒhlj<hn}rµ(hh‘hs]hr]hp]hq]hv]uhxM£hyhhz]r¶hƒXptp4l[304.713]: rms 7 max 12 ( -12, 1) freq -8253 +/- 4 delay 7 +/- 1 ptp4l[305.714]: rms 2 max 4 ( -4, 2) freq -8248 +/- 3 delay 8 +/- 0 ptp4l[306.714]: rms 2 max 3 ( -3, 3) freq -8248 +/- 3 delay 8 +/- 0r·…r¸}r¹(haUhbj³ubaubh§)rº}r»(haXJthen start phc2sys to perform the BC internal clock sync in the backgroundr¼hbjàhjhŒhlh«hn}r½(hp]hq]hr]hs]hv]uhxM¢hyhhz]r¾hƒXJthen start phc2sys to perform the BC internal clock sync in the backgroundr¿…rÀ}rÁ(haj¼hbjºubaubj9)rÂ}rÃ(haX.$ phc2sys -a -X -g eth1 -S 0.000002 -L 0 -m &hbjàhjhŒhlj<hn}rÄ(hh‘hs]hr]hp]hq]hv]uhxM¬hyhhz]rÅhƒX.$ phc2sys -a -X -g eth1 -S 0.000002 -L 0 -m &rÆ…rÇ}rÈ(haUhbjÂubaubh§)rÉ}rÊ(haX6where the new options added in this implementation arerËhbjàhjhŒhlh«hn}rÌ(hp]hq]hr]hs]hv]uhxM©hyhhz]rÍhƒX6where the new options added in this implementation arerÎ…rÏ}rÐ(hajËhbjÉubaubj9)rÑ}rÒ(haX½-X: use extts (pps) to perform BC internal clock synchronization. -g: specify which interface is the GMAC port interface -S: specify step threshold -L: specify sanity frequency limit in ppbhbjàhjhŒhlj<hn}rÓ(hh‘hs]hr]hp]hq]hv]uhxM²hyhhz]rÔhƒX½-X: use extts (pps) to perform BC internal clock synchronization. -g: specify which interface is the GMAC port interface -S: specify step threshold -L: specify sanity frequency limit in ppbrÕ…rÖ}r×(haUhbjÑubaubh§)rØ}rÙ(haX…Lines similar to the following should be displayed after a few seconds (mixed with the "ptp4l[304.713]: rms ..." lines from ptp4l) :rÚhbjàhjhŒhlh«hn}rÛ(hp]hq]hr]hs]hv]uhxM²hyhhz]rÜhƒX…Lines similar to the following should be displayed after a few seconds (mixed with the "ptp4l[304.713]: rms ..." lines from ptp4l) :rÝ…rÞ}rß(hajÚhbjØubaubj9)rà}rá(haXwphc2sys[373.480]: eth4 phc offset -14 s2 freq -8311 phc2sys[373.500]: eth1 phc offset -18 s2 freq -8315hbjàhjhŒhlj<hn}râ(hh‘hs]hr]hp]hq]hv]uhxM¼hyhhz]rãhƒXwphc2sys[373.480]: eth4 phc offset -14 s2 freq -8311 phc2sys[373.500]: eth1 phc offset -18 s2 freq -8315rä…rå}ræ(haUhbjàubaubh§)rç}rè(haXÕStart an AM57xx OC in slave only mode connected to a BC's master port, for example, the AM572x OC-3 in the `sample setup <#sample-bc-setups>`__. To make sure the OC is started in slave only mode, the ptp4l commandhbjàhjhŒhlh«hn}ré(hp]hq]hr]hs]hv]uhxMºhyhhz]rê(hƒXkStart an AM57xx OC in slave only mode connected to a BC's master port, for example, the AM572x OC-3 in the rë…rì}rí(haXkStart an AM57xx OC in slave only mode connected to a BC's master port, for example, the AM572x OC-3 in the hbjçubj_)rî}rï(haX$`sample setup <#sample-bc-setups>`__hn}rð(UnameX sample setupjvX#sample-bc-setupshs]hr]hp]hq]hv]uhbjçhz]rñhƒX sample setuprò…ró}rô(haUhbjîubahljhubhƒXF. To make sure the OC is started in slave only mode, the ptp4l commandrõ…rö}r÷(haXF. To make sure the OC is started in slave only mode, the ptp4l commandhbjçubeubj9)rø}rù(haX$ ptp4l -2 -P -f oc.cfg -s -mhbjàhjhŒhlj<hn}rú(hh‘hs]hr]hp]hq]hv]uhxMÆhyhhz]rûhƒX$ ptp4l -2 -P -f oc.cfg -s -mrü…rý}rþ(haUhbjøubaubh§)rÿ}r(haXbcan be used. The slave OC's PPS can then be measured against the reference PTP master clock's PPS.rhbjàhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxMÃhyhhz]rhƒXbcan be used. The slave OC's PPS can then be measured against the reference PTP master clock's PPS.r…r}r(hajhbjÿubaubj)r}r(haX2Forcing BC Port State Change (for Testing Purpose)r hbjàhjhŒhlj¡hn}r (hs]r U0forcing-bc-port-state-change-for-testing-purposer ahr]hp]hq]hv]r hauhxNhyhhz]rhƒX2Forcing BC Port State Change (for Testing Purpose)r…r}r(haj hbjubaubh§)r}r(haXqTo force a port state change on the BC ports for testing purpose, one can bring down the current reference PTP master clock and bring up another reference PTP master clock connected to, for example, the BC's eth1 interface in the `sample setup <#sample-bc-setups>`__. Or simply rearrange the cable connections in the `sample setup <#sample-bc-setups>`__ as shown below.hbjàhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxMÉhyhhz]r(hƒXæTo force a port state change on the BC ports for testing purpose, one can bring down the current reference PTP master clock and bring up another reference PTP master clock connected to, for example, the BC's eth1 interface in the r…r}r(haXæTo force a port state change on the BC ports for testing purpose, one can bring down the current reference PTP master clock and bring up another reference PTP master clock connected to, for example, the BC's eth1 interface in the hbjubj_)r}r(haX$`sample setup <#sample-bc-setups>`__hn}r(UnameX sample setupjvX#sample-bc-setupshs]hr]hp]hq]hv]uhbjhz]rhƒX sample setupr…r}r(haUhbjubahljhubhƒX3. Or simply rearrange the cable connections in the r …r!}r"(haX3. Or simply rearrange the cable connections in the hbjubj_)r#}r$(haX$`sample setup <#sample-bc-setups>`__hn}r%(UnameX sample setupjvX#sample-bc-setupshs]hr]hp]hq]hv]uhbjhz]r&hƒX sample setupr'…r(}r)(haUhbj#ubahljhubhƒX as shown below.r*…r+}r,(haX as shown below.hbjubeubjº)r-}r.(haX&.. Image:: ../images/Bc_reconnect.jpg hbjàhjhŒhlj½hn}r/(UuriX linux/../images/Bc_reconnect.jpgr0hs]hr]hp]hq]jÀ}r1U*j0shv]uhxMÑhyhhz]ubh§)r2}r3(haXSee `here `__ for a sample log when the BC's cables are reconnected. The sample log starts right before when the cable is disconnected from eth2 on BC's ICSS2 in the `sample setup <#sample-bc-setups>`__.hbjàhjhŒhlh«hn}r4(hp]hq]hr]hs]hv]uhxMÒhyhhz]r5(hƒXSee r6…r7}r8(haXSee hbj2ubj_)r9}r:(haXN`here `__hn}r;(UnameXherejvXChttp://processors.wiki.ti.com/images/8/83/Bc_reconnect_20180112.pdfhs]hr]hp]hq]hv]uhbj2hz]r<hƒXherer=…r>}r?(haUhbj9ubahljhubhƒX™ for a sample log when the BC's cables are reconnected. The sample log starts right before when the cable is disconnected from eth2 on BC's ICSS2 in the r@…rA}rB(haX™ for a sample log when the BC's cables are reconnected. The sample log starts right before when the cable is disconnected from eth2 on BC's ICSS2 in the hbj2ubj_)rC}rD(haX$`sample setup <#sample-bc-setups>`__hn}rE(UnameX sample setupjvX#sample-bc-setupshs]hr]hp]hq]hv]uhbj2hz]rFhƒX sample setuprG…rH}rI(haUhbjCubahljhubhƒX.…rJ}rK(haX.hbj2ubeubeubeubhc)rL}rM(haUh˜Khbj" hjhŒhlhmhn}rN(hp]rOjï ahq]hr]hs]rPUid6rQahv]uhxMÙhyhhz]rR(h|)rS}rT(haX Test ResultsrUhbjLhjhŒhlh€hn}rV(hp]hq]hr]hs]hv]uhxMÙhyhhz]rWhƒX Test ResultsrX…rY}rZ(hajUhbjSubaubj)r[}r\(haXBC (GMAC ICSS2)r]hbjLhjhŒhlj¡hn}r^(hs]r_U bc-gmac-icss2r`ahr]hp]hq]hv]rahFauhxNhyhhz]rbhƒXBC (GMAC ICSS2)rc…rd}re(haj]hbj[ubaubju)rf}rg(haUhbjLhjhŒhljxhn}rh(hp]hq]hr]hs]hv]uhxMÞhyhhz]rij{)rj}rk(haX?Oregano <==> BC-GMAC-eth1 <==> BC-ICSS2-eth2 <==> OC-ICSS2-eth2rlj~KhbjfhjhŒhlhxhn}rm(hp]hq]hr]hs]hv]uhxMÞhyhhz]rnhƒX?Oregano <==> BC-GMAC-eth1 <==> BC-ICSS2-eth2 <==> OC-ICSS2-eth2ro…rp}rq(hajlhbjjubaubaubjº)rr}rs(haX... Image:: ../images/Pic_ptp_bc_eth1_eth2.png hbjLhjhŒhlj½hn}rt(UuriX(linux/../images/Pic_ptp_bc_eth1_eth2.pngruhs]hr]hp]hq]jÀ}rvU*jushv]uhxMáhyhhz]ubju)rw}rx(haUhbjLhjhŒhljxhn}ry(hp]hq]hr]hs]hv]uhxMâhyhhz]rzj{)r{}r|(haUj~KhbjwhjhŒhlhxhn}r}(hp]hq]hr]hs]hv]uhxKhyhhz]ubaubj)r~}r(haXBC (GMAC ICSS1)r€hbjLhjhŒhlj¡hn}r(hs]r‚U bc-gmac-icss1rƒahr]hp]hq]hv]r„h!auhxNhyhhz]r…hƒXBC (GMAC ICSS1)r†…r‡}rˆ(haj€hbj~ubaubju)r‰}rŠ(haUhbjLhjhŒhljxhn}r‹(hp]hq]hr]hs]hv]uhxMçhyhhz]rŒj{)r}rŽ(haX?Oregano <==> BC-GMAC-eth1 <==> BC-ICSS1-eth4 <==> OC-ICSS2-eth2rj~Khbj‰hjhŒhlhxhn}r(hp]hq]hr]hs]hv]uhxMçhyhhz]r‘hƒX?Oregano <==> BC-GMAC-eth1 <==> BC-ICSS1-eth4 <==> OC-ICSS2-eth2r’…r“}r”(hajhbjubaubaubjº)r•}r–(haX... Image:: ../images/Pic_ptp_bc_eth1_eth4.png hbjLhjhŒhlj½hn}r—(UuriX(linux/../images/Pic_ptp_bc_eth1_eth4.pngr˜hs]hr]hp]hq]jÀ}r™U*j˜shv]uhxMêhyhhz]ubj)rš}r›(haXBC (ICSS2 GMAC)rœhbjLhjhŒhlj¡hn}r(hs]ržU bc-icss2-gmacrŸahr]hp]hq]hv]r h)auhxNhyhhz]r¡hƒXBC (ICSS2 GMAC)r¢…r£}r¤(hajœhbjšubaubju)r¥}r¦(haUhbjLhjhŒhljxhn}r§(hp]hq]hr]hs]hv]uhxMîhyhhz]r¨j{)r©}rª(haX>Oregano <==> BC-ICSS2-eth2 <==> BC-GMAC-eth1 <==> OC-GMAC-eth1r«j~Khbj¥hjhŒhlhxhn}r¬(hp]hq]hr]hs]hv]uhxMîhyhhz]r­hƒX>Oregano <==> BC-ICSS2-eth2 <==> BC-GMAC-eth1 <==> OC-GMAC-eth1r®…r¯}r°(haj«hbj©ubaubaubjº)r±}r²(haX... Image:: ../images/Pic_ptp_bc_eth2_eth1.png hbjLhjhŒhlj½hn}r³(UuriX(linux/../images/Pic_ptp_bc_eth2_eth1.pngr´hs]hr]hp]hq]jÀ}rµU*j´shv]uhxMñhyhhz]ubj)r¶}r·(haXBC (ICSS1 GMAC)r¸hbjLhjhŒhlj¡hn}r¹(hs]rºU bc-icss1-gmacr»ahr]hp]hq]hv]r¼h%auhxNhyhhz]r½hƒXBC (ICSS1 GMAC)r¾…r¿}rÀ(haj¸hbj¶ubaubju)rÁ}rÂ(haUhbjLhjhŒhljxhn}rÃ(hp]hq]hr]hs]hv]uhxMõhyhhz]rÄj{)rÅ}rÆ(haX>Oregano <==> BC-ICSS1-eth4 <==> BC-GMAC-eth1 <==> OC-GMAC-eth1rÇj~KhbjÁhjhŒhlhxhn}rÈ(hp]hq]hr]hs]hv]uhxMõhyhhz]rÉhƒX>Oregano <==> BC-ICSS1-eth4 <==> BC-GMAC-eth1 <==> OC-GMAC-eth1rÊ…rË}rÌ(hajÇhbjÅubaubaubjº)rÍ}rÎ(haX... Image:: ../images/Pic_ptp_bc_eth4_eth1.png hbjLhjhŒhlj½hn}rÏ(UuriX(linux/../images/Pic_ptp_bc_eth4_eth1.pngrÐhs]hr]hp]hq]jÀ}rÑU*jÐshv]uhxMøhyhhz]ubj)rÒ}rÓ(haXBC (ICSS2 ICSS1)rÔhbjLhjhŒhlj¡hn}rÕ(hs]rÖUbc-icss2-icss1r×ahr]hp]hq]hv]rØh-auhxNhyhhz]rÙhƒXBC (ICSS2 ICSS1)rÚ…rÛ}rÜ(hajÔhbjÒubaubju)rÝ}rÞ(haUhbjLhjhŒhljxhn}rß(hp]hq]hr]hs]hv]uhxMühyhhz]ràj{)rá}râ(haX@Oregano <==> BC-ICSS2-eth2 <==> BC-ICSS1-eth4 <==> OC-ICSS2-eth2rãj~KhbjÝhjhŒhlhxhn}rä(hp]hq]hr]hs]hv]uhxMühyhhz]råhƒX@Oregano <==> BC-ICSS2-eth2 <==> BC-ICSS1-eth4 <==> OC-ICSS2-eth2ræ…rç}rè(hajãhbjáubaubaubjº)ré}rê(haX... Image:: ../images/Pic_ptp_bc_eth2_eth4.png hbjLhjhŒhlj½hn}rë(UuriX(linux/../images/Pic_ptp_bc_eth2_eth4.pngrìhs]hr]hp]hq]jÀ}ríU*jìshv]uhxMÿhyhhz]ubj)rî}rï(haXBC (ICSS1 ICSS2)rðhbjLhjhŒhlj¡hn}rñ(hs]ròUbc-icss1-icss2róahr]hp]hq]hv]rôhOauhxNhyhhz]rõhƒXBC (ICSS1 ICSS2)rö…r÷}rø(hajðhbjîubaubju)rù}rú(haUhbjLhjhŒhljxhn}rû(hp]hq]hr]hs]hv]uhxMhyhhz]rüj{)rý}rþ(haX@Oregano <==> BC-ICSS1-eth4 <==> BC-ICSS2-eth2 <==> OC-ICSS2-eth2rÿj~KhbjùhjhŒhlhxhn}r(hp]hq]hr]hs]hv]uhxMhyhhz]rhƒX@Oregano <==> BC-ICSS1-eth4 <==> BC-ICSS2-eth2 <==> OC-ICSS2-eth2r…r}r(hajÿhbjýubaubaubjº)r}r(haX... Image:: ../images/Pic_ptp_bc_eth4_eth2.png hbjLhjhŒhlj½hn}r(UuriX(linux/../images/Pic_ptp_bc_eth4_eth2.pngrhs]hr]hp]hq]jÀ}r U*jshv]uhxMhyhhz]ubj)r }r (haXBC (GMAC ICSS1-HSR)r hbjLhjhŒhlj¡hn}r (hs]rUbc-gmac-icss1-hsrrahr]hp]hq]hv]rh BC-GMAC-eth1 <==> BC-ICSS1-eth4/5(HSR) <==> OC-ICSS2-eth2/3(HSR)rj~KhbjhjhŒhlhxhn}r(hp]hq]hr]hs]hv]uhxM hyhhz]rhƒXMOregano <==> BC-GMAC-eth1 <==> BC-ICSS1-eth4/5(HSR) <==> OC-ICSS2-eth2/3(HSR)r…r}r (hajhbjubaubaubjº)r!}r"(haX3.. Image:: ../images/Pic_ptp_bc_eth1_eth4_hsr.png hbjLhjhŒhlj½hn}r#(UuriX,linux/../images/Pic_ptp_bc_eth1_eth4_hsr.pngr$hs]hr]hp]hq]jÀ}r%U*j$shv]uhxMhyhhz]ubj)r&}r'(haXBC (GMAC ICSS1-PRP)r(hbjLhjhŒhlj¡hn}r)(hs]r*Ubc-gmac-icss1-prpr+ahr]hp]hq]hv]r,hauhxNhyhhz]r-hƒXBC (GMAC ICSS1-PRP)r.…r/}r0(haj(hbj&ubaubju)r1}r2(haUhbjLhjhŒhljxhn}r3(hp]hq]hr]hs]hv]uhxMhyhhz]r4j{)r5}r6(haXMOregano <==> BC-GMAC-eth1 <==> BC-ICSS1-eth4/5(PRP) <==> OC-ICSS2-eth2/3(PRP)r7j~Khbj1hjhŒhlhxhn}r8(hp]hq]hr]hs]hv]uhxMhyhhz]r9hƒXMOregano <==> BC-GMAC-eth1 <==> BC-ICSS1-eth4/5(PRP) <==> OC-ICSS2-eth2/3(PRP)r:…r;}r<(haj7hbj5ubaubaubjº)r=}r>(haX3.. Image:: ../images/Pic_ptp_bc_eth1_eth4_prp.png hbjLhjhŒhlj½hn}r?(UuriX,linux/../images/Pic_ptp_bc_eth1_eth4_prp.pngr@hs]hr]hp]hq]jÀ}rAU*j@shv]uhxMhyhhz]ubeubhc)rB}rC(haUh˜Khbj" hjhŒhlhmhn}rD(hp]rEj.ahq]hr]hs]rFUid7rGahv]uhxMhyhhz]rH(h|)rI}rJ(haX LimitationsrKhbjBhjhŒhlh€hn}rL(hp]hq]hr]hs]hv]uhxMhyhhz]rMhƒX LimitationsrN…rO}rP(hajKhbjIubaubh¹)rQ}rR(haUhbjBhjhŒhlh¼hn}rS(h¾X-hs]hr]hp]hq]hv]uhxMhyhhz]rThÀ)rU}rV(haXIn the current implementation, when running more than one OC, for example, ICSS1 OC and ICSS2 OC, only one pps can be enabled through command line. In this example, if ptp1 is the device for ICSS2 OC and ptp2 is the device for ICSS1 OC, then only one of the following will be allowed: hbjQhjhŒhlhÃhn}rW(hp]hq]hr]hs]hv]uhxNhyhhz]rXh§)rY}rZ(haXIn the current implementation, when running more than one OC, for example, ICSS1 OC and ICSS2 OC, only one pps can be enabled through command line. In this example, if ptp1 is the device for ICSS2 OC and ptp2 is the device for ICSS1 OC, then only one of the following will be allowed:r[hbjUhjhŒhlh«hn}r\(hp]hq]hr]hs]hv]uhxMhz]r]hƒXIn the current implementation, when running more than one OC, for example, ICSS1 OC and ICSS2 OC, only one pps can be enabled through command line. In this example, if ptp1 is the device for ICSS2 OC and ptp2 is the device for ICSS1 OC, then only one of the following will be allowed:r^…r_}r`(haj[hbjYubaubaubaubj9)ra}rb(haX=echo 1 > /sys/devices/platform/pruss2_eth/ptp/ptp1/pps_enablehbjBhjhŒhlj<hn}rc(hh‘hs]hr]hp]hq]hv]uhxM'hyhhz]rdhƒX=echo 1 > /sys/devices/platform/pruss2_eth/ptp/ptp1/pps_enablere…rf}rg(haUhbjaubaubh§)rh}ri(haXorrjhbjBhjhŒhlh«hn}rk(hp]hq]hr]hs]hv]uhxM$hyhhz]rlhƒXorrm…rn}ro(hajjhbjhubaubj9)rp}rq(haX=echo 1 > /sys/devices/platform/pruss1_eth/ptp/ptp2/pps_enablehbjBhjhŒhlj<hn}rr(hh‘hs]hr]hp]hq]hv]uhxM-hyhhz]rshƒX=echo 1 > /sys/devices/platform/pruss1_eth/ptp/ptp2/pps_enablert…ru}rv(haUhbjpubaubh§)rw}rx(haXThe same is true for other combinations. The intention is to avoid having more than one PPS enabled when the IDK has the HW mod mentioned in `Hardware Modifications for AM57xx IDK BC <#hardware-modifications-for-am57xx-idk-bc>`__ and the pins are tied together.hbjBhjhŒhlh«hn}ry(hp]hq]hr]hs]hv]uhxM*hyhhz]rz(hƒXThe same is true for other combinations. The intention is to avoid having more than one PPS enabled when the IDK has the HW mod mentioned in r{…r|}r}(haXThe same is true for other combinations. The intention is to avoid having more than one PPS enabled when the IDK has the HW mod mentioned in hbjwubj_)r~}r(haXX`Hardware Modifications for AM57xx IDK BC <#hardware-modifications-for-am57xx-idk-bc>`__hn}r€(UnameX(Hardware Modifications for AM57xx IDK BCjvX)#hardware-modifications-for-am57xx-idk-bchs]hr]hp]hq]hv]uhbjwhz]rhƒX(Hardware Modifications for AM57xx IDK BCr‚…rƒ}r„(haUhbj~ubahljhubhƒX and the pins are tied together.r……r†}r‡(haX and the pins are tied together.hbjwubeubeubeubhc)rˆ}r‰(haUhbhhhjhŒhlhmhn}rŠ(hp]hq]hr]hs]r‹U hsr-oc-tcrŒahv]rhauhxM2hyhhz]rŽ(h|)r}r(haX HSR OC TCr‘hbjˆhjhŒhlh€hn}r’(hp]hq]hr]hs]hv]uhxM2hyhhz]r“hƒX HSR OC TCr”…r•}r–(haj‘hbjubaubhc)r—}r˜(haUh˜KhbjˆhjhŒhlhmhn}r™(hp]ršh›ahq]hr]hs]r›Uid8rœahv]uhxM5hyhhz]r(h|)rž}rŸ(haXOverviewr hbj—hjhŒhlh€hn}r¡(hp]hq]hr]hs]hv]uhxM5hyhhz]r¢hƒXOverviewr£…r¤}r¥(haj hbjžubaubh§)r¦}r§(haX–The purpose of this section and the sub-sections there in is to provide an overview of Linux PTP ordinary clock (OC) and transparent clock (TC) in a HSR network, the internal mechanism of how HSR OC and TC works on TI's AM57xx processors, required software and hardware, test setup and procedure, and our test results. In this section boundary clock (BC) with connections in HSR network is not considered.r¨hbj—hjhŒhlh«hn}r©(hp]hq]hr]hs]hv]uhxM7hyhhz]rªhƒX–The purpose of this section and the sub-sections there in is to provide an overview of Linux PTP ordinary clock (OC) and transparent clock (TC) in a HSR network, the internal mechanism of how HSR OC and TC works on TI's AM57xx processors, required software and hardware, test setup and procedure, and our test results. In this section boundary clock (BC) with connections in HSR network is not considered.r«…r¬}r­(haj¨hbj¦ubaubeubhc)r®}r¯(haUhbjˆhjhŒhlhmhn}r°(hp]hq]hr]hs]r±Uptp-oc-tc-in-hsr-networkr²ahv]r³hauhxM?hyhhz]r´(h|)rµ}r¶(haXPTP OC, TC in HSR Networkr·hbj®hjhŒhlh€hn}r¸(hp]hq]hr]hs]hv]uhxM?hyhhz]r¹hƒXPTP OC, TC in HSR Networkrº…r»}r¼(haj·hbjµubaubh§)r½}r¾(haXóThe implementation of the HSR OC and TC on AM57xx is based on the IEEE-62439-03-2016 recommendation. Currently it supports only two-step HSR hybrid clock (OC+TC) without BMCA enhanced for HSR. Future releases will fill in the missing features.r¿hbj®hjhŒhlh«hn}rÀ(hp]hq]hr]hs]hv]uhxMAhyhhz]rÁhƒXóThe implementation of the HSR OC and TC on AM57xx is based on the IEEE-62439-03-2016 recommendation. Currently it supports only two-step HSR hybrid clock (OC+TC) without BMCA enhanced for HSR. Future releases will fill in the missing features.rÂ…rÃ}rÄ(haj¿hbj½ubaubh§)rÅ}rÆ(haXSince HSR network is a ring topology network, the PTP clocks in such networks must handle PTP messages communicated over the two slave ports under a HSR interface. In addition to originating its own PTP messages and receiving PTP messages, a HSR clock must also forward PTP messages, except link local messages, for downstream nodes to process. In other words, a PTP clock in a HSR network must either be a standalone TC or an OC which also functions as a TC, i.e. a hybrid clock, as is defined in IEEE-62439-03-2016.rÇhbj®hjhŒhlh«hn}rÈ(hp]hq]hr]hs]hv]uhxMFhyhhz]rÉhƒXSince HSR network is a ring topology network, the PTP clocks in such networks must handle PTP messages communicated over the two slave ports under a HSR interface. In addition to originating its own PTP messages and receiving PTP messages, a HSR clock must also forward PTP messages, except link local messages, for downstream nodes to process. In other words, a PTP clock in a HSR network must either be a standalone TC or an OC which also functions as a TC, i.e. a hybrid clock, as is defined in IEEE-62439-03-2016.rÊ…rË}rÌ(hajÇhbjÅubaubhc)rÍ}rÎ(haUh˜Khbj®hjhŒhlhmhn}rÏ(hp]rÐjá ahq]hr]hs]rÑUid9rÒahv]uhxMPhyhhz]rÓ(h|)rÔ}rÕ(haXHardwarerÖhbjÍhjhŒhlh€hn}r×(hp]hq]hr]hs]hv]uhxMPhyhhz]rØhƒXHardwarerÙ…rÚ}rÛ(hajÖhbjÔubaubh§)rÜ}rÝ(haXiOn AM57xx platforms, the HSR PTP OC and TC functionalities are provided by the ICSS-PRU hardware modules.rÞhbjÍhjhŒhlh«hn}rß(hp]hq]hr]hs]hv]uhxMRhyhhz]ràhƒXiOn AM57xx platforms, the HSR PTP OC and TC functionalities are provided by the ICSS-PRU hardware modules.rá…râ}rã(hajÞhbjÜubaubeubhc)rä}rå(haUh˜Khbj®hjhŒhlhmhn}ræ(hp]rçjäahq]hr]hs]rèUid10réahv]uhxMVhyhhz]rê(h|)rë}rì(haXSoftwareríhbjähjhŒhlh€hn}rî(hp]hq]hr]hs]hv]uhxMVhyhhz]rïhƒXSoftwarerð…rñ}rò(hajíhbjëubaubh§)ró}rô(haXÑOn the software side, the key software modules for supporting the HSR PTP clock functionalities include the HSR firmware, PRU ethernet driver, core HSR layer, core network layer and the application linuxptp. The Linux kernel modules are responsible passing timestamps and HSR tag information to application linuxptp on receive path. On transmit path, those kernel modules are also responsible for accepting HSR tag information (if passed in by application, for example, for delay corrected FOLLOW-UPs that are passing through the node) and sending frames out over a specific HSR slave port indicated by the application. Sending a PTP message over a specified HSR slave port is needed, for example, for FOLLOW-UP messages.rõhbjähjhŒhlh«hn}rö(hp]hq]hr]hs]hv]uhxMXhyhhz]r÷hƒXÑOn the software side, the key software modules for supporting the HSR PTP clock functionalities include the HSR firmware, PRU ethernet driver, core HSR layer, core network layer and the application linuxptp. The Linux kernel modules are responsible passing timestamps and HSR tag information to application linuxptp on receive path. On transmit path, those kernel modules are also responsible for accepting HSR tag information (if passed in by application, for example, for delay corrected FOLLOW-UPs that are passing through the node) and sending frames out over a specific HSR slave port indicated by the application. Sending a PTP message over a specified HSR slave port is needed, for example, for FOLLOW-UP messages.rø…rù}rú(hajõhbjóubaubh§)rû}rü(haXFor OC functionality, other than handling the HSR tag information, the processing of PTP messages by the application is similar to the regular OC functionality without HSR, although the application running on a slave OC must only allow the ACTIVE port to adjust its PTP clock.rýhbjähjhŒhlh«hn}rþ(hp]hq]hr]hs]hv]uhxMdhyhhz]rÿhƒXFor OC functionality, other than handling the HSR tag information, the processing of PTP messages by the application is similar to the regular OC functionality without HSR, although the application running on a slave OC must only allow the ACTIVE port to adjust its PTP clock.r…r}r(hajýhbjûubaubh§)r}r(haX»One of the key features of a TC is the capability of being able to make timestamp "corrections" in the FOLLOW-UP message for a SYNC message. This is achieved as follows. When the HSR firmware receives a SYNC message, it passes both the rx timestamp and cut-through forward tx timestamp of the SYNC message to the host driver. These timestamps are then passed to the application, along with the SYNC, by the kernel drivers. With the rx timestamp and the cut-through tx timestamp of the SYNC message, the application linuxptp can then add the residence time delay, in addtion to the peer path delay, in the correctionField of the SYNC's FOLLOW-UP message before the FOLLOW-UP is forwarded to next hop.rhbjähjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxMihyhhz]rhƒX»One of the key features of a TC is the capability of being able to make timestamp "corrections" in the FOLLOW-UP message for a SYNC message. This is achieved as follows. When the HSR firmware receives a SYNC message, it passes both the rx timestamp and cut-through forward tx timestamp of the SYNC message to the host driver. These timestamps are then passed to the application, along with the SYNC, by the kernel drivers. With the rx timestamp and the cut-through tx timestamp of the SYNC message, the application linuxptp can then add the residence time delay, in addtion to the peer path delay, in the correctionField of the SYNC's FOLLOW-UP message before the FOLLOW-UP is forwarded to next hop.r…r }r (hajhbjubaubeubeubhc)r }r (haUhbjˆhjhŒhlhmhn}r (hp]hq]hr]hs]rU1required-hardware-and-software-to-setup-hsr-oc-tcrahv]rhQauhxMuhyhhz]r(h|)r}r(haX2Required hardware and software to setup HSR OC, TCrhbj hjhŒhlh€hn}r(hp]hq]hr]hs]hv]uhxMuhyhhz]rhƒX2Required hardware and software to setup HSR OC, TCr…r}r(hajhbjubaubhc)r}r(haUhbj hjhŒhlhmhn}r(hp]hq]hr]hs]rU/hardware-modifications-for-am57xx-idk-hsr-oc-tcrahv]rhWauhxMxhyhhz]r (h|)r!}r"(haX0Hardware Modifications for AM57xx IDK HSR OC, TCr#hbjhjhŒhlh€hn}r$(hp]hq]hr]hs]hv]uhxMxhyhhz]r%hƒX0Hardware Modifications for AM57xx IDK HSR OC, TCr&…r'}r((haj#hbj!ubaubh§)r)}r*(haXÁThe hardware modifications needed for AM57xx IDK to function as HSR OC and TC are the same as those required for regular OC and BC. These modifications are for PPS generation on the AM57xx IDK.r+hbjhjhŒhlh«hn}r,(hp]hq]hr]hs]hv]uhxMzhyhhz]r-hƒXÁThe hardware modifications needed for AM57xx IDK to function as HSR OC and TC are the same as those required for regular OC and BC. These modifications are for PPS generation on the AM57xx IDK.r.…r/}r0(haj+hbj)ubaubhc)r1}r2(haUhbjhjhŒhlhmhn}r3(hp]hq]hr]hs]r4Uam571xr5ahv]r6hXauhxMhyhhz]r7(h|)r8}r9(haXAM571xr:hbj1hjhŒhlh€hn}r;(hp]hq]hr]hs]hv]uhxMhyhhz]r<hƒXAM571xr=…r>}r?(haj:hbj8ubaubh§)r@}rA(haXSee the `AM571x Mod List `_ for more details of the hardware modification specification. Sample assembly photos can be found `here `_hbj1hjhŒhlh«hn}rB(hp]hq]hr]hs]hv]uhxMhyhhz]rC(hƒXSee the rD…rE}rF(haXSee the hbj@ubj_)rG}rH(haXY`AM571x Mod List `_hn}rI(UnameXAM571x Mod ListjvXDhttp://processors.wiki.ti.com/images/3/34/Am571x_idk_pps_ModList.pdfrJhs]hr]hp]hq]hv]uhbj@hz]rKhƒXAM571x Mod ListrL…rM}rN(haUhbjGubahljhubj®)rO}rP(haXG h˜Khbj@hlj±hn}rQ(UrefurijJhs]rRUam571x-mod-listrSahr]hp]hq]hv]rThRauhz]ubhƒXb for more details of the hardware modification specification. Sample assembly photos can be found rU…rV}rW(haXb for more details of the hardware modification specification. Sample assembly photos can be found hbj@ubj_)rX}rY(haXM`here `_hn}rZ(Unameh'jvXChttp://processors.wiki.ti.com/images/9/9d/IDK-Mods-AM571x-v2.2c.pdfr[hs]hr]hp]hq]hv]uhbj@hz]r\hƒXherer]…r^}r_(haUhbjXubahljhubj®)r`}ra(haXF h˜Khbj@hlj±hn}rb(Urefurij[hs]rcUhererdahr]hp]hq]hv]reh'auhz]ubeubeubhc)rf}rg(haUhbjhjhŒhlhmhn}rh(hp]hq]hr]hs]riUam572x-and-am574xrjahv]rkhHauhxM‡hyhhz]rl(h|)rm}rn(haXAM572x and AM574xrohbjfhjhŒhlh€hn}rp(hp]hq]hr]hs]hv]uhxM‡hyhhz]rqhƒXAM572x and AM574xrr…rs}rt(hajohbjmubaubh§)ru}rv(haX¬See the `AM572x/AM574x Mod List `_ for more details of the hardware modification specification.hbjfhjhŒhlh«hn}rw(hp]hq]hr]hs]hv]uhxM‰hyhhz]rx(hƒXSee the ry…rz}r{(haXSee the hbjuubj_)r|}r}(haXg`AM572x/AM574x Mod List `_hn}r~(UnameXAM572x/AM574x Mod ListjvXKhttp://processors.wiki.ti.com/images/2/2f/Am572x_am574x_idk_pps_ModList.pdfrhs]hr]hp]hq]hv]uhbjuhz]r€hƒXAM572x/AM574x Mod Listr…r‚}rƒ(haUhbj|ubahljhubj®)r„}r…(haXN h˜Khbjuhlj±hn}r†(Urefurijhs]r‡Uam572x-am574x-mod-listrˆahr]hp]hq]hv]r‰h auhz]ubhƒX= for more details of the hardware modification specification.rŠ…r‹}rŒ(haX= for more details of the hardware modification specification.hbjuubeubeubeubhc)r}rŽ(haUh˜Khbj hjhŒhlhmhn}r(hp]rXsoftwarer‘ahq]hr]hs]r’Uid11r“ahv]uhxMŽhyhhz]r”(h|)r•}r–(haXSoftwarer—hbjhjhŒhlh€hn}r˜(hp]hq]hr]hs]hv]uhxMŽhyhhz]r™hƒXSoftwarerš…r›}rœ(haj—hbj•ubaubh§)r}rž(haX¶AM57xx HSR OC and TC are supported with limitations in ProcessorSDK Linux release starting from version 4.3.0.6. See the section `Limitations <#Limitations>`_ below for more details.hbjhjhŒhlh«hn}rŸ(hp]hq]hr]hs]hv]uhxMhyhhz]r (hƒXAM57xx HSR OC and TC are supported with limitations in ProcessorSDK Linux release starting from version 4.3.0.6. See the section r¡…r¢}r£(haXAM57xx HSR OC and TC are supported with limitations in ProcessorSDK Linux release starting from version 4.3.0.6. See the section hbjubj_)r¤}r¥(haX`Limitations <#Limitations>`_hn}r¦(UnameX LimitationsjvX #Limitationsr§hs]hr]hp]hq]hv]uhbjhz]r¨hƒX Limitationsr©…rª}r«(haUhbj¤ubahljhubj®)r¬}r­(haX <#Limitations>h˜Khbjhlj±hn}r®(Urefurij§hs]r¯Uid12r°ahr]hp]hq]hv]r±X limitationsr²auhz]ubhƒX below for more details.r³…r´}rµ(haX below for more details.hbjubeubh§)r¶}r·(haX **Remark** Because PPS needs to be enabled in PTP tests, so the devicetree (dtb) needs to be loaded when booting the kernel must contain the PPS configurations. But by default, after **make Linux\_install**, the default devicetree is not the right one for enabling PPS:hbjhjhŒhlh«hn}r¸(hp]hq]hr]hs]hv]uhxM”hyhhz]r¹(j)rº}r»(haX **Remark**hn}r¼(hp]hq]hr]hs]hv]uhbj¶hz]r½hƒXRemarkr¾…r¿}rÀ(haUhbjºubahlj‡ubhƒX­ Because PPS needs to be enabled in PTP tests, so the devicetree (dtb) needs to be loaded when booting the kernel must contain the PPS configurations. But by default, after rÁ…rÂ}rÃ(haX­ Because PPS needs to be enabled in PTP tests, so the devicetree (dtb) needs to be loaded when booting the kernel must contain the PPS configurations. But by default, after hbj¶ubj)rÄ}rÅ(haX**make Linux\_install**hn}rÆ(hp]hq]hr]hs]hv]uhbj¶hz]rÇhƒXmake Linux_installrÈ…rÉ}rÊ(haUhbjÄubahlj‡ubhƒX?, the default devicetree is not the right one for enabling PPS:rË…rÌ}rÍ(haX?, the default devicetree is not the right one for enabling PPS:hbj¶ubeubj9)rÎ}rÏ(haX™$ ls -l /rel4306/rootfs/boot/am571x-idk.dtb lrwxrwxrwx 1 user user32 Apr 20 22:54 /rel4306/rootfs/boot/am571x-idk.dtb -> devicetree-uImage-am571x-idk.dtbhbjhjhŒhlj<hn}rÐ(hh‘hs]hr]hp]hq]hv]uhxM hyhhz]rÑhƒX™$ ls -l /rel4306/rootfs/boot/am571x-idk.dtb lrwxrwxrwx 1 user user32 Apr 20 22:54 /rel4306/rootfs/boot/am571x-idk.dtb -> devicetree-uImage-am571x-idk.dtbrÒ…rÓ}rÔ(haUhbjÎubaubh§)rÕ}rÖ(haX*The correct dtb needed for enabling pps isr×hbjhjhŒhlh«hn}rØ(hp]hq]hr]hs]hv]uhxMžhyhhz]rÙhƒX*The correct dtb needed for enabling pps isrÚ…rÛ}rÜ(haj×hbjÕubaubj9)rÝ}rÞ(haX¦$ ls -l /rel4306/rootfs/boot/am571x-idk-pps.dtb lrwxrwxrwx 1 user user 36 Apr 20 22:54 /rel4306/rootfs/boot/am571x-idk-pps.dtb -> devicetree-uImage-am571x-idk-pps.dtbhbjhjhŒhlj<hn}rß(hh‘hs]hr]hp]hq]hv]uhxM§hyhhz]ràhƒX¦$ ls -l /rel4306/rootfs/boot/am571x-idk-pps.dtb lrwxrwxrwx 1 user user 36 Apr 20 22:54 /rel4306/rootfs/boot/am571x-idk-pps.dtb -> devicetree-uImage-am571x-idk-pps.dtbrá…râ}rã(haUhbjÝubaubh§)rä}rå(haXŒFor PTP tests, the default dtb **am571x-idk.dtb** needs to be replaced by **am571x-idk-pps.dtb** when creating the SDCard for kernel bootup.hbjhjhŒhlh«hn}ræ(hp]hq]hr]hs]hv]uhxM¥hyhhz]rç(hƒXFor PTP tests, the default dtb rè…ré}rê(haXFor PTP tests, the default dtb hbjäubj)rë}rì(haX**am571x-idk.dtb**hn}rí(hp]hq]hr]hs]hv]uhbjähz]rîhƒXam571x-idk.dtbrï…rð}rñ(haUhbjëubahlj‡ubhƒX needs to be replaced by rò…ró}rô(haX needs to be replaced by hbjäubj)rõ}rö(haX**am571x-idk-pps.dtb**hn}r÷(hp]hq]hr]hs]hv]uhbjähz]røhƒXam571x-idk-pps.dtbrù…rú}rû(haUhbjõubahlj‡ubhƒX, when creating the SDCard for kernel bootup.rü…rý}rþ(haX, when creating the SDCard for kernel bootup.hbjäubeubh§)rÿ}r(haXbOne way to do that is, for example, in the boot directory overwrite the default dtb by the pps dtbrhbjhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxM¨hyhhz]rhƒXbOne way to do that is, for example, in the boot directory overwrite the default dtb by the pps dtbr…r}r(hajhbjÿubaubj9)r}r(haXV$ cd /rel4306/rootfs/boot/ $ rm am571x-idk.dtb $ cp am571x-idk-pps.dtb am571x-idk.dtbhbjhjhŒhlj<hn}r (hh‘hs]hr]hp]hq]hv]uhxM²hyhhz]r hƒXV$ cd /rel4306/rootfs/boot/ $ rm am571x-idk.dtb $ cp am571x-idk-pps.dtb am571x-idk.dtbr …r }r (haUhbjubaubh§)r}r(haX5And then follow the usual steps to create the SDCard.rhbjhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxM±hyhhz]rhƒX5And then follow the usual steps to create the SDCard.r…r}r(hajhbjubaubh§)r}r(haXSimilarly for AM572x.rhbjhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxM³hyhhz]rhƒXSimilarly for AM572x.r…r}r(hajhbjubaubeubeubhc)r}r(haUh˜KhbjˆhjhŒhlhmhn}r (hp]r!j; ahq]hr]hs]r"Uid13r#ahv]uhxM¶hyhhz]r$(h|)r%}r&(haXTest Setup/Procedurer'hbjhjhŒhlh€hn}r((hp]hq]hr]hs]hv]uhxM¶hyhhz]r)hƒXTest Setup/Procedurer*…r+}r,(haj'hbj%ubaubhc)r-}r.(haUh˜KhbjhjhŒhlhmhn}r/(hp]r0XBtest 1. with a hybrid clock (oc+tc) between master and slave clockr1ahq]hr]hs]r2U?test-1-with-a-hybrid-clock-oc-tc-between-master-and-slave-clockr3ahv]uhxM¹hyhhz]r4(h|)r5}r6(haXBTest 1. With a hybrid clock (OC+TC) between master and slave clockr7hbj-hjhŒhlh€hn}r8(hp]hq]hr]hs]hv]uhxM¹hyhhz]r9hƒXBTest 1. With a hybrid clock (OC+TC) between master and slave clockr:…r;}r<(haj7hbj5ubaubhc)r=}r>(haUhbj-hjhŒhlhmhn}r?(hp]hq]hr]hs]r@U!a-sample-3-hsr-hybrid-clock-setuprAahv]rBh:auhxM¼hyhhz]rC(h|)rD}rE(haX!A Sample 3 HSR Hybrid Clock SetuprFhbj=hjhŒhlh€hn}rG(hp]hq]hr]hs]hv]uhxM¼hyhhz]rHhƒX!A Sample 3 HSR Hybrid Clock SetuprI…rJ}rK(hajFhbjDubaubjº)rL}rM(haX .. Image:: ../images/3clock.jpg hbj=hjhŒhlj½hn}rN(UuriXlinux/../images/3clock.jpgrOhs]hr]hp]hq]jÀ}rPU*jOshv]uhxM¿hyhhz]ubh§)rQ}rR(haXsAlthough each clock in this setup is a HSR hybrid clock, the role that each clock plays in this test is as follows:rShbj=hjhŒhlh«hn}rT(hp]hq]hr]hs]hv]uhxMÀhyhhz]rUhƒXsAlthough each clock in this setup is a HSR hybrid clock, the role that each clock plays in this test is as follows:rV…rW}rX(hajShbjQubaubj9)rY}rZ(haXcDUT-2 : AM572x : Master clock DUT-1 : AM571x : Transparent clock DUT-3 : AM572x : Slave clockhbj=hjhŒhlj<hn}r[(hh‘hs]hr]hp]hq]hv]uhxMÊhyhhz]r\hƒXcDUT-2 : AM572x : Master clock DUT-1 : AM571x : Transparent clock DUT-3 : AM572x : Slave clockr]…r^}r_(haUhbjYubaubcdocutils.nodes note r`)ra}rb(haXmIn this release BMCA enhanced for HSR is not supported, hence the connection is not a HSR close-loop network.rchbj=hjhŒhlUnoterdhn}re(hp]hq]hr]hs]hv]uhxNhyhhz]rfh§)rg}rh(hajchbjahjhŒhlh«hn}ri(hp]hq]hr]hs]hv]uhxMÉhz]rjhƒXmIn this release BMCA enhanced for HSR is not supported, hence the connection is not a HSR close-loop network.rk…rl}rm(hajchbjgubaubaubeubhc)rn}ro(haUh˜Khbj-hjhŒhlhmhn}rp(hp]rqX procedurerrahq]hr]hs]rsU procedurertahv]uhxMÌhyhhz]ru(h|)rv}rw(haX ProcedurerxhbjnhjhŒhlh€hn}ry(hp]hq]hr]hs]hv]uhxMÌhyhhz]rzhƒX Procedurer{…r|}r}(hajxhbjvubaubh§)r~}r(haXTThe script file `setup\_hsr.sh `_ and clock configuration files e.g. dut_1_hsr_oc.cfg, dut_2_hsr_oc.cfg, dut_3_hsr_oc.cfg (each identical, same as listed in `PTP Redundancy `__ section for HSR) will be used in the setup of the tests.hbjnhjhŒhlh«hn}r€(hp]hq]hr]hs]hv]uhxMÎhyhhz]r(hƒXThe script file r‚…rƒ}r„(haXThe script file hbj~ubj_)r…}r†(haXJ`setup\_hsr.sh `_hn}r‡(Unameh2jvX7http://processors.wiki.ti.com/images/1/18/Setup_hsr.pdfrˆhs]hr]hp]hq]hv]uhbj~hz]r‰hƒX setup_hsr.shrŠ…r‹}rŒ(haUhbj…ubahljhubj®)r}rŽ(haX: h˜Khbj~hlj±hn}r(Urefurijˆhs]rU setup-hsr-shr‘ahr]hp]hq]hv]r’h2auhz]ubhƒX| and clock configuration files e.g. dut_1_hsr_oc.cfg, dut_2_hsr_oc.cfg, dut_3_hsr_oc.cfg (each identical, same as listed in r“…r”}r•(haX| and clock configuration files e.g. dut_1_hsr_oc.cfg, dut_2_hsr_oc.cfg, dut_3_hsr_oc.cfg (each identical, same as listed in hbj~ubj_)r–}r—(haXE`PTP Redundancy `__hn}r˜(UnameXPTP RedundancyjvX0Industrial_Protocols_PTP.html#redundancy-hsr-prphs]hr]hp]hq]hv]uhbj~hz]r™hƒXPTP Redundancyrš…r›}rœ(haUhbj–ubahljhubhƒX9 section for HSR) will be used in the setup of the tests.r…rž}rŸ(haX9 section for HSR) will be used in the setup of the tests.hbj~ubeubh¹)r }r¡(haUhbjnhjhŒhlh¼hn}r¢(h¾X-hs]hr]hp]hq]hv]uhxMÕhyhhz]r£hÀ)r¤}r¥(haX©For each DUT-X, copy the setup script setup\_hsr.sh and the clock configuration file dut\_X\_hsr\_oc.cfg into the target filesystem of DUT-X. For the sample setup above hbj hjhŒhlhÃhn}r¦(hp]hq]hr]hs]hv]uhxNhyhhz]r§h§)r¨}r©(haX¨For each DUT-X, copy the setup script setup\_hsr.sh and the clock configuration file dut\_X\_hsr\_oc.cfg into the target filesystem of DUT-X. For the sample setup abovehbj¤hjhŒhlh«hn}rª(hp]hq]hr]hs]hv]uhxMÕhz]r«hƒX¤For each DUT-X, copy the setup script setup_hsr.sh and the clock configuration file dut_X_hsr_oc.cfg into the target filesystem of DUT-X. For the sample setup abover¬…r­}r®(haX¨For each DUT-X, copy the setup script setup\_hsr.sh and the clock configuration file dut\_X\_hsr\_oc.cfg into the target filesystem of DUT-X. For the sample setup abovehbj¨ubaubaubaubj9)r¯}r°(haX}DUT-2 : setup_hsr.sh : dut_2_hsr_oc.cfg DUT-1 : setup_hsr.sh : dut_1_hsr_oc.cfg DUT-3 : setup_hsr.sh : dut_3_hsr_oc.cfghbjnhjhŒhlj<hn}r±(hh‘hs]hr]hp]hq]hv]uhxMàhyhhz]r²hƒX}DUT-2 : setup_hsr.sh : dut_2_hsr_oc.cfg DUT-1 : setup_hsr.sh : dut_1_hsr_oc.cfg DUT-3 : setup_hsr.sh : dut_3_hsr_oc.cfgr³…r´}rµ(haUhbj¯ubaubh¹)r¶}r·(haUhbjnhjhŒhlh¼hn}r¸(h¾X-hs]hr]hp]hq]hv]uhxMßhyhhz]r¹(hÀ)rº}r»(haX*Connect the 3 AM57xx IDKs as shown above. hbj¶hjhŒhlhÃhn}r¼(hp]hq]hr]hs]hv]uhxNhyhhz]r½h§)r¾}r¿(haX)Connect the 3 AM57xx IDKs as shown above.rÀhbjºhjhŒhlh«hn}rÁ(hp]hq]hr]hs]hv]uhxMßhz]rÂhƒX)Connect the 3 AM57xx IDKs as shown above.rÃ…rÄ}rÅ(hajÀhbj¾ubaubaubhÀ)rÆ}rÇ(haXLBoot IDK into u-boot prompt and to specify HSR firmware is to be loaded, do hbj¶hjhŒhlhÃhn}rÈ(hp]hq]hr]hs]hv]uhxNhyhhz]rÉh§)rÊ}rË(haXKBoot IDK into u-boot prompt and to specify HSR firmware is to be loaded, dorÌhbjÆhjhŒhlh«hn}rÍ(hp]hq]hr]hs]hv]uhxMáhz]rÎhƒXKBoot IDK into u-boot prompt and to specify HSR firmware is to be loaded, dorÏ…rÐ}rÑ(hajÌhbjÊubaubaubeubj9)rÒ}rÓ(haX=$ setenv pruss1_ethtype 1 $ setenv pruss2_ethtype 1 $ saveenvhbjnhjhŒhlj<hn}rÔ(hh‘hs]hr]hp]hq]hv]uhxMëhyhhz]rÕhƒX=$ setenv pruss1_ethtype 1 $ setenv pruss2_ethtype 1 $ saveenvrÖ…r×}rØ(haUhbjÒubaubh¹)rÙ}rÚ(haUhbjnhjhŒhlh¼hn}rÛ(h¾X-hs]hr]hp]hq]hv]uhxMêhyhhz]rÜ(hÀ)rÝ}rÞ(haXBoot IDK into kernel prompt. hbjÙhjhŒhlhÃhn}rß(hp]hq]hr]hs]hv]uhxNhyhhz]ràh§)rá}râ(haXBoot IDK into kernel prompt.rãhbjÝhjhŒhlh«hn}rä(hp]hq]hr]hs]hv]uhxMêhz]råhƒXBoot IDK into kernel prompt.ræ…rç}rè(hajãhbjáubaubaubhÀ)ré}rê(haX:Modify the top fields in `setup\_hsr.sh `_ to reflect the HSR slave ports' MAC addresses and IP address of the DUT's HSR interface. The **ETHA** or **ETHB** fields may also need to be modified if an ICSS different from the one shown in the picture is used. hbjÙhjhŒhlhÃhn}rë(hp]hq]hr]hs]hv]uhxNhyhhz]rìh§)rí}rî(haX9Modify the top fields in `setup\_hsr.sh `_ to reflect the HSR slave ports' MAC addresses and IP address of the DUT's HSR interface. The **ETHA** or **ETHB** fields may also need to be modified if an ICSS different from the one shown in the picture is used.hbjéhjhŒhlh«hn}rï(hp]hq]hr]hs]hv]uhxMìhz]rð(hƒXModify the top fields in rñ…rò}ró(haXModify the top fields in hbjíubj_)rô}rõ(haXJ`setup\_hsr.sh `_hn}rö(UnameX setup_hsr.shr÷jvX7http://processors.wiki.ti.com/images/1/18/Setup_hsr.pdfrøhs]hr]hp]hq]hv]uhbjíhz]rùhƒX setup_hsr.shrú…rû}rü(haUhbjôubahljhubj®)rý}rþ(haX: h˜Khbjíhlj±hn}rÿ(Urefurijøhs]rUid14rahr]hp]rj÷ahq]hv]uhz]ubhƒX^ to reflect the HSR slave ports' MAC addresses and IP address of the DUT's HSR interface. The r…r}r(haX^ to reflect the HSR slave ports' MAC addresses and IP address of the DUT's HSR interface. The hbjíubj)r}r(haX**ETHA**hn}r(hp]hq]hr]hs]hv]uhbjíhz]r hƒXETHAr …r }r (haUhbjubahlj‡ubhƒX or r …r}r(haX or hbjíubj)r}r(haX**ETHB**hn}r(hp]hq]hr]hs]hv]uhbjíhz]rhƒXETHBr…r}r(haUhbjubahlj‡ubhƒXd fields may also need to be modified if an ICSS different from the one shown in the picture is used.r…r}r(haXd fields may also need to be modified if an ICSS different from the one shown in the picture is used.hbjíubeubaubhÀ)r}r(haXGRun the modified setup\_hsr.sh script to configure the hsr0 interface. hbjÙhjhŒhlhÃhn}r(hp]hq]hr]hs]hv]uhxNhyhhz]rh§)r}r(haXFRun the modified setup\_hsr.sh script to configure the hsr0 interface.hbjhjhŒhlh«hn}r (hp]hq]hr]hs]hv]uhxMòhz]r!hƒXERun the modified setup_hsr.sh script to configure the hsr0 interface.r"…r#}r$(haXFRun the modified setup\_hsr.sh script to configure the hsr0 interface.hbjubaubaubhÀ)r%}r&(haXDAfter each IDK is bootup, do a ping to make sure the setup is fine. hbjÙhjhŒhlhÃhn}r'(hp]hq]hr]hs]hv]uhxNhyhhz]r(h§)r)}r*(haXCAfter each IDK is bootup, do a ping to make sure the setup is fine.r+hbj%hjhŒhlh«hn}r,(hp]hq]hr]hs]hv]uhxMõhz]r-hƒXCAfter each IDK is bootup, do a ping to make sure the setup is fine.r.…r/}r0(haj+hbj)ubaubaubhÀ)r1}r2(haXOn DUT-2 (master OC) do hbjÙhjhŒhlhÃhn}r3(hp]hq]hr]hs]hv]uhxNhyhhz]r4h§)r5}r6(haXOn DUT-2 (master OC) dor7hbj1hjhŒhlh«hn}r8(hp]hq]hr]hs]hv]uhxM÷hz]r9hƒXOn DUT-2 (master OC) dor:…r;}r<(haj7hbj5ubaubaubeubj9)r=}r>(haX$$ ptp4l -2 -P -f dut_2_hsr_oc.cfg -mhbjnhjhŒhlj<hn}r?(hh‘hs]hr]hp]hq]hv]uhxMhyhhz]r@hƒX$$ ptp4l -2 -P -f dut_2_hsr_oc.cfg -mrA…rB}rC(haUhbj=ubaubh¹)rD}rE(haUhbjnhjhŒhlh¼hn}rF(h¾X-hs]hr]hp]hq]hv]uhxMýhyhhz]rGhÀ)rH}rI(haXOn DUT-1 (OC+TC) do hbjDhjhŒhlhÃhn}rJ(hp]hq]hr]hs]hv]uhxNhyhhz]rKh§)rL}rM(haXOn DUT-1 (OC+TC) dorNhbjHhjhŒhlh«hn}rO(hp]hq]hr]hs]hv]uhxMýhz]rPhƒXOn DUT-1 (OC+TC) dorQ…rR}rS(hajNhbjLubaubaubaubj9)rT}rU(haX'$ ptp4l -2 -P -f dut_1_hsr_oc.cfg -m -shbjnhjhŒhlj<hn}rV(hh‘hs]hr]hp]hq]hv]uhxMhyhhz]rWhƒX'$ ptp4l -2 -P -f dut_1_hsr_oc.cfg -m -srX…rY}rZ(haUhbjTubaubh¹)r[}r\(haUhbjnhjhŒhlh¼hn}r](h¾X-hs]hr]hp]hq]hv]uhxMhyhhz]r^hÀ)r_}r`(haXOn DUT-3 (slave OC) do: hbj[hjhŒhlhÃhn}ra(hp]hq]hr]hs]hv]uhxNhyhhz]rbh§)rc}rd(haXOn DUT-3 (slave OC) do:rehbj_hjhŒhlh«hn}rf(hp]hq]hr]hs]hv]uhxMhz]rghƒXOn DUT-3 (slave OC) do:rh…ri}rj(hajehbjcubaubaubaubj9)rk}rl(haX'$ ptp4l -2 -P -f dut_3_hsr_oc.cfg -m -shbjnhjhŒhlj<hn}rm(hh‘hs]hr]hp]hq]hv]uhxM hyhhz]rnhƒX'$ ptp4l -2 -P -f dut_3_hsr_oc.cfg -m -sro…rp}rq(haUhbjkubaubh¹)rr}rs(haUhbjnhjhŒhlh¼hn}rt(h¾X-hs]hr]hp]hq]hv]uhxM hyhhz]ruhÀ)rv}rw(haX0Open a telnet terminal to DUT-2 and enable PPS: hbjrhjhŒhlhÃhn}rx(hp]hq]hr]hs]hv]uhxNhyhhz]ryh§)rz}r{(haX/Open a telnet terminal to DUT-2 and enable PPS:r|hbjvhjhŒhlh«hn}r}(hp]hq]hr]hs]hv]uhxM hz]r~hƒX/Open a telnet terminal to DUT-2 and enable PPS:r…r€}r(haj|hbjzubaubaubaubj9)r‚}rƒ(haX?$ echo 1 > /sys/devices/platform/pruss2_eth/ptp/ptp1/pps_enablehbjnhjhŒhlj<hn}r„(hh‘hs]hr]hp]hq]hv]uhxMhyhhz]r…hƒX?$ echo 1 > /sys/devices/platform/pruss2_eth/ptp/ptp1/pps_enabler†…r‡}rˆ(haUhbj‚ubaubh¹)r‰}rŠ(haUhbjnhjhŒhlh¼hn}r‹(h¾X-hs]hr]hp]hq]hv]uhxMhyhhz]rŒhÀ)r}rŽ(haX0Open a telnet terminal to DUT-3 and enable PPS: hbj‰hjhŒhlhÃhn}r(hp]hq]hr]hs]hv]uhxNhyhhz]rh§)r‘}r’(haX/Open a telnet terminal to DUT-3 and enable PPS:r“hbjhjhŒhlh«hn}r”(hp]hq]hr]hs]hv]uhxMhz]r•hƒX/Open a telnet terminal to DUT-3 and enable PPS:r–…r—}r˜(haj“hbj‘ubaubaubaubj9)r™}rš(haX?$ echo 1 > /sys/devices/platform/pruss2_eth/ptp/ptp1/pps_enablehbjnhjhŒhlj<hn}r›(hh‘hs]hr]hp]hq]hv]uhxMhyhhz]rœhƒX?$ echo 1 > /sys/devices/platform/pruss2_eth/ptp/ptp1/pps_enabler…rž}rŸ(haUhbj™ubaubh¹)r }r¡(haUhbjnhjhŒhlh¼hn}r¢(h¾X-hs]hr]hp]hq]hv]uhxMhyhhz]r£(hÀ)r¤}r¥(haX<Measure PPS jitter between DUT-2 (master) and DUT-3 (slave) hbj hjhŒhlhÃhn}r¦(hp]hq]hr]hs]hv]uhxNhyhhz]r§h§)r¨}r©(haX;Measure PPS jitter between DUT-2 (master) and DUT-3 (slave)rªhbj¤hjhŒhlh«hn}r«(hp]hq]hr]hs]hv]uhxMhz]r¬hƒX;Measure PPS jitter between DUT-2 (master) and DUT-3 (slave)r­…r®}r¯(hajªhbj¨ubaubaubhÀ)r°}r±(haXSee sample capture files `dut\_1\_log.txt `_, `dut\_2\_log.txt `_, `dut\_3\_log,txt `_ for more detail. hbj hjhŒhlhÃhn}r²(hp]hq]hr]hs]hv]uhxNhyhhz]r³h§)r´}rµ(haXSee sample capture files `dut\_1\_log.txt `_, `dut\_2\_log.txt `_, `dut\_3\_log,txt `_ for more detail.hbj°hjhŒhlh«hn}r¶(hp]hq]hr]hs]hv]uhxMhz]r·(hƒXSee sample capture files r¸…r¹}rº(haXSee sample capture files hbj´ubj_)r»}r¼(haXH`dut\_1\_log.txt `_hn}r½(UnamehUjvX3http://processors.wiki.ti.com/images/7/77/Dut_1.pdfr¾hs]hr]hp]hq]hv]uhbj´hz]r¿hƒX dut_1_log.txtrÀ…rÁ}rÂ(haUhbj»ubahljhubj®)rÃ}rÄ(haX6 h˜Khbj´hlj±hn}rÅ(Urefurij¾hs]rÆU dut-1-log-txtrÇahr]hp]hq]hv]rÈhUauhz]ubhƒX, rÉ…rÊ}rË(haX, hbj´ubj_)rÌ}rÍ(haXH`dut\_2\_log.txt `_hn}rÎ(UnamehjvX3http://processors.wiki.ti.com/images/e/ea/Dut_2.pdfrÏhs]hr]hp]hq]hv]uhbj´hz]rÐhƒX dut_2_log.txtrÑ…rÒ}rÓ(haUhbjÌubahljhubj®)rÔ}rÕ(haX6 h˜Khbj´hlj±hn}rÖ(UrefurijÏhs]r×U dut-2-log-txtrØahr]hp]hq]hv]rÙhauhz]ubhƒX, rÚ…rÛ}rÜ(haX, hbj´ubj_)rÝ}rÞ(haXH`dut\_3\_log,txt `_hn}rß(UnamehjvX3http://processors.wiki.ti.com/images/0/08/Dut_3.pdfràhs]hr]hp]hq]hv]uhbj´hz]ráhƒX dut_3_log,txtrâ…rã}rä(haUhbjÝubahljhubj®)rå}ræ(haX6 h˜Khbj´hlj±hn}rç(Urefurijàhs]rèU dut-3-log-txtréahr]hp]hq]hv]rêhauhz]ubhƒX for more detail.rë…rì}rí(haX for more detail.hbj´ubeubaubeubh§)rî}rï(haX.**Remark:** When enabling the ICSS2 PPS, the ptpX entry associated with ICSS2 on DUT-2 and DUT-3 may be different on different setups. Run the script `ptpinfo.sh `_ to find out the correct ptpX entry that is associated with ICSS2 on each platform.hbjnhjhŒhlh«hn}rð(hp]hq]hr]hs]hv]uhxMhyhhz]rñ(j)rò}ró(haX **Remark:**hn}rô(hp]hq]hr]hs]hv]uhbjîhz]rõhƒXRemark:rö…r÷}rø(haUhbjòubahlj‡ubhƒX‹ When enabling the ICSS2 PPS, the ptpX entry associated with ICSS2 on DUT-2 and DUT-3 may be different on different setups. Run the script rù…rú}rû(haX‹ When enabling the ICSS2 PPS, the ptpX entry associated with ICSS2 on DUT-2 and DUT-3 may be different on different setups. Run the script hbjîubj_)rü}rý(haXE`ptpinfo.sh `_hn}rþ(Unameh>jvX5http://processors.wiki.ti.com/images/2/24/Ptpinfo.pdfrÿhs]hr]hp]hq]hv]uhbjîhz]rhƒX ptpinfo.shr…r}r(haUhbjüubahljhubj®)r}r(haX8 h˜Khbjîhlj±hn}r(Urefurijÿhs]rU ptpinfo-shrahr]hp]hq]hv]r h>auhz]ubhƒXS to find out the correct ptpX entry that is associated with ICSS2 on each platform.r …r }r (haXS to find out the correct ptpX entry that is associated with ICSS2 on each platform.hbjîubeubh§)r }r(haXtFrom the sample display of the ptpinfo.sh script below, the ptpX entry associated with ICSS2 (PRUSS2 timer) is ptp1.rhbjnhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxM$hyhhz]rhƒXtFrom the sample display of the ptpinfo.sh script below, the ptpX entry associated with ICSS2 (PRUSS2 timer) is ptp1.r…r}r(hajhbj ubaubj9)r}r(haX:root@am57xx-evm:~# ./ptpinfo.sh ls /sys/devices/platform/44000000.ocp/48484000.ethernet/net/ eth0 eth1 ls /sys/devices/platform/pruss2_eth/net eth2 eth3 lrwxrwxrwx 1 root root 0 Apr 20 19:11 ptp0 -> ../../devices/platform/44000000.ocp/48484000.ethernet/ptp/ptp0 lrwxrwxrwx 1 root root 0 Apr 21 21:18 ptp1 -> ../../devices/platform/pruss2_eth/ptp/ptp1 ptp clock names: /sys/class/ptp/ptp0 : CTPS timer /sys/class/ptp/ptp1 : PRUSS2 timer pps's ptp device: /sys/class/pps/pps0 : ptp0 /sys/class/pps/pps1 : ptp1 root@am57xx-evm:~#hbjnhjhŒhlj<hn}r(hh‘hs]hr]hp]hq]hv]uhxM.hyhhz]rhƒX:root@am57xx-evm:~# ./ptpinfo.sh ls /sys/devices/platform/44000000.ocp/48484000.ethernet/net/ eth0 eth1 ls /sys/devices/platform/pruss2_eth/net eth2 eth3 lrwxrwxrwx 1 root root 0 Apr 20 19:11 ptp0 -> ../../devices/platform/44000000.ocp/48484000.ethernet/ptp/ptp0 lrwxrwxrwx 1 root root 0 Apr 21 21:18 ptp1 -> ../../devices/platform/pruss2_eth/ptp/ptp1 ptp clock names: /sys/class/ptp/ptp0 : CTPS timer /sys/class/ptp/ptp1 : PRUSS2 timer pps's ptp device: /sys/class/pps/pps0 : ptp0 /sys/class/pps/pps1 : ptp1 root@am57xx-evm:~#r…r}r(haUhbjubaubeubeubhc)r}r(haUh˜KhbjhjhŒhlhmhn}r(hp]rX=test 2. without a hybrid clock between master and slave clockr ahq]hr]hs]r!Uhs]hr]hp]hq]jÀ}r?U*j>shv]uhxM?hyhhz]ubeubhc)r@}rA(haUh˜KhbjhjhŒhlhmhn}rB(hp]rCjrahq]hr]hs]rDUid15rEahv]uhxMAhyhhz]rF(h|)rG}rH(haX ProcedurerIhbj@hjhŒhlh€hn}rJ(hp]hq]hr]hs]hv]uhxMAhyhhz]rKhƒX ProcedurerL…rM}rN(hajIhbjGubaubh¹)rO}rP(haUhbj@hjhŒhlh¼hn}rQ(h¾X-hs]hr]hp]hq]hv]uhxMChyhhz]rR(hÀ)rS}rT(haX Remove DUT-1 (role: transparent clock) from the 3 clock test `setup <#A_Sample_3_HSR_Hybrid_Clock_Setup>`_ above and connect only port DUT-2-A to port DUT-3-A. hbjOhjhŒhlhÃhn}rU(hp]hq]hr]hs]hv]uhxNhyhhz]rVh§)rW}rX(haXŸRemove DUT-1 (role: transparent clock) from the 3 clock test `setup <#A_Sample_3_HSR_Hybrid_Clock_Setup>`_ above and connect only port DUT-2-A to port DUT-3-A.hbjShjhŒhlh«hn}rY(hp]hq]hr]hs]hv]uhxMChz]rZ(hƒX=Remove DUT-1 (role: transparent clock) from the 3 clock test r[…r\}r](haX=Remove DUT-1 (role: transparent clock) from the 3 clock test hbjWubj_)r^}r_(haX-`setup <#A_Sample_3_HSR_Hybrid_Clock_Setup>`_hn}r`(UnamehLjvX"#A_Sample_3_HSR_Hybrid_Clock_Setuprahs]hr]hp]hq]hv]uhbjWhz]rbhƒXsetuprc…rd}re(haUhbj^ubahljhubj®)rf}rg(haX% <#A_Sample_3_HSR_Hybrid_Clock_Setup>h˜KhbjWhlj±hn}rh(Urefurijahs]riUsetuprjahr]hp]hq]hv]rkhLauhz]ubhƒX5 above and connect only port DUT-2-A to port DUT-3-A.rl…rm}rn(haX5 above and connect only port DUT-2-A to port DUT-3-A.hbjWubeubaubhÀ)ro}rp(haX.Repeat Test 1 steps but skip those for DUT-1. hbjOhjhŒhlhÃhn}rq(hp]hq]hr]hs]hv]uhxNhyhhz]rrh§)rs}rt(haX-Repeat Test 1 steps but skip those for DUT-1.ruhbjohjhŒhlh«hn}rv(hp]hq]hr]hs]hv]uhxMGhz]rwhƒX-Repeat Test 1 steps but skip those for DUT-1.rx…ry}rz(hajuhbjsubaubaubhÀ)r{}r|(haXMeasure PPS jitter. hbjOhjhŒhlhÃhn}r}(hp]hq]hr]hs]hv]uhxNhyhhz]r~h§)r}r€(haXMeasure PPS jitter.rhbj{hjhŒhlh«hn}r‚(hp]hq]hr]hs]hv]uhxMIhz]rƒhƒXMeasure PPS jitter.r„…r…}r†(hajhbjubaubaubeubeubeubeubhc)r‡}rˆ(haUh˜KhbjˆhjhŒhlhmhn}r‰(hp]rŠX test resultsr‹ahq]hr]hs]rŒUid16rahv]uhxMLhyhhz]rŽ(h|)r}r(haX Test Resultsr‘hbj‡hjhŒhlh€hn}r’(hp]hq]hr]hs]hv]uhxMLhyhhz]r“hƒX Test Resultsr”…r•}r–(haj‘hbjubaubhc)r—}r˜(haUh˜Khbj‡hjhŒhlhmhn}r™(hp]ršj1ahq]hr]hs]r›Uid17rœahv]uhxMOhyhhz]r(h|)rž}rŸ(haXBTest 1. With a hybrid clock (OC+TC) between master and slave clockr hbj—hjhŒhlh€hn}r¡(hp]hq]hr]hs]hv]uhxMOhyhhz]r¢hƒXBTest 1. With a hybrid clock (OC+TC) between master and slave clockr£…r¤}r¥(haj hbjžubaubjº)r¦}r§(haX&.. Image:: ../images/Hsr_pps_w_tc.png hbj—hjhŒhlj½hn}r¨(UuriX linux/../images/Hsr_pps_w_tc.pngr©hs]hr]hp]hq]jÀ}rªU*j©shv]uhxMRhyhhz]ubeubhc)r«}r¬(haUh˜Khbj‡hjhŒhlhmhn}r­(hp]r®j ahq]hr]hs]r¯Uid18r°ahv]uhxMThyhhz]r±(h|)r²}r³(haX=Test 2. Without a hybrid clock between Master and Slave Clockr´hbj«hjhŒhlh€hn}rµ(hp]hq]hr]hs]hv]uhxMThyhhz]r¶hƒX=Test 2. Without a hybrid clock between Master and Slave Clockr·…r¸}r¹(haj´hbj²ubaubjº)rº}r»(haX'.. Image:: ../images/Hsr_pps_wo_tc.png hbj«hjhŒhlj½hn}r¼(UuriX!linux/../images/Hsr_pps_wo_tc.pngr½hs]hr]hp]hq]jÀ}r¾U*j½shv]uhxMWhyhhz]ubeubeubhc)r¿}rÀ(haUh˜KhbjˆhjhŒhlhmhn}rÁ(hp]rÂX limitationsrÃahq]hr]hs]rÄUid19rÅahv]uhxMYhyhhz]rÆ(h|)rÇ}rÈ(haX LimitationsrÉhbj¿hjhŒhlh€hn}rÊ(hp]hq]hr]hs]hv]uhxMYhyhhz]rËhƒX LimitationsrÌ…rÍ}rÎ(hajÉhbjÇubaubh§)rÏ}rÐ(haXMThe current implementation of HSR PTP OC and TC has the following limitationsrÑhbj¿hjhŒhlh«hn}rÒ(hp]hq]hr]hs]hv]uhxM[hyhhz]rÓhƒXMThe current implementation of HSR PTP OC and TC has the following limitationsrÔ…rÕ}rÖ(hajÑhbjÏubaubh¹)r×}rØ(haUhbj¿hjhŒhlh¼hn}rÙ(h¾X-hs]hr]hp]hq]hv]uhxM^hyhhz]rÚ(hÀ)rÛ}rÜ(haXDOnly HSR hybrid clock is supported. Standalone TC is not supported. hbj×hjhŒhlhÃhn}rÝ(hp]hq]hr]hs]hv]uhxNhyhhz]rÞh§)rß}rà(haXCOnly HSR hybrid clock is supported. Standalone TC is not supported.ráhbjÛhjhŒhlh«hn}râ(hp]hq]hr]hs]hv]uhxM^hz]rãhƒXCOnly HSR hybrid clock is supported. Standalone TC is not supported.rä…rå}ræ(hajáhbjßubaubaubhÀ)rç}rè(haX Only 2-step clock is supported. hbj×hjhŒhlhÃhn}ré(hp]hq]hr]hs]hv]uhxNhyhhz]rêh§)rë}rì(haXOnly 2-step clock is supported.ríhbjçhjhŒhlh«hn}rî(hp]hq]hr]hs]hv]uhxM`hz]rïhƒXOnly 2-step clock is supported.rð…rñ}rò(hajíhbjëubaubaubhÀ)ró}rô(haX(BMCA enhanced for HSR is not supported. hbj×hjhŒhlhÃhn}rõ(hp]hq]hr]hs]hv]uhxNhyhhz]röh§)r÷}rø(haX'BMCA enhanced for HSR is not supported.rùhbjóhjhŒhlh«hn}rú(hp]hq]hr]hs]hv]uhxMbhz]rûhƒX'BMCA enhanced for HSR is not supported.rü…rý}rþ(hajùhbj÷ubaubaubhÀ)rÿ}r(haX§The two slave ports of an HSR interface is assumed to have the same characteristics such as the linuxptp egressLatency and ingressLatency configurations are the same. hbj×hjhŒhlhÃhn}r(hp]hq]hr]hs]hv]uhxNhyhhz]rh§)r}r(haX¦The two slave ports of an HSR interface is assumed to have the same characteristics such as the linuxptp egressLatency and ingressLatency configurations are the same.rhbjÿhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxMdhz]rhƒX¦The two slave ports of an HSR interface is assumed to have the same characteristics such as the linuxptp egressLatency and ingressLatency configurations are the same.r…r }r (hajhbjubaubaubeubeubhc)r }r (haUhbjˆhjhŒhlhmhn}r (hp]hq]hr]hs]rU known-issuesrahv]rh&auhxMihyhhz]rh|)r}r(haX Known Issuesrhbj hjhŒhlh€hn}r(hp]hq]hr]hs]hv]uhxMihyhhz]rhƒX Known Issuesr…r}r(hajhbjubaubaubeubhc)r}r(haUhbhhhjhŒhlhmhn}r(hp]hq]hr]hs]rU ptp-roadmaprahv]rhJauhxMlhyhhz]r (h|)r!}r"(haX PTP Roadmapr#hbjhjhŒhlh€hn}r$(hp]hq]hr]hs]hv]uhxMlhyhhz]r%hƒX PTP Roadmapr&…r'}r((haj#hbj!ubaubh§)r)}r*(haXNThe following features are not yet supported, but will be added in the future:r+hbjhjhŒhlh«hn}r,(hp]hq]hr]hs]hv]uhxMmhyhhz]r-hƒXNThe following features are not yet supported, but will be added in the future:r.…r/}r0(haj+hbj)ubaubeubeubhjhŒhlhmhn}r1(hp]hq]hr]hs]r2Ugenerating-1-ppsr3ahv]r4h auhxK¢hyhhz]r5(h|)r6}r7(haXGenerating 1 PPSr8hbhfhjhŒhlh€hn}r9(hp]hq]hr]hs]hv]uhxK¢hyhhz]r:hƒXGenerating 1 PPSr;…r<}r=(haj8hbj6ubaubh§)r>}r?(haX{The PPS (Pulse Per Second) or 1PPS signal is an electrical signal that has a width of less than one second and a sharply rising or abruptly falling edge at the second boundary. The PPS signal can be used to measure the offset and jitters of the system time between the master and slave clock. This signal can also be used to synchronize the slave clock to its master within a BC.r@hbhfhjhŒhlh«hn}rA(hp]hq]hr]hs]hv]uhxK¤hyhhz]rBhƒX{The PPS (Pulse Per Second) or 1PPS signal is an electrical signal that has a width of less than one second and a sharply rising or abruptly falling edge at the second boundary. The PPS signal can be used to measure the offset and jitters of the system time between the master and slave clock. This signal can also be used to synchronize the slave clock to its master within a BC.rC…rD}rE(haj@hbj>ubaubhdhc)rF}rG(haUhbhfhjhŒhlhmhn}rH(hp]hq]hr]hs]rIU pru-icss-ieprJahv]rKh*auhxKÏhyhhz]rL(h|)rM}rN(haX PRU-ICSS IEPrOhbjFhjhŒhlh€hn}rP(hp]hq]hr]hs]hv]uhxKÏhyhhz]rQhƒX PRU-ICSS IEPrR…rS}rT(hajOhbjMubaubh§)rU}rV(haXÍIEP has an additional hardware to generate a programmable sync output which is tied to the IEP counter. This is called the SYNC unit. For this signal generation CMP1 is programmed to a value of 1 second. A HIT event is generated by PRU0. Linux PRUETH IEP driver checks this event in and re-programs CMP1 after every hit to ensure that accurate sync pulses are generated. This sync is equivalent to the 1PPS output and should not be confused with PTP Sync frame.rWhbjFhjhŒhlh«hn}rX(hp]hq]hr]hs]hv]uhxKÑhyhhz]rYhƒXÍIEP has an additional hardware to generate a programmable sync output which is tied to the IEP counter. This is called the SYNC unit. For this signal generation CMP1 is programmed to a value of 1 second. A HIT event is generated by PRU0. Linux PRUETH IEP driver checks this event in and re-programs CMP1 after every hit to ensure that accurate sync pulses are generated. This sync is equivalent to the 1PPS output and should not be confused with PTP Sync frame.rZ…r[}r\(hajWhbjUubaubh§)r]}r^(haXYTo enable/disable 1PPS signal on PRU-ICSS port, enter the following commands respectivelyr_hbjFhjhŒhlh«hn}r`(hp]hq]hr]hs]hv]uhxKÙhyhhz]rahƒXYTo enable/disable 1PPS signal on PRU-ICSS port, enter the following commands respectivelyrb…rc}rd(haj_hbj]ubaubj9)re}rf(haXúecho 1 > /sys/devices/platform/pruss2_eth/ptp/ptp1/pps_enable echo 0 > /sys/devices/platform/pruss2_eth/ptp/ptp1/pps_enable or echo 1 > /sys/devices/platform/pruss2_eth/ptp/ptp2/pps_enable echo 0 > /sys/devices/platform/pruss2_eth/ptp/ptp2/pps_enablehbjFhjhŒhlj<hn}rg(hh‘hs]hr]hp]hq]hv]uhxKãhyhhz]rhhƒXúecho 1 > /sys/devices/platform/pruss2_eth/ptp/ptp1/pps_enable echo 0 > /sys/devices/platform/pruss2_eth/ptp/ptp1/pps_enable or echo 1 > /sys/devices/platform/pruss2_eth/ptp/ptp2/pps_enable echo 0 > /sys/devices/platform/pruss2_eth/ptp/ptp2/pps_enableri…rj}rk(haUhbjeubaubj9)rl}rm(haXúecho 1 > /sys/devices/platform/pruss1_eth/ptp/ptp2/pps_enable echo 0 > /sys/devices/platform/pruss1_eth/ptp/ptp2/pps_enable or echo 1 > /sys/devices/platform/pruss1_eth/ptp/ptp1/pps_enable echo 0 > /sys/devices/platform/pruss1_eth/ptp/ptp1/pps_enablehbjFhjhŒhlj<hn}rn(hh‘hs]hr]hp]hq]hv]uhxKëhyhhz]rohƒXúecho 1 > /sys/devices/platform/pruss1_eth/ptp/ptp2/pps_enable echo 0 > /sys/devices/platform/pruss1_eth/ptp/ptp2/pps_enable or echo 1 > /sys/devices/platform/pruss1_eth/ptp/ptp1/pps_enable echo 0 > /sys/devices/platform/pruss1_eth/ptp/ptp1/pps_enablerp…rq}rr(haUhbjlubaubh§)rs}rt(haXžPlease note that both ptp1/2 may be assigned to pruss1(2)\_eth based on the order of operations. Use the following command to find out the assigned PTP ports.hbjFhjhŒhlh«hn}ru(hp]hq]hr]hs]hv]uhxKìhyhhz]rvhƒXPlease note that both ptp1/2 may be assigned to pruss1(2)_eth based on the order of operations. Use the following command to find out the assigned PTP ports.rw…rx}ry(haXžPlease note that both ptp1/2 may be assigned to pruss1(2)\_eth based on the order of operations. Use the following command to find out the assigned PTP ports.hbjsubaubj9)rz}r{(haXOls /sys/devices/platform/pruss1_eth/ptp ls /sys/devices/platform/pruss2_eth/ptphbjFhjhŒhlj<hn}r|(hh‘hs]hr]hp]hq]hv]uhxK÷hyhhz]r}hƒXOls /sys/devices/platform/pruss1_eth/ptp ls /sys/devices/platform/pruss2_eth/ptpr~…r}r€(haUhbjzubaubj`)r}r‚(haXÈKnown Issue: On AM335x/AM437x, the current PPS implementation has the possibility of failing to correctly synchronize PPS output to a master (only the PPS output is affected, the PTP functionality still succeeds). This appears as the slave PPS being offset from the master PPS signal on an order of 40-100ms either on starting PPS or after running for an extended period of time. As a workaround, if PPS output is observed to be offset, then to temporarily stabilize PPS output for measurement, bring down and then bring back up the ethernet interface in use to reset PTP/PPS (e.g. ifconfig eth1 down/ifconfig eth1 up). If the PPS output is successful, then the output is valid and can be used to measure jitter.hbjFhjhŒhljdhn}rƒ(hp]hq]hr]hs]hv]uhxNhyhhz]r„h§)r…}r†(haXÈKnown Issue: On AM335x/AM437x, the current PPS implementation has the possibility of failing to correctly synchronize PPS output to a master (only the PPS output is affected, the PTP functionality still succeeds). This appears as the slave PPS being offset from the master PPS signal on an order of 40-100ms either on starting PPS or after running for an extended period of time. As a workaround, if PPS output is observed to be offset, then to temporarily stabilize PPS output for measurement, bring down and then bring back up the ethernet interface in use to reset PTP/PPS (e.g. ifconfig eth1 down/ifconfig eth1 up). If the PPS output is successful, then the output is valid and can be used to measure jitter.r‡hbjhjhŒhlh«hn}rˆ(hp]hq]hr]hs]hv]uhxKöhz]r‰hƒXÈKnown Issue: On AM335x/AM437x, the current PPS implementation has the possibility of failing to correctly synchronize PPS output to a master (only the PPS output is affected, the PTP functionality still succeeds). This appears as the slave PPS being offset from the master PPS signal on an order of 40-100ms either on starting PPS or after running for an extended period of time. As a workaround, if PPS output is observed to be offset, then to temporarily stabilize PPS output for measurement, bring down and then bring back up the ethernet interface in use to reset PTP/PPS (e.g. ifconfig eth1 down/ifconfig eth1 up). If the PPS output is successful, then the output is valid and can be used to measure jitter.rŠ…r‹}rŒ(haj‡hbj…ubaubaubeubhc)r}rŽ(haUh˜KhbhfhjhŒhlhmhn}r(hp]rj`ahq]hr]hs]r‘Uid1r’ahv]uhxMhyhhz]r“(h|)r”}r•(haXGMACr–hbjhjhŒhlh€hn}r—(hp]hq]hr]hs]hv]uhxMhyhhz]r˜hƒXGMACr™…rš}r›(haj–hbj”ubaubh§)rœ}r(haXóThe GMAC/CPTS does not support a programmable sync output. Instead, the GP Timer16 can be programmed to generate an output pulse every 100ms or second and then this signal is passed to CPTS/HW\_TS\_PUSH4 to trigger the HW\_TS\_PUSH event. Linux CPSW/CPTS driver checks this event in and run through a simple algorithm to adjust the GP Timer reload value after every hit to ensure that output sync pulse is aligned at the second boundary of the PTP system time. In order to satisfy the +/-50ns jitter requirement by reducing the accumulation error, the current 1PPS implementation will generate a output pulse every 100ms and 9 out of 10 pulses will be filtered out except the one at the second boundary through the pad-config or GPIO-based output control.hbjhjhŒhlh«hn}rž(hp]hq]hr]hs]hv]uhxMhyhhz]rŸhƒXïThe GMAC/CPTS does not support a programmable sync output. Instead, the GP Timer16 can be programmed to generate an output pulse every 100ms or second and then this signal is passed to CPTS/HW_TS_PUSH4 to trigger the HW_TS_PUSH event. Linux CPSW/CPTS driver checks this event in and run through a simple algorithm to adjust the GP Timer reload value after every hit to ensure that output sync pulse is aligned at the second boundary of the PTP system time. In order to satisfy the +/-50ns jitter requirement by reducing the accumulation error, the current 1PPS implementation will generate a output pulse every 100ms and 9 out of 10 pulses will be filtered out except the one at the second boundary through the pad-config or GPIO-based output control.r …r¡}r¢(haXóThe GMAC/CPTS does not support a programmable sync output. Instead, the GP Timer16 can be programmed to generate an output pulse every 100ms or second and then this signal is passed to CPTS/HW\_TS\_PUSH4 to trigger the HW\_TS\_PUSH event. Linux CPSW/CPTS driver checks this event in and run through a simple algorithm to adjust the GP Timer reload value after every hit to ensure that output sync pulse is aligned at the second boundary of the PTP system time. In order to satisfy the +/-50ns jitter requirement by reducing the accumulation error, the current 1PPS implementation will generate a output pulse every 100ms and 9 out of 10 pulses will be filtered out except the one at the second boundary through the pad-config or GPIO-based output control.hbjœubaubh§)r£}r¤(haXUTo enable/disable 1PPS signal on GMAC/CPTS, enter the following command respectively:r¥hbjhjhŒhlh«hn}r¦(hp]hq]hr]hs]hv]uhxMhyhhz]r§hƒXUTo enable/disable 1PPS signal on GMAC/CPTS, enter the following command respectively:r¨…r©}rª(haj¥hbj£ubaubj9)r«}r¬(haX£echo 1 > /sys/devices/platform/44000000.ocp/48484000.ethernet/ptp/ptp0/pps_enable echo 0 > /sys/devices/platform/44000000.ocp/48484000.ethernet/ptp/ptp0/pps_enablehbjhjhŒhlj<hn}r­(hh‘hs]hr]hp]hq]hv]uhxMhyhhz]r®hƒX£echo 1 > /sys/devices/platform/44000000.ocp/48484000.ethernet/ptp/ptp0/pps_enable echo 0 > /sys/devices/platform/44000000.ocp/48484000.ethernet/ptp/ptp0/pps_enabler¯…r°}r±(haUhbj«ubaubeubjeubhjhŒhlhmhn}r²(hp]hq]hr]hs]r³Udevice-tree-setupr´ahv]rµhNauhxK¬hyhhz]r¶(h|)r·}r¸(haXDevice Tree Setupr¹hbhdhjhŒhlh€hn}rº(hp]hq]hr]hs]hv]uhxK¬hyhhz]r»hƒXDevice Tree Setupr¼…r½}r¾(haj¹hbj·ubaubh§)r¿}rÀ(haX}To enable PPS the device needs to first be booted using a different device tree file to enable the PPS pins, as listed below:rÁhbhdhjhŒhlh«hn}rÂ(hp]hq]hr]hs]hv]uhxK®hyhhz]rÃhƒX}To enable PPS the device needs to first be booted using a different device tree file to enable the PPS pins, as listed below:rÄ…rÅ}rÆ(hajÁhbj¿ubaubjÊ)rÇ}rÈ(haUhbhdhjhŒhljÍhn}rÉ(hp]hq]hr]hs]hv]uhxNhyhhz]rÊjÐ)rË}rÌ(haUhn}rÍ(hs]hr]hp]hq]hv]UcolsKuhbjÇhz]rÎ(jÕ)rÏ}rÐ(haUhn}rÑ(hs]hr]hp]hq]hv]UcolwidthKuhbjËhz]hljÙubjÕ)rÒ}rÓ(haUhn}rÔ(hs]hr]hp]hq]hv]UcolwidthKuhbjËhz]hljÙubjã)rÕ}rÖ(haUhn}r×(hp]hq]hr]hs]hv]uhbjËhz]rØjè)rÙ}rÚ(haUhn}rÛ(hp]hq]hr]hs]hv]uhbjÕhz]rÜ(jí)rÝ}rÞ(haUhn}rß(hp]hq]hr]hs]hv]uhbjÙhz]ràh§)rá}râ(haXSoCrãhbjÝhjhŒhlh«hn}rä(hp]hq]hr]hs]hv]uhxK²hz]råhƒXSoCræ…rç}rè(hajãhbjáubaubahljúubjí)ré}rê(haUhn}rë(hp]hq]hr]hs]hv]uhbjÙhz]rìh§)rí}rî(haXDevice Tree File (\*.dtb)hbjéhjhŒhlh«hn}rï(hp]hq]hr]hs]hv]uhxK²hz]rðhƒXDevice Tree File (*.dtb)rñ…rò}ró(haXDevice Tree File (\*.dtb)hbjíubaubahljúubehljubahlj ubj!)rô}rõ(haUhn}rö(hp]hq]hr]hs]hv]uhbjËhz]r÷(jè)rø}rù(haUhn}rú(hp]hq]hr]hs]hv]uhbjôhz]rû(jí)rü}rý(haUhn}rþ(hp]hq]hr]hs]hv]uhbjøhz]rÿh§)r}r(haXAM335xrhbjühjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxK´hz]rhƒXAM335xr…r}r(hajhbjubaubahljúubjí)r}r (haUhn}r (hp]hq]hr]hs]hv]uhbjøhz]r h§)r }r (haXam335x-icev2-prueth-pps.dtbrhbjhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxK´hz]rhƒXam335x-icev2-prueth-pps.dtbr…r}r(hajhbj ubaubahljúubehljubjè)r}r(haUhn}r(hp]hq]hr]hs]hv]uhbjôhz]r(jí)r}r(haUhn}r(hp]hq]hr]hs]hv]uhbjhz]rh§)r}r(haXAM437xrhbjhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxK¶hz]r hƒXAM437xr!…r"}r#(hajhbjubaubahljúubjí)r$}r%(haUhn}r&(hp]hq]hr]hs]hv]uhbjhz]r'h§)r(}r)(haXam437x-idk-pps.dtbr*hbj$hjhŒhlh«hn}r+(hp]hq]hr]hs]hv]uhxK¶hz]r,hƒXam437x-idk-pps.dtbr-…r.}r/(haj*hbj(ubaubahljúubehljubjè)r0}r1(haUhn}r2(hp]hq]hr]hs]hv]uhbjôhz]r3(jí)r4}r5(haUhn}r6(hp]hq]hr]hs]hv]uhbj0hz]r7h§)r8}r9(haXAM571xr:hbj4hjhŒhlh«hn}r;(hp]hq]hr]hs]hv]uhxK¸hz]r<hƒXAM571xr=…r>}r?(haj:hbj8ubaubahljúubjí)r@}rA(haUhn}rB(hp]hq]hr]hs]hv]uhbj0hz]rCh§)rD}rE(haXam571x-idk-pps.dtbrFhbj@hjhŒhlh«hn}rG(hp]hq]hr]hs]hv]uhxK¸hz]rHhƒXam571x-idk-pps.dtbrI…rJ}rK(hajFhbjDubaubahljúubehljubjè)rL}rM(haUhn}rN(hp]hq]hr]hs]hv]uhbjôhz]rO(jí)rP}rQ(haUhn}rR(hp]hq]hr]hs]hv]uhbjLhz]rSh§)rT}rU(haXAM572xrVhbjPhjhŒhlh«hn}rW(hp]hq]hr]hs]hv]uhxKºhz]rXhƒXAM572xrY…rZ}r[(hajVhbjTubaubahljúubjí)r\}r](haUhn}r^(hp]hq]hr]hs]hv]uhbjLhz]r_h§)r`}ra(haXam572x-idk-pps.dtbrbhbj\hjhŒhlh«hn}rc(hp]hq]hr]hs]hv]uhxKºhz]rdhƒXam572x-idk-pps.dtbre…rf}rg(hajbhbj`ubaubahljúubehljubjè)rh}ri(haUhn}rj(hp]hq]hr]hs]hv]uhbjôhz]rk(jí)rl}rm(haUhn}rn(hp]hq]hr]hs]hv]uhbjhhz]roh§)rp}rq(haXAM574xrrhbjlhjhŒhlh«hn}rs(hp]hq]hr]hs]hv]uhxK¼hz]rthƒXAM574xru…rv}rw(hajrhbjpubaubahljúubjí)rx}ry(haUhn}rz(hp]hq]hr]hs]hv]uhbjhhz]r{h§)r|}r}(haXam574x-idk-pps.dtbr~hbjxhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxK¼hz]r€hƒXam574x-idk-pps.dtbr…r‚}rƒ(haj~hbj|ubaubahljúubehljubjè)r„}r…(haUhn}r†(hp]hq]hr]hs]hv]uhbjôhz]r‡(jí)rˆ}r‰(haUhn}rŠ(hp]hq]hr]hs]hv]uhbj„hz]r‹h§)rŒ}r(haXK2GrŽhbjˆhjhŒhlh«hn}r(hp]hq]hr]hs]hv]uhxK¾hz]rhƒXK2Gr‘…r’}r“(hajŽhbjŒubaubahljúubjí)r”}r•(haUhn}r–(hp]hq]hr]hs]hv]uhbj„hz]r—h§)r˜}r™(haXkeystone-k2g-ice-pps.dtbršhbj”hjhŒhlh«hn}r›(hp]hq]hr]hs]hv]uhxK¾hz]rœhƒXkeystone-k2g-ice-pps.dtbr…rž}rŸ(hajšhbj˜ubaubahljúubehljubehljRubehljSubaubh§)r }r¡(haXÁTo configure this, change the device tree loaded in Uboot. If using the default Uboot environment, you can make the following changes to force the device to boot using the PPS device tree file.r¢hbhdhjhŒhlh«hn}r£(hp]hq]hr]hs]hv]uhxKÁhyhhz]r¤hƒXÁTo configure this, change the device tree loaded in Uboot. If using the default Uboot environment, you can make the following changes to force the device to boot using the PPS device tree file.r¥…r¦}r§(haj¢hbj ubaubh§)r¨}r©(haX‘1. Disable the automatic device tree file selection. Remove 'run findfdt;' from the relevant boot command (e.g. 'bootcmd', mmcboot' or 'netboot')rªhbhdhjhŒhlh«hn}r«(hp]hq]hr]hs]hv]uhxKÅhyhhz]r¬hƒX‘1. Disable the automatic device tree file selection. Remove 'run findfdt;' from the relevant boot command (e.g. 'bootcmd', mmcboot' or 'netboot')r­…r®}r¯(hajªhbj¨ubaubh§)r°}r±(haX*2. Set the device tree file to be used. ::hbhdhjhŒhlh«hn}r²(hp]hq]hr]hs]hv]uhxKÈhyhhz]r³hƒX'2. Set the device tree file to be used.r´…rµ}r¶(haX'2. Set the device tree file to be used.hbj°ubaubj9)r·}r¸(haXsetenv fdtfile hbhdhjhŒhlj<hn}r¹(hh‘hs]hr]hp]hq]hv]uhxKÐhyhhz]rºhƒXsetenv fdtfile r»…r¼}r½(haUhbj·ubaubeubhjhŒhlUsystem_messager¾hn}r¿(hp]UlevelKhs]hr]UsourcehŒhq]hv]UlineKÉUtypeUINFOrÀuhxKÉhyhhz]rÁh§)rÂ}rÃ(haXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.hn}rÄ(hp]hq]hr]hs]hv]uhbh_hz]rÅhƒXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rÆ…rÇ}rÈ(haUhbjÂubahlh«ubaubh^)rÉ}rÊ(haUhbjhjhŒhlj¾hn}rË(hp]UlevelKhs]hr]rÌj’aUsourcehŒhq]hv]UlineMUtypejÀuhxMhyhhz]rÍh§)rÎ}rÏ(haX'Duplicate implicit target name: "gmac".hn}rÐ(hp]hq]hr]hs]hv]uhbjÉhz]rÑhƒX'Duplicate implicit target name: "gmac".rÒ…rÓ}rÔ(haUhbjÎubahlh«ubaubh^)rÕ}rÖ(haUhbj€hjhŒhlj¾hn}r×(hp]UlevelKhs]hr]UsourcehŒhq]hv]UlineMåUtypejÀuhxMåhyhhz]rØh§)rÙ}rÚ(haXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.hn}rÛ(hp]hq]hr]hs]hv]uhbjÕhz]rÜhƒXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rÝ…rÞ}rß(haUhbjÙubahlh«ubaubh^)rà}rá(haUhbj€hjhŒhlj¾hn}râ(hp]UlevelKhs]hr]UsourcehŒhq]hv]UlineMUtypejÀuhxMhyhhz]rãh§)rä}rå(haXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.hn}ræ(hp]hq]hr]hs]hv]uhbjàhz]rçhƒXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.rè…ré}rê(haUhbjäubahlh«ubaubh^)rë}rì(haUhbjÃhjhŒhlj¾hn}rí(hp]UlevelKhs]hr]UsourcehŒhq]hv]UlineM]UtypejÀuhxM]hyhhz]rîh§)rï}rð(haXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.hn}rñ(hp]hq]hr]hs]hv]uhbjëhz]ròhƒXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.ró…rô}rõ(haUhbjïubahlh«ubaubh^)rö}r÷(haUhbjÂhjhŒhlj¾hn}rø(hp]UlevelKhs]hr]rùjÇaUsourcehŒhq]hv]UlineM]UtypejÀuhxM]hyhhz]rúh§)rû}rü(haXHDuplicate implicit target name: "phy delay compensation for am57xx idk".hn}rý(hp]hq]hr]hs]hv]uhbjöhz]rþhƒXHDuplicate implicit target name: "phy delay compensation for am57xx idk".rÿ…r}r(haUhbjûubahlh«ubaubh^)r}r(haUhbj9 hjhŒhlj¾hn}r(hp]UlevelKhs]hr]rj> aUsourcehŒhq]hv]UlineMúUtypejÀuhxMúhyhhz]rh§)r}r(haX4Duplicate implicit target name: "software overview".hn}r (hp]hq]hr]hs]hv]uhbjhz]r hƒX4Duplicate implicit target name: "software overview".r …r }r (haUhbjubahlh«ubaubh^)r}r(haUhbj hjhŒhlj¾hn}r(hp]UlevelKhs]hr]rj aUsourcehŒhq]hv]UlineMVUtypejÀuhxMVhyhhz]rh§)r}r(haX4Duplicate implicit target name: "hardware overview".hn}r(hp]hq]hr]hs]hv]uhbjhz]rhƒX4Duplicate implicit target name: "hardware overview".r…r}r(haUhbjubahlh«ubaubh^)r}r(haUhbjàhjhŒhlj¾hn}r(hp]UlevelKhs]hr]UsourcehŒhq]hv]UlineM±UtypejÀuhxM±hyhhz]rh§)r}r(haXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.hn}r (hp]hq]hr]hs]hv]uhbjhz]r!hƒXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.r"…r#}r$(haUhbjubahlh«ubaubh^)r%}r&(haUhbjàhjhŒhlj¾hn}r'(hp]UlevelKhs]hr]UsourcehŒhq]hv]UlineMéUtypejÀuhxMéhyhhz]r(h§)r)}r*(haXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.hn}r+(hp]hq]hr]hs]hv]uhbj%hz]r,hƒXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.r-…r.}r/(haUhbj)ubahlh«ubaubh^)r0}r1(haUhbjàhjhŒhlj¾hn}r2(hp]UlevelKhs]hr]UsourcehŒhq]hv]UlineM>UtypejÀuhxM>hyhhz]r3h§)r4}r5(haXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.hn}r6(hp]hq]hr]hs]hv]uhbj0hz]r7hƒXfPossible title underline, too short for the title. Treating it as ordinary text because it's so short.r8…r9}r:(haUhbj4ubahlh«ubaubh^)r;}r<(haUhbjLhjhŒhlj¾hn}r=(hp]UlevelKhs]hr]r>jQaUsourcehŒhq]hv]UlineMÙUtypejÀuhxMÙhyhhz]r?h§)r@}rA(haX/Duplicate implicit target name: "test results".hn}rB(hp]hq]hr]hs]hv]uhbj;hz]rChƒX/Duplicate implicit target name: "test results".rD…rE}rF(haUhbj@ubahlh«ubaubh^)rG}rH(haUhbjBhjhŒhlj¾hn}rI(hp]UlevelKhs]hr]rJjGaUsourcehŒhq]hv]UlineMUtypejÀuhxMhyhhz]rKh§)rL}rM(haX.Duplicate implicit target name: "limitations".hn}rN(hp]hq]hr]hs]hv]uhbjGhz]rOhƒX.Duplicate implicit target name: "limitations".rP…rQ}rR(haUhbjLubahlh«ubaubh^)rS}rT(haUhbj—hjhŒhlj¾hn}rU(hp]UlevelKhs]hr]rVjœaUsourcehŒhq]hv]UlineM5UtypejÀuhxM5hyhhz]rWh§)rX}rY(haX+Duplicate implicit target name: "overview".hn}rZ(hp]hq]hr]hs]hv]uhbjShz]r[hƒX+Duplicate implicit target name: "overview".r\…r]}r^(haUhbjXubahlh«ubaubh^)r_}r`(haUhbjÍhjhŒhlj¾hn}ra(hp]UlevelKhs]hr]rbjÒaUsourcehŒhq]hv]UlineMPUtypejÀuhxMPhyhhz]rch§)rd}re(haX+Duplicate implicit target name: "hardware".hn}rf(hp]hq]hr]hs]hv]uhbj_hz]rghƒX+Duplicate implicit target name: "hardware".rh…ri}rj(haUhbjdubahlh«ubaubh^)rk}rl(haUhbjähjhŒhlj¾hn}rm(hp]UlevelKhs]hr]rnjéaUsourcehŒhq]hv]UlineMVUtypejÀuhxMVhyhhz]roh§)rp}rq(haX+Duplicate implicit target name: "software".hn}rr(hp]hq]hr]hs]hv]uhbjkhz]rshƒX+Duplicate implicit target name: "software".rt…ru}rv(haUhbjpubahlh«ubaubh^)rw}rx(haUhbjhjhŒhlj¾hn}ry(hp]UlevelKhs]hr]rzj“aUsourcehŒhq]hv]UlineMŽUtypejÀuhxMŽhyhhz]r{h§)r|}r}(haX+Duplicate implicit target name: "software".hn}r~(hp]hq]hr]hs]hv]uhbjwhz]rhƒX+Duplicate implicit target name: "software".r€…r}r‚(haUhbj|ubahlh«ubaubh^)rƒ}r„(haUhbjhjhŒhlj¾hn}r…(hp]UlevelKhs]hr]r†j#aUsourcehŒhq]hv]UlineM¶UtypejÀuhxM¶hyhhz]r‡h§)rˆ}r‰(haX7Duplicate implicit target name: "test setup/procedure".hn}rŠ(hp]hq]hr]hs]hv]uhbjƒhz]r‹hƒX7Duplicate implicit target name: "test setup/procedure".rŒ…r}rŽ(haUhbjˆubahlh«ubaubh^)r}r(haUhn}r‘(hp]UlevelKhs]hr]r’jaUsourcehkhq]hv]UlineKUtypejÀuhbjéhz]r“h§)r”}r•(haX/Duplicate explicit target name: "setup_hsr.sh".hn}r–(hp]hq]hr]hs]hv]uhbjhz]r—hƒX/Duplicate explicit target name: "setup_hsr.sh".r˜…r™}rš(haUhbj”ubahlh«ubahlj¾ubh^)r›}rœ(haUhbj@hjhŒhlj¾hn}r(hp]UlevelKhs]hr]ržjEaUsourcehŒhq]hv]UlineMAUtypejÀuhxMAhyhhz]rŸh§)r }r¡(haX,Duplicate implicit target name: "procedure".hn}r¢(hp]hq]hr]hs]hv]uhbj›hz]r£hƒX,Duplicate implicit target name: "procedure".r¤…r¥}r¦(haUhbj ubahlh«ubaubh^)r§}r¨(haUhbj‡hjhŒhlj¾hn}r©(hp]UlevelKhs]hr]rªjaUsourcehŒhq]hv]UlineMLUtypejÀuhxMLhyhhz]r«h§)r¬}r­(haX/Duplicate implicit target name: "test results".hn}r®(hp]hq]hr]hs]hv]uhbj§hz]r¯hƒX/Duplicate implicit target name: "test results".r°…r±}r²(haUhbj¬ubahlh«ubaubh^)r³}r´(haUhbj—hjhŒhlj¾hn}rµ(hp]UlevelKhs]hr]r¶jœaUsourcehŒhq]hv]UlineMOUtypejÀuhxMOhyhhz]r·h§)r¸}r¹(haXeDuplicate implicit target name: "test 1. with a hybrid clock (oc+tc) between master and slave clock".hn}rº(hp]hq]hr]hs]hv]uhbj³hz]r»hƒXeDuplicate implicit target name: "test 1. with a hybrid clock (oc+tc) between master and slave clock".r¼…r½}r¾(haUhbj¸ubahlh«ubaubh^)r¿}rÀ(haUhbj«hjhŒhlj¾hn}rÁ(hp]UlevelKhs]hr]rÂj°aUsourcehŒhq]hv]UlineMTUtypejÀuhxMThyhhz]rÃh§)rÄ}rÅ(haX`Duplicate implicit target name: "test 2. without a hybrid clock between master and slave clock".hn}rÆ(hp]hq]hr]hs]hv]uhbj¿hz]rÇhƒX`Duplicate implicit target name: "test 2. without a hybrid clock between master and slave clock".rÈ…rÉ}rÊ(haUhbjÄubahlh«ubaubh^)rË}rÌ(haUhbj¿hjhŒhlj¾hn}rÍ(hp]UlevelKhs]hr]rÎjÅaUsourcehŒhq]hv]UlineMYUtypejÀuhxMYhyhhz]rÏh§)rÐ}rÑ(haX.Duplicate implicit target name: "limitations".hn}rÒ(hp]hq]hr]hs]hv]uhbjËhz]rÓhƒX.Duplicate implicit target name: "limitations".rÔ…rÕ}rÖ(haUhbjÐubahlh«ubaubeUcurrent_sourcer×NU decorationrØNUautofootnote_startrÙKUnameidsrÚ}rÛ(hjk hj+hNh j¤h Nh j3h jÏ h jˆhjdhNhNhjhjŒhj„hjhj÷hNhj hjÎhjéhjØhj²hjhjahjdhNh j° h!jƒh"jÞ h#jT h$jR h%j»h&jh'jdh(jþ h)jŸh*jJh+jÉ h,Nh-j×h.Nh/huh0j& h1j°h2j‘h3jôh4jª h5j h6j~ h7Nh8jMh9jÇh:jAh;j‚hjh?j´h@jÇ hAj0hBjÅhCNhDNhEj™ hFj`hGj»hHjjhIjK hJjhKjn hLjjhMj… hNj´hOjóhPjë hQjhRjShSjò hTjOhUjÇhVj hWjhXj5hYNuhz]rÜhhahaUU transformerrÝNU footnote_refsrÞ}rßUrefnamesrà}ráUsymbol_footnotesrâ]rãUautofootnote_refsrä]råUsymbol_footnote_refsræ]rçU citationsrè]réhyhU current_linerêNUtransform_messagesrë]rì(h^)rí}rî(haUhn}rï(hp]UlevelKhs]hr]UsourcehŒhq]hv]UlineK–UtypejÀuhz]rðh§)rñ}rò(haUhn}ró(hp]hq]hr]hs]hv]uhbjíhz]rôhƒX=Hyperlink target "plsdk-ptp-hw-mods-label" is not referenced.rõ…rö}r÷(haUhbjñubahlh«ubahlj¾ubh^)rø}rù(haUhn}rú(hp]UlevelKhs]hr]UsourcehŒhq]hv]UlineM?UtypejÀuhz]rûh§)rü}rý(haUhn}rþ(hp]hq]hr]hs]hv]uhbjøhz]rÿhƒX8Hyperlink target "plsdk-ptp-oc-label" is not referenced.r…r}r(haUhbjüubahlh«ubahlj¾ubeUreporterrNUid_startrKU autofootnotesr]rU citation_refsr}rUindirect_targetsr ]r Usettingsr (cdocutils.frontend Values r or }r(Ufootnote_backlinksrKUrecord_dependenciesrNU rfc_base_urlrUhttps://tools.ietf.org/html/rU tracebackrˆUpep_referencesrNUstrip_commentsrNU toc_backlinksrjúU language_coderUenrU datestamprNU report_levelrKU _destinationrNU halt_levelrKU strip_classesrNh€NUerror_encoding_error_handlerrUbackslashreplacerUdebugr NUembed_stylesheetr!‰Uoutput_encoding_error_handlerr"Ustrictr#U sectnum_xformr$KUdump_transformsr%NU docinfo_xformr&KUwarning_streamr'NUpep_file_url_templater(Upep-%04dr)Uexit_status_levelr*KUconfigr+NUstrict_visitorr,NUcloak_email_addressesr-ˆUtrim_footnote_reference_spacer.‰Uenvr/NUdump_pseudo_xmlr0NUexpose_internalsr1NUsectsubtitle_xformr2‰U source_linkr3NUrfc_referencesr4NUoutput_encodingr5Uutf-8r6U source_urlr7NUinput_encodingr8U utf-8-sigr9U_disable_configr:NU id_prefixr;UU tab_widthr<KUerror_encodingr=UUTF-8r>U_sourcer?hkUgettext_compactr@ˆU generatorrANUdump_internalsrBNU smart_quotesrC‰U pep_base_urlrDU https://www.python.org/dev/peps/rEUsyntax_highlightrFUlongrGUinput_encoding_error_handlerrHj#Uauto_id_prefixrIUidrJUdoctitle_xformrK‰Ustrip_elements_with_classesrLNU _config_filesrM]Ufile_insertion_enabledrNˆU raw_enabledrOKU dump_settingsrPNubUsymbol_footnote_startrQKUidsrR}rS(jK jG j¤jžjdj jjhuhhjaj jÇjÃjÞ jÚ j3j-jª j¥ j×jÒjÇ jà jò jí j5j1j‚ j~ j3hfj& j" jéjåj¸j²jj jÎjÊjSjOjœj—jˆj„jQjLjGjBj> j9 j j jÇjÂjÉ jÄ j’jj»jµj¨j¢j0j*j„j€jjjþ jù jdj`jbj\j`j[jƒj~jÏ jÊ j… j€ jMjIjjjjjÇjÃjæjàhh–j"jj+j&j jjR jM jj jéjäj“jj°j¬j#jjjýjEj@j j jœj—j°j«jÅj¿j= j7 jŒjˆj jjAj=jj‡jj jn jj jã jÝ jjjfjjjtjnj²j®jdj_j÷jójjü j»j¶jT jP jŸjšjÅjÁj0j,jØjÔj~ jy j´jµjôjðj‚j~jOjKjñ jë j° j¬ j™ j• jjjfj‘jjÒjÍjk jg jójîjë jæ j´hdjJjFjˆj‚uUsubstitution_namesrT}rUhlhyhn}rV(hp]hs]hr]Usourcehkhq]hv]uU footnotesrW]rXUrefidsrY}rZ(j´]r[j¯aja]r\jauub.