Many instructions in the C6000 instruction set across the various available target processors support a 64-bit register operand that can be specified as a register pair.
A register pair should be specified on the A side or the B side, depending on which functional unit an instruction is to be executed on, and whether a cross functional unit data path is utilized by the instruction. You cannot mix A-side and B-side registers in the same register pair operand.
The syntax for a register pair is as follows where (n%2 == 0):
| Rn+1:Rn |
The legal register pairs are:
| A1:A0 | B1:B0 |
| A3:A2 | B3:B2 |
| A5:A4 | B5:B4 |
| A7:A6 | B7:B6 |
| A9:A8 | B9:B8 |
| A11:A10 | B11:B10 |
| A13:A12 | B13:B12 |
| A15:A14 | B15:B14 |
| A17:A16 | B17:B16 |
| A19:A18 | B19:B18 |
| A21:A20 | B21:B20 |
| A23:A22 | B23:B22 |
| A25:A24 | B25:B24 |
| A27:A26 | B27:B26 |
| A29:A30 | B29:B30 |
| A31:A32 | B31:B32 |
Here is an example of an ADD instruction that uses a register pair operand:
ADD.L1 A5:A4,A1,A3:A2
For details on using register pairs in linear assembly, see the TMS320C6000 Optimizing Compiler User's Guide.
For more information on functional units, including which assembly instructions require which functional type, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide, TMS320C66x CPU and Instruction Set Reference Guide, or TMS320C6740 DSP CPU and Instruction Set Reference Guide.