| Benchmark | Cycles | (1) |
| Interrupt Latency | 129 | (2) |
| Hwi_restore() | 1 | |
| Hwi_disable() | 2 | |
| Hwi dispatcher prolog | 103 | |
| Hwi dispatcher epilog | 238 | |
| Hwi dispatcher | 335 | |
| Hardware Interrupt to Blocked Task | 541 | |
| Hardware Interrupt to Software Interrupt | 375 | |
| Swi_enable() | 79 | |
| Swi_disable() | 13 | |
| Post Software Interrupt Again | 36 | |
| Post Software Interrupt without Context Switch | 101 | |
| Post Software Interrupt with Context Switch | 199 | |
| Create a New Task without Context Switch | 2031 | |
| Set a Task Priority without a Context Switch | 167 | |
| Task_yield() | 207 | |
| Post Semaphore, No Waiting Task | 51 | |
| Post Semaphore No Task Switch | 195 | |
| Post Semaphore with Task Switch | 257 | |
| Pend on Semaphore, No Context Switch | 73 | |
| Pend on Semaphore with Task Switch | 278 | |
| Clock_getTicks() | 8 |
(1) The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: "--endian=little -mv7M4 --float_support=vfplib --abi=eabi -q -ms --opt_for_speed=2 --program_level_compile -o3".
Timings were obtained using the CC3200 Launchpad board running at 80MHz.
(2) The M4 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi CDOCs for details. Due to RTC Timer register access times, when the SYS/BIOS Clock module uses the CC3200 RTC timer as its tick source, interrupt latencies can be as high as 200 microseconds. These unusually high latencies should only occur once every 36 hours or so. See the CDOCs for the ti.sysbios.family.arm.cc32xx.Timer module for more details.