TI Cortex-M4 with hard FP Timing Benchmarks

ti.platforms.tiva:TM4C123GH6PM:1 (compiler version: 5.2.4)

Benchmark Cycles (1)
Interrupt Latency 135 (2)
Hwi_restore() 0
Hwi_disable() 2
Hwi dispatcher prolog 113
Hwi dispatcher epilog 208
Hwi dispatcher 313
Hardware Interrupt to Blocked Task 488
Hardware Interrupt to Software Interrupt 327
Swi_enable() 58
Swi_disable() 8
Post Software Interrupt Again 27
Post Software Interrupt without Context Switch 82
Post Software Interrupt with Context Switch 156
Create a New Task without Context Switch 1589
Set a Task Priority without a Context Switch 133
Task_yield() 195
Post Semaphore, No Waiting Task 42
Post Semaphore No Task Switch 151
Post Semaphore with Task Switch 236
Pend on Semaphore, No Context Switch 58
Pend on Semaphore with Task Switch 248
Clock_getTicks() 7

(1) The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: "--endian=little -mv7M4 --abi=eabi --float_support=fpv4spd16 -ms --opt_for_speed=2 --program_level_compile -o3".

Timings were obtained using the Tiva Launchpad TM4C123GH6PM board running at 40MHz.

(2) The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.