| Benchmark | Cycles | (1) |
| Interrupt Latency | 152 | (2) |
| Hwi_restore() | 1 | |
| Hwi_disable() | 4 | |
| Hwi dispatcher prolog | 116 | |
| Hwi dispatcher epilog | 212 | |
| Hwi dispatcher | 318 | |
| Hardware Interrupt to Blocked Task | 617 | |
| Hardware Interrupt to Software Interrupt | 370 | |
| Swi_enable() | 65 | |
| Swi_disable() | 12 | |
| Post Software Interrupt Again | 30 | |
| Post Software Interrupt without Context Switch | 82 | |
| Post Software Interrupt with Context Switch | 183 | |
| Create a New Task without Context Switch | 2148 | |
| Set a Task Priority without a Context Switch | 158 | |
| Task_yield() | 255 | |
| Post Semaphore, No Waiting Task | 47 | |
| Post Semaphore No Task Switch | 244 | |
| Post Semaphore with Task Switch | 347 | |
| Pend on Semaphore, No Context Switch | 55 | |
| Pend on Semaphore with Task Switch | 361 | |
| Clock_getTicks() | 8 |
(1) The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings:
"-mcpu=cortex-m3 -mthumb -mabi=aapcs -O3 -Wunused -Wunknown-pragmas -ffunction-sections -fdata-sections -Dti_sysbios_Build_useHwiMacros -Dfar= -D__DYNAMIC_REENT__".
Timings were obtained using the Tiva Launchpad TM4C123GH6PM board running at 40MHz.
(2) The M3 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.