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16
17 import xdc.runtime.Error;
18 import xdc.runtime.knl.ICacheSupport;
19
20 /*!
21 * ======== Cache ========
22 * Cache Services
23 *
24 * The Cache module provide APIs to allow applications to maintain cache
25 * coherency.
26 *
27 * This module will use an OS specific delegate (back-end) to manipulate the
28 * cache.
29 * This module has a module wide config parameter {@link #Proxy} which needs to
30 * be bound to an OS specific delegate before this module can be used.
31 *
32 * Here is an example showing how the proxy is bound to an BIOS 6.x specific
33 * delegate.
34 *
35 * @p(code)
36 * var Cache = xdc.useModule('xdc.runtime.knl.Cache');
37 * Cache.Proxy = xdc.useModule('ti.sysbios.xdcruntime.CacheSupport');
38 * @p
39 *
40 * Typically the package containing the delegates have a Settings module that
41 * will bind all {@link xdc.runtime.knl} proxies. The following
42 * example sets up all the xdc.runtime.knl proxies.
43 *
44 * @p(code)
45 * xdc.useModule("ti.sysbios.xdcruntime.Settings");
46 * @p
47 */
48 @DirectCall
49 @RomConsts
50
51 module Cache
52 {
53 /*!
54 * ======== Proxy ========
55 * ICacheSupport proxy
56 *
57 * Cache will use this proxy to access the cache hardware using
58 * OS specific APIs.
59 */
60 proxy Proxy inherits ICacheSupport;
61
62 /*!
63 * ======== inv ========
64 * Invalidate range of memory for all cache(s)
65 *
66 * Invalidate the range of memory within the specified starting
67 * address and byte count. The range of addresses operated on
68 * gets quantized to whole cache lines in each cache. All lines
69 * in range are invalidated for all cache types.
70 *
71 * @param(blockPtr) start address of range to be invalidated
72 * @param(byteCnt) number of bytes to be invalidated
73 * @param(wait) wait until the operation is completed
74 * @param(eb) error block
75 * @a(returns) true for success; false for error.
76 */
77 Bool inv(Ptr blockPtr, SizeT byteCnt, Bool wait, Error.Block *eb);
78
79 /*!
80 * ======== wb ========
81 * Writes back a range of memory from all cache(s)
82 *
83 * Writes back the range of memory within the specified starting
84 * address and byte count. The range of addresses operated on
85 * gets quantized to whole cache lines in each cache. All lines
86 * within the range are left valid in all caches and the data
87 * within the range will be written back to the source memory.
88 *
89 * @param(blockPtr) start address of range to be invalidated
90 * @param(byteCnt) number of bytes to be invalidated
91 * @param(wait) wait until the operation is completed
92 * @param(eb) error block
93 * @a(returns) true for success; false for error.
94 */
95 Bool wb(Ptr blockPtr, SizeT byteCnt, Bool wait, Error.Block *eb);
96
97 /*!
98 * ======== wbInv ========
99 * Write back and invalidate range of memory.
100 *
101 * Writes back and invalidates the range of memory within the
102 * specified starting address and byte count. The range of
103 * addresses operated on gets quantized to whole cache lines in
104 * each cache. All lines within the range are written back to the
105 * source memory and then invalidated for all cache types.
106 *
107 * @param(blockPtr) start address of range to be invalidated
108 * @param(byteCnt) number of bytes to be invalidated
109 * @param(wait) wait until the operation is completed
110 * @param(eb) error block
111 * @a(returns) true for success; false for error.
112 */
113 Bool wbInv(Ptr blockPtr, SizeT byteCnt, Bool wait, Error.Block *eb);
114
115 /*!
116 * ======== wait ========
117 * Wait for a previous cache operation to complete
118 *
119 * Wait for the cache wb/wbInv/inv operation to complete. A cache
120 * operation is not truly complete until it has worked its way
121 * through all buffering and all memory writes have landed in the
122 * source memory.
123 *
124 * @param(eb) error block
125 * @a(returns) true for success; false for error.
126 */
127 Bool wait(Error.Block *eb);
128 }
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