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22
23 metaonly interface IMSP430F55xx inherits ti.catalog.msp430.IMSP430
24 {
25
26 instance:
27
28 override config string cpuCore = "MSP430X";
29 override config string isa = "430|430X";
30
31 config ti.catalog.msp430.peripherals.special_function.IE1.Instance
32 interruptEnableRegister1;
33 config ti.catalog.msp430.peripherals.timer.Timer0_A5.Instance TA0;
34 config ti.catalog.msp430.peripherals.timer.Timer1_A3.Instance TA1;
35 config ti.catalog.msp430.peripherals.timer.Timer2_A3.Instance TA2;
36 config ti.catalog.msp430.peripherals.timer.Timer0_B7.Instance TB0;
37 config ti.catalog.msp430.peripherals.watchdog.WDTplus.Instance wdtPlus;
38 config ti.catalog.msp430.peripherals.interrupt.Interrupt_Controller.Instance
39 interruptController;
40
41 /*!
42 * ======== commonMap ========
43 * Memory map elements shared by all MSP430F55xx devices
44 */
45 config xdc.platform.IPlatform.Memory commonMap[string] = [
46
47 ["PERIPHERALS", {
48 comment: "Memory mapped peripherals",
49 name: "PERIPHERALS",
50 base: 0x0,
51 len: 0x1000,
52 space: "io",
53 access: "RW"
54 }],
55
56 ["BSL", {
57 comment: "Bootstrap loader (flash)",
58 name: "BSL",
59 base: 0x1000,
60 len: 0x800,
61 space: "code",
62 access: "RW"
63 }],
64
65 ["INFOD", {
66 comment: "Information Memory D (flash)",
67 name: "INFOD",
68 base: 0x1800,
69 len: 0x80,
70 space: "data",
71 access: "RW"
72 }],
73
74 ["INFOC", {
75 comment: "Information Memory C (flash)",
76 name: "INFOC",
77 base: 0x1880,
78 len: 0x80,
79 space: "data",
80 access: "RW"
81 }],
82
83 ["INFOB", {
84 comment: "Information Memory B (flash)",
85 name: "INFOB",
86 base: 0x1900,
87 len: 0x80,
88 space: "data",
89 access: "RW"
90 }],
91
92 ["INFOA", {
93 comment: "Information Memory A (flash)",
94 name: "INFOA",
95 base: 0x1980,
96 len: 0x80,
97 space: "data",
98 access: "RW"
99 }],
100
101 ["INT00", {
102 comment: "Reserved Vector",
103 name: "INT00",
104 base: 0xFF80,
105 len: 0x2,
106 space: "data"
107 }],
108
109 ["INT01", {
110 comment: "Reserved Vector",
111 name: "INT01",
112 base: 0xFF82,
113 len: 0x2,
114 space: "data"
115 }],
116
117 ["INT02", {
118 comment: "Reserved Vector",
119 name: "INT02",
120 base: 0xFF84,
121 len: 0x2,
122 space: "data"
123 }],
124
125 ["INT03", {
126 comment: "Reserved Vector",
127 name: "INT03",
128 base: 0xFF86,
129 len: 0x2,
130 space: "data"
131 }],
132
133 ["INT04", {
134 comment: "Reserved Vector",
135 name: "INT04",
136 base: 0xFF88,
137 len: 0x2,
138 space: "data"
139 }],
140
141 ["INT05", {
142 comment: "Reserved Vector",
143 name: "INT05",
144 base: 0xFF8A,
145 len: 0x2,
146 space: "data"
147 }],
148
149 ["INT06", {
150 comment: "Reserved Vector",
151 name: "INT06",
152 base: 0xFF8C,
153 len: 0x2,
154 space: "data"
155 }],
156
157 ["INT07", {
158 comment: "Reserved Vector",
159 name: "INT07",
160 base: 0xFF8E,
161 len: 0x2,
162 space: "data"
163 }],
164
165 ["INT08", {
166 comment: "Reserved Vector",
167 name: "INT08",
168 base: 0xFF90,
169 len: 0x2,
170 space: "data"
171 }],
172
173 ["INT09", {
174 comment: "Reserved Vector",
175 name: "INT09",
176 base: 0xFF92,
177 len: 0x2,
178 space: "data"
179 }],
180
181 ["INT10", {
182 comment: "Reserved Vector",
183 name: "INT10",
184 base: 0xFF94,
185 len: 0x2,
186 space: "data"
187 }],
188
189 ["INT11", {
190 comment: "Reserved Vector",
191 name: "INT11",
192 base: 0xFF96,
193 len: 0x2,
194 space: "data"
195 }],
196
197 ["INT12", {
198 comment: "Reserved Vector",
199 name: "INT12",
200 base: 0xFF98,
201 len: 0x2,
202 space: "data"
203 }],
204
205 ["INT13", {
206 comment: "Reserved Vector",
207 name: "INT13",
208 base: 0xFF9A,
209 len: 0x2,
210 space: "data"
211 }],
212
213 ["INT14", {
214 comment: "Reserved Vector",
215 name: "INT14",
216 base: 0xFF9C,
217 len: 0x2,
218 space: "data"
219 }],
220
221 ["INT15", {
222 comment: "Reserved Vector",
223 name: "INT15",
224 base: 0xFF9E,
225 len: 0x2,
226 space: "data"
227 }],
228
229 ["INT16", {
230 comment: "Reserved Vector",
231 name: "INT16",
232 base: 0xFFA0,
233 len: 0x2,
234 space: "data"
235 }],
236
237 ["INT17", {
238 comment: "Reserved Vector",
239 name: "INT17",
240 base: 0xFFA2,
241 len: 0x2,
242 space: "data"
243 }],
244
245 ["INT18", {
246 comment: "Reserved Vector",
247 name: "INT18",
248 base: 0xFFA4,
249 len: 0x2,
250 space: "data"
251 }],
252
253 ["INT19", {
254 comment: "Reserved Vector",
255 name: "INT19",
256 base: 0xFFA6,
257 len: 0x2,
258 space: "data"
259 }],
260
261 ["INT20", {
262 comment: "Reserved Vector",
263 name: "INT20",
264 base: 0xFFA8,
265 len: 0x2,
266 space: "data"
267 }],
268
269 ["INT21", {
270 comment: "Reserved Vector",
271 name: "INT21",
272 base: 0xFFAA,
273 len: 0x2,
274 space: "data"
275 }],
276
277 ["INT22", {
278 comment: "Reserved Vector",
279 name: "INT22",
280 base: 0xFFAC,
281 len: 0x2,
282 space: "data"
283 }],
284
285 ["INT23", {
286 comment: "Reserved Vector",
287 name: "INT23",
288 base: 0xFFAE,
289 len: 0x2,
290 space: "data"
291 }],
292
293 ["INT24", {
294 comment: "Reserved Vector",
295 name: "INT24",
296 base: 0xFFB0,
297 len: 0x2,
298 space: "data"
299 }],
300
301 ["INT25", {
302 comment: "Reserved Vector",
303 name: "INT25",
304 base: 0xFFB2,
305 len: 0x2,
306 space: "data"
307 }],
308
309 ["INT26", {
310 comment: "Reserved Vector",
311 name: "INT26",
312 base: 0xFFB4,
313 len: 0x2,
314 space: "data"
315 }],
316
317 ["INT27", {
318 comment: "Reserved Vector",
319 name: "INT27",
320 base: 0xFFB6,
321 len: 0x2,
322 space: "data"
323 }],
324
325 ["INT28", {
326 comment: "Reserved Vector",
327 name: "INT28",
328 base: 0xFFB8,
329 len: 0x2,
330 space: "data"
331 }],
332
333 ["INT29", {
334 comment: "Reserved Vector",
335 name: "INT29",
336 base: 0xFFBA,
337 len: 0x2,
338 space: "data"
339 }],
340
341 ["INT30", {
342 comment: "Reserved Vector",
343 name: "INT30",
344 base: 0xFFBC,
345 len: 0x2,
346 space: "data"
347 }],
348
349 ["INT31", {
350 comment: "Reserved Vector",
351 name: "INT31",
352 base: 0xFFBE,
353 len: 0x2,
354 space: "data"
355 }],
356
357 ["INT32", {
358 comment: "Reserved Vector",
359 name: "INT32",
360 base: 0xFFC0,
361 len: 0x2,
362 space: "data"
363 }],
364
365 ["INT33", {
366 comment: "Reserved Vector",
367 name: "INT33",
368 base: 0xFFC2,
369 len: 0x2,
370 space: "data"
371 }],
372
373 ["INT34", {
374 comment: "Reserved Vector",
375 name: "INT34",
376 base: 0xFFC4,
377 len: 0x2,
378 space: "data"
379 }],
380
381 ["INT35", {
382 comment: "Reserved Vector",
383 name: "INT35",
384 base: 0xFFC6,
385 len: 0x2,
386 space: "data"
387 }],
388
389 ["INT36", {
390 comment: "Reserved Vector",
391 name: "INT36",
392 base: 0xFFC8,
393 len: 0x2,
394 space: "data"
395 }],
396
397 ["INT37", {
398 comment: "Reserved Vector",
399 name: "INT37",
400 base: 0xFFCA,
401 len: 0x2,
402 space: "data"
403 }],
404
405 ["INT38", {
406 comment: "Reserved Vector",
407 name: "INT38",
408 base: 0xFFCC,
409 len: 0x2,
410 space: "data"
411 }],
412
413 ["INT39", {
414 comment: "Reserved Vector",
415 name: "INT39",
416 base: 0xFFCE,
417 len: 0x2,
418 space: "data"
419 }],
420
421 ["INT40", {
422 comment: "Reserved Vector",
423 name: "INT40",
424 base: 0xFFD0,
425 len: 0x2,
426 space: "data"
427 }],
428
429 ["INT41", {
430 comment: "RTC_A Vector",
431 name: "INT41",
432 base: 0xFFD2,
433 len: 0x2,
434 space: "data"
435 }],
436
437 ["INT42", {
438 comment: "I/O Port P2 Vector",
439 name: "INT42",
440 base: 0xFFD4,
441 len: 0x2,
442 space: "data"
443 }],
444
445 ["INT43", {
446 comment: "TA2 CCR1-CCR2 Vector",
447 name: "INT43",
448 base: 0xFFD6,
449 len: 0x2,
450 space: "data"
451 }],
452
453 ["INT44", {
454 comment: "TA2 CCR0 Vector",
455 name: "INT44",
456 base: 0xFFD8,
457 len: 0x2,
458 space: "data"
459 }],
460
461 ["INT45", {
462 comment: "USCI_B1 Receive/Transmit Vector",
463 name: "INT45",
464 base: 0xFFDA,
465 len: 0x2,
466 space: "data"
467 }],
468
469 ["INT46", {
470 comment: "USCI_A1 Receive/Transmit Vector",
471 name: "INT46",
472 base: 0xFFDC,
473 len: 0x2,
474 space: "data"
475 }],
476
477 ["INT47", {
478 comment: "I/O Port P1 Vector",
479 name: "INT47",
480 base: 0xFFDE,
481 len: 0x2,
482 space: "data"
483 }],
484
485 ["INT48", {
486 comment: "TA1 CCR1-CCR2 Vector",
487 name: "INT48",
488 base: 0xFFE0,
489 len: 0x2,
490 space: "data"
491 }],
492
493 ["INT49", {
494 comment: "TA1 CCR0 Vector",
495 name: "INT49",
496 base: 0xFFE2,
497 len: 0x2,
498 space: "data"
499 }],
500
501 ["INT50", {
502 comment: "DMA Vector",
503 name: "INT50",
504 base: 0xFFE4,
505 len: 0x2,
506 space: "data"
507 }],
508
509 ["INT51", {
510 comment: "USB_UBM Vector",
511 name: "INT51",
512 base: 0xFFE6,
513 len: 0x2,
514 space: "data"
515 }],
516
517 ["INT52", {
518 comment: "TA0 CCR1-CCR4 Vector",
519 name: "INT52",
520 base: 0xFFE8,
521 len: 0x2,
522 space: "data"
523 }],
524
525 ["INT53", {
526 comment: "TA0 CCR0 Vector",
527 name: "INT53",
528 base: 0xFFEA,
529 len: 0x2,
530 space: "data"
531 }],
532
533 ["INT54", {
534 comment: "ADC12_A Vector",
535 name: "INT54",
536 base: 0xFFEC,
537 len: 0x2,
538 space: "data"
539 }],
540
541 ["INT55", {
542 comment: "USCI_B0 Receive/Transmit Vector",
543 name: "INT55",
544 base: 0xFFEE,
545 len: 0x2,
546 space: "data"
547 }],
548
549 ["INT56", {
550 comment: "USCI_A0 Receive/Transmit Vector",
551 name: "INT56",
552 base: 0xFFF0,
553 len: 0x2,
554 space: "data"
555 }],
556
557 ["INT57", {
558 comment: "Watchdog Timer_A Interval Timer Mode Vector",
559 name: "INT57",
560 base: 0xFFF2,
561 len: 0x2,
562 space: "data"
563 }],
564
565 ["INT58", {
566 comment: "TB0 CCR1-CCR6 Vector",
567 name: "INT58",
568 base: 0xFFF4,
569 len: 0x2,
570 space: "data"
571 }],
572
573 ["INT59", {
574 comment: "TB0 CCR0 Vector",
575 name: "INT59",
576 base: 0xFFF6,
577 len: 0x2,
578 space: "data"
579 }],
580
581 ["INT60", {
582 comment: "Comp_B Vector",
583 name: "INT60",
584 base: 0xFFF8,
585 len: 0x2,
586 space: "data"
587 }],
588
589 ["INT61", {
590 comment: "User NMI Vector",
591 name: "INT61",
592 base: 0xFFFA,
593 len: 0x2,
594 space: "data"
595 }],
596
597 ["INT62", {
598 comment: "System NMI Vector",
599 name: "INT62",
600 base: 0xFFFC,
601 len: 0x2,
602 space: "data"
603 }],
604
605 ["RESET", {
606 comment: "Reset Vector",
607 name: "RESET",
608 base: 0xFFFE,
609 len: 0x2,
610 space: "data"
611 }],
612 ];
613 }
614 615 616
617