1    /*
     2     *  Copyright (c) 2015 by Texas Instruments and others.
     3     *  All rights reserved. This program and the accompanying materials
     4     *  are made available under the terms of the Eclipse Public License v1.0
     5     *  which accompanies this distribution, and is available at
     6     *  http://www.eclipse.org/legal/epl-v10.html
     7     *
     8     *  Contributors:
     9     *      Texas Instruments - initial implementation
    10     *
    11     * */
    12    
    13    /*
    14     *  ======== DRA7XX.xdc ========
    15     *
    16     */
    17    
    18    /*!
    19     *  ======== DRA7XX ========
    20     *  The DRA7XX device data sheet module.
    21     *
    22     *  This module implements the xdc.platform.ICpuDataSheet interface and is
    23     *  used by platforms to obtain "data sheet" information about this device.
    24     *
    25     */
    26    metaonly module DRA7XX inherits ti.catalog.ICpuDataSheet
    27    {
    28    instance:
    29        config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp0;
    30    
    31        override config string cpuCore           = "CM4";
    32        override config string isa               = "v7M4";
    33        override config string cpuCoreRevision   = "1.0";
    34        override config int    minProgUnitSize   = 1;
    35        override config int    minDataUnitSize   = 1;
    36        override config int    dataWordSize      = 4;
    37    
    38        /*!
    39         *  ======== memMap ========
    40         *  The memory map returned be getMemoryMap().
    41         */
    42        config xdc.platform.IPlatform.Memory memMap[string] = [
    43    
    44            /*
    45             * AMMU mapped L2 ROM virtual address
    46             * Physical address is 0x55000000
    47             */
    48            ["L2_ROM", {
    49                name: "L2_ROM",
    50                base: 0x00000000,
    51                len:  0x00004000
    52            }],
    53    
    54            /*
    55             * AMMU mapped L2 RAM virtual address
    56             * Physical address is 0x55020000
    57             */
    58            ["L2_RAM", {
    59                name: "L2_RAM",
    60                base: 0x20000000,
    61                len:  0x00010000
    62            }],
    63    
    64            /*
    65             * On-chip RAM memory 
    66             */
    67            ["OCMC_RAM1", {
    68                comment:    "OCMC (On-chip RAM) Bank 1 (512KB)",
    69                name: "OCMC_RAM1",
    70                base: 0x40300000,
    71                len:  0x00080000
    72            }],
    73    
    74            /*
    75             * On-chip RAM memory 
    76             */
    77            ["OCMC_RAM2", {
    78                comment:    "OCMC (On-chip RAM) Bank 2 (1MB)",
    79                name: "OCMC_RAM2",
    80                base: 0x40400000,
    81                len:  0x00100000
    82            }],
    83    
    84            /*
    85             * On-chip RAM memory 
    86             */
    87            ["OCMC_RAM3", {
    88                comment:    "OCMC (On-chip RAM) Bank 3 (1MB)",
    89                name: "OCMC_RAM3",
    90                base: 0x40500000,
    91                len:  0x00100000
    92            }]
    93        ];
    94    };
    95    /*
    96     *  @(#) ti.catalog.arm.cortexm4; 1, 0, 0,105; 1-21-2015 20:14:19; /db/ztree/library/trees/platform/platform-o69x/src/
    97     */
    98