1 2 3 4 5 6 7 8 9 10 11
12
13 14 15 16
17
18 metaonly module DRA7XX inherits ti.catalog.ICpuDataSheet
19 {
20 instance:
21 config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp0;
22
23 override config string cpuCore = "v7A15";
24 override config string isa = "v7A15";
25 override config string cpuCoreRevision = "1.0";
26 override config int minProgUnitSize = 1;
27 override config int minDataUnitSize = 1;
28 override config int dataWordSize = 4;
29
30 /*!
31 * ======== memMap ========
32 * The memory map returned be getMemoryMap().
33 */
34 config xdc.platform.IPlatform.Memory memMap[string] = [
35 ["SRAM", {
36 comment: "On-Chip SRAM",
37 name: "SRAM",
38 base: 0x402F0000,
39 len: 0x00010000,
40 space: "code/data",
41 access: "RWX"
42 }],
43
44 45 46
47 ["OCMC_RAM1", {
48 comment: "OCMC (On-chip RAM) Bank 1 (512KB)",
49 name: "OCMC_RAM1",
50 base: 0x40300000,
51 len: 0x00080000
52 }],
53
54 55 56
57 ["OCMC_RAM2", {
58 comment: "OCMC (On-chip RAM) Bank 2 (1MB)",
59 name: "OCMC_RAM2",
60 base: 0x40400000,
61 len: 0x00100000
62 }],
63
64 65 66
67 ["OCMC_RAM3", {
68 comment: "OCMC (On-chip RAM) Bank 3 (1MB)",
69 name: "OCMC_RAM3",
70 base: 0x40500000,
71 len: 0x00100000
72 }]
73 ];
74 }
75 76 77
78