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9
10 11 12 13
14 package ti.catalog.c6000;
15
16 /*!
17 * ======== ITMS320C6452 ========
18 * The interface for 6452 and similar devices' data sheet module.
19 *
20 * This module implements the ICpuDataSheet interface and is
21 * used by platforms to obtain "data sheet" information about this device.
22 */
23 metaonly interface ITMS320C6452 inherits ti.catalog.ICpuDataSheet
24 {
25
26 config long cacheSizeL1[string] = [
27 ["0k", 0x0000],
28 ["4k", 0x1000],
29 ["8k", 0x2000],
30 ["16k", 0x4000],
31 ["32k", 0x8000],
32 ];
33
34 config long cacheSizeL2[string] = [
35 ["0k", 0x00000],
36 ["32k", 0x08000],
37 ["64k", 0x10000],
38 ["128k", 0x20000],
39 ["256k", 0x40000]
40 ];
41
42 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
43 ['l1PMode',{desc:"L1P Cache",
44 map : [["0k",0x0000],
45 ["4k",0x1000],
46 ["8k",0x2000],
47 ["16k",0x4000],
48 ["32k",0x8000]],
49 defaultValue: "0k",
50 memorySection: "L1PSRAM"}],
51
52 ['l1DMode',{desc:"L1D Cache",
53 map : [["0k",0x0000],
54 ["4k",0x1000],
55 ["8k",0x2000],
56 ["16k",0x4000],
57 ["32k",0x8000]],
58 defaultValue: "0k",
59 memorySection: "L1DSRAM"}],
60
61 ['l2Mode',{desc:"L2 Cache",
62 map : [["0k",0x0000],
63 ["32k",0x8000],
64 ["64k",0x10000],
65 ["128k",0x20000],
66 ["256k",0x40000]],
67 defaultValue: "0k",
68 memorySection: "IRAM"}],
69 ];
70
71 instance:
72
73 override config string cpuCore = "64x+";
74 override config string isa = "64P";
75 override config string cpuCoreRevision = "1.0";
76
77 override config int minProgUnitSize = 1;
78 override config int minDataUnitSize = 1;
79 override config int dataWordSize = 4;
80
81 /*!
82 * ======== memMap ========
83 * The default memory map for this device
84 */
85 config xdc.platform.IPlatform.Memory memMap[string] = [
86 ["IRAM", {
87 comment: "Internal 1408KB L2 RAM/CACHE",
88 name: "IRAM",
89 base: 0xA00000,
90 len: 0x160000,
91 space: "code/data",
92 access: "RWX"
93 }],
94
95 ["L1PSRAM", {
96 comment: "Internal 32KB RAM/CACHE L1 program memory",
97 name: "L1PSRAM",
98 base: 0xE00000,
99 len: 0x008000,
100 space: "code",
101 access: "RWX"
102 }],
103
104 ["L1DSRAM", {
105 comment: "Internal 32KB RAM/CACHE L1 data memory",
106 name: "L1DSRAM",
107 base: 0xF00000,
108 len: 0x008000,
109 space: "data",
110 access: "RW"
111 }],
112
113 ];
114 };
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118