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15 /*!
16 * ======== ITMS320CTCI648x ========
17 * An interface implemented by TCI6487 and TCI6488 devices
18 *
19 * This interface is defined to factor common data about TCI6487 and TCI6488
20 * devices into a single place; they are all the same from the configuration
21 * point of view.
22 */
23 metaonly interface ITMS320CTCI648x inherits ti.catalog.ICpuDataSheet
24 {
25
26 config long cacheSizeL1[string] = [
27 ["0k", 0x0000],
28 ["4k", 0x1000],
29 ["8k", 0x2000],
30 ["16k", 0x4000],
31 ["32k", 0x8000],
32 ];
33
34 config long cacheSizeL2[string] = [
35 ["0k", 0x00000],
36 ["32k", 0x08000],
37 ["64k", 0x10000],
38 ["128k", 0x20000],
39 ["256k", 0x40000]
40 ];
41
42 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
43 ['l1PMode',{desc:"L1P Cache",
44 map : [["0k",0x0000],
45 ["4k",0x1000],
46 ["8k",0x2000],
47 ["16k",0x4000],
48 ["32k",0x8000]],
49 defaultValue: "0k",
50 memorySection: "L1PSRAM"}],
51
52 ['l1DMode',{desc:"L1D Cache",
53 map : [["0k",0x0000],
54 ["4k",0x1000],
55 ["8k",0x2000],
56 ["16k",0x4000],
57 ["32k",0x8000]],
58 defaultValue: "0k",
59 memorySection: "L1DSRAM"}],
60
61 ['l2Mode',{desc:"L2 Cache",
62 map : [["0k",0x0000],
63 ["32k",0x8000],
64 ["64k",0x10000],
65 ["128k",0x20000],
66 ["256k",0x40000]],
67 defaultValue: "0k",
68 memorySection: "L2RAM"}]
69
70 ];
71
72 config xdc.platform.IPlatform.Memory memBlock[string] = [
73 ["ASYMGEM0L2RAM", {
74 comment: "1536K L2 RAM/CACHE memory",
75 name: "L2RAM",
76 base: 0x00800000,
77 len: 0x00180000,
78 space: "code/data",
79 access: "RWX"
80 }],
81
82 ["ASYMGEM1L2RAM", {
83 comment: "1024K L2 RAM/CACHE memory",
84 name: "L2RAM",
85 base: 0x00800000,
86 len: 0x00100000,
87 space: "code/data",
88 access: "RWX"
89 }],
90
91 ["ASYMGEM2L2RAM", {
92 comment: "512K L2 RAM/CACHE memory",
93 name: "L2RAM",
94 base: 0x00800000,
95 len: 0x00080000,
96 space: "code/data",
97 access: "RWX"
98 }],
99
100 ["SYMGEML2RAM", {
101 comment: "1024K L2 RAM/CACHE memory",
102 name: "L2RAM",
103 base: 0x00800000,
104 len: 0x00100000,
105 space: "code/data",
106 access: "RWX"
107 }],
108
109 ];
110
111 instance:
112
113 override config string cpuCore = "64x+";
114 override config string isa = "64P";
115 override config string cpuCoreRevision = "1.0";
116
117 override config int minProgUnitSize = 1;
118 override config int minDataUnitSize = 1;
119 override config int dataWordSize = 4;
120
121 /*!
122 * ======== memMap ========
123 * The default memory map for this device
124 */
125 config xdc.platform.IPlatform.Memory memMap[string] = [
126
127 ["L1PSRAM", {
128 comment: "Internal 32KB RAM/CACHE L1 program memory",
129 name: "L1PSRAM",
130 base: 0xE00000,
131 len: 0x008000,
132 space: "code",
133 access: "RWX"
134 }],
135
136 ["L1DSRAM", {
137 comment: "Internal 32KB RAM/CACHE L1 data memory",
138 name: "L1DSRAM",
139 base: 0xF00000,
140 len: 0x008000,
141 space: "data",
142 access: "RW"
143 }],
144 ];
145
146 };
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